2 * Copyright (c) 2017 BayLibre, SAS
3 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/of_address.h>
9 #include <linux/platform_device.h>
10 #include <linux/pm_domain.h>
11 #include <linux/bitfield.h>
12 #include <linux/regmap.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/of_device.h>
15 #include <linux/reset.h>
16 #include <linux/clk.h>
17 #include <linux/module.h>
21 #define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2)
23 #define GEN_PWR_VPU_HDMI BIT(8)
24 #define GEN_PWR_VPU_HDMI_ISO BIT(9)
28 #define HHI_MEM_PD_REG0 (0x40 << 2)
29 #define HHI_VPU_MEM_PD_REG0 (0x41 << 2)
30 #define HHI_VPU_MEM_PD_REG1 (0x42 << 2)
31 #define HHI_VPU_MEM_PD_REG2 (0x4d << 2)
33 struct meson_gx_pwrc_vpu {
34 struct generic_pm_domain genpd;
35 struct regmap *regmap_ao;
36 struct regmap *regmap_hhi;
37 struct reset_control *rstc;
43 struct meson_gx_pwrc_vpu *genpd_to_pd(struct generic_pm_domain *d)
45 return container_of(d, struct meson_gx_pwrc_vpu, genpd);
48 static int meson_gx_pwrc_vpu_power_off(struct generic_pm_domain *genpd)
50 struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
53 regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
54 GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO);
57 /* Power Down Memories */
58 for (i = 0; i < 32; i += 2) {
59 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
63 for (i = 0; i < 32; i += 2) {
64 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
68 for (i = 8; i < 16; i++) {
69 regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
75 regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
76 GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI);
80 clk_disable_unprepare(pd->vpu_clk);
81 clk_disable_unprepare(pd->vapb_clk);
86 static int meson_g12a_pwrc_vpu_power_off(struct generic_pm_domain *genpd)
88 struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
91 regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
92 GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO);
95 /* Power Down Memories */
96 for (i = 0; i < 32; i += 2) {
97 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
101 for (i = 0; i < 32; i += 2) {
102 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
106 for (i = 0; i < 32; i += 2) {
107 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG2,
111 for (i = 8; i < 16; i++) {
112 regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
118 regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
119 GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI);
123 clk_disable_unprepare(pd->vpu_clk);
124 clk_disable_unprepare(pd->vapb_clk);
129 static int meson_gx_pwrc_vpu_setup_clk(struct meson_gx_pwrc_vpu *pd)
133 ret = clk_prepare_enable(pd->vpu_clk);
137 ret = clk_prepare_enable(pd->vapb_clk);
139 clk_disable_unprepare(pd->vpu_clk);
144 static int meson_gx_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
146 struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
150 regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
151 GEN_PWR_VPU_HDMI, 0);
154 /* Power Up Memories */
155 for (i = 0; i < 32; i += 2) {
156 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
161 for (i = 0; i < 32; i += 2) {
162 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
167 for (i = 8; i < 16; i++) {
168 regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
174 ret = reset_control_assert(pd->rstc);
178 regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
179 GEN_PWR_VPU_HDMI_ISO, 0);
181 ret = reset_control_deassert(pd->rstc);
185 ret = meson_gx_pwrc_vpu_setup_clk(pd);
192 static int meson_g12a_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
194 struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
198 regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
199 GEN_PWR_VPU_HDMI, 0);
202 /* Power Up Memories */
203 for (i = 0; i < 32; i += 2) {
204 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
209 for (i = 0; i < 32; i += 2) {
210 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
215 for (i = 0; i < 32; i += 2) {
216 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG2,
221 for (i = 8; i < 16; i++) {
222 regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
228 ret = reset_control_assert(pd->rstc);
232 regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
233 GEN_PWR_VPU_HDMI_ISO, 0);
235 ret = reset_control_deassert(pd->rstc);
239 ret = meson_gx_pwrc_vpu_setup_clk(pd);
246 static bool meson_gx_pwrc_vpu_get_power(struct meson_gx_pwrc_vpu *pd)
250 regmap_read(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, ®);
252 return (reg & GEN_PWR_VPU_HDMI);
255 static struct meson_gx_pwrc_vpu vpu_hdmi_pd = {
258 .power_off = meson_gx_pwrc_vpu_power_off,
259 .power_on = meson_gx_pwrc_vpu_power_on,
263 static struct meson_gx_pwrc_vpu vpu_hdmi_pd_g12a = {
266 .power_off = meson_g12a_pwrc_vpu_power_off,
267 .power_on = meson_g12a_pwrc_vpu_power_on,
271 static int meson_gx_pwrc_vpu_probe(struct platform_device *pdev)
273 const struct meson_gx_pwrc_vpu *vpu_pd_match;
274 struct regmap *regmap_ao, *regmap_hhi;
275 struct meson_gx_pwrc_vpu *vpu_pd;
276 struct reset_control *rstc;
278 struct clk *vapb_clk;
282 vpu_pd_match = of_device_get_match_data(&pdev->dev);
284 dev_err(&pdev->dev, "failed to get match data\n");
288 vpu_pd = devm_kzalloc(&pdev->dev, sizeof(*vpu_pd), GFP_KERNEL);
292 memcpy(vpu_pd, vpu_pd_match, sizeof(*vpu_pd));
294 regmap_ao = syscon_node_to_regmap(of_get_parent(pdev->dev.of_node));
295 if (IS_ERR(regmap_ao)) {
296 dev_err(&pdev->dev, "failed to get regmap\n");
297 return PTR_ERR(regmap_ao);
300 regmap_hhi = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
301 "amlogic,hhi-sysctrl");
302 if (IS_ERR(regmap_hhi)) {
303 dev_err(&pdev->dev, "failed to get HHI regmap\n");
304 return PTR_ERR(regmap_hhi);
307 rstc = devm_reset_control_array_get_exclusive(&pdev->dev);
309 if (PTR_ERR(rstc) != -EPROBE_DEFER)
310 dev_err(&pdev->dev, "failed to get reset lines\n");
311 return PTR_ERR(rstc);
314 vpu_clk = devm_clk_get(&pdev->dev, "vpu");
315 if (IS_ERR(vpu_clk)) {
316 dev_err(&pdev->dev, "vpu clock request failed\n");
317 return PTR_ERR(vpu_clk);
320 vapb_clk = devm_clk_get(&pdev->dev, "vapb");
321 if (IS_ERR(vapb_clk)) {
322 dev_err(&pdev->dev, "vapb clock request failed\n");
323 return PTR_ERR(vapb_clk);
326 vpu_pd->regmap_ao = regmap_ao;
327 vpu_pd->regmap_hhi = regmap_hhi;
329 vpu_pd->vpu_clk = vpu_clk;
330 vpu_pd->vapb_clk = vapb_clk;
332 platform_set_drvdata(pdev, vpu_pd);
334 powered_off = meson_gx_pwrc_vpu_get_power(vpu_pd);
336 /* If already powered, sync the clock states */
338 ret = meson_gx_pwrc_vpu_setup_clk(vpu_pd);
343 vpu_pd->genpd.flags = GENPD_FLAG_ALWAYS_ON;
344 pm_genpd_init(&vpu_pd->genpd, NULL, powered_off);
346 return of_genpd_add_provider_simple(pdev->dev.of_node,
350 static void meson_gx_pwrc_vpu_shutdown(struct platform_device *pdev)
352 struct meson_gx_pwrc_vpu *vpu_pd = platform_get_drvdata(pdev);
355 powered_off = meson_gx_pwrc_vpu_get_power(vpu_pd);
357 vpu_pd->genpd.power_off(&vpu_pd->genpd);
360 static const struct of_device_id meson_gx_pwrc_vpu_match_table[] = {
361 { .compatible = "amlogic,meson-gx-pwrc-vpu", .data = &vpu_hdmi_pd },
363 .compatible = "amlogic,meson-g12a-pwrc-vpu",
364 .data = &vpu_hdmi_pd_g12a
368 MODULE_DEVICE_TABLE(of, meson_gx_pwrc_vpu_match_table);
370 static struct platform_driver meson_gx_pwrc_vpu_driver = {
371 .probe = meson_gx_pwrc_vpu_probe,
372 .shutdown = meson_gx_pwrc_vpu_shutdown,
374 .name = "meson_gx_pwrc_vpu",
375 .of_match_table = meson_gx_pwrc_vpu_match_table,
378 module_platform_driver(meson_gx_pwrc_vpu_driver);
379 MODULE_LICENSE("GPL v2");