2 * Copyright (c) 2017 BayLibre, SAS
3 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/of_address.h>
9 #include <linux/platform_device.h>
10 #include <linux/pm_domain.h>
11 #include <linux/bitfield.h>
12 #include <linux/regmap.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/reset.h>
15 #include <linux/clk.h>
19 #define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2)
21 #define GEN_PWR_VPU_HDMI BIT(8)
22 #define GEN_PWR_VPU_HDMI_ISO BIT(9)
26 #define HHI_MEM_PD_REG0 (0x40 << 2)
27 #define HHI_VPU_MEM_PD_REG0 (0x41 << 2)
28 #define HHI_VPU_MEM_PD_REG1 (0x42 << 2)
30 struct meson_gx_pwrc_vpu {
31 struct generic_pm_domain genpd;
32 struct regmap *regmap_ao;
33 struct regmap *regmap_hhi;
34 struct reset_control *rstc;
40 struct meson_gx_pwrc_vpu *genpd_to_pd(struct generic_pm_domain *d)
42 return container_of(d, struct meson_gx_pwrc_vpu, genpd);
45 static int meson_gx_pwrc_vpu_power_off(struct generic_pm_domain *genpd)
47 struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
50 regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
51 GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO);
54 /* Power Down Memories */
55 for (i = 0; i < 32; i += 2) {
56 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
60 for (i = 0; i < 32; i += 2) {
61 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
65 for (i = 8; i < 16; i++) {
66 regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
72 regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
73 GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI);
77 clk_disable_unprepare(pd->vpu_clk);
78 clk_disable_unprepare(pd->vapb_clk);
83 static int meson_gx_pwrc_vpu_setup_clk(struct meson_gx_pwrc_vpu *pd)
87 ret = clk_prepare_enable(pd->vpu_clk);
91 ret = clk_prepare_enable(pd->vapb_clk);
93 clk_disable_unprepare(pd->vpu_clk);
98 static int meson_gx_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
100 struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
104 regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
105 GEN_PWR_VPU_HDMI, 0);
108 /* Power Up Memories */
109 for (i = 0; i < 32; i += 2) {
110 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
115 for (i = 0; i < 32; i += 2) {
116 regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
121 for (i = 8; i < 16; i++) {
122 regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
128 ret = reset_control_assert(pd->rstc);
132 regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
133 GEN_PWR_VPU_HDMI_ISO, 0);
135 ret = reset_control_deassert(pd->rstc);
139 ret = meson_gx_pwrc_vpu_setup_clk(pd);
146 static bool meson_gx_pwrc_vpu_get_power(struct meson_gx_pwrc_vpu *pd)
150 regmap_read(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, ®);
152 return (reg & GEN_PWR_VPU_HDMI);
155 static struct meson_gx_pwrc_vpu vpu_hdmi_pd = {
158 .power_off = meson_gx_pwrc_vpu_power_off,
159 .power_on = meson_gx_pwrc_vpu_power_on,
163 static int meson_gx_pwrc_vpu_probe(struct platform_device *pdev)
165 struct regmap *regmap_ao, *regmap_hhi;
166 struct reset_control *rstc;
168 struct clk *vapb_clk;
172 regmap_ao = syscon_node_to_regmap(of_get_parent(pdev->dev.of_node));
173 if (IS_ERR(regmap_ao)) {
174 dev_err(&pdev->dev, "failed to get regmap\n");
175 return PTR_ERR(regmap_ao);
178 regmap_hhi = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
179 "amlogic,hhi-sysctrl");
180 if (IS_ERR(regmap_hhi)) {
181 dev_err(&pdev->dev, "failed to get HHI regmap\n");
182 return PTR_ERR(regmap_hhi);
185 rstc = devm_reset_control_array_get(&pdev->dev, false, false);
187 dev_err(&pdev->dev, "failed to get reset lines\n");
188 return PTR_ERR(rstc);
191 vpu_clk = devm_clk_get(&pdev->dev, "vpu");
192 if (IS_ERR(vpu_clk)) {
193 dev_err(&pdev->dev, "vpu clock request failed\n");
194 return PTR_ERR(vpu_clk);
197 vapb_clk = devm_clk_get(&pdev->dev, "vapb");
198 if (IS_ERR(vapb_clk)) {
199 dev_err(&pdev->dev, "vapb clock request failed\n");
200 return PTR_ERR(vapb_clk);
203 vpu_hdmi_pd.regmap_ao = regmap_ao;
204 vpu_hdmi_pd.regmap_hhi = regmap_hhi;
205 vpu_hdmi_pd.rstc = rstc;
206 vpu_hdmi_pd.vpu_clk = vpu_clk;
207 vpu_hdmi_pd.vapb_clk = vapb_clk;
209 powered_off = meson_gx_pwrc_vpu_get_power(&vpu_hdmi_pd);
211 /* If already powered, sync the clock states */
213 ret = meson_gx_pwrc_vpu_setup_clk(&vpu_hdmi_pd);
218 pm_genpd_init(&vpu_hdmi_pd.genpd, &pm_domain_always_on_gov,
221 return of_genpd_add_provider_simple(pdev->dev.of_node,
225 static void meson_gx_pwrc_vpu_shutdown(struct platform_device *pdev)
227 meson_gx_pwrc_vpu_power_off(&vpu_hdmi_pd.genpd);
230 static const struct of_device_id meson_gx_pwrc_vpu_match_table[] = {
231 { .compatible = "amlogic,meson-gx-pwrc-vpu" },
235 static struct platform_driver meson_gx_pwrc_vpu_driver = {
236 .probe = meson_gx_pwrc_vpu_probe,
237 .shutdown = meson_gx_pwrc_vpu_shutdown,
239 .name = "meson_gx_pwrc_vpu",
240 .of_match_table = meson_gx_pwrc_vpu_match_table,
243 builtin_platform_driver(meson_gx_pwrc_vpu_driver);