1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011-2017, The Linux Foundation
7 #include <linux/kernel.h>
8 #include <linux/init.h>
9 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/platform_device.h>
13 #include <linux/delay.h>
14 #include <linux/clk.h>
16 #include <linux/pm_runtime.h>
19 /* Manager registers */
21 #define MGR_STATUS 0x204
22 #define MGR_INT_EN 0x210
23 #define MGR_INT_STAT 0x214
24 #define MGR_INT_CLR 0x218
25 #define MGR_TX_MSG 0x230
26 #define MGR_RX_MSG 0x270
27 #define MGR_IE_STAT 0x2F0
28 #define MGR_VE_STAT 0x300
29 #define MGR_CFG_ENABLE 1
31 /* Framer registers */
33 #define FRM_STAT 0x404
34 #define FRM_INT_EN 0x410
35 #define FRM_INT_STAT 0x414
36 #define FRM_INT_CLR 0x418
37 #define FRM_WAKEUP 0x41C
38 #define FRM_CLKCTL_DONE 0x420
39 #define FRM_IE_STAT 0x430
40 #define FRM_VE_STAT 0x440
42 /* Interface registers */
43 #define INTF_CFG 0x600
44 #define INTF_STAT 0x604
45 #define INTF_INT_EN 0x610
46 #define INTF_INT_STAT 0x614
47 #define INTF_INT_CLR 0x618
48 #define INTF_IE_STAT 0x630
49 #define INTF_VE_STAT 0x640
51 /* Interrupt status bits */
52 #define MGR_INT_TX_NACKED_2 BIT(25)
53 #define MGR_INT_MSG_BUF_CONTE BIT(26)
54 #define MGR_INT_RX_MSG_RCVD BIT(30)
55 #define MGR_INT_TX_MSG_SENT BIT(31)
57 /* Framer config register settings */
61 #define REF_CLK_GEAR 15
64 #define SLIM_MSG_ASM_FIRST_WORD(l, mt, mc, dt, ad) \
65 ((l) | ((mt) << 5) | ((mc) << 8) | ((dt) << 15) | ((ad) << 16))
67 #define SLIM_ROOT_FREQ 24576000
68 #define QCOM_SLIM_AUTOSUSPEND 1000
70 /* MAX message size over control channel */
71 #define SLIM_MSGQ_BUF_LEN 40
72 #define QCOM_TX_MSGS 2
73 #define QCOM_RX_MSGS 8
74 #define QCOM_BUF_ALLOC_RETRIES 10
76 #define CFG_PORT(r, v) ((v) ? CFG_PORT_V2(r) : CFG_PORT_V1(r))
78 /* V2 Component registers */
79 #define CFG_PORT_V2(r) ((r ## _V2))
81 #define COMP_TRUST_CFG_V2 0x3000
83 /* V1 Component registers */
84 #define CFG_PORT_V1(r) ((r ## _V1))
86 #define COMP_TRUST_CFG_V1 0x14
88 /* Resource group info for manager, and non-ported generic device-components */
89 #define EE_MGR_RSC_GRP (1 << 10)
90 #define EE_NGD_2 (2 << 6)
93 struct slim_ctrl_buf {
102 struct qcom_slim_ctrl {
103 struct slim_controller ctrl;
104 struct slim_framer framer;
107 void __iomem *slew_reg;
109 struct slim_ctrl_buf rx;
110 struct slim_ctrl_buf tx;
112 struct completion **wr_comp;
114 struct workqueue_struct *rxwq;
115 struct work_struct wd;
120 static void qcom_slim_queue_tx(struct qcom_slim_ctrl *ctrl, void *buf,
123 int count = (len + 3) >> 2;
125 __iowrite32_copy(ctrl->base + tx_reg, buf, count);
127 /* Ensure Oder of subsequent writes */
131 static void *slim_alloc_rxbuf(struct qcom_slim_ctrl *ctrl)
136 spin_lock_irqsave(&ctrl->rx.lock, flags);
137 if ((ctrl->rx.tail + 1) % ctrl->rx.n == ctrl->rx.head) {
138 spin_unlock_irqrestore(&ctrl->rx.lock, flags);
139 dev_err(ctrl->dev, "RX QUEUE full!");
143 ctrl->rx.tail = (ctrl->rx.tail + 1) % ctrl->rx.n;
144 spin_unlock_irqrestore(&ctrl->rx.lock, flags);
146 return ctrl->rx.base + (idx * ctrl->rx.sl_sz);
149 static void slim_ack_txn(struct qcom_slim_ctrl *ctrl, int err)
151 struct completion *comp;
155 spin_lock_irqsave(&ctrl->tx.lock, flags);
157 ctrl->tx.head = (ctrl->tx.head + 1) % ctrl->tx.n;
158 spin_unlock_irqrestore(&ctrl->tx.lock, flags);
160 comp = ctrl->wr_comp[idx];
161 ctrl->wr_comp[idx] = NULL;
166 static irqreturn_t qcom_slim_handle_tx_irq(struct qcom_slim_ctrl *ctrl,
171 if (stat & MGR_INT_TX_MSG_SENT)
172 writel_relaxed(MGR_INT_TX_MSG_SENT,
173 ctrl->base + MGR_INT_CLR);
175 if (stat & MGR_INT_TX_NACKED_2) {
176 u32 mgr_stat = readl_relaxed(ctrl->base + MGR_STATUS);
177 u32 mgr_ie_stat = readl_relaxed(ctrl->base + MGR_IE_STAT);
178 u32 frm_stat = readl_relaxed(ctrl->base + FRM_STAT);
179 u32 frm_cfg = readl_relaxed(ctrl->base + FRM_CFG);
180 u32 frm_intr_stat = readl_relaxed(ctrl->base + FRM_INT_STAT);
181 u32 frm_ie_stat = readl_relaxed(ctrl->base + FRM_IE_STAT);
182 u32 intf_stat = readl_relaxed(ctrl->base + INTF_STAT);
183 u32 intf_intr_stat = readl_relaxed(ctrl->base + INTF_INT_STAT);
184 u32 intf_ie_stat = readl_relaxed(ctrl->base + INTF_IE_STAT);
186 writel_relaxed(MGR_INT_TX_NACKED_2, ctrl->base + MGR_INT_CLR);
188 dev_err(ctrl->dev, "TX Nack MGR:int:0x%x, stat:0x%x\n",
190 dev_err(ctrl->dev, "TX Nack MGR:ie:0x%x\n", mgr_ie_stat);
191 dev_err(ctrl->dev, "TX Nack FRM:int:0x%x, stat:0x%x\n",
192 frm_intr_stat, frm_stat);
193 dev_err(ctrl->dev, "TX Nack FRM:cfg:0x%x, ie:0x%x\n",
194 frm_cfg, frm_ie_stat);
195 dev_err(ctrl->dev, "TX Nack INTF:intr:0x%x, stat:0x%x\n",
196 intf_intr_stat, intf_stat);
197 dev_err(ctrl->dev, "TX Nack INTF:ie:0x%x\n",
202 slim_ack_txn(ctrl, err);
207 static irqreturn_t qcom_slim_handle_rx_irq(struct qcom_slim_ctrl *ctrl,
210 u32 *rx_buf, pkt[10];
214 pkt[0] = readl_relaxed(ctrl->base + MGR_RX_MSG);
215 mt = SLIM_HEADER_GET_MT(pkt[0]);
216 len = SLIM_HEADER_GET_RL(pkt[0]);
217 mc = SLIM_HEADER_GET_MC(pkt[0]>>8);
220 * this message cannot be handled by ISR, so
221 * let work-queue handle it
223 if (mt == SLIM_MSG_MT_CORE && mc == SLIM_MSG_MC_REPORT_PRESENT) {
224 rx_buf = (u32 *)slim_alloc_rxbuf(ctrl);
226 dev_err(ctrl->dev, "dropping RX:0x%x due to RX full\n",
236 __ioread32_copy(rx_buf + 1, ctrl->base + MGR_RX_MSG + 4,
237 DIV_ROUND_UP(len, 4));
241 case SLIM_MSG_MC_REPORT_PRESENT:
244 case SLIM_MSG_MC_REPLY_INFORMATION:
245 case SLIM_MSG_MC_REPLY_VALUE:
246 slim_msg_response(&ctrl->ctrl, (u8 *)(rx_buf + 1),
247 (u8)(*rx_buf >> 24), (len - 4));
250 dev_err(ctrl->dev, "unsupported MC,%x MT:%x\n",
255 writel(MGR_INT_RX_MSG_RCVD, ctrl->base +
258 queue_work(ctrl->rxwq, &ctrl->wd);
263 static irqreturn_t qcom_slim_interrupt(int irq, void *d)
265 struct qcom_slim_ctrl *ctrl = d;
266 u32 stat = readl_relaxed(ctrl->base + MGR_INT_STAT);
269 if (stat & MGR_INT_TX_MSG_SENT || stat & MGR_INT_TX_NACKED_2)
270 ret = qcom_slim_handle_tx_irq(ctrl, stat);
272 if (stat & MGR_INT_RX_MSG_RCVD)
273 ret = qcom_slim_handle_rx_irq(ctrl, stat);
278 static int qcom_clk_pause_wakeup(struct slim_controller *sctrl)
280 struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
282 clk_prepare_enable(ctrl->hclk);
283 clk_prepare_enable(ctrl->rclk);
284 enable_irq(ctrl->irq);
286 writel_relaxed(1, ctrl->base + FRM_WAKEUP);
287 /* Make sure framer wakeup write goes through before ISR fires */
290 * HW Workaround: Currently, slave is reporting lost-sync messages
291 * after SLIMbus comes out of clock pause.
292 * Transaction with slave fail before slave reports that message
293 * Give some time for that report to come
294 * SLIMbus wakes up in clock gear 10 at 24.576MHz. With each superframe
295 * being 250 usecs, we wait for 5-10 superframes here to ensure
298 usleep_range(1250, 2500);
302 static void *slim_alloc_txbuf(struct qcom_slim_ctrl *ctrl,
303 struct slim_msg_txn *txn,
304 struct completion *done)
309 spin_lock_irqsave(&ctrl->tx.lock, flags);
310 if (((ctrl->tx.head + 1) % ctrl->tx.n) == ctrl->tx.tail) {
311 spin_unlock_irqrestore(&ctrl->tx.lock, flags);
312 dev_err(ctrl->dev, "controller TX buf unavailable");
316 ctrl->wr_comp[idx] = done;
317 ctrl->tx.tail = (ctrl->tx.tail + 1) % ctrl->tx.n;
319 spin_unlock_irqrestore(&ctrl->tx.lock, flags);
321 return ctrl->tx.base + (idx * ctrl->tx.sl_sz);
325 static int qcom_xfer_msg(struct slim_controller *sctrl,
326 struct slim_msg_txn *txn)
328 struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
329 DECLARE_COMPLETION_ONSTACK(done);
330 void *pbuf = slim_alloc_txbuf(ctrl, txn, &done);
331 unsigned long ms = txn->rl + HZ;
333 int ret = 0, timeout, retries = QCOM_BUF_ALLOC_RETRIES;
336 /* HW expects length field to be excluded */
339 /* spin till buffer is made available */
342 usleep_range(10000, 15000);
343 pbuf = slim_alloc_txbuf(ctrl, txn, &done);
349 if (retries < 0 && !pbuf)
355 if (txn->dt == SLIM_MSG_DEST_LOGICALADDR) {
356 *head = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt,
360 *head = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt,
365 if (slim_tid_txn(txn->mt, txn->mc))
368 if (slim_ec_txn(txn->mt, txn->mc)) {
369 *(puc++) = (txn->ec & 0xFF);
370 *(puc++) = (txn->ec >> 8) & 0xFF;
373 if (txn->msg && txn->msg->wbuf)
374 memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes);
376 qcom_slim_queue_tx(ctrl, head, txn->rl, MGR_TX_MSG);
377 timeout = wait_for_completion_timeout(&done, msecs_to_jiffies(ms));
380 dev_err(ctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc,
389 static int qcom_set_laddr(struct slim_controller *sctrl,
390 struct slim_eaddr *ead, u8 laddr)
392 struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
400 struct slim_val_inf msg = {0};
401 DEFINE_SLIM_EDEST_TXN(txn, SLIM_MSG_MC_ASSIGN_LOGICAL_ADDRESS,
405 p.manf_id = cpu_to_be16(ead->manf_id);
406 p.prod_code = cpu_to_be16(ead->prod_code);
407 p.dev_index = ead->dev_index;
408 p.instance = ead->instance;
411 msg.wbuf = (void *)&p;
413 ret = slim_do_transfer(&ctrl->ctrl, &txn);
416 dev_err(ctrl->dev, "set LA:0x%x failed:ret:%d\n",
421 static int slim_get_current_rxbuf(struct qcom_slim_ctrl *ctrl, void *buf)
425 spin_lock_irqsave(&ctrl->rx.lock, flags);
426 if (ctrl->rx.tail == ctrl->rx.head) {
427 spin_unlock_irqrestore(&ctrl->rx.lock, flags);
430 memcpy(buf, ctrl->rx.base + (ctrl->rx.head * ctrl->rx.sl_sz),
433 ctrl->rx.head = (ctrl->rx.head + 1) % ctrl->rx.n;
434 spin_unlock_irqrestore(&ctrl->rx.lock, flags);
439 static void qcom_slim_rxwq(struct work_struct *work)
441 u8 buf[SLIM_MSGQ_BUF_LEN];
444 struct qcom_slim_ctrl *ctrl = container_of(work, struct qcom_slim_ctrl,
447 while ((slim_get_current_rxbuf(ctrl, buf)) != -ENODATA) {
448 mt = SLIM_HEADER_GET_MT(buf[0]);
449 mc = SLIM_HEADER_GET_MC(buf[1]);
450 if (mt == SLIM_MSG_MT_CORE &&
451 mc == SLIM_MSG_MC_REPORT_PRESENT) {
452 struct slim_eaddr ea;
455 ea.manf_id = be16_to_cpup((__be16 *)&buf[2]);
456 ea.prod_code = be16_to_cpup((__be16 *)&buf[4]);
457 ea.dev_index = buf[6];
458 ea.instance = buf[7];
460 ret = slim_device_report_present(&ctrl->ctrl, &ea,
463 dev_err(ctrl->dev, "assign laddr failed:%d\n",
466 dev_err(ctrl->dev, "unexpected message:mc:%x, mt:%x\n",
472 static void qcom_slim_prg_slew(struct platform_device *pdev,
473 struct qcom_slim_ctrl *ctrl)
475 struct resource *slew_mem;
477 if (!ctrl->slew_reg) {
478 /* SLEW RATE register for this SLIMbus */
479 slew_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM,
481 ctrl->slew_reg = devm_ioremap(&pdev->dev, slew_mem->start,
482 resource_size(slew_mem));
487 writel_relaxed(1, ctrl->slew_reg);
488 /* Make sure SLIMbus-slew rate enabling goes through */
492 static int qcom_slim_probe(struct platform_device *pdev)
494 struct qcom_slim_ctrl *ctrl;
495 struct slim_controller *sctrl;
496 struct resource *slim_mem;
499 ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
503 ctrl->hclk = devm_clk_get(&pdev->dev, "iface");
504 if (IS_ERR(ctrl->hclk))
505 return PTR_ERR(ctrl->hclk);
507 ctrl->rclk = devm_clk_get(&pdev->dev, "core");
508 if (IS_ERR(ctrl->rclk))
509 return PTR_ERR(ctrl->rclk);
511 ret = clk_set_rate(ctrl->rclk, SLIM_ROOT_FREQ);
513 dev_err(&pdev->dev, "ref-clock set-rate failed:%d\n", ret);
517 ctrl->irq = platform_get_irq(pdev, 0);
519 dev_err(&pdev->dev, "no slimbus IRQ\n");
524 sctrl->dev = &pdev->dev;
525 ctrl->dev = &pdev->dev;
526 platform_set_drvdata(pdev, ctrl);
527 dev_set_drvdata(ctrl->dev, ctrl);
529 slim_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
530 ctrl->base = devm_ioremap_resource(ctrl->dev, slim_mem);
531 if (IS_ERR(ctrl->base))
532 return PTR_ERR(ctrl->base);
534 sctrl->set_laddr = qcom_set_laddr;
535 sctrl->xfer_msg = qcom_xfer_msg;
536 sctrl->wakeup = qcom_clk_pause_wakeup;
537 ctrl->tx.n = QCOM_TX_MSGS;
538 ctrl->tx.sl_sz = SLIM_MSGQ_BUF_LEN;
539 ctrl->rx.n = QCOM_RX_MSGS;
540 ctrl->rx.sl_sz = SLIM_MSGQ_BUF_LEN;
541 ctrl->wr_comp = kcalloc(QCOM_TX_MSGS, sizeof(struct completion *),
546 spin_lock_init(&ctrl->rx.lock);
547 spin_lock_init(&ctrl->tx.lock);
548 INIT_WORK(&ctrl->wd, qcom_slim_rxwq);
549 ctrl->rxwq = create_singlethread_workqueue("qcom_slim_rx");
551 dev_err(ctrl->dev, "Failed to start Rx WQ\n");
555 ctrl->framer.rootfreq = SLIM_ROOT_FREQ / 8;
556 ctrl->framer.superfreq =
557 ctrl->framer.rootfreq / SLIM_CL_PER_SUPERFRAME_DIV8;
558 sctrl->a_framer = &ctrl->framer;
559 sctrl->clkgear = SLIM_MAX_CLK_GEAR;
561 qcom_slim_prg_slew(pdev, ctrl);
563 ret = devm_request_irq(&pdev->dev, ctrl->irq, qcom_slim_interrupt,
564 IRQF_TRIGGER_HIGH, "qcom_slim_irq", ctrl);
566 dev_err(&pdev->dev, "request IRQ failed\n");
567 goto err_request_irq_failed;
570 ret = clk_prepare_enable(ctrl->hclk);
572 goto err_hclk_enable_failed;
574 ret = clk_prepare_enable(ctrl->rclk);
576 goto err_rclk_enable_failed;
578 ctrl->tx.base = devm_kcalloc(&pdev->dev, ctrl->tx.n, ctrl->tx.sl_sz,
580 if (!ctrl->tx.base) {
585 ctrl->rx.base = devm_kcalloc(&pdev->dev,ctrl->rx.n, ctrl->rx.sl_sz,
587 if (!ctrl->rx.base) {
592 /* Register with framework before enabling frame, clock */
593 ret = slim_register_controller(&ctrl->ctrl);
595 dev_err(ctrl->dev, "error adding controller\n");
599 ver = readl_relaxed(ctrl->base);
600 /* Version info in 16 MSbits */
602 /* Component register initialization */
603 writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver));
604 writel((EE_MGR_RSC_GRP | EE_NGD_2 | EE_NGD_1),
605 ctrl->base + CFG_PORT(COMP_TRUST_CFG, ver));
607 writel((MGR_INT_TX_NACKED_2 |
608 MGR_INT_MSG_BUF_CONTE | MGR_INT_RX_MSG_RCVD |
609 MGR_INT_TX_MSG_SENT), ctrl->base + MGR_INT_EN);
610 writel(1, ctrl->base + MGR_CFG);
611 /* Framer register initialization */
612 writel((1 << INTR_WAKE) | (0xA << REF_CLK_GEAR) |
613 (0xA << CLK_GEAR) | (1 << ROOT_FREQ) | (1 << FRM_ACTIVE) | 1,
614 ctrl->base + FRM_CFG);
615 writel(MGR_CFG_ENABLE, ctrl->base + MGR_CFG);
616 writel(1, ctrl->base + INTF_CFG);
617 writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver));
619 pm_runtime_use_autosuspend(&pdev->dev);
620 pm_runtime_set_autosuspend_delay(&pdev->dev, QCOM_SLIM_AUTOSUSPEND);
621 pm_runtime_set_active(&pdev->dev);
622 pm_runtime_mark_last_busy(&pdev->dev);
623 pm_runtime_enable(&pdev->dev);
625 dev_dbg(ctrl->dev, "QCOM SB controller is up:ver:0x%x!\n", ver);
629 clk_disable_unprepare(ctrl->rclk);
630 err_rclk_enable_failed:
631 clk_disable_unprepare(ctrl->hclk);
632 err_hclk_enable_failed:
633 err_request_irq_failed:
634 destroy_workqueue(ctrl->rxwq);
638 static int qcom_slim_remove(struct platform_device *pdev)
640 struct qcom_slim_ctrl *ctrl = platform_get_drvdata(pdev);
642 pm_runtime_disable(&pdev->dev);
643 slim_unregister_controller(&ctrl->ctrl);
644 clk_disable_unprepare(ctrl->rclk);
645 clk_disable_unprepare(ctrl->hclk);
646 destroy_workqueue(ctrl->rxwq);
651 * If PM_RUNTIME is not defined, these 2 functions become helper
652 * functions to be called from system suspend/resume.
655 static int qcom_slim_runtime_suspend(struct device *device)
657 struct qcom_slim_ctrl *ctrl = dev_get_drvdata(device);
660 dev_dbg(device, "pm_runtime: suspending...\n");
661 ret = slim_ctrl_clk_pause(&ctrl->ctrl, false, SLIM_CLK_UNSPECIFIED);
663 dev_err(device, "clk pause not entered:%d", ret);
665 disable_irq(ctrl->irq);
666 clk_disable_unprepare(ctrl->hclk);
667 clk_disable_unprepare(ctrl->rclk);
672 static int qcom_slim_runtime_resume(struct device *device)
674 struct qcom_slim_ctrl *ctrl = dev_get_drvdata(device);
677 dev_dbg(device, "pm_runtime: resuming...\n");
678 ret = slim_ctrl_clk_pause(&ctrl->ctrl, true, 0);
680 dev_err(device, "clk pause not exited:%d", ret);
685 #ifdef CONFIG_PM_SLEEP
686 static int qcom_slim_suspend(struct device *dev)
690 if (!pm_runtime_enabled(dev) ||
691 (!pm_runtime_suspended(dev))) {
692 dev_dbg(dev, "system suspend");
693 ret = qcom_slim_runtime_suspend(dev);
699 static int qcom_slim_resume(struct device *dev)
701 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
704 dev_dbg(dev, "system resume");
705 ret = qcom_slim_runtime_resume(dev);
707 pm_runtime_mark_last_busy(dev);
708 pm_request_autosuspend(dev);
715 #endif /* CONFIG_PM_SLEEP */
717 static const struct dev_pm_ops qcom_slim_dev_pm_ops = {
718 SET_SYSTEM_SLEEP_PM_OPS(qcom_slim_suspend, qcom_slim_resume)
720 qcom_slim_runtime_suspend,
721 qcom_slim_runtime_resume,
726 static const struct of_device_id qcom_slim_dt_match[] = {
727 { .compatible = "qcom,slim", },
728 { .compatible = "qcom,apq8064-slim", },
732 static struct platform_driver qcom_slim_driver = {
733 .probe = qcom_slim_probe,
734 .remove = qcom_slim_remove,
736 .name = "qcom_slim_ctrl",
737 .of_match_table = qcom_slim_dt_match,
738 .pm = &qcom_slim_dev_pm_ops,
741 module_platform_driver(qcom_slim_driver);
743 MODULE_LICENSE("GPL v2");
744 MODULE_DESCRIPTION("Qualcomm SLIMbus Controller");