2 * Helper routines for SuperH Clock Pulse Generator blocks (CPG).
4 * Copyright (C) 2010 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/clk.h>
11 #include <linux/compiler.h>
12 #include <linux/slab.h>
14 #include <linux/sh_clk.h>
16 static int sh_clk_mstp32_enable(struct clk *clk)
18 __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit),
23 static void sh_clk_mstp32_disable(struct clk *clk)
25 __raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit),
29 static struct clk_ops sh_clk_mstp32_clk_ops = {
30 .enable = sh_clk_mstp32_enable,
31 .disable = sh_clk_mstp32_disable,
32 .recalc = followparent_recalc,
35 int __init sh_clk_mstp32_register(struct clk *clks, int nr)
41 for (k = 0; !ret && (k < nr); k++) {
43 clkp->ops = &sh_clk_mstp32_clk_ops;
44 ret |= clk_register(clkp);
50 static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)
52 return clk_rate_table_round(clk, clk->freq_table, rate);
55 static int sh_clk_div6_divisors[64] = {
56 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
57 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
58 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
59 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
62 static struct clk_div_mult_table sh_clk_div6_table = {
63 .divisors = sh_clk_div6_divisors,
64 .nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors),
67 static unsigned long sh_clk_div6_recalc(struct clk *clk)
69 struct clk_div_mult_table *table = &sh_clk_div6_table;
72 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
75 idx = __raw_readl(clk->enable_reg) & 0x003f;
77 return clk->freq_table[idx].frequency;
80 static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)
82 struct clk_div_mult_table *table = &sh_clk_div6_table;
86 if (!clk->parent_table || !clk->parent_num)
89 /* Search the parent */
90 for (i = 0; i < clk->parent_num; i++)
91 if (clk->parent_table[i] == parent)
94 if (i == clk->parent_num)
97 ret = clk_reparent(clk, parent);
101 value = __raw_readl(clk->enable_reg) &
102 ~(((1 << clk->src_width) - 1) << clk->src_shift);
104 __raw_writel(value | (i << clk->src_shift), clk->enable_reg);
106 /* Rebuild the frequency table */
107 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
108 table, &clk->arch_flags);
113 static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate)
118 idx = clk_rate_table_find(clk, clk->freq_table, rate);
122 value = __raw_readl(clk->enable_reg);
125 __raw_writel(value, clk->enable_reg);
129 static int sh_clk_div6_enable(struct clk *clk)
134 ret = sh_clk_div6_set_rate(clk, clk->rate);
136 value = __raw_readl(clk->enable_reg);
137 value &= ~0x100; /* clear stop bit to enable clock */
138 __raw_writel(value, clk->enable_reg);
143 static void sh_clk_div6_disable(struct clk *clk)
147 value = __raw_readl(clk->enable_reg);
148 value |= 0x100; /* stop clock */
149 value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */
150 __raw_writel(value, clk->enable_reg);
153 static struct clk_ops sh_clk_div6_clk_ops = {
154 .recalc = sh_clk_div6_recalc,
155 .round_rate = sh_clk_div_round_rate,
156 .set_rate = sh_clk_div6_set_rate,
157 .enable = sh_clk_div6_enable,
158 .disable = sh_clk_div6_disable,
161 static struct clk_ops sh_clk_div6_reparent_clk_ops = {
162 .recalc = sh_clk_div6_recalc,
163 .round_rate = sh_clk_div_round_rate,
164 .set_rate = sh_clk_div6_set_rate,
165 .enable = sh_clk_div6_enable,
166 .disable = sh_clk_div6_disable,
167 .set_parent = sh_clk_div6_set_parent,
170 static int __init sh_clk_div6_register_ops(struct clk *clks, int nr,
175 int nr_divs = sh_clk_div6_table.nr_divisors;
176 int freq_table_size = sizeof(struct cpufreq_frequency_table);
180 freq_table_size *= (nr_divs + 1);
181 freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
183 pr_err("sh_clk_div6_register: unable to alloc memory\n");
187 for (k = 0; !ret && (k < nr); k++) {
191 clkp->freq_table = freq_table + (k * freq_table_size);
192 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
194 ret = clk_register(clkp);
200 int __init sh_clk_div6_register(struct clk *clks, int nr)
202 return sh_clk_div6_register_ops(clks, nr, &sh_clk_div6_clk_ops);
205 int __init sh_clk_div6_reparent_register(struct clk *clks, int nr)
207 return sh_clk_div6_register_ops(clks, nr,
208 &sh_clk_div6_reparent_clk_ops);
211 static unsigned long sh_clk_div4_recalc(struct clk *clk)
213 struct clk_div4_table *d4t = clk->priv;
214 struct clk_div_mult_table *table = d4t->div_mult_table;
217 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
218 table, &clk->arch_flags);
220 idx = (__raw_readl(clk->enable_reg) >> clk->enable_bit) & 0x000f;
222 return clk->freq_table[idx].frequency;
225 static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
227 struct clk_div4_table *d4t = clk->priv;
228 struct clk_div_mult_table *table = d4t->div_mult_table;
232 /* we really need a better way to determine parent index, but for
233 * now assume internal parent comes with CLK_ENABLE_ON_INIT set,
234 * no CLK_ENABLE_ON_INIT means external clock...
237 if (parent->flags & CLK_ENABLE_ON_INIT)
238 value = __raw_readl(clk->enable_reg) & ~(1 << 7);
240 value = __raw_readl(clk->enable_reg) | (1 << 7);
242 ret = clk_reparent(clk, parent);
246 __raw_writel(value, clk->enable_reg);
248 /* Rebiuld the frequency table */
249 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
250 table, &clk->arch_flags);
255 static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate)
257 struct clk_div4_table *d4t = clk->priv;
259 int idx = clk_rate_table_find(clk, clk->freq_table, rate);
263 value = __raw_readl(clk->enable_reg);
264 value &= ~(0xf << clk->enable_bit);
265 value |= (idx << clk->enable_bit);
266 __raw_writel(value, clk->enable_reg);
274 static int sh_clk_div4_enable(struct clk *clk)
276 __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << 8), clk->enable_reg);
280 static void sh_clk_div4_disable(struct clk *clk)
282 __raw_writel(__raw_readl(clk->enable_reg) | (1 << 8), clk->enable_reg);
285 static struct clk_ops sh_clk_div4_clk_ops = {
286 .recalc = sh_clk_div4_recalc,
287 .set_rate = sh_clk_div4_set_rate,
288 .round_rate = sh_clk_div_round_rate,
291 static struct clk_ops sh_clk_div4_enable_clk_ops = {
292 .recalc = sh_clk_div4_recalc,
293 .set_rate = sh_clk_div4_set_rate,
294 .round_rate = sh_clk_div_round_rate,
295 .enable = sh_clk_div4_enable,
296 .disable = sh_clk_div4_disable,
299 static struct clk_ops sh_clk_div4_reparent_clk_ops = {
300 .recalc = sh_clk_div4_recalc,
301 .set_rate = sh_clk_div4_set_rate,
302 .round_rate = sh_clk_div_round_rate,
303 .enable = sh_clk_div4_enable,
304 .disable = sh_clk_div4_disable,
305 .set_parent = sh_clk_div4_set_parent,
308 static int __init sh_clk_div4_register_ops(struct clk *clks, int nr,
309 struct clk_div4_table *table, struct clk_ops *ops)
313 int nr_divs = table->div_mult_table->nr_divisors;
314 int freq_table_size = sizeof(struct cpufreq_frequency_table);
318 freq_table_size *= (nr_divs + 1);
319 freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
321 pr_err("sh_clk_div4_register: unable to alloc memory\n");
325 for (k = 0; !ret && (k < nr); k++) {
331 clkp->freq_table = freq_table + (k * freq_table_size);
332 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
334 ret = clk_register(clkp);
340 int __init sh_clk_div4_register(struct clk *clks, int nr,
341 struct clk_div4_table *table)
343 return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_clk_ops);
346 int __init sh_clk_div4_enable_register(struct clk *clks, int nr,
347 struct clk_div4_table *table)
349 return sh_clk_div4_register_ops(clks, nr, table,
350 &sh_clk_div4_enable_clk_ops);
353 int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
354 struct clk_div4_table *table)
356 return sh_clk_div4_register_ops(clks, nr, table,
357 &sh_clk_div4_reparent_clk_ops);