drivers/scsi/ufs/ufshcd.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Universal Flash Storage Host controller driver Core
   4  * Copyright (C) 2011-2013 Samsung India Software Operations
   5  * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
   6  *
   7  * Authors:
   8  *      Santosh Yaraganavi <santosh.sy@samsung.com>
   9  *      Vinayak Holikatti <h.vinayak@samsung.com>
  10  */
  11
  12 #include <linux/async.h>
  13 #include <linux/devfreq.h>
  14 #include <linux/nls.h>
  15 #include <linux/of.h>
  16 #include <linux/bitfield.h>
  17 #include <linux/blk-pm.h>
  18 #include <linux/blkdev.h>
  19 #include <scsi/scsi_driver.h>
  20 #include <scsi/scsi_transport.h>
  21 #include "../scsi_transport_api.h"
  22 #include "ufshcd.h"
  23 #include "ufs_quirks.h"
  24 #include "unipro.h"
  25 #include "ufs-sysfs.h"
  26 #include "ufs-debugfs.h"
  27 #include "ufs-fault-injection.h"
  28 #include "ufs_bsg.h"
  29 #include "ufshcd-crypto.h"
  30 #include "ufshpb.h"
  31 #include <asm/unaligned.h>
  32
  33 #define CREATE_TRACE_POINTS
  34 #include <trace/events/ufs.h>
  35
  36 #define UFSHCD_ENABLE_INTRS     (UTP_TRANSFER_REQ_COMPL |\
  37                                  UTP_TASK_REQ_COMPL |\
  38                                  UFSHCD_ERROR_MASK)
  39 /* UIC command timeout, unit: ms */
  40 #define UIC_CMD_TIMEOUT 500
  41
  42 /* NOP OUT retries waiting for NOP IN response */
  43 #define NOP_OUT_RETRIES    10
  44 /* Timeout after 50 msecs if NOP OUT hangs without response */
  45 #define NOP_OUT_TIMEOUT    50 /* msecs */
  46
  47 /* Query request retries */
  48 #define QUERY_REQ_RETRIES 3
  49 /* Query request timeout */
  50 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
  51
  52 /* Task management command timeout */
  53 #define TM_CMD_TIMEOUT  100 /* msecs */
  54
  55 /* maximum number of retries for a general UIC command  */
  56 #define UFS_UIC_COMMAND_RETRIES 3
  57
  58 /* maximum number of link-startup retries */
  59 #define DME_LINKSTARTUP_RETRIES 3
  60
  61 /* Maximum retries for Hibern8 enter */
  62 #define UIC_HIBERN8_ENTER_RETRIES 3
  63
  64 /* maximum number of reset retries before giving up */
  65 #define MAX_HOST_RESET_RETRIES 5
  66
  67 /* Expose the flag value from utp_upiu_query.value */
  68 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
  69
  70 /* Interrupt aggregation default timeout, unit: 40us */
  71 #define INT_AGGR_DEF_TO 0x02
  72
  73 /* default delay of autosuspend: 2000 ms */
  74 #define RPM_AUTOSUSPEND_DELAY_MS 2000
  75
  76 /* Default delay of RPM device flush delayed work */
  77 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000
  78
  79 /* Default value of wait time before gating device ref clock */
  80 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */
  81
  82 /* Polling time to wait for fDeviceInit */
  83 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */
  84
  85 #define wlun_dev_to_hba(dv) shost_priv(to_scsi_device(dv)->host)
  86
  87 #define ufshcd_toggle_vreg(_dev, _vreg, _on)                            \
  88         ({                                                              \
  89                 int _ret;                                               \
  90                 if (_on)                                                \
  91                         _ret = ufshcd_enable_vreg(_dev, _vreg);         \
  92                 else                                                    \
  93                         _ret = ufshcd_disable_vreg(_dev, _vreg);        \
  94                 _ret;                                                   \
  95         })
  96
  97 #define ufshcd_hex_dump(prefix_str, buf, len) do {                       \
  98         size_t __len = (len);                                            \
  99         print_hex_dump(KERN_ERR, prefix_str,                             \
 100                        __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
 101                        16, 4, buf, __len, false);                        \
 102 } while (0)
 103
 104 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
 105                      const char *prefix)
 106 {
 107         u32 *regs;
 108         size_t pos;
 109
 110         if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
 111                 return -EINVAL;
 112
 113         regs = kzalloc(len, GFP_ATOMIC);
 114         if (!regs)
 115                 return -ENOMEM;
 116
 117         for (pos = 0; pos < len; pos += 4)
 118                 regs[pos / 4] = ufshcd_readl(hba, offset + pos);
 119
 120         ufshcd_hex_dump(prefix, regs, len);
 121         kfree(regs);
 122
 123         return 0;
 124 }
 125 EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
 126
 127 enum {
 128         UFSHCD_MAX_CHANNEL      = 0,
 129         UFSHCD_MAX_ID           = 1,
 130         UFSHCD_CMD_PER_LUN      = 32,
 131         UFSHCD_CAN_QUEUE        = 32,
 132 };
 133
 134 /* UFSHCD error handling flags */
 135 enum {
 136         UFSHCD_EH_IN_PROGRESS = (1 << 0),
 137 };
 138
 139 /* UFSHCD UIC layer error flags */
 140 enum {
 141         UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
 142         UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
 143         UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
 144         UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
 145         UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
 146         UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
 147         UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */
 148 };
 149
 150 #define ufshcd_set_eh_in_progress(h) \
 151         ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
 152 #define ufshcd_eh_in_progress(h) \
 153         ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
 154 #define ufshcd_clear_eh_in_progress(h) \
 155         ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
 156
 157 struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
 158         [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
 159         [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
 160         [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
 161         [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
 162         [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
 163         [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
 164         /*
 165          * For DeepSleep, the link is first put in hibern8 and then off.
 166          * Leaving the link in hibern8 is not supported.
 167          */
 168         [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE},
 169 };
 170
 171 static inline enum ufs_dev_pwr_mode
 172 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
 173 {
 174         return ufs_pm_lvl_states[lvl].dev_state;
 175 }
 176
 177 static inline enum uic_link_state
 178 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
 179 {
 180         return ufs_pm_lvl_states[lvl].link_state;
 181 }
 182
 183 static inline enum ufs_pm_level
 184 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
 185                                         enum uic_link_state link_state)
 186 {
 187         enum ufs_pm_level lvl;
 188
 189         for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
 190                 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
 191                         (ufs_pm_lvl_states[lvl].link_state == link_state))
 192                         return lvl;
 193         }
 194
 195         /* if no match found, return the level 0 */
 196         return UFS_PM_LVL_0;
 197 }
 198
 199 static struct ufs_dev_fix ufs_fixups[] = {
 200         /* UFS cards deviations table */
 201         UFS_FIX(UFS_VENDOR_MICRON, UFS_ANY_MODEL,
 202                 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
 203         UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
 204                 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
 205                 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE |
 206                 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
 207         UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
 208                 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
 209         UFS_FIX(UFS_VENDOR_SKHYNIX, "hB8aL1" /*H28U62301AMR*/,
 210                 UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME),
 211         UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
 212                 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
 213         UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
 214                 UFS_DEVICE_QUIRK_PA_TACTIVATE),
 215         UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
 216                 UFS_DEVICE_QUIRK_PA_TACTIVATE),
 217         END_FIX
 218 };
 219
 220 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
 221 static void ufshcd_async_scan(void *data, async_cookie_t cookie);
 222 static int ufshcd_reset_and_restore(struct ufs_hba *hba);
 223 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
 224 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
 225 static void ufshcd_hba_exit(struct ufs_hba *hba);
 226 static int ufshcd_clear_ua_wluns(struct ufs_hba *hba);
 227 static int ufshcd_probe_hba(struct ufs_hba *hba, bool async);
 228 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
 229 static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
 230 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
 231 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
 232 static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
 233 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
 234 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
 235 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
 236 static irqreturn_t ufshcd_intr(int irq, void *__hba);
 237 static int ufshcd_change_power_mode(struct ufs_hba *hba,
 238                              struct ufs_pa_layer_attr *pwr_mode);
 239 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on);
 240 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on);
 241 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
 242                                          struct ufs_vreg *vreg);
 243 static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag);
 244 static void ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set);
 245 static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable);
 246 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba);
 247 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba);
 248
 249 static inline void ufshcd_enable_irq(struct ufs_hba *hba)
 250 {
 251         if (!hba->is_irq_enabled) {
 252                 enable_irq(hba->irq);
 253                 hba->is_irq_enabled = true;
 254         }
 255 }
 256
 257 static inline void ufshcd_disable_irq(struct ufs_hba *hba)
 258 {
 259         if (hba->is_irq_enabled) {
 260                 disable_irq(hba->irq);
 261                 hba->is_irq_enabled = false;
 262         }
 263 }
 264
 265 static inline void ufshcd_wb_config(struct ufs_hba *hba)
 266 {
 267         if (!ufshcd_is_wb_allowed(hba))
 268                 return;
 269
 270         ufshcd_wb_toggle(hba, true);
 271
 272         ufshcd_wb_toggle_flush_during_h8(hba, true);
 273         if (!(hba->quirks & UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL))
 274                 ufshcd_wb_toggle_flush(hba, true);
 275 }
 276
 277 static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
 278 {
 279         if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
 280                 scsi_unblock_requests(hba->host);
 281 }
 282
 283 static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
 284 {
 285         if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
 286                 scsi_block_requests(hba->host);
 287 }
 288
 289 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
 290                                       enum ufs_trace_str_t str_t)
 291 {
 292         struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
 293         struct utp_upiu_header *header;
 294
 295         if (!trace_ufshcd_upiu_enabled())
 296                 return;
 297
 298         if (str_t == UFS_CMD_SEND)
 299                 header = &rq->header;
 300         else
 301                 header = &hba->lrb[tag].ucd_rsp_ptr->header;
 302
 303         trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb,
 304                           UFS_TSF_CDB);
 305 }
 306
 307 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba,
 308                                         enum ufs_trace_str_t str_t,
 309                                         struct utp_upiu_req *rq_rsp)
 310 {
 311         if (!trace_ufshcd_upiu_enabled())
 312                 return;
 313
 314         trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header,
 315                           &rq_rsp->qr, UFS_TSF_OSF);
 316 }
 317
 318 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
 319                                      enum ufs_trace_str_t str_t)
 320 {
 321         int off = (int)tag - hba->nutrs;
 322         struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[off];
 323
 324         if (!trace_ufshcd_upiu_enabled())
 325                 return;
 326
 327         if (str_t == UFS_TM_SEND)
 328                 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
 329                                   &descp->upiu_req.req_header,
 330                                   &descp->upiu_req.input_param1,
 331                                   UFS_TSF_TM_INPUT);
 332         else
 333                 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
 334                                   &descp->upiu_rsp.rsp_header,
 335                                   &descp->upiu_rsp.output_param1,
 336                                   UFS_TSF_TM_OUTPUT);
 337 }
 338
 339 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba,
 340                                          struct uic_command *ucmd,
 341                                          enum ufs_trace_str_t str_t)
 342 {
 343         u32 cmd;
 344
 345         if (!trace_ufshcd_uic_command_enabled())
 346                 return;
 347
 348         if (str_t == UFS_CMD_SEND)
 349                 cmd = ucmd->command;
 350         else
 351                 cmd = ufshcd_readl(hba, REG_UIC_COMMAND);
 352
 353         trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd,
 354                                  ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1),
 355                                  ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2),
 356                                  ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3));
 357 }
 358
 359 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag,
 360                                      enum ufs_trace_str_t str_t)
 361 {
 362         u64 lba = -1;
 363         u8 opcode = 0, group_id = 0;
 364         u32 intr, doorbell;
 365         struct ufshcd_lrb *lrbp = &hba->lrb[tag];
 366         struct scsi_cmnd *cmd = lrbp->cmd;
 367         int transfer_len = -1;
 368
 369         if (!cmd)
 370                 return;
 371
 372         /* trace UPIU also */
 373         ufshcd_add_cmd_upiu_trace(hba, tag, str_t);
 374         if (!trace_ufshcd_command_enabled())
 375                 return;
 376
 377         opcode = cmd->cmnd[0];
 378         lba = scsi_get_lba(cmd);
 379
 380         if (opcode == READ_10 || opcode == WRITE_10) {
 381                 /*
 382                  * Currently we only fully trace read(10) and write(10) commands
 383                  */
 384                 transfer_len =
 385                        be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
 386                 if (opcode == WRITE_10)
 387                         group_id = lrbp->cmd->cmnd[6];
 388         } else if (opcode == UNMAP) {
 389                 /*
 390                  * The number of Bytes to be unmapped beginning with the lba.
 391                  */
 392                 transfer_len = blk_rq_bytes(cmd->request);
 393         }
 394
 395         intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
 396         doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
 397         trace_ufshcd_command(dev_name(hba->dev), str_t, tag,
 398                         doorbell, transfer_len, intr, lba, opcode, group_id);
 399 }
 400
 401 static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
 402 {
 403         struct ufs_clk_info *clki;
 404         struct list_head *head = &hba->clk_list_head;
 405
 406         if (list_empty(head))
 407                 return;
 408
 409         list_for_each_entry(clki, head, list) {
 410                 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
 411                                 clki->max_freq)
 412                         dev_err(hba->dev, "clk: %s, rate: %u\n",
 413                                         clki->name, clki->curr_freq);
 414         }
 415 }
 416
 417 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id,
 418                              char *err_name)
 419 {
 420         int i;
 421         bool found = false;
 422         struct ufs_event_hist *e;
 423
 424         if (id >= UFS_EVT_CNT)
 425                 return;
 426
 427         e = &hba->ufs_stats.event[id];
 428
 429         for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) {
 430                 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH;
 431
 432                 if (e->tstamp[p] == 0)
 433                         continue;
 434                 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
 435                         e->val[p], ktime_to_us(e->tstamp[p]));
 436                 found = true;
 437         }
 438
 439         if (!found)
 440                 dev_err(hba->dev, "No record of %s\n", err_name);
 441         else
 442                 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt);
 443 }
 444
 445 static void ufshcd_print_evt_hist(struct ufs_hba *hba)
 446 {
 447         ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
 448
 449         ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err");
 450         ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err");
 451         ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err");
 452         ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err");
 453         ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err");
 454         ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR,
 455                          "auto_hibern8_err");
 456         ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err");
 457         ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL,
 458                          "link_startup_fail");
 459         ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail");
 460         ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR,
 461                          "suspend_fail");
 462         ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset");
 463         ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset");
 464         ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort");
 465
 466         ufshcd_vops_dbg_register_dump(hba);
 467 }
 468
 469 static
 470 void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
 471 {
 472         struct ufshcd_lrb *lrbp;
 473         int prdt_length;
 474         int tag;
 475
 476         for_each_set_bit(tag, &bitmap, hba->nutrs) {
 477                 lrbp = &hba->lrb[tag];
 478
 479                 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
 480                                 tag, ktime_to_us(lrbp->issue_time_stamp));
 481                 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
 482                                 tag, ktime_to_us(lrbp->compl_time_stamp));
 483                 dev_err(hba->dev,
 484                         "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
 485                         tag, (u64)lrbp->utrd_dma_addr);
 486
 487                 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
 488                                 sizeof(struct utp_transfer_req_desc));
 489                 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
 490                         (u64)lrbp->ucd_req_dma_addr);
 491                 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
 492                                 sizeof(struct utp_upiu_req));
 493                 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
 494                         (u64)lrbp->ucd_rsp_dma_addr);
 495                 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
 496                                 sizeof(struct utp_upiu_rsp));
 497
 498                 prdt_length = le16_to_cpu(
 499                         lrbp->utr_descriptor_ptr->prd_table_length);
 500                 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
 501                         prdt_length /= sizeof(struct ufshcd_sg_entry);
 502
 503                 dev_err(hba->dev,
 504                         "UPIU[%d] - PRDT - %d entries  phys@0x%llx\n",
 505                         tag, prdt_length,
 506                         (u64)lrbp->ucd_prdt_dma_addr);
 507
 508                 if (pr_prdt)
 509                         ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
 510                                 sizeof(struct ufshcd_sg_entry) * prdt_length);
 511         }
 512 }
 513
 514 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
 515 {
 516         int tag;
 517
 518         for_each_set_bit(tag, &bitmap, hba->nutmrs) {
 519                 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
 520
 521                 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
 522                 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
 523         }
 524 }
 525
 526 static void ufshcd_print_host_state(struct ufs_hba *hba)
 527 {
 528         struct scsi_device *sdev_ufs = hba->sdev_ufs_device;
 529
 530         dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
 531         dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n",
 532                 hba->outstanding_reqs, hba->outstanding_tasks);
 533         dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
 534                 hba->saved_err, hba->saved_uic_err);
 535         dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
 536                 hba->curr_dev_pwr_mode, hba->uic_link_state);
 537         dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
 538                 hba->pm_op_in_progress, hba->is_sys_suspended);
 539         dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
 540                 hba->auto_bkops_enabled, hba->host->host_self_blocked);
 541         dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
 542         dev_err(hba->dev,
 543                 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n",
 544                 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
 545                 hba->ufs_stats.hibern8_exit_cnt);
 546         dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n",
 547                 ktime_to_us(hba->ufs_stats.last_intr_ts),
 548                 hba->ufs_stats.last_intr_status);
 549         dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
 550                 hba->eh_flags, hba->req_abort_count);
 551         dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n",
 552                 hba->ufs_version, hba->capabilities, hba->caps);
 553         dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
 554                 hba->dev_quirks);
 555         if (sdev_ufs)
 556                 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n",
 557                         sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev);
 558
 559         ufshcd_print_clk_freqs(hba);
 560 }
 561
 562 /**
 563  * ufshcd_print_pwr_info - print power params as saved in hba
 564  * power info
 565  * @hba: per-adapter instance
 566  */
 567 static void ufshcd_print_pwr_info(struct ufs_hba *hba)
 568 {
 569         static const char * const names[] = {
 570                 "INVALID MODE",
 571                 "FAST MODE",
 572                 "SLOW_MODE",
 573                 "INVALID MODE",
 574                 "FASTAUTO_MODE",
 575                 "SLOWAUTO_MODE",
 576                 "INVALID MODE",
 577         };
 578
 579         dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
 580                  __func__,
 581                  hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
 582                  hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
 583                  names[hba->pwr_info.pwr_rx],
 584                  names[hba->pwr_info.pwr_tx],
 585                  hba->pwr_info.hs_rate);
 586 }
 587
 588 static void ufshcd_device_reset(struct ufs_hba *hba)
 589 {
 590         int err;
 591
 592         err = ufshcd_vops_device_reset(hba);
 593
 594         if (!err) {
 595                 ufshcd_set_ufs_dev_active(hba);
 596                 if (ufshcd_is_wb_allowed(hba)) {
 597                         hba->dev_info.wb_enabled = false;
 598                         hba->dev_info.wb_buf_flush_enabled = false;
 599                 }
 600         }
 601         if (err != -EOPNOTSUPP)
 602                 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err);
 603 }
 604
 605 void ufshcd_delay_us(unsigned long us, unsigned long tolerance)
 606 {
 607         if (!us)
 608                 return;
 609
 610         if (us < 10)
 611                 udelay(us);
 612         else
 613                 usleep_range(us, us + tolerance);
 614 }
 615 EXPORT_SYMBOL_GPL(ufshcd_delay_us);
 616
 617 /**
 618  * ufshcd_wait_for_register - wait for register value to change
 619  * @hba: per-adapter interface
 620  * @reg: mmio register offset
 621  * @mask: mask to apply to the read register value
 622  * @val: value to wait for
 623  * @interval_us: polling interval in microseconds
 624  * @timeout_ms: timeout in milliseconds
 625  *
 626  * Return:
 627  * -ETIMEDOUT on error, zero on success.
 628  */
 629 int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
 630                                 u32 val, unsigned long interval_us,
 631                                 unsigned long timeout_ms)
 632 {
 633         int err = 0;
 634         unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
 635
 636         /* ignore bits that we don't intend to wait on */
 637         val = val & mask;
 638
 639         while ((ufshcd_readl(hba, reg) & mask) != val) {
 640                 usleep_range(interval_us, interval_us + 50);
 641                 if (time_after(jiffies, timeout)) {
 642                         if ((ufshcd_readl(hba, reg) & mask) != val)
 643                                 err = -ETIMEDOUT;
 644                         break;
 645                 }
 646         }
 647
 648         return err;
 649 }
 650
 651 /**
 652  * ufshcd_get_intr_mask - Get the interrupt bit mask
 653  * @hba: Pointer to adapter instance
 654  *
 655  * Returns interrupt bit mask per version
 656  */
 657 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
 658 {
 659         if (hba->ufs_version == ufshci_version(1, 0))
 660                 return INTERRUPT_MASK_ALL_VER_10;
 661         if (hba->ufs_version <= ufshci_version(2, 0))
 662                 return INTERRUPT_MASK_ALL_VER_11;
 663
 664         return INTERRUPT_MASK_ALL_VER_21;
 665 }
 666
 667 /**
 668  * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
 669  * @hba: Pointer to adapter instance
 670  *
 671  * Returns UFSHCI version supported by the controller
 672  */
 673 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
 674 {
 675         u32 ufshci_ver;
 676
 677         if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
 678                 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba);
 679         else
 680                 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION);
 681
 682         /*
 683          * UFSHCI v1.x uses a different version scheme, in order
 684          * to allow the use of comparisons with the ufshci_version
 685          * function, we convert it to the same scheme as ufs 2.0+.
 686          */
 687         if (ufshci_ver & 0x00010000)
 688                 return ufshci_version(1, ufshci_ver & 0x00000100);
 689
 690         return ufshci_ver;
 691 }
 692
 693 /**
 694  * ufshcd_is_device_present - Check if any device connected to
 695  *                            the host controller
 696  * @hba: pointer to adapter instance
 697  *
 698  * Returns true if device present, false if no device detected
 699  */
 700 static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
 701 {
 702         return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
 703                                                 DEVICE_PRESENT) ? true : false;
 704 }
 705
 706 /**
 707  * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
 708  * @lrbp: pointer to local command reference block
 709  *
 710  * This function is used to get the OCS field from UTRD
 711  * Returns the OCS field in the UTRD
 712  */
 713 static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
 714 {
 715         return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
 716 }
 717
 718 /**
 719  * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
 720  * @hba: per adapter instance
 721  * @pos: position of the bit to be cleared
 722  */
 723 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
 724 {
 725         if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
 726                 ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
 727         else
 728                 ufshcd_writel(hba, ~(1 << pos),
 729                                 REG_UTP_TRANSFER_REQ_LIST_CLEAR);
 730 }
 731
 732 /**
 733  * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
 734  * @hba: per adapter instance
 735  * @pos: position of the bit to be cleared
 736  */
 737 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
 738 {
 739         if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
 740                 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
 741         else
 742                 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
 743 }
 744
 745 /**
 746  * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
 747  * @reg: Register value of host controller status
 748  *
 749  * Returns integer, 0 on Success and positive value if failed
 750  */
 751 static inline int ufshcd_get_lists_status(u32 reg)
 752 {
 753         return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
 754 }
 755
 756 /**
 757  * ufshcd_get_uic_cmd_result - Get the UIC command result
 758  * @hba: Pointer to adapter instance
 759  *
 760  * This function gets the result of UIC command completion
 761  * Returns 0 on success, non zero value on error
 762  */
 763 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
 764 {
 765         return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
 766                MASK_UIC_COMMAND_RESULT;
 767 }
 768
 769 /**
 770  * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
 771  * @hba: Pointer to adapter instance
 772  *
 773  * This function gets UIC command argument3
 774  * Returns 0 on success, non zero value on error
 775  */
 776 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
 777 {
 778         return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
 779 }
 780
 781 /**
 782  * ufshcd_get_req_rsp - returns the TR response transaction type
 783  * @ucd_rsp_ptr: pointer to response UPIU
 784  */
 785 static inline int
 786 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
 787 {
 788         return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
 789 }
 790
 791 /**
 792  * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
 793  * @ucd_rsp_ptr: pointer to response UPIU
 794  *
 795  * This function gets the response status and scsi_status from response UPIU
 796  * Returns the response result code.
 797  */
 798 static inline int
 799 ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
 800 {
 801         return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
 802 }
 803
 804 /*
 805  * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
 806  *                              from response UPIU
 807  * @ucd_rsp_ptr: pointer to response UPIU
 808  *
 809  * Return the data segment length.
 810  */
 811 static inline unsigned int
 812 ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
 813 {
 814         return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
 815                 MASK_RSP_UPIU_DATA_SEG_LEN;
 816 }
 817
 818 /**
 819  * ufshcd_is_exception_event - Check if the device raised an exception event
 820  * @ucd_rsp_ptr: pointer to response UPIU
 821  *
 822  * The function checks if the device raised an exception event indicated in
 823  * the Device Information field of response UPIU.
 824  *
 825  * Returns true if exception is raised, false otherwise.
 826  */
 827 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
 828 {
 829         return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
 830                         MASK_RSP_EXCEPTION_EVENT ? true : false;
 831 }
 832
 833 /**
 834  * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
 835  * @hba: per adapter instance
 836  */
 837 static inline void
 838 ufshcd_reset_intr_aggr(struct ufs_hba *hba)
 839 {
 840         ufshcd_writel(hba, INT_AGGR_ENABLE |
 841                       INT_AGGR_COUNTER_AND_TIMER_RESET,
 842                       REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
 843 }
 844
 845 /**
 846  * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
 847  * @hba: per adapter instance
 848  * @cnt: Interrupt aggregation counter threshold
 849  * @tmout: Interrupt aggregation timeout value
 850  */
 851 static inline void
 852 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
 853 {
 854         ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
 855                       INT_AGGR_COUNTER_THLD_VAL(cnt) |
 856                       INT_AGGR_TIMEOUT_VAL(tmout),
 857                       REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
 858 }
 859
 860 /**
 861  * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
 862  * @hba: per adapter instance
 863  */
 864 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
 865 {
 866         ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
 867 }
 868
 869 /**
 870  * ufshcd_enable_run_stop_reg - Enable run-stop registers,
 871  *                      When run-stop registers are set to 1, it indicates the
 872  *                      host controller that it can process the requests
 873  * @hba: per adapter instance
 874  */
 875 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
 876 {
 877         ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
 878                       REG_UTP_TASK_REQ_LIST_RUN_STOP);
 879         ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
 880                       REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
 881 }
 882
 883 /**
 884  * ufshcd_hba_start - Start controller initialization sequence
 885  * @hba: per adapter instance
 886  */
 887 static inline void ufshcd_hba_start(struct ufs_hba *hba)
 888 {
 889         u32 val = CONTROLLER_ENABLE;
 890
 891         if (ufshcd_crypto_enable(hba))
 892                 val |= CRYPTO_GENERAL_ENABLE;
 893
 894         ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
 895 }
 896
 897 /**
 898  * ufshcd_is_hba_active - Get controller state
 899  * @hba: per adapter instance
 900  *
 901  * Returns false if controller is active, true otherwise
 902  */
 903 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
 904 {
 905         return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
 906                 ? false : true;
 907 }
 908
 909 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
 910 {
 911         /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
 912         if (hba->ufs_version <= ufshci_version(1, 1))
 913                 return UFS_UNIPRO_VER_1_41;
 914         else
 915                 return UFS_UNIPRO_VER_1_6;
 916 }
 917 EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
 918
 919 static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
 920 {
 921         /*
 922          * If both host and device support UniPro ver1.6 or later, PA layer
 923          * parameters tuning happens during link startup itself.
 924          *
 925          * We can manually tune PA layer parameters if either host or device
 926          * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
 927          * logic simple, we will only do manual tuning if local unipro version
 928          * doesn't support ver1.6 or later.
 929          */
 930         if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
 931                 return true;
 932         else
 933                 return false;
 934 }
 935
 936 /**
 937  * ufshcd_set_clk_freq - set UFS controller clock frequencies
 938  * @hba: per adapter instance
 939  * @scale_up: If True, set max possible frequency othewise set low frequency
 940  *
 941  * Returns 0 if successful
 942  * Returns < 0 for any other errors
 943  */
 944 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
 945 {
 946         int ret = 0;
 947         struct ufs_clk_info *clki;
 948         struct list_head *head = &hba->clk_list_head;
 949
 950         if (list_empty(head))
 951                 goto out;
 952
 953         list_for_each_entry(clki, head, list) {
 954                 if (!IS_ERR_OR_NULL(clki->clk)) {
 955                         if (scale_up && clki->max_freq) {
 956                                 if (clki->curr_freq == clki->max_freq)
 957                                         continue;
 958
 959                                 ret = clk_set_rate(clki->clk, clki->max_freq);
 960                                 if (ret) {
 961                                         dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
 962                                                 __func__, clki->name,
 963                                                 clki->max_freq, ret);
 964                                         break;
 965                                 }
 966                                 trace_ufshcd_clk_scaling(dev_name(hba->dev),
 967                                                 "scaled up", clki->name,
 968                                                 clki->curr_freq,
 969                                                 clki->max_freq);
 970
 971                                 clki->curr_freq = clki->max_freq;
 972
 973                         } else if (!scale_up && clki->min_freq) {
 974                                 if (clki->curr_freq == clki->min_freq)
 975                                         continue;
 976
 977                                 ret = clk_set_rate(clki->clk, clki->min_freq);
 978                                 if (ret) {
 979                                         dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
 980                                                 __func__, clki->name,
 981                                                 clki->min_freq, ret);
 982                                         break;
 983                                 }
 984                                 trace_ufshcd_clk_scaling(dev_name(hba->dev),
 985                                                 "scaled down", clki->name,
 986                                                 clki->curr_freq,
 987                                                 clki->min_freq);
 988                                 clki->curr_freq = clki->min_freq;
 989                         }
 990                 }
 991                 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
 992                                 clki->name, clk_get_rate(clki->clk));
 993         }
 994
 995 out:
 996         return ret;
 997 }
 998
 999 /**
1000  * ufshcd_scale_clks - scale up or scale down UFS controller clocks
1001  * @hba: per adapter instance
1002  * @scale_up: True if scaling up and false if scaling down
1003  *
1004  * Returns 0 if successful
1005  * Returns < 0 for any other errors
1006  */
1007 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
1008 {
1009         int ret = 0;
1010         ktime_t start = ktime_get();
1011
1012         ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
1013         if (ret)
1014                 goto out;
1015
1016         ret = ufshcd_set_clk_freq(hba, scale_up);
1017         if (ret)
1018                 goto out;
1019
1020         ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1021         if (ret)
1022                 ufshcd_set_clk_freq(hba, !scale_up);
1023
1024 out:
1025         trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1026                         (scale_up ? "up" : "down"),
1027                         ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1028         return ret;
1029 }
1030
1031 /**
1032  * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
1033  * @hba: per adapter instance
1034  * @scale_up: True if scaling up and false if scaling down
1035  *
1036  * Returns true if scaling is required, false otherwise.
1037  */
1038 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
1039                                                bool scale_up)
1040 {
1041         struct ufs_clk_info *clki;
1042         struct list_head *head = &hba->clk_list_head;
1043
1044         if (list_empty(head))
1045                 return false;
1046
1047         list_for_each_entry(clki, head, list) {
1048                 if (!IS_ERR_OR_NULL(clki->clk)) {
1049                         if (scale_up && clki->max_freq) {
1050                                 if (clki->curr_freq == clki->max_freq)
1051                                         continue;
1052                                 return true;
1053                         } else if (!scale_up && clki->min_freq) {
1054                                 if (clki->curr_freq == clki->min_freq)
1055                                         continue;
1056                                 return true;
1057                         }
1058                 }
1059         }
1060
1061         return false;
1062 }
1063
1064 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1065                                         u64 wait_timeout_us)
1066 {
1067         unsigned long flags;
1068         int ret = 0;
1069         u32 tm_doorbell;
1070         u32 tr_doorbell;
1071         bool timeout = false, do_last_check = false;
1072         ktime_t start;
1073
1074         ufshcd_hold(hba, false);
1075         spin_lock_irqsave(hba->host->host_lock, flags);
1076         /*
1077          * Wait for all the outstanding tasks/transfer requests.
1078          * Verify by checking the doorbell registers are clear.
1079          */
1080         start = ktime_get();
1081         do {
1082                 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1083                         ret = -EBUSY;
1084                         goto out;
1085                 }
1086
1087                 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1088                 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1089                 if (!tm_doorbell && !tr_doorbell) {
1090                         timeout = false;
1091                         break;
1092                 } else if (do_last_check) {
1093                         break;
1094                 }
1095
1096                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1097                 schedule();
1098                 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1099                     wait_timeout_us) {
1100                         timeout = true;
1101                         /*
1102                          * We might have scheduled out for long time so make
1103                          * sure to check if doorbells are cleared by this time
1104                          * or not.
1105                          */
1106                         do_last_check = true;
1107                 }
1108                 spin_lock_irqsave(hba->host->host_lock, flags);
1109         } while (tm_doorbell || tr_doorbell);
1110
1111         if (timeout) {
1112                 dev_err(hba->dev,
1113                         "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1114                         __func__, tm_doorbell, tr_doorbell);
1115                 ret = -EBUSY;
1116         }
1117 out:
1118         spin_unlock_irqrestore(hba->host->host_lock, flags);
1119         ufshcd_release(hba);
1120         return ret;
1121 }
1122
1123 /**
1124  * ufshcd_scale_gear - scale up/down UFS gear
1125  * @hba: per adapter instance
1126  * @scale_up: True for scaling up gear and false for scaling down
1127  *
1128  * Returns 0 for success,
1129  * Returns -EBUSY if scaling can't happen at this time
1130  * Returns non-zero for any other errors
1131  */
1132 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1133 {
1134         int ret = 0;
1135         struct ufs_pa_layer_attr new_pwr_info;
1136
1137         if (scale_up) {
1138                 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1139                        sizeof(struct ufs_pa_layer_attr));
1140         } else {
1141                 memcpy(&new_pwr_info, &hba->pwr_info,
1142                        sizeof(struct ufs_pa_layer_attr));
1143
1144                 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear ||
1145                     hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) {
1146                         /* save the current power mode */
1147                         memcpy(&hba->clk_scaling.saved_pwr_info.info,
1148                                 &hba->pwr_info,
1149                                 sizeof(struct ufs_pa_layer_attr));
1150
1151                         /* scale down gear */
1152                         new_pwr_info.gear_tx = hba->clk_scaling.min_gear;
1153                         new_pwr_info.gear_rx = hba->clk_scaling.min_gear;
1154                 }
1155         }
1156
1157         /* check if the power mode needs to be changed or not? */
1158         ret = ufshcd_config_pwr_mode(hba, &new_pwr_info);
1159         if (ret)
1160                 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1161                         __func__, ret,
1162                         hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1163                         new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1164
1165         return ret;
1166 }
1167
1168 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1169 {
1170         #define DOORBELL_CLR_TOUT_US            (1000 * 1000) /* 1 sec */
1171         int ret = 0;
1172         /*
1173          * make sure that there are no outstanding requests when
1174          * clock scaling is in progress
1175          */
1176         ufshcd_scsi_block_requests(hba);
1177         down_write(&hba->clk_scaling_lock);
1178
1179         if (!hba->clk_scaling.is_allowed ||
1180             ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1181                 ret = -EBUSY;
1182                 up_write(&hba->clk_scaling_lock);
1183                 ufshcd_scsi_unblock_requests(hba);
1184                 goto out;
1185         }
1186
1187         /* let's not get into low power until clock scaling is completed */
1188         ufshcd_hold(hba, false);
1189
1190 out:
1191         return ret;
1192 }
1193
1194 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, bool writelock)
1195 {
1196         if (writelock)
1197                 up_write(&hba->clk_scaling_lock);
1198         else
1199                 up_read(&hba->clk_scaling_lock);
1200         ufshcd_scsi_unblock_requests(hba);
1201         ufshcd_release(hba);
1202 }
1203
1204 /**
1205  * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1206  * @hba: per adapter instance
1207  * @scale_up: True for scaling up and false for scalin down
1208  *
1209  * Returns 0 for success,
1210  * Returns -EBUSY if scaling can't happen at this time
1211  * Returns non-zero for any other errors
1212  */
1213 static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1214 {
1215         int ret = 0;
1216         bool is_writelock = true;
1217
1218         ret = ufshcd_clock_scaling_prepare(hba);
1219         if (ret)
1220                 return ret;
1221
1222         /* scale down the gear before scaling down clocks */
1223         if (!scale_up) {
1224                 ret = ufshcd_scale_gear(hba, false);
1225                 if (ret)
1226                         goto out_unprepare;
1227         }
1228
1229         ret = ufshcd_scale_clks(hba, scale_up);
1230         if (ret) {
1231                 if (!scale_up)
1232                         ufshcd_scale_gear(hba, true);
1233                 goto out_unprepare;
1234         }
1235
1236         /* scale up the gear after scaling up clocks */
1237         if (scale_up) {
1238                 ret = ufshcd_scale_gear(hba, true);
1239                 if (ret) {
1240                         ufshcd_scale_clks(hba, false);
1241                         goto out_unprepare;
1242                 }
1243         }
1244
1245         /* Enable Write Booster if we have scaled up else disable it */
1246         downgrade_write(&hba->clk_scaling_lock);
1247         is_writelock = false;
1248         ufshcd_wb_toggle(hba, scale_up);
1249
1250 out_unprepare:
1251         ufshcd_clock_scaling_unprepare(hba, is_writelock);
1252         return ret;
1253 }
1254
1255 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1256 {
1257         struct ufs_hba *hba = container_of(work, struct ufs_hba,
1258                                            clk_scaling.suspend_work);
1259         unsigned long irq_flags;
1260
1261         spin_lock_irqsave(hba->host->host_lock, irq_flags);
1262         if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1263                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1264                 return;
1265         }
1266         hba->clk_scaling.is_suspended = true;
1267         spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1268
1269         __ufshcd_suspend_clkscaling(hba);
1270 }
1271
1272 static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1273 {
1274         struct ufs_hba *hba = container_of(work, struct ufs_hba,
1275                                            clk_scaling.resume_work);
1276         unsigned long irq_flags;
1277
1278         spin_lock_irqsave(hba->host->host_lock, irq_flags);
1279         if (!hba->clk_scaling.is_suspended) {
1280                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1281                 return;
1282         }
1283         hba->clk_scaling.is_suspended = false;
1284         spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1285
1286         devfreq_resume_device(hba->devfreq);
1287 }
1288
1289 static int ufshcd_devfreq_target(struct device *dev,
1290                                 unsigned long *freq, u32 flags)
1291 {
1292         int ret = 0;
1293         struct ufs_hba *hba = dev_get_drvdata(dev);
1294         ktime_t start;
1295         bool scale_up, sched_clk_scaling_suspend_work = false;
1296         struct list_head *clk_list = &hba->clk_list_head;
1297         struct ufs_clk_info *clki;
1298         unsigned long irq_flags;
1299
1300         if (!ufshcd_is_clkscaling_supported(hba))
1301                 return -EINVAL;
1302
1303         clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1304         /* Override with the closest supported frequency */
1305         *freq = (unsigned long) clk_round_rate(clki->clk, *freq);
1306         spin_lock_irqsave(hba->host->host_lock, irq_flags);
1307         if (ufshcd_eh_in_progress(hba)) {
1308                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1309                 return 0;
1310         }
1311
1312         if (!hba->clk_scaling.active_reqs)
1313                 sched_clk_scaling_suspend_work = true;
1314
1315         if (list_empty(clk_list)) {
1316                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1317                 goto out;
1318         }
1319
1320         /* Decide based on the rounded-off frequency and update */
1321         scale_up = (*freq == clki->max_freq) ? true : false;
1322         if (!scale_up)
1323                 *freq = clki->min_freq;
1324         /* Update the frequency */
1325         if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1326                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1327                 ret = 0;
1328                 goto out; /* no state change required */
1329         }
1330         spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1331
1332         start = ktime_get();
1333         ret = ufshcd_devfreq_scale(hba, scale_up);
1334
1335         trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1336                 (scale_up ? "up" : "down"),
1337                 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1338
1339 out:
1340         if (sched_clk_scaling_suspend_work)
1341                 queue_work(hba->clk_scaling.workq,
1342                            &hba->clk_scaling.suspend_work);
1343
1344         return ret;
1345 }
1346
1347 static bool ufshcd_is_busy(struct request *req, void *priv, bool reserved)
1348 {
1349         int *busy = priv;
1350
1351         WARN_ON_ONCE(reserved);
1352         (*busy)++;
1353         return false;
1354 }
1355
1356 /* Whether or not any tag is in use by a request that is in progress. */
1357 static bool ufshcd_any_tag_in_use(struct ufs_hba *hba)
1358 {
1359         struct request_queue *q = hba->cmd_queue;
1360         int busy = 0;
1361
1362         blk_mq_tagset_busy_iter(q->tag_set, ufshcd_is_busy, &busy);
1363         return busy;
1364 }
1365
1366 static int ufshcd_devfreq_get_dev_status(struct device *dev,
1367                 struct devfreq_dev_status *stat)
1368 {
1369         struct ufs_hba *hba = dev_get_drvdata(dev);
1370         struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1371         unsigned long flags;
1372         struct list_head *clk_list = &hba->clk_list_head;
1373         struct ufs_clk_info *clki;
1374         ktime_t curr_t;
1375
1376         if (!ufshcd_is_clkscaling_supported(hba))
1377                 return -EINVAL;
1378
1379         memset(stat, 0, sizeof(*stat));
1380
1381         spin_lock_irqsave(hba->host->host_lock, flags);
1382         curr_t = ktime_get();
1383         if (!scaling->window_start_t)
1384                 goto start_window;
1385
1386         clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1387         /*
1388          * If current frequency is 0, then the ondemand governor considers
1389          * there's no initial frequency set. And it always requests to set
1390          * to max. frequency.
1391          */
1392         stat->current_frequency = clki->curr_freq;
1393         if (scaling->is_busy_started)
1394                 scaling->tot_busy_t += ktime_us_delta(curr_t,
1395                                 scaling->busy_start_t);
1396
1397         stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t);
1398         stat->busy_time = scaling->tot_busy_t;
1399 start_window:
1400         scaling->window_start_t = curr_t;
1401         scaling->tot_busy_t = 0;
1402
1403         if (hba->outstanding_reqs) {
1404                 scaling->busy_start_t = curr_t;
1405                 scaling->is_busy_started = true;
1406         } else {
1407                 scaling->busy_start_t = 0;
1408                 scaling->is_busy_started = false;
1409         }
1410         spin_unlock_irqrestore(hba->host->host_lock, flags);
1411         return 0;
1412 }
1413
1414 static int ufshcd_devfreq_init(struct ufs_hba *hba)
1415 {
1416         struct list_head *clk_list = &hba->clk_list_head;
1417         struct ufs_clk_info *clki;
1418         struct devfreq *devfreq;
1419         int ret;
1420
1421         /* Skip devfreq if we don't have any clocks in the list */
1422         if (list_empty(clk_list))
1423                 return 0;
1424
1425         clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1426         dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1427         dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1428
1429         ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile,
1430                                          &hba->vps->ondemand_data);
1431         devfreq = devfreq_add_device(hba->dev,
1432                         &hba->vps->devfreq_profile,
1433                         DEVFREQ_GOV_SIMPLE_ONDEMAND,
1434                         &hba->vps->ondemand_data);
1435         if (IS_ERR(devfreq)) {
1436                 ret = PTR_ERR(devfreq);
1437                 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
1438
1439                 dev_pm_opp_remove(hba->dev, clki->min_freq);
1440                 dev_pm_opp_remove(hba->dev, clki->max_freq);
1441                 return ret;
1442         }
1443
1444         hba->devfreq = devfreq;
1445
1446         return 0;
1447 }
1448
1449 static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1450 {
1451         struct list_head *clk_list = &hba->clk_list_head;
1452         struct ufs_clk_info *clki;
1453
1454         if (!hba->devfreq)
1455                 return;
1456
1457         devfreq_remove_device(hba->devfreq);
1458         hba->devfreq = NULL;
1459
1460         clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1461         dev_pm_opp_remove(hba->dev, clki->min_freq);
1462         dev_pm_opp_remove(hba->dev, clki->max_freq);
1463 }
1464
1465 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1466 {
1467         unsigned long flags;
1468
1469         devfreq_suspend_device(hba->devfreq);
1470         spin_lock_irqsave(hba->host->host_lock, flags);
1471         hba->clk_scaling.window_start_t = 0;
1472         spin_unlock_irqrestore(hba->host->host_lock, flags);
1473 }
1474
1475 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1476 {
1477         unsigned long flags;
1478         bool suspend = false;
1479
1480         cancel_work_sync(&hba->clk_scaling.suspend_work);
1481         cancel_work_sync(&hba->clk_scaling.resume_work);
1482
1483         spin_lock_irqsave(hba->host->host_lock, flags);
1484         if (!hba->clk_scaling.is_suspended) {
1485                 suspend = true;
1486                 hba->clk_scaling.is_suspended = true;
1487         }
1488         spin_unlock_irqrestore(hba->host->host_lock, flags);
1489
1490         if (suspend)
1491                 __ufshcd_suspend_clkscaling(hba);
1492 }
1493
1494 static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1495 {
1496         unsigned long flags;
1497         bool resume = false;
1498
1499         spin_lock_irqsave(hba->host->host_lock, flags);
1500         if (hba->clk_scaling.is_suspended) {
1501                 resume = true;
1502                 hba->clk_scaling.is_suspended = false;
1503         }
1504         spin_unlock_irqrestore(hba->host->host_lock, flags);
1505
1506         if (resume)
1507                 devfreq_resume_device(hba->devfreq);
1508 }
1509
1510 static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1511                 struct device_attribute *attr, char *buf)
1512 {
1513         struct ufs_hba *hba = dev_get_drvdata(dev);
1514
1515         return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled);
1516 }
1517
1518 static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1519                 struct device_attribute *attr, const char *buf, size_t count)
1520 {
1521         struct ufs_hba *hba = dev_get_drvdata(dev);
1522         u32 value;
1523         int err = 0;
1524
1525         if (kstrtou32(buf, 0, &value))
1526                 return -EINVAL;
1527
1528         down(&hba->host_sem);
1529         if (!ufshcd_is_user_access_allowed(hba)) {
1530                 err = -EBUSY;
1531                 goto out;
1532         }
1533
1534         value = !!value;
1535         if (value == hba->clk_scaling.is_enabled)
1536                 goto out;
1537
1538         ufshcd_rpm_get_sync(hba);
1539         ufshcd_hold(hba, false);
1540
1541         hba->clk_scaling.is_enabled = value;
1542
1543         if (value) {
1544                 ufshcd_resume_clkscaling(hba);
1545         } else {
1546                 ufshcd_suspend_clkscaling(hba);
1547                 err = ufshcd_devfreq_scale(hba, true);
1548                 if (err)
1549                         dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1550                                         __func__, err);
1551         }
1552
1553         ufshcd_release(hba);
1554         ufshcd_rpm_put_sync(hba);
1555 out:
1556         up(&hba->host_sem);
1557         return err ? err : count;
1558 }
1559
1560 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba)
1561 {
1562         hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1563         hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1564         sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1565         hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1566         hba->clk_scaling.enable_attr.attr.mode = 0644;
1567         if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1568                 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1569 }
1570
1571 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba)
1572 {
1573         if (hba->clk_scaling.enable_attr.attr.name)
1574                 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
1575 }
1576
1577 static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1578 {
1579         char wq_name[sizeof("ufs_clkscaling_00")];
1580
1581         if (!ufshcd_is_clkscaling_supported(hba))
1582                 return;
1583
1584         if (!hba->clk_scaling.min_gear)
1585                 hba->clk_scaling.min_gear = UFS_HS_G1;
1586
1587         INIT_WORK(&hba->clk_scaling.suspend_work,
1588                   ufshcd_clk_scaling_suspend_work);
1589         INIT_WORK(&hba->clk_scaling.resume_work,
1590                   ufshcd_clk_scaling_resume_work);
1591
1592         snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1593                  hba->host->host_no);
1594         hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1595
1596         hba->clk_scaling.is_initialized = true;
1597 }
1598
1599 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1600 {
1601         if (!hba->clk_scaling.is_initialized)
1602                 return;
1603
1604         ufshcd_remove_clk_scaling_sysfs(hba);
1605         destroy_workqueue(hba->clk_scaling.workq);
1606         ufshcd_devfreq_remove(hba);
1607         hba->clk_scaling.is_initialized = false;
1608 }
1609
1610 static void ufshcd_ungate_work(struct work_struct *work)
1611 {
1612         int ret;
1613         unsigned long flags;
1614         struct ufs_hba *hba = container_of(work, struct ufs_hba,
1615                         clk_gating.ungate_work);
1616
1617         cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1618
1619         spin_lock_irqsave(hba->host->host_lock, flags);
1620         if (hba->clk_gating.state == CLKS_ON) {
1621                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1622                 goto unblock_reqs;
1623         }
1624
1625         spin_unlock_irqrestore(hba->host->host_lock, flags);
1626         ufshcd_hba_vreg_set_hpm(hba);
1627         ufshcd_setup_clocks(hba, true);
1628
1629         ufshcd_enable_irq(hba);
1630
1631         /* Exit from hibern8 */
1632         if (ufshcd_can_hibern8_during_gating(hba)) {
1633                 /* Prevent gating in this path */
1634                 hba->clk_gating.is_suspended = true;
1635                 if (ufshcd_is_link_hibern8(hba)) {
1636                         ret = ufshcd_uic_hibern8_exit(hba);
1637                         if (ret)
1638                                 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1639                                         __func__, ret);
1640                         else
1641                                 ufshcd_set_link_active(hba);
1642                 }
1643                 hba->clk_gating.is_suspended = false;
1644         }
1645 unblock_reqs:
1646         ufshcd_scsi_unblock_requests(hba);
1647 }
1648
1649 /**
1650  * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1651  * Also, exit from hibern8 mode and set the link as active.
1652  * @hba: per adapter instance
1653  * @async: This indicates whether caller should ungate clocks asynchronously.
1654  */
1655 int ufshcd_hold(struct ufs_hba *hba, bool async)
1656 {
1657         int rc = 0;
1658         bool flush_result;
1659         unsigned long flags;
1660
1661         if (!ufshcd_is_clkgating_allowed(hba))
1662                 goto out;
1663         spin_lock_irqsave(hba->host->host_lock, flags);
1664         hba->clk_gating.active_reqs++;
1665
1666 start:
1667         switch (hba->clk_gating.state) {
1668         case CLKS_ON:
1669                 /*
1670                  * Wait for the ungate work to complete if in progress.
1671                  * Though the clocks may be in ON state, the link could
1672                  * still be in hibner8 state if hibern8 is allowed
1673                  * during clock gating.
1674                  * Make sure we exit hibern8 state also in addition to
1675                  * clocks being ON.
1676                  */
1677                 if (ufshcd_can_hibern8_during_gating(hba) &&
1678                     ufshcd_is_link_hibern8(hba)) {
1679                         if (async) {
1680                                 rc = -EAGAIN;
1681                                 hba->clk_gating.active_reqs--;
1682                                 break;
1683                         }
1684                         spin_unlock_irqrestore(hba->host->host_lock, flags);
1685                         flush_result = flush_work(&hba->clk_gating.ungate_work);
1686                         if (hba->clk_gating.is_suspended && !flush_result)
1687                                 goto out;
1688                         spin_lock_irqsave(hba->host->host_lock, flags);
1689                         goto start;
1690                 }
1691                 break;
1692         case REQ_CLKS_OFF:
1693                 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1694                         hba->clk_gating.state = CLKS_ON;
1695                         trace_ufshcd_clk_gating(dev_name(hba->dev),
1696                                                 hba->clk_gating.state);
1697                         break;
1698                 }
1699                 /*
1700                  * If we are here, it means gating work is either done or
1701                  * currently running. Hence, fall through to cancel gating
1702                  * work and to enable clocks.
1703                  */
1704                 fallthrough;
1705         case CLKS_OFF:
1706                 hba->clk_gating.state = REQ_CLKS_ON;
1707                 trace_ufshcd_clk_gating(dev_name(hba->dev),
1708                                         hba->clk_gating.state);
1709                 if (queue_work(hba->clk_gating.clk_gating_workq,
1710                                &hba->clk_gating.ungate_work))
1711                         ufshcd_scsi_block_requests(hba);
1712                 /*
1713                  * fall through to check if we should wait for this
1714                  * work to be done or not.
1715                  */
1716                 fallthrough;
1717         case REQ_CLKS_ON:
1718                 if (async) {
1719                         rc = -EAGAIN;
1720                         hba->clk_gating.active_reqs--;
1721                         break;
1722                 }
1723
1724                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1725                 flush_work(&hba->clk_gating.ungate_work);
1726                 /* Make sure state is CLKS_ON before returning */
1727                 spin_lock_irqsave(hba->host->host_lock, flags);
1728                 goto start;
1729         default:
1730                 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1731                                 __func__, hba->clk_gating.state);
1732                 break;
1733         }
1734         spin_unlock_irqrestore(hba->host->host_lock, flags);
1735 out:
1736         return rc;
1737 }
1738 EXPORT_SYMBOL_GPL(ufshcd_hold);
1739
1740 static void ufshcd_gate_work(struct work_struct *work)
1741 {
1742         struct ufs_hba *hba = container_of(work, struct ufs_hba,
1743                         clk_gating.gate_work.work);
1744         unsigned long flags;
1745         int ret;
1746
1747         spin_lock_irqsave(hba->host->host_lock, flags);
1748         /*
1749          * In case you are here to cancel this work the gating state
1750          * would be marked as REQ_CLKS_ON. In this case save time by
1751          * skipping the gating work and exit after changing the clock
1752          * state to CLKS_ON.
1753          */
1754         if (hba->clk_gating.is_suspended ||
1755                 (hba->clk_gating.state != REQ_CLKS_OFF)) {
1756                 hba->clk_gating.state = CLKS_ON;
1757                 trace_ufshcd_clk_gating(dev_name(hba->dev),
1758                                         hba->clk_gating.state);
1759                 goto rel_lock;
1760         }
1761
1762         if (hba->clk_gating.active_reqs
1763                 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1764                 || ufshcd_any_tag_in_use(hba) || hba->outstanding_tasks
1765                 || hba->active_uic_cmd || hba->uic_async_done)
1766                 goto rel_lock;
1767
1768         spin_unlock_irqrestore(hba->host->host_lock, flags);
1769
1770         /* put the link into hibern8 mode before turning off clocks */
1771         if (ufshcd_can_hibern8_during_gating(hba)) {
1772                 ret = ufshcd_uic_hibern8_enter(hba);
1773                 if (ret) {
1774                         hba->clk_gating.state = CLKS_ON;
1775                         dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
1776                                         __func__, ret);
1777                         trace_ufshcd_clk_gating(dev_name(hba->dev),
1778                                                 hba->clk_gating.state);
1779                         goto out;
1780                 }
1781                 ufshcd_set_link_hibern8(hba);
1782         }
1783
1784         ufshcd_disable_irq(hba);
1785
1786         ufshcd_setup_clocks(hba, false);
1787
1788         /* Put the host controller in low power mode if possible */
1789         ufshcd_hba_vreg_set_lpm(hba);
1790         /*
1791          * In case you are here to cancel this work the gating state
1792          * would be marked as REQ_CLKS_ON. In this case keep the state
1793          * as REQ_CLKS_ON which would anyway imply that clocks are off
1794          * and a request to turn them on is pending. By doing this way,
1795          * we keep the state machine in tact and this would ultimately
1796          * prevent from doing cancel work multiple times when there are
1797          * new requests arriving before the current cancel work is done.
1798          */
1799         spin_lock_irqsave(hba->host->host_lock, flags);
1800         if (hba->clk_gating.state == REQ_CLKS_OFF) {
1801                 hba->clk_gating.state = CLKS_OFF;
1802                 trace_ufshcd_clk_gating(dev_name(hba->dev),
1803                                         hba->clk_gating.state);
1804         }
1805 rel_lock:
1806         spin_unlock_irqrestore(hba->host->host_lock, flags);
1807 out:
1808         return;
1809 }
1810
1811 /* host lock must be held before calling this variant */
1812 static void __ufshcd_release(struct ufs_hba *hba)
1813 {
1814         if (!ufshcd_is_clkgating_allowed(hba))
1815                 return;
1816
1817         hba->clk_gating.active_reqs--;
1818
1819         if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended ||
1820             hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL ||
1821             hba->outstanding_tasks ||
1822             hba->active_uic_cmd || hba->uic_async_done ||
1823             hba->clk_gating.state == CLKS_OFF)
1824                 return;
1825
1826         hba->clk_gating.state = REQ_CLKS_OFF;
1827         trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
1828         queue_delayed_work(hba->clk_gating.clk_gating_workq,
1829                            &hba->clk_gating.gate_work,
1830                            msecs_to_jiffies(hba->clk_gating.delay_ms));
1831 }
1832
1833 void ufshcd_release(struct ufs_hba *hba)
1834 {
1835         unsigned long flags;
1836
1837         spin_lock_irqsave(hba->host->host_lock, flags);
1838         __ufshcd_release(hba);
1839         spin_unlock_irqrestore(hba->host->host_lock, flags);
1840 }
1841 EXPORT_SYMBOL_GPL(ufshcd_release);
1842
1843 static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1844                 struct device_attribute *attr, char *buf)
1845 {
1846         struct ufs_hba *hba = dev_get_drvdata(dev);
1847
1848         return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms);
1849 }
1850
1851 static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1852                 struct device_attribute *attr, const char *buf, size_t count)
1853 {
1854         struct ufs_hba *hba = dev_get_drvdata(dev);
1855         unsigned long flags, value;
1856
1857         if (kstrtoul(buf, 0, &value))
1858                 return -EINVAL;
1859
1860         spin_lock_irqsave(hba->host->host_lock, flags);
1861         hba->clk_gating.delay_ms = value;
1862         spin_unlock_irqrestore(hba->host->host_lock, flags);
1863         return count;
1864 }
1865
1866 static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1867                 struct device_attribute *attr, char *buf)
1868 {
1869         struct ufs_hba *hba = dev_get_drvdata(dev);
1870
1871         return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled);
1872 }
1873
1874 static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1875                 struct device_attribute *attr, const char *buf, size_t count)
1876 {
1877         struct ufs_hba *hba = dev_get_drvdata(dev);
1878         unsigned long flags;
1879         u32 value;
1880
1881         if (kstrtou32(buf, 0, &value))
1882                 return -EINVAL;
1883
1884         value = !!value;
1885
1886         spin_lock_irqsave(hba->host->host_lock, flags);
1887         if (value == hba->clk_gating.is_enabled)
1888                 goto out;
1889
1890         if (value)
1891                 __ufshcd_release(hba);
1892         else
1893                 hba->clk_gating.active_reqs++;
1894
1895         hba->clk_gating.is_enabled = value;
1896 out:
1897         spin_unlock_irqrestore(hba->host->host_lock, flags);
1898         return count;
1899 }
1900
1901 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba)
1902 {
1903         hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1904         hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1905         sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1906         hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
1907         hba->clk_gating.delay_attr.attr.mode = 0644;
1908         if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1909                 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
1910
1911         hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1912         hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1913         sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1914         hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1915         hba->clk_gating.enable_attr.attr.mode = 0644;
1916         if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1917                 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1918 }
1919
1920 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba)
1921 {
1922         if (hba->clk_gating.delay_attr.attr.name)
1923                 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
1924         if (hba->clk_gating.enable_attr.attr.name)
1925                 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
1926 }
1927
1928 static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1929 {
1930         char wq_name[sizeof("ufs_clk_gating_00")];
1931
1932         if (!ufshcd_is_clkgating_allowed(hba))
1933                 return;
1934
1935         hba->clk_gating.state = CLKS_ON;
1936
1937         hba->clk_gating.delay_ms = 150;
1938         INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1939         INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1940
1941         snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
1942                  hba->host->host_no);
1943         hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
1944                                         WQ_MEM_RECLAIM | WQ_HIGHPRI);
1945
1946         ufshcd_init_clk_gating_sysfs(hba);
1947
1948         hba->clk_gating.is_enabled = true;
1949         hba->clk_gating.is_initialized = true;
1950 }
1951
1952 static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1953 {
1954         if (!hba->clk_gating.is_initialized)
1955                 return;
1956         ufshcd_remove_clk_gating_sysfs(hba);
1957         cancel_work_sync(&hba->clk_gating.ungate_work);
1958         cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1959         destroy_workqueue(hba->clk_gating.clk_gating_workq);
1960         hba->clk_gating.is_initialized = false;
1961 }
1962
1963 /* Must be called with host lock acquired */
1964 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1965 {
1966         bool queue_resume_work = false;
1967         ktime_t curr_t = ktime_get();
1968         unsigned long flags;
1969
1970         if (!ufshcd_is_clkscaling_supported(hba))
1971                 return;
1972
1973         spin_lock_irqsave(hba->host->host_lock, flags);
1974         if (!hba->clk_scaling.active_reqs++)
1975                 queue_resume_work = true;
1976
1977         if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) {
1978                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1979                 return;
1980         }
1981
1982         if (queue_resume_work)
1983                 queue_work(hba->clk_scaling.workq,
1984                            &hba->clk_scaling.resume_work);
1985
1986         if (!hba->clk_scaling.window_start_t) {
1987                 hba->clk_scaling.window_start_t = curr_t;
1988                 hba->clk_scaling.tot_busy_t = 0;
1989                 hba->clk_scaling.is_busy_started = false;
1990         }
1991
1992         if (!hba->clk_scaling.is_busy_started) {
1993                 hba->clk_scaling.busy_start_t = curr_t;
1994                 hba->clk_scaling.is_busy_started = true;
1995         }
1996         spin_unlock_irqrestore(hba->host->host_lock, flags);
1997 }
1998
1999 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
2000 {
2001         struct ufs_clk_scaling *scaling = &hba->clk_scaling;
2002         unsigned long flags;
2003
2004         if (!ufshcd_is_clkscaling_supported(hba))
2005                 return;
2006
2007         spin_lock_irqsave(hba->host->host_lock, flags);
2008         hba->clk_scaling.active_reqs--;
2009         if (!hba->outstanding_reqs && scaling->is_busy_started) {
2010                 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
2011                                         scaling->busy_start_t));
2012                 scaling->busy_start_t = 0;
2013                 scaling->is_busy_started = false;
2014         }
2015         spin_unlock_irqrestore(hba->host->host_lock, flags);
2016 }
2017
2018 static inline int ufshcd_monitor_opcode2dir(u8 opcode)
2019 {
2020         if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16)
2021                 return READ;
2022         else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16)
2023                 return WRITE;
2024         else
2025                 return -EINVAL;
2026 }
2027
2028 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba,
2029                                                 struct ufshcd_lrb *lrbp)
2030 {
2031         struct ufs_hba_monitor *m = &hba->monitor;
2032
2033         return (m->enabled && lrbp && lrbp->cmd &&
2034                 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) &&
2035                 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp));
2036 }
2037
2038 static void ufshcd_start_monitor(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2039 {
2040         int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
2041         unsigned long flags;
2042
2043         spin_lock_irqsave(hba->host->host_lock, flags);
2044         if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0)
2045                 hba->monitor.busy_start_ts[dir] = ktime_get();
2046         spin_unlock_irqrestore(hba->host->host_lock, flags);
2047 }
2048
2049 static void ufshcd_update_monitor(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2050 {
2051         int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
2052         unsigned long flags;
2053
2054         spin_lock_irqsave(hba->host->host_lock, flags);
2055         if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) {
2056                 struct request *req = lrbp->cmd->request;
2057                 struct ufs_hba_monitor *m = &hba->monitor;
2058                 ktime_t now, inc, lat;
2059
2060                 now = lrbp->compl_time_stamp;
2061                 inc = ktime_sub(now, m->busy_start_ts[dir]);
2062                 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc);
2063                 m->nr_sec_rw[dir] += blk_rq_sectors(req);
2064
2065                 /* Update latencies */
2066                 m->nr_req[dir]++;
2067                 lat = ktime_sub(now, lrbp->issue_time_stamp);
2068                 m->lat_sum[dir] += lat;
2069                 if (m->lat_max[dir] < lat || !m->lat_max[dir])
2070                         m->lat_max[dir] = lat;
2071                 if (m->lat_min[dir] > lat || !m->lat_min[dir])
2072                         m->lat_min[dir] = lat;
2073
2074                 m->nr_queued[dir]--;
2075                 /* Push forward the busy start of monitor */
2076                 m->busy_start_ts[dir] = now;
2077         }
2078         spin_unlock_irqrestore(hba->host->host_lock, flags);
2079 }
2080
2081 /**
2082  * ufshcd_send_command - Send SCSI or device management commands
2083  * @hba: per adapter instance
2084  * @task_tag: Task tag of the command
2085  */
2086 static inline
2087 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
2088 {
2089         struct ufshcd_lrb *lrbp = &hba->lrb[task_tag];
2090         unsigned long flags;
2091
2092         lrbp->issue_time_stamp = ktime_get();
2093         lrbp->compl_time_stamp = ktime_set(0, 0);
2094         ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND);
2095         ufshcd_clk_scaling_start_busy(hba);
2096         if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
2097                 ufshcd_start_monitor(hba, lrbp);
2098
2099         spin_lock_irqsave(&hba->outstanding_lock, flags);
2100         if (hba->vops && hba->vops->setup_xfer_req)
2101                 hba->vops->setup_xfer_req(hba, task_tag, !!lrbp->cmd);
2102         __set_bit(task_tag, &hba->outstanding_reqs);
2103         ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
2104         spin_unlock_irqrestore(&hba->outstanding_lock, flags);
2105
2106         /* Make sure that doorbell is committed immediately */
2107         wmb();
2108 }
2109
2110 /**
2111  * ufshcd_copy_sense_data - Copy sense data in case of check condition
2112  * @lrbp: pointer to local reference block
2113  */
2114 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
2115 {
2116         int len;
2117         if (lrbp->sense_buffer &&
2118             ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
2119                 int len_to_copy;
2120
2121                 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
2122                 len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
2123
2124                 memcpy(lrbp->sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
2125                        len_to_copy);
2126         }
2127 }
2128
2129 /**
2130  * ufshcd_copy_query_response() - Copy the Query Response and the data
2131  * descriptor
2132  * @hba: per adapter instance
2133  * @lrbp: pointer to local reference block
2134  */
2135 static
2136 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2137 {
2138         struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2139
2140         memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
2141
2142         /* Get the descriptor */
2143         if (hba->dev_cmd.query.descriptor &&
2144             lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
2145                 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
2146                                 GENERAL_UPIU_REQUEST_SIZE;
2147                 u16 resp_len;
2148                 u16 buf_len;
2149
2150                 /* data segment length */
2151                 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
2152                                                 MASK_QUERY_DATA_SEG_LEN;
2153                 buf_len = be16_to_cpu(
2154                                 hba->dev_cmd.query.request.upiu_req.length);
2155                 if (likely(buf_len >= resp_len)) {
2156                         memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
2157                 } else {
2158                         dev_warn(hba->dev,
2159                                  "%s: rsp size %d is bigger than buffer size %d",
2160                                  __func__, resp_len, buf_len);
2161                         return -EINVAL;
2162                 }
2163         }
2164
2165         return 0;
2166 }
2167
2168 /**
2169  * ufshcd_hba_capabilities - Read controller capabilities
2170  * @hba: per adapter instance
2171  *
2172  * Return: 0 on success, negative on error.
2173  */
2174 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba)
2175 {
2176         int err;
2177
2178         hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
2179
2180         /* nutrs and nutmrs are 0 based values */
2181         hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
2182         hba->nutmrs =
2183         ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
2184
2185         /* Read crypto capabilities */
2186         err = ufshcd_hba_init_crypto_capabilities(hba);
2187         if (err)
2188                 dev_err(hba->dev, "crypto setup failed\n");
2189
2190         return err;
2191 }
2192
2193 /**
2194  * ufshcd_ready_for_uic_cmd - Check if controller is ready
2195  *                            to accept UIC commands
2196  * @hba: per adapter instance
2197  * Return true on success, else false
2198  */
2199 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
2200 {
2201         if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
2202                 return true;
2203         else
2204                 return false;
2205 }
2206
2207 /**
2208  * ufshcd_get_upmcrs - Get the power mode change request status
2209  * @hba: Pointer to adapter instance
2210  *
2211  * This function gets the UPMCRS field of HCS register
2212  * Returns value of UPMCRS field
2213  */
2214 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
2215 {
2216         return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
2217 }
2218
2219 /**
2220  * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer
2221  * @hba: per adapter instance
2222  * @uic_cmd: UIC command
2223  */
2224 static inline void
2225 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2226 {
2227         lockdep_assert_held(&hba->uic_cmd_mutex);
2228
2229         WARN_ON(hba->active_uic_cmd);
2230
2231         hba->active_uic_cmd = uic_cmd;
2232
2233         /* Write Args */
2234         ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2235         ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2236         ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
2237
2238         ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND);
2239
2240         /* Write UIC Cmd */
2241         ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
2242                       REG_UIC_COMMAND);
2243 }
2244
2245 /**
2246  * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command
2247  * @hba: per adapter instance
2248  * @uic_cmd: UIC command
2249  *
2250  * Returns 0 only if success.
2251  */
2252 static int
2253 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2254 {
2255         int ret;
2256         unsigned long flags;
2257
2258         lockdep_assert_held(&hba->uic_cmd_mutex);
2259
2260         if (wait_for_completion_timeout(&uic_cmd->done,
2261                                         msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2262                 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2263         } else {
2264                 ret = -ETIMEDOUT;
2265                 dev_err(hba->dev,
2266                         "uic cmd 0x%x with arg3 0x%x completion timeout\n",
2267                         uic_cmd->command, uic_cmd->argument3);
2268
2269                 if (!uic_cmd->cmd_active) {
2270                         dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n",
2271                                 __func__);
2272                         ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2273                 }
2274         }
2275
2276         spin_lock_irqsave(hba->host->host_lock, flags);
2277         hba->active_uic_cmd = NULL;
2278         spin_unlock_irqrestore(hba->host->host_lock, flags);
2279
2280         return ret;
2281 }
2282
2283 /**
2284  * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2285  * @hba: per adapter instance
2286  * @uic_cmd: UIC command
2287  * @completion: initialize the completion only if this is set to true
2288  *
2289  * Returns 0 only if success.
2290  */
2291 static int
2292 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2293                       bool completion)
2294 {
2295         lockdep_assert_held(&hba->uic_cmd_mutex);
2296         lockdep_assert_held(hba->host->host_lock);
2297
2298         if (!ufshcd_ready_for_uic_cmd(hba)) {
2299                 dev_err(hba->dev,
2300                         "Controller not ready to accept UIC commands\n");
2301                 return -EIO;
2302         }
2303
2304         if (completion)
2305                 init_completion(&uic_cmd->done);
2306
2307         uic_cmd->cmd_active = 1;
2308         ufshcd_dispatch_uic_cmd(hba, uic_cmd);
2309
2310         return 0;
2311 }
2312
2313 /**
2314  * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2315  * @hba: per adapter instance
2316  * @uic_cmd: UIC command
2317  *
2318  * Returns 0 only if success.
2319  */
2320 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2321 {
2322         int ret;
2323         unsigned long flags;
2324
2325         ufshcd_hold(hba, false);
2326         mutex_lock(&hba->uic_cmd_mutex);
2327         ufshcd_add_delay_before_dme_cmd(hba);
2328
2329         spin_lock_irqsave(hba->host->host_lock, flags);
2330         ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
2331         spin_unlock_irqrestore(hba->host->host_lock, flags);
2332         if (!ret)
2333                 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2334
2335         mutex_unlock(&hba->uic_cmd_mutex);
2336
2337         ufshcd_release(hba);
2338         return ret;
2339 }
2340
2341 /**
2342  * ufshcd_map_sg - Map scatter-gather list to prdt
2343  * @hba: per adapter instance
2344  * @lrbp: pointer to local reference block
2345  *
2346  * Returns 0 in case of success, non-zero value in case of failure
2347  */
2348 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2349 {
2350         struct ufshcd_sg_entry *prd_table;
2351         struct scatterlist *sg;
2352         struct scsi_cmnd *cmd;
2353         int sg_segments;
2354         int i;
2355
2356         cmd = lrbp->cmd;
2357         sg_segments = scsi_dma_map(cmd);
2358         if (sg_segments < 0)
2359                 return sg_segments;
2360
2361         if (sg_segments) {
2362
2363                 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2364                         lrbp->utr_descriptor_ptr->prd_table_length =
2365                                 cpu_to_le16((sg_segments *
2366                                         sizeof(struct ufshcd_sg_entry)));
2367                 else
2368                         lrbp->utr_descriptor_ptr->prd_table_length =
2369                                 cpu_to_le16((u16) (sg_segments));
2370
2371                 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
2372
2373                 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2374                         prd_table[i].size  =
2375                                 cpu_to_le32(((u32) sg_dma_len(sg))-1);
2376                         prd_table[i].base_addr =
2377                                 cpu_to_le32(lower_32_bits(sg->dma_address));
2378                         prd_table[i].upper_addr =
2379                                 cpu_to_le32(upper_32_bits(sg->dma_address));
2380                         prd_table[i].reserved = 0;
2381                 }
2382         } else {
2383                 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2384         }
2385
2386         return 0;
2387 }
2388
2389 /**
2390  * ufshcd_enable_intr - enable interrupts
2391  * @hba: per adapter instance
2392  * @intrs: interrupt bits
2393  */
2394 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
2395 {
2396         u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2397
2398         if (hba->ufs_version == ufshci_version(1, 0)) {
2399                 u32 rw;
2400                 rw = set & INTERRUPT_MASK_RW_VER_10;
2401                 set = rw | ((set ^ intrs) & intrs);
2402         } else {
2403                 set |= intrs;
2404         }
2405
2406         ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2407 }
2408
2409 /**
2410  * ufshcd_disable_intr - disable interrupts
2411  * @hba: per adapter instance
2412  * @intrs: interrupt bits
2413  */
2414 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2415 {
2416         u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2417
2418         if (hba->ufs_version == ufshci_version(1, 0)) {
2419                 u32 rw;
2420                 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2421                         ~(intrs & INTERRUPT_MASK_RW_VER_10);
2422                 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2423
2424         } else {
2425                 set &= ~intrs;
2426         }
2427
2428         ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2429 }
2430
2431 /**
2432  * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2433  * descriptor according to request
2434  * @lrbp: pointer to local reference block
2435  * @upiu_flags: flags required in the header
2436  * @cmd_dir: requests data direction
2437  */
2438 static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
2439                         u8 *upiu_flags, enum dma_data_direction cmd_dir)
2440 {
2441         struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2442         u32 data_direction;
2443         u32 dword_0;
2444         u32 dword_1 = 0;
2445         u32 dword_3 = 0;
2446
2447         if (cmd_dir == DMA_FROM_DEVICE) {
2448                 data_direction = UTP_DEVICE_TO_HOST;
2449                 *upiu_flags = UPIU_CMD_FLAGS_READ;
2450         } else if (cmd_dir == DMA_TO_DEVICE) {
2451                 data_direction = UTP_HOST_TO_DEVICE;
2452                 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2453         } else {
2454                 data_direction = UTP_NO_DATA_TRANSFER;
2455                 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2456         }
2457
2458         dword_0 = data_direction | (lrbp->command_type
2459                                 << UPIU_COMMAND_TYPE_OFFSET);
2460         if (lrbp->intr_cmd)
2461                 dword_0 |= UTP_REQ_DESC_INT_CMD;
2462
2463         /* Prepare crypto related dwords */
2464         ufshcd_prepare_req_desc_hdr_crypto(lrbp, &dword_0, &dword_1, &dword_3);
2465
2466         /* Transfer request descriptor header fields */
2467         req_desc->header.dword_0 = cpu_to_le32(dword_0);
2468         req_desc->header.dword_1 = cpu_to_le32(dword_1);
2469         /*
2470          * assigning invalid value for command status. Controller
2471          * updates OCS on command completion, with the command
2472          * status
2473          */
2474         req_desc->header.dword_2 =
2475                 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
2476         req_desc->header.dword_3 = cpu_to_le32(dword_3);
2477
2478         req_desc->prd_table_length = 0;
2479 }
2480
2481 /**
2482  * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2483  * for scsi commands
2484  * @lrbp: local reference block pointer
2485  * @upiu_flags: flags
2486  */
2487 static
2488 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags)
2489 {
2490         struct scsi_cmnd *cmd = lrbp->cmd;
2491         struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2492         unsigned short cdb_len;
2493
2494         /* command descriptor fields */
2495         ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2496                                 UPIU_TRANSACTION_COMMAND, upiu_flags,
2497                                 lrbp->lun, lrbp->task_tag);
2498         ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2499                                 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2500
2501         /* Total EHS length and Data segment length will be zero */
2502         ucd_req_ptr->header.dword_2 = 0;
2503
2504         ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
2505
2506         cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
2507         memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
2508         memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
2509
2510         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2511 }
2512
2513 /**
2514  * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2515  * for query requsts
2516  * @hba: UFS hba
2517  * @lrbp: local reference block pointer
2518  * @upiu_flags: flags
2519  */
2520 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2521                                 struct ufshcd_lrb *lrbp, u8 upiu_flags)
2522 {
2523         struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2524         struct ufs_query *query = &hba->dev_cmd.query;
2525         u16 len = be16_to_cpu(query->request.upiu_req.length);
2526
2527         /* Query request header */
2528         ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2529                         UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2530                         lrbp->lun, lrbp->task_tag);
2531         ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2532                         0, query->request.query_func, 0, 0);
2533
2534         /* Data segment length only need for WRITE_DESC */
2535         if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2536                 ucd_req_ptr->header.dword_2 =
2537                         UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2538         else
2539                 ucd_req_ptr->header.dword_2 = 0;
2540
2541         /* Copy the Query Request buffer as is */
2542         memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2543                         QUERY_OSF_SIZE);
2544
2545         /* Copy the Descriptor */
2546         if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2547                 memcpy(ucd_req_ptr + 1, query->descriptor, len);
2548
2549         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2550 }
2551
2552 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2553 {
2554         struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2555
2556         memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2557
2558         /* command descriptor fields */
2559         ucd_req_ptr->header.dword_0 =
2560                 UPIU_HEADER_DWORD(
2561                         UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
2562         /* clear rest of the fields of basic header */
2563         ucd_req_ptr->header.dword_1 = 0;
2564         ucd_req_ptr->header.dword_2 = 0;
2565
2566         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2567 }
2568
2569 /**
2570  * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU)
2571  *                           for Device Management Purposes
2572  * @hba: per adapter instance
2573  * @lrbp: pointer to local reference block
2574  */
2575 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba,
2576                                       struct ufshcd_lrb *lrbp)
2577 {
2578         u8 upiu_flags;
2579         int ret = 0;
2580
2581         if (hba->ufs_version <= ufshci_version(1, 1))
2582                 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
2583         else
2584                 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2585
2586         ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2587         if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2588                 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2589         else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2590                 ufshcd_prepare_utp_nop_upiu(lrbp);
2591         else
2592                 ret = -EINVAL;
2593
2594         return ret;
2595 }
2596
2597 /**
2598  * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2599  *                         for SCSI Purposes
2600  * @hba: per adapter instance
2601  * @lrbp: pointer to local reference block
2602  */
2603 static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2604 {
2605         u8 upiu_flags;
2606         int ret = 0;
2607
2608         if (hba->ufs_version <= ufshci_version(1, 1))
2609                 lrbp->command_type = UTP_CMD_TYPE_SCSI;
2610         else
2611                 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2612
2613         if (likely(lrbp->cmd)) {
2614                 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2615                                                 lrbp->cmd->sc_data_direction);
2616                 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2617         } else {
2618                 ret = -EINVAL;
2619         }
2620
2621         return ret;
2622 }
2623
2624 /**
2625  * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
2626  * @upiu_wlun_id: UPIU W-LUN id
2627  *
2628  * Returns SCSI W-LUN id
2629  */
2630 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2631 {
2632         return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2633 }
2634
2635 static inline bool is_rpmb_wlun(struct scsi_device *sdev)
2636 {
2637         return sdev->lun == ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN);
2638 }
2639
2640 static inline bool is_device_wlun(struct scsi_device *sdev)
2641 {
2642         return sdev->lun ==
2643                 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN);
2644 }
2645
2646 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i)
2647 {
2648         struct utp_transfer_cmd_desc *cmd_descp = hba->ucdl_base_addr;
2649         struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr;
2650         dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr +
2651                 i * sizeof(struct utp_transfer_cmd_desc);
2652         u16 response_offset = offsetof(struct utp_transfer_cmd_desc,
2653                                        response_upiu);
2654         u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
2655
2656         lrb->utr_descriptor_ptr = utrdlp + i;
2657         lrb->utrd_dma_addr = hba->utrdl_dma_addr +
2658                 i * sizeof(struct utp_transfer_req_desc);
2659         lrb->ucd_req_ptr = (struct utp_upiu_req *)(cmd_descp + i);
2660         lrb->ucd_req_dma_addr = cmd_desc_element_addr;
2661         lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2662         lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset;
2663         lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
2664         lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset;
2665 }
2666
2667 /**
2668  * ufshcd_queuecommand - main entry point for SCSI requests
2669  * @host: SCSI host pointer
2670  * @cmd: command from SCSI Midlayer
2671  *
2672  * Returns 0 for success, non-zero in case of failure
2673  */
2674 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2675 {
2676         struct ufs_hba *hba = shost_priv(host);
2677         int tag = cmd->request->tag;
2678         struct ufshcd_lrb *lrbp;
2679         int err = 0;
2680
2681         WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
2682
2683         if (!down_read_trylock(&hba->clk_scaling_lock))
2684                 return SCSI_MLQUEUE_HOST_BUSY;
2685
2686         switch (hba->ufshcd_state) {
2687         case UFSHCD_STATE_OPERATIONAL:
2688         case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL:
2689                 break;
2690         case UFSHCD_STATE_EH_SCHEDULED_FATAL:
2691                 /*
2692                  * pm_runtime_get_sync() is used at error handling preparation
2693                  * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's
2694                  * PM ops, it can never be finished if we let SCSI layer keep
2695                  * retrying it, which gets err handler stuck forever. Neither
2696                  * can we let the scsi cmd pass through, because UFS is in bad
2697                  * state, the scsi cmd may eventually time out, which will get
2698                  * err handler blocked for too long. So, just fail the scsi cmd
2699                  * sent from PM ops, err handler can recover PM error anyways.
2700                  */
2701                 if (hba->pm_op_in_progress) {
2702                         hba->force_reset = true;
2703                         set_host_byte(cmd, DID_BAD_TARGET);
2704                         cmd->scsi_done(cmd);
2705                         goto out;
2706                 }
2707                 fallthrough;
2708         case UFSHCD_STATE_RESET:
2709                 err = SCSI_MLQUEUE_HOST_BUSY;
2710                 goto out;
2711         case UFSHCD_STATE_ERROR:
2712                 set_host_byte(cmd, DID_ERROR);
2713                 cmd->scsi_done(cmd);
2714                 goto out;
2715         }
2716
2717         hba->req_abort_count = 0;
2718
2719         err = ufshcd_hold(hba, true);
2720         if (err) {
2721                 err = SCSI_MLQUEUE_HOST_BUSY;
2722                 goto out;
2723         }
2724         WARN_ON(ufshcd_is_clkgating_allowed(hba) &&
2725                 (hba->clk_gating.state != CLKS_ON));
2726
2727         lrbp = &hba->lrb[tag];
2728         WARN_ON(lrbp->cmd);
2729         lrbp->cmd = cmd;
2730         lrbp->sense_bufflen = UFS_SENSE_SIZE;
2731         lrbp->sense_buffer = cmd->sense_buffer;
2732         lrbp->task_tag = tag;
2733         lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
2734         lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
2735
2736         ufshcd_prepare_lrbp_crypto(cmd->request, lrbp);
2737
2738         lrbp->req_abort_skip = false;
2739
2740         err = ufshpb_prep(hba, lrbp);
2741         if (err == -EAGAIN) {
2742                 lrbp->cmd = NULL;
2743                 ufshcd_release(hba);
2744                 goto out;
2745         }
2746
2747         ufshcd_comp_scsi_upiu(hba, lrbp);
2748
2749         err = ufshcd_map_sg(hba, lrbp);
2750         if (err) {
2751                 lrbp->cmd = NULL;
2752                 ufshcd_release(hba);
2753                 goto out;
2754         }
2755
2756         ufshcd_send_command(hba, tag);
2757 out:
2758         up_read(&hba->clk_scaling_lock);
2759
2760         if (ufs_trigger_eh())
2761                 scsi_schedule_eh(hba->host);
2762
2763         return err;
2764 }
2765
2766 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2767                 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2768 {
2769         lrbp->cmd = NULL;
2770         lrbp->sense_bufflen = 0;
2771         lrbp->sense_buffer = NULL;
2772         lrbp->task_tag = tag;
2773         lrbp->lun = 0; /* device management cmd is not specific to any LUN */
2774         lrbp->intr_cmd = true; /* No interrupt aggregation */
2775         ufshcd_prepare_lrbp_crypto(NULL, lrbp);
2776         hba->dev_cmd.type = cmd_type;
2777
2778         return ufshcd_compose_devman_upiu(hba, lrbp);
2779 }
2780
2781 static int
2782 ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2783 {
2784         int err = 0;
2785         unsigned long flags;
2786         u32 mask = 1 << tag;
2787
2788         /* clear outstanding transaction before retry */
2789         spin_lock_irqsave(hba->host->host_lock, flags);
2790         ufshcd_utrl_clear(hba, tag);
2791         spin_unlock_irqrestore(hba->host->host_lock, flags);
2792
2793         /*
2794          * wait for h/w to clear corresponding bit in door-bell.
2795          * max. wait is 1 sec.
2796          */
2797         err = ufshcd_wait_for_register(hba,
2798                         REG_UTP_TRANSFER_REQ_DOOR_BELL,
2799                         mask, ~mask, 1000, 1000);
2800
2801         return err;
2802 }
2803
2804 static int
2805 ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2806 {
2807         struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2808
2809         /* Get the UPIU response */
2810         query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2811                                 UPIU_RSP_CODE_OFFSET;
2812         return query_res->response;
2813 }
2814
2815 /**
2816  * ufshcd_dev_cmd_completion() - handles device management command responses
2817  * @hba: per adapter instance
2818  * @lrbp: pointer to local reference block
2819  */
2820 static int
2821 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2822 {
2823         int resp;
2824         int err = 0;
2825
2826         hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
2827         resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2828
2829         switch (resp) {
2830         case UPIU_TRANSACTION_NOP_IN:
2831                 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2832                         err = -EINVAL;
2833                         dev_err(hba->dev, "%s: unexpected response %x\n",
2834                                         __func__, resp);
2835                 }
2836                 break;
2837         case UPIU_TRANSACTION_QUERY_RSP:
2838                 err = ufshcd_check_query_response(hba, lrbp);
2839                 if (!err)
2840                         err = ufshcd_copy_query_response(hba, lrbp);
2841                 break;
2842         case UPIU_TRANSACTION_REJECT_UPIU:
2843                 /* TODO: handle Reject UPIU Response */
2844                 err = -EPERM;
2845                 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2846                                 __func__);
2847                 break;
2848         default:
2849                 err = -EINVAL;
2850                 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2851                                 __func__, resp);
2852                 break;
2853         }
2854
2855         return err;
2856 }
2857
2858 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2859                 struct ufshcd_lrb *lrbp, int max_timeout)
2860 {
2861         int err = 0;
2862         unsigned long time_left;
2863         unsigned long flags;
2864
2865         time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2866                         msecs_to_jiffies(max_timeout));
2867
2868         spin_lock_irqsave(hba->host->host_lock, flags);
2869         hba->dev_cmd.complete = NULL;
2870         if (likely(time_left)) {
2871                 err = ufshcd_get_tr_ocs(lrbp);
2872                 if (!err)
2873                         err = ufshcd_dev_cmd_completion(hba, lrbp);
2874         }
2875         spin_unlock_irqrestore(hba->host->host_lock, flags);
2876
2877         if (!time_left) {
2878                 err = -ETIMEDOUT;
2879                 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2880                         __func__, lrbp->task_tag);
2881                 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
2882                         /* successfully cleared the command, retry if needed */
2883                         err = -EAGAIN;
2884                 /*
2885                  * in case of an error, after clearing the doorbell,
2886                  * we also need to clear the outstanding_request
2887                  * field in hba
2888                  */
2889                 spin_lock_irqsave(&hba->outstanding_lock, flags);
2890                 __clear_bit(lrbp->task_tag, &hba->outstanding_reqs);
2891                 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
2892         }
2893
2894         return err;
2895 }
2896
2897 /**
2898  * ufshcd_exec_dev_cmd - API for sending device management requests
2899  * @hba: UFS hba
2900  * @cmd_type: specifies the type (NOP, Query...)
2901  * @timeout: timeout in milliseconds
2902  *
2903  * NOTE: Since there is only one available tag for device management commands,
2904  * it is expected you hold the hba->dev_cmd.lock mutex.
2905  */
2906 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2907                 enum dev_cmd_type cmd_type, int timeout)
2908 {
2909         struct request_queue *q = hba->cmd_queue;
2910         DECLARE_COMPLETION_ONSTACK(wait);
2911         struct request *req;
2912         struct ufshcd_lrb *lrbp;
2913         int err;
2914         int tag;
2915
2916         down_read(&hba->clk_scaling_lock);
2917
2918         /*
2919          * Get free slot, sleep if slots are unavailable.
2920          * Even though we use wait_event() which sleeps indefinitely,
2921          * the maximum wait time is bounded by SCSI request timeout.
2922          */
2923         req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
2924         if (IS_ERR(req)) {
2925                 err = PTR_ERR(req);
2926                 goto out_unlock;
2927         }
2928         tag = req->tag;
2929         WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
2930         /* Set the timeout such that the SCSI error handler is not activated. */
2931         req->timeout = msecs_to_jiffies(2 * timeout);
2932         blk_mq_start_request(req);
2933
2934         lrbp = &hba->lrb[tag];
2935         WARN_ON(lrbp->cmd);
2936         err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2937         if (unlikely(err))
2938                 goto out;
2939
2940         hba->dev_cmd.complete = &wait;
2941
2942         ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
2943
2944         ufshcd_send_command(hba, tag);
2945         err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2946         ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
2947                                     (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
2948
2949 out:
2950         blk_put_request(req);
2951 out_unlock:
2952         up_read(&hba->clk_scaling_lock);
2953         return err;
2954 }
2955
2956 /**
2957  * ufshcd_init_query() - init the query response and request parameters
2958  * @hba: per-adapter instance
2959  * @request: address of the request pointer to be initialized
2960  * @response: address of the response pointer to be initialized
2961  * @opcode: operation to perform
2962  * @idn: flag idn to access
2963  * @index: LU number to access
2964  * @selector: query/flag/descriptor further identification
2965  */
2966 static inline void ufshcd_init_query(struct ufs_hba *hba,
2967                 struct ufs_query_req **request, struct ufs_query_res **response,
2968                 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2969 {
2970         *request = &hba->dev_cmd.query.request;
2971         *response = &hba->dev_cmd.query.response;
2972         memset(*request, 0, sizeof(struct ufs_query_req));
2973         memset(*response, 0, sizeof(struct ufs_query_res));
2974         (*request)->upiu_req.opcode = opcode;
2975         (*request)->upiu_req.idn = idn;
2976         (*request)->upiu_req.index = index;
2977         (*request)->upiu_req.selector = selector;
2978 }
2979
2980 static int ufshcd_query_flag_retry(struct ufs_hba *hba,
2981         enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res)
2982 {
2983         int ret;
2984         int retries;
2985
2986         for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
2987                 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res);
2988                 if (ret)
2989                         dev_dbg(hba->dev,
2990                                 "%s: failed with error %d, retries %d\n",
2991                                 __func__, ret, retries);
2992                 else
2993                         break;
2994         }
2995
2996         if (ret)
2997                 dev_err(hba->dev,
2998                         "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
2999                         __func__, opcode, idn, ret, retries);
3000         return ret;
3001 }
3002
3003 /**
3004  * ufshcd_query_flag() - API function for sending flag query requests
3005  * @hba: per-adapter instance
3006  * @opcode: flag query to perform
3007  * @idn: flag idn to access
3008  * @index: flag index to access
3009  * @flag_res: the flag value after the query request completes
3010  *
3011  * Returns 0 for success, non-zero in case of failure
3012  */
3013 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
3014                         enum flag_idn idn, u8 index, bool *flag_res)
3015 {
3016         struct ufs_query_req *request = NULL;
3017         struct ufs_query_res *response = NULL;
3018         int err, selector = 0;
3019         int timeout = QUERY_REQ_TIMEOUT;
3020
3021         BUG_ON(!hba);
3022
3023         ufshcd_hold(hba, false);
3024         mutex_lock(&hba->dev_cmd.lock);
3025         ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3026                         selector);
3027
3028         switch (opcode) {
3029         case UPIU_QUERY_OPCODE_SET_FLAG:
3030         case UPIU_QUERY_OPCODE_CLEAR_FLAG:
3031         case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
3032                 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3033                 break;
3034         case UPIU_QUERY_OPCODE_READ_FLAG:
3035                 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3036                 if (!flag_res) {
3037                         /* No dummy reads */
3038                         dev_err(hba->dev, "%s: Invalid argument for read request\n",
3039                                         __func__);
3040                         err = -EINVAL;
3041                         goto out_unlock;
3042                 }
3043                 break;
3044         default:
3045                 dev_err(hba->dev,
3046                         "%s: Expected query flag opcode but got = %d\n",
3047                         __func__, opcode);
3048                 err = -EINVAL;
3049                 goto out_unlock;
3050         }
3051
3052         err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
3053
3054         if (err) {
3055                 dev_err(hba->dev,
3056                         "%s: Sending flag query for idn %d failed, err = %d\n",
3057                         __func__, idn, err);
3058                 goto out_unlock;
3059         }
3060
3061         if (flag_res)
3062                 *flag_res = (be32_to_cpu(response->upiu_res.value) &
3063                                 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
3064
3065 out_unlock:
3066         mutex_unlock(&hba->dev_cmd.lock);
3067         ufshcd_release(hba);
3068         return err;
3069 }
3070
3071 /**
3072  * ufshcd_query_attr - API function for sending attribute requests
3073  * @hba: per-adapter instance
3074  * @opcode: attribute opcode
3075  * @idn: attribute idn to access
3076  * @index: index field
3077  * @selector: selector field
3078  * @attr_val: the attribute value after the query request completes
3079  *
3080  * Returns 0 for success, non-zero in case of failure
3081 */
3082 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
3083                       enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
3084 {
3085         struct ufs_query_req *request = NULL;
3086         struct ufs_query_res *response = NULL;
3087         int err;
3088
3089         BUG_ON(!hba);
3090
3091         if (!attr_val) {
3092                 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
3093                                 __func__, opcode);
3094                 return -EINVAL;
3095         }
3096
3097         ufshcd_hold(hba, false);
3098
3099         mutex_lock(&hba->dev_cmd.lock);
3100         ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3101                         selector);
3102
3103         switch (opcode) {
3104         case UPIU_QUERY_OPCODE_WRITE_ATTR:
3105                 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3106                 request->upiu_req.value = cpu_to_be32(*attr_val);
3107                 break;
3108         case UPIU_QUERY_OPCODE_READ_ATTR:
3109                 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3110                 break;
3111         default:
3112                 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
3113                                 __func__, opcode);
3114                 err = -EINVAL;
3115                 goto out_unlock;
3116         }
3117
3118         err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3119
3120         if (err) {
3121                 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3122                                 __func__, opcode, idn, index, err);
3123                 goto out_unlock;
3124         }
3125
3126         *attr_val = be32_to_cpu(response->upiu_res.value);
3127
3128 out_unlock:
3129         mutex_unlock(&hba->dev_cmd.lock);
3130         ufshcd_release(hba);
3131         return err;
3132 }
3133
3134 /**
3135  * ufshcd_query_attr_retry() - API function for sending query
3136  * attribute with retries
3137  * @hba: per-adapter instance
3138  * @opcode: attribute opcode
3139  * @idn: attribute idn to access
3140  * @index: index field
3141  * @selector: selector field
3142  * @attr_val: the attribute value after the query request
3143  * completes
3144  *
3145  * Returns 0 for success, non-zero in case of failure
3146 */
3147 int ufshcd_query_attr_retry(struct ufs_hba *hba,
3148         enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
3149         u32 *attr_val)
3150 {
3151         int ret = 0;
3152         u32 retries;
3153
3154         for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3155                 ret = ufshcd_query_attr(hba, opcode, idn, index,
3156                                                 selector, attr_val);
3157                 if (ret)
3158                         dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
3159                                 __func__, ret, retries);
3160                 else
3161                         break;
3162         }
3163
3164         if (ret)
3165                 dev_err(hba->dev,
3166                         "%s: query attribute, idn %d, failed with error %d after %d retires\n",
3167                         __func__, idn, ret, QUERY_REQ_RETRIES);
3168         return ret;
3169 }
3170
3171 static int __ufshcd_query_descriptor(struct ufs_hba *hba,
3172                         enum query_opcode opcode, enum desc_idn idn, u8 index,
3173                         u8 selector, u8 *desc_buf, int *buf_len)
3174 {
3175         struct ufs_query_req *request = NULL;
3176         struct ufs_query_res *response = NULL;
3177         int err;
3178
3179         BUG_ON(!hba);
3180
3181         if (!desc_buf) {
3182                 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
3183                                 __func__, opcode);
3184                 return -EINVAL;
3185         }
3186
3187         if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
3188                 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
3189                                 __func__, *buf_len);
3190                 return -EINVAL;
3191         }
3192
3193         ufshcd_hold(hba, false);
3194
3195         mutex_lock(&hba->dev_cmd.lock);
3196         ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3197                         selector);
3198         hba->dev_cmd.query.descriptor = desc_buf;
3199         request->upiu_req.length = cpu_to_be16(*buf_len);
3200
3201         switch (opcode) {
3202         case UPIU_QUERY_OPCODE_WRITE_DESC:
3203                 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3204                 break;
3205         case UPIU_QUERY_OPCODE_READ_DESC:
3206                 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3207                 break;
3208         default:
3209                 dev_err(hba->dev,
3210                                 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
3211                                 __func__, opcode);
3212                 err = -EINVAL;
3213                 goto out_unlock;
3214         }
3215
3216         err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3217
3218         if (err) {
3219                 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3220                                 __func__, opcode, idn, index, err);
3221                 goto out_unlock;
3222         }
3223
3224         *buf_len = be16_to_cpu(response->upiu_res.length);
3225
3226 out_unlock:
3227         hba->dev_cmd.query.descriptor = NULL;
3228         mutex_unlock(&hba->dev_cmd.lock);
3229         ufshcd_release(hba);
3230         return err;
3231 }
3232
3233 /**
3234  * ufshcd_query_descriptor_retry - API function for sending descriptor requests
3235  * @hba: per-adapter instance
3236  * @opcode: attribute opcode
3237  * @idn: attribute idn to access
3238  * @index: index field
3239  * @selector: selector field
3240  * @desc_buf: the buffer that contains the descriptor
3241  * @buf_len: length parameter passed to the device
3242  *
3243  * Returns 0 for success, non-zero in case of failure.
3244  * The buf_len parameter will contain, on return, the length parameter
3245  * received on the response.
3246  */
3247 int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3248                                   enum query_opcode opcode,
3249                                   enum desc_idn idn, u8 index,
3250                                   u8 selector,
3251                                   u8 *desc_buf, int *buf_len)
3252 {
3253         int err;
3254         int retries;
3255
3256         for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3257                 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3258                                                 selector, desc_buf, buf_len);
3259                 if (!err || err == -EINVAL)
3260                         break;
3261         }
3262
3263         return err;
3264 }
3265
3266 /**
3267  * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
3268  * @hba: Pointer to adapter instance
3269  * @desc_id: descriptor idn value
3270  * @desc_len: mapped desc length (out)
3271  */
3272 void ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
3273                                   int *desc_len)
3274 {
3275         if (desc_id >= QUERY_DESC_IDN_MAX || desc_id == QUERY_DESC_IDN_RFU_0 ||
3276             desc_id == QUERY_DESC_IDN_RFU_1)
3277                 *desc_len = 0;
3278         else
3279                 *desc_len = hba->desc_size[desc_id];
3280 }
3281 EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
3282
3283 static void ufshcd_update_desc_length(struct ufs_hba *hba,
3284                                       enum desc_idn desc_id, int desc_index,
3285                                       unsigned char desc_len)
3286 {
3287         if (hba->desc_size[desc_id] == QUERY_DESC_MAX_SIZE &&
3288             desc_id != QUERY_DESC_IDN_STRING && desc_index != UFS_RPMB_UNIT)
3289                 /* For UFS 3.1, the normal unit descriptor is 10 bytes larger
3290                  * than the RPMB unit, however, both descriptors share the same
3291                  * desc_idn, to cover both unit descriptors with one length, we
3292                  * choose the normal unit descriptor length by desc_index.
3293                  */
3294                 hba->desc_size[desc_id] = desc_len;
3295 }
3296
3297 /**
3298  * ufshcd_read_desc_param - read the specified descriptor parameter
3299  * @hba: Pointer to adapter instance
3300  * @desc_id: descriptor idn value
3301  * @desc_index: descriptor index
3302  * @param_offset: offset of the parameter to read
3303  * @param_read_buf: pointer to buffer where parameter would be read
3304  * @param_size: sizeof(param_read_buf)
3305  *
3306  * Return 0 in case of success, non-zero otherwise
3307  */
3308 int ufshcd_read_desc_param(struct ufs_hba *hba,
3309                            enum desc_idn desc_id,
3310                            int desc_index,
3311                            u8 param_offset,
3312                            u8 *param_read_buf,
3313                            u8 param_size)
3314 {
3315         int ret;
3316         u8 *desc_buf;
3317         int buff_len;
3318         bool is_kmalloc = true;
3319
3320         /* Safety check */
3321         if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
3322                 return -EINVAL;
3323
3324         /* Get the length of descriptor */
3325         ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
3326         if (!buff_len) {
3327                 dev_err(hba->dev, "%s: Failed to get desc length\n", __func__);
3328                 return -EINVAL;
3329         }
3330
3331         if (param_offset >= buff_len) {
3332                 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n",
3333                         __func__, param_offset, desc_id, buff_len);
3334                 return -EINVAL;
3335         }
3336
3337         /* Check whether we need temp memory */
3338         if (param_offset != 0 || param_size < buff_len) {
3339                 desc_buf = kzalloc(buff_len, GFP_KERNEL);
3340                 if (!desc_buf)
3341                         return -ENOMEM;
3342         } else {
3343                 desc_buf = param_read_buf;
3344                 is_kmalloc = false;
3345         }
3346
3347         /* Request for full descriptor */
3348         ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3349                                         desc_id, desc_index, 0,
3350                                         desc_buf, &buff_len);
3351
3352         if (ret) {
3353                 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n",
3354                         __func__, desc_id, desc_index, param_offset, ret);
3355                 goto out;
3356         }
3357
3358         /* Sanity check */
3359         if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3360                 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n",
3361                         __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3362                 ret = -EINVAL;
3363                 goto out;
3364         }
3365
3366         /* Update descriptor length */
3367         buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET];
3368         ufshcd_update_desc_length(hba, desc_id, desc_index, buff_len);
3369
3370         if (is_kmalloc) {
3371                 /* Make sure we don't copy more data than available */
3372                 if (param_offset >= buff_len)
3373                         ret = -EINVAL;
3374                 else
3375                         memcpy(param_read_buf, &desc_buf[param_offset],
3376                                min_t(u32, param_size, buff_len - param_offset));
3377         }
3378 out:
3379         if (is_kmalloc)
3380                 kfree(desc_buf);
3381         return ret;
3382 }
3383
3384 /**
3385  * struct uc_string_id - unicode string
3386  *
3387  * @len: size of this descriptor inclusive
3388  * @type: descriptor type
3389  * @uc: unicode string character
3390  */
3391 struct uc_string_id {
3392         u8 len;
3393         u8 type;
3394         wchar_t uc[];
3395 } __packed;
3396
3397 /* replace non-printable or non-ASCII characters with spaces */
3398 static inline char ufshcd_remove_non_printable(u8 ch)
3399 {
3400         return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3401 }
3402
3403 /**
3404  * ufshcd_read_string_desc - read string descriptor
3405  * @hba: pointer to adapter instance
3406  * @desc_index: descriptor index
3407  * @buf: pointer to buffer where descriptor would be read,
3408  *       the caller should free the memory.
3409  * @ascii: if true convert from unicode to ascii characters
3410  *         null terminated string.
3411  *
3412  * Return:
3413  * *      string size on success.
3414  * *      -ENOMEM: on allocation failure
3415  * *      -EINVAL: on a wrong parameter
3416  */
3417 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
3418                             u8 **buf, bool ascii)
3419 {
3420         struct uc_string_id *uc_str;
3421         u8 *str;
3422         int ret;
3423
3424         if (!buf)
3425                 return -EINVAL;
3426
3427         uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3428         if (!uc_str)
3429                 return -ENOMEM;
3430
3431         ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0,
3432                                      (u8 *)uc_str, QUERY_DESC_MAX_SIZE);
3433         if (ret < 0) {
3434                 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3435                         QUERY_REQ_RETRIES, ret);
3436                 str = NULL;
3437                 goto out;
3438         }
3439
3440         if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3441                 dev_dbg(hba->dev, "String Desc is of zero length\n");
3442                 str = NULL;
3443                 ret = 0;
3444                 goto out;
3445         }
3446
3447         if (ascii) {
3448                 ssize_t ascii_len;
3449                 int i;
3450                 /* remove header and divide by 2 to move from UTF16 to UTF8 */
3451                 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3452                 str = kzalloc(ascii_len, GFP_KERNEL);
3453                 if (!str) {
3454                         ret = -ENOMEM;
3455                         goto out;
3456                 }
3457
3458                 /*
3459                  * the descriptor contains string in UTF16 format
3460                  * we need to convert to utf-8 so it can be displayed
3461                  */
3462                 ret = utf16s_to_utf8s(uc_str->uc,
3463                                       uc_str->len - QUERY_DESC_HDR_SIZE,
3464                                       UTF16_BIG_ENDIAN, str, ascii_len);
3465
3466                 /* replace non-printable or non-ASCII characters with spaces */
3467                 for (i = 0; i < ret; i++)
3468                         str[i] = ufshcd_remove_non_printable(str[i]);
3469
3470                 str[ret++] = '\0';
3471
3472         } else {
3473                 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
3474                 if (!str) {
3475                         ret = -ENOMEM;
3476                         goto out;
3477                 }
3478                 ret = uc_str->len;
3479         }
3480 out:
3481         *buf = str;
3482         kfree(uc_str);
3483         return ret;
3484 }
3485
3486 /**
3487  * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3488  * @hba: Pointer to adapter instance
3489  * @lun: lun id
3490  * @param_offset: offset of the parameter to read
3491  * @param_read_buf: pointer to buffer where parameter would be read
3492  * @param_size: sizeof(param_read_buf)
3493  *
3494  * Return 0 in case of success, non-zero otherwise
3495  */
3496 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3497                                               int lun,
3498                                               enum unit_desc_param param_offset,
3499                                               u8 *param_read_buf,
3500                                               u32 param_size)
3501 {
3502         /*
3503          * Unit descriptors are only available for general purpose LUs (LUN id
3504          * from 0 to 7) and RPMB Well known LU.
3505          */
3506         if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun, param_offset))
3507                 return -EOPNOTSUPP;
3508
3509         return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3510                                       param_offset, param_read_buf, param_size);
3511 }
3512
3513 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
3514 {
3515         int err = 0;
3516         u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3517
3518         if (hba->dev_info.wspecversion >= 0x300) {
3519                 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3520                                 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0,
3521                                 &gating_wait);
3522                 if (err)
3523                         dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
3524                                          err, gating_wait);
3525
3526                 if (gating_wait == 0) {
3527                         gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3528                         dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
3529                                          gating_wait);
3530                 }
3531
3532                 hba->dev_info.clk_gating_wait_us = gating_wait;
3533         }
3534
3535         return err;
3536 }
3537
3538 /**
3539  * ufshcd_memory_alloc - allocate memory for host memory space data structures
3540  * @hba: per adapter instance
3541  *
3542  * 1. Allocate DMA memory for Command Descriptor array
3543  *      Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3544  * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3545  * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3546  *      (UTMRDL)
3547  * 4. Allocate memory for local reference block(lrb).
3548  *
3549  * Returns 0 for success, non-zero in case of failure
3550  */
3551 static int ufshcd_memory_alloc(struct ufs_hba *hba)
3552 {
3553         size_t utmrdl_size, utrdl_size, ucdl_size;
3554
3555         /* Allocate memory for UTP command descriptors */
3556         ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
3557         hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3558                                                   ucdl_size,
3559                                                   &hba->ucdl_dma_addr,
3560                                                   GFP_KERNEL);
3561
3562         /*
3563          * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3564          * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3565          * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3566          * be aligned to 128 bytes as well
3567          */
3568         if (!hba->ucdl_base_addr ||
3569             WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3570                 dev_err(hba->dev,
3571                         "Command Descriptor Memory allocation failed\n");
3572                 goto out;
3573         }
3574
3575         /*
3576          * Allocate memory for UTP Transfer descriptors
3577          * UFSHCI requires 1024 byte alignment of UTRD
3578          */
3579         utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
3580         hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3581                                                    utrdl_size,
3582                                                    &hba->utrdl_dma_addr,
3583                                                    GFP_KERNEL);
3584         if (!hba->utrdl_base_addr ||
3585             WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3586                 dev_err(hba->dev,
3587                         "Transfer Descriptor Memory allocation failed\n");
3588                 goto out;
3589         }
3590
3591         /*
3592          * Allocate memory for UTP Task Management descriptors
3593          * UFSHCI requires 1024 byte alignment of UTMRD
3594          */
3595         utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
3596         hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3597                                                     utmrdl_size,
3598                                                     &hba->utmrdl_dma_addr,
3599                                                     GFP_KERNEL);
3600         if (!hba->utmrdl_base_addr ||
3601             WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3602                 dev_err(hba->dev,
3603                 "Task Management Descriptor Memory allocation failed\n");
3604                 goto out;
3605         }
3606
3607         /* Allocate memory for local reference block */
3608         hba->lrb = devm_kcalloc(hba->dev,
3609                                 hba->nutrs, sizeof(struct ufshcd_lrb),
3610                                 GFP_KERNEL);
3611         if (!hba->lrb) {
3612                 dev_err(hba->dev, "LRB Memory allocation failed\n");
3613                 goto out;
3614         }
3615         return 0;
3616 out:
3617         return -ENOMEM;
3618 }
3619
3620 /**
3621  * ufshcd_host_memory_configure - configure local reference block with
3622  *                              memory offsets
3623  * @hba: per adapter instance
3624  *
3625  * Configure Host memory space
3626  * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3627  * address.
3628  * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3629  * and PRDT offset.
3630  * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3631  * into local reference block.
3632  */
3633 static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3634 {
3635         struct utp_transfer_req_desc *utrdlp;
3636         dma_addr_t cmd_desc_dma_addr;
3637         dma_addr_t cmd_desc_element_addr;
3638         u16 response_offset;
3639         u16 prdt_offset;
3640         int cmd_desc_size;
3641         int i;
3642
3643         utrdlp = hba->utrdl_base_addr;
3644
3645         response_offset =
3646                 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3647         prdt_offset =
3648                 offsetof(struct utp_transfer_cmd_desc, prd_table);
3649
3650         cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3651         cmd_desc_dma_addr = hba->ucdl_dma_addr;
3652
3653         for (i = 0; i < hba->nutrs; i++) {
3654                 /* Configure UTRD with command descriptor base address */
3655                 cmd_desc_element_addr =
3656                                 (cmd_desc_dma_addr + (cmd_desc_size * i));
3657                 utrdlp[i].command_desc_base_addr_lo =
3658                                 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3659                 utrdlp[i].command_desc_base_addr_hi =
3660                                 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3661
3662                 /* Response upiu and prdt offset should be in double words */
3663                 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3664                         utrdlp[i].response_upiu_offset =
3665                                 cpu_to_le16(response_offset);
3666                         utrdlp[i].prd_table_offset =
3667                                 cpu_to_le16(prdt_offset);
3668                         utrdlp[i].response_upiu_length =
3669                                 cpu_to_le16(ALIGNED_UPIU_SIZE);
3670                 } else {
3671                         utrdlp[i].response_upiu_offset =
3672                                 cpu_to_le16(response_offset >> 2);
3673                         utrdlp[i].prd_table_offset =
3674                                 cpu_to_le16(prdt_offset >> 2);
3675                         utrdlp[i].response_upiu_length =
3676                                 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
3677                 }
3678
3679                 ufshcd_init_lrb(hba, &hba->lrb[i], i);
3680         }
3681 }
3682
3683 /**
3684  * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3685  * @hba: per adapter instance
3686  *
3687  * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3688  * in order to initialize the Unipro link startup procedure.
3689  * Once the Unipro links are up, the device connected to the controller
3690  * is detected.
3691  *
3692  * Returns 0 on success, non-zero value on failure
3693  */
3694 static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3695 {
3696         struct uic_command uic_cmd = {0};
3697         int ret;
3698
3699         uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
3700
3701         ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3702         if (ret)
3703                 dev_dbg(hba->dev,
3704                         "dme-link-startup: error code %d\n", ret);
3705         return ret;
3706 }
3707 /**
3708  * ufshcd_dme_reset - UIC command for DME_RESET
3709  * @hba: per adapter instance
3710  *
3711  * DME_RESET command is issued in order to reset UniPro stack.
3712  * This function now deals with cold reset.
3713  *
3714  * Returns 0 on success, non-zero value on failure
3715  */
3716 static int ufshcd_dme_reset(struct ufs_hba *hba)
3717 {
3718         struct uic_command uic_cmd = {0};
3719         int ret;
3720
3721         uic_cmd.command = UIC_CMD_DME_RESET;
3722
3723         ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3724         if (ret)
3725                 dev_err(hba->dev,
3726                         "dme-reset: error code %d\n", ret);
3727
3728         return ret;
3729 }
3730
3731 int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
3732                                int agreed_gear,
3733                                int adapt_val)
3734 {
3735         int ret;
3736
3737         if (agreed_gear != UFS_HS_G4)
3738                 adapt_val = PA_NO_ADAPT;
3739
3740         ret = ufshcd_dme_set(hba,
3741                              UIC_ARG_MIB(PA_TXHSADAPTTYPE),
3742                              adapt_val);
3743         return ret;
3744 }
3745 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt);
3746
3747 /**
3748  * ufshcd_dme_enable - UIC command for DME_ENABLE
3749  * @hba: per adapter instance
3750  *
3751  * DME_ENABLE command is issued in order to enable UniPro stack.
3752  *
3753  * Returns 0 on success, non-zero value on failure
3754  */
3755 static int ufshcd_dme_enable(struct ufs_hba *hba)
3756 {
3757         struct uic_command uic_cmd = {0};
3758         int ret;
3759
3760         uic_cmd.command = UIC_CMD_DME_ENABLE;
3761
3762         ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3763         if (ret)
3764                 dev_err(hba->dev,
3765                         "dme-enable: error code %d\n", ret);
3766
3767         return ret;
3768 }
3769
3770 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3771 {
3772         #define MIN_DELAY_BEFORE_DME_CMDS_US    1000
3773         unsigned long min_sleep_time_us;
3774
3775         if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3776                 return;
3777
3778         /*
3779          * last_dme_cmd_tstamp will be 0 only for 1st call to
3780          * this function
3781          */
3782         if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3783                 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3784         } else {
3785                 unsigned long delta =
3786                         (unsigned long) ktime_to_us(
3787                                 ktime_sub(ktime_get(),
3788                                 hba->last_dme_cmd_tstamp));
3789
3790                 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3791                         min_sleep_time_us =
3792                                 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3793                 else
3794                         return; /* no more delay required */
3795         }
3796
3797         /* allow sleep for extra 50us if needed */
3798         usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3799 }
3800
3801 /**
3802  * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3803  * @hba: per adapter instance
3804  * @attr_sel: uic command argument1
3805  * @attr_set: attribute set type as uic command argument2
3806  * @mib_val: setting value as uic command argument3
3807  * @peer: indicate whether peer or local
3808  *
3809  * Returns 0 on success, non-zero value on failure
3810  */
3811 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3812                         u8 attr_set, u32 mib_val, u8 peer)
3813 {
3814         struct uic_command uic_cmd = {0};
3815         static const char *const action[] = {
3816                 "dme-set",
3817                 "dme-peer-set"
3818         };
3819         const char *set = action[!!peer];
3820         int ret;
3821         int retries = UFS_UIC_COMMAND_RETRIES;
3822
3823         uic_cmd.command = peer ?
3824                 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3825         uic_cmd.argument1 = attr_sel;
3826         uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3827         uic_cmd.argument3 = mib_val;
3828
3829         do {
3830                 /* for peer attributes we retry upon failure */
3831                 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3832                 if (ret)
3833                         dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3834                                 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3835         } while (ret && peer && --retries);
3836
3837         if (ret)
3838                 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
3839                         set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3840                         UFS_UIC_COMMAND_RETRIES - retries);
3841
3842         return ret;
3843 }
3844 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3845
3846 /**
3847  * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3848  * @hba: per adapter instance
3849  * @attr_sel: uic command argument1
3850  * @mib_val: the value of the attribute as returned by the UIC command
3851  * @peer: indicate whether peer or local
3852  *
3853  * Returns 0 on success, non-zero value on failure
3854  */
3855 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3856                         u32 *mib_val, u8 peer)
3857 {
3858         struct uic_command uic_cmd = {0};
3859         static const char *const action[] = {
3860                 "dme-get",
3861                 "dme-peer-get"
3862         };
3863         const char *get = action[!!peer];
3864         int ret;
3865         int retries = UFS_UIC_COMMAND_RETRIES;
3866         struct ufs_pa_layer_attr orig_pwr_info;
3867         struct ufs_pa_layer_attr temp_pwr_info;
3868         bool pwr_mode_change = false;
3869
3870         if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3871                 orig_pwr_info = hba->pwr_info;
3872                 temp_pwr_info = orig_pwr_info;
3873
3874                 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3875                     orig_pwr_info.pwr_rx == FAST_MODE) {
3876                         temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3877                         temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3878                         pwr_mode_change = true;
3879                 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3880                     orig_pwr_info.pwr_rx == SLOW_MODE) {
3881                         temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3882                         temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3883                         pwr_mode_change = true;
3884                 }
3885                 if (pwr_mode_change) {
3886                         ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3887                         if (ret)
3888                                 goto out;
3889                 }
3890         }
3891
3892         uic_cmd.command = peer ?
3893                 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3894         uic_cmd.argument1 = attr_sel;
3895
3896         do {
3897                 /* for peer attributes we retry upon failure */
3898                 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3899                 if (ret)
3900                         dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3901                                 get, UIC_GET_ATTR_ID(attr_sel), ret);
3902         } while (ret && peer && --retries);
3903
3904         if (ret)
3905                 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
3906                         get, UIC_GET_ATTR_ID(attr_sel),
3907                         UFS_UIC_COMMAND_RETRIES - retries);
3908
3909         if (mib_val && !ret)
3910                 *mib_val = uic_cmd.argument3;
3911
3912         if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3913             && pwr_mode_change)
3914                 ufshcd_change_power_mode(hba, &orig_pwr_info);
3915 out:
3916         return ret;
3917 }
3918 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3919
3920 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba)
3921 {
3922         lockdep_assert_held(hba->host->host_lock);
3923
3924         return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
3925                (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK));
3926 }
3927
3928 static void ufshcd_schedule_eh(struct ufs_hba *hba)
3929 {
3930         bool schedule_eh = false;
3931         unsigned long flags;
3932
3933         spin_lock_irqsave(hba->host->host_lock, flags);
3934         /* handle fatal errors only when link is not in error state */
3935         if (hba->ufshcd_state != UFSHCD_STATE_ERROR) {
3936                 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
3937                     ufshcd_is_saved_err_fatal(hba))
3938                         hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL;
3939                 else
3940                         hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL;
3941                 schedule_eh = true;
3942         }
3943         spin_unlock_irqrestore(hba->host->host_lock, flags);
3944
3945         if (schedule_eh)
3946                 scsi_schedule_eh(hba->host);
3947 }
3948
3949 /**
3950  * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3951  * state) and waits for it to take effect.
3952  *
3953  * @hba: per adapter instance
3954  * @cmd: UIC command to execute
3955  *
3956  * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3957  * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3958  * and device UniPro link and hence it's final completion would be indicated by
3959  * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3960  * addition to normal UIC command completion Status (UCCS). This function only
3961  * returns after the relevant status bits indicate the completion.
3962  *
3963  * Returns 0 on success, non-zero value on failure
3964  */
3965 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
3966 {
3967         DECLARE_COMPLETION_ONSTACK(uic_async_done);
3968         unsigned long flags;
3969         bool schedule_eh = false;
3970         u8 status;
3971         int ret;
3972         bool reenable_intr = false;
3973
3974         mutex_lock(&hba->uic_cmd_mutex);
3975         ufshcd_add_delay_before_dme_cmd(hba);
3976
3977         spin_lock_irqsave(hba->host->host_lock, flags);
3978         if (ufshcd_is_link_broken(hba)) {
3979                 ret = -ENOLINK;
3980                 goto out_unlock;
3981         }
3982         hba->uic_async_done = &uic_async_done;
3983         if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3984                 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3985                 /*
3986                  * Make sure UIC command completion interrupt is disabled before
3987                  * issuing UIC command.
3988                  */
3989                 wmb();
3990                 reenable_intr = true;
3991         }
3992         ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3993         spin_unlock_irqrestore(hba->host->host_lock, flags);
3994         if (ret) {
3995                 dev_err(hba->dev,
3996                         "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3997                         cmd->command, cmd->argument3, ret);
3998                 goto out;
3999         }
4000
4001         if (!wait_for_completion_timeout(hba->uic_async_done,
4002                                          msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
4003                 dev_err(hba->dev,
4004                         "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
4005                         cmd->command, cmd->argument3);
4006
4007                 if (!cmd->cmd_active) {
4008                         dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n",
4009                                 __func__);
4010                         goto check_upmcrs;
4011                 }
4012
4013                 ret = -ETIMEDOUT;
4014                 goto out;
4015         }
4016
4017 check_upmcrs:
4018         status = ufshcd_get_upmcrs(hba);
4019         if (status != PWR_LOCAL) {
4020                 dev_err(hba->dev,
4021                         "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
4022                         cmd->command, status);
4023                 ret = (status != PWR_OK) ? status : -1;
4024         }
4025 out:
4026         if (ret) {
4027                 ufshcd_print_host_state(hba);
4028                 ufshcd_print_pwr_info(hba);
4029                 ufshcd_print_evt_hist(hba);
4030         }
4031
4032         spin_lock_irqsave(hba->host->host_lock, flags);
4033         hba->active_uic_cmd = NULL;
4034         hba->uic_async_done = NULL;
4035         if (reenable_intr)
4036                 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
4037         if (ret) {
4038                 ufshcd_set_link_broken(hba);
4039                 schedule_eh = true;
4040         }
4041
4042 out_unlock:
4043         spin_unlock_irqrestore(hba->host->host_lock, flags);
4044
4045         if (schedule_eh)
4046                 ufshcd_schedule_eh(hba);
4047         mutex_unlock(&hba->uic_cmd_mutex);
4048
4049         return ret;
4050 }
4051
4052 /**
4053  * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
4054  *                              using DME_SET primitives.
4055  * @hba: per adapter instance
4056  * @mode: powr mode value
4057  *
4058  * Returns 0 on success, non-zero value on failure
4059  */
4060 static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
4061 {
4062         struct uic_command uic_cmd = {0};
4063         int ret;
4064
4065         if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
4066                 ret = ufshcd_dme_set(hba,
4067                                 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
4068                 if (ret) {
4069                         dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
4070                                                 __func__, ret);
4071                         goto out;
4072                 }
4073         }
4074
4075         uic_cmd.command = UIC_CMD_DME_SET;
4076         uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
4077         uic_cmd.argument3 = mode;
4078         ufshcd_hold(hba, false);
4079         ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4080         ufshcd_release(hba);
4081
4082 out:
4083         return ret;
4084 }
4085
4086 int ufshcd_link_recovery(struct ufs_hba *hba)
4087 {
4088         int ret;
4089         unsigned long flags;
4090
4091         spin_lock_irqsave(hba->host->host_lock, flags);
4092         hba->ufshcd_state = UFSHCD_STATE_RESET;
4093         ufshcd_set_eh_in_progress(hba);
4094         spin_unlock_irqrestore(hba->host->host_lock, flags);
4095
4096         /* Reset the attached device */
4097         ufshcd_device_reset(hba);
4098
4099         ret = ufshcd_host_reset_and_restore(hba);
4100
4101         spin_lock_irqsave(hba->host->host_lock, flags);
4102         if (ret)
4103                 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4104         ufshcd_clear_eh_in_progress(hba);
4105         spin_unlock_irqrestore(hba->host->host_lock, flags);
4106
4107         if (ret)
4108                 dev_err(hba->dev, "%s: link recovery failed, err %d",
4109                         __func__, ret);
4110         else
4111                 ufshcd_clear_ua_wluns(hba);
4112
4113         return ret;
4114 }
4115 EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
4116
4117 static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
4118 {
4119         int ret;
4120         struct uic_command uic_cmd = {0};
4121         ktime_t start = ktime_get();
4122
4123         ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
4124
4125         uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
4126         ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4127         trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
4128                              ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4129
4130         if (ret)
4131                 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
4132                         __func__, ret);
4133         else
4134                 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
4135                                                                 POST_CHANGE);
4136
4137         return ret;
4138 }
4139
4140 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
4141 {
4142         struct uic_command uic_cmd = {0};
4143         int ret;
4144         ktime_t start = ktime_get();
4145
4146         ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
4147
4148         uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
4149         ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4150         trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
4151                              ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4152
4153         if (ret) {
4154                 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
4155                         __func__, ret);
4156         } else {
4157                 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
4158                                                                 POST_CHANGE);
4159                 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
4160                 hba->ufs_stats.hibern8_exit_cnt++;
4161         }
4162
4163         return ret;
4164 }
4165 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit);
4166
4167 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
4168 {
4169         unsigned long flags;
4170         bool update = false;
4171
4172         if (!ufshcd_is_auto_hibern8_supported(hba))
4173                 return;
4174
4175         spin_lock_irqsave(hba->host->host_lock, flags);
4176         if (hba->ahit != ahit) {
4177                 hba->ahit = ahit;
4178                 update = true;
4179         }
4180         spin_unlock_irqrestore(hba->host->host_lock, flags);
4181
4182         if (update &&
4183             !pm_runtime_suspended(&hba->sdev_ufs_device->sdev_gendev)) {
4184                 ufshcd_rpm_get_sync(hba);
4185                 ufshcd_hold(hba, false);
4186                 ufshcd_auto_hibern8_enable(hba);
4187                 ufshcd_release(hba);
4188                 ufshcd_rpm_put_sync(hba);
4189         }
4190 }
4191 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
4192
4193 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
4194 {
4195         unsigned long flags;
4196
4197         if (!ufshcd_is_auto_hibern8_supported(hba))
4198                 return;
4199
4200         spin_lock_irqsave(hba->host->host_lock, flags);
4201         ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
4202         spin_unlock_irqrestore(hba->host->host_lock, flags);
4203 }
4204
4205  /**
4206  * ufshcd_init_pwr_info - setting the POR (power on reset)
4207  * values in hba power info
4208  * @hba: per-adapter instance
4209  */
4210 static void ufshcd_init_pwr_info(struct ufs_hba *hba)
4211 {
4212         hba->pwr_info.gear_rx = UFS_PWM_G1;
4213         hba->pwr_info.gear_tx = UFS_PWM_G1;
4214         hba->pwr_info.lane_rx = 1;
4215         hba->pwr_info.lane_tx = 1;
4216         hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
4217         hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
4218         hba->pwr_info.hs_rate = 0;
4219 }
4220
4221 /**
4222  * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
4223  * @hba: per-adapter instance
4224  */
4225 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
4226 {
4227         struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
4228
4229         if (hba->max_pwr_info.is_valid)
4230                 return 0;
4231
4232         pwr_info->pwr_tx = FAST_MODE;
4233         pwr_info->pwr_rx = FAST_MODE;
4234         pwr_info->hs_rate = PA_HS_MODE_B;
4235
4236         /* Get the connected lane count */
4237         ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
4238                         &pwr_info->lane_rx);
4239         ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4240                         &pwr_info->lane_tx);
4241
4242         if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
4243                 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
4244                                 __func__,
4245                                 pwr_info->lane_rx,
4246                                 pwr_info->lane_tx);
4247                 return -EINVAL;
4248         }
4249
4250         /*
4251          * First, get the maximum gears of HS speed.
4252          * If a zero value, it means there is no HSGEAR capability.
4253          * Then, get the maximum gears of PWM speed.
4254          */
4255         ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
4256         if (!pwr_info->gear_rx) {
4257                 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4258                                 &pwr_info->gear_rx);
4259                 if (!pwr_info->gear_rx) {
4260                         dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
4261                                 __func__, pwr_info->gear_rx);
4262                         return -EINVAL;
4263                 }
4264                 pwr_info->pwr_rx = SLOW_MODE;
4265         }
4266
4267         ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
4268                         &pwr_info->gear_tx);
4269         if (!pwr_info->gear_tx) {
4270                 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4271                                 &pwr_info->gear_tx);
4272                 if (!pwr_info->gear_tx) {
4273                         dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
4274                                 __func__, pwr_info->gear_tx);
4275                         return -EINVAL;
4276                 }
4277                 pwr_info->pwr_tx = SLOW_MODE;
4278         }
4279
4280         hba->max_pwr_info.is_valid = true;
4281         return 0;
4282 }
4283
4284 static int ufshcd_change_power_mode(struct ufs_hba *hba,
4285                              struct ufs_pa_layer_attr *pwr_mode)
4286 {
4287         int ret;
4288
4289         /* if already configured to the requested pwr_mode */
4290         if (!hba->force_pmc &&
4291             pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
4292             pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4293             pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4294             pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4295             pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4296             pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4297             pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4298                 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4299                 return 0;
4300         }
4301
4302         /*
4303          * Configure attributes for power mode change with below.
4304          * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4305          * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4306          * - PA_HSSERIES
4307          */
4308         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4309         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4310                         pwr_mode->lane_rx);
4311         if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4312                         pwr_mode->pwr_rx == FAST_MODE)
4313                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
4314         else
4315                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
4316
4317         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4318         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4319                         pwr_mode->lane_tx);
4320         if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4321                         pwr_mode->pwr_tx == FAST_MODE)
4322                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
4323         else
4324                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
4325
4326         if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4327             pwr_mode->pwr_tx == FASTAUTO_MODE ||
4328             pwr_mode->pwr_rx == FAST_MODE ||
4329             pwr_mode->pwr_tx == FAST_MODE)
4330                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4331                                                 pwr_mode->hs_rate);
4332
4333         if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) {
4334                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
4335                                 DL_FC0ProtectionTimeOutVal_Default);
4336                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
4337                                 DL_TC0ReplayTimeOutVal_Default);
4338                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
4339                                 DL_AFC0ReqTimeOutVal_Default);
4340                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
4341                                 DL_FC1ProtectionTimeOutVal_Default);
4342                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
4343                                 DL_TC1ReplayTimeOutVal_Default);
4344                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
4345                                 DL_AFC1ReqTimeOutVal_Default);
4346
4347                 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
4348                                 DL_FC0ProtectionTimeOutVal_Default);
4349                 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
4350                                 DL_TC0ReplayTimeOutVal_Default);
4351                 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
4352                                 DL_AFC0ReqTimeOutVal_Default);
4353         }
4354
4355         ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4356                         | pwr_mode->pwr_tx);
4357
4358         if (ret) {
4359                 dev_err(hba->dev,
4360                         "%s: power mode change failed %d\n", __func__, ret);
4361         } else {
4362                 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4363                                                                 pwr_mode);
4364
4365                 memcpy(&hba->pwr_info, pwr_mode,
4366                         sizeof(struct ufs_pa_layer_attr));
4367         }
4368
4369         return ret;
4370 }
4371
4372 /**
4373  * ufshcd_config_pwr_mode - configure a new power mode
4374  * @hba: per-adapter instance
4375  * @desired_pwr_mode: desired power configuration
4376  */
4377 int ufshcd_config_pwr_mode(struct ufs_hba *hba,
4378                 struct ufs_pa_layer_attr *desired_pwr_mode)
4379 {
4380         struct ufs_pa_layer_attr final_params = { 0 };
4381         int ret;
4382
4383         ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4384                                         desired_pwr_mode, &final_params);
4385
4386         if (ret)
4387                 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4388
4389         ret = ufshcd_change_power_mode(hba, &final_params);
4390
4391         return ret;
4392 }
4393 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
4394
4395 /**
4396  * ufshcd_complete_dev_init() - checks device readiness
4397  * @hba: per-adapter instance
4398  *
4399  * Set fDeviceInit flag and poll until device toggles it.
4400  */
4401 static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4402 {
4403         int err;
4404         bool flag_res = true;
4405         ktime_t timeout;
4406
4407         err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4408                 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL);
4409         if (err) {
4410                 dev_err(hba->dev,
4411                         "%s setting fDeviceInit flag failed with error %d\n",
4412                         __func__, err);
4413                 goto out;
4414         }
4415
4416         /* Poll fDeviceInit flag to be cleared */
4417         timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT);
4418         do {
4419                 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4420                                         QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res);
4421                 if (!flag_res)
4422                         break;
4423                 usleep_range(5000, 10000);
4424         } while (ktime_before(ktime_get(), timeout));
4425
4426         if (err) {
4427                 dev_err(hba->dev,
4428                                 "%s reading fDeviceInit flag failed with error %d\n",
4429                                 __func__, err);
4430         } else if (flag_res) {
4431                 dev_err(hba->dev,
4432                                 "%s fDeviceInit was not cleared by the device\n",
4433                                 __func__);
4434                 err = -EBUSY;
4435         }
4436 out:
4437         return err;
4438 }
4439
4440 /**
4441  * ufshcd_make_hba_operational - Make UFS controller operational
4442  * @hba: per adapter instance
4443  *
4444  * To bring UFS host controller to operational state,
4445  * 1. Enable required interrupts
4446  * 2. Configure interrupt aggregation
4447  * 3. Program UTRL and UTMRL base address
4448  * 4. Configure run-stop-registers
4449  *
4450  * Returns 0 on success, non-zero value on failure
4451  */
4452 int ufshcd_make_hba_operational(struct ufs_hba *hba)
4453 {
4454         int err = 0;
4455         u32 reg;
4456
4457         /* Enable required interrupts */
4458         ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4459
4460         /* Configure interrupt aggregation */
4461         if (ufshcd_is_intr_aggr_allowed(hba))
4462                 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4463         else
4464                 ufshcd_disable_intr_aggr(hba);
4465
4466         /* Configure UTRL and UTMRL base address registers */
4467         ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4468                         REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4469         ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4470                         REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4471         ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4472                         REG_UTP_TASK_REQ_LIST_BASE_L);
4473         ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4474                         REG_UTP_TASK_REQ_LIST_BASE_H);
4475
4476         /*
4477          * Make sure base address and interrupt setup are updated before
4478          * enabling the run/stop registers below.
4479          */
4480         wmb();
4481
4482         /*
4483          * UCRDY, UTMRLDY and UTRLRDY bits must be 1
4484          */
4485         reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
4486         if (!(ufshcd_get_lists_status(reg))) {
4487                 ufshcd_enable_run_stop_reg(hba);
4488         } else {
4489                 dev_err(hba->dev,
4490                         "Host controller not ready to process requests");
4491                 err = -EIO;
4492         }
4493
4494         return err;
4495 }
4496 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational);
4497
4498 /**
4499  * ufshcd_hba_stop - Send controller to reset state
4500  * @hba: per adapter instance
4501  */
4502 void ufshcd_hba_stop(struct ufs_hba *hba)
4503 {
4504         unsigned long flags;
4505         int err;
4506
4507         /*
4508          * Obtain the host lock to prevent that the controller is disabled
4509          * while the UFS interrupt handler is active on another CPU.
4510          */
4511         spin_lock_irqsave(hba->host->host_lock, flags);
4512         ufshcd_writel(hba, CONTROLLER_DISABLE,  REG_CONTROLLER_ENABLE);
4513         spin_unlock_irqrestore(hba->host->host_lock, flags);
4514
4515         err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4516                                         CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4517                                         10, 1);
4518         if (err)
4519                 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4520 }
4521 EXPORT_SYMBOL_GPL(ufshcd_hba_stop);
4522
4523 /**
4524  * ufshcd_hba_execute_hce - initialize the controller
4525  * @hba: per adapter instance
4526  *
4527  * The controller resets itself and controller firmware initialization
4528  * sequence kicks off. When controller is ready it will set
4529  * the Host Controller Enable bit to 1.
4530  *
4531  * Returns 0 on success, non-zero value on failure
4532  */
4533 static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
4534 {
4535         int retry_outer = 3;
4536         int retry_inner;
4537
4538 start:
4539         if (!ufshcd_is_hba_active(hba))
4540                 /* change controller state to "reset state" */
4541                 ufshcd_hba_stop(hba);
4542
4543         /* UniPro link is disabled at this point */
4544         ufshcd_set_link_off(hba);
4545
4546         ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4547
4548         /* start controller initialization sequence */
4549         ufshcd_hba_start(hba);
4550
4551         /*
4552          * To initialize a UFS host controller HCE bit must be set to 1.
4553          * During initialization the HCE bit value changes from 1->0->1.
4554          * When the host controller completes initialization sequence
4555          * it sets the value of HCE bit to 1. The same HCE bit is read back
4556          * to check if the controller has completed initialization sequence.
4557          * So without this delay the value HCE = 1, set in the previous
4558          * instruction might be read back.
4559          * This delay can be changed based on the controller.
4560          */
4561         ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100);
4562
4563         /* wait for the host controller to complete initialization */
4564         retry_inner = 50;
4565         while (ufshcd_is_hba_active(hba)) {
4566                 if (retry_inner) {
4567                         retry_inner--;
4568                 } else {
4569                         dev_err(hba->dev,
4570                                 "Controller enable failed\n");
4571                         if (retry_outer) {
4572                                 retry_outer--;
4573                                 goto start;
4574                         }
4575                         return -EIO;
4576                 }
4577                 usleep_range(1000, 1100);
4578         }
4579
4580         /* enable UIC related interrupts */
4581         ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4582
4583         ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4584
4585         return 0;
4586 }
4587
4588 int ufshcd_hba_enable(struct ufs_hba *hba)
4589 {
4590         int ret;
4591
4592         if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4593                 ufshcd_set_link_off(hba);
4594                 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4595
4596                 /* enable UIC related interrupts */
4597                 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4598                 ret = ufshcd_dme_reset(hba);
4599                 if (!ret) {
4600                         ret = ufshcd_dme_enable(hba);
4601                         if (!ret)
4602                                 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4603                         if (ret)
4604                                 dev_err(hba->dev,
4605                                         "Host controller enable failed with non-hce\n");
4606                 }
4607         } else {
4608                 ret = ufshcd_hba_execute_hce(hba);
4609         }
4610
4611         return ret;
4612 }
4613 EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
4614
4615 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4616 {
4617         int tx_lanes = 0, i, err = 0;
4618
4619         if (!peer)
4620                 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4621                                &tx_lanes);
4622         else
4623                 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4624                                     &tx_lanes);
4625         for (i = 0; i < tx_lanes; i++) {
4626                 if (!peer)
4627                         err = ufshcd_dme_set(hba,
4628                                 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4629                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4630                                         0);
4631                 else
4632                         err = ufshcd_dme_peer_set(hba,
4633                                 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4634                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4635                                         0);
4636                 if (err) {
4637                         dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4638                                 __func__, peer, i, err);
4639                         break;
4640                 }
4641         }
4642
4643         return err;
4644 }
4645
4646 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4647 {
4648         return ufshcd_disable_tx_lcc(hba, true);
4649 }
4650
4651 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val)
4652 {
4653         struct ufs_event_hist *e;
4654
4655         if (id >= UFS_EVT_CNT)
4656                 return;
4657
4658         e = &hba->ufs_stats.event[id];
4659         e->val[e->pos] = val;
4660         e->tstamp[e->pos] = ktime_get();
4661         e->cnt += 1;
4662         e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH;
4663
4664         ufshcd_vops_event_notify(hba, id, &val);
4665 }
4666 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist);
4667
4668 /**
4669  * ufshcd_link_startup - Initialize unipro link startup
4670  * @hba: per adapter instance
4671  *
4672  * Returns 0 for success, non-zero in case of failure
4673  */
4674 static int ufshcd_link_startup(struct ufs_hba *hba)
4675 {
4676         int ret;
4677         int retries = DME_LINKSTARTUP_RETRIES;
4678         bool link_startup_again = false;
4679
4680         /*
4681          * If UFS device isn't active then we will have to issue link startup
4682          * 2 times to make sure the device state move to active.
4683          */
4684         if (!ufshcd_is_ufs_dev_active(hba))
4685                 link_startup_again = true;
4686
4687 link_startup:
4688         do {
4689                 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
4690
4691                 ret = ufshcd_dme_link_startup(hba);
4692
4693                 /* check if device is detected by inter-connect layer */
4694                 if (!ret && !ufshcd_is_device_present(hba)) {
4695                         ufshcd_update_evt_hist(hba,
4696                                                UFS_EVT_LINK_STARTUP_FAIL,
4697                                                0);
4698                         dev_err(hba->dev, "%s: Device not present\n", __func__);
4699                         ret = -ENXIO;
4700                         goto out;
4701                 }
4702
4703                 /*
4704                  * DME link lost indication is only received when link is up,
4705                  * but we can't be sure if the link is up until link startup
4706                  * succeeds. So reset the local Uni-Pro and try again.
4707                  */
4708                 if (ret && ufshcd_hba_enable(hba)) {
4709                         ufshcd_update_evt_hist(hba,
4710                                                UFS_EVT_LINK_STARTUP_FAIL,
4711                                                (u32)ret);
4712                         goto out;
4713                 }
4714         } while (ret && retries--);
4715
4716         if (ret) {
4717                 /* failed to get the link up... retire */
4718                 ufshcd_update_evt_hist(hba,
4719                                        UFS_EVT_LINK_STARTUP_FAIL,
4720                                        (u32)ret);
4721                 goto out;
4722         }
4723
4724         if (link_startup_again) {
4725                 link_startup_again = false;
4726                 retries = DME_LINKSTARTUP_RETRIES;
4727                 goto link_startup;
4728         }
4729
4730         /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4731         ufshcd_init_pwr_info(hba);
4732         ufshcd_print_pwr_info(hba);
4733
4734         if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4735                 ret = ufshcd_disable_device_tx_lcc(hba);
4736                 if (ret)
4737                         goto out;
4738         }
4739
4740         /* Include any host controller configuration via UIC commands */
4741         ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4742         if (ret)
4743                 goto out;
4744
4745         /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */
4746         ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
4747         ret = ufshcd_make_hba_operational(hba);
4748 out:
4749         if (ret) {
4750                 dev_err(hba->dev, "link startup failed %d\n", ret);
4751                 ufshcd_print_host_state(hba);
4752                 ufshcd_print_pwr_info(hba);
4753                 ufshcd_print_evt_hist(hba);
4754         }
4755         return ret;
4756 }
4757
4758 /**
4759  * ufshcd_verify_dev_init() - Verify device initialization
4760  * @hba: per-adapter instance
4761  *
4762  * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4763  * device Transport Protocol (UTP) layer is ready after a reset.
4764  * If the UTP layer at the device side is not initialized, it may
4765  * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4766  * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4767  */
4768 static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4769 {
4770         int err = 0;
4771         int retries;
4772
4773         ufshcd_hold(hba, false);
4774         mutex_lock(&hba->dev_cmd.lock);
4775         for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4776                 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4777                                                NOP_OUT_TIMEOUT);
4778
4779                 if (!err || err == -ETIMEDOUT)
4780                         break;
4781
4782                 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4783         }
4784         mutex_unlock(&hba->dev_cmd.lock);
4785         ufshcd_release(hba);
4786
4787         if (err)
4788                 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4789         return err;
4790 }
4791
4792 /**
4793  * ufshcd_set_queue_depth - set lun queue depth
4794  * @sdev: pointer to SCSI device
4795  *
4796  * Read bLUQueueDepth value and activate scsi tagged command
4797  * queueing. For WLUN, queue depth is set to 1. For best-effort
4798  * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4799  * value that host can queue.
4800  */
4801 static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4802 {
4803         int ret = 0;
4804         u8 lun_qdepth;
4805         struct ufs_hba *hba;
4806
4807         hba = shost_priv(sdev->host);
4808
4809         lun_qdepth = hba->nutrs;
4810         ret = ufshcd_read_unit_desc_param(hba,
4811                                           ufshcd_scsi_to_upiu_lun(sdev->lun),
4812                                           UNIT_DESC_PARAM_LU_Q_DEPTH,
4813                                           &lun_qdepth,
4814                                           sizeof(lun_qdepth));
4815
4816         /* Some WLUN doesn't support unit descriptor */
4817         if (ret == -EOPNOTSUPP)
4818                 lun_qdepth = 1;
4819         else if (!lun_qdepth)
4820                 /* eventually, we can figure out the real queue depth */
4821                 lun_qdepth = hba->nutrs;
4822         else
4823                 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4824
4825         dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4826                         __func__, lun_qdepth);
4827         scsi_change_queue_depth(sdev, lun_qdepth);
4828 }
4829
4830 /*
4831  * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4832  * @hba: per-adapter instance
4833  * @lun: UFS device lun id
4834  * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4835  *
4836  * Returns 0 in case of success and b_lu_write_protect status would be returned
4837  * @b_lu_write_protect parameter.
4838  * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4839  * Returns -EINVAL in case of invalid parameters passed to this function.
4840  */
4841 static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4842                             u8 lun,
4843                             u8 *b_lu_write_protect)
4844 {
4845         int ret;
4846
4847         if (!b_lu_write_protect)
4848                 ret = -EINVAL;
4849         /*
4850          * According to UFS device spec, RPMB LU can't be write
4851          * protected so skip reading bLUWriteProtect parameter for
4852          * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4853          */
4854         else if (lun >= hba->dev_info.max_lu_supported)
4855                 ret = -ENOTSUPP;
4856         else
4857                 ret = ufshcd_read_unit_desc_param(hba,
4858                                           lun,
4859                                           UNIT_DESC_PARAM_LU_WR_PROTECT,
4860                                           b_lu_write_protect,
4861                                           sizeof(*b_lu_write_protect));
4862         return ret;
4863 }
4864
4865 /**
4866  * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4867  * status
4868  * @hba: per-adapter instance
4869  * @sdev: pointer to SCSI device
4870  *
4871  */
4872 static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4873                                                     struct scsi_device *sdev)
4874 {
4875         if (hba->dev_info.f_power_on_wp_en &&
4876             !hba->dev_info.is_lu_power_on_wp) {
4877                 u8 b_lu_write_protect;
4878
4879                 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4880                                       &b_lu_write_protect) &&
4881                     (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4882                         hba->dev_info.is_lu_power_on_wp = true;
4883         }
4884 }
4885
4886 /**
4887  * ufshcd_setup_links - associate link b/w device wlun and other luns
4888  * @sdev: pointer to SCSI device
4889  * @hba: pointer to ufs hba
4890  */
4891 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev)
4892 {
4893         struct device_link *link;
4894
4895         /*
4896          * Device wlun is the supplier & rest of the luns are consumers.
4897          * This ensures that device wlun suspends after all other luns.
4898          */
4899         if (hba->sdev_ufs_device) {
4900                 link = device_link_add(&sdev->sdev_gendev,
4901                                        &hba->sdev_ufs_device->sdev_gendev,
4902                                        DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
4903                 if (!link) {
4904                         dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n",
4905                                 dev_name(&hba->sdev_ufs_device->sdev_gendev));
4906                         return;
4907                 }
4908                 hba->luns_avail--;
4909                 /* Ignore REPORT_LUN wlun probing */
4910                 if (hba->luns_avail == 1) {
4911                         ufshcd_rpm_put(hba);
4912                         return;
4913                 }
4914         } else {
4915                 /*
4916                  * Device wlun is probed. The assumption is that WLUNs are
4917                  * scanned before other LUNs.
4918                  */
4919                 hba->luns_avail--;
4920         }
4921 }
4922
4923 /**
4924  * ufshcd_slave_alloc - handle initial SCSI device configurations
4925  * @sdev: pointer to SCSI device
4926  *
4927  * Returns success
4928  */
4929 static int ufshcd_slave_alloc(struct scsi_device *sdev)
4930 {
4931         struct ufs_hba *hba;
4932
4933         hba = shost_priv(sdev->host);
4934
4935         /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4936         sdev->use_10_for_ms = 1;
4937
4938         /* DBD field should be set to 1 in mode sense(10) */
4939         sdev->set_dbd_for_ms = 1;
4940
4941         /* allow SCSI layer to restart the device in case of errors */
4942         sdev->allow_restart = 1;
4943
4944         /* REPORT SUPPORTED OPERATION CODES is not supported */
4945         sdev->no_report_opcodes = 1;
4946
4947         /* WRITE_SAME command is not supported */
4948         sdev->no_write_same = 1;
4949
4950         ufshcd_set_queue_depth(sdev);
4951
4952         ufshcd_get_lu_power_on_wp_status(hba, sdev);
4953
4954         ufshcd_setup_links(hba, sdev);
4955
4956         return 0;
4957 }
4958
4959 /**
4960  * ufshcd_change_queue_depth - change queue depth
4961  * @sdev: pointer to SCSI device
4962  * @depth: required depth to set
4963  *
4964  * Change queue depth and make sure the max. limits are not crossed.
4965  */
4966 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4967 {
4968         struct ufs_hba *hba = shost_priv(sdev->host);
4969
4970         if (depth > hba->nutrs)
4971                 depth = hba->nutrs;
4972         return scsi_change_queue_depth(sdev, depth);
4973 }
4974
4975 static void ufshcd_hpb_destroy(struct ufs_hba *hba, struct scsi_device *sdev)
4976 {
4977         /* skip well-known LU */
4978         if ((sdev->lun >= UFS_UPIU_MAX_UNIT_NUM_ID) ||
4979             !(hba->dev_info.hpb_enabled) || !ufshpb_is_allowed(hba))
4980                 return;
4981
4982         ufshpb_destroy_lu(hba, sdev);
4983 }
4984
4985 static void ufshcd_hpb_configure(struct ufs_hba *hba, struct scsi_device *sdev)
4986 {
4987         /* skip well-known LU */
4988         if ((sdev->lun >= UFS_UPIU_MAX_UNIT_NUM_ID) ||
4989             !(hba->dev_info.hpb_enabled) || !ufshpb_is_allowed(hba))
4990                 return;
4991
4992         ufshpb_init_hpb_lu(hba, sdev);
4993 }
4994
4995 /**
4996  * ufshcd_slave_configure - adjust SCSI device configurations
4997  * @sdev: pointer to SCSI device
4998  */
4999 static int ufshcd_slave_configure(struct scsi_device *sdev)
5000 {
5001         struct ufs_hba *hba = shost_priv(sdev->host);
5002         struct request_queue *q = sdev->request_queue;
5003
5004         ufshcd_hpb_configure(hba, sdev);
5005
5006         blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
5007         if (hba->quirks & UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE)
5008                 blk_queue_update_dma_alignment(q, PAGE_SIZE - 1);
5009         /*
5010          * Block runtime-pm until all consumers are added.
5011          * Refer ufshcd_setup_links().
5012          */
5013         if (is_device_wlun(sdev))
5014                 pm_runtime_get_noresume(&sdev->sdev_gendev);
5015         else if (ufshcd_is_rpm_autosuspend_allowed(hba))
5016                 sdev->rpm_autosuspend = 1;
5017
5018         ufshcd_crypto_setup_rq_keyslot_manager(hba, q);
5019
5020         return 0;
5021 }
5022
5023 /**
5024  * ufshcd_slave_destroy - remove SCSI device configurations
5025  * @sdev: pointer to SCSI device
5026  */
5027 static void ufshcd_slave_destroy(struct scsi_device *sdev)
5028 {
5029         struct ufs_hba *hba;
5030
5031         hba = shost_priv(sdev->host);
5032
5033         ufshcd_hpb_destroy(hba, sdev);
5034
5035         /* Drop the reference as it won't be needed anymore */
5036         if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
5037                 unsigned long flags;
5038
5039                 spin_lock_irqsave(hba->host->host_lock, flags);
5040                 hba->sdev_ufs_device = NULL;
5041                 spin_unlock_irqrestore(hba->host->host_lock, flags);
5042         }
5043 }
5044
5045 /**
5046  * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
5047  * @lrbp: pointer to local reference block of completed command
5048  * @scsi_status: SCSI command status
5049  *
5050  * Returns value base on SCSI command status
5051  */
5052 static inline int
5053 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
5054 {
5055         int result = 0;
5056
5057         switch (scsi_status) {
5058         case SAM_STAT_CHECK_CONDITION:
5059                 ufshcd_copy_sense_data(lrbp);
5060                 fallthrough;
5061         case SAM_STAT_GOOD:
5062                 result |= DID_OK << 16 | scsi_status;
5063                 break;
5064         case SAM_STAT_TASK_SET_FULL:
5065         case SAM_STAT_BUSY:
5066         case SAM_STAT_TASK_ABORTED:
5067                 ufshcd_copy_sense_data(lrbp);
5068                 result |= scsi_status;
5069                 break;
5070         default:
5071                 result |= DID_ERROR << 16;
5072                 break;
5073         } /* end of switch */
5074
5075         return result;
5076 }
5077
5078 /**
5079  * ufshcd_transfer_rsp_status - Get overall status of the response
5080  * @hba: per adapter instance
5081  * @lrbp: pointer to local reference block of completed command
5082  *
5083  * Returns result of the command to notify SCSI midlayer
5084  */
5085 static inline int
5086 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
5087 {
5088         int result = 0;
5089         int scsi_status;
5090         int ocs;
5091
5092         /* overall command status of utrd */
5093         ocs = ufshcd_get_tr_ocs(lrbp);
5094
5095         if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) {
5096                 if (be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_1) &
5097                                         MASK_RSP_UPIU_RESULT)
5098                         ocs = OCS_SUCCESS;
5099         }
5100
5101         switch (ocs) {
5102         case OCS_SUCCESS:
5103                 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
5104                 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5105                 switch (result) {
5106                 case UPIU_TRANSACTION_RESPONSE:
5107                         /*
5108                          * get the response UPIU result to extract
5109                          * the SCSI command status
5110                          */
5111                         result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
5112
5113                         /*
5114                          * get the result based on SCSI status response
5115                          * to notify the SCSI midlayer of the command status
5116                          */
5117                         scsi_status = result & MASK_SCSI_STATUS;
5118                         result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
5119
5120                         /*
5121                          * Currently we are only supporting BKOPs exception
5122                          * events hence we can ignore BKOPs exception event
5123                          * during power management callbacks. BKOPs exception
5124                          * event is not expected to be raised in runtime suspend
5125                          * callback as it allows the urgent bkops.
5126                          * During system suspend, we are anyway forcefully
5127                          * disabling the bkops and if urgent bkops is needed
5128                          * it will be enabled on system resume. Long term
5129                          * solution could be to abort the system suspend if
5130                          * UFS device needs urgent BKOPs.
5131                          */
5132                         if (!hba->pm_op_in_progress &&
5133                             !ufshcd_eh_in_progress(hba) &&
5134                             ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
5135                                 /* Flushed in suspend */
5136                                 schedule_work(&hba->eeh_work);
5137
5138                         if (scsi_status == SAM_STAT_GOOD)
5139                                 ufshpb_rsp_upiu(hba, lrbp);
5140                         break;
5141                 case UPIU_TRANSACTION_REJECT_UPIU:
5142                         /* TODO: handle Reject UPIU Response */
5143                         result = DID_ERROR << 16;
5144                         dev_err(hba->dev,
5145                                 "Reject UPIU not fully implemented\n");
5146                         break;
5147                 default:
5148                         dev_err(hba->dev,
5149                                 "Unexpected request response code = %x\n",
5150                                 result);
5151                         result = DID_ERROR << 16;
5152                         break;
5153                 }
5154                 break;
5155         case OCS_ABORTED:
5156                 result |= DID_ABORT << 16;
5157                 break;
5158         case OCS_INVALID_COMMAND_STATUS:
5159                 result |= DID_REQUEUE << 16;
5160                 break;
5161         case OCS_INVALID_CMD_TABLE_ATTR:
5162         case OCS_INVALID_PRDT_ATTR:
5163         case OCS_MISMATCH_DATA_BUF_SIZE:
5164         case OCS_MISMATCH_RESP_UPIU_SIZE:
5165         case OCS_PEER_COMM_FAILURE:
5166         case OCS_FATAL_ERROR:
5167         case OCS_DEVICE_FATAL_ERROR:
5168         case OCS_INVALID_CRYPTO_CONFIG:
5169         case OCS_GENERAL_CRYPTO_ERROR:
5170         default:
5171                 result |= DID_ERROR << 16;
5172                 dev_err(hba->dev,
5173                                 "OCS error from controller = %x for tag %d\n",
5174                                 ocs, lrbp->task_tag);
5175                 ufshcd_print_evt_hist(hba);
5176                 ufshcd_print_host_state(hba);
5177                 break;
5178         } /* end of switch */
5179
5180         if ((host_byte(result) != DID_OK) &&
5181             (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs)
5182                 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
5183         return result;
5184 }
5185
5186 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
5187                                          u32 intr_mask)
5188 {
5189         if (!ufshcd_is_auto_hibern8_supported(hba) ||
5190             !ufshcd_is_auto_hibern8_enabled(hba))
5191                 return false;
5192
5193         if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
5194                 return false;
5195
5196         if (hba->active_uic_cmd &&
5197             (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
5198             hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
5199                 return false;
5200
5201         return true;
5202 }
5203
5204 /**
5205  * ufshcd_uic_cmd_compl - handle completion of uic command
5206  * @hba: per adapter instance
5207  * @intr_status: interrupt status generated by the controller
5208  *
5209  * Returns
5210  *  IRQ_HANDLED - If interrupt is valid
5211  *  IRQ_NONE    - If invalid interrupt
5212  */
5213 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
5214 {
5215         irqreturn_t retval = IRQ_NONE;
5216
5217         spin_lock(hba->host->host_lock);
5218         if (ufshcd_is_auto_hibern8_error(hba, intr_status))
5219                 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
5220
5221         if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
5222                 hba->active_uic_cmd->argument2 |=
5223                         ufshcd_get_uic_cmd_result(hba);
5224                 hba->active_uic_cmd->argument3 =
5225                         ufshcd_get_dme_attr_val(hba);
5226                 if (!hba->uic_async_done)
5227                         hba->active_uic_cmd->cmd_active = 0;
5228                 complete(&hba->active_uic_cmd->done);
5229                 retval = IRQ_HANDLED;
5230         }
5231
5232         if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
5233                 hba->active_uic_cmd->cmd_active = 0;
5234                 complete(hba->uic_async_done);
5235                 retval = IRQ_HANDLED;
5236         }
5237
5238         if (retval == IRQ_HANDLED)
5239                 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd,
5240                                              UFS_CMD_COMP);
5241         spin_unlock(hba->host->host_lock);
5242         return retval;
5243 }
5244
5245 /**
5246  * __ufshcd_transfer_req_compl - handle SCSI and query command completion
5247  * @hba: per adapter instance
5248  * @completed_reqs: bitmask that indicates which requests to complete
5249  * @retry_requests: whether to ask the SCSI core to retry completed requests
5250  */
5251 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
5252                                         unsigned long completed_reqs,
5253                                         bool retry_requests)
5254 {
5255         struct ufshcd_lrb *lrbp;
5256         struct scsi_cmnd *cmd;
5257         int result;
5258         int index;
5259         bool update_scaling = false;
5260
5261         for_each_set_bit(index, &completed_reqs, hba->nutrs) {
5262                 lrbp = &hba->lrb[index];
5263                 lrbp->compl_time_stamp = ktime_get();
5264                 cmd = lrbp->cmd;
5265                 if (cmd) {
5266                         if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
5267                                 ufshcd_update_monitor(hba, lrbp);
5268                         ufshcd_add_command_trace(hba, index, UFS_CMD_COMP);
5269                         result = retry_requests ? DID_BUS_BUSY << 16 :
5270                                 ufshcd_transfer_rsp_status(hba, lrbp);
5271                         scsi_dma_unmap(cmd);
5272                         cmd->result = result;
5273                         /* Mark completed command as NULL in LRB */
5274                         lrbp->cmd = NULL;
5275                         /* Do not touch lrbp after scsi done */
5276                         cmd->scsi_done(cmd);
5277                         ufshcd_release(hba);
5278                         update_scaling = true;
5279                 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
5280                         lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
5281                         if (hba->dev_cmd.complete) {
5282                                 ufshcd_add_command_trace(hba, index,
5283                                                          UFS_DEV_COMP);
5284                                 complete(hba->dev_cmd.complete);
5285                                 update_scaling = true;
5286                         }
5287                 }
5288                 if (update_scaling)
5289                         ufshcd_clk_scaling_update_busy(hba);
5290         }
5291 }
5292
5293 /**
5294  * ufshcd_transfer_req_compl - handle SCSI and query command completion
5295  * @hba: per adapter instance
5296  * @retry_requests: whether or not to ask to retry requests
5297  *
5298  * Returns
5299  *  IRQ_HANDLED - If interrupt is valid
5300  *  IRQ_NONE    - If invalid interrupt
5301  */
5302 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba,
5303                                              bool retry_requests)
5304 {
5305         unsigned long completed_reqs, flags;
5306         u32 tr_doorbell;
5307
5308         /* Resetting interrupt aggregation counters first and reading the
5309          * DOOR_BELL afterward allows us to handle all the completed requests.
5310          * In order to prevent other interrupts starvation the DB is read once
5311          * after reset. The down side of this solution is the possibility of
5312          * false interrupt if device completes another request after resetting
5313          * aggregation and before reading the DB.
5314          */
5315         if (ufshcd_is_intr_aggr_allowed(hba) &&
5316             !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
5317                 ufshcd_reset_intr_aggr(hba);
5318
5319         if (ufs_fail_completion())
5320                 return IRQ_HANDLED;
5321
5322         spin_lock_irqsave(&hba->outstanding_lock, flags);
5323         tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5324         completed_reqs = ~tr_doorbell & hba->outstanding_reqs;
5325         WARN_ONCE(completed_reqs & ~hba->outstanding_reqs,
5326                   "completed: %#lx; outstanding: %#lx\n", completed_reqs,
5327                   hba->outstanding_reqs);
5328         hba->outstanding_reqs &= ~completed_reqs;
5329         spin_unlock_irqrestore(&hba->outstanding_lock, flags);
5330
5331         if (completed_reqs) {
5332                 __ufshcd_transfer_req_compl(hba, completed_reqs,
5333                                             retry_requests);
5334                 return IRQ_HANDLED;
5335         } else {
5336                 return IRQ_NONE;
5337         }
5338 }
5339
5340 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask)
5341 {
5342         return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5343                                        QUERY_ATTR_IDN_EE_CONTROL, 0, 0,
5344                                        &ee_ctrl_mask);
5345 }
5346
5347 int ufshcd_write_ee_control(struct ufs_hba *hba)
5348 {
5349         int err;
5350
5351         mutex_lock(&hba->ee_ctrl_mutex);
5352         err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask);
5353         mutex_unlock(&hba->ee_ctrl_mutex);
5354         if (err)
5355                 dev_err(hba->dev, "%s: failed to write ee control %d\n",
5356                         __func__, err);
5357         return err;
5358 }
5359
5360 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, u16 *other_mask,
5361                              u16 set, u16 clr)
5362 {
5363         u16 new_mask, ee_ctrl_mask;
5364         int err = 0;
5365
5366         mutex_lock(&hba->ee_ctrl_mutex);
5367         new_mask = (*mask & ~clr) | set;
5368         ee_ctrl_mask = new_mask | *other_mask;
5369         if (ee_ctrl_mask != hba->ee_ctrl_mask)
5370                 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask);
5371         /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */
5372         if (!err) {
5373                 hba->ee_ctrl_mask = ee_ctrl_mask;
5374                 *mask = new_mask;
5375         }
5376         mutex_unlock(&hba->ee_ctrl_mutex);
5377         return err;
5378 }
5379
5380 /**
5381  * ufshcd_disable_ee - disable exception event
5382  * @hba: per-adapter instance
5383  * @mask: exception event to disable
5384  *
5385  * Disables exception event in the device so that the EVENT_ALERT
5386  * bit is not set.
5387  *
5388  * Returns zero on success, non-zero error value on failure.
5389  */
5390 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
5391 {
5392         return ufshcd_update_ee_drv_mask(hba, 0, mask);
5393 }
5394
5395 /**
5396  * ufshcd_enable_ee - enable exception event
5397  * @hba: per-adapter instance
5398  * @mask: exception event to enable
5399  *
5400  * Enable corresponding exception event in the device to allow
5401  * device to alert host in critical scenarios.
5402  *
5403  * Returns zero on success, non-zero error value on failure.
5404  */
5405 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
5406 {
5407         return ufshcd_update_ee_drv_mask(hba, mask, 0);
5408 }
5409
5410 /**
5411  * ufshcd_enable_auto_bkops - Allow device managed BKOPS
5412  * @hba: per-adapter instance
5413  *
5414  * Allow device to manage background operations on its own. Enabling
5415  * this might lead to inconsistent latencies during normal data transfers
5416  * as the device is allowed to manage its own way of handling background
5417  * operations.
5418  *
5419  * Returns zero on success, non-zero on failure.
5420  */
5421 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
5422 {
5423         int err = 0;
5424
5425         if (hba->auto_bkops_enabled)
5426                 goto out;
5427
5428         err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
5429                         QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5430         if (err) {
5431                 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
5432                                 __func__, err);
5433                 goto out;
5434         }
5435
5436         hba->auto_bkops_enabled = true;
5437         trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
5438
5439         /* No need of URGENT_BKOPS exception from the device */
5440         err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5441         if (err)
5442                 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
5443                                 __func__, err);
5444 out:
5445         return err;
5446 }
5447
5448 /**
5449  * ufshcd_disable_auto_bkops - block device in doing background operations
5450  * @hba: per-adapter instance
5451  *
5452  * Disabling background operations improves command response latency but
5453  * has drawback of device moving into critical state where the device is
5454  * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
5455  * host is idle so that BKOPS are managed effectively without any negative
5456  * impacts.
5457  *
5458  * Returns zero on success, non-zero on failure.
5459  */
5460 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5461 {
5462         int err = 0;
5463
5464         if (!hba->auto_bkops_enabled)
5465                 goto out;
5466
5467         /*
5468          * If host assisted BKOPs is to be enabled, make sure
5469          * urgent bkops exception is allowed.
5470          */
5471         err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5472         if (err) {
5473                 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5474                                 __func__, err);
5475                 goto out;
5476         }
5477
5478         err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
5479                         QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5480         if (err) {
5481                 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5482                                 __func__, err);
5483                 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5484                 goto out;
5485         }
5486
5487         hba->auto_bkops_enabled = false;
5488         trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
5489         hba->is_urgent_bkops_lvl_checked = false;
5490 out:
5491         return err;
5492 }
5493
5494 /**
5495  * ufshcd_force_reset_auto_bkops - force reset auto bkops state
5496  * @hba: per adapter instance
5497  *
5498  * After a device reset the device may toggle the BKOPS_EN flag
5499  * to default value. The s/w tracking variables should be updated
5500  * as well. This function would change the auto-bkops state based on
5501  * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
5502  */
5503 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
5504 {
5505         if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5506                 hba->auto_bkops_enabled = false;
5507                 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5508                 ufshcd_enable_auto_bkops(hba);
5509         } else {
5510                 hba->auto_bkops_enabled = true;
5511                 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5512                 ufshcd_disable_auto_bkops(hba);
5513         }
5514         hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
5515         hba->is_urgent_bkops_lvl_checked = false;
5516 }
5517
5518 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5519 {
5520         return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5521                         QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5522 }
5523
5524 /**
5525  * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
5526  * @hba: per-adapter instance
5527  * @status: bkops_status value
5528  *
5529  * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5530  * flag in the device to permit background operations if the device
5531  * bkops_status is greater than or equal to "status" argument passed to
5532  * this function, disable otherwise.
5533  *
5534  * Returns 0 for success, non-zero in case of failure.
5535  *
5536  * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5537  * to know whether auto bkops is enabled or disabled after this function
5538  * returns control to it.
5539  */
5540 static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5541                              enum bkops_status status)
5542 {
5543         int err;
5544         u32 curr_status = 0;
5545
5546         err = ufshcd_get_bkops_status(hba, &curr_status);
5547         if (err) {
5548                 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5549                                 __func__, err);
5550                 goto out;
5551         } else if (curr_status > BKOPS_STATUS_MAX) {
5552                 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5553                                 __func__, curr_status);
5554                 err = -EINVAL;
5555                 goto out;
5556         }
5557
5558         if (curr_status >= status)
5559                 err = ufshcd_enable_auto_bkops(hba);
5560         else
5561                 err = ufshcd_disable_auto_bkops(hba);
5562 out:
5563         return err;
5564 }
5565
5566 /**
5567  * ufshcd_urgent_bkops - handle urgent bkops exception event
5568  * @hba: per-adapter instance
5569  *
5570  * Enable fBackgroundOpsEn flag in the device to permit background
5571  * operations.
5572  *
5573  * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5574  * and negative error value for any other failure.
5575  */
5576 static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5577 {
5578         return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
5579 }
5580
5581 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5582 {
5583         return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5584                         QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5585 }
5586
5587 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5588 {
5589         int err;
5590         u32 curr_status = 0;
5591
5592         if (hba->is_urgent_bkops_lvl_checked)
5593                 goto enable_auto_bkops;
5594
5595         err = ufshcd_get_bkops_status(hba, &curr_status);
5596         if (err) {
5597                 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5598                                 __func__, err);
5599                 goto out;
5600         }
5601
5602         /*
5603          * We are seeing that some devices are raising the urgent bkops
5604          * exception events even when BKOPS status doesn't indicate performace
5605          * impacted or critical. Handle these device by determining their urgent
5606          * bkops status at runtime.
5607          */
5608         if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5609                 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5610                                 __func__, curr_status);
5611                 /* update the current status as the urgent bkops level */
5612                 hba->urgent_bkops_lvl = curr_status;
5613                 hba->is_urgent_bkops_lvl_checked = true;
5614         }
5615
5616 enable_auto_bkops:
5617         err = ufshcd_enable_auto_bkops(hba);
5618 out:
5619         if (err < 0)
5620                 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5621                                 __func__, err);
5622 }
5623
5624 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn)
5625 {
5626         u8 index;
5627         enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG :
5628                                    UPIU_QUERY_OPCODE_CLEAR_FLAG;
5629
5630         index = ufshcd_wb_get_query_index(hba);
5631         return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL);
5632 }
5633
5634 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable)
5635 {
5636         int ret;
5637
5638         if (!ufshcd_is_wb_allowed(hba))
5639                 return 0;
5640
5641         if (!(enable ^ hba->dev_info.wb_enabled))
5642                 return 0;
5643
5644         ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN);
5645         if (ret) {
5646                 dev_err(hba->dev, "%s Write Booster %s failed %d\n",
5647                         __func__, enable ? "enable" : "disable", ret);
5648                 return ret;
5649         }
5650
5651         hba->dev_info.wb_enabled = enable;
5652         dev_info(hba->dev, "%s Write Booster %s\n",
5653                         __func__, enable ? "enabled" : "disabled");
5654
5655         return ret;
5656 }
5657
5658 static void ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set)
5659 {
5660         int ret;
5661
5662         ret = __ufshcd_wb_toggle(hba, set,
5663                         QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8);
5664         if (ret) {
5665                 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed: %d\n",
5666                         __func__, set ? "enable" : "disable", ret);
5667                 return;
5668         }
5669         dev_dbg(hba->dev, "%s WB-Buf Flush during H8 %s\n",
5670                         __func__, set ? "enabled" : "disabled");
5671 }
5672
5673 static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable)
5674 {
5675         int ret;
5676
5677         if (!ufshcd_is_wb_allowed(hba) ||
5678             hba->dev_info.wb_buf_flush_enabled == enable)
5679                 return;
5680
5681         ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN);
5682         if (ret) {
5683                 dev_err(hba->dev, "%s WB-Buf Flush %s failed %d\n", __func__,
5684                         enable ? "enable" : "disable", ret);
5685                 return;
5686         }
5687
5688         hba->dev_info.wb_buf_flush_enabled = enable;
5689
5690         dev_dbg(hba->dev, "%s WB-Buf Flush %s\n",
5691                         __func__, enable ? "enabled" : "disabled");
5692 }
5693
5694 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba,
5695                                                 u32 avail_buf)
5696 {
5697         u32 cur_buf;
5698         int ret;
5699         u8 index;
5700
5701         index = ufshcd_wb_get_query_index(hba);
5702         ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5703                                               QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE,
5704                                               index, 0, &cur_buf);
5705         if (ret) {
5706                 dev_err(hba->dev, "%s dCurWriteBoosterBufferSize read failed %d\n",
5707                         __func__, ret);
5708                 return false;
5709         }
5710
5711         if (!cur_buf) {
5712                 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n",
5713                          cur_buf);
5714                 return false;
5715         }
5716         /* Let it continue to flush when available buffer exceeds threshold */
5717         if (avail_buf < hba->vps->wb_flush_threshold)
5718                 return true;
5719
5720         return false;
5721 }
5722
5723 static bool ufshcd_wb_need_flush(struct ufs_hba *hba)
5724 {
5725         int ret;
5726         u32 avail_buf;
5727         u8 index;
5728
5729         if (!ufshcd_is_wb_allowed(hba))
5730                 return false;
5731         /*
5732          * The ufs device needs the vcc to be ON to flush.
5733          * With user-space reduction enabled, it's enough to enable flush
5734          * by checking only the available buffer. The threshold
5735          * defined here is > 90% full.
5736          * With user-space preserved enabled, the current-buffer
5737          * should be checked too because the wb buffer size can reduce
5738          * when disk tends to be full. This info is provided by current
5739          * buffer (dCurrentWriteBoosterBufferSize). There's no point in
5740          * keeping vcc on when current buffer is empty.
5741          */
5742         index = ufshcd_wb_get_query_index(hba);
5743         ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5744                                       QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE,
5745                                       index, 0, &avail_buf);
5746         if (ret) {
5747                 dev_warn(hba->dev, "%s dAvailableWriteBoosterBufferSize read failed %d\n",
5748                          __func__, ret);
5749                 return false;
5750         }
5751
5752         if (!hba->dev_info.b_presrv_uspc_en) {
5753                 if (avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10))
5754                         return true;
5755                 return false;
5756         }
5757
5758         return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf);
5759 }
5760
5761 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work)
5762 {
5763         struct ufs_hba *hba = container_of(to_delayed_work(work),
5764                                            struct ufs_hba,
5765                                            rpm_dev_flush_recheck_work);
5766         /*
5767          * To prevent unnecessary VCC power drain after device finishes
5768          * WriteBooster buffer flush or Auto BKOPs, force runtime resume
5769          * after a certain delay to recheck the threshold by next runtime
5770          * suspend.
5771          */
5772         ufshcd_rpm_get_sync(hba);
5773         ufshcd_rpm_put_sync(hba);
5774 }
5775
5776 /**
5777  * ufshcd_exception_event_handler - handle exceptions raised by device
5778  * @work: pointer to work data
5779  *
5780  * Read bExceptionEventStatus attribute from the device and handle the
5781  * exception event accordingly.
5782  */
5783 static void ufshcd_exception_event_handler(struct work_struct *work)
5784 {
5785         struct ufs_hba *hba;
5786         int err;
5787         u32 status = 0;
5788         hba = container_of(work, struct ufs_hba, eeh_work);
5789
5790         ufshcd_scsi_block_requests(hba);
5791         err = ufshcd_get_ee_status(hba, &status);
5792         if (err) {
5793                 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5794                                 __func__, err);
5795                 goto out;
5796         }
5797
5798         trace_ufshcd_exception_event(dev_name(hba->dev), status);
5799
5800         if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS)
5801                 ufshcd_bkops_exception_event_handler(hba);
5802
5803         ufs_debugfs_exception_event(hba, status);
5804 out:
5805         ufshcd_scsi_unblock_requests(hba);
5806         return;
5807 }
5808
5809 /* Complete requests that have door-bell cleared */
5810 static void ufshcd_complete_requests(struct ufs_hba *hba)
5811 {
5812         ufshcd_transfer_req_compl(hba, /*retry_requests=*/false);
5813         ufshcd_tmc_handler(hba);
5814 }
5815
5816 static void ufshcd_retry_aborted_requests(struct ufs_hba *hba)
5817 {
5818         ufshcd_transfer_req_compl(hba, /*retry_requests=*/true);
5819         ufshcd_tmc_handler(hba);
5820 }
5821
5822 /**
5823  * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
5824  *                              to recover from the DL NAC errors or not.
5825  * @hba: per-adapter instance
5826  *
5827  * Returns true if error handling is required, false otherwise
5828  */
5829 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5830 {
5831         unsigned long flags;
5832         bool err_handling = true;
5833
5834         spin_lock_irqsave(hba->host->host_lock, flags);
5835         /*
5836          * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
5837          * device fatal error and/or DL NAC & REPLAY timeout errors.
5838          */
5839         if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5840                 goto out;
5841
5842         if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5843             ((hba->saved_err & UIC_ERROR) &&
5844              (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5845                 goto out;
5846
5847         if ((hba->saved_err & UIC_ERROR) &&
5848             (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5849                 int err;
5850                 /*
5851                  * wait for 50ms to see if we can get any other errors or not.
5852                  */
5853                 spin_unlock_irqrestore(hba->host->host_lock, flags);
5854                 msleep(50);
5855                 spin_lock_irqsave(hba->host->host_lock, flags);
5856
5857                 /*
5858                  * now check if we have got any other severe errors other than
5859                  * DL NAC error?
5860                  */
5861                 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5862                     ((hba->saved_err & UIC_ERROR) &&
5863                     (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
5864                         goto out;
5865
5866                 /*
5867                  * As DL NAC is the only error received so far, send out NOP
5868                  * command to confirm if link is still active or not.
5869                  *   - If we don't get any response then do error recovery.
5870                  *   - If we get response then clear the DL NAC error bit.
5871                  */
5872
5873                 spin_unlock_irqrestore(hba->host->host_lock, flags);
5874                 err = ufshcd_verify_dev_init(hba);
5875                 spin_lock_irqsave(hba->host->host_lock, flags);
5876
5877                 if (err)
5878                         goto out;
5879
5880                 /* Link seems to be alive hence ignore the DL NAC errors */
5881                 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5882                         hba->saved_err &= ~UIC_ERROR;
5883                 /* clear NAC error */
5884                 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5885                 if (!hba->saved_uic_err)
5886                         err_handling = false;
5887         }
5888 out:
5889         spin_unlock_irqrestore(hba->host->host_lock, flags);
5890         return err_handling;
5891 }
5892
5893 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow)
5894 {
5895         down_write(&hba->clk_scaling_lock);
5896         hba->clk_scaling.is_allowed = allow;
5897         up_write(&hba->clk_scaling_lock);
5898 }
5899
5900 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend)
5901 {
5902         if (suspend) {
5903                 if (hba->clk_scaling.is_enabled)
5904                         ufshcd_suspend_clkscaling(hba);
5905                 ufshcd_clk_scaling_allow(hba, false);
5906         } else {
5907                 ufshcd_clk_scaling_allow(hba, true);
5908                 if (hba->clk_scaling.is_enabled)
5909                         ufshcd_resume_clkscaling(hba);
5910         }
5911 }
5912
5913 static void ufshcd_err_handling_prepare(struct ufs_hba *hba)
5914 {
5915         ufshcd_rpm_get_sync(hba);
5916         if (pm_runtime_status_suspended(&hba->sdev_ufs_device->sdev_gendev) ||
5917             hba->is_sys_suspended) {
5918                 enum ufs_pm_op pm_op;
5919
5920                 /*
5921                  * Don't assume anything of resume, if
5922                  * resume fails, irq and clocks can be OFF, and powers
5923                  * can be OFF or in LPM.
5924                  */
5925                 ufshcd_setup_hba_vreg(hba, true);
5926                 ufshcd_enable_irq(hba);
5927                 ufshcd_setup_vreg(hba, true);
5928                 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
5929                 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
5930                 ufshcd_hold(hba, false);
5931                 if (!ufshcd_is_clkgating_allowed(hba))
5932                         ufshcd_setup_clocks(hba, true);
5933                 ufshcd_release(hba);
5934                 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM;
5935                 ufshcd_vops_resume(hba, pm_op);
5936         } else {
5937                 ufshcd_hold(hba, false);
5938                 if (ufshcd_is_clkscaling_supported(hba) &&
5939                     hba->clk_scaling.is_enabled)
5940                         ufshcd_suspend_clkscaling(hba);
5941                 ufshcd_clk_scaling_allow(hba, false);
5942         }
5943         ufshcd_scsi_block_requests(hba);
5944         /* Drain ufshcd_queuecommand() */
5945         down_write(&hba->clk_scaling_lock);
5946         up_write(&hba->clk_scaling_lock);
5947         cancel_work_sync(&hba->eeh_work);
5948 }
5949
5950 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba)
5951 {
5952         ufshcd_scsi_unblock_requests(hba);
5953         ufshcd_release(hba);
5954         if (ufshcd_is_clkscaling_supported(hba))
5955                 ufshcd_clk_scaling_suspend(hba, false);
5956         ufshcd_clear_ua_wluns(hba);
5957         ufshcd_rpm_put(hba);
5958 }
5959
5960 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba)
5961 {
5962         return (!hba->is_powered || hba->shutting_down ||
5963                 !hba->sdev_ufs_device ||
5964                 hba->ufshcd_state == UFSHCD_STATE_ERROR ||
5965                 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset ||
5966                    ufshcd_is_link_broken(hba))));
5967 }
5968
5969 #ifdef CONFIG_PM
5970 static void ufshcd_recover_pm_error(struct ufs_hba *hba)
5971 {
5972         struct Scsi_Host *shost = hba->host;
5973         struct scsi_device *sdev;
5974         struct request_queue *q;
5975         int ret;
5976
5977         hba->is_sys_suspended = false;
5978         /*
5979          * Set RPM status of wlun device to RPM_ACTIVE,
5980          * this also clears its runtime error.
5981          */
5982         ret = pm_runtime_set_active(&hba->sdev_ufs_device->sdev_gendev);
5983
5984         /* hba device might have a runtime error otherwise */
5985         if (ret)
5986                 ret = pm_runtime_set_active(hba->dev);
5987         /*
5988          * If wlun device had runtime error, we also need to resume those
5989          * consumer scsi devices in case any of them has failed to be
5990          * resumed due to supplier runtime resume failure. This is to unblock
5991          * blk_queue_enter in case there are bios waiting inside it.
5992          */
5993         if (!ret) {
5994                 shost_for_each_device(sdev, shost) {
5995                         q = sdev->request_queue;
5996                         if (q->dev && (q->rpm_status == RPM_SUSPENDED ||
5997                                        q->rpm_status == RPM_SUSPENDING))
5998                                 pm_request_resume(q->dev);
5999                 }
6000         }
6001 }
6002 #else
6003 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba)
6004 {
6005 }
6006 #endif
6007
6008 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba)
6009 {
6010         struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info;
6011         u32 mode;
6012
6013         ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode);
6014
6015         if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK))
6016                 return true;
6017
6018         if (pwr_info->pwr_tx != (mode & PWRMODE_MASK))
6019                 return true;
6020
6021         return false;
6022 }
6023
6024 /**
6025  * ufshcd_err_handler - handle UFS errors that require s/w attention
6026  * @host: SCSI host pointer
6027  */
6028 static void ufshcd_err_handler(struct Scsi_Host *host)
6029 {
6030         struct ufs_hba *hba = shost_priv(host);
6031         unsigned long flags;
6032         bool err_xfer = false;
6033         bool err_tm = false;
6034         int err = 0, pmc_err;
6035         int tag;
6036         bool needs_reset = false, needs_restore = false;
6037
6038         down(&hba->host_sem);
6039         spin_lock_irqsave(hba->host->host_lock, flags);
6040         hba->host->host_eh_scheduled = 0;
6041         if (ufshcd_err_handling_should_stop(hba)) {
6042                 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6043                         hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6044                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6045                 up(&hba->host_sem);
6046                 return;
6047         }
6048         ufshcd_set_eh_in_progress(hba);
6049         spin_unlock_irqrestore(hba->host->host_lock, flags);
6050         ufshcd_err_handling_prepare(hba);
6051         /* Complete requests that have door-bell cleared by h/w */
6052         ufshcd_complete_requests(hba);
6053         spin_lock_irqsave(hba->host->host_lock, flags);
6054         if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6055                 hba->ufshcd_state = UFSHCD_STATE_RESET;
6056         /*
6057          * A full reset and restore might have happened after preparation
6058          * is finished, double check whether we should stop.
6059          */
6060         if (ufshcd_err_handling_should_stop(hba))
6061                 goto skip_err_handling;
6062
6063         if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6064                 bool ret;
6065
6066                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6067                 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
6068                 ret = ufshcd_quirk_dl_nac_errors(hba);
6069                 spin_lock_irqsave(hba->host->host_lock, flags);
6070                 if (!ret && ufshcd_err_handling_should_stop(hba))
6071                         goto skip_err_handling;
6072         }
6073
6074         if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6075             (hba->saved_uic_err &&
6076              (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6077                 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR);
6078
6079                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6080                 ufshcd_print_host_state(hba);
6081                 ufshcd_print_pwr_info(hba);
6082                 ufshcd_print_evt_hist(hba);
6083                 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
6084                 ufshcd_print_trs(hba, hba->outstanding_reqs, pr_prdt);
6085                 spin_lock_irqsave(hba->host->host_lock, flags);
6086         }
6087
6088         /*
6089          * if host reset is required then skip clearing the pending
6090          * transfers forcefully because they will get cleared during
6091          * host reset and restore
6092          */
6093         if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6094             ufshcd_is_saved_err_fatal(hba) ||
6095             ((hba->saved_err & UIC_ERROR) &&
6096              (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
6097                                     UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) {
6098                 needs_reset = true;
6099                 goto do_reset;
6100         }
6101
6102         /*
6103          * If LINERESET was caught, UFS might have been put to PWM mode,
6104          * check if power mode restore is needed.
6105          */
6106         if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) {
6107                 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6108                 if (!hba->saved_uic_err)
6109                         hba->saved_err &= ~UIC_ERROR;
6110                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6111                 if (ufshcd_is_pwr_mode_restore_needed(hba))
6112                         needs_restore = true;
6113                 spin_lock_irqsave(hba->host->host_lock, flags);
6114                 if (!hba->saved_err && !needs_restore)
6115                         goto skip_err_handling;
6116         }
6117
6118         hba->silence_err_logs = true;
6119         /* release lock as clear command might sleep */
6120         spin_unlock_irqrestore(hba->host->host_lock, flags);
6121         /* Clear pending transfer requests */
6122         for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
6123                 if (ufshcd_try_to_abort_task(hba, tag)) {
6124                         err_xfer = true;
6125                         goto lock_skip_pending_xfer_clear;
6126                 }
6127         }
6128
6129         /* Clear pending task management requests */
6130         for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
6131                 if (ufshcd_clear_tm_cmd(hba, tag)) {
6132                         err_tm = true;
6133                         goto lock_skip_pending_xfer_clear;
6134                 }
6135         }
6136
6137 lock_skip_pending_xfer_clear:
6138         ufshcd_retry_aborted_requests(hba);
6139
6140         spin_lock_irqsave(hba->host->host_lock, flags);
6141         hba->silence_err_logs = false;
6142         if (err_xfer || err_tm) {
6143                 needs_reset = true;
6144                 goto do_reset;
6145         }
6146
6147         /*
6148          * After all reqs and tasks are cleared from doorbell,
6149          * now it is safe to retore power mode.
6150          */
6151         if (needs_restore) {
6152                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6153                 /*
6154                  * Hold the scaling lock just in case dev cmds
6155                  * are sent via bsg and/or sysfs.
6156                  */
6157                 down_write(&hba->clk_scaling_lock);
6158                 hba->force_pmc = true;
6159                 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info));
6160                 if (pmc_err) {
6161                         needs_reset = true;
6162                         dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n",
6163                                         __func__, pmc_err);
6164                 }
6165                 hba->force_pmc = false;
6166                 ufshcd_print_pwr_info(hba);
6167                 up_write(&hba->clk_scaling_lock);
6168                 spin_lock_irqsave(hba->host->host_lock, flags);
6169         }
6170
6171 do_reset:
6172         /* Fatal errors need reset */
6173         if (needs_reset) {
6174                 hba->force_reset = false;
6175                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6176                 err = ufshcd_reset_and_restore(hba);
6177                 if (err)
6178                         dev_err(hba->dev, "%s: reset and restore failed with err %d\n",
6179                                         __func__, err);
6180                 else
6181                         ufshcd_recover_pm_error(hba);
6182                 spin_lock_irqsave(hba->host->host_lock, flags);
6183         }
6184
6185 skip_err_handling:
6186         if (!needs_reset) {
6187                 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
6188                         hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6189                 if (hba->saved_err || hba->saved_uic_err)
6190                         dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
6191                             __func__, hba->saved_err, hba->saved_uic_err);
6192         }
6193         ufshcd_clear_eh_in_progress(hba);
6194         spin_unlock_irqrestore(hba->host->host_lock, flags);
6195         ufshcd_err_handling_unprepare(hba);
6196         up(&hba->host_sem);
6197 }
6198
6199 /**
6200  * ufshcd_update_uic_error - check and set fatal UIC error flags.
6201  * @hba: per-adapter instance
6202  *
6203  * Returns
6204  *  IRQ_HANDLED - If interrupt is valid
6205  *  IRQ_NONE    - If invalid interrupt
6206  */
6207 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
6208 {
6209         u32 reg;
6210         irqreturn_t retval = IRQ_NONE;
6211
6212         /* PHY layer error */
6213         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
6214         if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
6215             (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) {
6216                 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg);
6217                 /*
6218                  * To know whether this error is fatal or not, DB timeout
6219                  * must be checked but this error is handled separately.
6220                  */
6221                 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)
6222                         dev_dbg(hba->dev, "%s: UIC Lane error reported\n",
6223                                         __func__);
6224
6225                 /* Got a LINERESET indication. */
6226                 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) {
6227                         struct uic_command *cmd = NULL;
6228
6229                         hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR;
6230                         if (hba->uic_async_done && hba->active_uic_cmd)
6231                                 cmd = hba->active_uic_cmd;
6232                         /*
6233                          * Ignore the LINERESET during power mode change
6234                          * operation via DME_SET command.
6235                          */
6236                         if (cmd && (cmd->command == UIC_CMD_DME_SET))
6237                                 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6238                 }
6239                 retval |= IRQ_HANDLED;
6240         }
6241
6242         /* PA_INIT_ERROR is fatal and needs UIC reset */
6243         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
6244         if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
6245             (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
6246                 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg);
6247
6248                 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
6249                         hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
6250                 else if (hba->dev_quirks &
6251                                 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6252                         if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
6253                                 hba->uic_error |=
6254                                         UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6255                         else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
6256                                 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
6257                 }
6258                 retval |= IRQ_HANDLED;
6259         }
6260
6261         /* UIC NL/TL/DME errors needs software retry */
6262         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
6263         if ((reg & UIC_NETWORK_LAYER_ERROR) &&
6264             (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
6265                 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg);
6266                 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
6267                 retval |= IRQ_HANDLED;
6268         }
6269
6270         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
6271         if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
6272             (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
6273                 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg);
6274                 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
6275                 retval |= IRQ_HANDLED;
6276         }
6277
6278         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
6279         if ((reg & UIC_DME_ERROR) &&
6280             (reg & UIC_DME_ERROR_CODE_MASK)) {
6281                 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg);
6282                 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
6283                 retval |= IRQ_HANDLED;
6284         }
6285
6286         dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
6287                         __func__, hba->uic_error);
6288         return retval;
6289 }
6290
6291 /**
6292  * ufshcd_check_errors - Check for errors that need s/w attention
6293  * @hba: per-adapter instance
6294  * @intr_status: interrupt status generated by the controller
6295  *
6296  * Returns
6297  *  IRQ_HANDLED - If interrupt is valid
6298  *  IRQ_NONE    - If invalid interrupt
6299  */
6300 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status)
6301 {
6302         bool queue_eh_work = false;
6303         irqreturn_t retval = IRQ_NONE;
6304
6305         spin_lock(hba->host->host_lock);
6306         hba->errors |= UFSHCD_ERROR_MASK & intr_status;
6307
6308         if (hba->errors & INT_FATAL_ERRORS) {
6309                 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR,
6310                                        hba->errors);
6311                 queue_eh_work = true;
6312         }
6313
6314         if (hba->errors & UIC_ERROR) {
6315                 hba->uic_error = 0;
6316                 retval = ufshcd_update_uic_error(hba);
6317                 if (hba->uic_error)
6318                         queue_eh_work = true;
6319         }
6320
6321         if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
6322                 dev_err(hba->dev,
6323                         "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
6324                         __func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
6325                         "Enter" : "Exit",
6326                         hba->errors, ufshcd_get_upmcrs(hba));
6327                 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR,
6328                                        hba->errors);
6329                 ufshcd_set_link_broken(hba);
6330                 queue_eh_work = true;
6331         }
6332
6333         if (queue_eh_work) {
6334                 /*
6335                  * update the transfer error masks to sticky bits, let's do this
6336                  * irrespective of current ufshcd_state.
6337                  */
6338                 hba->saved_err |= hba->errors;
6339                 hba->saved_uic_err |= hba->uic_error;
6340
6341                 /* dump controller state before resetting */
6342                 if ((hba->saved_err &
6343                      (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6344                     (hba->saved_uic_err &&
6345                      (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6346                         dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
6347                                         __func__, hba->saved_err,
6348                                         hba->saved_uic_err);
6349                         ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE,
6350                                          "host_regs: ");
6351                         ufshcd_print_pwr_info(hba);
6352                 }
6353                 retval |= IRQ_HANDLED;
6354         }
6355         /*
6356          * if (!queue_eh_work) -
6357          * Other errors are either non-fatal where host recovers
6358          * itself without s/w intervention or errors that will be
6359          * handled by the SCSI core layer.
6360          */
6361         hba->errors = 0;
6362         hba->uic_error = 0;
6363         spin_unlock(hba->host->host_lock);
6364
6365         if (queue_eh_work)
6366                 ufshcd_schedule_eh(hba);
6367
6368         return retval;
6369 }
6370
6371 struct ctm_info {
6372         struct ufs_hba  *hba;
6373         unsigned long   pending;
6374         unsigned int    ncpl;
6375 };
6376
6377 static bool ufshcd_compl_tm(struct request *req, void *priv, bool reserved)
6378 {
6379         struct ctm_info *const ci = priv;
6380         struct completion *c;
6381
6382         WARN_ON_ONCE(reserved);
6383         if (test_bit(req->tag, &ci->pending))
6384                 return true;
6385         ci->ncpl++;
6386         c = req->end_io_data;
6387         if (c)
6388                 complete(c);
6389         return true;
6390 }
6391
6392 /**
6393  * ufshcd_tmc_handler - handle task management function completion
6394  * @hba: per adapter instance
6395  *
6396  * Returns
6397  *  IRQ_HANDLED - If interrupt is valid
6398  *  IRQ_NONE    - If invalid interrupt
6399  */
6400 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
6401 {
6402         unsigned long flags;
6403         struct request_queue *q = hba->tmf_queue;
6404         struct ctm_info ci = {
6405                 .hba     = hba,
6406         };
6407
6408         spin_lock_irqsave(hba->host->host_lock, flags);
6409         ci.pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
6410         blk_mq_tagset_busy_iter(q->tag_set, ufshcd_compl_tm, &ci);
6411         spin_unlock_irqrestore(hba->host->host_lock, flags);
6412
6413         return ci.ncpl ? IRQ_HANDLED : IRQ_NONE;
6414 }
6415
6416 /**
6417  * ufshcd_sl_intr - Interrupt service routine
6418  * @hba: per adapter instance
6419  * @intr_status: contains interrupts generated by the controller
6420  *
6421  * Returns
6422  *  IRQ_HANDLED - If interrupt is valid
6423  *  IRQ_NONE    - If invalid interrupt
6424  */
6425 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
6426 {
6427         irqreturn_t retval = IRQ_NONE;
6428
6429         if (intr_status & UFSHCD_UIC_MASK)
6430                 retval |= ufshcd_uic_cmd_compl(hba, intr_status);
6431
6432         if (intr_status & UFSHCD_ERROR_MASK || hba->errors)
6433                 retval |= ufshcd_check_errors(hba, intr_status);
6434
6435         if (intr_status & UTP_TASK_REQ_COMPL)
6436                 retval |= ufshcd_tmc_handler(hba);
6437
6438         if (intr_status & UTP_TRANSFER_REQ_COMPL)
6439                 retval |= ufshcd_transfer_req_compl(hba, /*retry_requests=*/false);
6440
6441         return retval;
6442 }
6443
6444 /**
6445  * ufshcd_intr - Main interrupt service routine
6446  * @irq: irq number
6447  * @__hba: pointer to adapter instance
6448  *
6449  * Returns
6450  *  IRQ_HANDLED - If interrupt is valid
6451  *  IRQ_NONE    - If invalid interrupt
6452  */
6453 static irqreturn_t ufshcd_intr(int irq, void *__hba)
6454 {
6455         u32 intr_status, enabled_intr_status = 0;
6456         irqreturn_t retval = IRQ_NONE;
6457         struct ufs_hba *hba = __hba;
6458         int retries = hba->nutrs;
6459
6460         intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6461         hba->ufs_stats.last_intr_status = intr_status;
6462         hba->ufs_stats.last_intr_ts = ktime_get();
6463
6464         /*
6465          * There could be max of hba->nutrs reqs in flight and in worst case
6466          * if the reqs get finished 1 by 1 after the interrupt status is
6467          * read, make sure we handle them by checking the interrupt status
6468          * again in a loop until we process all of the reqs before returning.
6469          */
6470         while (intr_status && retries--) {
6471                 enabled_intr_status =
6472                         intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
6473                 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
6474                 if (enabled_intr_status)
6475                         retval |= ufshcd_sl_intr(hba, enabled_intr_status);
6476
6477                 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6478         }
6479
6480         if (enabled_intr_status && retval == IRQ_NONE &&
6481             (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) ||
6482              hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) {
6483                 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n",
6484                                         __func__,
6485                                         intr_status,
6486                                         hba->ufs_stats.last_intr_status,
6487                                         enabled_intr_status);
6488                 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
6489         }
6490
6491         return retval;
6492 }
6493
6494 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
6495 {
6496         int err = 0;
6497         u32 mask = 1 << tag;
6498         unsigned long flags;
6499
6500         if (!test_bit(tag, &hba->outstanding_tasks))
6501                 goto out;
6502
6503         spin_lock_irqsave(hba->host->host_lock, flags);
6504         ufshcd_utmrl_clear(hba, tag);
6505         spin_unlock_irqrestore(hba->host->host_lock, flags);
6506
6507         /* poll for max. 1 sec to clear door bell register by h/w */
6508         err = ufshcd_wait_for_register(hba,
6509                         REG_UTP_TASK_REQ_DOOR_BELL,
6510                         mask, 0, 1000, 1000);
6511 out:
6512         return err;
6513 }
6514
6515 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
6516                 struct utp_task_req_desc *treq, u8 tm_function)
6517 {
6518         struct request_queue *q = hba->tmf_queue;
6519         struct Scsi_Host *host = hba->host;
6520         DECLARE_COMPLETION_ONSTACK(wait);
6521         struct request *req;
6522         unsigned long flags;
6523         int task_tag, err;
6524
6525         /*
6526          * blk_get_request() is used here only to get a free tag.
6527          */
6528         req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
6529         if (IS_ERR(req))
6530                 return PTR_ERR(req);
6531
6532         req->end_io_data = &wait;
6533         ufshcd_hold(hba, false);
6534
6535         spin_lock_irqsave(host->host_lock, flags);
6536         blk_mq_start_request(req);
6537
6538         task_tag = req->tag;
6539         treq->upiu_req.req_header.dword_0 |= cpu_to_be32(task_tag);
6540
6541         memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq));
6542         ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function);
6543
6544         /* send command to the controller */
6545         __set_bit(task_tag, &hba->outstanding_tasks);
6546
6547         ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL);
6548         /* Make sure that doorbell is committed immediately */
6549         wmb();
6550
6551         spin_unlock_irqrestore(host->host_lock, flags);
6552
6553         ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND);
6554
6555         /* wait until the task management command is completed */
6556         err = wait_for_completion_io_timeout(&wait,
6557                         msecs_to_jiffies(TM_CMD_TIMEOUT));
6558         if (!err) {
6559                 /*
6560                  * Make sure that ufshcd_compl_tm() does not trigger a
6561                  * use-after-free.
6562                  */
6563                 req->end_io_data = NULL;
6564                 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR);
6565                 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
6566                                 __func__, tm_function);
6567                 if (ufshcd_clear_tm_cmd(hba, task_tag))
6568                         dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n",
6569                                         __func__, task_tag);
6570                 err = -ETIMEDOUT;
6571         } else {
6572                 err = 0;
6573                 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq));
6574
6575                 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP);
6576         }
6577
6578         spin_lock_irqsave(hba->host->host_lock, flags);
6579         __clear_bit(task_tag, &hba->outstanding_tasks);
6580         spin_unlock_irqrestore(hba->host->host_lock, flags);
6581
6582         ufshcd_release(hba);
6583         blk_put_request(req);
6584
6585         return err;
6586 }
6587
6588 /**
6589  * ufshcd_issue_tm_cmd - issues task management commands to controller
6590  * @hba: per adapter instance
6591  * @lun_id: LUN ID to which TM command is sent
6592  * @task_id: task ID to which the TM command is applicable
6593  * @tm_function: task management function opcode
6594  * @tm_response: task management service response return value
6595  *
6596  * Returns non-zero value on error, zero on success.
6597  */
6598 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
6599                 u8 tm_function, u8 *tm_response)
6600 {
6601         struct utp_task_req_desc treq = { { 0 }, };
6602         int ocs_value, err;
6603
6604         /* Configure task request descriptor */
6605         treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6606         treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6607
6608         /* Configure task request UPIU */
6609         treq.upiu_req.req_header.dword_0 = cpu_to_be32(lun_id << 8) |
6610                                   cpu_to_be32(UPIU_TRANSACTION_TASK_REQ << 24);
6611         treq.upiu_req.req_header.dword_1 = cpu_to_be32(tm_function << 16);
6612
6613         /*
6614          * The host shall provide the same value for LUN field in the basic
6615          * header and for Input Parameter.
6616          */
6617         treq.upiu_req.input_param1 = cpu_to_be32(lun_id);
6618         treq.upiu_req.input_param2 = cpu_to_be32(task_id);
6619
6620         err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
6621         if (err == -ETIMEDOUT)
6622                 return err;
6623
6624         ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6625         if (ocs_value != OCS_SUCCESS)
6626                 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
6627                                 __func__, ocs_value);
6628         else if (tm_response)
6629                 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) &
6630                                 MASK_TM_SERVICE_RESP;
6631         return err;
6632 }
6633
6634 /**
6635  * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
6636  * @hba:        per-adapter instance
6637  * @req_upiu:   upiu request
6638  * @rsp_upiu:   upiu reply
6639  * @desc_buff:  pointer to descriptor buffer, NULL if NA
6640  * @buff_len:   descriptor size, 0 if NA
6641  * @cmd_type:   specifies the type (NOP, Query...)
6642  * @desc_op:    descriptor operation
6643  *
6644  * Those type of requests uses UTP Transfer Request Descriptor - utrd.
6645  * Therefore, it "rides" the device management infrastructure: uses its tag and
6646  * tasks work queues.
6647  *
6648  * Since there is only one available tag for device management commands,
6649  * the caller is expected to hold the hba->dev_cmd.lock mutex.
6650  */
6651 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
6652                                         struct utp_upiu_req *req_upiu,
6653                                         struct utp_upiu_req *rsp_upiu,
6654                                         u8 *desc_buff, int *buff_len,
6655                                         enum dev_cmd_type cmd_type,
6656                                         enum query_opcode desc_op)
6657 {
6658         struct request_queue *q = hba->cmd_queue;
6659         DECLARE_COMPLETION_ONSTACK(wait);
6660         struct request *req;
6661         struct ufshcd_lrb *lrbp;
6662         int err = 0;
6663         int tag;
6664         u8 upiu_flags;
6665
6666         down_read(&hba->clk_scaling_lock);
6667
6668         req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
6669         if (IS_ERR(req)) {
6670                 err = PTR_ERR(req);
6671                 goto out_unlock;
6672         }
6673         tag = req->tag;
6674         WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
6675
6676         if (unlikely(test_bit(tag, &hba->outstanding_reqs))) {
6677                 err = -EBUSY;
6678                 goto out;
6679         }
6680
6681         lrbp = &hba->lrb[tag];
6682         WARN_ON(lrbp->cmd);
6683         lrbp->cmd = NULL;
6684         lrbp->sense_bufflen = 0;
6685         lrbp->sense_buffer = NULL;
6686         lrbp->task_tag = tag;
6687         lrbp->lun = 0;
6688         lrbp->intr_cmd = true;
6689         ufshcd_prepare_lrbp_crypto(NULL, lrbp);
6690         hba->dev_cmd.type = cmd_type;
6691
6692         if (hba->ufs_version <= ufshci_version(1, 1))
6693                 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
6694         else
6695                 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
6696
6697         /* update the task tag in the request upiu */
6698         req_upiu->header.dword_0 |= cpu_to_be32(tag);
6699
6700         ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
6701
6702         /* just copy the upiu request as it is */
6703         memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
6704         if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
6705                 /* The Data Segment Area is optional depending upon the query
6706                  * function value. for WRITE DESCRIPTOR, the data segment
6707                  * follows right after the tsf.
6708                  */
6709                 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
6710                 *buff_len = 0;
6711         }
6712
6713         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
6714
6715         hba->dev_cmd.complete = &wait;
6716
6717         ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
6718
6719         ufshcd_send_command(hba, tag);
6720         /*
6721          * ignore the returning value here - ufshcd_check_query_response is
6722          * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
6723          * read the response directly ignoring all errors.
6724          */
6725         ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
6726
6727         /* just copy the upiu response as it is */
6728         memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
6729         if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
6730                 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
6731                 u16 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
6732                                MASK_QUERY_DATA_SEG_LEN;
6733
6734                 if (*buff_len >= resp_len) {
6735                         memcpy(desc_buff, descp, resp_len);
6736                         *buff_len = resp_len;
6737                 } else {
6738                         dev_warn(hba->dev,
6739                                  "%s: rsp size %d is bigger than buffer size %d",
6740                                  __func__, resp_len, *buff_len);
6741                         *buff_len = 0;
6742                         err = -EINVAL;
6743                 }
6744         }
6745         ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
6746                                     (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
6747
6748 out:
6749         blk_put_request(req);
6750 out_unlock:
6751         up_read(&hba->clk_scaling_lock);
6752         return err;
6753 }
6754
6755 /**
6756  * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
6757  * @hba:        per-adapter instance
6758  * @req_upiu:   upiu request
6759  * @rsp_upiu:   upiu reply - only 8 DW as we do not support scsi commands
6760  * @msgcode:    message code, one of UPIU Transaction Codes Initiator to Target
6761  * @desc_buff:  pointer to descriptor buffer, NULL if NA
6762  * @buff_len:   descriptor size, 0 if NA
6763  * @desc_op:    descriptor operation
6764  *
6765  * Supports UTP Transfer requests (nop and query), and UTP Task
6766  * Management requests.
6767  * It is up to the caller to fill the upiu conent properly, as it will
6768  * be copied without any further input validations.
6769  */
6770 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
6771                              struct utp_upiu_req *req_upiu,
6772                              struct utp_upiu_req *rsp_upiu,
6773                              int msgcode,
6774                              u8 *desc_buff, int *buff_len,
6775                              enum query_opcode desc_op)
6776 {
6777         int err;
6778         enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
6779         struct utp_task_req_desc treq = { { 0 }, };
6780         int ocs_value;
6781         u8 tm_f = be32_to_cpu(req_upiu->header.dword_1) >> 16 & MASK_TM_FUNC;
6782
6783         switch (msgcode) {
6784         case UPIU_TRANSACTION_NOP_OUT:
6785                 cmd_type = DEV_CMD_TYPE_NOP;
6786                 fallthrough;
6787         case UPIU_TRANSACTION_QUERY_REQ:
6788                 ufshcd_hold(hba, false);
6789                 mutex_lock(&hba->dev_cmd.lock);
6790                 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
6791                                                    desc_buff, buff_len,
6792                                                    cmd_type, desc_op);
6793                 mutex_unlock(&hba->dev_cmd.lock);
6794                 ufshcd_release(hba);
6795
6796                 break;
6797         case UPIU_TRANSACTION_TASK_REQ:
6798                 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6799                 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6800
6801                 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu));
6802
6803                 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
6804                 if (err == -ETIMEDOUT)
6805                         break;
6806
6807                 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6808                 if (ocs_value != OCS_SUCCESS) {
6809                         dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
6810                                 ocs_value);
6811                         break;
6812                 }
6813
6814                 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu));
6815
6816                 break;
6817         default:
6818                 err = -EINVAL;
6819
6820                 break;
6821         }
6822
6823         return err;
6824 }
6825
6826 /**
6827  * ufshcd_eh_device_reset_handler - device reset handler registered to
6828  *                                    scsi layer.
6829  * @cmd: SCSI command pointer
6830  *
6831  * Returns SUCCESS/FAILED
6832  */
6833 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
6834 {
6835         struct Scsi_Host *host;
6836         struct ufs_hba *hba;
6837         u32 pos;
6838         int err;
6839         u8 resp = 0xF, lun;
6840
6841         host = cmd->device->host;
6842         hba = shost_priv(host);
6843
6844         lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
6845         err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp);
6846         if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6847                 if (!err)
6848                         err = resp;
6849                 goto out;
6850         }
6851
6852         /* clear the commands that were pending for corresponding LUN */
6853         for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
6854                 if (hba->lrb[pos].lun == lun) {
6855                         err = ufshcd_clear_cmd(hba, pos);
6856                         if (err)
6857                                 break;
6858                         __ufshcd_transfer_req_compl(hba, pos, /*retry_requests=*/true);
6859                 }
6860         }
6861
6862 out:
6863         hba->req_abort_count = 0;
6864         ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err);
6865         if (!err) {
6866                 err = SUCCESS;
6867         } else {
6868                 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
6869                 err = FAILED;
6870         }
6871         return err;
6872 }
6873
6874 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
6875 {
6876         struct ufshcd_lrb *lrbp;
6877         int tag;
6878
6879         for_each_set_bit(tag, &bitmap, hba->nutrs) {
6880                 lrbp = &hba->lrb[tag];
6881                 lrbp->req_abort_skip = true;
6882         }
6883 }
6884
6885 /**
6886  * ufshcd_try_to_abort_task - abort a specific task
6887  * @hba: Pointer to adapter instance
6888  * @tag: Task tag/index to be aborted
6889  *
6890  * Abort the pending command in device by sending UFS_ABORT_TASK task management
6891  * command, and in host controller by clearing the door-bell register. There can
6892  * be race between controller sending the command to the device while abort is
6893  * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
6894  * really issued and then try to abort it.
6895  *
6896  * Returns zero on success, non-zero on failure
6897  */
6898 static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag)
6899 {
6900         struct ufshcd_lrb *lrbp = &hba->lrb[tag];
6901         int err = 0;
6902         int poll_cnt;
6903         u8 resp = 0xF;
6904         u32 reg;
6905
6906         for (poll_cnt = 100; poll_cnt; poll_cnt--) {
6907                 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6908                                 UFS_QUERY_TASK, &resp);
6909                 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
6910                         /* cmd pending in the device */
6911                         dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
6912                                 __func__, tag);
6913                         break;
6914                 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6915                         /*
6916                          * cmd not pending in the device, check if it is
6917                          * in transition.
6918                          */
6919                         dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
6920                                 __func__, tag);
6921                         reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
6922                         if (reg & (1 << tag)) {
6923                                 /* sleep for max. 200us to stabilize */
6924                                 usleep_range(100, 200);
6925                                 continue;
6926                         }
6927                         /* command completed already */
6928                         dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
6929                                 __func__, tag);
6930                         goto out;
6931                 } else {
6932                         dev_err(hba->dev,
6933                                 "%s: no response from device. tag = %d, err %d\n",
6934                                 __func__, tag, err);
6935                         if (!err)
6936                                 err = resp; /* service response error */
6937                         goto out;
6938                 }
6939         }
6940
6941         if (!poll_cnt) {
6942                 err = -EBUSY;
6943                 goto out;
6944         }
6945
6946         err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6947                         UFS_ABORT_TASK, &resp);
6948         if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6949                 if (!err) {
6950                         err = resp; /* service response error */
6951                         dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
6952                                 __func__, tag, err);
6953                 }
6954                 goto out;
6955         }
6956
6957         err = ufshcd_clear_cmd(hba, tag);
6958         if (err)
6959                 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
6960                         __func__, tag, err);
6961
6962 out:
6963         return err;
6964 }
6965
6966 /**
6967  * ufshcd_abort - scsi host template eh_abort_handler callback
6968  * @cmd: SCSI command pointer
6969  *
6970  * Returns SUCCESS/FAILED
6971  */
6972 static int ufshcd_abort(struct scsi_cmnd *cmd)
6973 {
6974         struct Scsi_Host *host = cmd->device->host;
6975         struct ufs_hba *hba = shost_priv(host);
6976         unsigned int tag = cmd->request->tag;
6977         struct ufshcd_lrb *lrbp = &hba->lrb[tag];
6978         unsigned long flags;
6979         int err = FAILED;
6980         u32 reg;
6981
6982         WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
6983
6984         ufshcd_hold(hba, false);
6985         reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
6986         /* If command is already aborted/completed, return FAILED. */
6987         if (!(test_bit(tag, &hba->outstanding_reqs))) {
6988                 dev_err(hba->dev,
6989                         "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
6990                         __func__, tag, hba->outstanding_reqs, reg);
6991                 goto release;
6992         }
6993
6994         /* Print Transfer Request of aborted task */
6995         dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
6996
6997         /*
6998          * Print detailed info about aborted request.
6999          * As more than one request might get aborted at the same time,
7000          * print full information only for the first aborted request in order
7001          * to reduce repeated printouts. For other aborted requests only print
7002          * basic details.
7003          */
7004         scsi_print_command(cmd);
7005         if (!hba->req_abort_count) {
7006                 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag);
7007                 ufshcd_print_evt_hist(hba);
7008                 ufshcd_print_host_state(hba);
7009                 ufshcd_print_pwr_info(hba);
7010                 ufshcd_print_trs(hba, 1 << tag, true);
7011         } else {
7012                 ufshcd_print_trs(hba, 1 << tag, false);
7013         }
7014         hba->req_abort_count++;
7015
7016         if (!(reg & (1 << tag))) {
7017                 dev_err(hba->dev,
7018                 "%s: cmd was completed, but without a notifying intr, tag = %d",
7019                 __func__, tag);
7020                 __ufshcd_transfer_req_compl(hba, 1UL << tag, /*retry_requests=*/false);
7021                 goto release;
7022         }
7023
7024         /*
7025          * Task abort to the device W-LUN is illegal. When this command
7026          * will fail, due to spec violation, scsi err handling next step
7027          * will be to send LU reset which, again, is a spec violation.
7028          * To avoid these unnecessary/illegal steps, first we clean up
7029          * the lrb taken by this cmd and re-set it in outstanding_reqs,
7030          * then queue the error handler and bail.
7031          */
7032         if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) {
7033                 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun);
7034
7035                 spin_lock_irqsave(host->host_lock, flags);
7036                 hba->force_reset = true;
7037                 spin_unlock_irqrestore(host->host_lock, flags);
7038
7039                 ufshcd_schedule_eh(hba);
7040
7041                 goto release;
7042         }
7043
7044         /* Skip task abort in case previous aborts failed and report failure */
7045         if (lrbp->req_abort_skip) {
7046                 dev_err(hba->dev, "%s: skipping abort\n", __func__);
7047                 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7048                 goto release;
7049         }
7050
7051         err = ufshcd_try_to_abort_task(hba, tag);
7052         if (err) {
7053                 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
7054                 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7055                 err = FAILED;
7056                 goto release;
7057         }
7058
7059         err = SUCCESS;
7060
7061 release:
7062         /* Matches the ufshcd_hold() call at the start of this function. */
7063         ufshcd_release(hba);
7064         return err;
7065 }
7066
7067 /**
7068  * ufshcd_host_reset_and_restore - reset and restore host controller
7069  * @hba: per-adapter instance
7070  *
7071  * Note that host controller reset may issue DME_RESET to
7072  * local and remote (device) Uni-Pro stack and the attributes
7073  * are reset to default state.
7074  *
7075  * Returns zero on success, non-zero on failure
7076  */
7077 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
7078 {
7079         int err;
7080
7081         /*
7082          * Stop the host controller and complete the requests
7083          * cleared by h/w
7084          */
7085         ufshpb_reset_host(hba);
7086         ufshcd_hba_stop(hba);
7087         hba->silence_err_logs = true;
7088         ufshcd_retry_aborted_requests(hba);
7089         hba->silence_err_logs = false;
7090
7091         /* scale up clocks to max frequency before full reinitialization */
7092         ufshcd_set_clk_freq(hba, true);
7093
7094         err = ufshcd_hba_enable(hba);
7095
7096         /* Establish the link again and restore the device */
7097         if (!err)
7098                 err = ufshcd_probe_hba(hba, false);
7099
7100         if (err)
7101                 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
7102         ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err);
7103         return err;
7104 }
7105
7106 /**
7107  * ufshcd_reset_and_restore - reset and re-initialize host/device
7108  * @hba: per-adapter instance
7109  *
7110  * Reset and recover device, host and re-establish link. This
7111  * is helpful to recover the communication in fatal error conditions.
7112  *
7113  * Returns zero on success, non-zero on failure
7114  */
7115 static int ufshcd_reset_and_restore(struct ufs_hba *hba)
7116 {
7117         u32 saved_err;
7118         u32 saved_uic_err;
7119         int err = 0;
7120         unsigned long flags;
7121         int retries = MAX_HOST_RESET_RETRIES;
7122
7123         /*
7124          * This is a fresh start, cache and clear saved error first,
7125          * in case new error generated during reset and restore.
7126          */
7127         spin_lock_irqsave(hba->host->host_lock, flags);
7128         saved_err = hba->saved_err;
7129         saved_uic_err = hba->saved_uic_err;
7130         hba->saved_err = 0;
7131         hba->saved_uic_err = 0;
7132         spin_unlock_irqrestore(hba->host->host_lock, flags);
7133
7134         do {
7135                 /* Reset the attached device */
7136                 ufshcd_device_reset(hba);
7137
7138                 err = ufshcd_host_reset_and_restore(hba);
7139         } while (err && --retries);
7140
7141         spin_lock_irqsave(hba->host->host_lock, flags);
7142         /*
7143          * Inform scsi mid-layer that we did reset and allow to handle
7144          * Unit Attention properly.
7145          */
7146         scsi_report_bus_reset(hba->host, 0);
7147         if (err) {
7148                 hba->ufshcd_state = UFSHCD_STATE_ERROR;
7149                 hba->saved_err |= saved_err;
7150                 hba->saved_uic_err |= saved_uic_err;
7151         }
7152         spin_unlock_irqrestore(hba->host->host_lock, flags);
7153
7154         return err;
7155 }
7156
7157 /**
7158  * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
7159  * @cmd: SCSI command pointer
7160  *
7161  * Returns SUCCESS/FAILED
7162  */
7163 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
7164 {
7165         int err = SUCCESS;
7166         unsigned long flags;
7167         struct ufs_hba *hba;
7168
7169         hba = shost_priv(cmd->device->host);
7170
7171         spin_lock_irqsave(hba->host->host_lock, flags);
7172         hba->force_reset = true;
7173         dev_err(hba->dev, "%s: reset in progress - 1\n", __func__);
7174         spin_unlock_irqrestore(hba->host->host_lock, flags);
7175
7176         ufshcd_err_handler(hba->host);
7177
7178         spin_lock_irqsave(hba->host->host_lock, flags);
7179         if (hba->ufshcd_state == UFSHCD_STATE_ERROR)
7180                 err = FAILED;
7181         spin_unlock_irqrestore(hba->host->host_lock, flags);
7182
7183         return err;
7184 }
7185
7186 /**
7187  * ufshcd_get_max_icc_level - calculate the ICC level
7188  * @sup_curr_uA: max. current supported by the regulator
7189  * @start_scan: row at the desc table to start scan from
7190  * @buff: power descriptor buffer
7191  *
7192  * Returns calculated max ICC level for specific regulator
7193  */
7194 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
7195 {
7196         int i;
7197         int curr_uA;
7198         u16 data;
7199         u16 unit;
7200
7201         for (i = start_scan; i >= 0; i--) {
7202                 data = be16_to_cpup((__be16 *)&buff[2 * i]);
7203                 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
7204                                                 ATTR_ICC_LVL_UNIT_OFFSET;
7205                 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
7206                 switch (unit) {
7207                 case UFSHCD_NANO_AMP:
7208                         curr_uA = curr_uA / 1000;
7209                         break;
7210                 case UFSHCD_MILI_AMP:
7211                         curr_uA = curr_uA * 1000;
7212                         break;
7213                 case UFSHCD_AMP:
7214                         curr_uA = curr_uA * 1000 * 1000;
7215                         break;
7216                 case UFSHCD_MICRO_AMP:
7217                 default:
7218                         break;
7219                 }
7220                 if (sup_curr_uA >= curr_uA)
7221                         break;
7222         }
7223         if (i < 0) {
7224                 i = 0;
7225                 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
7226         }
7227
7228         return (u32)i;
7229 }
7230
7231 /**
7232  * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level
7233  * In case regulators are not initialized we'll return 0
7234  * @hba: per-adapter instance
7235  * @desc_buf: power descriptor buffer to extract ICC levels from.
7236  * @len: length of desc_buff
7237  *
7238  * Returns calculated ICC level
7239  */
7240 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
7241                                                         u8 *desc_buf, int len)
7242 {
7243         u32 icc_level = 0;
7244
7245         if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
7246                                                 !hba->vreg_info.vccq2) {
7247                 dev_err(hba->dev,
7248                         "%s: Regulator capability was not set, actvIccLevel=%d",
7249                                                         __func__, icc_level);
7250                 goto out;
7251         }
7252
7253         if (hba->vreg_info.vcc->max_uA)
7254                 icc_level = ufshcd_get_max_icc_level(
7255                                 hba->vreg_info.vcc->max_uA,
7256                                 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
7257                                 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
7258
7259         if (hba->vreg_info.vccq->max_uA)
7260                 icc_level = ufshcd_get_max_icc_level(
7261                                 hba->vreg_info.vccq->max_uA,
7262                                 icc_level,
7263                                 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
7264
7265         if (hba->vreg_info.vccq2->max_uA)
7266                 icc_level = ufshcd_get_max_icc_level(
7267                                 hba->vreg_info.vccq2->max_uA,
7268                                 icc_level,
7269                                 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
7270 out:
7271         return icc_level;
7272 }
7273
7274 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba)
7275 {
7276         int ret;
7277         int buff_len = hba->desc_size[QUERY_DESC_IDN_POWER];
7278         u8 *desc_buf;
7279         u32 icc_level;
7280
7281         desc_buf = kmalloc(buff_len, GFP_KERNEL);
7282         if (!desc_buf)
7283                 return;
7284
7285         ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0,
7286                                      desc_buf, buff_len);
7287         if (ret) {
7288                 dev_err(hba->dev,
7289                         "%s: Failed reading power descriptor.len = %d ret = %d",
7290                         __func__, buff_len, ret);
7291                 goto out;
7292         }
7293
7294         icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf,
7295                                                          buff_len);
7296         dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level);
7297
7298         ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
7299                 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
7300
7301         if (ret)
7302                 dev_err(hba->dev,
7303                         "%s: Failed configuring bActiveICCLevel = %d ret = %d",
7304                         __func__, icc_level, ret);
7305
7306 out:
7307         kfree(desc_buf);
7308 }
7309
7310 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev)
7311 {
7312         scsi_autopm_get_device(sdev);
7313         blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev);
7314         if (sdev->rpm_autosuspend)
7315                 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev,
7316                                                  RPM_AUTOSUSPEND_DELAY_MS);
7317         scsi_autopm_put_device(sdev);
7318 }
7319
7320 /**
7321  * ufshcd_scsi_add_wlus - Adds required W-LUs
7322  * @hba: per-adapter instance
7323  *
7324  * UFS device specification requires the UFS devices to support 4 well known
7325  * logical units:
7326  *      "REPORT_LUNS" (address: 01h)
7327  *      "UFS Device" (address: 50h)
7328  *      "RPMB" (address: 44h)
7329  *      "BOOT" (address: 30h)
7330  * UFS device's power management needs to be controlled by "POWER CONDITION"
7331  * field of SSU (START STOP UNIT) command. But this "power condition" field
7332  * will take effect only when its sent to "UFS device" well known logical unit
7333  * hence we require the scsi_device instance to represent this logical unit in
7334  * order for the UFS host driver to send the SSU command for power management.
7335  *
7336  * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
7337  * Block) LU so user space process can control this LU. User space may also
7338  * want to have access to BOOT LU.
7339  *
7340  * This function adds scsi device instances for each of all well known LUs
7341  * (except "REPORT LUNS" LU).
7342  *
7343  * Returns zero on success (all required W-LUs are added successfully),
7344  * non-zero error value on failure (if failed to add any of the required W-LU).
7345  */
7346 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
7347 {
7348         int ret = 0;
7349         struct scsi_device *sdev_boot;
7350
7351         hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
7352                 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
7353         if (IS_ERR(hba->sdev_ufs_device)) {
7354                 ret = PTR_ERR(hba->sdev_ufs_device);
7355                 hba->sdev_ufs_device = NULL;
7356                 goto out;
7357         }
7358         scsi_device_put(hba->sdev_ufs_device);
7359
7360         hba->sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
7361                 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7362         if (IS_ERR(hba->sdev_rpmb)) {
7363                 ret = PTR_ERR(hba->sdev_rpmb);
7364                 goto remove_sdev_ufs_device;
7365         }
7366         ufshcd_blk_pm_runtime_init(hba->sdev_rpmb);
7367         scsi_device_put(hba->sdev_rpmb);
7368
7369         sdev_boot = __scsi_add_device(hba->host, 0, 0,
7370                 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7371         if (IS_ERR(sdev_boot)) {
7372                 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
7373         } else {
7374                 ufshcd_blk_pm_runtime_init(sdev_boot);
7375                 scsi_device_put(sdev_boot);
7376         }
7377         goto out;
7378
7379 remove_sdev_ufs_device:
7380         scsi_remove_device(hba->sdev_ufs_device);
7381 out:
7382         return ret;
7383 }
7384
7385 static void ufshcd_wb_probe(struct ufs_hba *hba, u8 *desc_buf)
7386 {
7387         struct ufs_dev_info *dev_info = &hba->dev_info;
7388         u8 lun;
7389         u32 d_lu_wb_buf_alloc;
7390         u32 ext_ufs_feature;
7391
7392         if (!ufshcd_is_wb_allowed(hba))
7393                 return;
7394         /*
7395          * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or
7396          * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES
7397          * enabled
7398          */
7399         if (!(dev_info->wspecversion >= 0x310 ||
7400               dev_info->wspecversion == 0x220 ||
7401              (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES)))
7402                 goto wb_disabled;
7403
7404         if (hba->desc_size[QUERY_DESC_IDN_DEVICE] <
7405             DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP + 4)
7406                 goto wb_disabled;
7407
7408         ext_ufs_feature = get_unaligned_be32(desc_buf +
7409                                         DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
7410
7411         if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP))
7412                 goto wb_disabled;
7413
7414         /*
7415          * WB may be supported but not configured while provisioning. The spec
7416          * says, in dedicated wb buffer mode, a max of 1 lun would have wb
7417          * buffer configured.
7418          */
7419         dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE];
7420
7421         dev_info->b_presrv_uspc_en =
7422                 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN];
7423
7424         if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) {
7425                 if (!get_unaligned_be32(desc_buf +
7426                                    DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS))
7427                         goto wb_disabled;
7428         } else {
7429                 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) {
7430                         d_lu_wb_buf_alloc = 0;
7431                         ufshcd_read_unit_desc_param(hba,
7432                                         lun,
7433                                         UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS,
7434                                         (u8 *)&d_lu_wb_buf_alloc,
7435                                         sizeof(d_lu_wb_buf_alloc));
7436                         if (d_lu_wb_buf_alloc) {
7437                                 dev_info->wb_dedicated_lu = lun;
7438                                 break;
7439                         }
7440                 }
7441
7442                 if (!d_lu_wb_buf_alloc)
7443                         goto wb_disabled;
7444         }
7445         return;
7446
7447 wb_disabled:
7448         hba->caps &= ~UFSHCD_CAP_WB_EN;
7449 }
7450
7451 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, struct ufs_dev_fix *fixups)
7452 {
7453         struct ufs_dev_fix *f;
7454         struct ufs_dev_info *dev_info = &hba->dev_info;
7455
7456         if (!fixups)
7457                 return;
7458
7459         for (f = fixups; f->quirk; f++) {
7460                 if ((f->wmanufacturerid == dev_info->wmanufacturerid ||
7461                      f->wmanufacturerid == UFS_ANY_VENDOR) &&
7462                      ((dev_info->model &&
7463                        STR_PRFX_EQUAL(f->model, dev_info->model)) ||
7464                       !strcmp(f->model, UFS_ANY_MODEL)))
7465                         hba->dev_quirks |= f->quirk;
7466         }
7467 }
7468 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks);
7469
7470 static void ufs_fixup_device_setup(struct ufs_hba *hba)
7471 {
7472         /* fix by general quirk table */
7473         ufshcd_fixup_dev_quirks(hba, ufs_fixups);
7474
7475         /* allow vendors to fix quirks */
7476         ufshcd_vops_fixup_dev_quirks(hba);
7477 }
7478
7479 static int ufs_get_device_desc(struct ufs_hba *hba)
7480 {
7481         int err;
7482         u8 model_index;
7483         u8 b_ufs_feature_sup;
7484         u8 *desc_buf;
7485         struct ufs_dev_info *dev_info = &hba->dev_info;
7486
7487         desc_buf = kmalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
7488         if (!desc_buf) {
7489                 err = -ENOMEM;
7490                 goto out;
7491         }
7492
7493         err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf,
7494                                      hba->desc_size[QUERY_DESC_IDN_DEVICE]);
7495         if (err) {
7496                 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
7497                         __func__, err);
7498                 goto out;
7499         }
7500
7501         /*
7502          * getting vendor (manufacturerID) and Bank Index in big endian
7503          * format
7504          */
7505         dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
7506                                      desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
7507
7508         /* getting Specification Version in big endian format */
7509         dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
7510                                       desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
7511         b_ufs_feature_sup = desc_buf[DEVICE_DESC_PARAM_UFS_FEAT];
7512
7513         model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
7514
7515         if (dev_info->wspecversion >= UFS_DEV_HPB_SUPPORT_VERSION &&
7516             (b_ufs_feature_sup & UFS_DEV_HPB_SUPPORT)) {
7517                 bool hpb_en = false;
7518
7519                 ufshpb_get_dev_info(hba, desc_buf);
7520
7521                 if (!ufshpb_is_legacy(hba))
7522                         err = ufshcd_query_flag_retry(hba,
7523                                                       UPIU_QUERY_OPCODE_READ_FLAG,
7524                                                       QUERY_FLAG_IDN_HPB_EN, 0,
7525                                                       &hpb_en);
7526
7527                 if (ufshpb_is_legacy(hba) || (!err && hpb_en))
7528                         dev_info->hpb_enabled = true;
7529         }
7530
7531         err = ufshcd_read_string_desc(hba, model_index,
7532                                       &dev_info->model, SD_ASCII_STD);
7533         if (err < 0) {
7534                 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
7535                         __func__, err);
7536                 goto out;
7537         }
7538
7539         hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] +
7540                 desc_buf[DEVICE_DESC_PARAM_NUM_WLU];
7541
7542         ufs_fixup_device_setup(hba);
7543
7544         ufshcd_wb_probe(hba, desc_buf);
7545
7546         /*
7547          * ufshcd_read_string_desc returns size of the string
7548          * reset the error value
7549          */
7550         err = 0;
7551
7552 out:
7553         kfree(desc_buf);
7554         return err;
7555 }
7556
7557 static void ufs_put_device_desc(struct ufs_hba *hba)
7558 {
7559         struct ufs_dev_info *dev_info = &hba->dev_info;
7560
7561         kfree(dev_info->model);
7562         dev_info->model = NULL;
7563 }
7564
7565 /**
7566  * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
7567  * @hba: per-adapter instance
7568  *
7569  * PA_TActivate parameter can be tuned manually if UniPro version is less than
7570  * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
7571  * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
7572  * the hibern8 exit latency.
7573  *
7574  * Returns zero on success, non-zero error value on failure.
7575  */
7576 static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
7577 {
7578         int ret = 0;
7579         u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
7580
7581         ret = ufshcd_dme_peer_get(hba,
7582                                   UIC_ARG_MIB_SEL(
7583                                         RX_MIN_ACTIVATETIME_CAPABILITY,
7584                                         UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7585                                   &peer_rx_min_activatetime);
7586         if (ret)
7587                 goto out;
7588
7589         /* make sure proper unit conversion is applied */
7590         tuned_pa_tactivate =
7591                 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
7592                  / PA_TACTIVATE_TIME_UNIT_US);
7593         ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7594                              tuned_pa_tactivate);
7595
7596 out:
7597         return ret;
7598 }
7599
7600 /**
7601  * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
7602  * @hba: per-adapter instance
7603  *
7604  * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
7605  * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
7606  * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
7607  * This optimal value can help reduce the hibern8 exit latency.
7608  *
7609  * Returns zero on success, non-zero error value on failure.
7610  */
7611 static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
7612 {
7613         int ret = 0;
7614         u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
7615         u32 max_hibern8_time, tuned_pa_hibern8time;
7616
7617         ret = ufshcd_dme_get(hba,
7618                              UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
7619                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
7620                                   &local_tx_hibern8_time_cap);
7621         if (ret)
7622                 goto out;
7623
7624         ret = ufshcd_dme_peer_get(hba,
7625                                   UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
7626                                         UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7627                                   &peer_rx_hibern8_time_cap);
7628         if (ret)
7629                 goto out;
7630
7631         max_hibern8_time = max(local_tx_hibern8_time_cap,
7632                                peer_rx_hibern8_time_cap);
7633         /* make sure proper unit conversion is applied */
7634         tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
7635                                 / PA_HIBERN8_TIME_UNIT_US);
7636         ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
7637                              tuned_pa_hibern8time);
7638 out:
7639         return ret;
7640 }
7641
7642 /**
7643  * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
7644  * less than device PA_TACTIVATE time.
7645  * @hba: per-adapter instance
7646  *
7647  * Some UFS devices require host PA_TACTIVATE to be lower than device
7648  * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
7649  * for such devices.
7650  *
7651  * Returns zero on success, non-zero error value on failure.
7652  */
7653 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
7654 {
7655         int ret = 0;
7656         u32 granularity, peer_granularity;
7657         u32 pa_tactivate, peer_pa_tactivate;
7658         u32 pa_tactivate_us, peer_pa_tactivate_us;
7659         u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
7660
7661         ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7662                                   &granularity);
7663         if (ret)
7664                 goto out;
7665
7666         ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7667                                   &peer_granularity);
7668         if (ret)
7669                 goto out;
7670
7671         if ((granularity < PA_GRANULARITY_MIN_VAL) ||
7672             (granularity > PA_GRANULARITY_MAX_VAL)) {
7673                 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
7674                         __func__, granularity);
7675                 return -EINVAL;
7676         }
7677
7678         if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
7679             (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
7680                 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
7681                         __func__, peer_granularity);
7682                 return -EINVAL;
7683         }
7684
7685         ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
7686         if (ret)
7687                 goto out;
7688
7689         ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
7690                                   &peer_pa_tactivate);
7691         if (ret)
7692                 goto out;
7693
7694         pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
7695         peer_pa_tactivate_us = peer_pa_tactivate *
7696                              gran_to_us_table[peer_granularity - 1];
7697
7698         if (pa_tactivate_us > peer_pa_tactivate_us) {
7699                 u32 new_peer_pa_tactivate;
7700
7701                 new_peer_pa_tactivate = pa_tactivate_us /
7702                                       gran_to_us_table[peer_granularity - 1];
7703                 new_peer_pa_tactivate++;
7704                 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7705                                           new_peer_pa_tactivate);
7706         }
7707
7708 out:
7709         return ret;
7710 }
7711
7712 static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
7713 {
7714         if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
7715                 ufshcd_tune_pa_tactivate(hba);
7716                 ufshcd_tune_pa_hibern8time(hba);
7717         }
7718
7719         ufshcd_vops_apply_dev_quirks(hba);
7720
7721         if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
7722                 /* set 1ms timeout for PA_TACTIVATE */
7723                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
7724
7725         if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
7726                 ufshcd_quirk_tune_host_pa_tactivate(hba);
7727 }
7728
7729 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
7730 {
7731         hba->ufs_stats.hibern8_exit_cnt = 0;
7732         hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
7733         hba->req_abort_count = 0;
7734 }
7735
7736 static int ufshcd_device_geo_params_init(struct ufs_hba *hba)
7737 {
7738         int err;
7739         size_t buff_len;
7740         u8 *desc_buf;
7741
7742         buff_len = hba->desc_size[QUERY_DESC_IDN_GEOMETRY];
7743         desc_buf = kmalloc(buff_len, GFP_KERNEL);
7744         if (!desc_buf) {
7745                 err = -ENOMEM;
7746                 goto out;
7747         }
7748
7749         err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0,
7750                                      desc_buf, buff_len);
7751         if (err) {
7752                 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n",
7753                                 __func__, err);
7754                 goto out;
7755         }
7756
7757         if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1)
7758                 hba->dev_info.max_lu_supported = 32;
7759         else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0)
7760                 hba->dev_info.max_lu_supported = 8;
7761
7762         if (hba->desc_size[QUERY_DESC_IDN_GEOMETRY] >=
7763                 GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS)
7764                 ufshpb_get_geo_info(hba, desc_buf);
7765
7766 out:
7767         kfree(desc_buf);
7768         return err;
7769 }
7770
7771 static struct ufs_ref_clk ufs_ref_clk_freqs[] = {
7772         {19200000, REF_CLK_FREQ_19_2_MHZ},
7773         {26000000, REF_CLK_FREQ_26_MHZ},
7774         {38400000, REF_CLK_FREQ_38_4_MHZ},
7775         {52000000, REF_CLK_FREQ_52_MHZ},
7776         {0, REF_CLK_FREQ_INVAL},
7777 };
7778
7779 static enum ufs_ref_clk_freq
7780 ufs_get_bref_clk_from_hz(unsigned long freq)
7781 {
7782         int i;
7783
7784         for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
7785                 if (ufs_ref_clk_freqs[i].freq_hz == freq)
7786                         return ufs_ref_clk_freqs[i].val;
7787
7788         return REF_CLK_FREQ_INVAL;
7789 }
7790
7791 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
7792 {
7793         unsigned long freq;
7794
7795         freq = clk_get_rate(refclk);
7796
7797         hba->dev_ref_clk_freq =
7798                 ufs_get_bref_clk_from_hz(freq);
7799
7800         if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
7801                 dev_err(hba->dev,
7802                 "invalid ref_clk setting = %ld\n", freq);
7803 }
7804
7805 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
7806 {
7807         int err;
7808         u32 ref_clk;
7809         u32 freq = hba->dev_ref_clk_freq;
7810
7811         err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
7812                         QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
7813
7814         if (err) {
7815                 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
7816                         err);
7817                 goto out;
7818         }
7819
7820         if (ref_clk == freq)
7821                 goto out; /* nothing to update */
7822
7823         err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
7824                         QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
7825
7826         if (err) {
7827                 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
7828                         ufs_ref_clk_freqs[freq].freq_hz);
7829                 goto out;
7830         }
7831
7832         dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
7833                         ufs_ref_clk_freqs[freq].freq_hz);
7834
7835 out:
7836         return err;
7837 }
7838
7839 static int ufshcd_device_params_init(struct ufs_hba *hba)
7840 {
7841         bool flag;
7842         int ret, i;
7843
7844          /* Init device descriptor sizes */
7845         for (i = 0; i < QUERY_DESC_IDN_MAX; i++)
7846                 hba->desc_size[i] = QUERY_DESC_MAX_SIZE;
7847
7848         /* Init UFS geometry descriptor related parameters */
7849         ret = ufshcd_device_geo_params_init(hba);
7850         if (ret)
7851                 goto out;
7852
7853         /* Check and apply UFS device quirks */
7854         ret = ufs_get_device_desc(hba);
7855         if (ret) {
7856                 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
7857                         __func__, ret);
7858                 goto out;
7859         }
7860
7861         ufshcd_get_ref_clk_gating_wait(hba);
7862
7863         if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
7864                         QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag))
7865                 hba->dev_info.f_power_on_wp_en = flag;
7866
7867         /* Probe maximum power mode co-supported by both UFS host and device */
7868         if (ufshcd_get_max_pwr_mode(hba))
7869                 dev_err(hba->dev,
7870                         "%s: Failed getting max supported power mode\n",
7871                         __func__);
7872 out:
7873         return ret;
7874 }
7875
7876 /**
7877  * ufshcd_add_lus - probe and add UFS logical units
7878  * @hba: per-adapter instance
7879  */
7880 static int ufshcd_add_lus(struct ufs_hba *hba)
7881 {
7882         int ret;
7883
7884         /* Add required well known logical units to scsi mid layer */
7885         ret = ufshcd_scsi_add_wlus(hba);
7886         if (ret)
7887                 goto out;
7888
7889         ufshcd_clear_ua_wluns(hba);
7890
7891         /* Initialize devfreq after UFS device is detected */
7892         if (ufshcd_is_clkscaling_supported(hba)) {
7893                 memcpy(&hba->clk_scaling.saved_pwr_info.info,
7894                         &hba->pwr_info,
7895                         sizeof(struct ufs_pa_layer_attr));
7896                 hba->clk_scaling.saved_pwr_info.is_valid = true;
7897                 hba->clk_scaling.is_allowed = true;
7898
7899                 ret = ufshcd_devfreq_init(hba);
7900                 if (ret)
7901                         goto out;
7902
7903                 hba->clk_scaling.is_enabled = true;
7904                 ufshcd_init_clk_scaling_sysfs(hba);
7905         }
7906
7907         ufs_bsg_probe(hba);
7908         ufshpb_init(hba);
7909         scsi_scan_host(hba->host);
7910         pm_runtime_put_sync(hba->dev);
7911
7912 out:
7913         return ret;
7914 }
7915
7916 static void ufshcd_request_sense_done(struct request *rq, blk_status_t error)
7917 {
7918         if (error != BLK_STS_OK)
7919                 pr_err("%s: REQUEST SENSE failed (%d)", __func__, error);
7920         blk_put_request(rq);
7921 }
7922
7923 static int
7924 ufshcd_request_sense_async(struct ufs_hba *hba, struct scsi_device *sdev)
7925 {
7926         /*
7927          * From SPC-6: the REQUEST SENSE command with any allocation length
7928          * clears the sense data.
7929          */
7930         static const u8 cmd[6] = {REQUEST_SENSE, 0, 0, 0, 0, 0};
7931         struct scsi_request *rq;
7932         struct request *req;
7933
7934         req = blk_get_request(sdev->request_queue, REQ_OP_DRV_IN, /*flags=*/0);
7935         if (IS_ERR(req))
7936                 return PTR_ERR(req);
7937
7938         rq = scsi_req(req);
7939         rq->cmd_len = ARRAY_SIZE(cmd);
7940         memcpy(rq->cmd, cmd, rq->cmd_len);
7941         rq->retries = 3;
7942         req->timeout = 1 * HZ;
7943         req->rq_flags |= RQF_PM | RQF_QUIET;
7944
7945         blk_execute_rq_nowait(/*bd_disk=*/NULL, req, /*at_head=*/true,
7946                               ufshcd_request_sense_done);
7947         return 0;
7948 }
7949
7950 static int ufshcd_clear_ua_wlun(struct ufs_hba *hba, u8 wlun)
7951 {
7952         struct scsi_device *sdp;
7953         unsigned long flags;
7954         int ret = 0;
7955
7956         spin_lock_irqsave(hba->host->host_lock, flags);
7957         if (wlun == UFS_UPIU_UFS_DEVICE_WLUN)
7958                 sdp = hba->sdev_ufs_device;
7959         else if (wlun == UFS_UPIU_RPMB_WLUN)
7960                 sdp = hba->sdev_rpmb;
7961         else
7962                 BUG();
7963         if (sdp) {
7964                 ret = scsi_device_get(sdp);
7965                 if (!ret && !scsi_device_online(sdp)) {
7966                         ret = -ENODEV;
7967                         scsi_device_put(sdp);
7968                 }
7969         } else {
7970                 ret = -ENODEV;
7971         }
7972         spin_unlock_irqrestore(hba->host->host_lock, flags);
7973         if (ret)
7974                 goto out_err;
7975
7976         ret = ufshcd_request_sense_async(hba, sdp);
7977         scsi_device_put(sdp);
7978 out_err:
7979         if (ret)
7980                 dev_err(hba->dev, "%s: UAC clear LU=%x ret = %d\n",
7981                                 __func__, wlun, ret);
7982         return ret;
7983 }
7984
7985 static int ufshcd_clear_ua_wluns(struct ufs_hba *hba)
7986 {
7987         int ret = 0;
7988
7989         if (!hba->wlun_dev_clr_ua)
7990                 goto out;
7991
7992         ret = ufshcd_clear_ua_wlun(hba, UFS_UPIU_UFS_DEVICE_WLUN);
7993         if (!ret)
7994                 ret = ufshcd_clear_ua_wlun(hba, UFS_UPIU_RPMB_WLUN);
7995         if (!ret)
7996                 hba->wlun_dev_clr_ua = false;
7997 out:
7998         if (ret)
7999                 dev_err(hba->dev, "%s: Failed to clear UAC WLUNS ret = %d\n",
8000                                 __func__, ret);
8001         return ret;
8002 }
8003
8004 /**
8005  * ufshcd_probe_hba - probe hba to detect device and initialize it
8006  * @hba: per-adapter instance
8007  * @init_dev_params: whether or not to call ufshcd_device_params_init().
8008  *
8009  * Execute link-startup and verify device initialization
8010  */
8011 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params)
8012 {
8013         int ret;
8014         unsigned long flags;
8015         ktime_t start = ktime_get();
8016
8017         hba->ufshcd_state = UFSHCD_STATE_RESET;
8018
8019         ret = ufshcd_link_startup(hba);
8020         if (ret)
8021                 goto out;
8022
8023         /* Debug counters initialization */
8024         ufshcd_clear_dbg_ufs_stats(hba);
8025
8026         /* UniPro link is active now */
8027         ufshcd_set_link_active(hba);
8028
8029         /* Verify device initialization by sending NOP OUT UPIU */
8030         ret = ufshcd_verify_dev_init(hba);
8031         if (ret)
8032                 goto out;
8033
8034         /* Initiate UFS initialization, and waiting until completion */
8035         ret = ufshcd_complete_dev_init(hba);
8036         if (ret)
8037                 goto out;
8038
8039         /*
8040          * Initialize UFS device parameters used by driver, these
8041          * parameters are associated with UFS descriptors.
8042          */
8043         if (init_dev_params) {
8044                 ret = ufshcd_device_params_init(hba);
8045                 if (ret)
8046                         goto out;
8047         }
8048
8049         ufshcd_tune_unipro_params(hba);
8050
8051         /* UFS device is also active now */
8052         ufshcd_set_ufs_dev_active(hba);
8053         ufshcd_force_reset_auto_bkops(hba);
8054         hba->wlun_dev_clr_ua = true;
8055         hba->wlun_rpmb_clr_ua = true;
8056
8057         /* Gear up to HS gear if supported */
8058         if (hba->max_pwr_info.is_valid) {
8059                 /*
8060                  * Set the right value to bRefClkFreq before attempting to
8061                  * switch to HS gears.
8062                  */
8063                 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
8064                         ufshcd_set_dev_ref_clk(hba);
8065                 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8066                 if (ret) {
8067                         dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
8068                                         __func__, ret);
8069                         goto out;
8070                 }
8071                 ufshcd_print_pwr_info(hba);
8072         }
8073
8074         /*
8075          * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec)
8076          * and for removable UFS card as well, hence always set the parameter.
8077          * Note: Error handler may issue the device reset hence resetting
8078          * bActiveICCLevel as well so it is always safe to set this here.
8079          */
8080         ufshcd_set_active_icc_lvl(hba);
8081
8082         ufshcd_wb_config(hba);
8083         if (hba->ee_usr_mask)
8084                 ufshcd_write_ee_control(hba);
8085         /* Enable Auto-Hibernate if configured */
8086         ufshcd_auto_hibern8_enable(hba);
8087
8088         ufshpb_reset(hba);
8089 out:
8090         spin_lock_irqsave(hba->host->host_lock, flags);
8091         if (ret)
8092                 hba->ufshcd_state = UFSHCD_STATE_ERROR;
8093         else if (hba->ufshcd_state == UFSHCD_STATE_RESET)
8094                 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
8095         spin_unlock_irqrestore(hba->host->host_lock, flags);
8096
8097         trace_ufshcd_init(dev_name(hba->dev), ret,
8098                 ktime_to_us(ktime_sub(ktime_get(), start)),
8099                 hba->curr_dev_pwr_mode, hba->uic_link_state);
8100         return ret;
8101 }
8102
8103 /**
8104  * ufshcd_async_scan - asynchronous execution for probing hba
8105  * @data: data pointer to pass to this function
8106  * @cookie: cookie data
8107  */
8108 static void ufshcd_async_scan(void *data, async_cookie_t cookie)
8109 {
8110         struct ufs_hba *hba = (struct ufs_hba *)data;
8111         int ret;
8112
8113         down(&hba->host_sem);
8114         /* Initialize hba, detect and initialize UFS device */
8115         ret = ufshcd_probe_hba(hba, true);
8116         up(&hba->host_sem);
8117         if (ret)
8118                 goto out;
8119
8120         /* Probe and add UFS logical units  */
8121         ret = ufshcd_add_lus(hba);
8122 out:
8123         /*
8124          * If we failed to initialize the device or the device is not
8125          * present, turn off the power/clocks etc.
8126          */
8127         if (ret) {
8128                 pm_runtime_put_sync(hba->dev);
8129                 ufshcd_hba_exit(hba);
8130         }
8131 }
8132
8133 static const struct attribute_group *ufshcd_driver_groups[] = {
8134         &ufs_sysfs_unit_descriptor_group,
8135         &ufs_sysfs_lun_attributes_group,
8136 #ifdef CONFIG_SCSI_UFS_HPB
8137         &ufs_sysfs_hpb_stat_group,
8138         &ufs_sysfs_hpb_param_group,
8139 #endif
8140         NULL,
8141 };
8142
8143 static struct ufs_hba_variant_params ufs_hba_vps = {
8144         .hba_enable_delay_us            = 1000,
8145         .wb_flush_threshold             = UFS_WB_BUF_REMAIN_PERCENT(40),
8146         .devfreq_profile.polling_ms     = 100,
8147         .devfreq_profile.target         = ufshcd_devfreq_target,
8148         .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status,
8149         .ondemand_data.upthreshold      = 70,
8150         .ondemand_data.downdifferential = 5,
8151 };
8152
8153 static struct scsi_host_template ufshcd_driver_template = {
8154         .module                 = THIS_MODULE,
8155         .name                   = UFSHCD,
8156         .proc_name              = UFSHCD,
8157         .queuecommand           = ufshcd_queuecommand,
8158         .slave_alloc            = ufshcd_slave_alloc,
8159         .slave_configure        = ufshcd_slave_configure,
8160         .slave_destroy          = ufshcd_slave_destroy,
8161         .change_queue_depth     = ufshcd_change_queue_depth,
8162         .eh_abort_handler       = ufshcd_abort,
8163         .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
8164         .eh_host_reset_handler   = ufshcd_eh_host_reset_handler,
8165         .this_id                = -1,
8166         .sg_tablesize           = SG_ALL,
8167         .cmd_per_lun            = UFSHCD_CMD_PER_LUN,
8168         .can_queue              = UFSHCD_CAN_QUEUE,
8169         .max_segment_size       = PRDT_DATA_BYTE_COUNT_MAX,
8170         .max_host_blocked       = 1,
8171         .track_queue_depth      = 1,
8172         .sdev_groups            = ufshcd_driver_groups,
8173         .dma_boundary           = PAGE_SIZE - 1,
8174         .rpm_autosuspend_delay  = RPM_AUTOSUSPEND_DELAY_MS,
8175 };
8176
8177 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
8178                                    int ua)
8179 {
8180         int ret;
8181
8182         if (!vreg)
8183                 return 0;
8184
8185         /*
8186          * "set_load" operation shall be required on those regulators
8187          * which specifically configured current limitation. Otherwise
8188          * zero max_uA may cause unexpected behavior when regulator is
8189          * enabled or set as high power mode.
8190          */
8191         if (!vreg->max_uA)
8192                 return 0;
8193
8194         ret = regulator_set_load(vreg->reg, ua);
8195         if (ret < 0) {
8196                 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
8197                                 __func__, vreg->name, ua, ret);
8198         }
8199
8200         return ret;
8201 }
8202
8203 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
8204                                          struct ufs_vreg *vreg)
8205 {
8206         return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
8207 }
8208
8209 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
8210                                          struct ufs_vreg *vreg)
8211 {
8212         if (!vreg)
8213                 return 0;
8214
8215         return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
8216 }
8217
8218 static int ufshcd_config_vreg(struct device *dev,
8219                 struct ufs_vreg *vreg, bool on)
8220 {
8221         int ret = 0;
8222         struct regulator *reg;
8223         const char *name;
8224         int min_uV, uA_load;
8225
8226         BUG_ON(!vreg);
8227
8228         reg = vreg->reg;
8229         name = vreg->name;
8230
8231         if (regulator_count_voltages(reg) > 0) {
8232                 uA_load = on ? vreg->max_uA : 0;
8233                 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
8234                 if (ret)
8235                         goto out;
8236
8237                 if (vreg->min_uV && vreg->max_uV) {
8238                         min_uV = on ? vreg->min_uV : 0;
8239                         ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
8240                         if (ret)
8241                                 dev_err(dev,
8242                                         "%s: %s set voltage failed, err=%d\n",
8243                                         __func__, name, ret);
8244                 }
8245         }
8246 out:
8247         return ret;
8248 }
8249
8250 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
8251 {
8252         int ret = 0;
8253
8254         if (!vreg || vreg->enabled)
8255                 goto out;
8256
8257         ret = ufshcd_config_vreg(dev, vreg, true);
8258         if (!ret)
8259                 ret = regulator_enable(vreg->reg);
8260
8261         if (!ret)
8262                 vreg->enabled = true;
8263         else
8264                 dev_err(dev, "%s: %s enable failed, err=%d\n",
8265                                 __func__, vreg->name, ret);
8266 out:
8267         return ret;
8268 }
8269
8270 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
8271 {
8272         int ret = 0;
8273
8274         if (!vreg || !vreg->enabled || vreg->always_on)
8275                 goto out;
8276
8277         ret = regulator_disable(vreg->reg);
8278
8279         if (!ret) {
8280                 /* ignore errors on applying disable config */
8281                 ufshcd_config_vreg(dev, vreg, false);
8282                 vreg->enabled = false;
8283         } else {
8284                 dev_err(dev, "%s: %s disable failed, err=%d\n",
8285                                 __func__, vreg->name, ret);
8286         }
8287 out:
8288         return ret;
8289 }
8290
8291 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
8292 {
8293         int ret = 0;
8294         struct device *dev = hba->dev;
8295         struct ufs_vreg_info *info = &hba->vreg_info;
8296
8297         ret = ufshcd_toggle_vreg(dev, info->vcc, on);
8298         if (ret)
8299                 goto out;
8300
8301         ret = ufshcd_toggle_vreg(dev, info->vccq, on);
8302         if (ret)
8303                 goto out;
8304
8305         ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
8306
8307 out:
8308         if (ret) {
8309                 ufshcd_toggle_vreg(dev, info->vccq2, false);
8310                 ufshcd_toggle_vreg(dev, info->vccq, false);
8311                 ufshcd_toggle_vreg(dev, info->vcc, false);
8312         }
8313         return ret;
8314 }
8315
8316 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
8317 {
8318         struct ufs_vreg_info *info = &hba->vreg_info;
8319
8320         return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
8321 }
8322
8323 static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
8324 {
8325         int ret = 0;
8326
8327         if (!vreg)
8328                 goto out;
8329
8330         vreg->reg = devm_regulator_get(dev, vreg->name);
8331         if (IS_ERR(vreg->reg)) {
8332                 ret = PTR_ERR(vreg->reg);
8333                 dev_err(dev, "%s: %s get failed, err=%d\n",
8334                                 __func__, vreg->name, ret);
8335         }
8336 out:
8337         return ret;
8338 }
8339
8340 static int ufshcd_init_vreg(struct ufs_hba *hba)
8341 {
8342         int ret = 0;
8343         struct device *dev = hba->dev;
8344         struct ufs_vreg_info *info = &hba->vreg_info;
8345
8346         ret = ufshcd_get_vreg(dev, info->vcc);
8347         if (ret)
8348                 goto out;
8349
8350         ret = ufshcd_get_vreg(dev, info->vccq);
8351         if (!ret)
8352                 ret = ufshcd_get_vreg(dev, info->vccq2);
8353 out:
8354         return ret;
8355 }
8356
8357 static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
8358 {
8359         struct ufs_vreg_info *info = &hba->vreg_info;
8360
8361         if (info)
8362                 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
8363
8364         return 0;
8365 }
8366
8367 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
8368 {
8369         int ret = 0;
8370         struct ufs_clk_info *clki;
8371         struct list_head *head = &hba->clk_list_head;
8372         unsigned long flags;
8373         ktime_t start = ktime_get();
8374         bool clk_state_changed = false;
8375
8376         if (list_empty(head))
8377                 goto out;
8378
8379         ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
8380         if (ret)
8381                 return ret;
8382
8383         list_for_each_entry(clki, head, list) {
8384                 if (!IS_ERR_OR_NULL(clki->clk)) {
8385                         /*
8386                          * Don't disable clocks which are needed
8387                          * to keep the link active.
8388                          */
8389                         if (ufshcd_is_link_active(hba) &&
8390                             clki->keep_link_active)
8391                                 continue;
8392
8393                         clk_state_changed = on ^ clki->enabled;
8394                         if (on && !clki->enabled) {
8395                                 ret = clk_prepare_enable(clki->clk);
8396                                 if (ret) {
8397                                         dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
8398                                                 __func__, clki->name, ret);
8399                                         goto out;
8400                                 }
8401                         } else if (!on && clki->enabled) {
8402                                 clk_disable_unprepare(clki->clk);
8403                         }
8404                         clki->enabled = on;
8405                         dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
8406                                         clki->name, on ? "en" : "dis");
8407                 }
8408         }
8409
8410         ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
8411         if (ret)
8412                 return ret;
8413
8414 out:
8415         if (ret) {
8416                 list_for_each_entry(clki, head, list) {
8417                         if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
8418                                 clk_disable_unprepare(clki->clk);
8419                 }
8420         } else if (!ret && on) {
8421                 spin_lock_irqsave(hba->host->host_lock, flags);
8422                 hba->clk_gating.state = CLKS_ON;
8423                 trace_ufshcd_clk_gating(dev_name(hba->dev),
8424                                         hba->clk_gating.state);
8425                 spin_unlock_irqrestore(hba->host->host_lock, flags);
8426         }
8427
8428         if (clk_state_changed)
8429                 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
8430                         (on ? "on" : "off"),
8431                         ktime_to_us(ktime_sub(ktime_get(), start)), ret);
8432         return ret;
8433 }
8434
8435 static int ufshcd_init_clocks(struct ufs_hba *hba)
8436 {
8437         int ret = 0;
8438         struct ufs_clk_info *clki;
8439         struct device *dev = hba->dev;
8440         struct list_head *head = &hba->clk_list_head;
8441
8442         if (list_empty(head))
8443                 goto out;
8444
8445         list_for_each_entry(clki, head, list) {
8446                 if (!clki->name)
8447                         continue;
8448
8449                 clki->clk = devm_clk_get(dev, clki->name);
8450                 if (IS_ERR(clki->clk)) {
8451                         ret = PTR_ERR(clki->clk);
8452                         dev_err(dev, "%s: %s clk get failed, %d\n",
8453                                         __func__, clki->name, ret);
8454                         goto out;
8455                 }
8456
8457                 /*
8458                  * Parse device ref clk freq as per device tree "ref_clk".
8459                  * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
8460                  * in ufshcd_alloc_host().
8461                  */
8462                 if (!strcmp(clki->name, "ref_clk"))
8463                         ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
8464
8465                 if (clki->max_freq) {
8466                         ret = clk_set_rate(clki->clk, clki->max_freq);
8467                         if (ret) {
8468                                 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
8469                                         __func__, clki->name,
8470                                         clki->max_freq, ret);
8471                                 goto out;
8472                         }
8473                         clki->curr_freq = clki->max_freq;
8474                 }
8475                 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
8476                                 clki->name, clk_get_rate(clki->clk));
8477         }
8478 out:
8479         return ret;
8480 }
8481
8482 static int ufshcd_variant_hba_init(struct ufs_hba *hba)
8483 {
8484         int err = 0;
8485
8486         if (!hba->vops)
8487                 goto out;
8488
8489         err = ufshcd_vops_init(hba);
8490         if (err)
8491                 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
8492                         __func__, ufshcd_get_var_name(hba), err);
8493 out:
8494         return err;
8495 }
8496
8497 static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
8498 {
8499         if (!hba->vops)
8500                 return;
8501
8502         ufshcd_vops_exit(hba);
8503 }
8504
8505 static int ufshcd_hba_init(struct ufs_hba *hba)
8506 {
8507         int err;
8508
8509         /*
8510          * Handle host controller power separately from the UFS device power
8511          * rails as it will help controlling the UFS host controller power
8512          * collapse easily which is different than UFS device power collapse.
8513          * Also, enable the host controller power before we go ahead with rest
8514          * of the initialization here.
8515          */
8516         err = ufshcd_init_hba_vreg(hba);
8517         if (err)
8518                 goto out;
8519
8520         err = ufshcd_setup_hba_vreg(hba, true);
8521         if (err)
8522                 goto out;
8523
8524         err = ufshcd_init_clocks(hba);
8525         if (err)
8526                 goto out_disable_hba_vreg;
8527
8528         err = ufshcd_setup_clocks(hba, true);
8529         if (err)
8530                 goto out_disable_hba_vreg;
8531
8532         err = ufshcd_init_vreg(hba);
8533         if (err)
8534                 goto out_disable_clks;
8535
8536         err = ufshcd_setup_vreg(hba, true);
8537         if (err)
8538                 goto out_disable_clks;
8539
8540         err = ufshcd_variant_hba_init(hba);
8541         if (err)
8542                 goto out_disable_vreg;
8543
8544         ufs_debugfs_hba_init(hba);
8545
8546         hba->is_powered = true;
8547         goto out;
8548
8549 out_disable_vreg:
8550         ufshcd_setup_vreg(hba, false);
8551 out_disable_clks:
8552         ufshcd_setup_clocks(hba, false);
8553 out_disable_hba_vreg:
8554         ufshcd_setup_hba_vreg(hba, false);
8555 out:
8556         return err;
8557 }
8558
8559 static void ufshcd_hba_exit(struct ufs_hba *hba)
8560 {
8561         if (hba->is_powered) {
8562                 ufshcd_exit_clk_scaling(hba);
8563                 ufshcd_exit_clk_gating(hba);
8564                 ufs_debugfs_hba_exit(hba);
8565                 ufshcd_variant_hba_exit(hba);
8566                 ufshcd_setup_vreg(hba, false);
8567                 ufshcd_setup_clocks(hba, false);
8568                 ufshcd_setup_hba_vreg(hba, false);
8569                 hba->is_powered = false;
8570                 ufs_put_device_desc(hba);
8571         }
8572 }
8573
8574 /**
8575  * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
8576  *                           power mode
8577  * @hba: per adapter instance
8578  * @pwr_mode: device power mode to set
8579  *
8580  * Returns 0 if requested power mode is set successfully
8581  * Returns non-zero if failed to set the requested power mode
8582  */
8583 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
8584                                      enum ufs_dev_pwr_mode pwr_mode)
8585 {
8586         unsigned char cmd[6] = { START_STOP };
8587         struct scsi_sense_hdr sshdr;
8588         struct scsi_device *sdp;
8589         unsigned long flags;
8590         int ret;
8591
8592         spin_lock_irqsave(hba->host->host_lock, flags);
8593         sdp = hba->sdev_ufs_device;
8594         if (sdp) {
8595                 ret = scsi_device_get(sdp);
8596                 if (!ret && !scsi_device_online(sdp)) {
8597                         ret = -ENODEV;
8598                         scsi_device_put(sdp);
8599                 }
8600         } else {
8601                 ret = -ENODEV;
8602         }
8603         spin_unlock_irqrestore(hba->host->host_lock, flags);
8604
8605         if (ret)
8606                 return ret;
8607
8608         /*
8609          * If scsi commands fail, the scsi mid-layer schedules scsi error-
8610          * handling, which would wait for host to be resumed. Since we know
8611          * we are functional while we are here, skip host resume in error
8612          * handling context.
8613          */
8614         hba->host->eh_noresume = 1;
8615         if (hba->wlun_dev_clr_ua)
8616                 ufshcd_clear_ua_wlun(hba, UFS_UPIU_UFS_DEVICE_WLUN);
8617
8618         cmd[4] = pwr_mode << 4;
8619
8620         /*
8621          * Current function would be generally called from the power management
8622          * callbacks hence set the RQF_PM flag so that it doesn't resume the
8623          * already suspended childs.
8624          */
8625         ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
8626                         START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
8627         if (ret) {
8628                 sdev_printk(KERN_WARNING, sdp,
8629                             "START_STOP failed for power mode: %d, result %x\n",
8630                             pwr_mode, ret);
8631                 if (ret > 0 && scsi_sense_valid(&sshdr))
8632                         scsi_print_sense_hdr(sdp, NULL, &sshdr);
8633         }
8634
8635         if (!ret)
8636                 hba->curr_dev_pwr_mode = pwr_mode;
8637
8638         scsi_device_put(sdp);
8639         hba->host->eh_noresume = 0;
8640         return ret;
8641 }
8642
8643 static int ufshcd_link_state_transition(struct ufs_hba *hba,
8644                                         enum uic_link_state req_link_state,
8645                                         int check_for_bkops)
8646 {
8647         int ret = 0;
8648
8649         if (req_link_state == hba->uic_link_state)
8650                 return 0;
8651
8652         if (req_link_state == UIC_LINK_HIBERN8_STATE) {
8653                 ret = ufshcd_uic_hibern8_enter(hba);
8654                 if (!ret) {
8655                         ufshcd_set_link_hibern8(hba);
8656                 } else {
8657                         dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
8658                                         __func__, ret);
8659                         goto out;
8660                 }
8661         }
8662         /*
8663          * If autobkops is enabled, link can't be turned off because
8664          * turning off the link would also turn off the device, except in the
8665          * case of DeepSleep where the device is expected to remain powered.
8666          */
8667         else if ((req_link_state == UIC_LINK_OFF_STATE) &&
8668                  (!check_for_bkops || !hba->auto_bkops_enabled)) {
8669                 /*
8670                  * Let's make sure that link is in low power mode, we are doing
8671                  * this currently by putting the link in Hibern8. Otherway to
8672                  * put the link in low power mode is to send the DME end point
8673                  * to device and then send the DME reset command to local
8674                  * unipro. But putting the link in hibern8 is much faster.
8675                  *
8676                  * Note also that putting the link in Hibern8 is a requirement
8677                  * for entering DeepSleep.
8678                  */
8679                 ret = ufshcd_uic_hibern8_enter(hba);
8680                 if (ret) {
8681                         dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
8682                                         __func__, ret);
8683                         goto out;
8684                 }
8685                 /*
8686                  * Change controller state to "reset state" which
8687                  * should also put the link in off/reset state
8688                  */
8689                 ufshcd_hba_stop(hba);
8690                 /*
8691                  * TODO: Check if we need any delay to make sure that
8692                  * controller is reset
8693                  */
8694                 ufshcd_set_link_off(hba);
8695         }
8696
8697 out:
8698         return ret;
8699 }
8700
8701 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
8702 {
8703         bool vcc_off = false;
8704
8705         /*
8706          * It seems some UFS devices may keep drawing more than sleep current
8707          * (atleast for 500us) from UFS rails (especially from VCCQ rail).
8708          * To avoid this situation, add 2ms delay before putting these UFS
8709          * rails in LPM mode.
8710          */
8711         if (!ufshcd_is_link_active(hba) &&
8712             hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
8713                 usleep_range(2000, 2100);
8714
8715         /*
8716          * If UFS device is either in UFS_Sleep turn off VCC rail to save some
8717          * power.
8718          *
8719          * If UFS device and link is in OFF state, all power supplies (VCC,
8720          * VCCQ, VCCQ2) can be turned off if power on write protect is not
8721          * required. If UFS link is inactive (Hibern8 or OFF state) and device
8722          * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
8723          *
8724          * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
8725          * in low power state which would save some power.
8726          *
8727          * If Write Booster is enabled and the device needs to flush the WB
8728          * buffer OR if bkops status is urgent for WB, keep Vcc on.
8729          */
8730         if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8731             !hba->dev_info.is_lu_power_on_wp) {
8732                 ufshcd_setup_vreg(hba, false);
8733                 vcc_off = true;
8734         } else if (!ufshcd_is_ufs_dev_active(hba)) {
8735                 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
8736                 vcc_off = true;
8737                 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) {
8738                         ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8739                         ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
8740                 }
8741         }
8742
8743         /*
8744          * Some UFS devices require delay after VCC power rail is turned-off.
8745          */
8746         if (vcc_off && hba->vreg_info.vcc &&
8747                 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)
8748                 usleep_range(5000, 5100);
8749 }
8750
8751 #ifdef CONFIG_PM
8752 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
8753 {
8754         int ret = 0;
8755
8756         if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8757             !hba->dev_info.is_lu_power_on_wp) {
8758                 ret = ufshcd_setup_vreg(hba, true);
8759         } else if (!ufshcd_is_ufs_dev_active(hba)) {
8760                 if (!ufshcd_is_link_active(hba)) {
8761                         ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
8762                         if (ret)
8763                                 goto vcc_disable;
8764                         ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
8765                         if (ret)
8766                                 goto vccq_lpm;
8767                 }
8768                 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
8769         }
8770         goto out;
8771
8772 vccq_lpm:
8773         ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8774 vcc_disable:
8775         ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
8776 out:
8777         return ret;
8778 }
8779 #endif /* CONFIG_PM */
8780
8781 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
8782 {
8783         if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
8784                 ufshcd_setup_hba_vreg(hba, false);
8785 }
8786
8787 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
8788 {
8789         if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
8790                 ufshcd_setup_hba_vreg(hba, true);
8791 }
8792
8793 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
8794 {
8795         int ret = 0;
8796         int check_for_bkops;
8797         enum ufs_pm_level pm_lvl;
8798         enum ufs_dev_pwr_mode req_dev_pwr_mode;
8799         enum uic_link_state req_link_state;
8800
8801         hba->pm_op_in_progress = true;
8802         if (pm_op != UFS_SHUTDOWN_PM) {
8803                 pm_lvl = pm_op == UFS_RUNTIME_PM ?
8804                          hba->rpm_lvl : hba->spm_lvl;
8805                 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
8806                 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
8807         } else {
8808                 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
8809                 req_link_state = UIC_LINK_OFF_STATE;
8810         }
8811
8812         ufshpb_suspend(hba);
8813
8814         /*
8815          * If we can't transition into any of the low power modes
8816          * just gate the clocks.
8817          */
8818         ufshcd_hold(hba, false);
8819         hba->clk_gating.is_suspended = true;
8820
8821         if (ufshcd_is_clkscaling_supported(hba))
8822                 ufshcd_clk_scaling_suspend(hba, true);
8823
8824         if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
8825                         req_link_state == UIC_LINK_ACTIVE_STATE) {
8826                 goto vops_suspend;
8827         }
8828
8829         if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
8830             (req_link_state == hba->uic_link_state))
8831                 goto enable_scaling;
8832
8833         /* UFS device & link must be active before we enter in this function */
8834         if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
8835                 ret = -EINVAL;
8836                 goto enable_scaling;
8837         }
8838
8839         if (pm_op == UFS_RUNTIME_PM) {
8840                 if (ufshcd_can_autobkops_during_suspend(hba)) {
8841                         /*
8842                          * The device is idle with no requests in the queue,
8843                          * allow background operations if bkops status shows
8844                          * that performance might be impacted.
8845                          */
8846                         ret = ufshcd_urgent_bkops(hba);
8847                         if (ret)
8848                                 goto enable_scaling;
8849                 } else {
8850                         /* make sure that auto bkops is disabled */
8851                         ufshcd_disable_auto_bkops(hba);
8852                 }
8853                 /*
8854                  * If device needs to do BKOP or WB buffer flush during
8855                  * Hibern8, keep device power mode as "active power mode"
8856                  * and VCC supply.
8857                  */
8858                 hba->dev_info.b_rpm_dev_flush_capable =
8859                         hba->auto_bkops_enabled ||
8860                         (((req_link_state == UIC_LINK_HIBERN8_STATE) ||
8861                         ((req_link_state == UIC_LINK_ACTIVE_STATE) &&
8862                         ufshcd_is_auto_hibern8_enabled(hba))) &&
8863                         ufshcd_wb_need_flush(hba));
8864         }
8865
8866         flush_work(&hba->eeh_work);
8867
8868         if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {
8869                 if (pm_op != UFS_RUNTIME_PM)
8870                         /* ensure that bkops is disabled */
8871                         ufshcd_disable_auto_bkops(hba);
8872
8873                 if (!hba->dev_info.b_rpm_dev_flush_capable) {
8874                         ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
8875                         if (ret)
8876                                 goto enable_scaling;
8877                 }
8878         }
8879
8880         /*
8881          * In the case of DeepSleep, the device is expected to remain powered
8882          * with the link off, so do not check for bkops.
8883          */
8884         check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba);
8885         ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops);
8886         if (ret)
8887                 goto set_dev_active;
8888
8889 vops_suspend:
8890         /*
8891          * Call vendor specific suspend callback. As these callbacks may access
8892          * vendor specific host controller register space call them before the
8893          * host clocks are ON.
8894          */
8895         ret = ufshcd_vops_suspend(hba, pm_op);
8896         if (ret)
8897                 goto set_link_active;
8898         goto out;
8899
8900 set_link_active:
8901         /*
8902          * Device hardware reset is required to exit DeepSleep. Also, for
8903          * DeepSleep, the link is off so host reset and restore will be done
8904          * further below.
8905          */
8906         if (ufshcd_is_ufs_dev_deepsleep(hba)) {
8907                 ufshcd_device_reset(hba);
8908                 WARN_ON(!ufshcd_is_link_off(hba));
8909         }
8910         if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
8911                 ufshcd_set_link_active(hba);
8912         else if (ufshcd_is_link_off(hba))
8913                 ufshcd_host_reset_and_restore(hba);
8914 set_dev_active:
8915         /* Can also get here needing to exit DeepSleep */
8916         if (ufshcd_is_ufs_dev_deepsleep(hba)) {
8917                 ufshcd_device_reset(hba);
8918                 ufshcd_host_reset_and_restore(hba);
8919         }
8920         if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
8921                 ufshcd_disable_auto_bkops(hba);
8922 enable_scaling:
8923         if (ufshcd_is_clkscaling_supported(hba))
8924                 ufshcd_clk_scaling_suspend(hba, false);
8925
8926         hba->dev_info.b_rpm_dev_flush_capable = false;
8927 out:
8928         if (hba->dev_info.b_rpm_dev_flush_capable) {
8929                 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work,
8930                         msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS));
8931         }
8932
8933         if (ret) {
8934                 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret);
8935                 hba->clk_gating.is_suspended = false;
8936                 ufshcd_release(hba);
8937                 ufshpb_resume(hba);
8938         }
8939         hba->pm_op_in_progress = false;
8940         return ret;
8941 }
8942
8943 #ifdef CONFIG_PM
8944 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
8945 {
8946         int ret;
8947         enum uic_link_state old_link_state = hba->uic_link_state;
8948
8949         hba->pm_op_in_progress = true;
8950
8951         /*
8952          * Call vendor specific resume callback. As these callbacks may access
8953          * vendor specific host controller register space call them when the
8954          * host clocks are ON.
8955          */
8956         ret = ufshcd_vops_resume(hba, pm_op);
8957         if (ret)
8958                 goto out;
8959
8960         /* For DeepSleep, the only supported option is to have the link off */
8961         WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba));
8962
8963         if (ufshcd_is_link_hibern8(hba)) {
8964                 ret = ufshcd_uic_hibern8_exit(hba);
8965                 if (!ret) {
8966                         ufshcd_set_link_active(hba);
8967                 } else {
8968                         dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
8969                                         __func__, ret);
8970                         goto vendor_suspend;
8971                 }
8972         } else if (ufshcd_is_link_off(hba)) {
8973                 /*
8974                  * A full initialization of the host and the device is
8975                  * required since the link was put to off during suspend.
8976                  * Note, in the case of DeepSleep, the device will exit
8977                  * DeepSleep due to device reset.
8978                  */
8979                 ret = ufshcd_reset_and_restore(hba);
8980                 /*
8981                  * ufshcd_reset_and_restore() should have already
8982                  * set the link state as active
8983                  */
8984                 if (ret || !ufshcd_is_link_active(hba))
8985                         goto vendor_suspend;
8986         }
8987
8988         if (!ufshcd_is_ufs_dev_active(hba)) {
8989                 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
8990                 if (ret)
8991                         goto set_old_link_state;
8992         }
8993
8994         if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
8995                 ufshcd_enable_auto_bkops(hba);
8996         else
8997                 /*
8998                  * If BKOPs operations are urgently needed at this moment then
8999                  * keep auto-bkops enabled or else disable it.
9000                  */
9001                 ufshcd_urgent_bkops(hba);
9002
9003         if (hba->ee_usr_mask)
9004                 ufshcd_write_ee_control(hba);
9005
9006         if (ufshcd_is_clkscaling_supported(hba))
9007                 ufshcd_clk_scaling_suspend(hba, false);
9008
9009         if (hba->dev_info.b_rpm_dev_flush_capable) {
9010                 hba->dev_info.b_rpm_dev_flush_capable = false;
9011                 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work);
9012         }
9013
9014         /* Enable Auto-Hibernate if configured */
9015         ufshcd_auto_hibern8_enable(hba);
9016
9017         ufshpb_resume(hba);
9018         goto out;
9019
9020 set_old_link_state:
9021         ufshcd_link_state_transition(hba, old_link_state, 0);
9022 vendor_suspend:
9023         ufshcd_vops_suspend(hba, pm_op);
9024 out:
9025         if (ret)
9026                 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret);
9027         hba->clk_gating.is_suspended = false;
9028         ufshcd_release(hba);
9029         hba->pm_op_in_progress = false;
9030         return ret;
9031 }
9032
9033 static int ufshcd_wl_runtime_suspend(struct device *dev)
9034 {
9035         struct scsi_device *sdev = to_scsi_device(dev);
9036         struct ufs_hba *hba;
9037         int ret;
9038         ktime_t start = ktime_get();
9039
9040         hba = shost_priv(sdev->host);
9041
9042         ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM);
9043         if (ret)
9044                 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9045
9046         trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret,
9047                 ktime_to_us(ktime_sub(ktime_get(), start)),
9048                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9049
9050         return ret;
9051 }
9052
9053 static int ufshcd_wl_runtime_resume(struct device *dev)
9054 {
9055         struct scsi_device *sdev = to_scsi_device(dev);
9056         struct ufs_hba *hba;
9057         int ret = 0;
9058         ktime_t start = ktime_get();
9059
9060         hba = shost_priv(sdev->host);
9061
9062         ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM);
9063         if (ret)
9064                 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9065
9066         trace_ufshcd_wl_runtime_resume(dev_name(dev), ret,
9067                 ktime_to_us(ktime_sub(ktime_get(), start)),
9068                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9069
9070         return ret;
9071 }
9072 #endif
9073
9074 #ifdef CONFIG_PM_SLEEP
9075 static int ufshcd_wl_suspend(struct device *dev)
9076 {
9077         struct scsi_device *sdev = to_scsi_device(dev);
9078         struct ufs_hba *hba;
9079         int ret = 0;
9080         ktime_t start = ktime_get();
9081
9082         hba = shost_priv(sdev->host);
9083         down(&hba->host_sem);
9084
9085         if (pm_runtime_suspended(dev))
9086                 goto out;
9087
9088         ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM);
9089         if (ret) {
9090                 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__,  ret);
9091                 up(&hba->host_sem);
9092         }
9093
9094 out:
9095         if (!ret)
9096                 hba->is_sys_suspended = true;
9097         trace_ufshcd_wl_suspend(dev_name(dev), ret,
9098                 ktime_to_us(ktime_sub(ktime_get(), start)),
9099                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9100
9101         return ret;
9102 }
9103
9104 static int ufshcd_wl_resume(struct device *dev)
9105 {
9106         struct scsi_device *sdev = to_scsi_device(dev);
9107         struct ufs_hba *hba;
9108         int ret = 0;
9109         ktime_t start = ktime_get();
9110
9111         hba = shost_priv(sdev->host);
9112
9113         if (pm_runtime_suspended(dev))
9114                 goto out;
9115
9116         ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM);
9117         if (ret)
9118                 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9119 out:
9120         trace_ufshcd_wl_resume(dev_name(dev), ret,
9121                 ktime_to_us(ktime_sub(ktime_get(), start)),
9122                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9123         if (!ret)
9124                 hba->is_sys_suspended = false;
9125         up(&hba->host_sem);
9126         return ret;
9127 }
9128 #endif
9129
9130 static void ufshcd_wl_shutdown(struct device *dev)
9131 {
9132         struct scsi_device *sdev = to_scsi_device(dev);
9133         struct ufs_hba *hba;
9134
9135         hba = shost_priv(sdev->host);
9136
9137         down(&hba->host_sem);
9138         hba->shutting_down = true;
9139         up(&hba->host_sem);
9140
9141         /* Turn on everything while shutting down */
9142         ufshcd_rpm_get_sync(hba);
9143         scsi_device_quiesce(sdev);
9144         shost_for_each_device(sdev, hba->host) {
9145                 if (sdev == hba->sdev_ufs_device)
9146                         continue;
9147                 scsi_device_quiesce(sdev);
9148         }
9149         __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
9150 }
9151
9152 /**
9153  * ufshcd_suspend - helper function for suspend operations
9154  * @hba: per adapter instance
9155  *
9156  * This function will put disable irqs, turn off clocks
9157  * and set vreg and hba-vreg in lpm mode.
9158  */
9159 static int ufshcd_suspend(struct ufs_hba *hba)
9160 {
9161         int ret;
9162
9163         if (!hba->is_powered)
9164                 return 0;
9165         /*
9166          * Disable the host irq as host controller as there won't be any
9167          * host controller transaction expected till resume.
9168          */
9169         ufshcd_disable_irq(hba);
9170         ret = ufshcd_setup_clocks(hba, false);
9171         if (ret) {
9172                 ufshcd_enable_irq(hba);
9173                 return ret;
9174         }
9175         if (ufshcd_is_clkgating_allowed(hba)) {
9176                 hba->clk_gating.state = CLKS_OFF;
9177                 trace_ufshcd_clk_gating(dev_name(hba->dev),
9178                                         hba->clk_gating.state);
9179         }
9180
9181         ufshcd_vreg_set_lpm(hba);
9182         /* Put the host controller in low power mode if possible */
9183         ufshcd_hba_vreg_set_lpm(hba);
9184         return ret;
9185 }
9186
9187 #ifdef CONFIG_PM
9188 /**
9189  * ufshcd_resume - helper function for resume operations
9190  * @hba: per adapter instance
9191  *
9192  * This function basically turns on the regulators, clocks and
9193  * irqs of the hba.
9194  *
9195  * Returns 0 for success and non-zero for failure
9196  */
9197 static int ufshcd_resume(struct ufs_hba *hba)
9198 {
9199         int ret;
9200
9201         if (!hba->is_powered)
9202                 return 0;
9203
9204         ufshcd_hba_vreg_set_hpm(hba);
9205         ret = ufshcd_vreg_set_hpm(hba);
9206         if (ret)
9207                 goto out;
9208
9209         /* Make sure clocks are enabled before accessing controller */
9210         ret = ufshcd_setup_clocks(hba, true);
9211         if (ret)
9212                 goto disable_vreg;
9213
9214         /* enable the host irq as host controller would be active soon */
9215         ufshcd_enable_irq(hba);
9216         goto out;
9217
9218 disable_vreg:
9219         ufshcd_vreg_set_lpm(hba);
9220 out:
9221         if (ret)
9222                 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret);
9223         return ret;
9224 }
9225 #endif /* CONFIG_PM */
9226
9227 #ifdef CONFIG_PM_SLEEP
9228 /**
9229  * ufshcd_system_suspend - system suspend callback
9230  * @dev: Device associated with the UFS controller.
9231  *
9232  * Executed before putting the system into a sleep state in which the contents
9233  * of main memory are preserved.
9234  *
9235  * Returns 0 for success and non-zero for failure
9236  */
9237 int ufshcd_system_suspend(struct device *dev)
9238 {
9239         struct ufs_hba *hba = dev_get_drvdata(dev);
9240         int ret = 0;
9241         ktime_t start = ktime_get();
9242
9243         if (pm_runtime_suspended(hba->dev))
9244                 goto out;
9245
9246         ret = ufshcd_suspend(hba);
9247 out:
9248         trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
9249                 ktime_to_us(ktime_sub(ktime_get(), start)),
9250                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9251         return ret;
9252 }
9253 EXPORT_SYMBOL(ufshcd_system_suspend);
9254
9255 /**
9256  * ufshcd_system_resume - system resume callback
9257  * @dev: Device associated with the UFS controller.
9258  *
9259  * Executed after waking the system up from a sleep state in which the contents
9260  * of main memory were preserved.
9261  *
9262  * Returns 0 for success and non-zero for failure
9263  */
9264 int ufshcd_system_resume(struct device *dev)
9265 {
9266         struct ufs_hba *hba = dev_get_drvdata(dev);
9267         ktime_t start = ktime_get();
9268         int ret = 0;
9269
9270         if (pm_runtime_suspended(hba->dev))
9271                 goto out;
9272
9273         ret = ufshcd_resume(hba);
9274
9275 out:
9276         trace_ufshcd_system_resume(dev_name(hba->dev), ret,
9277                 ktime_to_us(ktime_sub(ktime_get(), start)),
9278                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9279
9280         return ret;
9281 }
9282 EXPORT_SYMBOL(ufshcd_system_resume);
9283 #endif /* CONFIG_PM_SLEEP */
9284
9285 #ifdef CONFIG_PM
9286 /**
9287  * ufshcd_runtime_suspend - runtime suspend callback
9288  * @dev: Device associated with the UFS controller.
9289  *
9290  * Check the description of ufshcd_suspend() function for more details.
9291  *
9292  * Returns 0 for success and non-zero for failure
9293  */
9294 int ufshcd_runtime_suspend(struct device *dev)
9295 {
9296         struct ufs_hba *hba = dev_get_drvdata(dev);
9297         int ret;
9298         ktime_t start = ktime_get();
9299
9300         ret = ufshcd_suspend(hba);
9301
9302         trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
9303                 ktime_to_us(ktime_sub(ktime_get(), start)),
9304                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9305         return ret;
9306 }
9307 EXPORT_SYMBOL(ufshcd_runtime_suspend);
9308
9309 /**
9310  * ufshcd_runtime_resume - runtime resume routine
9311  * @dev: Device associated with the UFS controller.
9312  *
9313  * This function basically brings controller
9314  * to active state. Following operations are done in this function:
9315  *
9316  * 1. Turn on all the controller related clocks
9317  * 2. Turn ON VCC rail
9318  */
9319 int ufshcd_runtime_resume(struct device *dev)
9320 {
9321         struct ufs_hba *hba = dev_get_drvdata(dev);
9322         int ret;
9323         ktime_t start = ktime_get();
9324
9325         ret = ufshcd_resume(hba);
9326
9327         trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
9328                 ktime_to_us(ktime_sub(ktime_get(), start)),
9329                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9330         return ret;
9331 }
9332 EXPORT_SYMBOL(ufshcd_runtime_resume);
9333 #endif /* CONFIG_PM */
9334
9335 /**
9336  * ufshcd_shutdown - shutdown routine
9337  * @hba: per adapter instance
9338  *
9339  * This function would turn off both UFS device and UFS hba
9340  * regulators. It would also disable clocks.
9341  *
9342  * Returns 0 always to allow force shutdown even in case of errors.
9343  */
9344 int ufshcd_shutdown(struct ufs_hba *hba)
9345 {
9346         if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
9347                 goto out;
9348
9349         pm_runtime_get_sync(hba->dev);
9350
9351         ufshcd_suspend(hba);
9352 out:
9353         hba->is_powered = false;
9354         /* allow force shutdown even in case of errors */
9355         return 0;
9356 }
9357 EXPORT_SYMBOL(ufshcd_shutdown);
9358
9359 /**
9360  * ufshcd_remove - de-allocate SCSI host and host memory space
9361  *              data structure memory
9362  * @hba: per adapter instance
9363  */
9364 void ufshcd_remove(struct ufs_hba *hba)
9365 {
9366         if (hba->sdev_ufs_device)
9367                 ufshcd_rpm_get_sync(hba);
9368         ufs_bsg_remove(hba);
9369         ufshpb_remove(hba);
9370         ufs_sysfs_remove_nodes(hba->dev);
9371         blk_cleanup_queue(hba->tmf_queue);
9372         blk_mq_free_tag_set(&hba->tmf_tag_set);
9373         blk_cleanup_queue(hba->cmd_queue);
9374         scsi_remove_host(hba->host);
9375         /* disable interrupts */
9376         ufshcd_disable_intr(hba, hba->intr_mask);
9377         ufshcd_hba_stop(hba);
9378         ufshcd_hba_exit(hba);
9379 }
9380 EXPORT_SYMBOL_GPL(ufshcd_remove);
9381
9382 /**
9383  * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
9384  * @hba: pointer to Host Bus Adapter (HBA)
9385  */
9386 void ufshcd_dealloc_host(struct ufs_hba *hba)
9387 {
9388         scsi_host_put(hba->host);
9389 }
9390 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
9391
9392 /**
9393  * ufshcd_set_dma_mask - Set dma mask based on the controller
9394  *                       addressing capability
9395  * @hba: per adapter instance
9396  *
9397  * Returns 0 for success, non-zero for failure
9398  */
9399 static int ufshcd_set_dma_mask(struct ufs_hba *hba)
9400 {
9401         if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
9402                 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
9403                         return 0;
9404         }
9405         return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
9406 }
9407
9408 static struct scsi_transport_template ufshcd_transport_template = {
9409         .eh_strategy_handler = ufshcd_err_handler,
9410 };
9411
9412 /**
9413  * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
9414  * @dev: pointer to device handle
9415  * @hba_handle: driver private handle
9416  * Returns 0 on success, non-zero value on failure
9417  */
9418 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
9419 {
9420         struct Scsi_Host *host;
9421         struct ufs_hba *hba;
9422         int err = 0;
9423
9424         if (!dev) {
9425                 dev_err(dev,
9426                 "Invalid memory reference for dev is NULL\n");
9427                 err = -ENODEV;
9428                 goto out_error;
9429         }
9430
9431         host = scsi_host_alloc(&ufshcd_driver_template,
9432                                 sizeof(struct ufs_hba));
9433         if (!host) {
9434                 dev_err(dev, "scsi_host_alloc failed\n");
9435                 err = -ENOMEM;
9436                 goto out_error;
9437         }
9438         host->transportt = &ufshcd_transport_template;
9439         hba = shost_priv(host);
9440         hba->host = host;
9441         hba->dev = dev;
9442         hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
9443         INIT_LIST_HEAD(&hba->clk_list_head);
9444         spin_lock_init(&hba->outstanding_lock);
9445
9446         *hba_handle = hba;
9447
9448 out_error:
9449         return err;
9450 }
9451 EXPORT_SYMBOL(ufshcd_alloc_host);
9452
9453 /* This function exists because blk_mq_alloc_tag_set() requires this. */
9454 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
9455                                      const struct blk_mq_queue_data *qd)
9456 {
9457         WARN_ON_ONCE(true);
9458         return BLK_STS_NOTSUPP;
9459 }
9460
9461 static const struct blk_mq_ops ufshcd_tmf_ops = {
9462         .queue_rq = ufshcd_queue_tmf,
9463 };
9464
9465 /**
9466  * ufshcd_init - Driver initialization routine
9467  * @hba: per-adapter instance
9468  * @mmio_base: base register address
9469  * @irq: Interrupt line of device
9470  * Returns 0 on success, non-zero value on failure
9471  */
9472 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
9473 {
9474         int err;
9475         struct Scsi_Host *host = hba->host;
9476         struct device *dev = hba->dev;
9477
9478         if (!mmio_base) {
9479                 dev_err(hba->dev,
9480                 "Invalid memory reference for mmio_base is NULL\n");
9481                 err = -ENODEV;
9482                 goto out_error;
9483         }
9484
9485         hba->mmio_base = mmio_base;
9486         hba->irq = irq;
9487         hba->vps = &ufs_hba_vps;
9488
9489         err = ufshcd_hba_init(hba);
9490         if (err)
9491                 goto out_error;
9492
9493         /* Read capabilities registers */
9494         err = ufshcd_hba_capabilities(hba);
9495         if (err)
9496                 goto out_disable;
9497
9498         /* Get UFS version supported by the controller */
9499         hba->ufs_version = ufshcd_get_ufs_version(hba);
9500
9501         /* Get Interrupt bit mask per version */
9502         hba->intr_mask = ufshcd_get_intr_mask(hba);
9503
9504         err = ufshcd_set_dma_mask(hba);
9505         if (err) {
9506                 dev_err(hba->dev, "set dma mask failed\n");
9507                 goto out_disable;
9508         }
9509
9510         /* Allocate memory for host memory space */
9511         err = ufshcd_memory_alloc(hba);
9512         if (err) {
9513                 dev_err(hba->dev, "Memory allocation failed\n");
9514                 goto out_disable;
9515         }
9516
9517         /* Configure LRB */
9518         ufshcd_host_memory_configure(hba);
9519
9520         host->can_queue = hba->nutrs;
9521         host->cmd_per_lun = hba->nutrs;
9522         host->max_id = UFSHCD_MAX_ID;
9523         host->max_lun = UFS_MAX_LUNS;
9524         host->max_channel = UFSHCD_MAX_CHANNEL;
9525         host->unique_id = host->host_no;
9526         host->max_cmd_len = UFS_CDB_SIZE;
9527
9528         hba->max_pwr_info.is_valid = false;
9529
9530         INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
9531
9532         sema_init(&hba->host_sem, 1);
9533
9534         /* Initialize UIC command mutex */
9535         mutex_init(&hba->uic_cmd_mutex);
9536
9537         /* Initialize mutex for device management commands */
9538         mutex_init(&hba->dev_cmd.lock);
9539
9540         /* Initialize mutex for exception event control */
9541         mutex_init(&hba->ee_ctrl_mutex);
9542
9543         init_rwsem(&hba->clk_scaling_lock);
9544
9545         ufshcd_init_clk_gating(hba);
9546
9547         ufshcd_init_clk_scaling(hba);
9548
9549         /*
9550          * In order to avoid any spurious interrupt immediately after
9551          * registering UFS controller interrupt handler, clear any pending UFS
9552          * interrupt status and disable all the UFS interrupts.
9553          */
9554         ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
9555                       REG_INTERRUPT_STATUS);
9556         ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
9557         /*
9558          * Make sure that UFS interrupts are disabled and any pending interrupt
9559          * status is cleared before registering UFS interrupt handler.
9560          */
9561         mb();
9562
9563         /* IRQ registration */
9564         err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
9565         if (err) {
9566                 dev_err(hba->dev, "request irq failed\n");
9567                 goto out_disable;
9568         } else {
9569                 hba->is_irq_enabled = true;
9570         }
9571
9572         err = scsi_add_host(host, hba->dev);
9573         if (err) {
9574                 dev_err(hba->dev, "scsi_add_host failed\n");
9575                 goto out_disable;
9576         }
9577
9578         hba->cmd_queue = blk_mq_init_queue(&hba->host->tag_set);
9579         if (IS_ERR(hba->cmd_queue)) {
9580                 err = PTR_ERR(hba->cmd_queue);
9581                 goto out_remove_scsi_host;
9582         }
9583
9584         hba->tmf_tag_set = (struct blk_mq_tag_set) {
9585                 .nr_hw_queues   = 1,
9586                 .queue_depth    = hba->nutmrs,
9587                 .ops            = &ufshcd_tmf_ops,
9588                 .flags          = BLK_MQ_F_NO_SCHED,
9589         };
9590         err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
9591         if (err < 0)
9592                 goto free_cmd_queue;
9593         hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set);
9594         if (IS_ERR(hba->tmf_queue)) {
9595                 err = PTR_ERR(hba->tmf_queue);
9596                 goto free_tmf_tag_set;
9597         }
9598
9599         /* Reset the attached device */
9600         ufshcd_device_reset(hba);
9601
9602         ufshcd_init_crypto(hba);
9603
9604         /* Host controller enable */
9605         err = ufshcd_hba_enable(hba);
9606         if (err) {
9607                 dev_err(hba->dev, "Host controller enable failed\n");
9608                 ufshcd_print_evt_hist(hba);
9609                 ufshcd_print_host_state(hba);
9610                 goto free_tmf_queue;
9611         }
9612
9613         /*
9614          * Set the default power management level for runtime and system PM.
9615          * Default power saving mode is to keep UFS link in Hibern8 state
9616          * and UFS device in sleep state.
9617          */
9618         hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
9619                                                 UFS_SLEEP_PWR_MODE,
9620                                                 UIC_LINK_HIBERN8_STATE);
9621         hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
9622                                                 UFS_SLEEP_PWR_MODE,
9623                                                 UIC_LINK_HIBERN8_STATE);
9624
9625         INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work,
9626                           ufshcd_rpm_dev_flush_recheck_work);
9627
9628         /* Set the default auto-hiberate idle timer value to 150 ms */
9629         if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
9630                 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
9631                             FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
9632         }
9633
9634         /* Hold auto suspend until async scan completes */
9635         pm_runtime_get_sync(dev);
9636         atomic_set(&hba->scsi_block_reqs_cnt, 0);
9637         /*
9638          * We are assuming that device wasn't put in sleep/power-down
9639          * state exclusively during the boot stage before kernel.
9640          * This assumption helps avoid doing link startup twice during
9641          * ufshcd_probe_hba().
9642          */
9643         ufshcd_set_ufs_dev_active(hba);
9644
9645         async_schedule(ufshcd_async_scan, hba);
9646         ufs_sysfs_add_nodes(hba->dev);
9647
9648         device_enable_async_suspend(dev);
9649         return 0;
9650
9651 free_tmf_queue:
9652         blk_cleanup_queue(hba->tmf_queue);
9653 free_tmf_tag_set:
9654         blk_mq_free_tag_set(&hba->tmf_tag_set);
9655 free_cmd_queue:
9656         blk_cleanup_queue(hba->cmd_queue);
9657 out_remove_scsi_host:
9658         scsi_remove_host(hba->host);
9659 out_disable:
9660         hba->is_irq_enabled = false;
9661         ufshcd_hba_exit(hba);
9662 out_error:
9663         return err;
9664 }
9665 EXPORT_SYMBOL_GPL(ufshcd_init);
9666
9667 void ufshcd_resume_complete(struct device *dev)
9668 {
9669         struct ufs_hba *hba = dev_get_drvdata(dev);
9670
9671         if (hba->complete_put) {
9672                 ufshcd_rpm_put(hba);
9673                 hba->complete_put = false;
9674         }
9675         if (hba->rpmb_complete_put) {
9676                 ufshcd_rpmb_rpm_put(hba);
9677                 hba->rpmb_complete_put = false;
9678         }
9679 }
9680 EXPORT_SYMBOL_GPL(ufshcd_resume_complete);
9681
9682 int ufshcd_suspend_prepare(struct device *dev)
9683 {
9684         struct ufs_hba *hba = dev_get_drvdata(dev);
9685         int ret;
9686
9687         /*
9688          * SCSI assumes that runtime-pm and system-pm for scsi drivers
9689          * are same. And it doesn't wake up the device for system-suspend
9690          * if it's runtime suspended. But ufs doesn't follow that.
9691          * Refer ufshcd_resume_complete()
9692          */
9693         if (hba->sdev_ufs_device) {
9694                 ret = ufshcd_rpm_get_sync(hba);
9695                 if (ret < 0 && ret != -EACCES) {
9696                         ufshcd_rpm_put(hba);
9697                         return ret;
9698                 }
9699                 hba->complete_put = true;
9700         }
9701         if (hba->sdev_rpmb) {
9702                 ufshcd_rpmb_rpm_get_sync(hba);
9703                 hba->rpmb_complete_put = true;
9704         }
9705         return 0;
9706 }
9707 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare);
9708
9709 #ifdef CONFIG_PM_SLEEP
9710 static int ufshcd_wl_poweroff(struct device *dev)
9711 {
9712         struct scsi_device *sdev = to_scsi_device(dev);
9713         struct ufs_hba *hba = shost_priv(sdev->host);
9714
9715         __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
9716         return 0;
9717 }
9718 #endif
9719
9720 static int ufshcd_wl_probe(struct device *dev)
9721 {
9722         struct scsi_device *sdev = to_scsi_device(dev);
9723
9724         if (!is_device_wlun(sdev))
9725                 return -ENODEV;
9726
9727         blk_pm_runtime_init(sdev->request_queue, dev);
9728         pm_runtime_set_autosuspend_delay(dev, 0);
9729         pm_runtime_allow(dev);
9730
9731         return  0;
9732 }
9733
9734 static int ufshcd_wl_remove(struct device *dev)
9735 {
9736         pm_runtime_forbid(dev);
9737         return 0;
9738 }
9739
9740 static const struct dev_pm_ops ufshcd_wl_pm_ops = {
9741 #ifdef CONFIG_PM_SLEEP
9742         .suspend = ufshcd_wl_suspend,
9743         .resume = ufshcd_wl_resume,
9744         .freeze = ufshcd_wl_suspend,
9745         .thaw = ufshcd_wl_resume,
9746         .poweroff = ufshcd_wl_poweroff,
9747         .restore = ufshcd_wl_resume,
9748 #endif
9749         SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL)
9750 };
9751
9752 /*
9753  * ufs_dev_wlun_template - describes ufs device wlun
9754  * ufs-device wlun - used to send pm commands
9755  * All luns are consumers of ufs-device wlun.
9756  *
9757  * Currently, no sd driver is present for wluns.
9758  * Hence the no specific pm operations are performed.
9759  * With ufs design, SSU should be sent to ufs-device wlun.
9760  * Hence register a scsi driver for ufs wluns only.
9761  */
9762 static struct scsi_driver ufs_dev_wlun_template = {
9763         .gendrv = {
9764                 .name = "ufs_device_wlun",
9765                 .owner = THIS_MODULE,
9766                 .probe = ufshcd_wl_probe,
9767                 .remove = ufshcd_wl_remove,
9768                 .pm = &ufshcd_wl_pm_ops,
9769                 .shutdown = ufshcd_wl_shutdown,
9770         },
9771 };
9772
9773 static int ufshcd_rpmb_probe(struct device *dev)
9774 {
9775         return is_rpmb_wlun(to_scsi_device(dev)) ? 0 : -ENODEV;
9776 }
9777
9778 static inline int ufshcd_clear_rpmb_uac(struct ufs_hba *hba)
9779 {
9780         int ret = 0;
9781
9782         if (!hba->wlun_rpmb_clr_ua)
9783                 return 0;
9784         ret = ufshcd_clear_ua_wlun(hba, UFS_UPIU_RPMB_WLUN);
9785         if (!ret)
9786                 hba->wlun_rpmb_clr_ua = 0;
9787         return ret;
9788 }
9789
9790 #ifdef CONFIG_PM
9791 static int ufshcd_rpmb_resume(struct device *dev)
9792 {
9793         struct ufs_hba *hba = wlun_dev_to_hba(dev);
9794
9795         if (hba->sdev_rpmb)
9796                 ufshcd_clear_rpmb_uac(hba);
9797         return 0;
9798 }
9799 #endif
9800
9801 static const struct dev_pm_ops ufs_rpmb_pm_ops = {
9802         SET_RUNTIME_PM_OPS(NULL, ufshcd_rpmb_resume, NULL)
9803         SET_SYSTEM_SLEEP_PM_OPS(NULL, ufshcd_rpmb_resume)
9804 };
9805
9806 /* ufs_rpmb_wlun_template - Describes UFS RPMB WLUN. Used only to send UAC. */
9807 static struct scsi_driver ufs_rpmb_wlun_template = {
9808         .gendrv = {
9809                 .name = "ufs_rpmb_wlun",
9810                 .owner = THIS_MODULE,
9811                 .probe = ufshcd_rpmb_probe,
9812                 .pm = &ufs_rpmb_pm_ops,
9813         },
9814 };
9815
9816 static int __init ufshcd_core_init(void)
9817 {
9818         int ret;
9819
9820         ufs_debugfs_init();
9821
9822         ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv);
9823         if (ret)
9824                 goto debugfs_exit;
9825
9826         ret = scsi_register_driver(&ufs_rpmb_wlun_template.gendrv);
9827         if (ret)
9828                 goto unregister;
9829
9830         return ret;
9831 unregister:
9832         scsi_unregister_driver(&ufs_dev_wlun_template.gendrv);
9833 debugfs_exit:
9834         ufs_debugfs_exit();
9835         return ret;
9836 }
9837
9838 static void __exit ufshcd_core_exit(void)
9839 {
9840         ufs_debugfs_exit();
9841         scsi_unregister_driver(&ufs_rpmb_wlun_template.gendrv);
9842         scsi_unregister_driver(&ufs_dev_wlun_template.gendrv);
9843 }
9844
9845 module_init(ufshcd_core_init);
9846 module_exit(ufshcd_core_exit);
9847
9848 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
9849 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
9850 MODULE_DESCRIPTION("Generic UFS host controller driver Core");
9851 MODULE_LICENSE("GPL");
9852 MODULE_VERSION(UFSHCD_DRIVER_VERSION);