drivers/scsi/ufs/ufshcd.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Universal Flash Storage Host controller driver Core
   4  * Copyright (C) 2011-2013 Samsung India Software Operations
   5  * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
   6  *
   7  * Authors:
   8  *      Santosh Yaraganavi <santosh.sy@samsung.com>
   9  *      Vinayak Holikatti <h.vinayak@samsung.com>
  10  */
  11
  12 #include <linux/async.h>
  13 #include <linux/devfreq.h>
  14 #include <linux/nls.h>
  15 #include <linux/of.h>
  16 #include <linux/bitfield.h>
  17 #include <linux/blk-pm.h>
  18 #include <linux/blkdev.h>
  19 #include <scsi/scsi_driver.h>
  20 #include "ufshcd.h"
  21 #include "ufs_quirks.h"
  22 #include "unipro.h"
  23 #include "ufs-sysfs.h"
  24 #include "ufs-debugfs.h"
  25 #include "ufs_bsg.h"
  26 #include "ufshcd-crypto.h"
  27 #include <asm/unaligned.h>
  28
  29 #define CREATE_TRACE_POINTS
  30 #include <trace/events/ufs.h>
  31
  32 #define UFSHCD_ENABLE_INTRS     (UTP_TRANSFER_REQ_COMPL |\
  33                                  UTP_TASK_REQ_COMPL |\
  34                                  UFSHCD_ERROR_MASK)
  35 /* UIC command timeout, unit: ms */
  36 #define UIC_CMD_TIMEOUT 500
  37
  38 /* NOP OUT retries waiting for NOP IN response */
  39 #define NOP_OUT_RETRIES    10
  40 /* Timeout after 50 msecs if NOP OUT hangs without response */
  41 #define NOP_OUT_TIMEOUT    50 /* msecs */
  42
  43 /* Query request retries */
  44 #define QUERY_REQ_RETRIES 3
  45 /* Query request timeout */
  46 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
  47
  48 /* Task management command timeout */
  49 #define TM_CMD_TIMEOUT  100 /* msecs */
  50
  51 /* maximum number of retries for a general UIC command  */
  52 #define UFS_UIC_COMMAND_RETRIES 3
  53
  54 /* maximum number of link-startup retries */
  55 #define DME_LINKSTARTUP_RETRIES 3
  56
  57 /* Maximum retries for Hibern8 enter */
  58 #define UIC_HIBERN8_ENTER_RETRIES 3
  59
  60 /* maximum number of reset retries before giving up */
  61 #define MAX_HOST_RESET_RETRIES 5
  62
  63 /* Expose the flag value from utp_upiu_query.value */
  64 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
  65
  66 /* Interrupt aggregation default timeout, unit: 40us */
  67 #define INT_AGGR_DEF_TO 0x02
  68
  69 /* default delay of autosuspend: 2000 ms */
  70 #define RPM_AUTOSUSPEND_DELAY_MS 2000
  71
  72 /* Default delay of RPM device flush delayed work */
  73 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000
  74
  75 /* Default value of wait time before gating device ref clock */
  76 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */
  77
  78 /* Polling time to wait for fDeviceInit */
  79 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */
  80
  81 #define wlun_dev_to_hba(dv) shost_priv(to_scsi_device(dv)->host)
  82
  83 #define ufshcd_toggle_vreg(_dev, _vreg, _on)                            \
  84         ({                                                              \
  85                 int _ret;                                               \
  86                 if (_on)                                                \
  87                         _ret = ufshcd_enable_vreg(_dev, _vreg);         \
  88                 else                                                    \
  89                         _ret = ufshcd_disable_vreg(_dev, _vreg);        \
  90                 _ret;                                                   \
  91         })
  92
  93 #define ufshcd_hex_dump(prefix_str, buf, len) do {                       \
  94         size_t __len = (len);                                            \
  95         print_hex_dump(KERN_ERR, prefix_str,                             \
  96                        __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
  97                        16, 4, buf, __len, false);                        \
  98 } while (0)
  99
 100 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
 101                      const char *prefix)
 102 {
 103         u32 *regs;
 104         size_t pos;
 105
 106         if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
 107                 return -EINVAL;
 108
 109         regs = kzalloc(len, GFP_ATOMIC);
 110         if (!regs)
 111                 return -ENOMEM;
 112
 113         for (pos = 0; pos < len; pos += 4)
 114                 regs[pos / 4] = ufshcd_readl(hba, offset + pos);
 115
 116         ufshcd_hex_dump(prefix, regs, len);
 117         kfree(regs);
 118
 119         return 0;
 120 }
 121 EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
 122
 123 enum {
 124         UFSHCD_MAX_CHANNEL      = 0,
 125         UFSHCD_MAX_ID           = 1,
 126         UFSHCD_CMD_PER_LUN      = 32,
 127         UFSHCD_CAN_QUEUE        = 32,
 128 };
 129
 130 /* UFSHCD states */
 131 enum {
 132         UFSHCD_STATE_RESET,
 133         UFSHCD_STATE_ERROR,
 134         UFSHCD_STATE_OPERATIONAL,
 135         UFSHCD_STATE_EH_SCHEDULED_FATAL,
 136         UFSHCD_STATE_EH_SCHEDULED_NON_FATAL,
 137 };
 138
 139 /* UFSHCD error handling flags */
 140 enum {
 141         UFSHCD_EH_IN_PROGRESS = (1 << 0),
 142 };
 143
 144 /* UFSHCD UIC layer error flags */
 145 enum {
 146         UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
 147         UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
 148         UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
 149         UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
 150         UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
 151         UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
 152         UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */
 153 };
 154
 155 #define ufshcd_set_eh_in_progress(h) \
 156         ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
 157 #define ufshcd_eh_in_progress(h) \
 158         ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
 159 #define ufshcd_clear_eh_in_progress(h) \
 160         ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
 161
 162 struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
 163         [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
 164         [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
 165         [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
 166         [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
 167         [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
 168         [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
 169         /*
 170          * For DeepSleep, the link is first put in hibern8 and then off.
 171          * Leaving the link in hibern8 is not supported.
 172          */
 173         [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE},
 174 };
 175
 176 static inline enum ufs_dev_pwr_mode
 177 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
 178 {
 179         return ufs_pm_lvl_states[lvl].dev_state;
 180 }
 181
 182 static inline enum uic_link_state
 183 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
 184 {
 185         return ufs_pm_lvl_states[lvl].link_state;
 186 }
 187
 188 static inline enum ufs_pm_level
 189 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
 190                                         enum uic_link_state link_state)
 191 {
 192         enum ufs_pm_level lvl;
 193
 194         for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
 195                 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
 196                         (ufs_pm_lvl_states[lvl].link_state == link_state))
 197                         return lvl;
 198         }
 199
 200         /* if no match found, return the level 0 */
 201         return UFS_PM_LVL_0;
 202 }
 203
 204 static struct ufs_dev_fix ufs_fixups[] = {
 205         /* UFS cards deviations table */
 206         UFS_FIX(UFS_VENDOR_MICRON, UFS_ANY_MODEL,
 207                 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
 208         UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
 209                 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
 210                 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE |
 211                 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
 212         UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
 213                 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
 214         UFS_FIX(UFS_VENDOR_SKHYNIX, "hB8aL1" /*H28U62301AMR*/,
 215                 UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME),
 216         UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
 217                 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
 218         UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
 219                 UFS_DEVICE_QUIRK_PA_TACTIVATE),
 220         UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
 221                 UFS_DEVICE_QUIRK_PA_TACTIVATE),
 222         END_FIX
 223 };
 224
 225 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
 226 static void ufshcd_async_scan(void *data, async_cookie_t cookie);
 227 static int ufshcd_reset_and_restore(struct ufs_hba *hba);
 228 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
 229 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
 230 static void ufshcd_hba_exit(struct ufs_hba *hba);
 231 static int ufshcd_clear_ua_wluns(struct ufs_hba *hba);
 232 static int ufshcd_probe_hba(struct ufs_hba *hba, bool async);
 233 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
 234 static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
 235 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
 236 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
 237 static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
 238 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
 239 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
 240 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
 241 static irqreturn_t ufshcd_intr(int irq, void *__hba);
 242 static int ufshcd_change_power_mode(struct ufs_hba *hba,
 243                              struct ufs_pa_layer_attr *pwr_mode);
 244 static void ufshcd_schedule_eh_work(struct ufs_hba *hba);
 245 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on);
 246 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on);
 247 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
 248                                          struct ufs_vreg *vreg);
 249 static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag);
 250 static void ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set);
 251 static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable);
 252 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba);
 253 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba);
 254
 255 static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
 256 {
 257         return tag >= 0 && tag < hba->nutrs;
 258 }
 259
 260 static inline void ufshcd_enable_irq(struct ufs_hba *hba)
 261 {
 262         if (!hba->is_irq_enabled) {
 263                 enable_irq(hba->irq);
 264                 hba->is_irq_enabled = true;
 265         }
 266 }
 267
 268 static inline void ufshcd_disable_irq(struct ufs_hba *hba)
 269 {
 270         if (hba->is_irq_enabled) {
 271                 disable_irq(hba->irq);
 272                 hba->is_irq_enabled = false;
 273         }
 274 }
 275
 276 static inline void ufshcd_wb_config(struct ufs_hba *hba)
 277 {
 278         if (!ufshcd_is_wb_allowed(hba))
 279                 return;
 280
 281         ufshcd_wb_toggle(hba, true);
 282
 283         ufshcd_wb_toggle_flush_during_h8(hba, true);
 284         if (!(hba->quirks & UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL))
 285                 ufshcd_wb_toggle_flush(hba, true);
 286 }
 287
 288 static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
 289 {
 290         if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
 291                 scsi_unblock_requests(hba->host);
 292 }
 293
 294 static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
 295 {
 296         if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
 297                 scsi_block_requests(hba->host);
 298 }
 299
 300 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
 301                                       enum ufs_trace_str_t str_t)
 302 {
 303         struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
 304
 305         if (!trace_ufshcd_upiu_enabled())
 306                 return;
 307
 308         trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq->header, &rq->sc.cdb,
 309                           UFS_TSF_CDB);
 310 }
 311
 312 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba,
 313                                         enum ufs_trace_str_t str_t,
 314                                         struct utp_upiu_req *rq_rsp)
 315 {
 316         if (!trace_ufshcd_upiu_enabled())
 317                 return;
 318
 319         trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header,
 320                           &rq_rsp->qr, UFS_TSF_OSF);
 321 }
 322
 323 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
 324                                      enum ufs_trace_str_t str_t)
 325 {
 326         int off = (int)tag - hba->nutrs;
 327         struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[off];
 328
 329         if (!trace_ufshcd_upiu_enabled())
 330                 return;
 331
 332         if (str_t == UFS_TM_SEND)
 333                 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
 334                                   &descp->upiu_req.req_header,
 335                                   &descp->upiu_req.input_param1,
 336                                   UFS_TSF_TM_INPUT);
 337         else
 338                 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
 339                                   &descp->upiu_rsp.rsp_header,
 340                                   &descp->upiu_rsp.output_param1,
 341                                   UFS_TSF_TM_OUTPUT);
 342 }
 343
 344 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba,
 345                                          struct uic_command *ucmd,
 346                                          enum ufs_trace_str_t str_t)
 347 {
 348         u32 cmd;
 349
 350         if (!trace_ufshcd_uic_command_enabled())
 351                 return;
 352
 353         if (str_t == UFS_CMD_SEND)
 354                 cmd = ucmd->command;
 355         else
 356                 cmd = ufshcd_readl(hba, REG_UIC_COMMAND);
 357
 358         trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd,
 359                                  ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1),
 360                                  ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2),
 361                                  ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3));
 362 }
 363
 364 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag,
 365                                      enum ufs_trace_str_t str_t)
 366 {
 367         sector_t lba = -1;
 368         u8 opcode = 0, group_id = 0;
 369         u32 intr, doorbell;
 370         struct ufshcd_lrb *lrbp = &hba->lrb[tag];
 371         struct scsi_cmnd *cmd = lrbp->cmd;
 372         int transfer_len = -1;
 373
 374         if (!trace_ufshcd_command_enabled()) {
 375                 /* trace UPIU W/O tracing command */
 376                 if (cmd)
 377                         ufshcd_add_cmd_upiu_trace(hba, tag, str_t);
 378                 return;
 379         }
 380
 381         if (cmd) { /* data phase exists */
 382                 /* trace UPIU also */
 383                 ufshcd_add_cmd_upiu_trace(hba, tag, str_t);
 384                 opcode = cmd->cmnd[0];
 385                 if ((opcode == READ_10) || (opcode == WRITE_10)) {
 386                         /*
 387                          * Currently we only fully trace read(10) and write(10)
 388                          * commands
 389                          */
 390                         if (cmd->request && cmd->request->bio)
 391                                 lba = cmd->request->bio->bi_iter.bi_sector;
 392                         transfer_len = be32_to_cpu(
 393                                 lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
 394                         if (opcode == WRITE_10)
 395                                 group_id = lrbp->cmd->cmnd[6];
 396                 } else if (opcode == UNMAP) {
 397                         if (cmd->request) {
 398                                 lba = scsi_get_lba(cmd);
 399                                 transfer_len = blk_rq_bytes(cmd->request);
 400                         }
 401                 }
 402         }
 403
 404         intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
 405         doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
 406         trace_ufshcd_command(dev_name(hba->dev), str_t, tag,
 407                         doorbell, transfer_len, intr, lba, opcode, group_id);
 408 }
 409
 410 static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
 411 {
 412         struct ufs_clk_info *clki;
 413         struct list_head *head = &hba->clk_list_head;
 414
 415         if (list_empty(head))
 416                 return;
 417
 418         list_for_each_entry(clki, head, list) {
 419                 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
 420                                 clki->max_freq)
 421                         dev_err(hba->dev, "clk: %s, rate: %u\n",
 422                                         clki->name, clki->curr_freq);
 423         }
 424 }
 425
 426 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id,
 427                              char *err_name)
 428 {
 429         int i;
 430         bool found = false;
 431         struct ufs_event_hist *e;
 432
 433         if (id >= UFS_EVT_CNT)
 434                 return;
 435
 436         e = &hba->ufs_stats.event[id];
 437
 438         for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) {
 439                 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH;
 440
 441                 if (e->tstamp[p] == 0)
 442                         continue;
 443                 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
 444                         e->val[p], ktime_to_us(e->tstamp[p]));
 445                 found = true;
 446         }
 447
 448         if (!found)
 449                 dev_err(hba->dev, "No record of %s\n", err_name);
 450         else
 451                 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt);
 452 }
 453
 454 static void ufshcd_print_evt_hist(struct ufs_hba *hba)
 455 {
 456         ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
 457
 458         ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err");
 459         ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err");
 460         ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err");
 461         ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err");
 462         ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err");
 463         ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR,
 464                          "auto_hibern8_err");
 465         ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err");
 466         ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL,
 467                          "link_startup_fail");
 468         ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail");
 469         ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR,
 470                          "suspend_fail");
 471         ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset");
 472         ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset");
 473         ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort");
 474
 475         ufshcd_vops_dbg_register_dump(hba);
 476 }
 477
 478 static
 479 void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
 480 {
 481         struct ufshcd_lrb *lrbp;
 482         int prdt_length;
 483         int tag;
 484
 485         for_each_set_bit(tag, &bitmap, hba->nutrs) {
 486                 lrbp = &hba->lrb[tag];
 487
 488                 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
 489                                 tag, ktime_to_us(lrbp->issue_time_stamp));
 490                 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
 491                                 tag, ktime_to_us(lrbp->compl_time_stamp));
 492                 dev_err(hba->dev,
 493                         "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
 494                         tag, (u64)lrbp->utrd_dma_addr);
 495
 496                 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
 497                                 sizeof(struct utp_transfer_req_desc));
 498                 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
 499                         (u64)lrbp->ucd_req_dma_addr);
 500                 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
 501                                 sizeof(struct utp_upiu_req));
 502                 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
 503                         (u64)lrbp->ucd_rsp_dma_addr);
 504                 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
 505                                 sizeof(struct utp_upiu_rsp));
 506
 507                 prdt_length = le16_to_cpu(
 508                         lrbp->utr_descriptor_ptr->prd_table_length);
 509                 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
 510                         prdt_length /= sizeof(struct ufshcd_sg_entry);
 511
 512                 dev_err(hba->dev,
 513                         "UPIU[%d] - PRDT - %d entries  phys@0x%llx\n",
 514                         tag, prdt_length,
 515                         (u64)lrbp->ucd_prdt_dma_addr);
 516
 517                 if (pr_prdt)
 518                         ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
 519                                 sizeof(struct ufshcd_sg_entry) * prdt_length);
 520         }
 521 }
 522
 523 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
 524 {
 525         int tag;
 526
 527         for_each_set_bit(tag, &bitmap, hba->nutmrs) {
 528                 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
 529
 530                 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
 531                 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
 532         }
 533 }
 534
 535 static void ufshcd_print_host_state(struct ufs_hba *hba)
 536 {
 537         struct scsi_device *sdev_ufs = hba->sdev_ufs_device;
 538
 539         dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
 540         dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n",
 541                 hba->outstanding_reqs, hba->outstanding_tasks);
 542         dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
 543                 hba->saved_err, hba->saved_uic_err);
 544         dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
 545                 hba->curr_dev_pwr_mode, hba->uic_link_state);
 546         dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
 547                 hba->pm_op_in_progress, hba->is_sys_suspended);
 548         dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
 549                 hba->auto_bkops_enabled, hba->host->host_self_blocked);
 550         dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
 551         dev_err(hba->dev,
 552                 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n",
 553                 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
 554                 hba->ufs_stats.hibern8_exit_cnt);
 555         dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n",
 556                 ktime_to_us(hba->ufs_stats.last_intr_ts),
 557                 hba->ufs_stats.last_intr_status);
 558         dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
 559                 hba->eh_flags, hba->req_abort_count);
 560         dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n",
 561                 hba->ufs_version, hba->capabilities, hba->caps);
 562         dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
 563                 hba->dev_quirks);
 564         if (sdev_ufs)
 565                 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n",
 566                         sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev);
 567
 568         ufshcd_print_clk_freqs(hba);
 569 }
 570
 571 /**
 572  * ufshcd_print_pwr_info - print power params as saved in hba
 573  * power info
 574  * @hba: per-adapter instance
 575  */
 576 static void ufshcd_print_pwr_info(struct ufs_hba *hba)
 577 {
 578         static const char * const names[] = {
 579                 "INVALID MODE",
 580                 "FAST MODE",
 581                 "SLOW_MODE",
 582                 "INVALID MODE",
 583                 "FASTAUTO_MODE",
 584                 "SLOWAUTO_MODE",
 585                 "INVALID MODE",
 586         };
 587
 588         dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
 589                  __func__,
 590                  hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
 591                  hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
 592                  names[hba->pwr_info.pwr_rx],
 593                  names[hba->pwr_info.pwr_tx],
 594                  hba->pwr_info.hs_rate);
 595 }
 596
 597 static void ufshcd_device_reset(struct ufs_hba *hba)
 598 {
 599         int err;
 600
 601         err = ufshcd_vops_device_reset(hba);
 602
 603         if (!err) {
 604                 ufshcd_set_ufs_dev_active(hba);
 605                 if (ufshcd_is_wb_allowed(hba)) {
 606                         hba->dev_info.wb_enabled = false;
 607                         hba->dev_info.wb_buf_flush_enabled = false;
 608                 }
 609         }
 610         if (err != -EOPNOTSUPP)
 611                 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err);
 612 }
 613
 614 void ufshcd_delay_us(unsigned long us, unsigned long tolerance)
 615 {
 616         if (!us)
 617                 return;
 618
 619         if (us < 10)
 620                 udelay(us);
 621         else
 622                 usleep_range(us, us + tolerance);
 623 }
 624 EXPORT_SYMBOL_GPL(ufshcd_delay_us);
 625
 626 /**
 627  * ufshcd_wait_for_register - wait for register value to change
 628  * @hba: per-adapter interface
 629  * @reg: mmio register offset
 630  * @mask: mask to apply to the read register value
 631  * @val: value to wait for
 632  * @interval_us: polling interval in microseconds
 633  * @timeout_ms: timeout in milliseconds
 634  *
 635  * Return:
 636  * -ETIMEDOUT on error, zero on success.
 637  */
 638 int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
 639                                 u32 val, unsigned long interval_us,
 640                                 unsigned long timeout_ms)
 641 {
 642         int err = 0;
 643         unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
 644
 645         /* ignore bits that we don't intend to wait on */
 646         val = val & mask;
 647
 648         while ((ufshcd_readl(hba, reg) & mask) != val) {
 649                 usleep_range(interval_us, interval_us + 50);
 650                 if (time_after(jiffies, timeout)) {
 651                         if ((ufshcd_readl(hba, reg) & mask) != val)
 652                                 err = -ETIMEDOUT;
 653                         break;
 654                 }
 655         }
 656
 657         return err;
 658 }
 659
 660 /**
 661  * ufshcd_get_intr_mask - Get the interrupt bit mask
 662  * @hba: Pointer to adapter instance
 663  *
 664  * Returns interrupt bit mask per version
 665  */
 666 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
 667 {
 668         if (hba->ufs_version == ufshci_version(1, 0))
 669                 return INTERRUPT_MASK_ALL_VER_10;
 670         if (hba->ufs_version <= ufshci_version(2, 0))
 671                 return INTERRUPT_MASK_ALL_VER_11;
 672
 673         return INTERRUPT_MASK_ALL_VER_21;
 674 }
 675
 676 /**
 677  * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
 678  * @hba: Pointer to adapter instance
 679  *
 680  * Returns UFSHCI version supported by the controller
 681  */
 682 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
 683 {
 684         u32 ufshci_ver;
 685
 686         if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
 687                 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba);
 688         else
 689                 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION);
 690
 691         /*
 692          * UFSHCI v1.x uses a different version scheme, in order
 693          * to allow the use of comparisons with the ufshci_version
 694          * function, we convert it to the same scheme as ufs 2.0+.
 695          */
 696         if (ufshci_ver & 0x00010000)
 697                 return ufshci_version(1, ufshci_ver & 0x00000100);
 698
 699         return ufshci_ver;
 700 }
 701
 702 /**
 703  * ufshcd_is_device_present - Check if any device connected to
 704  *                            the host controller
 705  * @hba: pointer to adapter instance
 706  *
 707  * Returns true if device present, false if no device detected
 708  */
 709 static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
 710 {
 711         return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
 712                                                 DEVICE_PRESENT) ? true : false;
 713 }
 714
 715 /**
 716  * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
 717  * @lrbp: pointer to local command reference block
 718  *
 719  * This function is used to get the OCS field from UTRD
 720  * Returns the OCS field in the UTRD
 721  */
 722 static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
 723 {
 724         return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
 725 }
 726
 727 /**
 728  * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
 729  * @hba: per adapter instance
 730  * @pos: position of the bit to be cleared
 731  */
 732 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
 733 {
 734         if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
 735                 ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
 736         else
 737                 ufshcd_writel(hba, ~(1 << pos),
 738                                 REG_UTP_TRANSFER_REQ_LIST_CLEAR);
 739 }
 740
 741 /**
 742  * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
 743  * @hba: per adapter instance
 744  * @pos: position of the bit to be cleared
 745  */
 746 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
 747 {
 748         if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
 749                 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
 750         else
 751                 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
 752 }
 753
 754 /**
 755  * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
 756  * @hba: per adapter instance
 757  * @tag: position of the bit to be cleared
 758  */
 759 static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
 760 {
 761         __clear_bit(tag, &hba->outstanding_reqs);
 762 }
 763
 764 /**
 765  * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
 766  * @reg: Register value of host controller status
 767  *
 768  * Returns integer, 0 on Success and positive value if failed
 769  */
 770 static inline int ufshcd_get_lists_status(u32 reg)
 771 {
 772         return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
 773 }
 774
 775 /**
 776  * ufshcd_get_uic_cmd_result - Get the UIC command result
 777  * @hba: Pointer to adapter instance
 778  *
 779  * This function gets the result of UIC command completion
 780  * Returns 0 on success, non zero value on error
 781  */
 782 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
 783 {
 784         return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
 785                MASK_UIC_COMMAND_RESULT;
 786 }
 787
 788 /**
 789  * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
 790  * @hba: Pointer to adapter instance
 791  *
 792  * This function gets UIC command argument3
 793  * Returns 0 on success, non zero value on error
 794  */
 795 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
 796 {
 797         return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
 798 }
 799
 800 /**
 801  * ufshcd_get_req_rsp - returns the TR response transaction type
 802  * @ucd_rsp_ptr: pointer to response UPIU
 803  */
 804 static inline int
 805 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
 806 {
 807         return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
 808 }
 809
 810 /**
 811  * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
 812  * @ucd_rsp_ptr: pointer to response UPIU
 813  *
 814  * This function gets the response status and scsi_status from response UPIU
 815  * Returns the response result code.
 816  */
 817 static inline int
 818 ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
 819 {
 820         return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
 821 }
 822
 823 /*
 824  * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
 825  *                              from response UPIU
 826  * @ucd_rsp_ptr: pointer to response UPIU
 827  *
 828  * Return the data segment length.
 829  */
 830 static inline unsigned int
 831 ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
 832 {
 833         return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
 834                 MASK_RSP_UPIU_DATA_SEG_LEN;
 835 }
 836
 837 /**
 838  * ufshcd_is_exception_event - Check if the device raised an exception event
 839  * @ucd_rsp_ptr: pointer to response UPIU
 840  *
 841  * The function checks if the device raised an exception event indicated in
 842  * the Device Information field of response UPIU.
 843  *
 844  * Returns true if exception is raised, false otherwise.
 845  */
 846 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
 847 {
 848         return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
 849                         MASK_RSP_EXCEPTION_EVENT ? true : false;
 850 }
 851
 852 /**
 853  * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
 854  * @hba: per adapter instance
 855  */
 856 static inline void
 857 ufshcd_reset_intr_aggr(struct ufs_hba *hba)
 858 {
 859         ufshcd_writel(hba, INT_AGGR_ENABLE |
 860                       INT_AGGR_COUNTER_AND_TIMER_RESET,
 861                       REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
 862 }
 863
 864 /**
 865  * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
 866  * @hba: per adapter instance
 867  * @cnt: Interrupt aggregation counter threshold
 868  * @tmout: Interrupt aggregation timeout value
 869  */
 870 static inline void
 871 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
 872 {
 873         ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
 874                       INT_AGGR_COUNTER_THLD_VAL(cnt) |
 875                       INT_AGGR_TIMEOUT_VAL(tmout),
 876                       REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
 877 }
 878
 879 /**
 880  * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
 881  * @hba: per adapter instance
 882  */
 883 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
 884 {
 885         ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
 886 }
 887
 888 /**
 889  * ufshcd_enable_run_stop_reg - Enable run-stop registers,
 890  *                      When run-stop registers are set to 1, it indicates the
 891  *                      host controller that it can process the requests
 892  * @hba: per adapter instance
 893  */
 894 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
 895 {
 896         ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
 897                       REG_UTP_TASK_REQ_LIST_RUN_STOP);
 898         ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
 899                       REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
 900 }
 901
 902 /**
 903  * ufshcd_hba_start - Start controller initialization sequence
 904  * @hba: per adapter instance
 905  */
 906 static inline void ufshcd_hba_start(struct ufs_hba *hba)
 907 {
 908         u32 val = CONTROLLER_ENABLE;
 909
 910         if (ufshcd_crypto_enable(hba))
 911                 val |= CRYPTO_GENERAL_ENABLE;
 912
 913         ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
 914 }
 915
 916 /**
 917  * ufshcd_is_hba_active - Get controller state
 918  * @hba: per adapter instance
 919  *
 920  * Returns false if controller is active, true otherwise
 921  */
 922 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
 923 {
 924         return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
 925                 ? false : true;
 926 }
 927
 928 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
 929 {
 930         /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
 931         if (hba->ufs_version <= ufshci_version(1, 1))
 932                 return UFS_UNIPRO_VER_1_41;
 933         else
 934                 return UFS_UNIPRO_VER_1_6;
 935 }
 936 EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
 937
 938 static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
 939 {
 940         /*
 941          * If both host and device support UniPro ver1.6 or later, PA layer
 942          * parameters tuning happens during link startup itself.
 943          *
 944          * We can manually tune PA layer parameters if either host or device
 945          * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
 946          * logic simple, we will only do manual tuning if local unipro version
 947          * doesn't support ver1.6 or later.
 948          */
 949         if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
 950                 return true;
 951         else
 952                 return false;
 953 }
 954
 955 /**
 956  * ufshcd_set_clk_freq - set UFS controller clock frequencies
 957  * @hba: per adapter instance
 958  * @scale_up: If True, set max possible frequency othewise set low frequency
 959  *
 960  * Returns 0 if successful
 961  * Returns < 0 for any other errors
 962  */
 963 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
 964 {
 965         int ret = 0;
 966         struct ufs_clk_info *clki;
 967         struct list_head *head = &hba->clk_list_head;
 968
 969         if (list_empty(head))
 970                 goto out;
 971
 972         list_for_each_entry(clki, head, list) {
 973                 if (!IS_ERR_OR_NULL(clki->clk)) {
 974                         if (scale_up && clki->max_freq) {
 975                                 if (clki->curr_freq == clki->max_freq)
 976                                         continue;
 977
 978                                 ret = clk_set_rate(clki->clk, clki->max_freq);
 979                                 if (ret) {
 980                                         dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
 981                                                 __func__, clki->name,
 982                                                 clki->max_freq, ret);
 983                                         break;
 984                                 }
 985                                 trace_ufshcd_clk_scaling(dev_name(hba->dev),
 986                                                 "scaled up", clki->name,
 987                                                 clki->curr_freq,
 988                                                 clki->max_freq);
 989
 990                                 clki->curr_freq = clki->max_freq;
 991
 992                         } else if (!scale_up && clki->min_freq) {
 993                                 if (clki->curr_freq == clki->min_freq)
 994                                         continue;
 995
 996                                 ret = clk_set_rate(clki->clk, clki->min_freq);
 997                                 if (ret) {
 998                                         dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
 999                                                 __func__, clki->name,
1000                                                 clki->min_freq, ret);
1001                                         break;
1002                                 }
1003                                 trace_ufshcd_clk_scaling(dev_name(hba->dev),
1004                                                 "scaled down", clki->name,
1005                                                 clki->curr_freq,
1006                                                 clki->min_freq);
1007                                 clki->curr_freq = clki->min_freq;
1008                         }
1009                 }
1010                 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
1011                                 clki->name, clk_get_rate(clki->clk));
1012         }
1013
1014 out:
1015         return ret;
1016 }
1017
1018 /**
1019  * ufshcd_scale_clks - scale up or scale down UFS controller clocks
1020  * @hba: per adapter instance
1021  * @scale_up: True if scaling up and false if scaling down
1022  *
1023  * Returns 0 if successful
1024  * Returns < 0 for any other errors
1025  */
1026 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
1027 {
1028         int ret = 0;
1029         ktime_t start = ktime_get();
1030
1031         ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
1032         if (ret)
1033                 goto out;
1034
1035         ret = ufshcd_set_clk_freq(hba, scale_up);
1036         if (ret)
1037                 goto out;
1038
1039         ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1040         if (ret)
1041                 ufshcd_set_clk_freq(hba, !scale_up);
1042
1043 out:
1044         trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1045                         (scale_up ? "up" : "down"),
1046                         ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1047         return ret;
1048 }
1049
1050 /**
1051  * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
1052  * @hba: per adapter instance
1053  * @scale_up: True if scaling up and false if scaling down
1054  *
1055  * Returns true if scaling is required, false otherwise.
1056  */
1057 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
1058                                                bool scale_up)
1059 {
1060         struct ufs_clk_info *clki;
1061         struct list_head *head = &hba->clk_list_head;
1062
1063         if (list_empty(head))
1064                 return false;
1065
1066         list_for_each_entry(clki, head, list) {
1067                 if (!IS_ERR_OR_NULL(clki->clk)) {
1068                         if (scale_up && clki->max_freq) {
1069                                 if (clki->curr_freq == clki->max_freq)
1070                                         continue;
1071                                 return true;
1072                         } else if (!scale_up && clki->min_freq) {
1073                                 if (clki->curr_freq == clki->min_freq)
1074                                         continue;
1075                                 return true;
1076                         }
1077                 }
1078         }
1079
1080         return false;
1081 }
1082
1083 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1084                                         u64 wait_timeout_us)
1085 {
1086         unsigned long flags;
1087         int ret = 0;
1088         u32 tm_doorbell;
1089         u32 tr_doorbell;
1090         bool timeout = false, do_last_check = false;
1091         ktime_t start;
1092
1093         ufshcd_hold(hba, false);
1094         spin_lock_irqsave(hba->host->host_lock, flags);
1095         /*
1096          * Wait for all the outstanding tasks/transfer requests.
1097          * Verify by checking the doorbell registers are clear.
1098          */
1099         start = ktime_get();
1100         do {
1101                 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1102                         ret = -EBUSY;
1103                         goto out;
1104                 }
1105
1106                 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1107                 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1108                 if (!tm_doorbell && !tr_doorbell) {
1109                         timeout = false;
1110                         break;
1111                 } else if (do_last_check) {
1112                         break;
1113                 }
1114
1115                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1116                 schedule();
1117                 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1118                     wait_timeout_us) {
1119                         timeout = true;
1120                         /*
1121                          * We might have scheduled out for long time so make
1122                          * sure to check if doorbells are cleared by this time
1123                          * or not.
1124                          */
1125                         do_last_check = true;
1126                 }
1127                 spin_lock_irqsave(hba->host->host_lock, flags);
1128         } while (tm_doorbell || tr_doorbell);
1129
1130         if (timeout) {
1131                 dev_err(hba->dev,
1132                         "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1133                         __func__, tm_doorbell, tr_doorbell);
1134                 ret = -EBUSY;
1135         }
1136 out:
1137         spin_unlock_irqrestore(hba->host->host_lock, flags);
1138         ufshcd_release(hba);
1139         return ret;
1140 }
1141
1142 /**
1143  * ufshcd_scale_gear - scale up/down UFS gear
1144  * @hba: per adapter instance
1145  * @scale_up: True for scaling up gear and false for scaling down
1146  *
1147  * Returns 0 for success,
1148  * Returns -EBUSY if scaling can't happen at this time
1149  * Returns non-zero for any other errors
1150  */
1151 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1152 {
1153         int ret = 0;
1154         struct ufs_pa_layer_attr new_pwr_info;
1155
1156         if (scale_up) {
1157                 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1158                        sizeof(struct ufs_pa_layer_attr));
1159         } else {
1160                 memcpy(&new_pwr_info, &hba->pwr_info,
1161                        sizeof(struct ufs_pa_layer_attr));
1162
1163                 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear ||
1164                     hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) {
1165                         /* save the current power mode */
1166                         memcpy(&hba->clk_scaling.saved_pwr_info.info,
1167                                 &hba->pwr_info,
1168                                 sizeof(struct ufs_pa_layer_attr));
1169
1170                         /* scale down gear */
1171                         new_pwr_info.gear_tx = hba->clk_scaling.min_gear;
1172                         new_pwr_info.gear_rx = hba->clk_scaling.min_gear;
1173                 }
1174         }
1175
1176         /* check if the power mode needs to be changed or not? */
1177         ret = ufshcd_config_pwr_mode(hba, &new_pwr_info);
1178         if (ret)
1179                 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1180                         __func__, ret,
1181                         hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1182                         new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1183
1184         return ret;
1185 }
1186
1187 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1188 {
1189         #define DOORBELL_CLR_TOUT_US            (1000 * 1000) /* 1 sec */
1190         int ret = 0;
1191         /*
1192          * make sure that there are no outstanding requests when
1193          * clock scaling is in progress
1194          */
1195         ufshcd_scsi_block_requests(hba);
1196         down_write(&hba->clk_scaling_lock);
1197
1198         if (!hba->clk_scaling.is_allowed ||
1199             ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1200                 ret = -EBUSY;
1201                 up_write(&hba->clk_scaling_lock);
1202                 ufshcd_scsi_unblock_requests(hba);
1203                 goto out;
1204         }
1205
1206         /* let's not get into low power until clock scaling is completed */
1207         ufshcd_hold(hba, false);
1208
1209 out:
1210         return ret;
1211 }
1212
1213 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, bool writelock)
1214 {
1215         if (writelock)
1216                 up_write(&hba->clk_scaling_lock);
1217         else
1218                 up_read(&hba->clk_scaling_lock);
1219         ufshcd_scsi_unblock_requests(hba);
1220         ufshcd_release(hba);
1221 }
1222
1223 /**
1224  * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1225  * @hba: per adapter instance
1226  * @scale_up: True for scaling up and false for scalin down
1227  *
1228  * Returns 0 for success,
1229  * Returns -EBUSY if scaling can't happen at this time
1230  * Returns non-zero for any other errors
1231  */
1232 static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1233 {
1234         int ret = 0;
1235         bool is_writelock = true;
1236
1237         ret = ufshcd_clock_scaling_prepare(hba);
1238         if (ret)
1239                 return ret;
1240
1241         /* scale down the gear before scaling down clocks */
1242         if (!scale_up) {
1243                 ret = ufshcd_scale_gear(hba, false);
1244                 if (ret)
1245                         goto out_unprepare;
1246         }
1247
1248         ret = ufshcd_scale_clks(hba, scale_up);
1249         if (ret) {
1250                 if (!scale_up)
1251                         ufshcd_scale_gear(hba, true);
1252                 goto out_unprepare;
1253         }
1254
1255         /* scale up the gear after scaling up clocks */
1256         if (scale_up) {
1257                 ret = ufshcd_scale_gear(hba, true);
1258                 if (ret) {
1259                         ufshcd_scale_clks(hba, false);
1260                         goto out_unprepare;
1261                 }
1262         }
1263
1264         /* Enable Write Booster if we have scaled up else disable it */
1265         downgrade_write(&hba->clk_scaling_lock);
1266         is_writelock = false;
1267         ufshcd_wb_toggle(hba, scale_up);
1268
1269 out_unprepare:
1270         ufshcd_clock_scaling_unprepare(hba, is_writelock);
1271         return ret;
1272 }
1273
1274 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1275 {
1276         struct ufs_hba *hba = container_of(work, struct ufs_hba,
1277                                            clk_scaling.suspend_work);
1278         unsigned long irq_flags;
1279
1280         spin_lock_irqsave(hba->host->host_lock, irq_flags);
1281         if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1282                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1283                 return;
1284         }
1285         hba->clk_scaling.is_suspended = true;
1286         spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1287
1288         __ufshcd_suspend_clkscaling(hba);
1289 }
1290
1291 static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1292 {
1293         struct ufs_hba *hba = container_of(work, struct ufs_hba,
1294                                            clk_scaling.resume_work);
1295         unsigned long irq_flags;
1296
1297         spin_lock_irqsave(hba->host->host_lock, irq_flags);
1298         if (!hba->clk_scaling.is_suspended) {
1299                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1300                 return;
1301         }
1302         hba->clk_scaling.is_suspended = false;
1303         spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1304
1305         devfreq_resume_device(hba->devfreq);
1306 }
1307
1308 static int ufshcd_devfreq_target(struct device *dev,
1309                                 unsigned long *freq, u32 flags)
1310 {
1311         int ret = 0;
1312         struct ufs_hba *hba = dev_get_drvdata(dev);
1313         ktime_t start;
1314         bool scale_up, sched_clk_scaling_suspend_work = false;
1315         struct list_head *clk_list = &hba->clk_list_head;
1316         struct ufs_clk_info *clki;
1317         unsigned long irq_flags;
1318
1319         if (!ufshcd_is_clkscaling_supported(hba))
1320                 return -EINVAL;
1321
1322         clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1323         /* Override with the closest supported frequency */
1324         *freq = (unsigned long) clk_round_rate(clki->clk, *freq);
1325         spin_lock_irqsave(hba->host->host_lock, irq_flags);
1326         if (ufshcd_eh_in_progress(hba)) {
1327                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1328                 return 0;
1329         }
1330
1331         if (!hba->clk_scaling.active_reqs)
1332                 sched_clk_scaling_suspend_work = true;
1333
1334         if (list_empty(clk_list)) {
1335                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1336                 goto out;
1337         }
1338
1339         /* Decide based on the rounded-off frequency and update */
1340         scale_up = (*freq == clki->max_freq) ? true : false;
1341         if (!scale_up)
1342                 *freq = clki->min_freq;
1343         /* Update the frequency */
1344         if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1345                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1346                 ret = 0;
1347                 goto out; /* no state change required */
1348         }
1349         spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1350
1351         start = ktime_get();
1352         ret = ufshcd_devfreq_scale(hba, scale_up);
1353
1354         trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1355                 (scale_up ? "up" : "down"),
1356                 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1357
1358 out:
1359         if (sched_clk_scaling_suspend_work)
1360                 queue_work(hba->clk_scaling.workq,
1361                            &hba->clk_scaling.suspend_work);
1362
1363         return ret;
1364 }
1365
1366 static bool ufshcd_is_busy(struct request *req, void *priv, bool reserved)
1367 {
1368         int *busy = priv;
1369
1370         WARN_ON_ONCE(reserved);
1371         (*busy)++;
1372         return false;
1373 }
1374
1375 /* Whether or not any tag is in use by a request that is in progress. */
1376 static bool ufshcd_any_tag_in_use(struct ufs_hba *hba)
1377 {
1378         struct request_queue *q = hba->cmd_queue;
1379         int busy = 0;
1380
1381         blk_mq_tagset_busy_iter(q->tag_set, ufshcd_is_busy, &busy);
1382         return busy;
1383 }
1384
1385 static int ufshcd_devfreq_get_dev_status(struct device *dev,
1386                 struct devfreq_dev_status *stat)
1387 {
1388         struct ufs_hba *hba = dev_get_drvdata(dev);
1389         struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1390         unsigned long flags;
1391         struct list_head *clk_list = &hba->clk_list_head;
1392         struct ufs_clk_info *clki;
1393         ktime_t curr_t;
1394
1395         if (!ufshcd_is_clkscaling_supported(hba))
1396                 return -EINVAL;
1397
1398         memset(stat, 0, sizeof(*stat));
1399
1400         spin_lock_irqsave(hba->host->host_lock, flags);
1401         curr_t = ktime_get();
1402         if (!scaling->window_start_t)
1403                 goto start_window;
1404
1405         clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1406         /*
1407          * If current frequency is 0, then the ondemand governor considers
1408          * there's no initial frequency set. And it always requests to set
1409          * to max. frequency.
1410          */
1411         stat->current_frequency = clki->curr_freq;
1412         if (scaling->is_busy_started)
1413                 scaling->tot_busy_t += ktime_us_delta(curr_t,
1414                                 scaling->busy_start_t);
1415
1416         stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t);
1417         stat->busy_time = scaling->tot_busy_t;
1418 start_window:
1419         scaling->window_start_t = curr_t;
1420         scaling->tot_busy_t = 0;
1421
1422         if (hba->outstanding_reqs) {
1423                 scaling->busy_start_t = curr_t;
1424                 scaling->is_busy_started = true;
1425         } else {
1426                 scaling->busy_start_t = 0;
1427                 scaling->is_busy_started = false;
1428         }
1429         spin_unlock_irqrestore(hba->host->host_lock, flags);
1430         return 0;
1431 }
1432
1433 static int ufshcd_devfreq_init(struct ufs_hba *hba)
1434 {
1435         struct list_head *clk_list = &hba->clk_list_head;
1436         struct ufs_clk_info *clki;
1437         struct devfreq *devfreq;
1438         int ret;
1439
1440         /* Skip devfreq if we don't have any clocks in the list */
1441         if (list_empty(clk_list))
1442                 return 0;
1443
1444         clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1445         dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1446         dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1447
1448         ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile,
1449                                          &hba->vps->ondemand_data);
1450         devfreq = devfreq_add_device(hba->dev,
1451                         &hba->vps->devfreq_profile,
1452                         DEVFREQ_GOV_SIMPLE_ONDEMAND,
1453                         &hba->vps->ondemand_data);
1454         if (IS_ERR(devfreq)) {
1455                 ret = PTR_ERR(devfreq);
1456                 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
1457
1458                 dev_pm_opp_remove(hba->dev, clki->min_freq);
1459                 dev_pm_opp_remove(hba->dev, clki->max_freq);
1460                 return ret;
1461         }
1462
1463         hba->devfreq = devfreq;
1464
1465         return 0;
1466 }
1467
1468 static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1469 {
1470         struct list_head *clk_list = &hba->clk_list_head;
1471         struct ufs_clk_info *clki;
1472
1473         if (!hba->devfreq)
1474                 return;
1475
1476         devfreq_remove_device(hba->devfreq);
1477         hba->devfreq = NULL;
1478
1479         clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1480         dev_pm_opp_remove(hba->dev, clki->min_freq);
1481         dev_pm_opp_remove(hba->dev, clki->max_freq);
1482 }
1483
1484 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1485 {
1486         unsigned long flags;
1487
1488         devfreq_suspend_device(hba->devfreq);
1489         spin_lock_irqsave(hba->host->host_lock, flags);
1490         hba->clk_scaling.window_start_t = 0;
1491         spin_unlock_irqrestore(hba->host->host_lock, flags);
1492 }
1493
1494 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1495 {
1496         unsigned long flags;
1497         bool suspend = false;
1498
1499         cancel_work_sync(&hba->clk_scaling.suspend_work);
1500         cancel_work_sync(&hba->clk_scaling.resume_work);
1501
1502         spin_lock_irqsave(hba->host->host_lock, flags);
1503         if (!hba->clk_scaling.is_suspended) {
1504                 suspend = true;
1505                 hba->clk_scaling.is_suspended = true;
1506         }
1507         spin_unlock_irqrestore(hba->host->host_lock, flags);
1508
1509         if (suspend)
1510                 __ufshcd_suspend_clkscaling(hba);
1511 }
1512
1513 static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1514 {
1515         unsigned long flags;
1516         bool resume = false;
1517
1518         spin_lock_irqsave(hba->host->host_lock, flags);
1519         if (hba->clk_scaling.is_suspended) {
1520                 resume = true;
1521                 hba->clk_scaling.is_suspended = false;
1522         }
1523         spin_unlock_irqrestore(hba->host->host_lock, flags);
1524
1525         if (resume)
1526                 devfreq_resume_device(hba->devfreq);
1527 }
1528
1529 static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1530                 struct device_attribute *attr, char *buf)
1531 {
1532         struct ufs_hba *hba = dev_get_drvdata(dev);
1533
1534         return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled);
1535 }
1536
1537 static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1538                 struct device_attribute *attr, const char *buf, size_t count)
1539 {
1540         struct ufs_hba *hba = dev_get_drvdata(dev);
1541         u32 value;
1542         int err = 0;
1543
1544         if (kstrtou32(buf, 0, &value))
1545                 return -EINVAL;
1546
1547         down(&hba->host_sem);
1548         if (!ufshcd_is_user_access_allowed(hba)) {
1549                 err = -EBUSY;
1550                 goto out;
1551         }
1552
1553         value = !!value;
1554         if (value == hba->clk_scaling.is_enabled)
1555                 goto out;
1556
1557         ufshcd_rpm_get_sync(hba);
1558         ufshcd_hold(hba, false);
1559
1560         hba->clk_scaling.is_enabled = value;
1561
1562         if (value) {
1563                 ufshcd_resume_clkscaling(hba);
1564         } else {
1565                 ufshcd_suspend_clkscaling(hba);
1566                 err = ufshcd_devfreq_scale(hba, true);
1567                 if (err)
1568                         dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1569                                         __func__, err);
1570         }
1571
1572         ufshcd_release(hba);
1573         ufshcd_rpm_put_sync(hba);
1574 out:
1575         up(&hba->host_sem);
1576         return err ? err : count;
1577 }
1578
1579 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba)
1580 {
1581         hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1582         hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1583         sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1584         hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1585         hba->clk_scaling.enable_attr.attr.mode = 0644;
1586         if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1587                 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1588 }
1589
1590 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba)
1591 {
1592         if (hba->clk_scaling.enable_attr.attr.name)
1593                 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
1594 }
1595
1596 static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1597 {
1598         char wq_name[sizeof("ufs_clkscaling_00")];
1599
1600         if (!ufshcd_is_clkscaling_supported(hba))
1601                 return;
1602
1603         if (!hba->clk_scaling.min_gear)
1604                 hba->clk_scaling.min_gear = UFS_HS_G1;
1605
1606         INIT_WORK(&hba->clk_scaling.suspend_work,
1607                   ufshcd_clk_scaling_suspend_work);
1608         INIT_WORK(&hba->clk_scaling.resume_work,
1609                   ufshcd_clk_scaling_resume_work);
1610
1611         snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1612                  hba->host->host_no);
1613         hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1614
1615         hba->clk_scaling.is_initialized = true;
1616 }
1617
1618 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1619 {
1620         if (!hba->clk_scaling.is_initialized)
1621                 return;
1622
1623         ufshcd_remove_clk_scaling_sysfs(hba);
1624         destroy_workqueue(hba->clk_scaling.workq);
1625         ufshcd_devfreq_remove(hba);
1626         hba->clk_scaling.is_initialized = false;
1627 }
1628
1629 static void ufshcd_ungate_work(struct work_struct *work)
1630 {
1631         int ret;
1632         unsigned long flags;
1633         struct ufs_hba *hba = container_of(work, struct ufs_hba,
1634                         clk_gating.ungate_work);
1635
1636         cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1637
1638         spin_lock_irqsave(hba->host->host_lock, flags);
1639         if (hba->clk_gating.state == CLKS_ON) {
1640                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1641                 goto unblock_reqs;
1642         }
1643
1644         spin_unlock_irqrestore(hba->host->host_lock, flags);
1645         ufshcd_hba_vreg_set_hpm(hba);
1646         ufshcd_setup_clocks(hba, true);
1647
1648         ufshcd_enable_irq(hba);
1649
1650         /* Exit from hibern8 */
1651         if (ufshcd_can_hibern8_during_gating(hba)) {
1652                 /* Prevent gating in this path */
1653                 hba->clk_gating.is_suspended = true;
1654                 if (ufshcd_is_link_hibern8(hba)) {
1655                         ret = ufshcd_uic_hibern8_exit(hba);
1656                         if (ret)
1657                                 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1658                                         __func__, ret);
1659                         else
1660                                 ufshcd_set_link_active(hba);
1661                 }
1662                 hba->clk_gating.is_suspended = false;
1663         }
1664 unblock_reqs:
1665         ufshcd_scsi_unblock_requests(hba);
1666 }
1667
1668 /**
1669  * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1670  * Also, exit from hibern8 mode and set the link as active.
1671  * @hba: per adapter instance
1672  * @async: This indicates whether caller should ungate clocks asynchronously.
1673  */
1674 int ufshcd_hold(struct ufs_hba *hba, bool async)
1675 {
1676         int rc = 0;
1677         bool flush_result;
1678         unsigned long flags;
1679
1680         if (!ufshcd_is_clkgating_allowed(hba))
1681                 goto out;
1682         spin_lock_irqsave(hba->host->host_lock, flags);
1683         hba->clk_gating.active_reqs++;
1684
1685 start:
1686         switch (hba->clk_gating.state) {
1687         case CLKS_ON:
1688                 /*
1689                  * Wait for the ungate work to complete if in progress.
1690                  * Though the clocks may be in ON state, the link could
1691                  * still be in hibner8 state if hibern8 is allowed
1692                  * during clock gating.
1693                  * Make sure we exit hibern8 state also in addition to
1694                  * clocks being ON.
1695                  */
1696                 if (ufshcd_can_hibern8_during_gating(hba) &&
1697                     ufshcd_is_link_hibern8(hba)) {
1698                         if (async) {
1699                                 rc = -EAGAIN;
1700                                 hba->clk_gating.active_reqs--;
1701                                 break;
1702                         }
1703                         spin_unlock_irqrestore(hba->host->host_lock, flags);
1704                         flush_result = flush_work(&hba->clk_gating.ungate_work);
1705                         if (hba->clk_gating.is_suspended && !flush_result)
1706                                 goto out;
1707                         spin_lock_irqsave(hba->host->host_lock, flags);
1708                         goto start;
1709                 }
1710                 break;
1711         case REQ_CLKS_OFF:
1712                 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1713                         hba->clk_gating.state = CLKS_ON;
1714                         trace_ufshcd_clk_gating(dev_name(hba->dev),
1715                                                 hba->clk_gating.state);
1716                         break;
1717                 }
1718                 /*
1719                  * If we are here, it means gating work is either done or
1720                  * currently running. Hence, fall through to cancel gating
1721                  * work and to enable clocks.
1722                  */
1723                 fallthrough;
1724         case CLKS_OFF:
1725                 hba->clk_gating.state = REQ_CLKS_ON;
1726                 trace_ufshcd_clk_gating(dev_name(hba->dev),
1727                                         hba->clk_gating.state);
1728                 if (queue_work(hba->clk_gating.clk_gating_workq,
1729                                &hba->clk_gating.ungate_work))
1730                         ufshcd_scsi_block_requests(hba);
1731                 /*
1732                  * fall through to check if we should wait for this
1733                  * work to be done or not.
1734                  */
1735                 fallthrough;
1736         case REQ_CLKS_ON:
1737                 if (async) {
1738                         rc = -EAGAIN;
1739                         hba->clk_gating.active_reqs--;
1740                         break;
1741                 }
1742
1743                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1744                 flush_work(&hba->clk_gating.ungate_work);
1745                 /* Make sure state is CLKS_ON before returning */
1746                 spin_lock_irqsave(hba->host->host_lock, flags);
1747                 goto start;
1748         default:
1749                 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1750                                 __func__, hba->clk_gating.state);
1751                 break;
1752         }
1753         spin_unlock_irqrestore(hba->host->host_lock, flags);
1754 out:
1755         return rc;
1756 }
1757 EXPORT_SYMBOL_GPL(ufshcd_hold);
1758
1759 static void ufshcd_gate_work(struct work_struct *work)
1760 {
1761         struct ufs_hba *hba = container_of(work, struct ufs_hba,
1762                         clk_gating.gate_work.work);
1763         unsigned long flags;
1764         int ret;
1765
1766         spin_lock_irqsave(hba->host->host_lock, flags);
1767         /*
1768          * In case you are here to cancel this work the gating state
1769          * would be marked as REQ_CLKS_ON. In this case save time by
1770          * skipping the gating work and exit after changing the clock
1771          * state to CLKS_ON.
1772          */
1773         if (hba->clk_gating.is_suspended ||
1774                 (hba->clk_gating.state != REQ_CLKS_OFF)) {
1775                 hba->clk_gating.state = CLKS_ON;
1776                 trace_ufshcd_clk_gating(dev_name(hba->dev),
1777                                         hba->clk_gating.state);
1778                 goto rel_lock;
1779         }
1780
1781         if (hba->clk_gating.active_reqs
1782                 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1783                 || ufshcd_any_tag_in_use(hba) || hba->outstanding_tasks
1784                 || hba->active_uic_cmd || hba->uic_async_done)
1785                 goto rel_lock;
1786
1787         spin_unlock_irqrestore(hba->host->host_lock, flags);
1788
1789         /* put the link into hibern8 mode before turning off clocks */
1790         if (ufshcd_can_hibern8_during_gating(hba)) {
1791                 ret = ufshcd_uic_hibern8_enter(hba);
1792                 if (ret) {
1793                         hba->clk_gating.state = CLKS_ON;
1794                         dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
1795                                         __func__, ret);
1796                         trace_ufshcd_clk_gating(dev_name(hba->dev),
1797                                                 hba->clk_gating.state);
1798                         goto out;
1799                 }
1800                 ufshcd_set_link_hibern8(hba);
1801         }
1802
1803         ufshcd_disable_irq(hba);
1804
1805         ufshcd_setup_clocks(hba, false);
1806
1807         /* Put the host controller in low power mode if possible */
1808         ufshcd_hba_vreg_set_lpm(hba);
1809         /*
1810          * In case you are here to cancel this work the gating state
1811          * would be marked as REQ_CLKS_ON. In this case keep the state
1812          * as REQ_CLKS_ON which would anyway imply that clocks are off
1813          * and a request to turn them on is pending. By doing this way,
1814          * we keep the state machine in tact and this would ultimately
1815          * prevent from doing cancel work multiple times when there are
1816          * new requests arriving before the current cancel work is done.
1817          */
1818         spin_lock_irqsave(hba->host->host_lock, flags);
1819         if (hba->clk_gating.state == REQ_CLKS_OFF) {
1820                 hba->clk_gating.state = CLKS_OFF;
1821                 trace_ufshcd_clk_gating(dev_name(hba->dev),
1822                                         hba->clk_gating.state);
1823         }
1824 rel_lock:
1825         spin_unlock_irqrestore(hba->host->host_lock, flags);
1826 out:
1827         return;
1828 }
1829
1830 /* host lock must be held before calling this variant */
1831 static void __ufshcd_release(struct ufs_hba *hba)
1832 {
1833         if (!ufshcd_is_clkgating_allowed(hba))
1834                 return;
1835
1836         hba->clk_gating.active_reqs--;
1837
1838         if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended ||
1839             hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL ||
1840             hba->outstanding_tasks ||
1841             hba->active_uic_cmd || hba->uic_async_done ||
1842             hba->clk_gating.state == CLKS_OFF)
1843                 return;
1844
1845         hba->clk_gating.state = REQ_CLKS_OFF;
1846         trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
1847         queue_delayed_work(hba->clk_gating.clk_gating_workq,
1848                            &hba->clk_gating.gate_work,
1849                            msecs_to_jiffies(hba->clk_gating.delay_ms));
1850 }
1851
1852 void ufshcd_release(struct ufs_hba *hba)
1853 {
1854         unsigned long flags;
1855
1856         spin_lock_irqsave(hba->host->host_lock, flags);
1857         __ufshcd_release(hba);
1858         spin_unlock_irqrestore(hba->host->host_lock, flags);
1859 }
1860 EXPORT_SYMBOL_GPL(ufshcd_release);
1861
1862 static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1863                 struct device_attribute *attr, char *buf)
1864 {
1865         struct ufs_hba *hba = dev_get_drvdata(dev);
1866
1867         return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms);
1868 }
1869
1870 static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1871                 struct device_attribute *attr, const char *buf, size_t count)
1872 {
1873         struct ufs_hba *hba = dev_get_drvdata(dev);
1874         unsigned long flags, value;
1875
1876         if (kstrtoul(buf, 0, &value))
1877                 return -EINVAL;
1878
1879         spin_lock_irqsave(hba->host->host_lock, flags);
1880         hba->clk_gating.delay_ms = value;
1881         spin_unlock_irqrestore(hba->host->host_lock, flags);
1882         return count;
1883 }
1884
1885 static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1886                 struct device_attribute *attr, char *buf)
1887 {
1888         struct ufs_hba *hba = dev_get_drvdata(dev);
1889
1890         return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled);
1891 }
1892
1893 static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1894                 struct device_attribute *attr, const char *buf, size_t count)
1895 {
1896         struct ufs_hba *hba = dev_get_drvdata(dev);
1897         unsigned long flags;
1898         u32 value;
1899
1900         if (kstrtou32(buf, 0, &value))
1901                 return -EINVAL;
1902
1903         value = !!value;
1904
1905         spin_lock_irqsave(hba->host->host_lock, flags);
1906         if (value == hba->clk_gating.is_enabled)
1907                 goto out;
1908
1909         if (value)
1910                 __ufshcd_release(hba);
1911         else
1912                 hba->clk_gating.active_reqs++;
1913
1914         hba->clk_gating.is_enabled = value;
1915 out:
1916         spin_unlock_irqrestore(hba->host->host_lock, flags);
1917         return count;
1918 }
1919
1920 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba)
1921 {
1922         hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1923         hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1924         sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1925         hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
1926         hba->clk_gating.delay_attr.attr.mode = 0644;
1927         if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1928                 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
1929
1930         hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1931         hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1932         sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1933         hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1934         hba->clk_gating.enable_attr.attr.mode = 0644;
1935         if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1936                 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1937 }
1938
1939 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba)
1940 {
1941         if (hba->clk_gating.delay_attr.attr.name)
1942                 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
1943         if (hba->clk_gating.enable_attr.attr.name)
1944                 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
1945 }
1946
1947 static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1948 {
1949         char wq_name[sizeof("ufs_clk_gating_00")];
1950
1951         if (!ufshcd_is_clkgating_allowed(hba))
1952                 return;
1953
1954         hba->clk_gating.state = CLKS_ON;
1955
1956         hba->clk_gating.delay_ms = 150;
1957         INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1958         INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1959
1960         snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
1961                  hba->host->host_no);
1962         hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
1963                                         WQ_MEM_RECLAIM | WQ_HIGHPRI);
1964
1965         ufshcd_init_clk_gating_sysfs(hba);
1966
1967         hba->clk_gating.is_enabled = true;
1968         hba->clk_gating.is_initialized = true;
1969 }
1970
1971 static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1972 {
1973         if (!hba->clk_gating.is_initialized)
1974                 return;
1975         ufshcd_remove_clk_gating_sysfs(hba);
1976         cancel_work_sync(&hba->clk_gating.ungate_work);
1977         cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1978         destroy_workqueue(hba->clk_gating.clk_gating_workq);
1979         hba->clk_gating.is_initialized = false;
1980 }
1981
1982 /* Must be called with host lock acquired */
1983 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1984 {
1985         bool queue_resume_work = false;
1986         ktime_t curr_t = ktime_get();
1987
1988         if (!ufshcd_is_clkscaling_supported(hba))
1989                 return;
1990
1991         if (!hba->clk_scaling.active_reqs++)
1992                 queue_resume_work = true;
1993
1994         if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress)
1995                 return;
1996
1997         if (queue_resume_work)
1998                 queue_work(hba->clk_scaling.workq,
1999                            &hba->clk_scaling.resume_work);
2000
2001         if (!hba->clk_scaling.window_start_t) {
2002                 hba->clk_scaling.window_start_t = curr_t;
2003                 hba->clk_scaling.tot_busy_t = 0;
2004                 hba->clk_scaling.is_busy_started = false;
2005         }
2006
2007         if (!hba->clk_scaling.is_busy_started) {
2008                 hba->clk_scaling.busy_start_t = curr_t;
2009                 hba->clk_scaling.is_busy_started = true;
2010         }
2011 }
2012
2013 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
2014 {
2015         struct ufs_clk_scaling *scaling = &hba->clk_scaling;
2016
2017         if (!ufshcd_is_clkscaling_supported(hba))
2018                 return;
2019
2020         if (!hba->outstanding_reqs && scaling->is_busy_started) {
2021                 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
2022                                         scaling->busy_start_t));
2023                 scaling->busy_start_t = 0;
2024                 scaling->is_busy_started = false;
2025         }
2026 }
2027
2028 static inline int ufshcd_monitor_opcode2dir(u8 opcode)
2029 {
2030         if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16)
2031                 return READ;
2032         else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16)
2033                 return WRITE;
2034         else
2035                 return -EINVAL;
2036 }
2037
2038 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba,
2039                                                 struct ufshcd_lrb *lrbp)
2040 {
2041         struct ufs_hba_monitor *m = &hba->monitor;
2042
2043         return (m->enabled && lrbp && lrbp->cmd &&
2044                 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) &&
2045                 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp));
2046 }
2047
2048 static void ufshcd_start_monitor(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2049 {
2050         int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
2051
2052         if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0)
2053                 hba->monitor.busy_start_ts[dir] = ktime_get();
2054 }
2055
2056 static void ufshcd_update_monitor(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2057 {
2058         int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
2059
2060         if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) {
2061                 struct request *req = lrbp->cmd->request;
2062                 struct ufs_hba_monitor *m = &hba->monitor;
2063                 ktime_t now, inc, lat;
2064
2065                 now = lrbp->compl_time_stamp;
2066                 inc = ktime_sub(now, m->busy_start_ts[dir]);
2067                 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc);
2068                 m->nr_sec_rw[dir] += blk_rq_sectors(req);
2069
2070                 /* Update latencies */
2071                 m->nr_req[dir]++;
2072                 lat = ktime_sub(now, lrbp->issue_time_stamp);
2073                 m->lat_sum[dir] += lat;
2074                 if (m->lat_max[dir] < lat || !m->lat_max[dir])
2075                         m->lat_max[dir] = lat;
2076                 if (m->lat_min[dir] > lat || !m->lat_min[dir])
2077                         m->lat_min[dir] = lat;
2078
2079                 m->nr_queued[dir]--;
2080                 /* Push forward the busy start of monitor */
2081                 m->busy_start_ts[dir] = now;
2082         }
2083 }
2084
2085 /**
2086  * ufshcd_send_command - Send SCSI or device management commands
2087  * @hba: per adapter instance
2088  * @task_tag: Task tag of the command
2089  */
2090 static inline
2091 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
2092 {
2093         struct ufshcd_lrb *lrbp = &hba->lrb[task_tag];
2094
2095         lrbp->issue_time_stamp = ktime_get();
2096         lrbp->compl_time_stamp = ktime_set(0, 0);
2097         ufshcd_vops_setup_xfer_req(hba, task_tag, (lrbp->cmd ? true : false));
2098         ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND);
2099         ufshcd_clk_scaling_start_busy(hba);
2100         __set_bit(task_tag, &hba->outstanding_reqs);
2101         if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
2102                 ufshcd_start_monitor(hba, lrbp);
2103         ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
2104         /* Make sure that doorbell is committed immediately */
2105         wmb();
2106 }
2107
2108 /**
2109  * ufshcd_copy_sense_data - Copy sense data in case of check condition
2110  * @lrbp: pointer to local reference block
2111  */
2112 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
2113 {
2114         int len;
2115         if (lrbp->sense_buffer &&
2116             ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
2117                 int len_to_copy;
2118
2119                 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
2120                 len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
2121
2122                 memcpy(lrbp->sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
2123                        len_to_copy);
2124         }
2125 }
2126
2127 /**
2128  * ufshcd_copy_query_response() - Copy the Query Response and the data
2129  * descriptor
2130  * @hba: per adapter instance
2131  * @lrbp: pointer to local reference block
2132  */
2133 static
2134 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2135 {
2136         struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2137
2138         memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
2139
2140         /* Get the descriptor */
2141         if (hba->dev_cmd.query.descriptor &&
2142             lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
2143                 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
2144                                 GENERAL_UPIU_REQUEST_SIZE;
2145                 u16 resp_len;
2146                 u16 buf_len;
2147
2148                 /* data segment length */
2149                 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
2150                                                 MASK_QUERY_DATA_SEG_LEN;
2151                 buf_len = be16_to_cpu(
2152                                 hba->dev_cmd.query.request.upiu_req.length);
2153                 if (likely(buf_len >= resp_len)) {
2154                         memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
2155                 } else {
2156                         dev_warn(hba->dev,
2157                                  "%s: rsp size %d is bigger than buffer size %d",
2158                                  __func__, resp_len, buf_len);
2159                         return -EINVAL;
2160                 }
2161         }
2162
2163         return 0;
2164 }
2165
2166 /**
2167  * ufshcd_hba_capabilities - Read controller capabilities
2168  * @hba: per adapter instance
2169  *
2170  * Return: 0 on success, negative on error.
2171  */
2172 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba)
2173 {
2174         int err;
2175
2176         hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
2177
2178         /* nutrs and nutmrs are 0 based values */
2179         hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
2180         hba->nutmrs =
2181         ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
2182
2183         /* Read crypto capabilities */
2184         err = ufshcd_hba_init_crypto_capabilities(hba);
2185         if (err)
2186                 dev_err(hba->dev, "crypto setup failed\n");
2187
2188         return err;
2189 }
2190
2191 /**
2192  * ufshcd_ready_for_uic_cmd - Check if controller is ready
2193  *                            to accept UIC commands
2194  * @hba: per adapter instance
2195  * Return true on success, else false
2196  */
2197 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
2198 {
2199         if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
2200                 return true;
2201         else
2202                 return false;
2203 }
2204
2205 /**
2206  * ufshcd_get_upmcrs - Get the power mode change request status
2207  * @hba: Pointer to adapter instance
2208  *
2209  * This function gets the UPMCRS field of HCS register
2210  * Returns value of UPMCRS field
2211  */
2212 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
2213 {
2214         return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
2215 }
2216
2217 /**
2218  * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
2219  * @hba: per adapter instance
2220  * @uic_cmd: UIC command
2221  *
2222  * Mutex must be held.
2223  */
2224 static inline void
2225 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2226 {
2227         WARN_ON(hba->active_uic_cmd);
2228
2229         hba->active_uic_cmd = uic_cmd;
2230
2231         /* Write Args */
2232         ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2233         ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2234         ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
2235
2236         ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND);
2237
2238         /* Write UIC Cmd */
2239         ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
2240                       REG_UIC_COMMAND);
2241 }
2242
2243 /**
2244  * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
2245  * @hba: per adapter instance
2246  * @uic_cmd: UIC command
2247  *
2248  * Must be called with mutex held.
2249  * Returns 0 only if success.
2250  */
2251 static int
2252 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2253 {
2254         int ret;
2255         unsigned long flags;
2256
2257         if (wait_for_completion_timeout(&uic_cmd->done,
2258                                         msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2259                 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2260         } else {
2261                 ret = -ETIMEDOUT;
2262                 dev_err(hba->dev,
2263                         "uic cmd 0x%x with arg3 0x%x completion timeout\n",
2264                         uic_cmd->command, uic_cmd->argument3);
2265
2266                 if (!uic_cmd->cmd_active) {
2267                         dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n",
2268                                 __func__);
2269                         ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2270                 }
2271         }
2272
2273         spin_lock_irqsave(hba->host->host_lock, flags);
2274         hba->active_uic_cmd = NULL;
2275         spin_unlock_irqrestore(hba->host->host_lock, flags);
2276
2277         return ret;
2278 }
2279
2280 /**
2281  * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2282  * @hba: per adapter instance
2283  * @uic_cmd: UIC command
2284  * @completion: initialize the completion only if this is set to true
2285  *
2286  * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
2287  * with mutex held and host_lock locked.
2288  * Returns 0 only if success.
2289  */
2290 static int
2291 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2292                       bool completion)
2293 {
2294         if (!ufshcd_ready_for_uic_cmd(hba)) {
2295                 dev_err(hba->dev,
2296                         "Controller not ready to accept UIC commands\n");
2297                 return -EIO;
2298         }
2299
2300         if (completion)
2301                 init_completion(&uic_cmd->done);
2302
2303         uic_cmd->cmd_active = 1;
2304         ufshcd_dispatch_uic_cmd(hba, uic_cmd);
2305
2306         return 0;
2307 }
2308
2309 /**
2310  * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2311  * @hba: per adapter instance
2312  * @uic_cmd: UIC command
2313  *
2314  * Returns 0 only if success.
2315  */
2316 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2317 {
2318         int ret;
2319         unsigned long flags;
2320
2321         ufshcd_hold(hba, false);
2322         mutex_lock(&hba->uic_cmd_mutex);
2323         ufshcd_add_delay_before_dme_cmd(hba);
2324
2325         spin_lock_irqsave(hba->host->host_lock, flags);
2326         ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
2327         spin_unlock_irqrestore(hba->host->host_lock, flags);
2328         if (!ret)
2329                 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2330
2331         mutex_unlock(&hba->uic_cmd_mutex);
2332
2333         ufshcd_release(hba);
2334         return ret;
2335 }
2336
2337 /**
2338  * ufshcd_map_sg - Map scatter-gather list to prdt
2339  * @hba: per adapter instance
2340  * @lrbp: pointer to local reference block
2341  *
2342  * Returns 0 in case of success, non-zero value in case of failure
2343  */
2344 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2345 {
2346         struct ufshcd_sg_entry *prd_table;
2347         struct scatterlist *sg;
2348         struct scsi_cmnd *cmd;
2349         int sg_segments;
2350         int i;
2351
2352         cmd = lrbp->cmd;
2353         sg_segments = scsi_dma_map(cmd);
2354         if (sg_segments < 0)
2355                 return sg_segments;
2356
2357         if (sg_segments) {
2358
2359                 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2360                         lrbp->utr_descriptor_ptr->prd_table_length =
2361                                 cpu_to_le16((sg_segments *
2362                                         sizeof(struct ufshcd_sg_entry)));
2363                 else
2364                         lrbp->utr_descriptor_ptr->prd_table_length =
2365                                 cpu_to_le16((u16) (sg_segments));
2366
2367                 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
2368
2369                 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2370                         prd_table[i].size  =
2371                                 cpu_to_le32(((u32) sg_dma_len(sg))-1);
2372                         prd_table[i].base_addr =
2373                                 cpu_to_le32(lower_32_bits(sg->dma_address));
2374                         prd_table[i].upper_addr =
2375                                 cpu_to_le32(upper_32_bits(sg->dma_address));
2376                         prd_table[i].reserved = 0;
2377                 }
2378         } else {
2379                 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2380         }
2381
2382         return 0;
2383 }
2384
2385 /**
2386  * ufshcd_enable_intr - enable interrupts
2387  * @hba: per adapter instance
2388  * @intrs: interrupt bits
2389  */
2390 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
2391 {
2392         u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2393
2394         if (hba->ufs_version == ufshci_version(1, 0)) {
2395                 u32 rw;
2396                 rw = set & INTERRUPT_MASK_RW_VER_10;
2397                 set = rw | ((set ^ intrs) & intrs);
2398         } else {
2399                 set |= intrs;
2400         }
2401
2402         ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2403 }
2404
2405 /**
2406  * ufshcd_disable_intr - disable interrupts
2407  * @hba: per adapter instance
2408  * @intrs: interrupt bits
2409  */
2410 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2411 {
2412         u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2413
2414         if (hba->ufs_version == ufshci_version(1, 0)) {
2415                 u32 rw;
2416                 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2417                         ~(intrs & INTERRUPT_MASK_RW_VER_10);
2418                 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2419
2420         } else {
2421                 set &= ~intrs;
2422         }
2423
2424         ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2425 }
2426
2427 /**
2428  * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2429  * descriptor according to request
2430  * @lrbp: pointer to local reference block
2431  * @upiu_flags: flags required in the header
2432  * @cmd_dir: requests data direction
2433  */
2434 static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
2435                         u8 *upiu_flags, enum dma_data_direction cmd_dir)
2436 {
2437         struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2438         u32 data_direction;
2439         u32 dword_0;
2440         u32 dword_1 = 0;
2441         u32 dword_3 = 0;
2442
2443         if (cmd_dir == DMA_FROM_DEVICE) {
2444                 data_direction = UTP_DEVICE_TO_HOST;
2445                 *upiu_flags = UPIU_CMD_FLAGS_READ;
2446         } else if (cmd_dir == DMA_TO_DEVICE) {
2447                 data_direction = UTP_HOST_TO_DEVICE;
2448                 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2449         } else {
2450                 data_direction = UTP_NO_DATA_TRANSFER;
2451                 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2452         }
2453
2454         dword_0 = data_direction | (lrbp->command_type
2455                                 << UPIU_COMMAND_TYPE_OFFSET);
2456         if (lrbp->intr_cmd)
2457                 dword_0 |= UTP_REQ_DESC_INT_CMD;
2458
2459         /* Prepare crypto related dwords */
2460         ufshcd_prepare_req_desc_hdr_crypto(lrbp, &dword_0, &dword_1, &dword_3);
2461
2462         /* Transfer request descriptor header fields */
2463         req_desc->header.dword_0 = cpu_to_le32(dword_0);
2464         req_desc->header.dword_1 = cpu_to_le32(dword_1);
2465         /*
2466          * assigning invalid value for command status. Controller
2467          * updates OCS on command completion, with the command
2468          * status
2469          */
2470         req_desc->header.dword_2 =
2471                 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
2472         req_desc->header.dword_3 = cpu_to_le32(dword_3);
2473
2474         req_desc->prd_table_length = 0;
2475 }
2476
2477 /**
2478  * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2479  * for scsi commands
2480  * @lrbp: local reference block pointer
2481  * @upiu_flags: flags
2482  */
2483 static
2484 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags)
2485 {
2486         struct scsi_cmnd *cmd = lrbp->cmd;
2487         struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2488         unsigned short cdb_len;
2489
2490         /* command descriptor fields */
2491         ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2492                                 UPIU_TRANSACTION_COMMAND, upiu_flags,
2493                                 lrbp->lun, lrbp->task_tag);
2494         ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2495                                 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2496
2497         /* Total EHS length and Data segment length will be zero */
2498         ucd_req_ptr->header.dword_2 = 0;
2499
2500         ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
2501
2502         cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
2503         memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
2504         memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
2505
2506         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2507 }
2508
2509 /**
2510  * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2511  * for query requsts
2512  * @hba: UFS hba
2513  * @lrbp: local reference block pointer
2514  * @upiu_flags: flags
2515  */
2516 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2517                                 struct ufshcd_lrb *lrbp, u8 upiu_flags)
2518 {
2519         struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2520         struct ufs_query *query = &hba->dev_cmd.query;
2521         u16 len = be16_to_cpu(query->request.upiu_req.length);
2522
2523         /* Query request header */
2524         ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2525                         UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2526                         lrbp->lun, lrbp->task_tag);
2527         ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2528                         0, query->request.query_func, 0, 0);
2529
2530         /* Data segment length only need for WRITE_DESC */
2531         if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2532                 ucd_req_ptr->header.dword_2 =
2533                         UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2534         else
2535                 ucd_req_ptr->header.dword_2 = 0;
2536
2537         /* Copy the Query Request buffer as is */
2538         memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2539                         QUERY_OSF_SIZE);
2540
2541         /* Copy the Descriptor */
2542         if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2543                 memcpy(ucd_req_ptr + 1, query->descriptor, len);
2544
2545         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2546 }
2547
2548 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2549 {
2550         struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2551
2552         memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2553
2554         /* command descriptor fields */
2555         ucd_req_ptr->header.dword_0 =
2556                 UPIU_HEADER_DWORD(
2557                         UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
2558         /* clear rest of the fields of basic header */
2559         ucd_req_ptr->header.dword_1 = 0;
2560         ucd_req_ptr->header.dword_2 = 0;
2561
2562         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2563 }
2564
2565 /**
2566  * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU)
2567  *                           for Device Management Purposes
2568  * @hba: per adapter instance
2569  * @lrbp: pointer to local reference block
2570  */
2571 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba,
2572                                       struct ufshcd_lrb *lrbp)
2573 {
2574         u8 upiu_flags;
2575         int ret = 0;
2576
2577         if (hba->ufs_version <= ufshci_version(1, 1))
2578                 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
2579         else
2580                 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2581
2582         ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2583         if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2584                 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2585         else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2586                 ufshcd_prepare_utp_nop_upiu(lrbp);
2587         else
2588                 ret = -EINVAL;
2589
2590         return ret;
2591 }
2592
2593 /**
2594  * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2595  *                         for SCSI Purposes
2596  * @hba: per adapter instance
2597  * @lrbp: pointer to local reference block
2598  */
2599 static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2600 {
2601         u8 upiu_flags;
2602         int ret = 0;
2603
2604         if (hba->ufs_version <= ufshci_version(1, 1))
2605                 lrbp->command_type = UTP_CMD_TYPE_SCSI;
2606         else
2607                 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2608
2609         if (likely(lrbp->cmd)) {
2610                 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2611                                                 lrbp->cmd->sc_data_direction);
2612                 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2613         } else {
2614                 ret = -EINVAL;
2615         }
2616
2617         return ret;
2618 }
2619
2620 /**
2621  * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
2622  * @upiu_wlun_id: UPIU W-LUN id
2623  *
2624  * Returns SCSI W-LUN id
2625  */
2626 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2627 {
2628         return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2629 }
2630
2631 static inline bool is_rpmb_wlun(struct scsi_device *sdev)
2632 {
2633         return sdev->lun == ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN);
2634 }
2635
2636 static inline bool is_device_wlun(struct scsi_device *sdev)
2637 {
2638         return sdev->lun ==
2639                 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN);
2640 }
2641
2642 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i)
2643 {
2644         struct utp_transfer_cmd_desc *cmd_descp = hba->ucdl_base_addr;
2645         struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr;
2646         dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr +
2647                 i * sizeof(struct utp_transfer_cmd_desc);
2648         u16 response_offset = offsetof(struct utp_transfer_cmd_desc,
2649                                        response_upiu);
2650         u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
2651
2652         lrb->utr_descriptor_ptr = utrdlp + i;
2653         lrb->utrd_dma_addr = hba->utrdl_dma_addr +
2654                 i * sizeof(struct utp_transfer_req_desc);
2655         lrb->ucd_req_ptr = (struct utp_upiu_req *)(cmd_descp + i);
2656         lrb->ucd_req_dma_addr = cmd_desc_element_addr;
2657         lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2658         lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset;
2659         lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
2660         lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset;
2661 }
2662
2663 /**
2664  * ufshcd_queuecommand - main entry point for SCSI requests
2665  * @host: SCSI host pointer
2666  * @cmd: command from SCSI Midlayer
2667  *
2668  * Returns 0 for success, non-zero in case of failure
2669  */
2670 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2671 {
2672         struct ufshcd_lrb *lrbp;
2673         struct ufs_hba *hba;
2674         unsigned long flags;
2675         int tag;
2676         int err = 0;
2677
2678         hba = shost_priv(host);
2679
2680         tag = cmd->request->tag;
2681         if (!ufshcd_valid_tag(hba, tag)) {
2682                 dev_err(hba->dev,
2683                         "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
2684                         __func__, tag, cmd, cmd->request);
2685                 BUG();
2686         }
2687
2688         if (!down_read_trylock(&hba->clk_scaling_lock))
2689                 return SCSI_MLQUEUE_HOST_BUSY;
2690
2691         hba->req_abort_count = 0;
2692
2693         err = ufshcd_hold(hba, true);
2694         if (err) {
2695                 err = SCSI_MLQUEUE_HOST_BUSY;
2696                 goto out;
2697         }
2698         WARN_ON(ufshcd_is_clkgating_allowed(hba) &&
2699                 (hba->clk_gating.state != CLKS_ON));
2700
2701         lrbp = &hba->lrb[tag];
2702         if (unlikely(lrbp->in_use)) {
2703                 if (hba->pm_op_in_progress)
2704                         set_host_byte(cmd, DID_BAD_TARGET);
2705                 else
2706                         err = SCSI_MLQUEUE_HOST_BUSY;
2707                 ufshcd_release(hba);
2708                 goto out;
2709         }
2710
2711         WARN_ON(lrbp->cmd);
2712         lrbp->cmd = cmd;
2713         lrbp->sense_bufflen = UFS_SENSE_SIZE;
2714         lrbp->sense_buffer = cmd->sense_buffer;
2715         lrbp->task_tag = tag;
2716         lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
2717         lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
2718
2719         ufshcd_prepare_lrbp_crypto(cmd->request, lrbp);
2720
2721         lrbp->req_abort_skip = false;
2722
2723         ufshcd_comp_scsi_upiu(hba, lrbp);
2724
2725         err = ufshcd_map_sg(hba, lrbp);
2726         if (err) {
2727                 lrbp->cmd = NULL;
2728                 ufshcd_release(hba);
2729                 goto out;
2730         }
2731         /* Make sure descriptors are ready before ringing the doorbell */
2732         wmb();
2733
2734         spin_lock_irqsave(hba->host->host_lock, flags);
2735         switch (hba->ufshcd_state) {
2736         case UFSHCD_STATE_OPERATIONAL:
2737         case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL:
2738                 break;
2739         case UFSHCD_STATE_EH_SCHEDULED_FATAL:
2740                 /*
2741                  * pm_runtime_get_sync() is used at error handling preparation
2742                  * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's
2743                  * PM ops, it can never be finished if we let SCSI layer keep
2744                  * retrying it, which gets err handler stuck forever. Neither
2745                  * can we let the scsi cmd pass through, because UFS is in bad
2746                  * state, the scsi cmd may eventually time out, which will get
2747                  * err handler blocked for too long. So, just fail the scsi cmd
2748                  * sent from PM ops, err handler can recover PM error anyways.
2749                  */
2750                 if (hba->pm_op_in_progress) {
2751                         hba->force_reset = true;
2752                         set_host_byte(cmd, DID_BAD_TARGET);
2753                         goto out_compl_cmd;
2754                 }
2755                 fallthrough;
2756         case UFSHCD_STATE_RESET:
2757                 err = SCSI_MLQUEUE_HOST_BUSY;
2758                 goto out_compl_cmd;
2759         case UFSHCD_STATE_ERROR:
2760                 set_host_byte(cmd, DID_ERROR);
2761                 goto out_compl_cmd;
2762         default:
2763                 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
2764                                 __func__, hba->ufshcd_state);
2765                 set_host_byte(cmd, DID_BAD_TARGET);
2766                 goto out_compl_cmd;
2767         }
2768         ufshcd_send_command(hba, tag);
2769         spin_unlock_irqrestore(hba->host->host_lock, flags);
2770         goto out;
2771
2772 out_compl_cmd:
2773         scsi_dma_unmap(lrbp->cmd);
2774         lrbp->cmd = NULL;
2775         spin_unlock_irqrestore(hba->host->host_lock, flags);
2776         ufshcd_release(hba);
2777         if (!err)
2778                 cmd->scsi_done(cmd);
2779 out:
2780         up_read(&hba->clk_scaling_lock);
2781         return err;
2782 }
2783
2784 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2785                 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2786 {
2787         lrbp->cmd = NULL;
2788         lrbp->sense_bufflen = 0;
2789         lrbp->sense_buffer = NULL;
2790         lrbp->task_tag = tag;
2791         lrbp->lun = 0; /* device management cmd is not specific to any LUN */
2792         lrbp->intr_cmd = true; /* No interrupt aggregation */
2793         ufshcd_prepare_lrbp_crypto(NULL, lrbp);
2794         hba->dev_cmd.type = cmd_type;
2795
2796         return ufshcd_compose_devman_upiu(hba, lrbp);
2797 }
2798
2799 static int
2800 ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2801 {
2802         int err = 0;
2803         unsigned long flags;
2804         u32 mask = 1 << tag;
2805
2806         /* clear outstanding transaction before retry */
2807         spin_lock_irqsave(hba->host->host_lock, flags);
2808         ufshcd_utrl_clear(hba, tag);
2809         spin_unlock_irqrestore(hba->host->host_lock, flags);
2810
2811         /*
2812          * wait for for h/w to clear corresponding bit in door-bell.
2813          * max. wait is 1 sec.
2814          */
2815         err = ufshcd_wait_for_register(hba,
2816                         REG_UTP_TRANSFER_REQ_DOOR_BELL,
2817                         mask, ~mask, 1000, 1000);
2818
2819         return err;
2820 }
2821
2822 static int
2823 ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2824 {
2825         struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2826
2827         /* Get the UPIU response */
2828         query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2829                                 UPIU_RSP_CODE_OFFSET;
2830         return query_res->response;
2831 }
2832
2833 /**
2834  * ufshcd_dev_cmd_completion() - handles device management command responses
2835  * @hba: per adapter instance
2836  * @lrbp: pointer to local reference block
2837  */
2838 static int
2839 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2840 {
2841         int resp;
2842         int err = 0;
2843
2844         hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
2845         resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2846
2847         switch (resp) {
2848         case UPIU_TRANSACTION_NOP_IN:
2849                 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2850                         err = -EINVAL;
2851                         dev_err(hba->dev, "%s: unexpected response %x\n",
2852                                         __func__, resp);
2853                 }
2854                 break;
2855         case UPIU_TRANSACTION_QUERY_RSP:
2856                 err = ufshcd_check_query_response(hba, lrbp);
2857                 if (!err)
2858                         err = ufshcd_copy_query_response(hba, lrbp);
2859                 break;
2860         case UPIU_TRANSACTION_REJECT_UPIU:
2861                 /* TODO: handle Reject UPIU Response */
2862                 err = -EPERM;
2863                 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2864                                 __func__);
2865                 break;
2866         default:
2867                 err = -EINVAL;
2868                 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2869                                 __func__, resp);
2870                 break;
2871         }
2872
2873         return err;
2874 }
2875
2876 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2877                 struct ufshcd_lrb *lrbp, int max_timeout)
2878 {
2879         int err = 0;
2880         unsigned long time_left;
2881         unsigned long flags;
2882
2883         time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2884                         msecs_to_jiffies(max_timeout));
2885
2886         /* Make sure descriptors are ready before ringing the doorbell */
2887         wmb();
2888         spin_lock_irqsave(hba->host->host_lock, flags);
2889         hba->dev_cmd.complete = NULL;
2890         if (likely(time_left)) {
2891                 err = ufshcd_get_tr_ocs(lrbp);
2892                 if (!err)
2893                         err = ufshcd_dev_cmd_completion(hba, lrbp);
2894         }
2895         spin_unlock_irqrestore(hba->host->host_lock, flags);
2896
2897         if (!time_left) {
2898                 err = -ETIMEDOUT;
2899                 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2900                         __func__, lrbp->task_tag);
2901                 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
2902                         /* successfully cleared the command, retry if needed */
2903                         err = -EAGAIN;
2904                 /*
2905                  * in case of an error, after clearing the doorbell,
2906                  * we also need to clear the outstanding_request
2907                  * field in hba
2908                  */
2909                 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
2910         }
2911
2912         return err;
2913 }
2914
2915 /**
2916  * ufshcd_exec_dev_cmd - API for sending device management requests
2917  * @hba: UFS hba
2918  * @cmd_type: specifies the type (NOP, Query...)
2919  * @timeout: time in seconds
2920  *
2921  * NOTE: Since there is only one available tag for device management commands,
2922  * it is expected you hold the hba->dev_cmd.lock mutex.
2923  */
2924 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2925                 enum dev_cmd_type cmd_type, int timeout)
2926 {
2927         struct request_queue *q = hba->cmd_queue;
2928         struct request *req;
2929         struct ufshcd_lrb *lrbp;
2930         int err;
2931         int tag;
2932         struct completion wait;
2933         unsigned long flags;
2934
2935         down_read(&hba->clk_scaling_lock);
2936
2937         /*
2938          * Get free slot, sleep if slots are unavailable.
2939          * Even though we use wait_event() which sleeps indefinitely,
2940          * the maximum wait time is bounded by SCSI request timeout.
2941          */
2942         req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
2943         if (IS_ERR(req)) {
2944                 err = PTR_ERR(req);
2945                 goto out_unlock;
2946         }
2947         tag = req->tag;
2948         WARN_ON_ONCE(!ufshcd_valid_tag(hba, tag));
2949
2950         init_completion(&wait);
2951         lrbp = &hba->lrb[tag];
2952         if (unlikely(lrbp->in_use)) {
2953                 err = -EBUSY;
2954                 goto out;
2955         }
2956
2957         WARN_ON(lrbp->cmd);
2958         err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2959         if (unlikely(err))
2960                 goto out_put_tag;
2961
2962         hba->dev_cmd.complete = &wait;
2963
2964         ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
2965         /* Make sure descriptors are ready before ringing the doorbell */
2966         wmb();
2967         spin_lock_irqsave(hba->host->host_lock, flags);
2968         ufshcd_send_command(hba, tag);
2969         spin_unlock_irqrestore(hba->host->host_lock, flags);
2970
2971         err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2972
2973 out:
2974         ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
2975                                     (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
2976
2977 out_put_tag:
2978         blk_put_request(req);
2979 out_unlock:
2980         up_read(&hba->clk_scaling_lock);
2981         return err;
2982 }
2983
2984 /**
2985  * ufshcd_init_query() - init the query response and request parameters
2986  * @hba: per-adapter instance
2987  * @request: address of the request pointer to be initialized
2988  * @response: address of the response pointer to be initialized
2989  * @opcode: operation to perform
2990  * @idn: flag idn to access
2991  * @index: LU number to access
2992  * @selector: query/flag/descriptor further identification
2993  */
2994 static inline void ufshcd_init_query(struct ufs_hba *hba,
2995                 struct ufs_query_req **request, struct ufs_query_res **response,
2996                 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2997 {
2998         *request = &hba->dev_cmd.query.request;
2999         *response = &hba->dev_cmd.query.response;
3000         memset(*request, 0, sizeof(struct ufs_query_req));
3001         memset(*response, 0, sizeof(struct ufs_query_res));
3002         (*request)->upiu_req.opcode = opcode;
3003         (*request)->upiu_req.idn = idn;
3004         (*request)->upiu_req.index = index;
3005         (*request)->upiu_req.selector = selector;
3006 }
3007
3008 static int ufshcd_query_flag_retry(struct ufs_hba *hba,
3009         enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res)
3010 {
3011         int ret;
3012         int retries;
3013
3014         for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
3015                 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res);
3016                 if (ret)
3017                         dev_dbg(hba->dev,
3018                                 "%s: failed with error %d, retries %d\n",
3019                                 __func__, ret, retries);
3020                 else
3021                         break;
3022         }
3023
3024         if (ret)
3025                 dev_err(hba->dev,
3026                         "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
3027                         __func__, opcode, idn, ret, retries);
3028         return ret;
3029 }
3030
3031 /**
3032  * ufshcd_query_flag() - API function for sending flag query requests
3033  * @hba: per-adapter instance
3034  * @opcode: flag query to perform
3035  * @idn: flag idn to access
3036  * @index: flag index to access
3037  * @flag_res: the flag value after the query request completes
3038  *
3039  * Returns 0 for success, non-zero in case of failure
3040  */
3041 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
3042                         enum flag_idn idn, u8 index, bool *flag_res)
3043 {
3044         struct ufs_query_req *request = NULL;
3045         struct ufs_query_res *response = NULL;
3046         int err, selector = 0;
3047         int timeout = QUERY_REQ_TIMEOUT;
3048
3049         BUG_ON(!hba);
3050
3051         ufshcd_hold(hba, false);
3052         mutex_lock(&hba->dev_cmd.lock);
3053         ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3054                         selector);
3055
3056         switch (opcode) {
3057         case UPIU_QUERY_OPCODE_SET_FLAG:
3058         case UPIU_QUERY_OPCODE_CLEAR_FLAG:
3059         case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
3060                 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3061                 break;
3062         case UPIU_QUERY_OPCODE_READ_FLAG:
3063                 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3064                 if (!flag_res) {
3065                         /* No dummy reads */
3066                         dev_err(hba->dev, "%s: Invalid argument for read request\n",
3067                                         __func__);
3068                         err = -EINVAL;
3069                         goto out_unlock;
3070                 }
3071                 break;
3072         default:
3073                 dev_err(hba->dev,
3074                         "%s: Expected query flag opcode but got = %d\n",
3075                         __func__, opcode);
3076                 err = -EINVAL;
3077                 goto out_unlock;
3078         }
3079
3080         err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
3081
3082         if (err) {
3083                 dev_err(hba->dev,
3084                         "%s: Sending flag query for idn %d failed, err = %d\n",
3085                         __func__, idn, err);
3086                 goto out_unlock;
3087         }
3088
3089         if (flag_res)
3090                 *flag_res = (be32_to_cpu(response->upiu_res.value) &
3091                                 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
3092
3093 out_unlock:
3094         mutex_unlock(&hba->dev_cmd.lock);
3095         ufshcd_release(hba);
3096         return err;
3097 }
3098
3099 /**
3100  * ufshcd_query_attr - API function for sending attribute requests
3101  * @hba: per-adapter instance
3102  * @opcode: attribute opcode
3103  * @idn: attribute idn to access
3104  * @index: index field
3105  * @selector: selector field
3106  * @attr_val: the attribute value after the query request completes
3107  *
3108  * Returns 0 for success, non-zero in case of failure
3109 */
3110 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
3111                       enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
3112 {
3113         struct ufs_query_req *request = NULL;
3114         struct ufs_query_res *response = NULL;
3115         int err;
3116
3117         BUG_ON(!hba);
3118
3119         if (!attr_val) {
3120                 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
3121                                 __func__, opcode);
3122                 return -EINVAL;
3123         }
3124
3125         ufshcd_hold(hba, false);
3126
3127         mutex_lock(&hba->dev_cmd.lock);
3128         ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3129                         selector);
3130
3131         switch (opcode) {
3132         case UPIU_QUERY_OPCODE_WRITE_ATTR:
3133                 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3134                 request->upiu_req.value = cpu_to_be32(*attr_val);
3135                 break;
3136         case UPIU_QUERY_OPCODE_READ_ATTR:
3137                 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3138                 break;
3139         default:
3140                 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
3141                                 __func__, opcode);
3142                 err = -EINVAL;
3143                 goto out_unlock;
3144         }
3145
3146         err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3147
3148         if (err) {
3149                 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3150                                 __func__, opcode, idn, index, err);
3151                 goto out_unlock;
3152         }
3153
3154         *attr_val = be32_to_cpu(response->upiu_res.value);
3155
3156 out_unlock:
3157         mutex_unlock(&hba->dev_cmd.lock);
3158         ufshcd_release(hba);
3159         return err;
3160 }
3161
3162 /**
3163  * ufshcd_query_attr_retry() - API function for sending query
3164  * attribute with retries
3165  * @hba: per-adapter instance
3166  * @opcode: attribute opcode
3167  * @idn: attribute idn to access
3168  * @index: index field
3169  * @selector: selector field
3170  * @attr_val: the attribute value after the query request
3171  * completes
3172  *
3173  * Returns 0 for success, non-zero in case of failure
3174 */
3175 static int ufshcd_query_attr_retry(struct ufs_hba *hba,
3176         enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
3177         u32 *attr_val)
3178 {
3179         int ret = 0;
3180         u32 retries;
3181
3182         for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3183                 ret = ufshcd_query_attr(hba, opcode, idn, index,
3184                                                 selector, attr_val);
3185                 if (ret)
3186                         dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
3187                                 __func__, ret, retries);
3188                 else
3189                         break;
3190         }
3191
3192         if (ret)
3193                 dev_err(hba->dev,
3194                         "%s: query attribute, idn %d, failed with error %d after %d retires\n",
3195                         __func__, idn, ret, QUERY_REQ_RETRIES);
3196         return ret;
3197 }
3198
3199 static int __ufshcd_query_descriptor(struct ufs_hba *hba,
3200                         enum query_opcode opcode, enum desc_idn idn, u8 index,
3201                         u8 selector, u8 *desc_buf, int *buf_len)
3202 {
3203         struct ufs_query_req *request = NULL;
3204         struct ufs_query_res *response = NULL;
3205         int err;
3206
3207         BUG_ON(!hba);
3208
3209         if (!desc_buf) {
3210                 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
3211                                 __func__, opcode);
3212                 return -EINVAL;
3213         }
3214
3215         if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
3216                 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
3217                                 __func__, *buf_len);
3218                 return -EINVAL;
3219         }
3220
3221         ufshcd_hold(hba, false);
3222
3223         mutex_lock(&hba->dev_cmd.lock);
3224         ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3225                         selector);
3226         hba->dev_cmd.query.descriptor = desc_buf;
3227         request->upiu_req.length = cpu_to_be16(*buf_len);
3228
3229         switch (opcode) {
3230         case UPIU_QUERY_OPCODE_WRITE_DESC:
3231                 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3232                 break;
3233         case UPIU_QUERY_OPCODE_READ_DESC:
3234                 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3235                 break;
3236         default:
3237                 dev_err(hba->dev,
3238                                 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
3239                                 __func__, opcode);
3240                 err = -EINVAL;
3241                 goto out_unlock;
3242         }
3243
3244         err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3245
3246         if (err) {
3247                 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3248                                 __func__, opcode, idn, index, err);
3249                 goto out_unlock;
3250         }
3251
3252         *buf_len = be16_to_cpu(response->upiu_res.length);
3253
3254 out_unlock:
3255         hba->dev_cmd.query.descriptor = NULL;
3256         mutex_unlock(&hba->dev_cmd.lock);
3257         ufshcd_release(hba);
3258         return err;
3259 }
3260
3261 /**
3262  * ufshcd_query_descriptor_retry - API function for sending descriptor requests
3263  * @hba: per-adapter instance
3264  * @opcode: attribute opcode
3265  * @idn: attribute idn to access
3266  * @index: index field
3267  * @selector: selector field
3268  * @desc_buf: the buffer that contains the descriptor
3269  * @buf_len: length parameter passed to the device
3270  *
3271  * Returns 0 for success, non-zero in case of failure.
3272  * The buf_len parameter will contain, on return, the length parameter
3273  * received on the response.
3274  */
3275 int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3276                                   enum query_opcode opcode,
3277                                   enum desc_idn idn, u8 index,
3278                                   u8 selector,
3279                                   u8 *desc_buf, int *buf_len)
3280 {
3281         int err;
3282         int retries;
3283
3284         for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3285                 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3286                                                 selector, desc_buf, buf_len);
3287                 if (!err || err == -EINVAL)
3288                         break;
3289         }
3290
3291         return err;
3292 }
3293
3294 /**
3295  * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
3296  * @hba: Pointer to adapter instance
3297  * @desc_id: descriptor idn value
3298  * @desc_len: mapped desc length (out)
3299  */
3300 void ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
3301                                   int *desc_len)
3302 {
3303         if (desc_id >= QUERY_DESC_IDN_MAX || desc_id == QUERY_DESC_IDN_RFU_0 ||
3304             desc_id == QUERY_DESC_IDN_RFU_1)
3305                 *desc_len = 0;
3306         else
3307                 *desc_len = hba->desc_size[desc_id];
3308 }
3309 EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
3310
3311 static void ufshcd_update_desc_length(struct ufs_hba *hba,
3312                                       enum desc_idn desc_id, int desc_index,
3313                                       unsigned char desc_len)
3314 {
3315         if (hba->desc_size[desc_id] == QUERY_DESC_MAX_SIZE &&
3316             desc_id != QUERY_DESC_IDN_STRING && desc_index != UFS_RPMB_UNIT)
3317                 /* For UFS 3.1, the normal unit descriptor is 10 bytes larger
3318                  * than the RPMB unit, however, both descriptors share the same
3319                  * desc_idn, to cover both unit descriptors with one length, we
3320                  * choose the normal unit descriptor length by desc_index.
3321                  */
3322                 hba->desc_size[desc_id] = desc_len;
3323 }
3324
3325 /**
3326  * ufshcd_read_desc_param - read the specified descriptor parameter
3327  * @hba: Pointer to adapter instance
3328  * @desc_id: descriptor idn value
3329  * @desc_index: descriptor index
3330  * @param_offset: offset of the parameter to read
3331  * @param_read_buf: pointer to buffer where parameter would be read
3332  * @param_size: sizeof(param_read_buf)
3333  *
3334  * Return 0 in case of success, non-zero otherwise
3335  */
3336 int ufshcd_read_desc_param(struct ufs_hba *hba,
3337                            enum desc_idn desc_id,
3338                            int desc_index,
3339                            u8 param_offset,
3340                            u8 *param_read_buf,
3341                            u8 param_size)
3342 {
3343         int ret;
3344         u8 *desc_buf;
3345         int buff_len;
3346         bool is_kmalloc = true;
3347
3348         /* Safety check */
3349         if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
3350                 return -EINVAL;
3351
3352         /* Get the length of descriptor */
3353         ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
3354         if (!buff_len) {
3355                 dev_err(hba->dev, "%s: Failed to get desc length\n", __func__);
3356                 return -EINVAL;
3357         }
3358
3359         if (param_offset >= buff_len) {
3360                 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n",
3361                         __func__, param_offset, desc_id, buff_len);
3362                 return -EINVAL;
3363         }
3364
3365         /* Check whether we need temp memory */
3366         if (param_offset != 0 || param_size < buff_len) {
3367                 desc_buf = kzalloc(buff_len, GFP_KERNEL);
3368                 if (!desc_buf)
3369                         return -ENOMEM;
3370         } else {
3371                 desc_buf = param_read_buf;
3372                 is_kmalloc = false;
3373         }
3374
3375         /* Request for full descriptor */
3376         ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3377                                         desc_id, desc_index, 0,
3378                                         desc_buf, &buff_len);
3379
3380         if (ret) {
3381                 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n",
3382                         __func__, desc_id, desc_index, param_offset, ret);
3383                 goto out;
3384         }
3385
3386         /* Sanity check */
3387         if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3388                 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n",
3389                         __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3390                 ret = -EINVAL;
3391                 goto out;
3392         }
3393
3394         /* Update descriptor length */
3395         buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET];
3396         ufshcd_update_desc_length(hba, desc_id, desc_index, buff_len);
3397
3398         if (is_kmalloc) {
3399                 /* Make sure we don't copy more data than available */
3400                 if (param_offset + param_size > buff_len)
3401                         param_size = buff_len - param_offset;
3402                 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
3403         }
3404 out:
3405         if (is_kmalloc)
3406                 kfree(desc_buf);
3407         return ret;
3408 }
3409
3410 /**
3411  * struct uc_string_id - unicode string
3412  *
3413  * @len: size of this descriptor inclusive
3414  * @type: descriptor type
3415  * @uc: unicode string character
3416  */
3417 struct uc_string_id {
3418         u8 len;
3419         u8 type;
3420         wchar_t uc[];
3421 } __packed;
3422
3423 /* replace non-printable or non-ASCII characters with spaces */
3424 static inline char ufshcd_remove_non_printable(u8 ch)
3425 {
3426         return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3427 }
3428
3429 /**
3430  * ufshcd_read_string_desc - read string descriptor
3431  * @hba: pointer to adapter instance
3432  * @desc_index: descriptor index
3433  * @buf: pointer to buffer where descriptor would be read,
3434  *       the caller should free the memory.
3435  * @ascii: if true convert from unicode to ascii characters
3436  *         null terminated string.
3437  *
3438  * Return:
3439  * *      string size on success.
3440  * *      -ENOMEM: on allocation failure
3441  * *      -EINVAL: on a wrong parameter
3442  */
3443 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
3444                             u8 **buf, bool ascii)
3445 {
3446         struct uc_string_id *uc_str;
3447         u8 *str;
3448         int ret;
3449
3450         if (!buf)
3451                 return -EINVAL;
3452
3453         uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3454         if (!uc_str)
3455                 return -ENOMEM;
3456
3457         ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0,
3458                                      (u8 *)uc_str, QUERY_DESC_MAX_SIZE);
3459         if (ret < 0) {
3460                 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3461                         QUERY_REQ_RETRIES, ret);
3462                 str = NULL;
3463                 goto out;
3464         }
3465
3466         if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3467                 dev_dbg(hba->dev, "String Desc is of zero length\n");
3468                 str = NULL;
3469                 ret = 0;
3470                 goto out;
3471         }
3472
3473         if (ascii) {
3474                 ssize_t ascii_len;
3475                 int i;
3476                 /* remove header and divide by 2 to move from UTF16 to UTF8 */
3477                 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3478                 str = kzalloc(ascii_len, GFP_KERNEL);
3479                 if (!str) {
3480                         ret = -ENOMEM;
3481                         goto out;
3482                 }
3483
3484                 /*
3485                  * the descriptor contains string in UTF16 format
3486                  * we need to convert to utf-8 so it can be displayed
3487                  */
3488                 ret = utf16s_to_utf8s(uc_str->uc,
3489                                       uc_str->len - QUERY_DESC_HDR_SIZE,
3490                                       UTF16_BIG_ENDIAN, str, ascii_len);
3491
3492                 /* replace non-printable or non-ASCII characters with spaces */
3493                 for (i = 0; i < ret; i++)
3494                         str[i] = ufshcd_remove_non_printable(str[i]);
3495
3496                 str[ret++] = '\0';
3497
3498         } else {
3499                 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
3500                 if (!str) {
3501                         ret = -ENOMEM;
3502                         goto out;
3503                 }
3504                 ret = uc_str->len;
3505         }
3506 out:
3507         *buf = str;
3508         kfree(uc_str);
3509         return ret;
3510 }
3511
3512 /**
3513  * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3514  * @hba: Pointer to adapter instance
3515  * @lun: lun id
3516  * @param_offset: offset of the parameter to read
3517  * @param_read_buf: pointer to buffer where parameter would be read
3518  * @param_size: sizeof(param_read_buf)
3519  *
3520  * Return 0 in case of success, non-zero otherwise
3521  */
3522 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3523                                               int lun,
3524                                               enum unit_desc_param param_offset,
3525                                               u8 *param_read_buf,
3526                                               u32 param_size)
3527 {
3528         /*
3529          * Unit descriptors are only available for general purpose LUs (LUN id
3530          * from 0 to 7) and RPMB Well known LU.
3531          */
3532         if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun, param_offset))
3533                 return -EOPNOTSUPP;
3534
3535         return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3536                                       param_offset, param_read_buf, param_size);
3537 }
3538
3539 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
3540 {
3541         int err = 0;
3542         u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3543
3544         if (hba->dev_info.wspecversion >= 0x300) {
3545                 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3546                                 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0,
3547                                 &gating_wait);
3548                 if (err)
3549                         dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
3550                                          err, gating_wait);
3551
3552                 if (gating_wait == 0) {
3553                         gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3554                         dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
3555                                          gating_wait);
3556                 }
3557
3558                 hba->dev_info.clk_gating_wait_us = gating_wait;
3559         }
3560
3561         return err;
3562 }
3563
3564 /**
3565  * ufshcd_memory_alloc - allocate memory for host memory space data structures
3566  * @hba: per adapter instance
3567  *
3568  * 1. Allocate DMA memory for Command Descriptor array
3569  *      Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3570  * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3571  * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3572  *      (UTMRDL)
3573  * 4. Allocate memory for local reference block(lrb).
3574  *
3575  * Returns 0 for success, non-zero in case of failure
3576  */
3577 static int ufshcd_memory_alloc(struct ufs_hba *hba)
3578 {
3579         size_t utmrdl_size, utrdl_size, ucdl_size;
3580
3581         /* Allocate memory for UTP command descriptors */
3582         ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
3583         hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3584                                                   ucdl_size,
3585                                                   &hba->ucdl_dma_addr,
3586                                                   GFP_KERNEL);
3587
3588         /*
3589          * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3590          * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3591          * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3592          * be aligned to 128 bytes as well
3593          */
3594         if (!hba->ucdl_base_addr ||
3595             WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3596                 dev_err(hba->dev,
3597                         "Command Descriptor Memory allocation failed\n");
3598                 goto out;
3599         }
3600
3601         /*
3602          * Allocate memory for UTP Transfer descriptors
3603          * UFSHCI requires 1024 byte alignment of UTRD
3604          */
3605         utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
3606         hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3607                                                    utrdl_size,
3608                                                    &hba->utrdl_dma_addr,
3609                                                    GFP_KERNEL);
3610         if (!hba->utrdl_base_addr ||
3611             WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3612                 dev_err(hba->dev,
3613                         "Transfer Descriptor Memory allocation failed\n");
3614                 goto out;
3615         }
3616
3617         /*
3618          * Allocate memory for UTP Task Management descriptors
3619          * UFSHCI requires 1024 byte alignment of UTMRD
3620          */
3621         utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
3622         hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3623                                                     utmrdl_size,
3624                                                     &hba->utmrdl_dma_addr,
3625                                                     GFP_KERNEL);
3626         if (!hba->utmrdl_base_addr ||
3627             WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3628                 dev_err(hba->dev,
3629                 "Task Management Descriptor Memory allocation failed\n");
3630                 goto out;
3631         }
3632
3633         /* Allocate memory for local reference block */
3634         hba->lrb = devm_kcalloc(hba->dev,
3635                                 hba->nutrs, sizeof(struct ufshcd_lrb),
3636                                 GFP_KERNEL);
3637         if (!hba->lrb) {
3638                 dev_err(hba->dev, "LRB Memory allocation failed\n");
3639                 goto out;
3640         }
3641         return 0;
3642 out:
3643         return -ENOMEM;
3644 }
3645
3646 /**
3647  * ufshcd_host_memory_configure - configure local reference block with
3648  *                              memory offsets
3649  * @hba: per adapter instance
3650  *
3651  * Configure Host memory space
3652  * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3653  * address.
3654  * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3655  * and PRDT offset.
3656  * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3657  * into local reference block.
3658  */
3659 static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3660 {
3661         struct utp_transfer_req_desc *utrdlp;
3662         dma_addr_t cmd_desc_dma_addr;
3663         dma_addr_t cmd_desc_element_addr;
3664         u16 response_offset;
3665         u16 prdt_offset;
3666         int cmd_desc_size;
3667         int i;
3668
3669         utrdlp = hba->utrdl_base_addr;
3670
3671         response_offset =
3672                 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3673         prdt_offset =
3674                 offsetof(struct utp_transfer_cmd_desc, prd_table);
3675
3676         cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3677         cmd_desc_dma_addr = hba->ucdl_dma_addr;
3678
3679         for (i = 0; i < hba->nutrs; i++) {
3680                 /* Configure UTRD with command descriptor base address */
3681                 cmd_desc_element_addr =
3682                                 (cmd_desc_dma_addr + (cmd_desc_size * i));
3683                 utrdlp[i].command_desc_base_addr_lo =
3684                                 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3685                 utrdlp[i].command_desc_base_addr_hi =
3686                                 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3687
3688                 /* Response upiu and prdt offset should be in double words */
3689                 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3690                         utrdlp[i].response_upiu_offset =
3691                                 cpu_to_le16(response_offset);
3692                         utrdlp[i].prd_table_offset =
3693                                 cpu_to_le16(prdt_offset);
3694                         utrdlp[i].response_upiu_length =
3695                                 cpu_to_le16(ALIGNED_UPIU_SIZE);
3696                 } else {
3697                         utrdlp[i].response_upiu_offset =
3698                                 cpu_to_le16(response_offset >> 2);
3699                         utrdlp[i].prd_table_offset =
3700                                 cpu_to_le16(prdt_offset >> 2);
3701                         utrdlp[i].response_upiu_length =
3702                                 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
3703                 }
3704
3705                 ufshcd_init_lrb(hba, &hba->lrb[i], i);
3706         }
3707 }
3708
3709 /**
3710  * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3711  * @hba: per adapter instance
3712  *
3713  * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3714  * in order to initialize the Unipro link startup procedure.
3715  * Once the Unipro links are up, the device connected to the controller
3716  * is detected.
3717  *
3718  * Returns 0 on success, non-zero value on failure
3719  */
3720 static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3721 {
3722         struct uic_command uic_cmd = {0};
3723         int ret;
3724
3725         uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
3726
3727         ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3728         if (ret)
3729                 dev_dbg(hba->dev,
3730                         "dme-link-startup: error code %d\n", ret);
3731         return ret;
3732 }
3733 /**
3734  * ufshcd_dme_reset - UIC command for DME_RESET
3735  * @hba: per adapter instance
3736  *
3737  * DME_RESET command is issued in order to reset UniPro stack.
3738  * This function now deals with cold reset.
3739  *
3740  * Returns 0 on success, non-zero value on failure
3741  */
3742 static int ufshcd_dme_reset(struct ufs_hba *hba)
3743 {
3744         struct uic_command uic_cmd = {0};
3745         int ret;
3746
3747         uic_cmd.command = UIC_CMD_DME_RESET;
3748
3749         ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3750         if (ret)
3751                 dev_err(hba->dev,
3752                         "dme-reset: error code %d\n", ret);
3753
3754         return ret;
3755 }
3756
3757 int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
3758                                int agreed_gear,
3759                                int adapt_val)
3760 {
3761         int ret;
3762
3763         if (agreed_gear != UFS_HS_G4)
3764                 adapt_val = PA_NO_ADAPT;
3765
3766         ret = ufshcd_dme_set(hba,
3767                              UIC_ARG_MIB(PA_TXHSADAPTTYPE),
3768                              adapt_val);
3769         return ret;
3770 }
3771 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt);
3772
3773 /**
3774  * ufshcd_dme_enable - UIC command for DME_ENABLE
3775  * @hba: per adapter instance
3776  *
3777  * DME_ENABLE command is issued in order to enable UniPro stack.
3778  *
3779  * Returns 0 on success, non-zero value on failure
3780  */
3781 static int ufshcd_dme_enable(struct ufs_hba *hba)
3782 {
3783         struct uic_command uic_cmd = {0};
3784         int ret;
3785
3786         uic_cmd.command = UIC_CMD_DME_ENABLE;
3787
3788         ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3789         if (ret)
3790                 dev_err(hba->dev,
3791                         "dme-enable: error code %d\n", ret);
3792
3793         return ret;
3794 }
3795
3796 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3797 {
3798         #define MIN_DELAY_BEFORE_DME_CMDS_US    1000
3799         unsigned long min_sleep_time_us;
3800
3801         if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3802                 return;
3803
3804         /*
3805          * last_dme_cmd_tstamp will be 0 only for 1st call to
3806          * this function
3807          */
3808         if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3809                 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3810         } else {
3811                 unsigned long delta =
3812                         (unsigned long) ktime_to_us(
3813                                 ktime_sub(ktime_get(),
3814                                 hba->last_dme_cmd_tstamp));
3815
3816                 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3817                         min_sleep_time_us =
3818                                 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3819                 else
3820                         return; /* no more delay required */
3821         }
3822
3823         /* allow sleep for extra 50us if needed */
3824         usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3825 }
3826
3827 /**
3828  * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3829  * @hba: per adapter instance
3830  * @attr_sel: uic command argument1
3831  * @attr_set: attribute set type as uic command argument2
3832  * @mib_val: setting value as uic command argument3
3833  * @peer: indicate whether peer or local
3834  *
3835  * Returns 0 on success, non-zero value on failure
3836  */
3837 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3838                         u8 attr_set, u32 mib_val, u8 peer)
3839 {
3840         struct uic_command uic_cmd = {0};
3841         static const char *const action[] = {
3842                 "dme-set",
3843                 "dme-peer-set"
3844         };
3845         const char *set = action[!!peer];
3846         int ret;
3847         int retries = UFS_UIC_COMMAND_RETRIES;
3848
3849         uic_cmd.command = peer ?
3850                 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3851         uic_cmd.argument1 = attr_sel;
3852         uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3853         uic_cmd.argument3 = mib_val;
3854
3855         do {
3856                 /* for peer attributes we retry upon failure */
3857                 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3858                 if (ret)
3859                         dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3860                                 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3861         } while (ret && peer && --retries);
3862
3863         if (ret)
3864                 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
3865                         set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3866                         UFS_UIC_COMMAND_RETRIES - retries);
3867
3868         return ret;
3869 }
3870 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3871
3872 /**
3873  * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3874  * @hba: per adapter instance
3875  * @attr_sel: uic command argument1
3876  * @mib_val: the value of the attribute as returned by the UIC command
3877  * @peer: indicate whether peer or local
3878  *
3879  * Returns 0 on success, non-zero value on failure
3880  */
3881 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3882                         u32 *mib_val, u8 peer)
3883 {
3884         struct uic_command uic_cmd = {0};
3885         static const char *const action[] = {
3886                 "dme-get",
3887                 "dme-peer-get"
3888         };
3889         const char *get = action[!!peer];
3890         int ret;
3891         int retries = UFS_UIC_COMMAND_RETRIES;
3892         struct ufs_pa_layer_attr orig_pwr_info;
3893         struct ufs_pa_layer_attr temp_pwr_info;
3894         bool pwr_mode_change = false;
3895
3896         if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3897                 orig_pwr_info = hba->pwr_info;
3898                 temp_pwr_info = orig_pwr_info;
3899
3900                 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3901                     orig_pwr_info.pwr_rx == FAST_MODE) {
3902                         temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3903                         temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3904                         pwr_mode_change = true;
3905                 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3906                     orig_pwr_info.pwr_rx == SLOW_MODE) {
3907                         temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3908                         temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3909                         pwr_mode_change = true;
3910                 }
3911                 if (pwr_mode_change) {
3912                         ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3913                         if (ret)
3914                                 goto out;
3915                 }
3916         }
3917
3918         uic_cmd.command = peer ?
3919                 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3920         uic_cmd.argument1 = attr_sel;
3921
3922         do {
3923                 /* for peer attributes we retry upon failure */
3924                 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3925                 if (ret)
3926                         dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3927                                 get, UIC_GET_ATTR_ID(attr_sel), ret);
3928         } while (ret && peer && --retries);
3929
3930         if (ret)
3931                 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
3932                         get, UIC_GET_ATTR_ID(attr_sel),
3933                         UFS_UIC_COMMAND_RETRIES - retries);
3934
3935         if (mib_val && !ret)
3936                 *mib_val = uic_cmd.argument3;
3937
3938         if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3939             && pwr_mode_change)
3940                 ufshcd_change_power_mode(hba, &orig_pwr_info);
3941 out:
3942         return ret;
3943 }
3944 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3945
3946 /**
3947  * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3948  * state) and waits for it to take effect.
3949  *
3950  * @hba: per adapter instance
3951  * @cmd: UIC command to execute
3952  *
3953  * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3954  * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3955  * and device UniPro link and hence it's final completion would be indicated by
3956  * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3957  * addition to normal UIC command completion Status (UCCS). This function only
3958  * returns after the relevant status bits indicate the completion.
3959  *
3960  * Returns 0 on success, non-zero value on failure
3961  */
3962 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
3963 {
3964         struct completion uic_async_done;
3965         unsigned long flags;
3966         u8 status;
3967         int ret;
3968         bool reenable_intr = false;
3969
3970         mutex_lock(&hba->uic_cmd_mutex);
3971         init_completion(&uic_async_done);
3972         ufshcd_add_delay_before_dme_cmd(hba);
3973
3974         spin_lock_irqsave(hba->host->host_lock, flags);
3975         if (ufshcd_is_link_broken(hba)) {
3976                 ret = -ENOLINK;
3977                 goto out_unlock;
3978         }
3979         hba->uic_async_done = &uic_async_done;
3980         if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3981                 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3982                 /*
3983                  * Make sure UIC command completion interrupt is disabled before
3984                  * issuing UIC command.
3985                  */
3986                 wmb();
3987                 reenable_intr = true;
3988         }
3989         ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3990         spin_unlock_irqrestore(hba->host->host_lock, flags);
3991         if (ret) {
3992                 dev_err(hba->dev,
3993                         "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3994                         cmd->command, cmd->argument3, ret);
3995                 goto out;
3996         }
3997
3998         if (!wait_for_completion_timeout(hba->uic_async_done,
3999                                          msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
4000                 dev_err(hba->dev,
4001                         "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
4002                         cmd->command, cmd->argument3);
4003
4004                 if (!cmd->cmd_active) {
4005                         dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n",
4006                                 __func__);
4007                         goto check_upmcrs;
4008                 }
4009
4010                 ret = -ETIMEDOUT;
4011                 goto out;
4012         }
4013
4014 check_upmcrs:
4015         status = ufshcd_get_upmcrs(hba);
4016         if (status != PWR_LOCAL) {
4017                 dev_err(hba->dev,
4018                         "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
4019                         cmd->command, status);
4020                 ret = (status != PWR_OK) ? status : -1;
4021         }
4022 out:
4023         if (ret) {
4024                 ufshcd_print_host_state(hba);
4025                 ufshcd_print_pwr_info(hba);
4026                 ufshcd_print_evt_hist(hba);
4027         }
4028
4029         spin_lock_irqsave(hba->host->host_lock, flags);
4030         hba->active_uic_cmd = NULL;
4031         hba->uic_async_done = NULL;
4032         if (reenable_intr)
4033                 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
4034         if (ret) {
4035                 ufshcd_set_link_broken(hba);
4036                 ufshcd_schedule_eh_work(hba);
4037         }
4038 out_unlock:
4039         spin_unlock_irqrestore(hba->host->host_lock, flags);
4040         mutex_unlock(&hba->uic_cmd_mutex);
4041
4042         return ret;
4043 }
4044
4045 /**
4046  * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
4047  *                              using DME_SET primitives.
4048  * @hba: per adapter instance
4049  * @mode: powr mode value
4050  *
4051  * Returns 0 on success, non-zero value on failure
4052  */
4053 static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
4054 {
4055         struct uic_command uic_cmd = {0};
4056         int ret;
4057
4058         if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
4059                 ret = ufshcd_dme_set(hba,
4060                                 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
4061                 if (ret) {
4062                         dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
4063                                                 __func__, ret);
4064                         goto out;
4065                 }
4066         }
4067
4068         uic_cmd.command = UIC_CMD_DME_SET;
4069         uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
4070         uic_cmd.argument3 = mode;
4071         ufshcd_hold(hba, false);
4072         ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4073         ufshcd_release(hba);
4074
4075 out:
4076         return ret;
4077 }
4078
4079 int ufshcd_link_recovery(struct ufs_hba *hba)
4080 {
4081         int ret;
4082         unsigned long flags;
4083
4084         spin_lock_irqsave(hba->host->host_lock, flags);
4085         hba->ufshcd_state = UFSHCD_STATE_RESET;
4086         ufshcd_set_eh_in_progress(hba);
4087         spin_unlock_irqrestore(hba->host->host_lock, flags);
4088
4089         /* Reset the attached device */
4090         ufshcd_device_reset(hba);
4091
4092         ret = ufshcd_host_reset_and_restore(hba);
4093
4094         spin_lock_irqsave(hba->host->host_lock, flags);
4095         if (ret)
4096                 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4097         ufshcd_clear_eh_in_progress(hba);
4098         spin_unlock_irqrestore(hba->host->host_lock, flags);
4099
4100         if (ret)
4101                 dev_err(hba->dev, "%s: link recovery failed, err %d",
4102                         __func__, ret);
4103         else
4104                 ufshcd_clear_ua_wluns(hba);
4105
4106         return ret;
4107 }
4108 EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
4109
4110 static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
4111 {
4112         int ret;
4113         struct uic_command uic_cmd = {0};
4114         ktime_t start = ktime_get();
4115
4116         ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
4117
4118         uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
4119         ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4120         trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
4121                              ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4122
4123         if (ret)
4124                 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
4125                         __func__, ret);
4126         else
4127                 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
4128                                                                 POST_CHANGE);
4129
4130         return ret;
4131 }
4132
4133 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
4134 {
4135         struct uic_command uic_cmd = {0};
4136         int ret;
4137         ktime_t start = ktime_get();
4138
4139         ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
4140
4141         uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
4142         ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4143         trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
4144                              ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4145
4146         if (ret) {
4147                 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
4148                         __func__, ret);
4149         } else {
4150                 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
4151                                                                 POST_CHANGE);
4152                 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
4153                 hba->ufs_stats.hibern8_exit_cnt++;
4154         }
4155
4156         return ret;
4157 }
4158 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit);
4159
4160 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
4161 {
4162         unsigned long flags;
4163         bool update = false;
4164
4165         if (!ufshcd_is_auto_hibern8_supported(hba))
4166                 return;
4167
4168         spin_lock_irqsave(hba->host->host_lock, flags);
4169         if (hba->ahit != ahit) {
4170                 hba->ahit = ahit;
4171                 update = true;
4172         }
4173         spin_unlock_irqrestore(hba->host->host_lock, flags);
4174
4175         if (update &&
4176             !pm_runtime_suspended(&hba->sdev_ufs_device->sdev_gendev)) {
4177                 ufshcd_rpm_get_sync(hba);
4178                 ufshcd_hold(hba, false);
4179                 ufshcd_auto_hibern8_enable(hba);
4180                 ufshcd_release(hba);
4181                 ufshcd_rpm_put_sync(hba);
4182         }
4183 }
4184 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
4185
4186 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
4187 {
4188         unsigned long flags;
4189
4190         if (!ufshcd_is_auto_hibern8_supported(hba))
4191                 return;
4192
4193         spin_lock_irqsave(hba->host->host_lock, flags);
4194         ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
4195         spin_unlock_irqrestore(hba->host->host_lock, flags);
4196 }
4197
4198  /**
4199  * ufshcd_init_pwr_info - setting the POR (power on reset)
4200  * values in hba power info
4201  * @hba: per-adapter instance
4202  */
4203 static void ufshcd_init_pwr_info(struct ufs_hba *hba)
4204 {
4205         hba->pwr_info.gear_rx = UFS_PWM_G1;
4206         hba->pwr_info.gear_tx = UFS_PWM_G1;
4207         hba->pwr_info.lane_rx = 1;
4208         hba->pwr_info.lane_tx = 1;
4209         hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
4210         hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
4211         hba->pwr_info.hs_rate = 0;
4212 }
4213
4214 /**
4215  * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
4216  * @hba: per-adapter instance
4217  */
4218 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
4219 {
4220         struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
4221
4222         if (hba->max_pwr_info.is_valid)
4223                 return 0;
4224
4225         pwr_info->pwr_tx = FAST_MODE;
4226         pwr_info->pwr_rx = FAST_MODE;
4227         pwr_info->hs_rate = PA_HS_MODE_B;
4228
4229         /* Get the connected lane count */
4230         ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
4231                         &pwr_info->lane_rx);
4232         ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4233                         &pwr_info->lane_tx);
4234
4235         if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
4236                 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
4237                                 __func__,
4238                                 pwr_info->lane_rx,
4239                                 pwr_info->lane_tx);
4240                 return -EINVAL;
4241         }
4242
4243         /*
4244          * First, get the maximum gears of HS speed.
4245          * If a zero value, it means there is no HSGEAR capability.
4246          * Then, get the maximum gears of PWM speed.
4247          */
4248         ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
4249         if (!pwr_info->gear_rx) {
4250                 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4251                                 &pwr_info->gear_rx);
4252                 if (!pwr_info->gear_rx) {
4253                         dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
4254                                 __func__, pwr_info->gear_rx);
4255                         return -EINVAL;
4256                 }
4257                 pwr_info->pwr_rx = SLOW_MODE;
4258         }
4259
4260         ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
4261                         &pwr_info->gear_tx);
4262         if (!pwr_info->gear_tx) {
4263                 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4264                                 &pwr_info->gear_tx);
4265                 if (!pwr_info->gear_tx) {
4266                         dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
4267                                 __func__, pwr_info->gear_tx);
4268                         return -EINVAL;
4269                 }
4270                 pwr_info->pwr_tx = SLOW_MODE;
4271         }
4272
4273         hba->max_pwr_info.is_valid = true;
4274         return 0;
4275 }
4276
4277 static int ufshcd_change_power_mode(struct ufs_hba *hba,
4278                              struct ufs_pa_layer_attr *pwr_mode)
4279 {
4280         int ret;
4281
4282         /* if already configured to the requested pwr_mode */
4283         if (!hba->force_pmc &&
4284             pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
4285             pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4286             pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4287             pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4288             pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4289             pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4290             pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4291                 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4292                 return 0;
4293         }
4294
4295         /*
4296          * Configure attributes for power mode change with below.
4297          * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4298          * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4299          * - PA_HSSERIES
4300          */
4301         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4302         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4303                         pwr_mode->lane_rx);
4304         if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4305                         pwr_mode->pwr_rx == FAST_MODE)
4306                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
4307         else
4308                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
4309
4310         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4311         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4312                         pwr_mode->lane_tx);
4313         if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4314                         pwr_mode->pwr_tx == FAST_MODE)
4315                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
4316         else
4317                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
4318
4319         if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4320             pwr_mode->pwr_tx == FASTAUTO_MODE ||
4321             pwr_mode->pwr_rx == FAST_MODE ||
4322             pwr_mode->pwr_tx == FAST_MODE)
4323                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4324                                                 pwr_mode->hs_rate);
4325
4326         if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) {
4327                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
4328                                 DL_FC0ProtectionTimeOutVal_Default);
4329                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
4330                                 DL_TC0ReplayTimeOutVal_Default);
4331                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
4332                                 DL_AFC0ReqTimeOutVal_Default);
4333                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
4334                                 DL_FC1ProtectionTimeOutVal_Default);
4335                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
4336                                 DL_TC1ReplayTimeOutVal_Default);
4337                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
4338                                 DL_AFC1ReqTimeOutVal_Default);
4339
4340                 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
4341                                 DL_FC0ProtectionTimeOutVal_Default);
4342                 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
4343                                 DL_TC0ReplayTimeOutVal_Default);
4344                 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
4345                                 DL_AFC0ReqTimeOutVal_Default);
4346         }
4347
4348         ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4349                         | pwr_mode->pwr_tx);
4350
4351         if (ret) {
4352                 dev_err(hba->dev,
4353                         "%s: power mode change failed %d\n", __func__, ret);
4354         } else {
4355                 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4356                                                                 pwr_mode);
4357
4358                 memcpy(&hba->pwr_info, pwr_mode,
4359                         sizeof(struct ufs_pa_layer_attr));
4360         }
4361
4362         return ret;
4363 }
4364
4365 /**
4366  * ufshcd_config_pwr_mode - configure a new power mode
4367  * @hba: per-adapter instance
4368  * @desired_pwr_mode: desired power configuration
4369  */
4370 int ufshcd_config_pwr_mode(struct ufs_hba *hba,
4371                 struct ufs_pa_layer_attr *desired_pwr_mode)
4372 {
4373         struct ufs_pa_layer_attr final_params = { 0 };
4374         int ret;
4375
4376         ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4377                                         desired_pwr_mode, &final_params);
4378
4379         if (ret)
4380                 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4381
4382         ret = ufshcd_change_power_mode(hba, &final_params);
4383
4384         return ret;
4385 }
4386 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
4387
4388 /**
4389  * ufshcd_complete_dev_init() - checks device readiness
4390  * @hba: per-adapter instance
4391  *
4392  * Set fDeviceInit flag and poll until device toggles it.
4393  */
4394 static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4395 {
4396         int err;
4397         bool flag_res = true;
4398         ktime_t timeout;
4399
4400         err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4401                 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL);
4402         if (err) {
4403                 dev_err(hba->dev,
4404                         "%s setting fDeviceInit flag failed with error %d\n",
4405                         __func__, err);
4406                 goto out;
4407         }
4408
4409         /* Poll fDeviceInit flag to be cleared */
4410         timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT);
4411         do {
4412                 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4413                                         QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res);
4414                 if (!flag_res)
4415                         break;
4416                 usleep_range(5000, 10000);
4417         } while (ktime_before(ktime_get(), timeout));
4418
4419         if (err) {
4420                 dev_err(hba->dev,
4421                                 "%s reading fDeviceInit flag failed with error %d\n",
4422                                 __func__, err);
4423         } else if (flag_res) {
4424                 dev_err(hba->dev,
4425                                 "%s fDeviceInit was not cleared by the device\n",
4426                                 __func__);
4427                 err = -EBUSY;
4428         }
4429 out:
4430         return err;
4431 }
4432
4433 /**
4434  * ufshcd_make_hba_operational - Make UFS controller operational
4435  * @hba: per adapter instance
4436  *
4437  * To bring UFS host controller to operational state,
4438  * 1. Enable required interrupts
4439  * 2. Configure interrupt aggregation
4440  * 3. Program UTRL and UTMRL base address
4441  * 4. Configure run-stop-registers
4442  *
4443  * Returns 0 on success, non-zero value on failure
4444  */
4445 int ufshcd_make_hba_operational(struct ufs_hba *hba)
4446 {
4447         int err = 0;
4448         u32 reg;
4449
4450         /* Enable required interrupts */
4451         ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4452
4453         /* Configure interrupt aggregation */
4454         if (ufshcd_is_intr_aggr_allowed(hba))
4455                 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4456         else
4457                 ufshcd_disable_intr_aggr(hba);
4458
4459         /* Configure UTRL and UTMRL base address registers */
4460         ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4461                         REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4462         ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4463                         REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4464         ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4465                         REG_UTP_TASK_REQ_LIST_BASE_L);
4466         ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4467                         REG_UTP_TASK_REQ_LIST_BASE_H);
4468
4469         /*
4470          * Make sure base address and interrupt setup are updated before
4471          * enabling the run/stop registers below.
4472          */
4473         wmb();
4474
4475         /*
4476          * UCRDY, UTMRLDY and UTRLRDY bits must be 1
4477          */
4478         reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
4479         if (!(ufshcd_get_lists_status(reg))) {
4480                 ufshcd_enable_run_stop_reg(hba);
4481         } else {
4482                 dev_err(hba->dev,
4483                         "Host controller not ready to process requests");
4484                 err = -EIO;
4485         }
4486
4487         return err;
4488 }
4489 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational);
4490
4491 /**
4492  * ufshcd_hba_stop - Send controller to reset state
4493  * @hba: per adapter instance
4494  */
4495 void ufshcd_hba_stop(struct ufs_hba *hba)
4496 {
4497         unsigned long flags;
4498         int err;
4499
4500         /*
4501          * Obtain the host lock to prevent that the controller is disabled
4502          * while the UFS interrupt handler is active on another CPU.
4503          */
4504         spin_lock_irqsave(hba->host->host_lock, flags);
4505         ufshcd_writel(hba, CONTROLLER_DISABLE,  REG_CONTROLLER_ENABLE);
4506         spin_unlock_irqrestore(hba->host->host_lock, flags);
4507
4508         err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4509                                         CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4510                                         10, 1);
4511         if (err)
4512                 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4513 }
4514 EXPORT_SYMBOL_GPL(ufshcd_hba_stop);
4515
4516 /**
4517  * ufshcd_hba_execute_hce - initialize the controller
4518  * @hba: per adapter instance
4519  *
4520  * The controller resets itself and controller firmware initialization
4521  * sequence kicks off. When controller is ready it will set
4522  * the Host Controller Enable bit to 1.
4523  *
4524  * Returns 0 on success, non-zero value on failure
4525  */
4526 static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
4527 {
4528         int retry_outer = 3;
4529         int retry_inner;
4530
4531 start:
4532         if (!ufshcd_is_hba_active(hba))
4533                 /* change controller state to "reset state" */
4534                 ufshcd_hba_stop(hba);
4535
4536         /* UniPro link is disabled at this point */
4537         ufshcd_set_link_off(hba);
4538
4539         ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4540
4541         /* start controller initialization sequence */
4542         ufshcd_hba_start(hba);
4543
4544         /*
4545          * To initialize a UFS host controller HCE bit must be set to 1.
4546          * During initialization the HCE bit value changes from 1->0->1.
4547          * When the host controller completes initialization sequence
4548          * it sets the value of HCE bit to 1. The same HCE bit is read back
4549          * to check if the controller has completed initialization sequence.
4550          * So without this delay the value HCE = 1, set in the previous
4551          * instruction might be read back.
4552          * This delay can be changed based on the controller.
4553          */
4554         ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100);
4555
4556         /* wait for the host controller to complete initialization */
4557         retry_inner = 50;
4558         while (ufshcd_is_hba_active(hba)) {
4559                 if (retry_inner) {
4560                         retry_inner--;
4561                 } else {
4562                         dev_err(hba->dev,
4563                                 "Controller enable failed\n");
4564                         if (retry_outer) {
4565                                 retry_outer--;
4566                                 goto start;
4567                         }
4568                         return -EIO;
4569                 }
4570                 usleep_range(1000, 1100);
4571         }
4572
4573         /* enable UIC related interrupts */
4574         ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4575
4576         ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4577
4578         return 0;
4579 }
4580
4581 int ufshcd_hba_enable(struct ufs_hba *hba)
4582 {
4583         int ret;
4584
4585         if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4586                 ufshcd_set_link_off(hba);
4587                 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4588
4589                 /* enable UIC related interrupts */
4590                 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4591                 ret = ufshcd_dme_reset(hba);
4592                 if (!ret) {
4593                         ret = ufshcd_dme_enable(hba);
4594                         if (!ret)
4595                                 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4596                         if (ret)
4597                                 dev_err(hba->dev,
4598                                         "Host controller enable failed with non-hce\n");
4599                 }
4600         } else {
4601                 ret = ufshcd_hba_execute_hce(hba);
4602         }
4603
4604         return ret;
4605 }
4606 EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
4607
4608 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4609 {
4610         int tx_lanes = 0, i, err = 0;
4611
4612         if (!peer)
4613                 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4614                                &tx_lanes);
4615         else
4616                 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4617                                     &tx_lanes);
4618         for (i = 0; i < tx_lanes; i++) {
4619                 if (!peer)
4620                         err = ufshcd_dme_set(hba,
4621                                 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4622                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4623                                         0);
4624                 else
4625                         err = ufshcd_dme_peer_set(hba,
4626                                 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4627                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4628                                         0);
4629                 if (err) {
4630                         dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4631                                 __func__, peer, i, err);
4632                         break;
4633                 }
4634         }
4635
4636         return err;
4637 }
4638
4639 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4640 {
4641         return ufshcd_disable_tx_lcc(hba, true);
4642 }
4643
4644 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val)
4645 {
4646         struct ufs_event_hist *e;
4647
4648         if (id >= UFS_EVT_CNT)
4649                 return;
4650
4651         e = &hba->ufs_stats.event[id];
4652         e->val[e->pos] = val;
4653         e->tstamp[e->pos] = ktime_get();
4654         e->cnt += 1;
4655         e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH;
4656
4657         ufshcd_vops_event_notify(hba, id, &val);
4658 }
4659 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist);
4660
4661 /**
4662  * ufshcd_link_startup - Initialize unipro link startup
4663  * @hba: per adapter instance
4664  *
4665  * Returns 0 for success, non-zero in case of failure
4666  */
4667 static int ufshcd_link_startup(struct ufs_hba *hba)
4668 {
4669         int ret;
4670         int retries = DME_LINKSTARTUP_RETRIES;
4671         bool link_startup_again = false;
4672
4673         /*
4674          * If UFS device isn't active then we will have to issue link startup
4675          * 2 times to make sure the device state move to active.
4676          */
4677         if (!ufshcd_is_ufs_dev_active(hba))
4678                 link_startup_again = true;
4679
4680 link_startup:
4681         do {
4682                 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
4683
4684                 ret = ufshcd_dme_link_startup(hba);
4685
4686                 /* check if device is detected by inter-connect layer */
4687                 if (!ret && !ufshcd_is_device_present(hba)) {
4688                         ufshcd_update_evt_hist(hba,
4689                                                UFS_EVT_LINK_STARTUP_FAIL,
4690                                                0);
4691                         dev_err(hba->dev, "%s: Device not present\n", __func__);
4692                         ret = -ENXIO;
4693                         goto out;
4694                 }
4695
4696                 /*
4697                  * DME link lost indication is only received when link is up,
4698                  * but we can't be sure if the link is up until link startup
4699                  * succeeds. So reset the local Uni-Pro and try again.
4700                  */
4701                 if (ret && ufshcd_hba_enable(hba)) {
4702                         ufshcd_update_evt_hist(hba,
4703                                                UFS_EVT_LINK_STARTUP_FAIL,
4704                                                (u32)ret);
4705                         goto out;
4706                 }
4707         } while (ret && retries--);
4708
4709         if (ret) {
4710                 /* failed to get the link up... retire */
4711                 ufshcd_update_evt_hist(hba,
4712                                        UFS_EVT_LINK_STARTUP_FAIL,
4713                                        (u32)ret);
4714                 goto out;
4715         }
4716
4717         if (link_startup_again) {
4718                 link_startup_again = false;
4719                 retries = DME_LINKSTARTUP_RETRIES;
4720                 goto link_startup;
4721         }
4722
4723         /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4724         ufshcd_init_pwr_info(hba);
4725         ufshcd_print_pwr_info(hba);
4726
4727         if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4728                 ret = ufshcd_disable_device_tx_lcc(hba);
4729                 if (ret)
4730                         goto out;
4731         }
4732
4733         /* Include any host controller configuration via UIC commands */
4734         ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4735         if (ret)
4736                 goto out;
4737
4738         /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */
4739         ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
4740         ret = ufshcd_make_hba_operational(hba);
4741 out:
4742         if (ret) {
4743                 dev_err(hba->dev, "link startup failed %d\n", ret);
4744                 ufshcd_print_host_state(hba);
4745                 ufshcd_print_pwr_info(hba);
4746                 ufshcd_print_evt_hist(hba);
4747         }
4748         return ret;
4749 }
4750
4751 /**
4752  * ufshcd_verify_dev_init() - Verify device initialization
4753  * @hba: per-adapter instance
4754  *
4755  * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4756  * device Transport Protocol (UTP) layer is ready after a reset.
4757  * If the UTP layer at the device side is not initialized, it may
4758  * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4759  * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4760  */
4761 static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4762 {
4763         int err = 0;
4764         int retries;
4765
4766         ufshcd_hold(hba, false);
4767         mutex_lock(&hba->dev_cmd.lock);
4768         for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4769                 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4770                                                NOP_OUT_TIMEOUT);
4771
4772                 if (!err || err == -ETIMEDOUT)
4773                         break;
4774
4775                 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4776         }
4777         mutex_unlock(&hba->dev_cmd.lock);
4778         ufshcd_release(hba);
4779
4780         if (err)
4781                 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4782         return err;
4783 }
4784
4785 /**
4786  * ufshcd_set_queue_depth - set lun queue depth
4787  * @sdev: pointer to SCSI device
4788  *
4789  * Read bLUQueueDepth value and activate scsi tagged command
4790  * queueing. For WLUN, queue depth is set to 1. For best-effort
4791  * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4792  * value that host can queue.
4793  */
4794 static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4795 {
4796         int ret = 0;
4797         u8 lun_qdepth;
4798         struct ufs_hba *hba;
4799
4800         hba = shost_priv(sdev->host);
4801
4802         lun_qdepth = hba->nutrs;
4803         ret = ufshcd_read_unit_desc_param(hba,
4804                                           ufshcd_scsi_to_upiu_lun(sdev->lun),
4805                                           UNIT_DESC_PARAM_LU_Q_DEPTH,
4806                                           &lun_qdepth,
4807                                           sizeof(lun_qdepth));
4808
4809         /* Some WLUN doesn't support unit descriptor */
4810         if (ret == -EOPNOTSUPP)
4811                 lun_qdepth = 1;
4812         else if (!lun_qdepth)
4813                 /* eventually, we can figure out the real queue depth */
4814                 lun_qdepth = hba->nutrs;
4815         else
4816                 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4817
4818         dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4819                         __func__, lun_qdepth);
4820         scsi_change_queue_depth(sdev, lun_qdepth);
4821 }
4822
4823 /*
4824  * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4825  * @hba: per-adapter instance
4826  * @lun: UFS device lun id
4827  * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4828  *
4829  * Returns 0 in case of success and b_lu_write_protect status would be returned
4830  * @b_lu_write_protect parameter.
4831  * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4832  * Returns -EINVAL in case of invalid parameters passed to this function.
4833  */
4834 static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4835                             u8 lun,
4836                             u8 *b_lu_write_protect)
4837 {
4838         int ret;
4839
4840         if (!b_lu_write_protect)
4841                 ret = -EINVAL;
4842         /*
4843          * According to UFS device spec, RPMB LU can't be write
4844          * protected so skip reading bLUWriteProtect parameter for
4845          * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4846          */
4847         else if (lun >= hba->dev_info.max_lu_supported)
4848                 ret = -ENOTSUPP;
4849         else
4850                 ret = ufshcd_read_unit_desc_param(hba,
4851                                           lun,
4852                                           UNIT_DESC_PARAM_LU_WR_PROTECT,
4853                                           b_lu_write_protect,
4854                                           sizeof(*b_lu_write_protect));
4855         return ret;
4856 }
4857
4858 /**
4859  * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4860  * status
4861  * @hba: per-adapter instance
4862  * @sdev: pointer to SCSI device
4863  *
4864  */
4865 static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4866                                                     struct scsi_device *sdev)
4867 {
4868         if (hba->dev_info.f_power_on_wp_en &&
4869             !hba->dev_info.is_lu_power_on_wp) {
4870                 u8 b_lu_write_protect;
4871
4872                 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4873                                       &b_lu_write_protect) &&
4874                     (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4875                         hba->dev_info.is_lu_power_on_wp = true;
4876         }
4877 }
4878
4879 /**
4880  * ufshcd_setup_links - associate link b/w device wlun and other luns
4881  * @sdev: pointer to SCSI device
4882  * @hba: pointer to ufs hba
4883  */
4884 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev)
4885 {
4886         struct device_link *link;
4887
4888         /*
4889          * Device wlun is the supplier & rest of the luns are consumers.
4890          * This ensures that device wlun suspends after all other luns.
4891          */
4892         if (hba->sdev_ufs_device) {
4893                 link = device_link_add(&sdev->sdev_gendev,
4894                                        &hba->sdev_ufs_device->sdev_gendev,
4895                                        DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
4896                 if (!link) {
4897                         dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n",
4898                                 dev_name(&hba->sdev_ufs_device->sdev_gendev));
4899                         return;
4900                 }
4901                 hba->luns_avail--;
4902                 /* Ignore REPORT_LUN wlun probing */
4903                 if (hba->luns_avail == 1) {
4904                         ufshcd_rpm_put(hba);
4905                         return;
4906                 }
4907         } else {
4908                 /*
4909                  * Device wlun is probed. The assumption is that WLUNs are
4910                  * scanned before other LUNs.
4911                  */
4912                 hba->luns_avail--;
4913         }
4914 }
4915
4916 /**
4917  * ufshcd_slave_alloc - handle initial SCSI device configurations
4918  * @sdev: pointer to SCSI device
4919  *
4920  * Returns success
4921  */
4922 static int ufshcd_slave_alloc(struct scsi_device *sdev)
4923 {
4924         struct ufs_hba *hba;
4925
4926         hba = shost_priv(sdev->host);
4927
4928         /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4929         sdev->use_10_for_ms = 1;
4930
4931         /* DBD field should be set to 1 in mode sense(10) */
4932         sdev->set_dbd_for_ms = 1;
4933
4934         /* allow SCSI layer to restart the device in case of errors */
4935         sdev->allow_restart = 1;
4936
4937         /* REPORT SUPPORTED OPERATION CODES is not supported */
4938         sdev->no_report_opcodes = 1;
4939
4940         /* WRITE_SAME command is not supported */
4941         sdev->no_write_same = 1;
4942
4943         ufshcd_set_queue_depth(sdev);
4944
4945         ufshcd_get_lu_power_on_wp_status(hba, sdev);
4946
4947         ufshcd_setup_links(hba, sdev);
4948
4949         return 0;
4950 }
4951
4952 /**
4953  * ufshcd_change_queue_depth - change queue depth
4954  * @sdev: pointer to SCSI device
4955  * @depth: required depth to set
4956  *
4957  * Change queue depth and make sure the max. limits are not crossed.
4958  */
4959 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4960 {
4961         struct ufs_hba *hba = shost_priv(sdev->host);
4962
4963         if (depth > hba->nutrs)
4964                 depth = hba->nutrs;
4965         return scsi_change_queue_depth(sdev, depth);
4966 }
4967
4968 /**
4969  * ufshcd_slave_configure - adjust SCSI device configurations
4970  * @sdev: pointer to SCSI device
4971  */
4972 static int ufshcd_slave_configure(struct scsi_device *sdev)
4973 {
4974         struct ufs_hba *hba = shost_priv(sdev->host);
4975         struct request_queue *q = sdev->request_queue;
4976
4977         blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
4978         if (hba->quirks & UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE)
4979                 blk_queue_update_dma_alignment(q, PAGE_SIZE - 1);
4980         /*
4981          * Block runtime-pm until all consumers are added.
4982          * Refer ufshcd_setup_links().
4983          */
4984         if (is_device_wlun(sdev))
4985                 pm_runtime_get_noresume(&sdev->sdev_gendev);
4986         else if (ufshcd_is_rpm_autosuspend_allowed(hba))
4987                 sdev->rpm_autosuspend = 1;
4988
4989         ufshcd_crypto_setup_rq_keyslot_manager(hba, q);
4990
4991         return 0;
4992 }
4993
4994 /**
4995  * ufshcd_slave_destroy - remove SCSI device configurations
4996  * @sdev: pointer to SCSI device
4997  */
4998 static void ufshcd_slave_destroy(struct scsi_device *sdev)
4999 {
5000         struct ufs_hba *hba;
5001
5002         hba = shost_priv(sdev->host);
5003         /* Drop the reference as it won't be needed anymore */
5004         if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
5005                 unsigned long flags;
5006
5007                 spin_lock_irqsave(hba->host->host_lock, flags);
5008                 hba->sdev_ufs_device = NULL;
5009                 spin_unlock_irqrestore(hba->host->host_lock, flags);
5010         }
5011 }
5012
5013 /**
5014  * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
5015  * @lrbp: pointer to local reference block of completed command
5016  * @scsi_status: SCSI command status
5017  *
5018  * Returns value base on SCSI command status
5019  */
5020 static inline int
5021 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
5022 {
5023         int result = 0;
5024
5025         switch (scsi_status) {
5026         case SAM_STAT_CHECK_CONDITION:
5027                 ufshcd_copy_sense_data(lrbp);
5028                 fallthrough;
5029         case SAM_STAT_GOOD:
5030                 result |= DID_OK << 16 | scsi_status;
5031                 break;
5032         case SAM_STAT_TASK_SET_FULL:
5033         case SAM_STAT_BUSY:
5034         case SAM_STAT_TASK_ABORTED:
5035                 ufshcd_copy_sense_data(lrbp);
5036                 result |= scsi_status;
5037                 break;
5038         default:
5039                 result |= DID_ERROR << 16;
5040                 break;
5041         } /* end of switch */
5042
5043         return result;
5044 }
5045
5046 /**
5047  * ufshcd_transfer_rsp_status - Get overall status of the response
5048  * @hba: per adapter instance
5049  * @lrbp: pointer to local reference block of completed command
5050  *
5051  * Returns result of the command to notify SCSI midlayer
5052  */
5053 static inline int
5054 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
5055 {
5056         int result = 0;
5057         int scsi_status;
5058         int ocs;
5059
5060         /* overall command status of utrd */
5061         ocs = ufshcd_get_tr_ocs(lrbp);
5062
5063         if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) {
5064                 if (be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_1) &
5065                                         MASK_RSP_UPIU_RESULT)
5066                         ocs = OCS_SUCCESS;
5067         }
5068
5069         switch (ocs) {
5070         case OCS_SUCCESS:
5071                 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
5072                 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5073                 switch (result) {
5074                 case UPIU_TRANSACTION_RESPONSE:
5075                         /*
5076                          * get the response UPIU result to extract
5077                          * the SCSI command status
5078                          */
5079                         result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
5080
5081                         /*
5082                          * get the result based on SCSI status response
5083                          * to notify the SCSI midlayer of the command status
5084                          */
5085                         scsi_status = result & MASK_SCSI_STATUS;
5086                         result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
5087
5088                         /*
5089                          * Currently we are only supporting BKOPs exception
5090                          * events hence we can ignore BKOPs exception event
5091                          * during power management callbacks. BKOPs exception
5092                          * event is not expected to be raised in runtime suspend
5093                          * callback as it allows the urgent bkops.
5094                          * During system suspend, we are anyway forcefully
5095                          * disabling the bkops and if urgent bkops is needed
5096                          * it will be enabled on system resume. Long term
5097                          * solution could be to abort the system suspend if
5098                          * UFS device needs urgent BKOPs.
5099                          */
5100                         if (!hba->pm_op_in_progress &&
5101                             !ufshcd_eh_in_progress(hba) &&
5102                             ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
5103                                 /* Flushed in suspend */
5104                                 schedule_work(&hba->eeh_work);
5105                         break;
5106                 case UPIU_TRANSACTION_REJECT_UPIU:
5107                         /* TODO: handle Reject UPIU Response */
5108                         result = DID_ERROR << 16;
5109                         dev_err(hba->dev,
5110                                 "Reject UPIU not fully implemented\n");
5111                         break;
5112                 default:
5113                         dev_err(hba->dev,
5114                                 "Unexpected request response code = %x\n",
5115                                 result);
5116                         result = DID_ERROR << 16;
5117                         break;
5118                 }
5119                 break;
5120         case OCS_ABORTED:
5121                 result |= DID_ABORT << 16;
5122                 break;
5123         case OCS_INVALID_COMMAND_STATUS:
5124                 result |= DID_REQUEUE << 16;
5125                 break;
5126         case OCS_INVALID_CMD_TABLE_ATTR:
5127         case OCS_INVALID_PRDT_ATTR:
5128         case OCS_MISMATCH_DATA_BUF_SIZE:
5129         case OCS_MISMATCH_RESP_UPIU_SIZE:
5130         case OCS_PEER_COMM_FAILURE:
5131         case OCS_FATAL_ERROR:
5132         case OCS_DEVICE_FATAL_ERROR:
5133         case OCS_INVALID_CRYPTO_CONFIG:
5134         case OCS_GENERAL_CRYPTO_ERROR:
5135         default:
5136                 result |= DID_ERROR << 16;
5137                 dev_err(hba->dev,
5138                                 "OCS error from controller = %x for tag %d\n",
5139                                 ocs, lrbp->task_tag);
5140                 ufshcd_print_evt_hist(hba);
5141                 ufshcd_print_host_state(hba);
5142                 break;
5143         } /* end of switch */
5144
5145         if ((host_byte(result) != DID_OK) &&
5146             (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs)
5147                 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
5148         return result;
5149 }
5150
5151 /**
5152  * ufshcd_uic_cmd_compl - handle completion of uic command
5153  * @hba: per adapter instance
5154  * @intr_status: interrupt status generated by the controller
5155  *
5156  * Returns
5157  *  IRQ_HANDLED - If interrupt is valid
5158  *  IRQ_NONE    - If invalid interrupt
5159  */
5160 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
5161 {
5162         irqreturn_t retval = IRQ_NONE;
5163
5164         if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
5165                 hba->active_uic_cmd->argument2 |=
5166                         ufshcd_get_uic_cmd_result(hba);
5167                 hba->active_uic_cmd->argument3 =
5168                         ufshcd_get_dme_attr_val(hba);
5169                 if (!hba->uic_async_done)
5170                         hba->active_uic_cmd->cmd_active = 0;
5171                 complete(&hba->active_uic_cmd->done);
5172                 retval = IRQ_HANDLED;
5173         }
5174
5175         if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
5176                 hba->active_uic_cmd->cmd_active = 0;
5177                 complete(hba->uic_async_done);
5178                 retval = IRQ_HANDLED;
5179         }
5180
5181         if (retval == IRQ_HANDLED)
5182                 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd,
5183                                              UFS_CMD_COMP);
5184         return retval;
5185 }
5186
5187 /**
5188  * __ufshcd_transfer_req_compl - handle SCSI and query command completion
5189  * @hba: per adapter instance
5190  * @completed_reqs: requests to complete
5191  */
5192 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
5193                                         unsigned long completed_reqs)
5194 {
5195         struct ufshcd_lrb *lrbp;
5196         struct scsi_cmnd *cmd;
5197         int result;
5198         int index;
5199         bool update_scaling = false;
5200
5201         for_each_set_bit(index, &completed_reqs, hba->nutrs) {
5202                 lrbp = &hba->lrb[index];
5203                 lrbp->in_use = false;
5204                 lrbp->compl_time_stamp = ktime_get();
5205                 cmd = lrbp->cmd;
5206                 if (cmd) {
5207                         if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
5208                                 ufshcd_update_monitor(hba, lrbp);
5209                         ufshcd_add_command_trace(hba, index, UFS_CMD_COMP);
5210                         result = ufshcd_transfer_rsp_status(hba, lrbp);
5211                         scsi_dma_unmap(cmd);
5212                         cmd->result = result;
5213                         /* Mark completed command as NULL in LRB */
5214                         lrbp->cmd = NULL;
5215                         /* Do not touch lrbp after scsi done */
5216                         cmd->scsi_done(cmd);
5217                         __ufshcd_release(hba);
5218                         update_scaling = true;
5219                 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
5220                         lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
5221                         if (hba->dev_cmd.complete) {
5222                                 ufshcd_add_command_trace(hba, index,
5223                                                          UFS_DEV_COMP);
5224                                 complete(hba->dev_cmd.complete);
5225                                 update_scaling = true;
5226                         }
5227                 }
5228                 if (ufshcd_is_clkscaling_supported(hba) && update_scaling)
5229                         hba->clk_scaling.active_reqs--;
5230         }
5231
5232         /* clear corresponding bits of completed commands */
5233         hba->outstanding_reqs ^= completed_reqs;
5234
5235         ufshcd_clk_scaling_update_busy(hba);
5236 }
5237
5238 /**
5239  * ufshcd_transfer_req_compl - handle SCSI and query command completion
5240  * @hba: per adapter instance
5241  *
5242  * Returns
5243  *  IRQ_HANDLED - If interrupt is valid
5244  *  IRQ_NONE    - If invalid interrupt
5245  */
5246 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
5247 {
5248         unsigned long completed_reqs;
5249         u32 tr_doorbell;
5250
5251         /* Resetting interrupt aggregation counters first and reading the
5252          * DOOR_BELL afterward allows us to handle all the completed requests.
5253          * In order to prevent other interrupts starvation the DB is read once
5254          * after reset. The down side of this solution is the possibility of
5255          * false interrupt if device completes another request after resetting
5256          * aggregation and before reading the DB.
5257          */
5258         if (ufshcd_is_intr_aggr_allowed(hba) &&
5259             !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
5260                 ufshcd_reset_intr_aggr(hba);
5261
5262         tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5263         completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
5264
5265         if (completed_reqs) {
5266                 __ufshcd_transfer_req_compl(hba, completed_reqs);
5267                 return IRQ_HANDLED;
5268         } else {
5269                 return IRQ_NONE;
5270         }
5271 }
5272
5273 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask)
5274 {
5275         return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5276                                        QUERY_ATTR_IDN_EE_CONTROL, 0, 0,
5277                                        &ee_ctrl_mask);
5278 }
5279
5280 int ufshcd_write_ee_control(struct ufs_hba *hba)
5281 {
5282         int err;
5283
5284         mutex_lock(&hba->ee_ctrl_mutex);
5285         err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask);
5286         mutex_unlock(&hba->ee_ctrl_mutex);
5287         if (err)
5288                 dev_err(hba->dev, "%s: failed to write ee control %d\n",
5289                         __func__, err);
5290         return err;
5291 }
5292
5293 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, u16 *other_mask,
5294                              u16 set, u16 clr)
5295 {
5296         u16 new_mask, ee_ctrl_mask;
5297         int err = 0;
5298
5299         mutex_lock(&hba->ee_ctrl_mutex);
5300         new_mask = (*mask & ~clr) | set;
5301         ee_ctrl_mask = new_mask | *other_mask;
5302         if (ee_ctrl_mask != hba->ee_ctrl_mask)
5303                 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask);
5304         /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */
5305         if (!err) {
5306                 hba->ee_ctrl_mask = ee_ctrl_mask;
5307                 *mask = new_mask;
5308         }
5309         mutex_unlock(&hba->ee_ctrl_mutex);
5310         return err;
5311 }
5312
5313 /**
5314  * ufshcd_disable_ee - disable exception event
5315  * @hba: per-adapter instance
5316  * @mask: exception event to disable
5317  *
5318  * Disables exception event in the device so that the EVENT_ALERT
5319  * bit is not set.
5320  *
5321  * Returns zero on success, non-zero error value on failure.
5322  */
5323 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
5324 {
5325         return ufshcd_update_ee_drv_mask(hba, 0, mask);
5326 }
5327
5328 /**
5329  * ufshcd_enable_ee - enable exception event
5330  * @hba: per-adapter instance
5331  * @mask: exception event to enable
5332  *
5333  * Enable corresponding exception event in the device to allow
5334  * device to alert host in critical scenarios.
5335  *
5336  * Returns zero on success, non-zero error value on failure.
5337  */
5338 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
5339 {
5340         return ufshcd_update_ee_drv_mask(hba, mask, 0);
5341 }
5342
5343 /**
5344  * ufshcd_enable_auto_bkops - Allow device managed BKOPS
5345  * @hba: per-adapter instance
5346  *
5347  * Allow device to manage background operations on its own. Enabling
5348  * this might lead to inconsistent latencies during normal data transfers
5349  * as the device is allowed to manage its own way of handling background
5350  * operations.
5351  *
5352  * Returns zero on success, non-zero on failure.
5353  */
5354 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
5355 {
5356         int err = 0;
5357
5358         if (hba->auto_bkops_enabled)
5359                 goto out;
5360
5361         err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
5362                         QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5363         if (err) {
5364                 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
5365                                 __func__, err);
5366                 goto out;
5367         }
5368
5369         hba->auto_bkops_enabled = true;
5370         trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
5371
5372         /* No need of URGENT_BKOPS exception from the device */
5373         err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5374         if (err)
5375                 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
5376                                 __func__, err);
5377 out:
5378         return err;
5379 }
5380
5381 /**
5382  * ufshcd_disable_auto_bkops - block device in doing background operations
5383  * @hba: per-adapter instance
5384  *
5385  * Disabling background operations improves command response latency but
5386  * has drawback of device moving into critical state where the device is
5387  * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
5388  * host is idle so that BKOPS are managed effectively without any negative
5389  * impacts.
5390  *
5391  * Returns zero on success, non-zero on failure.
5392  */
5393 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5394 {
5395         int err = 0;
5396
5397         if (!hba->auto_bkops_enabled)
5398                 goto out;
5399
5400         /*
5401          * If host assisted BKOPs is to be enabled, make sure
5402          * urgent bkops exception is allowed.
5403          */
5404         err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5405         if (err) {
5406                 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5407                                 __func__, err);
5408                 goto out;
5409         }
5410
5411         err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
5412                         QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5413         if (err) {
5414                 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5415                                 __func__, err);
5416                 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5417                 goto out;
5418         }
5419
5420         hba->auto_bkops_enabled = false;
5421         trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
5422         hba->is_urgent_bkops_lvl_checked = false;
5423 out:
5424         return err;
5425 }
5426
5427 /**
5428  * ufshcd_force_reset_auto_bkops - force reset auto bkops state
5429  * @hba: per adapter instance
5430  *
5431  * After a device reset the device may toggle the BKOPS_EN flag
5432  * to default value. The s/w tracking variables should be updated
5433  * as well. This function would change the auto-bkops state based on
5434  * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
5435  */
5436 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
5437 {
5438         if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5439                 hba->auto_bkops_enabled = false;
5440                 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5441                 ufshcd_enable_auto_bkops(hba);
5442         } else {
5443                 hba->auto_bkops_enabled = true;
5444                 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5445                 ufshcd_disable_auto_bkops(hba);
5446         }
5447         hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
5448         hba->is_urgent_bkops_lvl_checked = false;
5449 }
5450
5451 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5452 {
5453         return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5454                         QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5455 }
5456
5457 /**
5458  * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
5459  * @hba: per-adapter instance
5460  * @status: bkops_status value
5461  *
5462  * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5463  * flag in the device to permit background operations if the device
5464  * bkops_status is greater than or equal to "status" argument passed to
5465  * this function, disable otherwise.
5466  *
5467  * Returns 0 for success, non-zero in case of failure.
5468  *
5469  * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5470  * to know whether auto bkops is enabled or disabled after this function
5471  * returns control to it.
5472  */
5473 static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5474                              enum bkops_status status)
5475 {
5476         int err;
5477         u32 curr_status = 0;
5478
5479         err = ufshcd_get_bkops_status(hba, &curr_status);
5480         if (err) {
5481                 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5482                                 __func__, err);
5483                 goto out;
5484         } else if (curr_status > BKOPS_STATUS_MAX) {
5485                 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5486                                 __func__, curr_status);
5487                 err = -EINVAL;
5488                 goto out;
5489         }
5490
5491         if (curr_status >= status)
5492                 err = ufshcd_enable_auto_bkops(hba);
5493         else
5494                 err = ufshcd_disable_auto_bkops(hba);
5495 out:
5496         return err;
5497 }
5498
5499 /**
5500  * ufshcd_urgent_bkops - handle urgent bkops exception event
5501  * @hba: per-adapter instance
5502  *
5503  * Enable fBackgroundOpsEn flag in the device to permit background
5504  * operations.
5505  *
5506  * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5507  * and negative error value for any other failure.
5508  */
5509 static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5510 {
5511         return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
5512 }
5513
5514 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5515 {
5516         return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5517                         QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5518 }
5519
5520 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5521 {
5522         int err;
5523         u32 curr_status = 0;
5524
5525         if (hba->is_urgent_bkops_lvl_checked)
5526                 goto enable_auto_bkops;
5527
5528         err = ufshcd_get_bkops_status(hba, &curr_status);
5529         if (err) {
5530                 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5531                                 __func__, err);
5532                 goto out;
5533         }
5534
5535         /*
5536          * We are seeing that some devices are raising the urgent bkops
5537          * exception events even when BKOPS status doesn't indicate performace
5538          * impacted or critical. Handle these device by determining their urgent
5539          * bkops status at runtime.
5540          */
5541         if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5542                 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5543                                 __func__, curr_status);
5544                 /* update the current status as the urgent bkops level */
5545                 hba->urgent_bkops_lvl = curr_status;
5546                 hba->is_urgent_bkops_lvl_checked = true;
5547         }
5548
5549 enable_auto_bkops:
5550         err = ufshcd_enable_auto_bkops(hba);
5551 out:
5552         if (err < 0)
5553                 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5554                                 __func__, err);
5555 }
5556
5557 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn)
5558 {
5559         u8 index;
5560         enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG :
5561                                    UPIU_QUERY_OPCODE_CLEAR_FLAG;
5562
5563         index = ufshcd_wb_get_query_index(hba);
5564         return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL);
5565 }
5566
5567 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable)
5568 {
5569         int ret;
5570
5571         if (!ufshcd_is_wb_allowed(hba))
5572                 return 0;
5573
5574         if (!(enable ^ hba->dev_info.wb_enabled))
5575                 return 0;
5576
5577         ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN);
5578         if (ret) {
5579                 dev_err(hba->dev, "%s Write Booster %s failed %d\n",
5580                         __func__, enable ? "enable" : "disable", ret);
5581                 return ret;
5582         }
5583
5584         hba->dev_info.wb_enabled = enable;
5585         dev_info(hba->dev, "%s Write Booster %s\n",
5586                         __func__, enable ? "enabled" : "disabled");
5587
5588         return ret;
5589 }
5590
5591 static void ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set)
5592 {
5593         int ret;
5594
5595         ret = __ufshcd_wb_toggle(hba, set,
5596                         QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8);
5597         if (ret) {
5598                 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed: %d\n",
5599                         __func__, set ? "enable" : "disable", ret);
5600                 return;
5601         }
5602         dev_dbg(hba->dev, "%s WB-Buf Flush during H8 %s\n",
5603                         __func__, set ? "enabled" : "disabled");
5604 }
5605
5606 static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable)
5607 {
5608         int ret;
5609
5610         if (!ufshcd_is_wb_allowed(hba) ||
5611             hba->dev_info.wb_buf_flush_enabled == enable)
5612                 return;
5613
5614         ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN);
5615         if (ret) {
5616                 dev_err(hba->dev, "%s WB-Buf Flush %s failed %d\n", __func__,
5617                         enable ? "enable" : "disable", ret);
5618                 return;
5619         }
5620
5621         hba->dev_info.wb_buf_flush_enabled = enable;
5622
5623         dev_dbg(hba->dev, "%s WB-Buf Flush %s\n",
5624                         __func__, enable ? "enabled" : "disabled");
5625 }
5626
5627 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba,
5628                                                 u32 avail_buf)
5629 {
5630         u32 cur_buf;
5631         int ret;
5632         u8 index;
5633
5634         index = ufshcd_wb_get_query_index(hba);
5635         ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5636                                               QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE,
5637                                               index, 0, &cur_buf);
5638         if (ret) {
5639                 dev_err(hba->dev, "%s dCurWriteBoosterBufferSize read failed %d\n",
5640                         __func__, ret);
5641                 return false;
5642         }
5643
5644         if (!cur_buf) {
5645                 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n",
5646                          cur_buf);
5647                 return false;
5648         }
5649         /* Let it continue to flush when available buffer exceeds threshold */
5650         if (avail_buf < hba->vps->wb_flush_threshold)
5651                 return true;
5652
5653         return false;
5654 }
5655
5656 static bool ufshcd_wb_need_flush(struct ufs_hba *hba)
5657 {
5658         int ret;
5659         u32 avail_buf;
5660         u8 index;
5661
5662         if (!ufshcd_is_wb_allowed(hba))
5663                 return false;
5664         /*
5665          * The ufs device needs the vcc to be ON to flush.
5666          * With user-space reduction enabled, it's enough to enable flush
5667          * by checking only the available buffer. The threshold
5668          * defined here is > 90% full.
5669          * With user-space preserved enabled, the current-buffer
5670          * should be checked too because the wb buffer size can reduce
5671          * when disk tends to be full. This info is provided by current
5672          * buffer (dCurrentWriteBoosterBufferSize). There's no point in
5673          * keeping vcc on when current buffer is empty.
5674          */
5675         index = ufshcd_wb_get_query_index(hba);
5676         ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5677                                       QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE,
5678                                       index, 0, &avail_buf);
5679         if (ret) {
5680                 dev_warn(hba->dev, "%s dAvailableWriteBoosterBufferSize read failed %d\n",
5681                          __func__, ret);
5682                 return false;
5683         }
5684
5685         if (!hba->dev_info.b_presrv_uspc_en) {
5686                 if (avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10))
5687                         return true;
5688                 return false;
5689         }
5690
5691         return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf);
5692 }
5693
5694 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work)
5695 {
5696         struct ufs_hba *hba = container_of(to_delayed_work(work),
5697                                            struct ufs_hba,
5698                                            rpm_dev_flush_recheck_work);
5699         /*
5700          * To prevent unnecessary VCC power drain after device finishes
5701          * WriteBooster buffer flush or Auto BKOPs, force runtime resume
5702          * after a certain delay to recheck the threshold by next runtime
5703          * suspend.
5704          */
5705         ufshcd_rpm_get_sync(hba);
5706         ufshcd_rpm_put_sync(hba);
5707 }
5708
5709 /**
5710  * ufshcd_exception_event_handler - handle exceptions raised by device
5711  * @work: pointer to work data
5712  *
5713  * Read bExceptionEventStatus attribute from the device and handle the
5714  * exception event accordingly.
5715  */
5716 static void ufshcd_exception_event_handler(struct work_struct *work)
5717 {
5718         struct ufs_hba *hba;
5719         int err;
5720         u32 status = 0;
5721         hba = container_of(work, struct ufs_hba, eeh_work);
5722
5723         ufshcd_scsi_block_requests(hba);
5724         err = ufshcd_get_ee_status(hba, &status);
5725         if (err) {
5726                 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5727                                 __func__, err);
5728                 goto out;
5729         }
5730
5731         trace_ufshcd_exception_event(dev_name(hba->dev), status);
5732
5733         if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS)
5734                 ufshcd_bkops_exception_event_handler(hba);
5735
5736         ufs_debugfs_exception_event(hba, status);
5737 out:
5738         ufshcd_scsi_unblock_requests(hba);
5739         return;
5740 }
5741
5742 /* Complete requests that have door-bell cleared */
5743 static void ufshcd_complete_requests(struct ufs_hba *hba)
5744 {
5745         ufshcd_transfer_req_compl(hba);
5746         ufshcd_tmc_handler(hba);
5747 }
5748
5749 /**
5750  * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
5751  *                              to recover from the DL NAC errors or not.
5752  * @hba: per-adapter instance
5753  *
5754  * Returns true if error handling is required, false otherwise
5755  */
5756 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5757 {
5758         unsigned long flags;
5759         bool err_handling = true;
5760
5761         spin_lock_irqsave(hba->host->host_lock, flags);
5762         /*
5763          * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
5764          * device fatal error and/or DL NAC & REPLAY timeout errors.
5765          */
5766         if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5767                 goto out;
5768
5769         if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5770             ((hba->saved_err & UIC_ERROR) &&
5771              (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5772                 goto out;
5773
5774         if ((hba->saved_err & UIC_ERROR) &&
5775             (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5776                 int err;
5777                 /*
5778                  * wait for 50ms to see if we can get any other errors or not.
5779                  */
5780                 spin_unlock_irqrestore(hba->host->host_lock, flags);
5781                 msleep(50);
5782                 spin_lock_irqsave(hba->host->host_lock, flags);
5783
5784                 /*
5785                  * now check if we have got any other severe errors other than
5786                  * DL NAC error?
5787                  */
5788                 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5789                     ((hba->saved_err & UIC_ERROR) &&
5790                     (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
5791                         goto out;
5792
5793                 /*
5794                  * As DL NAC is the only error received so far, send out NOP
5795                  * command to confirm if link is still active or not.
5796                  *   - If we don't get any response then do error recovery.
5797                  *   - If we get response then clear the DL NAC error bit.
5798                  */
5799
5800                 spin_unlock_irqrestore(hba->host->host_lock, flags);
5801                 err = ufshcd_verify_dev_init(hba);
5802                 spin_lock_irqsave(hba->host->host_lock, flags);
5803
5804                 if (err)
5805                         goto out;
5806
5807                 /* Link seems to be alive hence ignore the DL NAC errors */
5808                 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5809                         hba->saved_err &= ~UIC_ERROR;
5810                 /* clear NAC error */
5811                 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5812                 if (!hba->saved_uic_err)
5813                         err_handling = false;
5814         }
5815 out:
5816         spin_unlock_irqrestore(hba->host->host_lock, flags);
5817         return err_handling;
5818 }
5819
5820 /* host lock must be held before calling this func */
5821 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba)
5822 {
5823         return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
5824                (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK));
5825 }
5826
5827 /* host lock must be held before calling this func */
5828 static inline void ufshcd_schedule_eh_work(struct ufs_hba *hba)
5829 {
5830         /* handle fatal errors only when link is not in error state */
5831         if (hba->ufshcd_state != UFSHCD_STATE_ERROR) {
5832                 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
5833                     ufshcd_is_saved_err_fatal(hba))
5834                         hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL;
5835                 else
5836                         hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL;
5837                 queue_work(hba->eh_wq, &hba->eh_work);
5838         }
5839 }
5840
5841 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow)
5842 {
5843         down_write(&hba->clk_scaling_lock);
5844         hba->clk_scaling.is_allowed = allow;
5845         up_write(&hba->clk_scaling_lock);
5846 }
5847
5848 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend)
5849 {
5850         if (suspend) {
5851                 if (hba->clk_scaling.is_enabled)
5852                         ufshcd_suspend_clkscaling(hba);
5853                 ufshcd_clk_scaling_allow(hba, false);
5854         } else {
5855                 ufshcd_clk_scaling_allow(hba, true);
5856                 if (hba->clk_scaling.is_enabled)
5857                         ufshcd_resume_clkscaling(hba);
5858         }
5859 }
5860
5861 static void ufshcd_err_handling_prepare(struct ufs_hba *hba)
5862 {
5863         ufshcd_rpm_get_sync(hba);
5864         if (pm_runtime_status_suspended(&hba->sdev_ufs_device->sdev_gendev) ||
5865             hba->is_sys_suspended) {
5866                 enum ufs_pm_op pm_op;
5867
5868                 /*
5869                  * Don't assume anything of resume, if
5870                  * resume fails, irq and clocks can be OFF, and powers
5871                  * can be OFF or in LPM.
5872                  */
5873                 ufshcd_setup_hba_vreg(hba, true);
5874                 ufshcd_enable_irq(hba);
5875                 ufshcd_setup_vreg(hba, true);
5876                 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
5877                 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
5878                 ufshcd_hold(hba, false);
5879                 if (!ufshcd_is_clkgating_allowed(hba))
5880                         ufshcd_setup_clocks(hba, true);
5881                 ufshcd_release(hba);
5882                 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM;
5883                 ufshcd_vops_resume(hba, pm_op);
5884         } else {
5885                 ufshcd_hold(hba, false);
5886                 if (ufshcd_is_clkscaling_supported(hba) &&
5887                     hba->clk_scaling.is_enabled)
5888                         ufshcd_suspend_clkscaling(hba);
5889                 ufshcd_clk_scaling_allow(hba, false);
5890         }
5891         ufshcd_scsi_block_requests(hba);
5892         /* Drain ufshcd_queuecommand() */
5893         down_write(&hba->clk_scaling_lock);
5894         up_write(&hba->clk_scaling_lock);
5895         cancel_work_sync(&hba->eeh_work);
5896 }
5897
5898 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba)
5899 {
5900         ufshcd_scsi_unblock_requests(hba);
5901         ufshcd_release(hba);
5902         if (ufshcd_is_clkscaling_supported(hba))
5903                 ufshcd_clk_scaling_suspend(hba, false);
5904         ufshcd_clear_ua_wluns(hba);
5905         ufshcd_rpm_put(hba);
5906 }
5907
5908 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba)
5909 {
5910         return (!hba->is_powered || hba->shutting_down ||
5911                 !hba->sdev_ufs_device ||
5912                 hba->ufshcd_state == UFSHCD_STATE_ERROR ||
5913                 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset ||
5914                    ufshcd_is_link_broken(hba))));
5915 }
5916
5917 #ifdef CONFIG_PM
5918 static void ufshcd_recover_pm_error(struct ufs_hba *hba)
5919 {
5920         struct Scsi_Host *shost = hba->host;
5921         struct scsi_device *sdev;
5922         struct request_queue *q;
5923         int ret;
5924
5925         hba->is_sys_suspended = false;
5926         /*
5927          * Set RPM status of wlun device to RPM_ACTIVE,
5928          * this also clears its runtime error.
5929          */
5930         ret = pm_runtime_set_active(&hba->sdev_ufs_device->sdev_gendev);
5931
5932         /* hba device might have a runtime error otherwise */
5933         if (ret)
5934                 ret = pm_runtime_set_active(hba->dev);
5935         /*
5936          * If wlun device had runtime error, we also need to resume those
5937          * consumer scsi devices in case any of them has failed to be
5938          * resumed due to supplier runtime resume failure. This is to unblock
5939          * blk_queue_enter in case there are bios waiting inside it.
5940          */
5941         if (!ret) {
5942                 shost_for_each_device(sdev, shost) {
5943                         q = sdev->request_queue;
5944                         if (q->dev && (q->rpm_status == RPM_SUSPENDED ||
5945                                        q->rpm_status == RPM_SUSPENDING))
5946                                 pm_request_resume(q->dev);
5947                 }
5948         }
5949 }
5950 #else
5951 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba)
5952 {
5953 }
5954 #endif
5955
5956 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba)
5957 {
5958         struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info;
5959         u32 mode;
5960
5961         ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode);
5962
5963         if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK))
5964                 return true;
5965
5966         if (pwr_info->pwr_tx != (mode & PWRMODE_MASK))
5967                 return true;
5968
5969         return false;
5970 }
5971
5972 /**
5973  * ufshcd_err_handler - handle UFS errors that require s/w attention
5974  * @work: pointer to work structure
5975  */
5976 static void ufshcd_err_handler(struct work_struct *work)
5977 {
5978         struct ufs_hba *hba;
5979         unsigned long flags;
5980         bool err_xfer = false;
5981         bool err_tm = false;
5982         int err = 0, pmc_err;
5983         int tag;
5984         bool needs_reset = false, needs_restore = false;
5985
5986         hba = container_of(work, struct ufs_hba, eh_work);
5987
5988         down(&hba->host_sem);
5989         spin_lock_irqsave(hba->host->host_lock, flags);
5990         if (ufshcd_err_handling_should_stop(hba)) {
5991                 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
5992                         hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5993                 spin_unlock_irqrestore(hba->host->host_lock, flags);
5994                 up(&hba->host_sem);
5995                 return;
5996         }
5997         ufshcd_set_eh_in_progress(hba);
5998         spin_unlock_irqrestore(hba->host->host_lock, flags);
5999         ufshcd_err_handling_prepare(hba);
6000         spin_lock_irqsave(hba->host->host_lock, flags);
6001         if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6002                 hba->ufshcd_state = UFSHCD_STATE_RESET;
6003
6004         /* Complete requests that have door-bell cleared by h/w */
6005         ufshcd_complete_requests(hba);
6006
6007         /*
6008          * A full reset and restore might have happened after preparation
6009          * is finished, double check whether we should stop.
6010          */
6011         if (ufshcd_err_handling_should_stop(hba))
6012                 goto skip_err_handling;
6013
6014         if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6015                 bool ret;
6016
6017                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6018                 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
6019                 ret = ufshcd_quirk_dl_nac_errors(hba);
6020                 spin_lock_irqsave(hba->host->host_lock, flags);
6021                 if (!ret && ufshcd_err_handling_should_stop(hba))
6022                         goto skip_err_handling;
6023         }
6024
6025         if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6026             (hba->saved_uic_err &&
6027              (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6028                 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR);
6029
6030                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6031                 ufshcd_print_host_state(hba);
6032                 ufshcd_print_pwr_info(hba);
6033                 ufshcd_print_evt_hist(hba);
6034                 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
6035                 ufshcd_print_trs(hba, hba->outstanding_reqs, pr_prdt);
6036                 spin_lock_irqsave(hba->host->host_lock, flags);
6037         }
6038
6039         /*
6040          * if host reset is required then skip clearing the pending
6041          * transfers forcefully because they will get cleared during
6042          * host reset and restore
6043          */
6044         if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6045             ufshcd_is_saved_err_fatal(hba) ||
6046             ((hba->saved_err & UIC_ERROR) &&
6047              (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
6048                                     UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) {
6049                 needs_reset = true;
6050                 goto do_reset;
6051         }
6052
6053         /*
6054          * If LINERESET was caught, UFS might have been put to PWM mode,
6055          * check if power mode restore is needed.
6056          */
6057         if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) {
6058                 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6059                 if (!hba->saved_uic_err)
6060                         hba->saved_err &= ~UIC_ERROR;
6061                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6062                 if (ufshcd_is_pwr_mode_restore_needed(hba))
6063                         needs_restore = true;
6064                 spin_lock_irqsave(hba->host->host_lock, flags);
6065                 if (!hba->saved_err && !needs_restore)
6066                         goto skip_err_handling;
6067         }
6068
6069         hba->silence_err_logs = true;
6070         /* release lock as clear command might sleep */
6071         spin_unlock_irqrestore(hba->host->host_lock, flags);
6072         /* Clear pending transfer requests */
6073         for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
6074                 if (ufshcd_try_to_abort_task(hba, tag)) {
6075                         err_xfer = true;
6076                         goto lock_skip_pending_xfer_clear;
6077                 }
6078         }
6079
6080         /* Clear pending task management requests */
6081         for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
6082                 if (ufshcd_clear_tm_cmd(hba, tag)) {
6083                         err_tm = true;
6084                         goto lock_skip_pending_xfer_clear;
6085                 }
6086         }
6087
6088 lock_skip_pending_xfer_clear:
6089         spin_lock_irqsave(hba->host->host_lock, flags);
6090
6091         /* Complete the requests that are cleared by s/w */
6092         ufshcd_complete_requests(hba);
6093         hba->silence_err_logs = false;
6094
6095         if (err_xfer || err_tm) {
6096                 needs_reset = true;
6097                 goto do_reset;
6098         }
6099
6100         /*
6101          * After all reqs and tasks are cleared from doorbell,
6102          * now it is safe to retore power mode.
6103          */
6104         if (needs_restore) {
6105                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6106                 /*
6107                  * Hold the scaling lock just in case dev cmds
6108                  * are sent via bsg and/or sysfs.
6109                  */
6110                 down_write(&hba->clk_scaling_lock);
6111                 hba->force_pmc = true;
6112                 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info));
6113                 if (pmc_err) {
6114                         needs_reset = true;
6115                         dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n",
6116                                         __func__, pmc_err);
6117                 }
6118                 hba->force_pmc = false;
6119                 ufshcd_print_pwr_info(hba);
6120                 up_write(&hba->clk_scaling_lock);
6121                 spin_lock_irqsave(hba->host->host_lock, flags);
6122         }
6123
6124 do_reset:
6125         /* Fatal errors need reset */
6126         if (needs_reset) {
6127                 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
6128
6129                 /*
6130                  * ufshcd_reset_and_restore() does the link reinitialization
6131                  * which will need atleast one empty doorbell slot to send the
6132                  * device management commands (NOP and query commands).
6133                  * If there is no slot empty at this moment then free up last
6134                  * slot forcefully.
6135                  */
6136                 if (hba->outstanding_reqs == max_doorbells)
6137                         __ufshcd_transfer_req_compl(hba,
6138                                                     (1UL << (hba->nutrs - 1)));
6139
6140                 hba->force_reset = false;
6141                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6142                 err = ufshcd_reset_and_restore(hba);
6143                 if (err)
6144                         dev_err(hba->dev, "%s: reset and restore failed with err %d\n",
6145                                         __func__, err);
6146                 else
6147                         ufshcd_recover_pm_error(hba);
6148                 spin_lock_irqsave(hba->host->host_lock, flags);
6149         }
6150
6151 skip_err_handling:
6152         if (!needs_reset) {
6153                 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
6154                         hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6155                 if (hba->saved_err || hba->saved_uic_err)
6156                         dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
6157                             __func__, hba->saved_err, hba->saved_uic_err);
6158         }
6159         ufshcd_clear_eh_in_progress(hba);
6160         spin_unlock_irqrestore(hba->host->host_lock, flags);
6161         ufshcd_err_handling_unprepare(hba);
6162         up(&hba->host_sem);
6163 }
6164
6165 /**
6166  * ufshcd_update_uic_error - check and set fatal UIC error flags.
6167  * @hba: per-adapter instance
6168  *
6169  * Returns
6170  *  IRQ_HANDLED - If interrupt is valid
6171  *  IRQ_NONE    - If invalid interrupt
6172  */
6173 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
6174 {
6175         u32 reg;
6176         irqreturn_t retval = IRQ_NONE;
6177
6178         /* PHY layer error */
6179         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
6180         if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
6181             (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) {
6182                 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg);
6183                 /*
6184                  * To know whether this error is fatal or not, DB timeout
6185                  * must be checked but this error is handled separately.
6186                  */
6187                 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)
6188                         dev_dbg(hba->dev, "%s: UIC Lane error reported\n",
6189                                         __func__);
6190
6191                 /* Got a LINERESET indication. */
6192                 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) {
6193                         struct uic_command *cmd = NULL;
6194
6195                         hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR;
6196                         if (hba->uic_async_done && hba->active_uic_cmd)
6197                                 cmd = hba->active_uic_cmd;
6198                         /*
6199                          * Ignore the LINERESET during power mode change
6200                          * operation via DME_SET command.
6201                          */
6202                         if (cmd && (cmd->command == UIC_CMD_DME_SET))
6203                                 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6204                 }
6205                 retval |= IRQ_HANDLED;
6206         }
6207
6208         /* PA_INIT_ERROR is fatal and needs UIC reset */
6209         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
6210         if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
6211             (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
6212                 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg);
6213
6214                 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
6215                         hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
6216                 else if (hba->dev_quirks &
6217                                 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6218                         if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
6219                                 hba->uic_error |=
6220                                         UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6221                         else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
6222                                 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
6223                 }
6224                 retval |= IRQ_HANDLED;
6225         }
6226
6227         /* UIC NL/TL/DME errors needs software retry */
6228         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
6229         if ((reg & UIC_NETWORK_LAYER_ERROR) &&
6230             (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
6231                 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg);
6232                 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
6233                 retval |= IRQ_HANDLED;
6234         }
6235
6236         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
6237         if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
6238             (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
6239                 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg);
6240                 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
6241                 retval |= IRQ_HANDLED;
6242         }
6243
6244         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
6245         if ((reg & UIC_DME_ERROR) &&
6246             (reg & UIC_DME_ERROR_CODE_MASK)) {
6247                 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg);
6248                 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
6249                 retval |= IRQ_HANDLED;
6250         }
6251
6252         dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
6253                         __func__, hba->uic_error);
6254         return retval;
6255 }
6256
6257 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
6258                                          u32 intr_mask)
6259 {
6260         if (!ufshcd_is_auto_hibern8_supported(hba) ||
6261             !ufshcd_is_auto_hibern8_enabled(hba))
6262                 return false;
6263
6264         if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
6265                 return false;
6266
6267         if (hba->active_uic_cmd &&
6268             (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
6269             hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
6270                 return false;
6271
6272         return true;
6273 }
6274
6275 /**
6276  * ufshcd_check_errors - Check for errors that need s/w attention
6277  * @hba: per-adapter instance
6278  *
6279  * Returns
6280  *  IRQ_HANDLED - If interrupt is valid
6281  *  IRQ_NONE    - If invalid interrupt
6282  */
6283 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba)
6284 {
6285         bool queue_eh_work = false;
6286         irqreturn_t retval = IRQ_NONE;
6287
6288         if (hba->errors & INT_FATAL_ERRORS) {
6289                 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR,
6290                                        hba->errors);
6291                 queue_eh_work = true;
6292         }
6293
6294         if (hba->errors & UIC_ERROR) {
6295                 hba->uic_error = 0;
6296                 retval = ufshcd_update_uic_error(hba);
6297                 if (hba->uic_error)
6298                         queue_eh_work = true;
6299         }
6300
6301         if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
6302                 dev_err(hba->dev,
6303                         "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
6304                         __func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
6305                         "Enter" : "Exit",
6306                         hba->errors, ufshcd_get_upmcrs(hba));
6307                 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR,
6308                                        hba->errors);
6309                 ufshcd_set_link_broken(hba);
6310                 queue_eh_work = true;
6311         }
6312
6313         if (queue_eh_work) {
6314                 /*
6315                  * update the transfer error masks to sticky bits, let's do this
6316                  * irrespective of current ufshcd_state.
6317                  */
6318                 hba->saved_err |= hba->errors;
6319                 hba->saved_uic_err |= hba->uic_error;
6320
6321                 /* dump controller state before resetting */
6322                 if ((hba->saved_err &
6323                      (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6324                     (hba->saved_uic_err &&
6325                      (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6326                         dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
6327                                         __func__, hba->saved_err,
6328                                         hba->saved_uic_err);
6329                         ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE,
6330                                          "host_regs: ");
6331                         ufshcd_print_pwr_info(hba);
6332                 }
6333                 ufshcd_schedule_eh_work(hba);
6334                 retval |= IRQ_HANDLED;
6335         }
6336         /*
6337          * if (!queue_eh_work) -
6338          * Other errors are either non-fatal where host recovers
6339          * itself without s/w intervention or errors that will be
6340          * handled by the SCSI core layer.
6341          */
6342         return retval;
6343 }
6344
6345 struct ctm_info {
6346         struct ufs_hba  *hba;
6347         unsigned long   pending;
6348         unsigned int    ncpl;
6349 };
6350
6351 static bool ufshcd_compl_tm(struct request *req, void *priv, bool reserved)
6352 {
6353         struct ctm_info *const ci = priv;
6354         struct completion *c;
6355
6356         WARN_ON_ONCE(reserved);
6357         if (test_bit(req->tag, &ci->pending))
6358                 return true;
6359         ci->ncpl++;
6360         c = req->end_io_data;
6361         if (c)
6362                 complete(c);
6363         return true;
6364 }
6365
6366 /**
6367  * ufshcd_tmc_handler - handle task management function completion
6368  * @hba: per adapter instance
6369  *
6370  * Returns
6371  *  IRQ_HANDLED - If interrupt is valid
6372  *  IRQ_NONE    - If invalid interrupt
6373  */
6374 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
6375 {
6376         struct request_queue *q = hba->tmf_queue;
6377         struct ctm_info ci = {
6378                 .hba     = hba,
6379                 .pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL),
6380         };
6381
6382         blk_mq_tagset_busy_iter(q->tag_set, ufshcd_compl_tm, &ci);
6383         return ci.ncpl ? IRQ_HANDLED : IRQ_NONE;
6384 }
6385
6386 /**
6387  * ufshcd_sl_intr - Interrupt service routine
6388  * @hba: per adapter instance
6389  * @intr_status: contains interrupts generated by the controller
6390  *
6391  * Returns
6392  *  IRQ_HANDLED - If interrupt is valid
6393  *  IRQ_NONE    - If invalid interrupt
6394  */
6395 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
6396 {
6397         irqreturn_t retval = IRQ_NONE;
6398
6399         hba->errors = UFSHCD_ERROR_MASK & intr_status;
6400
6401         if (ufshcd_is_auto_hibern8_error(hba, intr_status))
6402                 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
6403
6404         if (hba->errors)
6405                 retval |= ufshcd_check_errors(hba);
6406
6407         if (intr_status & UFSHCD_UIC_MASK)
6408                 retval |= ufshcd_uic_cmd_compl(hba, intr_status);
6409
6410         if (intr_status & UTP_TASK_REQ_COMPL)
6411                 retval |= ufshcd_tmc_handler(hba);
6412
6413         if (intr_status & UTP_TRANSFER_REQ_COMPL)
6414                 retval |= ufshcd_transfer_req_compl(hba);
6415
6416         return retval;
6417 }
6418
6419 /**
6420  * ufshcd_intr - Main interrupt service routine
6421  * @irq: irq number
6422  * @__hba: pointer to adapter instance
6423  *
6424  * Returns
6425  *  IRQ_HANDLED - If interrupt is valid
6426  *  IRQ_NONE    - If invalid interrupt
6427  */
6428 static irqreturn_t ufshcd_intr(int irq, void *__hba)
6429 {
6430         u32 intr_status, enabled_intr_status = 0;
6431         irqreturn_t retval = IRQ_NONE;
6432         struct ufs_hba *hba = __hba;
6433         int retries = hba->nutrs;
6434
6435         spin_lock(hba->host->host_lock);
6436         intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6437         hba->ufs_stats.last_intr_status = intr_status;
6438         hba->ufs_stats.last_intr_ts = ktime_get();
6439
6440         /*
6441          * There could be max of hba->nutrs reqs in flight and in worst case
6442          * if the reqs get finished 1 by 1 after the interrupt status is
6443          * read, make sure we handle them by checking the interrupt status
6444          * again in a loop until we process all of the reqs before returning.
6445          */
6446         while (intr_status && retries--) {
6447                 enabled_intr_status =
6448                         intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
6449                 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
6450                 if (enabled_intr_status)
6451                         retval |= ufshcd_sl_intr(hba, enabled_intr_status);
6452
6453                 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6454         }
6455
6456         if (enabled_intr_status && retval == IRQ_NONE &&
6457             (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) ||
6458              hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) {
6459                 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n",
6460                                         __func__,
6461                                         intr_status,
6462                                         hba->ufs_stats.last_intr_status,
6463                                         enabled_intr_status);
6464                 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
6465         }
6466
6467         spin_unlock(hba->host->host_lock);
6468         return retval;
6469 }
6470
6471 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
6472 {
6473         int err = 0;
6474         u32 mask = 1 << tag;
6475         unsigned long flags;
6476
6477         if (!test_bit(tag, &hba->outstanding_tasks))
6478                 goto out;
6479
6480         spin_lock_irqsave(hba->host->host_lock, flags);
6481         ufshcd_utmrl_clear(hba, tag);
6482         spin_unlock_irqrestore(hba->host->host_lock, flags);
6483
6484         /* poll for max. 1 sec to clear door bell register by h/w */
6485         err = ufshcd_wait_for_register(hba,
6486                         REG_UTP_TASK_REQ_DOOR_BELL,
6487                         mask, 0, 1000, 1000);
6488 out:
6489         return err;
6490 }
6491
6492 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
6493                 struct utp_task_req_desc *treq, u8 tm_function)
6494 {
6495         struct request_queue *q = hba->tmf_queue;
6496         struct Scsi_Host *host = hba->host;
6497         DECLARE_COMPLETION_ONSTACK(wait);
6498         struct request *req;
6499         unsigned long flags;
6500         int task_tag, err;
6501
6502         /*
6503          * blk_get_request() is used here only to get a free tag.
6504          */
6505         req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
6506         if (IS_ERR(req))
6507                 return PTR_ERR(req);
6508
6509         req->end_io_data = &wait;
6510         ufshcd_hold(hba, false);
6511
6512         spin_lock_irqsave(host->host_lock, flags);
6513         blk_mq_start_request(req);
6514
6515         task_tag = req->tag;
6516         treq->upiu_req.req_header.dword_0 |= cpu_to_be32(task_tag);
6517
6518         memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq));
6519         ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function);
6520
6521         /* send command to the controller */
6522         __set_bit(task_tag, &hba->outstanding_tasks);
6523
6524         /* Make sure descriptors are ready before ringing the task doorbell */
6525         wmb();
6526
6527         ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL);
6528         /* Make sure that doorbell is committed immediately */
6529         wmb();
6530
6531         spin_unlock_irqrestore(host->host_lock, flags);
6532
6533         ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND);
6534
6535         /* wait until the task management command is completed */
6536         err = wait_for_completion_io_timeout(&wait,
6537                         msecs_to_jiffies(TM_CMD_TIMEOUT));
6538         if (!err) {
6539                 /*
6540                  * Make sure that ufshcd_compl_tm() does not trigger a
6541                  * use-after-free.
6542                  */
6543                 req->end_io_data = NULL;
6544                 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR);
6545                 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
6546                                 __func__, tm_function);
6547                 if (ufshcd_clear_tm_cmd(hba, task_tag))
6548                         dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n",
6549                                         __func__, task_tag);
6550                 err = -ETIMEDOUT;
6551         } else {
6552                 err = 0;
6553                 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq));
6554
6555                 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP);
6556         }
6557
6558         spin_lock_irqsave(hba->host->host_lock, flags);
6559         __clear_bit(task_tag, &hba->outstanding_tasks);
6560         spin_unlock_irqrestore(hba->host->host_lock, flags);
6561
6562         ufshcd_release(hba);
6563         blk_put_request(req);
6564
6565         return err;
6566 }
6567
6568 /**
6569  * ufshcd_issue_tm_cmd - issues task management commands to controller
6570  * @hba: per adapter instance
6571  * @lun_id: LUN ID to which TM command is sent
6572  * @task_id: task ID to which the TM command is applicable
6573  * @tm_function: task management function opcode
6574  * @tm_response: task management service response return value
6575  *
6576  * Returns non-zero value on error, zero on success.
6577  */
6578 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
6579                 u8 tm_function, u8 *tm_response)
6580 {
6581         struct utp_task_req_desc treq = { { 0 }, };
6582         int ocs_value, err;
6583
6584         /* Configure task request descriptor */
6585         treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6586         treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6587
6588         /* Configure task request UPIU */
6589         treq.upiu_req.req_header.dword_0 = cpu_to_be32(lun_id << 8) |
6590                                   cpu_to_be32(UPIU_TRANSACTION_TASK_REQ << 24);
6591         treq.upiu_req.req_header.dword_1 = cpu_to_be32(tm_function << 16);
6592
6593         /*
6594          * The host shall provide the same value for LUN field in the basic
6595          * header and for Input Parameter.
6596          */
6597         treq.upiu_req.input_param1 = cpu_to_be32(lun_id);
6598         treq.upiu_req.input_param2 = cpu_to_be32(task_id);
6599
6600         err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
6601         if (err == -ETIMEDOUT)
6602                 return err;
6603
6604         ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6605         if (ocs_value != OCS_SUCCESS)
6606                 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
6607                                 __func__, ocs_value);
6608         else if (tm_response)
6609                 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) &
6610                                 MASK_TM_SERVICE_RESP;
6611         return err;
6612 }
6613
6614 /**
6615  * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
6616  * @hba:        per-adapter instance
6617  * @req_upiu:   upiu request
6618  * @rsp_upiu:   upiu reply
6619  * @desc_buff:  pointer to descriptor buffer, NULL if NA
6620  * @buff_len:   descriptor size, 0 if NA
6621  * @cmd_type:   specifies the type (NOP, Query...)
6622  * @desc_op:    descriptor operation
6623  *
6624  * Those type of requests uses UTP Transfer Request Descriptor - utrd.
6625  * Therefore, it "rides" the device management infrastructure: uses its tag and
6626  * tasks work queues.
6627  *
6628  * Since there is only one available tag for device management commands,
6629  * the caller is expected to hold the hba->dev_cmd.lock mutex.
6630  */
6631 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
6632                                         struct utp_upiu_req *req_upiu,
6633                                         struct utp_upiu_req *rsp_upiu,
6634                                         u8 *desc_buff, int *buff_len,
6635                                         enum dev_cmd_type cmd_type,
6636                                         enum query_opcode desc_op)
6637 {
6638         struct request_queue *q = hba->cmd_queue;
6639         struct request *req;
6640         struct ufshcd_lrb *lrbp;
6641         int err = 0;
6642         int tag;
6643         struct completion wait;
6644         unsigned long flags;
6645         u8 upiu_flags;
6646
6647         down_read(&hba->clk_scaling_lock);
6648
6649         req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
6650         if (IS_ERR(req)) {
6651                 err = PTR_ERR(req);
6652                 goto out_unlock;
6653         }
6654         tag = req->tag;
6655         WARN_ON_ONCE(!ufshcd_valid_tag(hba, tag));
6656
6657         init_completion(&wait);
6658         lrbp = &hba->lrb[tag];
6659         if (unlikely(lrbp->in_use)) {
6660                 err = -EBUSY;
6661                 goto out;
6662         }
6663
6664         WARN_ON(lrbp->cmd);
6665         lrbp->cmd = NULL;
6666         lrbp->sense_bufflen = 0;
6667         lrbp->sense_buffer = NULL;
6668         lrbp->task_tag = tag;
6669         lrbp->lun = 0;
6670         lrbp->intr_cmd = true;
6671         ufshcd_prepare_lrbp_crypto(NULL, lrbp);
6672         hba->dev_cmd.type = cmd_type;
6673
6674         if (hba->ufs_version <= ufshci_version(1, 1))
6675                 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
6676         else
6677                 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
6678
6679         /* update the task tag in the request upiu */
6680         req_upiu->header.dword_0 |= cpu_to_be32(tag);
6681
6682         ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
6683
6684         /* just copy the upiu request as it is */
6685         memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
6686         if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
6687                 /* The Data Segment Area is optional depending upon the query
6688                  * function value. for WRITE DESCRIPTOR, the data segment
6689                  * follows right after the tsf.
6690                  */
6691                 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
6692                 *buff_len = 0;
6693         }
6694
6695         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
6696
6697         hba->dev_cmd.complete = &wait;
6698
6699         /* Make sure descriptors are ready before ringing the doorbell */
6700         wmb();
6701         spin_lock_irqsave(hba->host->host_lock, flags);
6702         ufshcd_send_command(hba, tag);
6703         spin_unlock_irqrestore(hba->host->host_lock, flags);
6704
6705         /*
6706          * ignore the returning value here - ufshcd_check_query_response is
6707          * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
6708          * read the response directly ignoring all errors.
6709          */
6710         ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
6711
6712         /* just copy the upiu response as it is */
6713         memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
6714         if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
6715                 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
6716                 u16 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
6717                                MASK_QUERY_DATA_SEG_LEN;
6718
6719                 if (*buff_len >= resp_len) {
6720                         memcpy(desc_buff, descp, resp_len);
6721                         *buff_len = resp_len;
6722                 } else {
6723                         dev_warn(hba->dev,
6724                                  "%s: rsp size %d is bigger than buffer size %d",
6725                                  __func__, resp_len, *buff_len);
6726                         *buff_len = 0;
6727                         err = -EINVAL;
6728                 }
6729         }
6730
6731 out:
6732         blk_put_request(req);
6733 out_unlock:
6734         up_read(&hba->clk_scaling_lock);
6735         return err;
6736 }
6737
6738 /**
6739  * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
6740  * @hba:        per-adapter instance
6741  * @req_upiu:   upiu request
6742  * @rsp_upiu:   upiu reply - only 8 DW as we do not support scsi commands
6743  * @msgcode:    message code, one of UPIU Transaction Codes Initiator to Target
6744  * @desc_buff:  pointer to descriptor buffer, NULL if NA
6745  * @buff_len:   descriptor size, 0 if NA
6746  * @desc_op:    descriptor operation
6747  *
6748  * Supports UTP Transfer requests (nop and query), and UTP Task
6749  * Management requests.
6750  * It is up to the caller to fill the upiu conent properly, as it will
6751  * be copied without any further input validations.
6752  */
6753 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
6754                              struct utp_upiu_req *req_upiu,
6755                              struct utp_upiu_req *rsp_upiu,
6756                              int msgcode,
6757                              u8 *desc_buff, int *buff_len,
6758                              enum query_opcode desc_op)
6759 {
6760         int err;
6761         enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
6762         struct utp_task_req_desc treq = { { 0 }, };
6763         int ocs_value;
6764         u8 tm_f = be32_to_cpu(req_upiu->header.dword_1) >> 16 & MASK_TM_FUNC;
6765
6766         switch (msgcode) {
6767         case UPIU_TRANSACTION_NOP_OUT:
6768                 cmd_type = DEV_CMD_TYPE_NOP;
6769                 fallthrough;
6770         case UPIU_TRANSACTION_QUERY_REQ:
6771                 ufshcd_hold(hba, false);
6772                 mutex_lock(&hba->dev_cmd.lock);
6773                 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
6774                                                    desc_buff, buff_len,
6775                                                    cmd_type, desc_op);
6776                 mutex_unlock(&hba->dev_cmd.lock);
6777                 ufshcd_release(hba);
6778
6779                 break;
6780         case UPIU_TRANSACTION_TASK_REQ:
6781                 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6782                 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6783
6784                 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu));
6785
6786                 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
6787                 if (err == -ETIMEDOUT)
6788                         break;
6789
6790                 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6791                 if (ocs_value != OCS_SUCCESS) {
6792                         dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
6793                                 ocs_value);
6794                         break;
6795                 }
6796
6797                 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu));
6798
6799                 break;
6800         default:
6801                 err = -EINVAL;
6802
6803                 break;
6804         }
6805
6806         return err;
6807 }
6808
6809 /**
6810  * ufshcd_eh_device_reset_handler - device reset handler registered to
6811  *                                    scsi layer.
6812  * @cmd: SCSI command pointer
6813  *
6814  * Returns SUCCESS/FAILED
6815  */
6816 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
6817 {
6818         struct Scsi_Host *host;
6819         struct ufs_hba *hba;
6820         u32 pos;
6821         int err;
6822         u8 resp = 0xF, lun;
6823         unsigned long flags;
6824
6825         host = cmd->device->host;
6826         hba = shost_priv(host);
6827
6828         lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
6829         err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp);
6830         if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6831                 if (!err)
6832                         err = resp;
6833                 goto out;
6834         }
6835
6836         /* clear the commands that were pending for corresponding LUN */
6837         for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
6838                 if (hba->lrb[pos].lun == lun) {
6839                         err = ufshcd_clear_cmd(hba, pos);
6840                         if (err)
6841                                 break;
6842                 }
6843         }
6844         spin_lock_irqsave(host->host_lock, flags);
6845         ufshcd_transfer_req_compl(hba);
6846         spin_unlock_irqrestore(host->host_lock, flags);
6847
6848 out:
6849         hba->req_abort_count = 0;
6850         ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err);
6851         if (!err) {
6852                 err = SUCCESS;
6853         } else {
6854                 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
6855                 err = FAILED;
6856         }
6857         return err;
6858 }
6859
6860 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
6861 {
6862         struct ufshcd_lrb *lrbp;
6863         int tag;
6864
6865         for_each_set_bit(tag, &bitmap, hba->nutrs) {
6866                 lrbp = &hba->lrb[tag];
6867                 lrbp->req_abort_skip = true;
6868         }
6869 }
6870
6871 /**
6872  * ufshcd_try_to_abort_task - abort a specific task
6873  * @hba: Pointer to adapter instance
6874  * @tag: Task tag/index to be aborted
6875  *
6876  * Abort the pending command in device by sending UFS_ABORT_TASK task management
6877  * command, and in host controller by clearing the door-bell register. There can
6878  * be race between controller sending the command to the device while abort is
6879  * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
6880  * really issued and then try to abort it.
6881  *
6882  * Returns zero on success, non-zero on failure
6883  */
6884 static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag)
6885 {
6886         struct ufshcd_lrb *lrbp = &hba->lrb[tag];
6887         int err = 0;
6888         int poll_cnt;
6889         u8 resp = 0xF;
6890         u32 reg;
6891
6892         for (poll_cnt = 100; poll_cnt; poll_cnt--) {
6893                 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6894                                 UFS_QUERY_TASK, &resp);
6895                 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
6896                         /* cmd pending in the device */
6897                         dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
6898                                 __func__, tag);
6899                         break;
6900                 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6901                         /*
6902                          * cmd not pending in the device, check if it is
6903                          * in transition.
6904                          */
6905                         dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
6906                                 __func__, tag);
6907                         reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
6908                         if (reg & (1 << tag)) {
6909                                 /* sleep for max. 200us to stabilize */
6910                                 usleep_range(100, 200);
6911                                 continue;
6912                         }
6913                         /* command completed already */
6914                         dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
6915                                 __func__, tag);
6916                         goto out;
6917                 } else {
6918                         dev_err(hba->dev,
6919                                 "%s: no response from device. tag = %d, err %d\n",
6920                                 __func__, tag, err);
6921                         if (!err)
6922                                 err = resp; /* service response error */
6923                         goto out;
6924                 }
6925         }
6926
6927         if (!poll_cnt) {
6928                 err = -EBUSY;
6929                 goto out;
6930         }
6931
6932         err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6933                         UFS_ABORT_TASK, &resp);
6934         if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6935                 if (!err) {
6936                         err = resp; /* service response error */
6937                         dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
6938                                 __func__, tag, err);
6939                 }
6940                 goto out;
6941         }
6942
6943         err = ufshcd_clear_cmd(hba, tag);
6944         if (err)
6945                 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
6946                         __func__, tag, err);
6947
6948 out:
6949         return err;
6950 }
6951
6952 /**
6953  * ufshcd_abort - scsi host template eh_abort_handler callback
6954  * @cmd: SCSI command pointer
6955  *
6956  * Returns SUCCESS/FAILED
6957  */
6958 static int ufshcd_abort(struct scsi_cmnd *cmd)
6959 {
6960         struct Scsi_Host *host;
6961         struct ufs_hba *hba;
6962         unsigned long flags;
6963         unsigned int tag;
6964         int err = 0;
6965         struct ufshcd_lrb *lrbp;
6966         u32 reg;
6967
6968         host = cmd->device->host;
6969         hba = shost_priv(host);
6970         tag = cmd->request->tag;
6971         lrbp = &hba->lrb[tag];
6972         if (!ufshcd_valid_tag(hba, tag)) {
6973                 dev_err(hba->dev,
6974                         "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
6975                         __func__, tag, cmd, cmd->request);
6976                 BUG();
6977         }
6978
6979         ufshcd_hold(hba, false);
6980         reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
6981         /* If command is already aborted/completed, return SUCCESS */
6982         if (!(test_bit(tag, &hba->outstanding_reqs))) {
6983                 dev_err(hba->dev,
6984                         "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
6985                         __func__, tag, hba->outstanding_reqs, reg);
6986                 goto out;
6987         }
6988
6989         /* Print Transfer Request of aborted task */
6990         dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
6991
6992         /*
6993          * Print detailed info about aborted request.
6994          * As more than one request might get aborted at the same time,
6995          * print full information only for the first aborted request in order
6996          * to reduce repeated printouts. For other aborted requests only print
6997          * basic details.
6998          */
6999         scsi_print_command(cmd);
7000         if (!hba->req_abort_count) {
7001                 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag);
7002                 ufshcd_print_evt_hist(hba);
7003                 ufshcd_print_host_state(hba);
7004                 ufshcd_print_pwr_info(hba);
7005                 ufshcd_print_trs(hba, 1 << tag, true);
7006         } else {
7007                 ufshcd_print_trs(hba, 1 << tag, false);
7008         }
7009         hba->req_abort_count++;
7010
7011         if (!(reg & (1 << tag))) {
7012                 dev_err(hba->dev,
7013                 "%s: cmd was completed, but without a notifying intr, tag = %d",
7014                 __func__, tag);
7015                 goto cleanup;
7016         }
7017
7018         /*
7019          * Task abort to the device W-LUN is illegal. When this command
7020          * will fail, due to spec violation, scsi err handling next step
7021          * will be to send LU reset which, again, is a spec violation.
7022          * To avoid these unnecessary/illegal steps, first we clean up
7023          * the lrb taken by this cmd and mark the lrb as in_use, then
7024          * queue the eh_work and bail.
7025          */
7026         if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) {
7027                 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun);
7028                 spin_lock_irqsave(host->host_lock, flags);
7029                 if (lrbp->cmd) {
7030                         __ufshcd_transfer_req_compl(hba, (1UL << tag));
7031                         __set_bit(tag, &hba->outstanding_reqs);
7032                         lrbp->in_use = true;
7033                         hba->force_reset = true;
7034                         ufshcd_schedule_eh_work(hba);
7035                 }
7036
7037                 spin_unlock_irqrestore(host->host_lock, flags);
7038                 goto out;
7039         }
7040
7041         /* Skip task abort in case previous aborts failed and report failure */
7042         if (lrbp->req_abort_skip)
7043                 err = -EIO;
7044         else
7045                 err = ufshcd_try_to_abort_task(hba, tag);
7046
7047         if (!err) {
7048 cleanup:
7049                 spin_lock_irqsave(host->host_lock, flags);
7050                 __ufshcd_transfer_req_compl(hba, (1UL << tag));
7051                 spin_unlock_irqrestore(host->host_lock, flags);
7052 out:
7053                 err = SUCCESS;
7054         } else {
7055                 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
7056                 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7057                 err = FAILED;
7058         }
7059
7060         /*
7061          * This ufshcd_release() corresponds to the original scsi cmd that got
7062          * aborted here (as we won't get any IRQ for it).
7063          */
7064         ufshcd_release(hba);
7065         return err;
7066 }
7067
7068 /**
7069  * ufshcd_host_reset_and_restore - reset and restore host controller
7070  * @hba: per-adapter instance
7071  *
7072  * Note that host controller reset may issue DME_RESET to
7073  * local and remote (device) Uni-Pro stack and the attributes
7074  * are reset to default state.
7075  *
7076  * Returns zero on success, non-zero on failure
7077  */
7078 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
7079 {
7080         int err;
7081         unsigned long flags;
7082
7083         /*
7084          * Stop the host controller and complete the requests
7085          * cleared by h/w
7086          */
7087         ufshcd_hba_stop(hba);
7088
7089         spin_lock_irqsave(hba->host->host_lock, flags);
7090         hba->silence_err_logs = true;
7091         ufshcd_complete_requests(hba);
7092         hba->silence_err_logs = false;
7093         spin_unlock_irqrestore(hba->host->host_lock, flags);
7094
7095         /* scale up clocks to max frequency before full reinitialization */
7096         ufshcd_set_clk_freq(hba, true);
7097
7098         err = ufshcd_hba_enable(hba);
7099
7100         /* Establish the link again and restore the device */
7101         if (!err)
7102                 err = ufshcd_probe_hba(hba, false);
7103
7104         if (err)
7105                 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
7106         ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err);
7107         return err;
7108 }
7109
7110 /**
7111  * ufshcd_reset_and_restore - reset and re-initialize host/device
7112  * @hba: per-adapter instance
7113  *
7114  * Reset and recover device, host and re-establish link. This
7115  * is helpful to recover the communication in fatal error conditions.
7116  *
7117  * Returns zero on success, non-zero on failure
7118  */
7119 static int ufshcd_reset_and_restore(struct ufs_hba *hba)
7120 {
7121         u32 saved_err;
7122         u32 saved_uic_err;
7123         int err = 0;
7124         unsigned long flags;
7125         int retries = MAX_HOST_RESET_RETRIES;
7126
7127         /*
7128          * This is a fresh start, cache and clear saved error first,
7129          * in case new error generated during reset and restore.
7130          */
7131         spin_lock_irqsave(hba->host->host_lock, flags);
7132         saved_err = hba->saved_err;
7133         saved_uic_err = hba->saved_uic_err;
7134         hba->saved_err = 0;
7135         hba->saved_uic_err = 0;
7136         spin_unlock_irqrestore(hba->host->host_lock, flags);
7137
7138         do {
7139                 /* Reset the attached device */
7140                 ufshcd_device_reset(hba);
7141
7142                 err = ufshcd_host_reset_and_restore(hba);
7143         } while (err && --retries);
7144
7145         spin_lock_irqsave(hba->host->host_lock, flags);
7146         /*
7147          * Inform scsi mid-layer that we did reset and allow to handle
7148          * Unit Attention properly.
7149          */
7150         scsi_report_bus_reset(hba->host, 0);
7151         if (err) {
7152                 hba->ufshcd_state = UFSHCD_STATE_ERROR;
7153                 hba->saved_err |= saved_err;
7154                 hba->saved_uic_err |= saved_uic_err;
7155         }
7156         spin_unlock_irqrestore(hba->host->host_lock, flags);
7157
7158         return err;
7159 }
7160
7161 /**
7162  * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
7163  * @cmd: SCSI command pointer
7164  *
7165  * Returns SUCCESS/FAILED
7166  */
7167 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
7168 {
7169         int err = SUCCESS;
7170         unsigned long flags;
7171         struct ufs_hba *hba;
7172
7173         hba = shost_priv(cmd->device->host);
7174
7175         spin_lock_irqsave(hba->host->host_lock, flags);
7176         hba->force_reset = true;
7177         ufshcd_schedule_eh_work(hba);
7178         dev_err(hba->dev, "%s: reset in progress - 1\n", __func__);
7179         spin_unlock_irqrestore(hba->host->host_lock, flags);
7180
7181         flush_work(&hba->eh_work);
7182
7183         spin_lock_irqsave(hba->host->host_lock, flags);
7184         if (hba->ufshcd_state == UFSHCD_STATE_ERROR)
7185                 err = FAILED;
7186         spin_unlock_irqrestore(hba->host->host_lock, flags);
7187
7188         return err;
7189 }
7190
7191 /**
7192  * ufshcd_get_max_icc_level - calculate the ICC level
7193  * @sup_curr_uA: max. current supported by the regulator
7194  * @start_scan: row at the desc table to start scan from
7195  * @buff: power descriptor buffer
7196  *
7197  * Returns calculated max ICC level for specific regulator
7198  */
7199 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
7200 {
7201         int i;
7202         int curr_uA;
7203         u16 data;
7204         u16 unit;
7205
7206         for (i = start_scan; i >= 0; i--) {
7207                 data = be16_to_cpup((__be16 *)&buff[2 * i]);
7208                 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
7209                                                 ATTR_ICC_LVL_UNIT_OFFSET;
7210                 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
7211                 switch (unit) {
7212                 case UFSHCD_NANO_AMP:
7213                         curr_uA = curr_uA / 1000;
7214                         break;
7215                 case UFSHCD_MILI_AMP:
7216                         curr_uA = curr_uA * 1000;
7217                         break;
7218                 case UFSHCD_AMP:
7219                         curr_uA = curr_uA * 1000 * 1000;
7220                         break;
7221                 case UFSHCD_MICRO_AMP:
7222                 default:
7223                         break;
7224                 }
7225                 if (sup_curr_uA >= curr_uA)
7226                         break;
7227         }
7228         if (i < 0) {
7229                 i = 0;
7230                 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
7231         }
7232
7233         return (u32)i;
7234 }
7235
7236 /**
7237  * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level
7238  * In case regulators are not initialized we'll return 0
7239  * @hba: per-adapter instance
7240  * @desc_buf: power descriptor buffer to extract ICC levels from.
7241  * @len: length of desc_buff
7242  *
7243  * Returns calculated ICC level
7244  */
7245 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
7246                                                         u8 *desc_buf, int len)
7247 {
7248         u32 icc_level = 0;
7249
7250         if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
7251                                                 !hba->vreg_info.vccq2) {
7252                 dev_err(hba->dev,
7253                         "%s: Regulator capability was not set, actvIccLevel=%d",
7254                                                         __func__, icc_level);
7255                 goto out;
7256         }
7257
7258         if (hba->vreg_info.vcc->max_uA)
7259                 icc_level = ufshcd_get_max_icc_level(
7260                                 hba->vreg_info.vcc->max_uA,
7261                                 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
7262                                 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
7263
7264         if (hba->vreg_info.vccq->max_uA)
7265                 icc_level = ufshcd_get_max_icc_level(
7266                                 hba->vreg_info.vccq->max_uA,
7267                                 icc_level,
7268                                 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
7269
7270         if (hba->vreg_info.vccq2->max_uA)
7271                 icc_level = ufshcd_get_max_icc_level(
7272                                 hba->vreg_info.vccq2->max_uA,
7273                                 icc_level,
7274                                 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
7275 out:
7276         return icc_level;
7277 }
7278
7279 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba)
7280 {
7281         int ret;
7282         int buff_len = hba->desc_size[QUERY_DESC_IDN_POWER];
7283         u8 *desc_buf;
7284         u32 icc_level;
7285
7286         desc_buf = kmalloc(buff_len, GFP_KERNEL);
7287         if (!desc_buf)
7288                 return;
7289
7290         ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0,
7291                                      desc_buf, buff_len);
7292         if (ret) {
7293                 dev_err(hba->dev,
7294                         "%s: Failed reading power descriptor.len = %d ret = %d",
7295                         __func__, buff_len, ret);
7296                 goto out;
7297         }
7298
7299         icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf,
7300                                                          buff_len);
7301         dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level);
7302
7303         ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
7304                 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
7305
7306         if (ret)
7307                 dev_err(hba->dev,
7308                         "%s: Failed configuring bActiveICCLevel = %d ret = %d",
7309                         __func__, icc_level, ret);
7310
7311 out:
7312         kfree(desc_buf);
7313 }
7314
7315 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev)
7316 {
7317         scsi_autopm_get_device(sdev);
7318         blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev);
7319         if (sdev->rpm_autosuspend)
7320                 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev,
7321                                                  RPM_AUTOSUSPEND_DELAY_MS);
7322         scsi_autopm_put_device(sdev);
7323 }
7324
7325 /**
7326  * ufshcd_scsi_add_wlus - Adds required W-LUs
7327  * @hba: per-adapter instance
7328  *
7329  * UFS device specification requires the UFS devices to support 4 well known
7330  * logical units:
7331  *      "REPORT_LUNS" (address: 01h)
7332  *      "UFS Device" (address: 50h)
7333  *      "RPMB" (address: 44h)
7334  *      "BOOT" (address: 30h)
7335  * UFS device's power management needs to be controlled by "POWER CONDITION"
7336  * field of SSU (START STOP UNIT) command. But this "power condition" field
7337  * will take effect only when its sent to "UFS device" well known logical unit
7338  * hence we require the scsi_device instance to represent this logical unit in
7339  * order for the UFS host driver to send the SSU command for power management.
7340  *
7341  * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
7342  * Block) LU so user space process can control this LU. User space may also
7343  * want to have access to BOOT LU.
7344  *
7345  * This function adds scsi device instances for each of all well known LUs
7346  * (except "REPORT LUNS" LU).
7347  *
7348  * Returns zero on success (all required W-LUs are added successfully),
7349  * non-zero error value on failure (if failed to add any of the required W-LU).
7350  */
7351 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
7352 {
7353         int ret = 0;
7354         struct scsi_device *sdev_boot;
7355
7356         hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
7357                 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
7358         if (IS_ERR(hba->sdev_ufs_device)) {
7359                 ret = PTR_ERR(hba->sdev_ufs_device);
7360                 hba->sdev_ufs_device = NULL;
7361                 goto out;
7362         }
7363         scsi_device_put(hba->sdev_ufs_device);
7364
7365         hba->sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
7366                 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7367         if (IS_ERR(hba->sdev_rpmb)) {
7368                 ret = PTR_ERR(hba->sdev_rpmb);
7369                 goto remove_sdev_ufs_device;
7370         }
7371         ufshcd_blk_pm_runtime_init(hba->sdev_rpmb);
7372         scsi_device_put(hba->sdev_rpmb);
7373
7374         sdev_boot = __scsi_add_device(hba->host, 0, 0,
7375                 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7376         if (IS_ERR(sdev_boot)) {
7377                 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
7378         } else {
7379                 ufshcd_blk_pm_runtime_init(sdev_boot);
7380                 scsi_device_put(sdev_boot);
7381         }
7382         goto out;
7383
7384 remove_sdev_ufs_device:
7385         scsi_remove_device(hba->sdev_ufs_device);
7386 out:
7387         return ret;
7388 }
7389
7390 static void ufshcd_wb_probe(struct ufs_hba *hba, u8 *desc_buf)
7391 {
7392         struct ufs_dev_info *dev_info = &hba->dev_info;
7393         u8 lun;
7394         u32 d_lu_wb_buf_alloc;
7395         u32 ext_ufs_feature;
7396
7397         if (!ufshcd_is_wb_allowed(hba))
7398                 return;
7399         /*
7400          * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or
7401          * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES
7402          * enabled
7403          */
7404         if (!(dev_info->wspecversion >= 0x310 ||
7405               dev_info->wspecversion == 0x220 ||
7406              (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES)))
7407                 goto wb_disabled;
7408
7409         if (hba->desc_size[QUERY_DESC_IDN_DEVICE] <
7410             DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP + 4)
7411                 goto wb_disabled;
7412
7413         ext_ufs_feature = get_unaligned_be32(desc_buf +
7414                                         DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
7415
7416         if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP))
7417                 goto wb_disabled;
7418
7419         /*
7420          * WB may be supported but not configured while provisioning. The spec
7421          * says, in dedicated wb buffer mode, a max of 1 lun would have wb
7422          * buffer configured.
7423          */
7424         dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE];
7425
7426         dev_info->b_presrv_uspc_en =
7427                 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN];
7428
7429         if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) {
7430                 if (!get_unaligned_be32(desc_buf +
7431                                    DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS))
7432                         goto wb_disabled;
7433         } else {
7434                 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) {
7435                         d_lu_wb_buf_alloc = 0;
7436                         ufshcd_read_unit_desc_param(hba,
7437                                         lun,
7438                                         UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS,
7439                                         (u8 *)&d_lu_wb_buf_alloc,
7440                                         sizeof(d_lu_wb_buf_alloc));
7441                         if (d_lu_wb_buf_alloc) {
7442                                 dev_info->wb_dedicated_lu = lun;
7443                                 break;
7444                         }
7445                 }
7446
7447                 if (!d_lu_wb_buf_alloc)
7448                         goto wb_disabled;
7449         }
7450         return;
7451
7452 wb_disabled:
7453         hba->caps &= ~UFSHCD_CAP_WB_EN;
7454 }
7455
7456 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, struct ufs_dev_fix *fixups)
7457 {
7458         struct ufs_dev_fix *f;
7459         struct ufs_dev_info *dev_info = &hba->dev_info;
7460
7461         if (!fixups)
7462                 return;
7463
7464         for (f = fixups; f->quirk; f++) {
7465                 if ((f->wmanufacturerid == dev_info->wmanufacturerid ||
7466                      f->wmanufacturerid == UFS_ANY_VENDOR) &&
7467                      ((dev_info->model &&
7468                        STR_PRFX_EQUAL(f->model, dev_info->model)) ||
7469                       !strcmp(f->model, UFS_ANY_MODEL)))
7470                         hba->dev_quirks |= f->quirk;
7471         }
7472 }
7473 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks);
7474
7475 static void ufs_fixup_device_setup(struct ufs_hba *hba)
7476 {
7477         /* fix by general quirk table */
7478         ufshcd_fixup_dev_quirks(hba, ufs_fixups);
7479
7480         /* allow vendors to fix quirks */
7481         ufshcd_vops_fixup_dev_quirks(hba);
7482 }
7483
7484 static int ufs_get_device_desc(struct ufs_hba *hba)
7485 {
7486         int err;
7487         u8 model_index;
7488         u8 *desc_buf;
7489         struct ufs_dev_info *dev_info = &hba->dev_info;
7490
7491         desc_buf = kmalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
7492         if (!desc_buf) {
7493                 err = -ENOMEM;
7494                 goto out;
7495         }
7496
7497         err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf,
7498                                      hba->desc_size[QUERY_DESC_IDN_DEVICE]);
7499         if (err) {
7500                 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
7501                         __func__, err);
7502                 goto out;
7503         }
7504
7505         /*
7506          * getting vendor (manufacturerID) and Bank Index in big endian
7507          * format
7508          */
7509         dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
7510                                      desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
7511
7512         /* getting Specification Version in big endian format */
7513         dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
7514                                       desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
7515
7516         model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
7517
7518         err = ufshcd_read_string_desc(hba, model_index,
7519                                       &dev_info->model, SD_ASCII_STD);
7520         if (err < 0) {
7521                 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
7522                         __func__, err);
7523                 goto out;
7524         }
7525
7526         hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] +
7527                 desc_buf[DEVICE_DESC_PARAM_NUM_WLU];
7528
7529         ufs_fixup_device_setup(hba);
7530
7531         ufshcd_wb_probe(hba, desc_buf);
7532
7533         /*
7534          * ufshcd_read_string_desc returns size of the string
7535          * reset the error value
7536          */
7537         err = 0;
7538
7539 out:
7540         kfree(desc_buf);
7541         return err;
7542 }
7543
7544 static void ufs_put_device_desc(struct ufs_hba *hba)
7545 {
7546         struct ufs_dev_info *dev_info = &hba->dev_info;
7547
7548         kfree(dev_info->model);
7549         dev_info->model = NULL;
7550 }
7551
7552 /**
7553  * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
7554  * @hba: per-adapter instance
7555  *
7556  * PA_TActivate parameter can be tuned manually if UniPro version is less than
7557  * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
7558  * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
7559  * the hibern8 exit latency.
7560  *
7561  * Returns zero on success, non-zero error value on failure.
7562  */
7563 static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
7564 {
7565         int ret = 0;
7566         u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
7567
7568         ret = ufshcd_dme_peer_get(hba,
7569                                   UIC_ARG_MIB_SEL(
7570                                         RX_MIN_ACTIVATETIME_CAPABILITY,
7571                                         UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7572                                   &peer_rx_min_activatetime);
7573         if (ret)
7574                 goto out;
7575
7576         /* make sure proper unit conversion is applied */
7577         tuned_pa_tactivate =
7578                 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
7579                  / PA_TACTIVATE_TIME_UNIT_US);
7580         ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7581                              tuned_pa_tactivate);
7582
7583 out:
7584         return ret;
7585 }
7586
7587 /**
7588  * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
7589  * @hba: per-adapter instance
7590  *
7591  * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
7592  * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
7593  * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
7594  * This optimal value can help reduce the hibern8 exit latency.
7595  *
7596  * Returns zero on success, non-zero error value on failure.
7597  */
7598 static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
7599 {
7600         int ret = 0;
7601         u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
7602         u32 max_hibern8_time, tuned_pa_hibern8time;
7603
7604         ret = ufshcd_dme_get(hba,
7605                              UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
7606                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
7607                                   &local_tx_hibern8_time_cap);
7608         if (ret)
7609                 goto out;
7610
7611         ret = ufshcd_dme_peer_get(hba,
7612                                   UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
7613                                         UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7614                                   &peer_rx_hibern8_time_cap);
7615         if (ret)
7616                 goto out;
7617
7618         max_hibern8_time = max(local_tx_hibern8_time_cap,
7619                                peer_rx_hibern8_time_cap);
7620         /* make sure proper unit conversion is applied */
7621         tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
7622                                 / PA_HIBERN8_TIME_UNIT_US);
7623         ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
7624                              tuned_pa_hibern8time);
7625 out:
7626         return ret;
7627 }
7628
7629 /**
7630  * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
7631  * less than device PA_TACTIVATE time.
7632  * @hba: per-adapter instance
7633  *
7634  * Some UFS devices require host PA_TACTIVATE to be lower than device
7635  * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
7636  * for such devices.
7637  *
7638  * Returns zero on success, non-zero error value on failure.
7639  */
7640 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
7641 {
7642         int ret = 0;
7643         u32 granularity, peer_granularity;
7644         u32 pa_tactivate, peer_pa_tactivate;
7645         u32 pa_tactivate_us, peer_pa_tactivate_us;
7646         u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
7647
7648         ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7649                                   &granularity);
7650         if (ret)
7651                 goto out;
7652
7653         ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7654                                   &peer_granularity);
7655         if (ret)
7656                 goto out;
7657
7658         if ((granularity < PA_GRANULARITY_MIN_VAL) ||
7659             (granularity > PA_GRANULARITY_MAX_VAL)) {
7660                 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
7661                         __func__, granularity);
7662                 return -EINVAL;
7663         }
7664
7665         if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
7666             (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
7667                 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
7668                         __func__, peer_granularity);
7669                 return -EINVAL;
7670         }
7671
7672         ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
7673         if (ret)
7674                 goto out;
7675
7676         ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
7677                                   &peer_pa_tactivate);
7678         if (ret)
7679                 goto out;
7680
7681         pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
7682         peer_pa_tactivate_us = peer_pa_tactivate *
7683                              gran_to_us_table[peer_granularity - 1];
7684
7685         if (pa_tactivate_us > peer_pa_tactivate_us) {
7686                 u32 new_peer_pa_tactivate;
7687
7688                 new_peer_pa_tactivate = pa_tactivate_us /
7689                                       gran_to_us_table[peer_granularity - 1];
7690                 new_peer_pa_tactivate++;
7691                 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7692                                           new_peer_pa_tactivate);
7693         }
7694
7695 out:
7696         return ret;
7697 }
7698
7699 static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
7700 {
7701         if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
7702                 ufshcd_tune_pa_tactivate(hba);
7703                 ufshcd_tune_pa_hibern8time(hba);
7704         }
7705
7706         ufshcd_vops_apply_dev_quirks(hba);
7707
7708         if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
7709                 /* set 1ms timeout for PA_TACTIVATE */
7710                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
7711
7712         if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
7713                 ufshcd_quirk_tune_host_pa_tactivate(hba);
7714 }
7715
7716 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
7717 {
7718         hba->ufs_stats.hibern8_exit_cnt = 0;
7719         hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
7720         hba->req_abort_count = 0;
7721 }
7722
7723 static int ufshcd_device_geo_params_init(struct ufs_hba *hba)
7724 {
7725         int err;
7726         size_t buff_len;
7727         u8 *desc_buf;
7728
7729         buff_len = hba->desc_size[QUERY_DESC_IDN_GEOMETRY];
7730         desc_buf = kmalloc(buff_len, GFP_KERNEL);
7731         if (!desc_buf) {
7732                 err = -ENOMEM;
7733                 goto out;
7734         }
7735
7736         err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0,
7737                                      desc_buf, buff_len);
7738         if (err) {
7739                 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n",
7740                                 __func__, err);
7741                 goto out;
7742         }
7743
7744         if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1)
7745                 hba->dev_info.max_lu_supported = 32;
7746         else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0)
7747                 hba->dev_info.max_lu_supported = 8;
7748
7749 out:
7750         kfree(desc_buf);
7751         return err;
7752 }
7753
7754 static struct ufs_ref_clk ufs_ref_clk_freqs[] = {
7755         {19200000, REF_CLK_FREQ_19_2_MHZ},
7756         {26000000, REF_CLK_FREQ_26_MHZ},
7757         {38400000, REF_CLK_FREQ_38_4_MHZ},
7758         {52000000, REF_CLK_FREQ_52_MHZ},
7759         {0, REF_CLK_FREQ_INVAL},
7760 };
7761
7762 static enum ufs_ref_clk_freq
7763 ufs_get_bref_clk_from_hz(unsigned long freq)
7764 {
7765         int i;
7766
7767         for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
7768                 if (ufs_ref_clk_freqs[i].freq_hz == freq)
7769                         return ufs_ref_clk_freqs[i].val;
7770
7771         return REF_CLK_FREQ_INVAL;
7772 }
7773
7774 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
7775 {
7776         unsigned long freq;
7777
7778         freq = clk_get_rate(refclk);
7779
7780         hba->dev_ref_clk_freq =
7781                 ufs_get_bref_clk_from_hz(freq);
7782
7783         if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
7784                 dev_err(hba->dev,
7785                 "invalid ref_clk setting = %ld\n", freq);
7786 }
7787
7788 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
7789 {
7790         int err;
7791         u32 ref_clk;
7792         u32 freq = hba->dev_ref_clk_freq;
7793
7794         err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
7795                         QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
7796
7797         if (err) {
7798                 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
7799                         err);
7800                 goto out;
7801         }
7802
7803         if (ref_clk == freq)
7804                 goto out; /* nothing to update */
7805
7806         err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
7807                         QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
7808
7809         if (err) {
7810                 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
7811                         ufs_ref_clk_freqs[freq].freq_hz);
7812                 goto out;
7813         }
7814
7815         dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
7816                         ufs_ref_clk_freqs[freq].freq_hz);
7817
7818 out:
7819         return err;
7820 }
7821
7822 static int ufshcd_device_params_init(struct ufs_hba *hba)
7823 {
7824         bool flag;
7825         int ret, i;
7826
7827          /* Init device descriptor sizes */
7828         for (i = 0; i < QUERY_DESC_IDN_MAX; i++)
7829                 hba->desc_size[i] = QUERY_DESC_MAX_SIZE;
7830
7831         /* Init UFS geometry descriptor related parameters */
7832         ret = ufshcd_device_geo_params_init(hba);
7833         if (ret)
7834                 goto out;
7835
7836         /* Check and apply UFS device quirks */
7837         ret = ufs_get_device_desc(hba);
7838         if (ret) {
7839                 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
7840                         __func__, ret);
7841                 goto out;
7842         }
7843
7844         ufshcd_get_ref_clk_gating_wait(hba);
7845
7846         if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
7847                         QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag))
7848                 hba->dev_info.f_power_on_wp_en = flag;
7849
7850         /* Probe maximum power mode co-supported by both UFS host and device */
7851         if (ufshcd_get_max_pwr_mode(hba))
7852                 dev_err(hba->dev,
7853                         "%s: Failed getting max supported power mode\n",
7854                         __func__);
7855 out:
7856         return ret;
7857 }
7858
7859 /**
7860  * ufshcd_add_lus - probe and add UFS logical units
7861  * @hba: per-adapter instance
7862  */
7863 static int ufshcd_add_lus(struct ufs_hba *hba)
7864 {
7865         int ret;
7866
7867         /* Add required well known logical units to scsi mid layer */
7868         ret = ufshcd_scsi_add_wlus(hba);
7869         if (ret)
7870                 goto out;
7871
7872         ufshcd_clear_ua_wluns(hba);
7873
7874         /* Initialize devfreq after UFS device is detected */
7875         if (ufshcd_is_clkscaling_supported(hba)) {
7876                 memcpy(&hba->clk_scaling.saved_pwr_info.info,
7877                         &hba->pwr_info,
7878                         sizeof(struct ufs_pa_layer_attr));
7879                 hba->clk_scaling.saved_pwr_info.is_valid = true;
7880                 hba->clk_scaling.is_allowed = true;
7881
7882                 ret = ufshcd_devfreq_init(hba);
7883                 if (ret)
7884                         goto out;
7885
7886                 hba->clk_scaling.is_enabled = true;
7887                 ufshcd_init_clk_scaling_sysfs(hba);
7888         }
7889
7890         ufs_bsg_probe(hba);
7891         scsi_scan_host(hba->host);
7892         pm_runtime_put_sync(hba->dev);
7893
7894 out:
7895         return ret;
7896 }
7897
7898 static int
7899 ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp);
7900
7901 static int ufshcd_clear_ua_wlun(struct ufs_hba *hba, u8 wlun)
7902 {
7903         struct scsi_device *sdp;
7904         unsigned long flags;
7905         int ret = 0;
7906
7907         spin_lock_irqsave(hba->host->host_lock, flags);
7908         if (wlun == UFS_UPIU_UFS_DEVICE_WLUN)
7909                 sdp = hba->sdev_ufs_device;
7910         else if (wlun == UFS_UPIU_RPMB_WLUN)
7911                 sdp = hba->sdev_rpmb;
7912         else
7913                 BUG();
7914         if (sdp) {
7915                 ret = scsi_device_get(sdp);
7916                 if (!ret && !scsi_device_online(sdp)) {
7917                         ret = -ENODEV;
7918                         scsi_device_put(sdp);
7919                 }
7920         } else {
7921                 ret = -ENODEV;
7922         }
7923         spin_unlock_irqrestore(hba->host->host_lock, flags);
7924         if (ret)
7925                 goto out_err;
7926
7927         ret = ufshcd_send_request_sense(hba, sdp);
7928         scsi_device_put(sdp);
7929 out_err:
7930         if (ret)
7931                 dev_err(hba->dev, "%s: UAC clear LU=%x ret = %d\n",
7932                                 __func__, wlun, ret);
7933         return ret;
7934 }
7935
7936 static int ufshcd_clear_ua_wluns(struct ufs_hba *hba)
7937 {
7938         int ret = 0;
7939
7940         if (!hba->wlun_dev_clr_ua)
7941                 goto out;
7942
7943         ret = ufshcd_clear_ua_wlun(hba, UFS_UPIU_UFS_DEVICE_WLUN);
7944         if (!ret)
7945                 ret = ufshcd_clear_ua_wlun(hba, UFS_UPIU_RPMB_WLUN);
7946         if (!ret)
7947                 hba->wlun_dev_clr_ua = false;
7948 out:
7949         if (ret)
7950                 dev_err(hba->dev, "%s: Failed to clear UAC WLUNS ret = %d\n",
7951                                 __func__, ret);
7952         return ret;
7953 }
7954
7955 /**
7956  * ufshcd_probe_hba - probe hba to detect device and initialize
7957  * @hba: per-adapter instance
7958  * @async: asynchronous execution or not
7959  *
7960  * Execute link-startup and verify device initialization
7961  */
7962 static int ufshcd_probe_hba(struct ufs_hba *hba, bool async)
7963 {
7964         int ret;
7965         unsigned long flags;
7966         ktime_t start = ktime_get();
7967
7968         hba->ufshcd_state = UFSHCD_STATE_RESET;
7969
7970         ret = ufshcd_link_startup(hba);
7971         if (ret)
7972                 goto out;
7973
7974         /* Debug counters initialization */
7975         ufshcd_clear_dbg_ufs_stats(hba);
7976
7977         /* UniPro link is active now */
7978         ufshcd_set_link_active(hba);
7979
7980         /* Verify device initialization by sending NOP OUT UPIU */
7981         ret = ufshcd_verify_dev_init(hba);
7982         if (ret)
7983                 goto out;
7984
7985         /* Initiate UFS initialization, and waiting until completion */
7986         ret = ufshcd_complete_dev_init(hba);
7987         if (ret)
7988                 goto out;
7989
7990         /*
7991          * Initialize UFS device parameters used by driver, these
7992          * parameters are associated with UFS descriptors.
7993          */
7994         if (async) {
7995                 ret = ufshcd_device_params_init(hba);
7996                 if (ret)
7997                         goto out;
7998         }
7999
8000         ufshcd_tune_unipro_params(hba);
8001
8002         /* UFS device is also active now */
8003         ufshcd_set_ufs_dev_active(hba);
8004         ufshcd_force_reset_auto_bkops(hba);
8005         hba->wlun_dev_clr_ua = true;
8006         hba->wlun_rpmb_clr_ua = true;
8007
8008         /* Gear up to HS gear if supported */
8009         if (hba->max_pwr_info.is_valid) {
8010                 /*
8011                  * Set the right value to bRefClkFreq before attempting to
8012                  * switch to HS gears.
8013                  */
8014                 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
8015                         ufshcd_set_dev_ref_clk(hba);
8016                 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8017                 if (ret) {
8018                         dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
8019                                         __func__, ret);
8020                         goto out;
8021                 }
8022                 ufshcd_print_pwr_info(hba);
8023         }
8024
8025         /*
8026          * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec)
8027          * and for removable UFS card as well, hence always set the parameter.
8028          * Note: Error handler may issue the device reset hence resetting
8029          * bActiveICCLevel as well so it is always safe to set this here.
8030          */
8031         ufshcd_set_active_icc_lvl(hba);
8032
8033         ufshcd_wb_config(hba);
8034         if (hba->ee_usr_mask)
8035                 ufshcd_write_ee_control(hba);
8036         /* Enable Auto-Hibernate if configured */
8037         ufshcd_auto_hibern8_enable(hba);
8038
8039 out:
8040         spin_lock_irqsave(hba->host->host_lock, flags);
8041         if (ret)
8042                 hba->ufshcd_state = UFSHCD_STATE_ERROR;
8043         else if (hba->ufshcd_state == UFSHCD_STATE_RESET)
8044                 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
8045         spin_unlock_irqrestore(hba->host->host_lock, flags);
8046
8047         trace_ufshcd_init(dev_name(hba->dev), ret,
8048                 ktime_to_us(ktime_sub(ktime_get(), start)),
8049                 hba->curr_dev_pwr_mode, hba->uic_link_state);
8050         return ret;
8051 }
8052
8053 /**
8054  * ufshcd_async_scan - asynchronous execution for probing hba
8055  * @data: data pointer to pass to this function
8056  * @cookie: cookie data
8057  */
8058 static void ufshcd_async_scan(void *data, async_cookie_t cookie)
8059 {
8060         struct ufs_hba *hba = (struct ufs_hba *)data;
8061         int ret;
8062
8063         down(&hba->host_sem);
8064         /* Initialize hba, detect and initialize UFS device */
8065         ret = ufshcd_probe_hba(hba, true);
8066         up(&hba->host_sem);
8067         if (ret)
8068                 goto out;
8069
8070         /* Probe and add UFS logical units  */
8071         ret = ufshcd_add_lus(hba);
8072 out:
8073         /*
8074          * If we failed to initialize the device or the device is not
8075          * present, turn off the power/clocks etc.
8076          */
8077         if (ret) {
8078                 pm_runtime_put_sync(hba->dev);
8079                 ufshcd_hba_exit(hba);
8080         }
8081 }
8082
8083 static const struct attribute_group *ufshcd_driver_groups[] = {
8084         &ufs_sysfs_unit_descriptor_group,
8085         &ufs_sysfs_lun_attributes_group,
8086         NULL,
8087 };
8088
8089 static struct ufs_hba_variant_params ufs_hba_vps = {
8090         .hba_enable_delay_us            = 1000,
8091         .wb_flush_threshold             = UFS_WB_BUF_REMAIN_PERCENT(40),
8092         .devfreq_profile.polling_ms     = 100,
8093         .devfreq_profile.target         = ufshcd_devfreq_target,
8094         .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status,
8095         .ondemand_data.upthreshold      = 70,
8096         .ondemand_data.downdifferential = 5,
8097 };
8098
8099 static struct scsi_host_template ufshcd_driver_template = {
8100         .module                 = THIS_MODULE,
8101         .name                   = UFSHCD,
8102         .proc_name              = UFSHCD,
8103         .queuecommand           = ufshcd_queuecommand,
8104         .slave_alloc            = ufshcd_slave_alloc,
8105         .slave_configure        = ufshcd_slave_configure,
8106         .slave_destroy          = ufshcd_slave_destroy,
8107         .change_queue_depth     = ufshcd_change_queue_depth,
8108         .eh_abort_handler       = ufshcd_abort,
8109         .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
8110         .eh_host_reset_handler   = ufshcd_eh_host_reset_handler,
8111         .this_id                = -1,
8112         .sg_tablesize           = SG_ALL,
8113         .cmd_per_lun            = UFSHCD_CMD_PER_LUN,
8114         .can_queue              = UFSHCD_CAN_QUEUE,
8115         .max_segment_size       = PRDT_DATA_BYTE_COUNT_MAX,
8116         .max_host_blocked       = 1,
8117         .track_queue_depth      = 1,
8118         .sdev_groups            = ufshcd_driver_groups,
8119         .dma_boundary           = PAGE_SIZE - 1,
8120         .rpm_autosuspend_delay  = RPM_AUTOSUSPEND_DELAY_MS,
8121 };
8122
8123 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
8124                                    int ua)
8125 {
8126         int ret;
8127
8128         if (!vreg)
8129                 return 0;
8130
8131         /*
8132          * "set_load" operation shall be required on those regulators
8133          * which specifically configured current limitation. Otherwise
8134          * zero max_uA may cause unexpected behavior when regulator is
8135          * enabled or set as high power mode.
8136          */
8137         if (!vreg->max_uA)
8138                 return 0;
8139
8140         ret = regulator_set_load(vreg->reg, ua);
8141         if (ret < 0) {
8142                 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
8143                                 __func__, vreg->name, ua, ret);
8144         }
8145
8146         return ret;
8147 }
8148
8149 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
8150                                          struct ufs_vreg *vreg)
8151 {
8152         return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
8153 }
8154
8155 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
8156                                          struct ufs_vreg *vreg)
8157 {
8158         if (!vreg)
8159                 return 0;
8160
8161         return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
8162 }
8163
8164 static int ufshcd_config_vreg(struct device *dev,
8165                 struct ufs_vreg *vreg, bool on)
8166 {
8167         int ret = 0;
8168         struct regulator *reg;
8169         const char *name;
8170         int min_uV, uA_load;
8171
8172         BUG_ON(!vreg);
8173
8174         reg = vreg->reg;
8175         name = vreg->name;
8176
8177         if (regulator_count_voltages(reg) > 0) {
8178                 uA_load = on ? vreg->max_uA : 0;
8179                 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
8180                 if (ret)
8181                         goto out;
8182
8183                 if (vreg->min_uV && vreg->max_uV) {
8184                         min_uV = on ? vreg->min_uV : 0;
8185                         ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
8186                         if (ret)
8187                                 dev_err(dev,
8188                                         "%s: %s set voltage failed, err=%d\n",
8189                                         __func__, name, ret);
8190                 }
8191         }
8192 out:
8193         return ret;
8194 }
8195
8196 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
8197 {
8198         int ret = 0;
8199
8200         if (!vreg || vreg->enabled)
8201                 goto out;
8202
8203         ret = ufshcd_config_vreg(dev, vreg, true);
8204         if (!ret)
8205                 ret = regulator_enable(vreg->reg);
8206
8207         if (!ret)
8208                 vreg->enabled = true;
8209         else
8210                 dev_err(dev, "%s: %s enable failed, err=%d\n",
8211                                 __func__, vreg->name, ret);
8212 out:
8213         return ret;
8214 }
8215
8216 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
8217 {
8218         int ret = 0;
8219
8220         if (!vreg || !vreg->enabled || vreg->always_on)
8221                 goto out;
8222
8223         ret = regulator_disable(vreg->reg);
8224
8225         if (!ret) {
8226                 /* ignore errors on applying disable config */
8227                 ufshcd_config_vreg(dev, vreg, false);
8228                 vreg->enabled = false;
8229         } else {
8230                 dev_err(dev, "%s: %s disable failed, err=%d\n",
8231                                 __func__, vreg->name, ret);
8232         }
8233 out:
8234         return ret;
8235 }
8236
8237 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
8238 {
8239         int ret = 0;
8240         struct device *dev = hba->dev;
8241         struct ufs_vreg_info *info = &hba->vreg_info;
8242
8243         ret = ufshcd_toggle_vreg(dev, info->vcc, on);
8244         if (ret)
8245                 goto out;
8246
8247         ret = ufshcd_toggle_vreg(dev, info->vccq, on);
8248         if (ret)
8249                 goto out;
8250
8251         ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
8252
8253 out:
8254         if (ret) {
8255                 ufshcd_toggle_vreg(dev, info->vccq2, false);
8256                 ufshcd_toggle_vreg(dev, info->vccq, false);
8257                 ufshcd_toggle_vreg(dev, info->vcc, false);
8258         }
8259         return ret;
8260 }
8261
8262 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
8263 {
8264         struct ufs_vreg_info *info = &hba->vreg_info;
8265
8266         return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
8267 }
8268
8269 static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
8270 {
8271         int ret = 0;
8272
8273         if (!vreg)
8274                 goto out;
8275
8276         vreg->reg = devm_regulator_get(dev, vreg->name);
8277         if (IS_ERR(vreg->reg)) {
8278                 ret = PTR_ERR(vreg->reg);
8279                 dev_err(dev, "%s: %s get failed, err=%d\n",
8280                                 __func__, vreg->name, ret);
8281         }
8282 out:
8283         return ret;
8284 }
8285
8286 static int ufshcd_init_vreg(struct ufs_hba *hba)
8287 {
8288         int ret = 0;
8289         struct device *dev = hba->dev;
8290         struct ufs_vreg_info *info = &hba->vreg_info;
8291
8292         ret = ufshcd_get_vreg(dev, info->vcc);
8293         if (ret)
8294                 goto out;
8295
8296         ret = ufshcd_get_vreg(dev, info->vccq);
8297         if (!ret)
8298                 ret = ufshcd_get_vreg(dev, info->vccq2);
8299 out:
8300         return ret;
8301 }
8302
8303 static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
8304 {
8305         struct ufs_vreg_info *info = &hba->vreg_info;
8306
8307         if (info)
8308                 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
8309
8310         return 0;
8311 }
8312
8313 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
8314 {
8315         int ret = 0;
8316         struct ufs_clk_info *clki;
8317         struct list_head *head = &hba->clk_list_head;
8318         unsigned long flags;
8319         ktime_t start = ktime_get();
8320         bool clk_state_changed = false;
8321
8322         if (list_empty(head))
8323                 goto out;
8324
8325         ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
8326         if (ret)
8327                 return ret;
8328
8329         list_for_each_entry(clki, head, list) {
8330                 if (!IS_ERR_OR_NULL(clki->clk)) {
8331                         /*
8332                          * Don't disable clocks which are needed
8333                          * to keep the link active.
8334                          */
8335                         if (ufshcd_is_link_active(hba) &&
8336                             clki->keep_link_active)
8337                                 continue;
8338
8339                         clk_state_changed = on ^ clki->enabled;
8340                         if (on && !clki->enabled) {
8341                                 ret = clk_prepare_enable(clki->clk);
8342                                 if (ret) {
8343                                         dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
8344                                                 __func__, clki->name, ret);
8345                                         goto out;
8346                                 }
8347                         } else if (!on && clki->enabled) {
8348                                 clk_disable_unprepare(clki->clk);
8349                         }
8350                         clki->enabled = on;
8351                         dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
8352                                         clki->name, on ? "en" : "dis");
8353                 }
8354         }
8355
8356         ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
8357         if (ret)
8358                 return ret;
8359
8360 out:
8361         if (ret) {
8362                 list_for_each_entry(clki, head, list) {
8363                         if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
8364                                 clk_disable_unprepare(clki->clk);
8365                 }
8366         } else if (!ret && on) {
8367                 spin_lock_irqsave(hba->host->host_lock, flags);
8368                 hba->clk_gating.state = CLKS_ON;
8369                 trace_ufshcd_clk_gating(dev_name(hba->dev),
8370                                         hba->clk_gating.state);
8371                 spin_unlock_irqrestore(hba->host->host_lock, flags);
8372         }
8373
8374         if (clk_state_changed)
8375                 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
8376                         (on ? "on" : "off"),
8377                         ktime_to_us(ktime_sub(ktime_get(), start)), ret);
8378         return ret;
8379 }
8380
8381 static int ufshcd_init_clocks(struct ufs_hba *hba)
8382 {
8383         int ret = 0;
8384         struct ufs_clk_info *clki;
8385         struct device *dev = hba->dev;
8386         struct list_head *head = &hba->clk_list_head;
8387
8388         if (list_empty(head))
8389                 goto out;
8390
8391         list_for_each_entry(clki, head, list) {
8392                 if (!clki->name)
8393                         continue;
8394
8395                 clki->clk = devm_clk_get(dev, clki->name);
8396                 if (IS_ERR(clki->clk)) {
8397                         ret = PTR_ERR(clki->clk);
8398                         dev_err(dev, "%s: %s clk get failed, %d\n",
8399                                         __func__, clki->name, ret);
8400                         goto out;
8401                 }
8402
8403                 /*
8404                  * Parse device ref clk freq as per device tree "ref_clk".
8405                  * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
8406                  * in ufshcd_alloc_host().
8407                  */
8408                 if (!strcmp(clki->name, "ref_clk"))
8409                         ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
8410
8411                 if (clki->max_freq) {
8412                         ret = clk_set_rate(clki->clk, clki->max_freq);
8413                         if (ret) {
8414                                 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
8415                                         __func__, clki->name,
8416                                         clki->max_freq, ret);
8417                                 goto out;
8418                         }
8419                         clki->curr_freq = clki->max_freq;
8420                 }
8421                 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
8422                                 clki->name, clk_get_rate(clki->clk));
8423         }
8424 out:
8425         return ret;
8426 }
8427
8428 static int ufshcd_variant_hba_init(struct ufs_hba *hba)
8429 {
8430         int err = 0;
8431
8432         if (!hba->vops)
8433                 goto out;
8434
8435         err = ufshcd_vops_init(hba);
8436         if (err)
8437                 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
8438                         __func__, ufshcd_get_var_name(hba), err);
8439 out:
8440         return err;
8441 }
8442
8443 static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
8444 {
8445         if (!hba->vops)
8446                 return;
8447
8448         ufshcd_vops_exit(hba);
8449 }
8450
8451 static int ufshcd_hba_init(struct ufs_hba *hba)
8452 {
8453         int err;
8454
8455         /*
8456          * Handle host controller power separately from the UFS device power
8457          * rails as it will help controlling the UFS host controller power
8458          * collapse easily which is different than UFS device power collapse.
8459          * Also, enable the host controller power before we go ahead with rest
8460          * of the initialization here.
8461          */
8462         err = ufshcd_init_hba_vreg(hba);
8463         if (err)
8464                 goto out;
8465
8466         err = ufshcd_setup_hba_vreg(hba, true);
8467         if (err)
8468                 goto out;
8469
8470         err = ufshcd_init_clocks(hba);
8471         if (err)
8472                 goto out_disable_hba_vreg;
8473
8474         err = ufshcd_setup_clocks(hba, true);
8475         if (err)
8476                 goto out_disable_hba_vreg;
8477
8478         err = ufshcd_init_vreg(hba);
8479         if (err)
8480                 goto out_disable_clks;
8481
8482         err = ufshcd_setup_vreg(hba, true);
8483         if (err)
8484                 goto out_disable_clks;
8485
8486         err = ufshcd_variant_hba_init(hba);
8487         if (err)
8488                 goto out_disable_vreg;
8489
8490         ufs_debugfs_hba_init(hba);
8491
8492         hba->is_powered = true;
8493         goto out;
8494
8495 out_disable_vreg:
8496         ufshcd_setup_vreg(hba, false);
8497 out_disable_clks:
8498         ufshcd_setup_clocks(hba, false);
8499 out_disable_hba_vreg:
8500         ufshcd_setup_hba_vreg(hba, false);
8501 out:
8502         return err;
8503 }
8504
8505 static void ufshcd_hba_exit(struct ufs_hba *hba)
8506 {
8507         if (hba->is_powered) {
8508                 ufshcd_exit_clk_scaling(hba);
8509                 ufshcd_exit_clk_gating(hba);
8510                 if (hba->eh_wq)
8511                         destroy_workqueue(hba->eh_wq);
8512                 ufs_debugfs_hba_exit(hba);
8513                 ufshcd_variant_hba_exit(hba);
8514                 ufshcd_setup_vreg(hba, false);
8515                 ufshcd_setup_clocks(hba, false);
8516                 ufshcd_setup_hba_vreg(hba, false);
8517                 hba->is_powered = false;
8518                 ufs_put_device_desc(hba);
8519         }
8520 }
8521
8522 static int
8523 ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
8524 {
8525         unsigned char cmd[6] = {REQUEST_SENSE,
8526                                 0,
8527                                 0,
8528                                 0,
8529                                 UFS_SENSE_SIZE,
8530                                 0};
8531         char *buffer;
8532         int ret;
8533
8534         buffer = kzalloc(UFS_SENSE_SIZE, GFP_KERNEL);
8535         if (!buffer) {
8536                 ret = -ENOMEM;
8537                 goto out;
8538         }
8539
8540         ret = scsi_execute(sdp, cmd, DMA_FROM_DEVICE, buffer,
8541                         UFS_SENSE_SIZE, NULL, NULL,
8542                         msecs_to_jiffies(1000), 3, 0, RQF_PM, NULL);
8543         if (ret)
8544                 pr_err("%s: failed with err %d\n", __func__, ret);
8545
8546         kfree(buffer);
8547 out:
8548         return ret;
8549 }
8550
8551 /**
8552  * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
8553  *                           power mode
8554  * @hba: per adapter instance
8555  * @pwr_mode: device power mode to set
8556  *
8557  * Returns 0 if requested power mode is set successfully
8558  * Returns non-zero if failed to set the requested power mode
8559  */
8560 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
8561                                      enum ufs_dev_pwr_mode pwr_mode)
8562 {
8563         unsigned char cmd[6] = { START_STOP };
8564         struct scsi_sense_hdr sshdr;
8565         struct scsi_device *sdp;
8566         unsigned long flags;
8567         int ret;
8568
8569         spin_lock_irqsave(hba->host->host_lock, flags);
8570         sdp = hba->sdev_ufs_device;
8571         if (sdp) {
8572                 ret = scsi_device_get(sdp);
8573                 if (!ret && !scsi_device_online(sdp)) {
8574                         ret = -ENODEV;
8575                         scsi_device_put(sdp);
8576                 }
8577         } else {
8578                 ret = -ENODEV;
8579         }
8580         spin_unlock_irqrestore(hba->host->host_lock, flags);
8581
8582         if (ret)
8583                 return ret;
8584
8585         /*
8586          * If scsi commands fail, the scsi mid-layer schedules scsi error-
8587          * handling, which would wait for host to be resumed. Since we know
8588          * we are functional while we are here, skip host resume in error
8589          * handling context.
8590          */
8591         hba->host->eh_noresume = 1;
8592         if (hba->wlun_dev_clr_ua)
8593                 ufshcd_clear_ua_wlun(hba, UFS_UPIU_UFS_DEVICE_WLUN);
8594
8595         cmd[4] = pwr_mode << 4;
8596
8597         /*
8598          * Current function would be generally called from the power management
8599          * callbacks hence set the RQF_PM flag so that it doesn't resume the
8600          * already suspended childs.
8601          */
8602         ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
8603                         START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
8604         if (ret) {
8605                 sdev_printk(KERN_WARNING, sdp,
8606                             "START_STOP failed for power mode: %d, result %x\n",
8607                             pwr_mode, ret);
8608                 if (ret > 0 && scsi_sense_valid(&sshdr))
8609                         scsi_print_sense_hdr(sdp, NULL, &sshdr);
8610         }
8611
8612         if (!ret)
8613                 hba->curr_dev_pwr_mode = pwr_mode;
8614
8615         scsi_device_put(sdp);
8616         hba->host->eh_noresume = 0;
8617         return ret;
8618 }
8619
8620 static int ufshcd_link_state_transition(struct ufs_hba *hba,
8621                                         enum uic_link_state req_link_state,
8622                                         int check_for_bkops)
8623 {
8624         int ret = 0;
8625
8626         if (req_link_state == hba->uic_link_state)
8627                 return 0;
8628
8629         if (req_link_state == UIC_LINK_HIBERN8_STATE) {
8630                 ret = ufshcd_uic_hibern8_enter(hba);
8631                 if (!ret) {
8632                         ufshcd_set_link_hibern8(hba);
8633                 } else {
8634                         dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
8635                                         __func__, ret);
8636                         goto out;
8637                 }
8638         }
8639         /*
8640          * If autobkops is enabled, link can't be turned off because
8641          * turning off the link would also turn off the device, except in the
8642          * case of DeepSleep where the device is expected to remain powered.
8643          */
8644         else if ((req_link_state == UIC_LINK_OFF_STATE) &&
8645                  (!check_for_bkops || !hba->auto_bkops_enabled)) {
8646                 /*
8647                  * Let's make sure that link is in low power mode, we are doing
8648                  * this currently by putting the link in Hibern8. Otherway to
8649                  * put the link in low power mode is to send the DME end point
8650                  * to device and then send the DME reset command to local
8651                  * unipro. But putting the link in hibern8 is much faster.
8652                  *
8653                  * Note also that putting the link in Hibern8 is a requirement
8654                  * for entering DeepSleep.
8655                  */
8656                 ret = ufshcd_uic_hibern8_enter(hba);
8657                 if (ret) {
8658                         dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
8659                                         __func__, ret);
8660                         goto out;
8661                 }
8662                 /*
8663                  * Change controller state to "reset state" which
8664                  * should also put the link in off/reset state
8665                  */
8666                 ufshcd_hba_stop(hba);
8667                 /*
8668                  * TODO: Check if we need any delay to make sure that
8669                  * controller is reset
8670                  */
8671                 ufshcd_set_link_off(hba);
8672         }
8673
8674 out:
8675         return ret;
8676 }
8677
8678 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
8679 {
8680         bool vcc_off = false;
8681
8682         /*
8683          * It seems some UFS devices may keep drawing more than sleep current
8684          * (atleast for 500us) from UFS rails (especially from VCCQ rail).
8685          * To avoid this situation, add 2ms delay before putting these UFS
8686          * rails in LPM mode.
8687          */
8688         if (!ufshcd_is_link_active(hba) &&
8689             hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
8690                 usleep_range(2000, 2100);
8691
8692         /*
8693          * If UFS device is either in UFS_Sleep turn off VCC rail to save some
8694          * power.
8695          *
8696          * If UFS device and link is in OFF state, all power supplies (VCC,
8697          * VCCQ, VCCQ2) can be turned off if power on write protect is not
8698          * required. If UFS link is inactive (Hibern8 or OFF state) and device
8699          * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
8700          *
8701          * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
8702          * in low power state which would save some power.
8703          *
8704          * If Write Booster is enabled and the device needs to flush the WB
8705          * buffer OR if bkops status is urgent for WB, keep Vcc on.
8706          */
8707         if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8708             !hba->dev_info.is_lu_power_on_wp) {
8709                 ufshcd_setup_vreg(hba, false);
8710                 vcc_off = true;
8711         } else if (!ufshcd_is_ufs_dev_active(hba)) {
8712                 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
8713                 vcc_off = true;
8714                 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) {
8715                         ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8716                         ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
8717                 }
8718         }
8719
8720         /*
8721          * Some UFS devices require delay after VCC power rail is turned-off.
8722          */
8723         if (vcc_off && hba->vreg_info.vcc &&
8724                 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)
8725                 usleep_range(5000, 5100);
8726 }
8727
8728 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
8729 {
8730         int ret = 0;
8731
8732         if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8733             !hba->dev_info.is_lu_power_on_wp) {
8734                 ret = ufshcd_setup_vreg(hba, true);
8735         } else if (!ufshcd_is_ufs_dev_active(hba)) {
8736                 if (!ufshcd_is_link_active(hba)) {
8737                         ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
8738                         if (ret)
8739                                 goto vcc_disable;
8740                         ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
8741                         if (ret)
8742                                 goto vccq_lpm;
8743                 }
8744                 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
8745         }
8746         goto out;
8747
8748 vccq_lpm:
8749         ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8750 vcc_disable:
8751         ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
8752 out:
8753         return ret;
8754 }
8755
8756 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
8757 {
8758         if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
8759                 ufshcd_setup_hba_vreg(hba, false);
8760 }
8761
8762 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
8763 {
8764         if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
8765                 ufshcd_setup_hba_vreg(hba, true);
8766 }
8767
8768 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
8769 {
8770         int ret = 0;
8771         int check_for_bkops;
8772         enum ufs_pm_level pm_lvl;
8773         enum ufs_dev_pwr_mode req_dev_pwr_mode;
8774         enum uic_link_state req_link_state;
8775
8776         hba->pm_op_in_progress = true;
8777         if (pm_op != UFS_SHUTDOWN_PM) {
8778                 pm_lvl = pm_op == UFS_RUNTIME_PM ?
8779                          hba->rpm_lvl : hba->spm_lvl;
8780                 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
8781                 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
8782         } else {
8783                 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
8784                 req_link_state = UIC_LINK_OFF_STATE;
8785         }
8786
8787         /*
8788          * If we can't transition into any of the low power modes
8789          * just gate the clocks.
8790          */
8791         ufshcd_hold(hba, false);
8792         hba->clk_gating.is_suspended = true;
8793
8794         if (ufshcd_is_clkscaling_supported(hba))
8795                 ufshcd_clk_scaling_suspend(hba, true);
8796
8797         if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
8798                         req_link_state == UIC_LINK_ACTIVE_STATE) {
8799                 goto vops_suspend;
8800         }
8801
8802         if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
8803             (req_link_state == hba->uic_link_state))
8804                 goto enable_scaling;
8805
8806         /* UFS device & link must be active before we enter in this function */
8807         if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
8808                 ret = -EINVAL;
8809                 goto enable_scaling;
8810         }
8811
8812         if (pm_op == UFS_RUNTIME_PM) {
8813                 if (ufshcd_can_autobkops_during_suspend(hba)) {
8814                         /*
8815                          * The device is idle with no requests in the queue,
8816                          * allow background operations if bkops status shows
8817                          * that performance might be impacted.
8818                          */
8819                         ret = ufshcd_urgent_bkops(hba);
8820                         if (ret)
8821                                 goto enable_scaling;
8822                 } else {
8823                         /* make sure that auto bkops is disabled */
8824                         ufshcd_disable_auto_bkops(hba);
8825                 }
8826                 /*
8827                  * If device needs to do BKOP or WB buffer flush during
8828                  * Hibern8, keep device power mode as "active power mode"
8829                  * and VCC supply.
8830                  */
8831                 hba->dev_info.b_rpm_dev_flush_capable =
8832                         hba->auto_bkops_enabled ||
8833                         (((req_link_state == UIC_LINK_HIBERN8_STATE) ||
8834                         ((req_link_state == UIC_LINK_ACTIVE_STATE) &&
8835                         ufshcd_is_auto_hibern8_enabled(hba))) &&
8836                         ufshcd_wb_need_flush(hba));
8837         }
8838
8839         flush_work(&hba->eeh_work);
8840
8841         if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {
8842                 if (pm_op != UFS_RUNTIME_PM)
8843                         /* ensure that bkops is disabled */
8844                         ufshcd_disable_auto_bkops(hba);
8845
8846                 if (!hba->dev_info.b_rpm_dev_flush_capable) {
8847                         ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
8848                         if (ret)
8849                                 goto enable_scaling;
8850                 }
8851         }
8852
8853         /*
8854          * In the case of DeepSleep, the device is expected to remain powered
8855          * with the link off, so do not check for bkops.
8856          */
8857         check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba);
8858         ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops);
8859         if (ret)
8860                 goto set_dev_active;
8861
8862 vops_suspend:
8863         /*
8864          * Call vendor specific suspend callback. As these callbacks may access
8865          * vendor specific host controller register space call them before the
8866          * host clocks are ON.
8867          */
8868         ret = ufshcd_vops_suspend(hba, pm_op);
8869         if (ret)
8870                 goto set_link_active;
8871         goto out;
8872
8873 set_link_active:
8874         /*
8875          * Device hardware reset is required to exit DeepSleep. Also, for
8876          * DeepSleep, the link is off so host reset and restore will be done
8877          * further below.
8878          */
8879         if (ufshcd_is_ufs_dev_deepsleep(hba)) {
8880                 ufshcd_device_reset(hba);
8881                 WARN_ON(!ufshcd_is_link_off(hba));
8882         }
8883         if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
8884                 ufshcd_set_link_active(hba);
8885         else if (ufshcd_is_link_off(hba))
8886                 ufshcd_host_reset_and_restore(hba);
8887 set_dev_active:
8888         /* Can also get here needing to exit DeepSleep */
8889         if (ufshcd_is_ufs_dev_deepsleep(hba)) {
8890                 ufshcd_device_reset(hba);
8891                 ufshcd_host_reset_and_restore(hba);
8892         }
8893         if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
8894                 ufshcd_disable_auto_bkops(hba);
8895 enable_scaling:
8896         if (ufshcd_is_clkscaling_supported(hba))
8897                 ufshcd_clk_scaling_suspend(hba, false);
8898
8899         hba->dev_info.b_rpm_dev_flush_capable = false;
8900 out:
8901         if (hba->dev_info.b_rpm_dev_flush_capable) {
8902                 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work,
8903                         msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS));
8904         }
8905
8906         if (ret) {
8907                 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret);
8908                 hba->clk_gating.is_suspended = false;
8909                 ufshcd_release(hba);
8910         }
8911         hba->pm_op_in_progress = false;
8912         return ret;
8913 }
8914
8915 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
8916 {
8917         int ret;
8918         enum uic_link_state old_link_state = hba->uic_link_state;
8919
8920         hba->pm_op_in_progress = true;
8921
8922         /*
8923          * Call vendor specific resume callback. As these callbacks may access
8924          * vendor specific host controller register space call them when the
8925          * host clocks are ON.
8926          */
8927         ret = ufshcd_vops_resume(hba, pm_op);
8928         if (ret)
8929                 goto out;
8930
8931         /* For DeepSleep, the only supported option is to have the link off */
8932         WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba));
8933
8934         if (ufshcd_is_link_hibern8(hba)) {
8935                 ret = ufshcd_uic_hibern8_exit(hba);
8936                 if (!ret) {
8937                         ufshcd_set_link_active(hba);
8938                 } else {
8939                         dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
8940                                         __func__, ret);
8941                         goto vendor_suspend;
8942                 }
8943         } else if (ufshcd_is_link_off(hba)) {
8944                 /*
8945                  * A full initialization of the host and the device is
8946                  * required since the link was put to off during suspend.
8947                  * Note, in the case of DeepSleep, the device will exit
8948                  * DeepSleep due to device reset.
8949                  */
8950                 ret = ufshcd_reset_and_restore(hba);
8951                 /*
8952                  * ufshcd_reset_and_restore() should have already
8953                  * set the link state as active
8954                  */
8955                 if (ret || !ufshcd_is_link_active(hba))
8956                         goto vendor_suspend;
8957         }
8958
8959         if (!ufshcd_is_ufs_dev_active(hba)) {
8960                 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
8961                 if (ret)
8962                         goto set_old_link_state;
8963         }
8964
8965         if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
8966                 ufshcd_enable_auto_bkops(hba);
8967         else
8968                 /*
8969                  * If BKOPs operations are urgently needed at this moment then
8970                  * keep auto-bkops enabled or else disable it.
8971                  */
8972                 ufshcd_urgent_bkops(hba);
8973
8974         if (hba->ee_usr_mask)
8975                 ufshcd_write_ee_control(hba);
8976
8977         if (ufshcd_is_clkscaling_supported(hba))
8978                 ufshcd_clk_scaling_suspend(hba, false);
8979
8980         if (hba->dev_info.b_rpm_dev_flush_capable) {
8981                 hba->dev_info.b_rpm_dev_flush_capable = false;
8982                 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work);
8983         }
8984
8985         /* Enable Auto-Hibernate if configured */
8986         ufshcd_auto_hibern8_enable(hba);
8987         goto out;
8988
8989 set_old_link_state:
8990         ufshcd_link_state_transition(hba, old_link_state, 0);
8991 vendor_suspend:
8992         ufshcd_vops_suspend(hba, pm_op);
8993 out:
8994         if (ret)
8995                 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret);
8996         hba->clk_gating.is_suspended = false;
8997         ufshcd_release(hba);
8998         hba->pm_op_in_progress = false;
8999         return ret;
9000 }
9001
9002 static int ufshcd_wl_runtime_suspend(struct device *dev)
9003 {
9004         struct scsi_device *sdev = to_scsi_device(dev);
9005         struct ufs_hba *hba;
9006         int ret;
9007         ktime_t start = ktime_get();
9008
9009         hba = shost_priv(sdev->host);
9010
9011         ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM);
9012         if (ret)
9013                 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9014
9015         trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret,
9016                 ktime_to_us(ktime_sub(ktime_get(), start)),
9017                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9018
9019         return ret;
9020 }
9021
9022 static int ufshcd_wl_runtime_resume(struct device *dev)
9023 {
9024         struct scsi_device *sdev = to_scsi_device(dev);
9025         struct ufs_hba *hba;
9026         int ret = 0;
9027         ktime_t start = ktime_get();
9028
9029         hba = shost_priv(sdev->host);
9030
9031         ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM);
9032         if (ret)
9033                 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9034
9035         trace_ufshcd_wl_runtime_resume(dev_name(dev), ret,
9036                 ktime_to_us(ktime_sub(ktime_get(), start)),
9037                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9038
9039         return ret;
9040 }
9041
9042 #ifdef CONFIG_PM_SLEEP
9043 static int ufshcd_wl_suspend(struct device *dev)
9044 {
9045         struct scsi_device *sdev = to_scsi_device(dev);
9046         struct ufs_hba *hba;
9047         int ret = 0;
9048         ktime_t start = ktime_get();
9049
9050         hba = shost_priv(sdev->host);
9051         down(&hba->host_sem);
9052
9053         if (pm_runtime_suspended(dev))
9054                 goto out;
9055
9056         ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM);
9057         if (ret) {
9058                 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__,  ret);
9059                 up(&hba->host_sem);
9060         }
9061
9062 out:
9063         if (!ret)
9064                 hba->is_sys_suspended = true;
9065         trace_ufshcd_wl_suspend(dev_name(dev), ret,
9066                 ktime_to_us(ktime_sub(ktime_get(), start)),
9067                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9068
9069         return ret;
9070 }
9071
9072 static int ufshcd_wl_resume(struct device *dev)
9073 {
9074         struct scsi_device *sdev = to_scsi_device(dev);
9075         struct ufs_hba *hba;
9076         int ret = 0;
9077         ktime_t start = ktime_get();
9078
9079         hba = shost_priv(sdev->host);
9080
9081         if (pm_runtime_suspended(dev))
9082                 goto out;
9083
9084         ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM);
9085         if (ret)
9086                 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9087 out:
9088         trace_ufshcd_wl_resume(dev_name(dev), ret,
9089                 ktime_to_us(ktime_sub(ktime_get(), start)),
9090                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9091         if (!ret)
9092                 hba->is_sys_suspended = false;
9093         up(&hba->host_sem);
9094         return ret;
9095 }
9096 #endif
9097
9098 static void ufshcd_wl_shutdown(struct device *dev)
9099 {
9100         struct scsi_device *sdev = to_scsi_device(dev);
9101         struct ufs_hba *hba;
9102
9103         hba = shost_priv(sdev->host);
9104
9105         down(&hba->host_sem);
9106         hba->shutting_down = true;
9107         up(&hba->host_sem);
9108
9109         /* Turn on everything while shutting down */
9110         ufshcd_rpm_get_sync(hba);
9111         scsi_device_quiesce(sdev);
9112         shost_for_each_device(sdev, hba->host) {
9113                 if (sdev == hba->sdev_ufs_device)
9114                         continue;
9115                 scsi_device_quiesce(sdev);
9116         }
9117         __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
9118 }
9119
9120 /**
9121  * ufshcd_suspend - helper function for suspend operations
9122  * @hba: per adapter instance
9123  *
9124  * This function will put disable irqs, turn off clocks
9125  * and set vreg and hba-vreg in lpm mode.
9126  */
9127 static int ufshcd_suspend(struct ufs_hba *hba)
9128 {
9129         int ret;
9130
9131         if (!hba->is_powered)
9132                 return 0;
9133         /*
9134          * Disable the host irq as host controller as there won't be any
9135          * host controller transaction expected till resume.
9136          */
9137         ufshcd_disable_irq(hba);
9138         ret = ufshcd_setup_clocks(hba, false);
9139         if (ret) {
9140                 ufshcd_enable_irq(hba);
9141                 return ret;
9142         }
9143         if (ufshcd_is_clkgating_allowed(hba)) {
9144                 hba->clk_gating.state = CLKS_OFF;
9145                 trace_ufshcd_clk_gating(dev_name(hba->dev),
9146                                         hba->clk_gating.state);
9147         }
9148
9149         ufshcd_vreg_set_lpm(hba);
9150         /* Put the host controller in low power mode if possible */
9151         ufshcd_hba_vreg_set_lpm(hba);
9152         return ret;
9153 }
9154
9155 /**
9156  * ufshcd_resume - helper function for resume operations
9157  * @hba: per adapter instance
9158  *
9159  * This function basically turns on the regulators, clocks and
9160  * irqs of the hba.
9161  *
9162  * Returns 0 for success and non-zero for failure
9163  */
9164 static int ufshcd_resume(struct ufs_hba *hba)
9165 {
9166         int ret;
9167
9168         if (!hba->is_powered)
9169                 return 0;
9170
9171         ufshcd_hba_vreg_set_hpm(hba);
9172         ret = ufshcd_vreg_set_hpm(hba);
9173         if (ret)
9174                 goto out;
9175
9176         /* Make sure clocks are enabled before accessing controller */
9177         ret = ufshcd_setup_clocks(hba, true);
9178         if (ret)
9179                 goto disable_vreg;
9180
9181         /* enable the host irq as host controller would be active soon */
9182         ufshcd_enable_irq(hba);
9183         goto out;
9184
9185 disable_vreg:
9186         ufshcd_vreg_set_lpm(hba);
9187 out:
9188         if (ret)
9189                 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret);
9190         return ret;
9191 }
9192
9193 /**
9194  * ufshcd_system_suspend - system suspend routine
9195  * @hba: per adapter instance
9196  *
9197  * Check the description of ufshcd_suspend() function for more details.
9198  *
9199  * Returns 0 for success and non-zero for failure
9200  */
9201 int ufshcd_system_suspend(struct ufs_hba *hba)
9202 {
9203         int ret = 0;
9204         ktime_t start = ktime_get();
9205
9206         if (pm_runtime_suspended(hba->dev))
9207                 goto out;
9208
9209         ret = ufshcd_suspend(hba);
9210 out:
9211         trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
9212                 ktime_to_us(ktime_sub(ktime_get(), start)),
9213                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9214         return ret;
9215 }
9216 EXPORT_SYMBOL(ufshcd_system_suspend);
9217
9218 /**
9219  * ufshcd_system_resume - system resume routine
9220  * @hba: per adapter instance
9221  *
9222  * Returns 0 for success and non-zero for failure
9223  */
9224
9225 int ufshcd_system_resume(struct ufs_hba *hba)
9226 {
9227         int ret = 0;
9228         ktime_t start = ktime_get();
9229
9230         if (pm_runtime_suspended(hba->dev))
9231                 goto out;
9232
9233         ret = ufshcd_resume(hba);
9234
9235 out:
9236         trace_ufshcd_system_resume(dev_name(hba->dev), ret,
9237                 ktime_to_us(ktime_sub(ktime_get(), start)),
9238                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9239
9240         return ret;
9241 }
9242 EXPORT_SYMBOL(ufshcd_system_resume);
9243
9244 /**
9245  * ufshcd_runtime_suspend - runtime suspend routine
9246  * @hba: per adapter instance
9247  *
9248  * Check the description of ufshcd_suspend() function for more details.
9249  *
9250  * Returns 0 for success and non-zero for failure
9251  */
9252 int ufshcd_runtime_suspend(struct ufs_hba *hba)
9253 {
9254         int ret;
9255         ktime_t start = ktime_get();
9256
9257         ret = ufshcd_suspend(hba);
9258
9259         trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
9260                 ktime_to_us(ktime_sub(ktime_get(), start)),
9261                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9262         return ret;
9263 }
9264 EXPORT_SYMBOL(ufshcd_runtime_suspend);
9265
9266 /**
9267  * ufshcd_runtime_resume - runtime resume routine
9268  * @hba: per adapter instance
9269  *
9270  * This function basically brings controller
9271  * to active state. Following operations are done in this function:
9272  *
9273  * 1. Turn on all the controller related clocks
9274  * 2. Turn ON VCC rail
9275  */
9276 int ufshcd_runtime_resume(struct ufs_hba *hba)
9277 {
9278         int ret;
9279         ktime_t start = ktime_get();
9280
9281         ret = ufshcd_resume(hba);
9282
9283         trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
9284                 ktime_to_us(ktime_sub(ktime_get(), start)),
9285                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9286         return ret;
9287 }
9288 EXPORT_SYMBOL(ufshcd_runtime_resume);
9289
9290 int ufshcd_runtime_idle(struct ufs_hba *hba)
9291 {
9292         return 0;
9293 }
9294 EXPORT_SYMBOL(ufshcd_runtime_idle);
9295
9296 /**
9297  * ufshcd_shutdown - shutdown routine
9298  * @hba: per adapter instance
9299  *
9300  * This function would turn off both UFS device and UFS hba
9301  * regulators. It would also disable clocks.
9302  *
9303  * Returns 0 always to allow force shutdown even in case of errors.
9304  */
9305 int ufshcd_shutdown(struct ufs_hba *hba)
9306 {
9307         if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
9308                 goto out;
9309
9310         pm_runtime_get_sync(hba->dev);
9311
9312         ufshcd_suspend(hba);
9313 out:
9314         hba->is_powered = false;
9315         /* allow force shutdown even in case of errors */
9316         return 0;
9317 }
9318 EXPORT_SYMBOL(ufshcd_shutdown);
9319
9320 /**
9321  * ufshcd_remove - de-allocate SCSI host and host memory space
9322  *              data structure memory
9323  * @hba: per adapter instance
9324  */
9325 void ufshcd_remove(struct ufs_hba *hba)
9326 {
9327         if (hba->sdev_ufs_device)
9328                 ufshcd_rpm_get_sync(hba);
9329         ufs_bsg_remove(hba);
9330         ufs_sysfs_remove_nodes(hba->dev);
9331         blk_cleanup_queue(hba->tmf_queue);
9332         blk_mq_free_tag_set(&hba->tmf_tag_set);
9333         blk_cleanup_queue(hba->cmd_queue);
9334         scsi_remove_host(hba->host);
9335         /* disable interrupts */
9336         ufshcd_disable_intr(hba, hba->intr_mask);
9337         ufshcd_hba_stop(hba);
9338         ufshcd_hba_exit(hba);
9339 }
9340 EXPORT_SYMBOL_GPL(ufshcd_remove);
9341
9342 /**
9343  * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
9344  * @hba: pointer to Host Bus Adapter (HBA)
9345  */
9346 void ufshcd_dealloc_host(struct ufs_hba *hba)
9347 {
9348         scsi_host_put(hba->host);
9349 }
9350 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
9351
9352 /**
9353  * ufshcd_set_dma_mask - Set dma mask based on the controller
9354  *                       addressing capability
9355  * @hba: per adapter instance
9356  *
9357  * Returns 0 for success, non-zero for failure
9358  */
9359 static int ufshcd_set_dma_mask(struct ufs_hba *hba)
9360 {
9361         if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
9362                 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
9363                         return 0;
9364         }
9365         return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
9366 }
9367
9368 /**
9369  * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
9370  * @dev: pointer to device handle
9371  * @hba_handle: driver private handle
9372  * Returns 0 on success, non-zero value on failure
9373  */
9374 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
9375 {
9376         struct Scsi_Host *host;
9377         struct ufs_hba *hba;
9378         int err = 0;
9379
9380         if (!dev) {
9381                 dev_err(dev,
9382                 "Invalid memory reference for dev is NULL\n");
9383                 err = -ENODEV;
9384                 goto out_error;
9385         }
9386
9387         host = scsi_host_alloc(&ufshcd_driver_template,
9388                                 sizeof(struct ufs_hba));
9389         if (!host) {
9390                 dev_err(dev, "scsi_host_alloc failed\n");
9391                 err = -ENOMEM;
9392                 goto out_error;
9393         }
9394         hba = shost_priv(host);
9395         hba->host = host;
9396         hba->dev = dev;
9397         *hba_handle = hba;
9398         hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
9399
9400         INIT_LIST_HEAD(&hba->clk_list_head);
9401
9402 out_error:
9403         return err;
9404 }
9405 EXPORT_SYMBOL(ufshcd_alloc_host);
9406
9407 /* This function exists because blk_mq_alloc_tag_set() requires this. */
9408 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
9409                                      const struct blk_mq_queue_data *qd)
9410 {
9411         WARN_ON_ONCE(true);
9412         return BLK_STS_NOTSUPP;
9413 }
9414
9415 static const struct blk_mq_ops ufshcd_tmf_ops = {
9416         .queue_rq = ufshcd_queue_tmf,
9417 };
9418
9419 /**
9420  * ufshcd_init - Driver initialization routine
9421  * @hba: per-adapter instance
9422  * @mmio_base: base register address
9423  * @irq: Interrupt line of device
9424  * Returns 0 on success, non-zero value on failure
9425  */
9426 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
9427 {
9428         int err;
9429         struct Scsi_Host *host = hba->host;
9430         struct device *dev = hba->dev;
9431         char eh_wq_name[sizeof("ufs_eh_wq_00")];
9432
9433         if (!mmio_base) {
9434                 dev_err(hba->dev,
9435                 "Invalid memory reference for mmio_base is NULL\n");
9436                 err = -ENODEV;
9437                 goto out_error;
9438         }
9439
9440         hba->mmio_base = mmio_base;
9441         hba->irq = irq;
9442         hba->vps = &ufs_hba_vps;
9443
9444         err = ufshcd_hba_init(hba);
9445         if (err)
9446                 goto out_error;
9447
9448         /* Read capabilities registers */
9449         err = ufshcd_hba_capabilities(hba);
9450         if (err)
9451                 goto out_disable;
9452
9453         /* Get UFS version supported by the controller */
9454         hba->ufs_version = ufshcd_get_ufs_version(hba);
9455
9456         /* Get Interrupt bit mask per version */
9457         hba->intr_mask = ufshcd_get_intr_mask(hba);
9458
9459         err = ufshcd_set_dma_mask(hba);
9460         if (err) {
9461                 dev_err(hba->dev, "set dma mask failed\n");
9462                 goto out_disable;
9463         }
9464
9465         /* Allocate memory for host memory space */
9466         err = ufshcd_memory_alloc(hba);
9467         if (err) {
9468                 dev_err(hba->dev, "Memory allocation failed\n");
9469                 goto out_disable;
9470         }
9471
9472         /* Configure LRB */
9473         ufshcd_host_memory_configure(hba);
9474
9475         host->can_queue = hba->nutrs;
9476         host->cmd_per_lun = hba->nutrs;
9477         host->max_id = UFSHCD_MAX_ID;
9478         host->max_lun = UFS_MAX_LUNS;
9479         host->max_channel = UFSHCD_MAX_CHANNEL;
9480         host->unique_id = host->host_no;
9481         host->max_cmd_len = UFS_CDB_SIZE;
9482
9483         hba->max_pwr_info.is_valid = false;
9484
9485         /* Initialize work queues */
9486         snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d",
9487                  hba->host->host_no);
9488         hba->eh_wq = create_singlethread_workqueue(eh_wq_name);
9489         if (!hba->eh_wq) {
9490                 dev_err(hba->dev, "%s: failed to create eh workqueue\n",
9491                                 __func__);
9492                 err = -ENOMEM;
9493                 goto out_disable;
9494         }
9495         INIT_WORK(&hba->eh_work, ufshcd_err_handler);
9496         INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
9497
9498         sema_init(&hba->host_sem, 1);
9499
9500         /* Initialize UIC command mutex */
9501         mutex_init(&hba->uic_cmd_mutex);
9502
9503         /* Initialize mutex for device management commands */
9504         mutex_init(&hba->dev_cmd.lock);
9505
9506         /* Initialize mutex for exception event control */
9507         mutex_init(&hba->ee_ctrl_mutex);
9508
9509         init_rwsem(&hba->clk_scaling_lock);
9510
9511         ufshcd_init_clk_gating(hba);
9512
9513         ufshcd_init_clk_scaling(hba);
9514
9515         /*
9516          * In order to avoid any spurious interrupt immediately after
9517          * registering UFS controller interrupt handler, clear any pending UFS
9518          * interrupt status and disable all the UFS interrupts.
9519          */
9520         ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
9521                       REG_INTERRUPT_STATUS);
9522         ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
9523         /*
9524          * Make sure that UFS interrupts are disabled and any pending interrupt
9525          * status is cleared before registering UFS interrupt handler.
9526          */
9527         mb();
9528
9529         /* IRQ registration */
9530         err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
9531         if (err) {
9532                 dev_err(hba->dev, "request irq failed\n");
9533                 goto out_disable;
9534         } else {
9535                 hba->is_irq_enabled = true;
9536         }
9537
9538         err = scsi_add_host(host, hba->dev);
9539         if (err) {
9540                 dev_err(hba->dev, "scsi_add_host failed\n");
9541                 goto out_disable;
9542         }
9543
9544         hba->cmd_queue = blk_mq_init_queue(&hba->host->tag_set);
9545         if (IS_ERR(hba->cmd_queue)) {
9546                 err = PTR_ERR(hba->cmd_queue);
9547                 goto out_remove_scsi_host;
9548         }
9549
9550         hba->tmf_tag_set = (struct blk_mq_tag_set) {
9551                 .nr_hw_queues   = 1,
9552                 .queue_depth    = hba->nutmrs,
9553                 .ops            = &ufshcd_tmf_ops,
9554                 .flags          = BLK_MQ_F_NO_SCHED,
9555         };
9556         err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
9557         if (err < 0)
9558                 goto free_cmd_queue;
9559         hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set);
9560         if (IS_ERR(hba->tmf_queue)) {
9561                 err = PTR_ERR(hba->tmf_queue);
9562                 goto free_tmf_tag_set;
9563         }
9564
9565         /* Reset the attached device */
9566         ufshcd_device_reset(hba);
9567
9568         ufshcd_init_crypto(hba);
9569
9570         /* Host controller enable */
9571         err = ufshcd_hba_enable(hba);
9572         if (err) {
9573                 dev_err(hba->dev, "Host controller enable failed\n");
9574                 ufshcd_print_evt_hist(hba);
9575                 ufshcd_print_host_state(hba);
9576                 goto free_tmf_queue;
9577         }
9578
9579         /*
9580          * Set the default power management level for runtime and system PM.
9581          * Default power saving mode is to keep UFS link in Hibern8 state
9582          * and UFS device in sleep state.
9583          */
9584         hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
9585                                                 UFS_SLEEP_PWR_MODE,
9586                                                 UIC_LINK_HIBERN8_STATE);
9587         hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
9588                                                 UFS_SLEEP_PWR_MODE,
9589                                                 UIC_LINK_HIBERN8_STATE);
9590
9591         INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work,
9592                           ufshcd_rpm_dev_flush_recheck_work);
9593
9594         /* Set the default auto-hiberate idle timer value to 150 ms */
9595         if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
9596                 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
9597                             FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
9598         }
9599
9600         /* Hold auto suspend until async scan completes */
9601         pm_runtime_get_sync(dev);
9602         atomic_set(&hba->scsi_block_reqs_cnt, 0);
9603         /*
9604          * We are assuming that device wasn't put in sleep/power-down
9605          * state exclusively during the boot stage before kernel.
9606          * This assumption helps avoid doing link startup twice during
9607          * ufshcd_probe_hba().
9608          */
9609         ufshcd_set_ufs_dev_active(hba);
9610
9611         async_schedule(ufshcd_async_scan, hba);
9612         ufs_sysfs_add_nodes(hba->dev);
9613
9614         return 0;
9615
9616 free_tmf_queue:
9617         blk_cleanup_queue(hba->tmf_queue);
9618 free_tmf_tag_set:
9619         blk_mq_free_tag_set(&hba->tmf_tag_set);
9620 free_cmd_queue:
9621         blk_cleanup_queue(hba->cmd_queue);
9622 out_remove_scsi_host:
9623         scsi_remove_host(hba->host);
9624 out_disable:
9625         hba->is_irq_enabled = false;
9626         ufshcd_hba_exit(hba);
9627 out_error:
9628         return err;
9629 }
9630 EXPORT_SYMBOL_GPL(ufshcd_init);
9631
9632 void ufshcd_resume_complete(struct device *dev)
9633 {
9634         struct ufs_hba *hba = dev_get_drvdata(dev);
9635
9636         if (hba->complete_put) {
9637                 ufshcd_rpm_put(hba);
9638                 hba->complete_put = false;
9639         }
9640         if (hba->rpmb_complete_put) {
9641                 ufshcd_rpmb_rpm_put(hba);
9642                 hba->rpmb_complete_put = false;
9643         }
9644 }
9645 EXPORT_SYMBOL_GPL(ufshcd_resume_complete);
9646
9647 int ufshcd_suspend_prepare(struct device *dev)
9648 {
9649         struct ufs_hba *hba = dev_get_drvdata(dev);
9650         int ret;
9651
9652         /*
9653          * SCSI assumes that runtime-pm and system-pm for scsi drivers
9654          * are same. And it doesn't wake up the device for system-suspend
9655          * if it's runtime suspended. But ufs doesn't follow that.
9656          * Refer ufshcd_resume_complete()
9657          */
9658         if (hba->sdev_ufs_device) {
9659                 ret = ufshcd_rpm_get_sync(hba);
9660                 if (ret < 0 && ret != -EACCES) {
9661                         ufshcd_rpm_put(hba);
9662                         return ret;
9663                 }
9664                 hba->complete_put = true;
9665         }
9666         if (hba->sdev_rpmb) {
9667                 ufshcd_rpmb_rpm_get_sync(hba);
9668                 hba->rpmb_complete_put = true;
9669         }
9670         return 0;
9671 }
9672 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare);
9673
9674 #ifdef CONFIG_PM_SLEEP
9675 static int ufshcd_wl_poweroff(struct device *dev)
9676 {
9677         struct scsi_device *sdev = to_scsi_device(dev);
9678         struct ufs_hba *hba = shost_priv(sdev->host);
9679
9680         __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
9681         return 0;
9682 }
9683 #endif
9684
9685 static int ufshcd_wl_probe(struct device *dev)
9686 {
9687         struct scsi_device *sdev = to_scsi_device(dev);
9688
9689         if (!is_device_wlun(sdev))
9690                 return -ENODEV;
9691
9692         blk_pm_runtime_init(sdev->request_queue, dev);
9693         pm_runtime_set_autosuspend_delay(dev, 0);
9694         pm_runtime_allow(dev);
9695
9696         return  0;
9697 }
9698
9699 static int ufshcd_wl_remove(struct device *dev)
9700 {
9701         pm_runtime_forbid(dev);
9702         return 0;
9703 }
9704
9705 static const struct dev_pm_ops ufshcd_wl_pm_ops = {
9706 #ifdef CONFIG_PM_SLEEP
9707         .suspend = ufshcd_wl_suspend,
9708         .resume = ufshcd_wl_resume,
9709         .freeze = ufshcd_wl_suspend,
9710         .thaw = ufshcd_wl_resume,
9711         .poweroff = ufshcd_wl_poweroff,
9712         .restore = ufshcd_wl_resume,
9713 #endif
9714         SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL)
9715 };
9716
9717 /*
9718  * ufs_dev_wlun_template - describes ufs device wlun
9719  * ufs-device wlun - used to send pm commands
9720  * All luns are consumers of ufs-device wlun.
9721  *
9722  * Currently, no sd driver is present for wluns.
9723  * Hence the no specific pm operations are performed.
9724  * With ufs design, SSU should be sent to ufs-device wlun.
9725  * Hence register a scsi driver for ufs wluns only.
9726  */
9727 static struct scsi_driver ufs_dev_wlun_template = {
9728         .gendrv = {
9729                 .name = "ufs_device_wlun",
9730                 .owner = THIS_MODULE,
9731                 .probe = ufshcd_wl_probe,
9732                 .remove = ufshcd_wl_remove,
9733                 .pm = &ufshcd_wl_pm_ops,
9734                 .shutdown = ufshcd_wl_shutdown,
9735         },
9736 };
9737
9738 static int ufshcd_rpmb_probe(struct device *dev)
9739 {
9740         return is_rpmb_wlun(to_scsi_device(dev)) ? 0 : -ENODEV;
9741 }
9742
9743 static inline int ufshcd_clear_rpmb_uac(struct ufs_hba *hba)
9744 {
9745         int ret = 0;
9746
9747         if (!hba->wlun_rpmb_clr_ua)
9748                 return 0;
9749         ret = ufshcd_clear_ua_wlun(hba, UFS_UPIU_RPMB_WLUN);
9750         if (!ret)
9751                 hba->wlun_rpmb_clr_ua = 0;
9752         return ret;
9753 }
9754
9755 static int ufshcd_rpmb_resume(struct device *dev)
9756 {
9757         struct ufs_hba *hba = wlun_dev_to_hba(dev);
9758
9759         if (hba->sdev_rpmb)
9760                 ufshcd_clear_rpmb_uac(hba);
9761         return 0;
9762 }
9763
9764 static const struct dev_pm_ops ufs_rpmb_pm_ops = {
9765         SET_RUNTIME_PM_OPS(NULL, ufshcd_rpmb_resume, NULL)
9766         SET_SYSTEM_SLEEP_PM_OPS(NULL, ufshcd_rpmb_resume)
9767 };
9768
9769 /* ufs_rpmb_wlun_template - Describes UFS RPMB WLUN. Used only to send UAC. */
9770 static struct scsi_driver ufs_rpmb_wlun_template = {
9771         .gendrv = {
9772                 .name = "ufs_rpmb_wlun",
9773                 .owner = THIS_MODULE,
9774                 .probe = ufshcd_rpmb_probe,
9775                 .pm = &ufs_rpmb_pm_ops,
9776         },
9777 };
9778
9779 static int __init ufshcd_core_init(void)
9780 {
9781         int ret;
9782
9783         ufs_debugfs_init();
9784
9785         ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv);
9786         if (ret)
9787                 goto debugfs_exit;
9788
9789         ret = scsi_register_driver(&ufs_rpmb_wlun_template.gendrv);
9790         if (ret)
9791                 goto unregister;
9792
9793         return ret;
9794 unregister:
9795         scsi_unregister_driver(&ufs_dev_wlun_template.gendrv);
9796 debugfs_exit:
9797         ufs_debugfs_exit();
9798         return ret;
9799 }
9800
9801 static void __exit ufshcd_core_exit(void)
9802 {
9803         ufs_debugfs_exit();
9804         scsi_unregister_driver(&ufs_rpmb_wlun_template.gendrv);
9805         scsi_unregister_driver(&ufs_dev_wlun_template.gendrv);
9806 }
9807
9808 module_init(ufshcd_core_init);
9809 module_exit(ufshcd_core_exit);
9810
9811 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
9812 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
9813 MODULE_DESCRIPTION("Generic UFS host controller driver Core");
9814 MODULE_LICENSE("GPL");
9815 MODULE_VERSION(UFSHCD_DRIVER_VERSION);