drivers/scsi/ufs/ufshcd.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Universal Flash Storage Host controller driver Core
   4  * Copyright (C) 2011-2013 Samsung India Software Operations
   5  * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
   6  *
   7  * Authors:
   8  *      Santosh Yaraganavi <santosh.sy@samsung.com>
   9  *      Vinayak Holikatti <h.vinayak@samsung.com>
  10  */
  11
  12 #include <linux/async.h>
  13 #include <linux/devfreq.h>
  14 #include <linux/nls.h>
  15 #include <linux/of.h>
  16 #include <linux/bitfield.h>
  17 #include <linux/blk-pm.h>
  18 #include <linux/blkdev.h>
  19 #include <scsi/scsi_driver.h>
  20 #include "ufshcd.h"
  21 #include "ufs_quirks.h"
  22 #include "unipro.h"
  23 #include "ufs-sysfs.h"
  24 #include "ufs-debugfs.h"
  25 #include "ufs_bsg.h"
  26 #include "ufshcd-crypto.h"
  27 #include "ufshpb.h"
  28 #include <asm/unaligned.h>
  29
  30 #define CREATE_TRACE_POINTS
  31 #include <trace/events/ufs.h>
  32
  33 #define UFSHCD_ENABLE_INTRS     (UTP_TRANSFER_REQ_COMPL |\
  34                                  UTP_TASK_REQ_COMPL |\
  35                                  UFSHCD_ERROR_MASK)
  36 /* UIC command timeout, unit: ms */
  37 #define UIC_CMD_TIMEOUT 500
  38
  39 /* NOP OUT retries waiting for NOP IN response */
  40 #define NOP_OUT_RETRIES    10
  41 /* Timeout after 50 msecs if NOP OUT hangs without response */
  42 #define NOP_OUT_TIMEOUT    50 /* msecs */
  43
  44 /* Query request retries */
  45 #define QUERY_REQ_RETRIES 3
  46 /* Query request timeout */
  47 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
  48
  49 /* Task management command timeout */
  50 #define TM_CMD_TIMEOUT  100 /* msecs */
  51
  52 /* maximum number of retries for a general UIC command  */
  53 #define UFS_UIC_COMMAND_RETRIES 3
  54
  55 /* maximum number of link-startup retries */
  56 #define DME_LINKSTARTUP_RETRIES 3
  57
  58 /* Maximum retries for Hibern8 enter */
  59 #define UIC_HIBERN8_ENTER_RETRIES 3
  60
  61 /* maximum number of reset retries before giving up */
  62 #define MAX_HOST_RESET_RETRIES 5
  63
  64 /* Expose the flag value from utp_upiu_query.value */
  65 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
  66
  67 /* Interrupt aggregation default timeout, unit: 40us */
  68 #define INT_AGGR_DEF_TO 0x02
  69
  70 /* default delay of autosuspend: 2000 ms */
  71 #define RPM_AUTOSUSPEND_DELAY_MS 2000
  72
  73 /* Default delay of RPM device flush delayed work */
  74 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000
  75
  76 /* Default value of wait time before gating device ref clock */
  77 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */
  78
  79 /* Polling time to wait for fDeviceInit */
  80 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */
  81
  82 #define wlun_dev_to_hba(dv) shost_priv(to_scsi_device(dv)->host)
  83
  84 #define ufshcd_toggle_vreg(_dev, _vreg, _on)                            \
  85         ({                                                              \
  86                 int _ret;                                               \
  87                 if (_on)                                                \
  88                         _ret = ufshcd_enable_vreg(_dev, _vreg);         \
  89                 else                                                    \
  90                         _ret = ufshcd_disable_vreg(_dev, _vreg);        \
  91                 _ret;                                                   \
  92         })
  93
  94 #define ufshcd_hex_dump(prefix_str, buf, len) do {                       \
  95         size_t __len = (len);                                            \
  96         print_hex_dump(KERN_ERR, prefix_str,                             \
  97                        __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
  98                        16, 4, buf, __len, false);                        \
  99 } while (0)
 100
 101 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
 102                      const char *prefix)
 103 {
 104         u32 *regs;
 105         size_t pos;
 106
 107         if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
 108                 return -EINVAL;
 109
 110         regs = kzalloc(len, GFP_ATOMIC);
 111         if (!regs)
 112                 return -ENOMEM;
 113
 114         for (pos = 0; pos < len; pos += 4)
 115                 regs[pos / 4] = ufshcd_readl(hba, offset + pos);
 116
 117         ufshcd_hex_dump(prefix, regs, len);
 118         kfree(regs);
 119
 120         return 0;
 121 }
 122 EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
 123
 124 enum {
 125         UFSHCD_MAX_CHANNEL      = 0,
 126         UFSHCD_MAX_ID           = 1,
 127         UFSHCD_CMD_PER_LUN      = 32,
 128         UFSHCD_CAN_QUEUE        = 32,
 129 };
 130
 131 /* UFSHCD error handling flags */
 132 enum {
 133         UFSHCD_EH_IN_PROGRESS = (1 << 0),
 134 };
 135
 136 /* UFSHCD UIC layer error flags */
 137 enum {
 138         UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
 139         UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
 140         UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
 141         UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
 142         UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
 143         UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
 144         UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */
 145 };
 146
 147 #define ufshcd_set_eh_in_progress(h) \
 148         ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
 149 #define ufshcd_eh_in_progress(h) \
 150         ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
 151 #define ufshcd_clear_eh_in_progress(h) \
 152         ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
 153
 154 struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
 155         [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
 156         [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
 157         [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
 158         [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
 159         [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
 160         [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
 161         /*
 162          * For DeepSleep, the link is first put in hibern8 and then off.
 163          * Leaving the link in hibern8 is not supported.
 164          */
 165         [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE},
 166 };
 167
 168 static inline enum ufs_dev_pwr_mode
 169 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
 170 {
 171         return ufs_pm_lvl_states[lvl].dev_state;
 172 }
 173
 174 static inline enum uic_link_state
 175 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
 176 {
 177         return ufs_pm_lvl_states[lvl].link_state;
 178 }
 179
 180 static inline enum ufs_pm_level
 181 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
 182                                         enum uic_link_state link_state)
 183 {
 184         enum ufs_pm_level lvl;
 185
 186         for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
 187                 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
 188                         (ufs_pm_lvl_states[lvl].link_state == link_state))
 189                         return lvl;
 190         }
 191
 192         /* if no match found, return the level 0 */
 193         return UFS_PM_LVL_0;
 194 }
 195
 196 static struct ufs_dev_fix ufs_fixups[] = {
 197         /* UFS cards deviations table */
 198         UFS_FIX(UFS_VENDOR_MICRON, UFS_ANY_MODEL,
 199                 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
 200         UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
 201                 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
 202                 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE |
 203                 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
 204         UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
 205                 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
 206         UFS_FIX(UFS_VENDOR_SKHYNIX, "hB8aL1" /*H28U62301AMR*/,
 207                 UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME),
 208         UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
 209                 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
 210         UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
 211                 UFS_DEVICE_QUIRK_PA_TACTIVATE),
 212         UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
 213                 UFS_DEVICE_QUIRK_PA_TACTIVATE),
 214         END_FIX
 215 };
 216
 217 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
 218 static void ufshcd_async_scan(void *data, async_cookie_t cookie);
 219 static int ufshcd_reset_and_restore(struct ufs_hba *hba);
 220 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
 221 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
 222 static void ufshcd_hba_exit(struct ufs_hba *hba);
 223 static int ufshcd_clear_ua_wluns(struct ufs_hba *hba);
 224 static int ufshcd_probe_hba(struct ufs_hba *hba, bool async);
 225 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
 226 static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
 227 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
 228 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
 229 static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
 230 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
 231 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
 232 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
 233 static irqreturn_t ufshcd_intr(int irq, void *__hba);
 234 static int ufshcd_change_power_mode(struct ufs_hba *hba,
 235                              struct ufs_pa_layer_attr *pwr_mode);
 236 static void ufshcd_schedule_eh_work(struct ufs_hba *hba);
 237 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on);
 238 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on);
 239 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
 240                                          struct ufs_vreg *vreg);
 241 static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag);
 242 static void ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set);
 243 static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable);
 244 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba);
 245 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba);
 246
 247 static inline void ufshcd_enable_irq(struct ufs_hba *hba)
 248 {
 249         if (!hba->is_irq_enabled) {
 250                 enable_irq(hba->irq);
 251                 hba->is_irq_enabled = true;
 252         }
 253 }
 254
 255 static inline void ufshcd_disable_irq(struct ufs_hba *hba)
 256 {
 257         if (hba->is_irq_enabled) {
 258                 disable_irq(hba->irq);
 259                 hba->is_irq_enabled = false;
 260         }
 261 }
 262
 263 static inline void ufshcd_wb_config(struct ufs_hba *hba)
 264 {
 265         if (!ufshcd_is_wb_allowed(hba))
 266                 return;
 267
 268         ufshcd_wb_toggle(hba, true);
 269
 270         ufshcd_wb_toggle_flush_during_h8(hba, true);
 271         if (!(hba->quirks & UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL))
 272                 ufshcd_wb_toggle_flush(hba, true);
 273 }
 274
 275 static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
 276 {
 277         if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
 278                 scsi_unblock_requests(hba->host);
 279 }
 280
 281 static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
 282 {
 283         if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
 284                 scsi_block_requests(hba->host);
 285 }
 286
 287 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
 288                                       enum ufs_trace_str_t str_t)
 289 {
 290         struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
 291         struct utp_upiu_header *header;
 292
 293         if (!trace_ufshcd_upiu_enabled())
 294                 return;
 295
 296         if (str_t == UFS_CMD_SEND)
 297                 header = &rq->header;
 298         else
 299                 header = &hba->lrb[tag].ucd_rsp_ptr->header;
 300
 301         trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb,
 302                           UFS_TSF_CDB);
 303 }
 304
 305 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba,
 306                                         enum ufs_trace_str_t str_t,
 307                                         struct utp_upiu_req *rq_rsp)
 308 {
 309         if (!trace_ufshcd_upiu_enabled())
 310                 return;
 311
 312         trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header,
 313                           &rq_rsp->qr, UFS_TSF_OSF);
 314 }
 315
 316 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
 317                                      enum ufs_trace_str_t str_t)
 318 {
 319         int off = (int)tag - hba->nutrs;
 320         struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[off];
 321
 322         if (!trace_ufshcd_upiu_enabled())
 323                 return;
 324
 325         if (str_t == UFS_TM_SEND)
 326                 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
 327                                   &descp->upiu_req.req_header,
 328                                   &descp->upiu_req.input_param1,
 329                                   UFS_TSF_TM_INPUT);
 330         else
 331                 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
 332                                   &descp->upiu_rsp.rsp_header,
 333                                   &descp->upiu_rsp.output_param1,
 334                                   UFS_TSF_TM_OUTPUT);
 335 }
 336
 337 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba,
 338                                          struct uic_command *ucmd,
 339                                          enum ufs_trace_str_t str_t)
 340 {
 341         u32 cmd;
 342
 343         if (!trace_ufshcd_uic_command_enabled())
 344                 return;
 345
 346         if (str_t == UFS_CMD_SEND)
 347                 cmd = ucmd->command;
 348         else
 349                 cmd = ufshcd_readl(hba, REG_UIC_COMMAND);
 350
 351         trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd,
 352                                  ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1),
 353                                  ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2),
 354                                  ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3));
 355 }
 356
 357 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag,
 358                                      enum ufs_trace_str_t str_t)
 359 {
 360         u64 lba = -1;
 361         u8 opcode = 0, group_id = 0;
 362         u32 intr, doorbell;
 363         struct ufshcd_lrb *lrbp = &hba->lrb[tag];
 364         struct scsi_cmnd *cmd = lrbp->cmd;
 365         int transfer_len = -1;
 366
 367         if (!cmd)
 368                 return;
 369
 370         if (!trace_ufshcd_command_enabled()) {
 371                 /* trace UPIU W/O tracing command */
 372                 ufshcd_add_cmd_upiu_trace(hba, tag, str_t);
 373                 return;
 374         }
 375
 376         /* trace UPIU also */
 377         ufshcd_add_cmd_upiu_trace(hba, tag, str_t);
 378         opcode = cmd->cmnd[0];
 379         lba = scsi_get_lba(cmd);
 380
 381         if (opcode == READ_10 || opcode == WRITE_10) {
 382                 /*
 383                  * Currently we only fully trace read(10) and write(10) commands
 384                  */
 385                 transfer_len =
 386                        be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
 387                 if (opcode == WRITE_10)
 388                         group_id = lrbp->cmd->cmnd[6];
 389         } else if (opcode == UNMAP) {
 390                 /*
 391                  * The number of Bytes to be unmapped beginning with the lba.
 392                  */
 393                 transfer_len = blk_rq_bytes(cmd->request);
 394         }
 395
 396         intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
 397         doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
 398         trace_ufshcd_command(dev_name(hba->dev), str_t, tag,
 399                         doorbell, transfer_len, intr, lba, opcode, group_id);
 400 }
 401
 402 static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
 403 {
 404         struct ufs_clk_info *clki;
 405         struct list_head *head = &hba->clk_list_head;
 406
 407         if (list_empty(head))
 408                 return;
 409
 410         list_for_each_entry(clki, head, list) {
 411                 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
 412                                 clki->max_freq)
 413                         dev_err(hba->dev, "clk: %s, rate: %u\n",
 414                                         clki->name, clki->curr_freq);
 415         }
 416 }
 417
 418 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id,
 419                              char *err_name)
 420 {
 421         int i;
 422         bool found = false;
 423         struct ufs_event_hist *e;
 424
 425         if (id >= UFS_EVT_CNT)
 426                 return;
 427
 428         e = &hba->ufs_stats.event[id];
 429
 430         for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) {
 431                 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH;
 432
 433                 if (e->tstamp[p] == 0)
 434                         continue;
 435                 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
 436                         e->val[p], ktime_to_us(e->tstamp[p]));
 437                 found = true;
 438         }
 439
 440         if (!found)
 441                 dev_err(hba->dev, "No record of %s\n", err_name);
 442         else
 443                 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt);
 444 }
 445
 446 static void ufshcd_print_evt_hist(struct ufs_hba *hba)
 447 {
 448         ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
 449
 450         ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err");
 451         ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err");
 452         ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err");
 453         ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err");
 454         ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err");
 455         ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR,
 456                          "auto_hibern8_err");
 457         ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err");
 458         ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL,
 459                          "link_startup_fail");
 460         ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail");
 461         ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR,
 462                          "suspend_fail");
 463         ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset");
 464         ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset");
 465         ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort");
 466
 467         ufshcd_vops_dbg_register_dump(hba);
 468 }
 469
 470 static
 471 void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
 472 {
 473         struct ufshcd_lrb *lrbp;
 474         int prdt_length;
 475         int tag;
 476
 477         for_each_set_bit(tag, &bitmap, hba->nutrs) {
 478                 lrbp = &hba->lrb[tag];
 479
 480                 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
 481                                 tag, ktime_to_us(lrbp->issue_time_stamp));
 482                 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
 483                                 tag, ktime_to_us(lrbp->compl_time_stamp));
 484                 dev_err(hba->dev,
 485                         "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
 486                         tag, (u64)lrbp->utrd_dma_addr);
 487
 488                 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
 489                                 sizeof(struct utp_transfer_req_desc));
 490                 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
 491                         (u64)lrbp->ucd_req_dma_addr);
 492                 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
 493                                 sizeof(struct utp_upiu_req));
 494                 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
 495                         (u64)lrbp->ucd_rsp_dma_addr);
 496                 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
 497                                 sizeof(struct utp_upiu_rsp));
 498
 499                 prdt_length = le16_to_cpu(
 500                         lrbp->utr_descriptor_ptr->prd_table_length);
 501                 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
 502                         prdt_length /= sizeof(struct ufshcd_sg_entry);
 503
 504                 dev_err(hba->dev,
 505                         "UPIU[%d] - PRDT - %d entries  phys@0x%llx\n",
 506                         tag, prdt_length,
 507                         (u64)lrbp->ucd_prdt_dma_addr);
 508
 509                 if (pr_prdt)
 510                         ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
 511                                 sizeof(struct ufshcd_sg_entry) * prdt_length);
 512         }
 513 }
 514
 515 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
 516 {
 517         int tag;
 518
 519         for_each_set_bit(tag, &bitmap, hba->nutmrs) {
 520                 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
 521
 522                 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
 523                 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
 524         }
 525 }
 526
 527 static void ufshcd_print_host_state(struct ufs_hba *hba)
 528 {
 529         struct scsi_device *sdev_ufs = hba->sdev_ufs_device;
 530
 531         dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
 532         dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n",
 533                 hba->outstanding_reqs, hba->outstanding_tasks);
 534         dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
 535                 hba->saved_err, hba->saved_uic_err);
 536         dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
 537                 hba->curr_dev_pwr_mode, hba->uic_link_state);
 538         dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
 539                 hba->pm_op_in_progress, hba->is_sys_suspended);
 540         dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
 541                 hba->auto_bkops_enabled, hba->host->host_self_blocked);
 542         dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
 543         dev_err(hba->dev,
 544                 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n",
 545                 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
 546                 hba->ufs_stats.hibern8_exit_cnt);
 547         dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n",
 548                 ktime_to_us(hba->ufs_stats.last_intr_ts),
 549                 hba->ufs_stats.last_intr_status);
 550         dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
 551                 hba->eh_flags, hba->req_abort_count);
 552         dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n",
 553                 hba->ufs_version, hba->capabilities, hba->caps);
 554         dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
 555                 hba->dev_quirks);
 556         if (sdev_ufs)
 557                 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n",
 558                         sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev);
 559
 560         ufshcd_print_clk_freqs(hba);
 561 }
 562
 563 /**
 564  * ufshcd_print_pwr_info - print power params as saved in hba
 565  * power info
 566  * @hba: per-adapter instance
 567  */
 568 static void ufshcd_print_pwr_info(struct ufs_hba *hba)
 569 {
 570         static const char * const names[] = {
 571                 "INVALID MODE",
 572                 "FAST MODE",
 573                 "SLOW_MODE",
 574                 "INVALID MODE",
 575                 "FASTAUTO_MODE",
 576                 "SLOWAUTO_MODE",
 577                 "INVALID MODE",
 578         };
 579
 580         dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
 581                  __func__,
 582                  hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
 583                  hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
 584                  names[hba->pwr_info.pwr_rx],
 585                  names[hba->pwr_info.pwr_tx],
 586                  hba->pwr_info.hs_rate);
 587 }
 588
 589 static void ufshcd_device_reset(struct ufs_hba *hba)
 590 {
 591         int err;
 592
 593         err = ufshcd_vops_device_reset(hba);
 594
 595         if (!err) {
 596                 ufshcd_set_ufs_dev_active(hba);
 597                 if (ufshcd_is_wb_allowed(hba)) {
 598                         hba->dev_info.wb_enabled = false;
 599                         hba->dev_info.wb_buf_flush_enabled = false;
 600                 }
 601         }
 602         if (err != -EOPNOTSUPP)
 603                 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err);
 604 }
 605
 606 void ufshcd_delay_us(unsigned long us, unsigned long tolerance)
 607 {
 608         if (!us)
 609                 return;
 610
 611         if (us < 10)
 612                 udelay(us);
 613         else
 614                 usleep_range(us, us + tolerance);
 615 }
 616 EXPORT_SYMBOL_GPL(ufshcd_delay_us);
 617
 618 /**
 619  * ufshcd_wait_for_register - wait for register value to change
 620  * @hba: per-adapter interface
 621  * @reg: mmio register offset
 622  * @mask: mask to apply to the read register value
 623  * @val: value to wait for
 624  * @interval_us: polling interval in microseconds
 625  * @timeout_ms: timeout in milliseconds
 626  *
 627  * Return:
 628  * -ETIMEDOUT on error, zero on success.
 629  */
 630 int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
 631                                 u32 val, unsigned long interval_us,
 632                                 unsigned long timeout_ms)
 633 {
 634         int err = 0;
 635         unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
 636
 637         /* ignore bits that we don't intend to wait on */
 638         val = val & mask;
 639
 640         while ((ufshcd_readl(hba, reg) & mask) != val) {
 641                 usleep_range(interval_us, interval_us + 50);
 642                 if (time_after(jiffies, timeout)) {
 643                         if ((ufshcd_readl(hba, reg) & mask) != val)
 644                                 err = -ETIMEDOUT;
 645                         break;
 646                 }
 647         }
 648
 649         return err;
 650 }
 651
 652 /**
 653  * ufshcd_get_intr_mask - Get the interrupt bit mask
 654  * @hba: Pointer to adapter instance
 655  *
 656  * Returns interrupt bit mask per version
 657  */
 658 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
 659 {
 660         if (hba->ufs_version == ufshci_version(1, 0))
 661                 return INTERRUPT_MASK_ALL_VER_10;
 662         if (hba->ufs_version <= ufshci_version(2, 0))
 663                 return INTERRUPT_MASK_ALL_VER_11;
 664
 665         return INTERRUPT_MASK_ALL_VER_21;
 666 }
 667
 668 /**
 669  * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
 670  * @hba: Pointer to adapter instance
 671  *
 672  * Returns UFSHCI version supported by the controller
 673  */
 674 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
 675 {
 676         u32 ufshci_ver;
 677
 678         if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
 679                 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba);
 680         else
 681                 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION);
 682
 683         /*
 684          * UFSHCI v1.x uses a different version scheme, in order
 685          * to allow the use of comparisons with the ufshci_version
 686          * function, we convert it to the same scheme as ufs 2.0+.
 687          */
 688         if (ufshci_ver & 0x00010000)
 689                 return ufshci_version(1, ufshci_ver & 0x00000100);
 690
 691         return ufshci_ver;
 692 }
 693
 694 /**
 695  * ufshcd_is_device_present - Check if any device connected to
 696  *                            the host controller
 697  * @hba: pointer to adapter instance
 698  *
 699  * Returns true if device present, false if no device detected
 700  */
 701 static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
 702 {
 703         return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
 704                                                 DEVICE_PRESENT) ? true : false;
 705 }
 706
 707 /**
 708  * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
 709  * @lrbp: pointer to local command reference block
 710  *
 711  * This function is used to get the OCS field from UTRD
 712  * Returns the OCS field in the UTRD
 713  */
 714 static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
 715 {
 716         return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
 717 }
 718
 719 /**
 720  * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
 721  * @hba: per adapter instance
 722  * @pos: position of the bit to be cleared
 723  */
 724 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
 725 {
 726         if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
 727                 ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
 728         else
 729                 ufshcd_writel(hba, ~(1 << pos),
 730                                 REG_UTP_TRANSFER_REQ_LIST_CLEAR);
 731 }
 732
 733 /**
 734  * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
 735  * @hba: per adapter instance
 736  * @pos: position of the bit to be cleared
 737  */
 738 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
 739 {
 740         if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
 741                 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
 742         else
 743                 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
 744 }
 745
 746 /**
 747  * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
 748  * @reg: Register value of host controller status
 749  *
 750  * Returns integer, 0 on Success and positive value if failed
 751  */
 752 static inline int ufshcd_get_lists_status(u32 reg)
 753 {
 754         return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
 755 }
 756
 757 /**
 758  * ufshcd_get_uic_cmd_result - Get the UIC command result
 759  * @hba: Pointer to adapter instance
 760  *
 761  * This function gets the result of UIC command completion
 762  * Returns 0 on success, non zero value on error
 763  */
 764 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
 765 {
 766         return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
 767                MASK_UIC_COMMAND_RESULT;
 768 }
 769
 770 /**
 771  * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
 772  * @hba: Pointer to adapter instance
 773  *
 774  * This function gets UIC command argument3
 775  * Returns 0 on success, non zero value on error
 776  */
 777 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
 778 {
 779         return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
 780 }
 781
 782 /**
 783  * ufshcd_get_req_rsp - returns the TR response transaction type
 784  * @ucd_rsp_ptr: pointer to response UPIU
 785  */
 786 static inline int
 787 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
 788 {
 789         return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
 790 }
 791
 792 /**
 793  * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
 794  * @ucd_rsp_ptr: pointer to response UPIU
 795  *
 796  * This function gets the response status and scsi_status from response UPIU
 797  * Returns the response result code.
 798  */
 799 static inline int
 800 ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
 801 {
 802         return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
 803 }
 804
 805 /*
 806  * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
 807  *                              from response UPIU
 808  * @ucd_rsp_ptr: pointer to response UPIU
 809  *
 810  * Return the data segment length.
 811  */
 812 static inline unsigned int
 813 ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
 814 {
 815         return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
 816                 MASK_RSP_UPIU_DATA_SEG_LEN;
 817 }
 818
 819 /**
 820  * ufshcd_is_exception_event - Check if the device raised an exception event
 821  * @ucd_rsp_ptr: pointer to response UPIU
 822  *
 823  * The function checks if the device raised an exception event indicated in
 824  * the Device Information field of response UPIU.
 825  *
 826  * Returns true if exception is raised, false otherwise.
 827  */
 828 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
 829 {
 830         return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
 831                         MASK_RSP_EXCEPTION_EVENT ? true : false;
 832 }
 833
 834 /**
 835  * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
 836  * @hba: per adapter instance
 837  */
 838 static inline void
 839 ufshcd_reset_intr_aggr(struct ufs_hba *hba)
 840 {
 841         ufshcd_writel(hba, INT_AGGR_ENABLE |
 842                       INT_AGGR_COUNTER_AND_TIMER_RESET,
 843                       REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
 844 }
 845
 846 /**
 847  * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
 848  * @hba: per adapter instance
 849  * @cnt: Interrupt aggregation counter threshold
 850  * @tmout: Interrupt aggregation timeout value
 851  */
 852 static inline void
 853 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
 854 {
 855         ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
 856                       INT_AGGR_COUNTER_THLD_VAL(cnt) |
 857                       INT_AGGR_TIMEOUT_VAL(tmout),
 858                       REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
 859 }
 860
 861 /**
 862  * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
 863  * @hba: per adapter instance
 864  */
 865 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
 866 {
 867         ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
 868 }
 869
 870 /**
 871  * ufshcd_enable_run_stop_reg - Enable run-stop registers,
 872  *                      When run-stop registers are set to 1, it indicates the
 873  *                      host controller that it can process the requests
 874  * @hba: per adapter instance
 875  */
 876 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
 877 {
 878         ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
 879                       REG_UTP_TASK_REQ_LIST_RUN_STOP);
 880         ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
 881                       REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
 882 }
 883
 884 /**
 885  * ufshcd_hba_start - Start controller initialization sequence
 886  * @hba: per adapter instance
 887  */
 888 static inline void ufshcd_hba_start(struct ufs_hba *hba)
 889 {
 890         u32 val = CONTROLLER_ENABLE;
 891
 892         if (ufshcd_crypto_enable(hba))
 893                 val |= CRYPTO_GENERAL_ENABLE;
 894
 895         ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
 896 }
 897
 898 /**
 899  * ufshcd_is_hba_active - Get controller state
 900  * @hba: per adapter instance
 901  *
 902  * Returns false if controller is active, true otherwise
 903  */
 904 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
 905 {
 906         return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
 907                 ? false : true;
 908 }
 909
 910 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
 911 {
 912         /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
 913         if (hba->ufs_version <= ufshci_version(1, 1))
 914                 return UFS_UNIPRO_VER_1_41;
 915         else
 916                 return UFS_UNIPRO_VER_1_6;
 917 }
 918 EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
 919
 920 static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
 921 {
 922         /*
 923          * If both host and device support UniPro ver1.6 or later, PA layer
 924          * parameters tuning happens during link startup itself.
 925          *
 926          * We can manually tune PA layer parameters if either host or device
 927          * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
 928          * logic simple, we will only do manual tuning if local unipro version
 929          * doesn't support ver1.6 or later.
 930          */
 931         if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
 932                 return true;
 933         else
 934                 return false;
 935 }
 936
 937 /**
 938  * ufshcd_set_clk_freq - set UFS controller clock frequencies
 939  * @hba: per adapter instance
 940  * @scale_up: If True, set max possible frequency othewise set low frequency
 941  *
 942  * Returns 0 if successful
 943  * Returns < 0 for any other errors
 944  */
 945 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
 946 {
 947         int ret = 0;
 948         struct ufs_clk_info *clki;
 949         struct list_head *head = &hba->clk_list_head;
 950
 951         if (list_empty(head))
 952                 goto out;
 953
 954         list_for_each_entry(clki, head, list) {
 955                 if (!IS_ERR_OR_NULL(clki->clk)) {
 956                         if (scale_up && clki->max_freq) {
 957                                 if (clki->curr_freq == clki->max_freq)
 958                                         continue;
 959
 960                                 ret = clk_set_rate(clki->clk, clki->max_freq);
 961                                 if (ret) {
 962                                         dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
 963                                                 __func__, clki->name,
 964                                                 clki->max_freq, ret);
 965                                         break;
 966                                 }
 967                                 trace_ufshcd_clk_scaling(dev_name(hba->dev),
 968                                                 "scaled up", clki->name,
 969                                                 clki->curr_freq,
 970                                                 clki->max_freq);
 971
 972                                 clki->curr_freq = clki->max_freq;
 973
 974                         } else if (!scale_up && clki->min_freq) {
 975                                 if (clki->curr_freq == clki->min_freq)
 976                                         continue;
 977
 978                                 ret = clk_set_rate(clki->clk, clki->min_freq);
 979                                 if (ret) {
 980                                         dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
 981                                                 __func__, clki->name,
 982                                                 clki->min_freq, ret);
 983                                         break;
 984                                 }
 985                                 trace_ufshcd_clk_scaling(dev_name(hba->dev),
 986                                                 "scaled down", clki->name,
 987                                                 clki->curr_freq,
 988                                                 clki->min_freq);
 989                                 clki->curr_freq = clki->min_freq;
 990                         }
 991                 }
 992                 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
 993                                 clki->name, clk_get_rate(clki->clk));
 994         }
 995
 996 out:
 997         return ret;
 998 }
 999
1000 /**
1001  * ufshcd_scale_clks - scale up or scale down UFS controller clocks
1002  * @hba: per adapter instance
1003  * @scale_up: True if scaling up and false if scaling down
1004  *
1005  * Returns 0 if successful
1006  * Returns < 0 for any other errors
1007  */
1008 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
1009 {
1010         int ret = 0;
1011         ktime_t start = ktime_get();
1012
1013         ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
1014         if (ret)
1015                 goto out;
1016
1017         ret = ufshcd_set_clk_freq(hba, scale_up);
1018         if (ret)
1019                 goto out;
1020
1021         ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1022         if (ret)
1023                 ufshcd_set_clk_freq(hba, !scale_up);
1024
1025 out:
1026         trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1027                         (scale_up ? "up" : "down"),
1028                         ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1029         return ret;
1030 }
1031
1032 /**
1033  * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
1034  * @hba: per adapter instance
1035  * @scale_up: True if scaling up and false if scaling down
1036  *
1037  * Returns true if scaling is required, false otherwise.
1038  */
1039 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
1040                                                bool scale_up)
1041 {
1042         struct ufs_clk_info *clki;
1043         struct list_head *head = &hba->clk_list_head;
1044
1045         if (list_empty(head))
1046                 return false;
1047
1048         list_for_each_entry(clki, head, list) {
1049                 if (!IS_ERR_OR_NULL(clki->clk)) {
1050                         if (scale_up && clki->max_freq) {
1051                                 if (clki->curr_freq == clki->max_freq)
1052                                         continue;
1053                                 return true;
1054                         } else if (!scale_up && clki->min_freq) {
1055                                 if (clki->curr_freq == clki->min_freq)
1056                                         continue;
1057                                 return true;
1058                         }
1059                 }
1060         }
1061
1062         return false;
1063 }
1064
1065 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1066                                         u64 wait_timeout_us)
1067 {
1068         unsigned long flags;
1069         int ret = 0;
1070         u32 tm_doorbell;
1071         u32 tr_doorbell;
1072         bool timeout = false, do_last_check = false;
1073         ktime_t start;
1074
1075         ufshcd_hold(hba, false);
1076         spin_lock_irqsave(hba->host->host_lock, flags);
1077         /*
1078          * Wait for all the outstanding tasks/transfer requests.
1079          * Verify by checking the doorbell registers are clear.
1080          */
1081         start = ktime_get();
1082         do {
1083                 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1084                         ret = -EBUSY;
1085                         goto out;
1086                 }
1087
1088                 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1089                 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1090                 if (!tm_doorbell && !tr_doorbell) {
1091                         timeout = false;
1092                         break;
1093                 } else if (do_last_check) {
1094                         break;
1095                 }
1096
1097                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1098                 schedule();
1099                 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1100                     wait_timeout_us) {
1101                         timeout = true;
1102                         /*
1103                          * We might have scheduled out for long time so make
1104                          * sure to check if doorbells are cleared by this time
1105                          * or not.
1106                          */
1107                         do_last_check = true;
1108                 }
1109                 spin_lock_irqsave(hba->host->host_lock, flags);
1110         } while (tm_doorbell || tr_doorbell);
1111
1112         if (timeout) {
1113                 dev_err(hba->dev,
1114                         "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1115                         __func__, tm_doorbell, tr_doorbell);
1116                 ret = -EBUSY;
1117         }
1118 out:
1119         spin_unlock_irqrestore(hba->host->host_lock, flags);
1120         ufshcd_release(hba);
1121         return ret;
1122 }
1123
1124 /**
1125  * ufshcd_scale_gear - scale up/down UFS gear
1126  * @hba: per adapter instance
1127  * @scale_up: True for scaling up gear and false for scaling down
1128  *
1129  * Returns 0 for success,
1130  * Returns -EBUSY if scaling can't happen at this time
1131  * Returns non-zero for any other errors
1132  */
1133 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1134 {
1135         int ret = 0;
1136         struct ufs_pa_layer_attr new_pwr_info;
1137
1138         if (scale_up) {
1139                 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1140                        sizeof(struct ufs_pa_layer_attr));
1141         } else {
1142                 memcpy(&new_pwr_info, &hba->pwr_info,
1143                        sizeof(struct ufs_pa_layer_attr));
1144
1145                 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear ||
1146                     hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) {
1147                         /* save the current power mode */
1148                         memcpy(&hba->clk_scaling.saved_pwr_info.info,
1149                                 &hba->pwr_info,
1150                                 sizeof(struct ufs_pa_layer_attr));
1151
1152                         /* scale down gear */
1153                         new_pwr_info.gear_tx = hba->clk_scaling.min_gear;
1154                         new_pwr_info.gear_rx = hba->clk_scaling.min_gear;
1155                 }
1156         }
1157
1158         /* check if the power mode needs to be changed or not? */
1159         ret = ufshcd_config_pwr_mode(hba, &new_pwr_info);
1160         if (ret)
1161                 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1162                         __func__, ret,
1163                         hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1164                         new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1165
1166         return ret;
1167 }
1168
1169 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1170 {
1171         #define DOORBELL_CLR_TOUT_US            (1000 * 1000) /* 1 sec */
1172         int ret = 0;
1173         /*
1174          * make sure that there are no outstanding requests when
1175          * clock scaling is in progress
1176          */
1177         ufshcd_scsi_block_requests(hba);
1178         down_write(&hba->clk_scaling_lock);
1179
1180         if (!hba->clk_scaling.is_allowed ||
1181             ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1182                 ret = -EBUSY;
1183                 up_write(&hba->clk_scaling_lock);
1184                 ufshcd_scsi_unblock_requests(hba);
1185                 goto out;
1186         }
1187
1188         /* let's not get into low power until clock scaling is completed */
1189         ufshcd_hold(hba, false);
1190
1191 out:
1192         return ret;
1193 }
1194
1195 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, bool writelock)
1196 {
1197         if (writelock)
1198                 up_write(&hba->clk_scaling_lock);
1199         else
1200                 up_read(&hba->clk_scaling_lock);
1201         ufshcd_scsi_unblock_requests(hba);
1202         ufshcd_release(hba);
1203 }
1204
1205 /**
1206  * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1207  * @hba: per adapter instance
1208  * @scale_up: True for scaling up and false for scalin down
1209  *
1210  * Returns 0 for success,
1211  * Returns -EBUSY if scaling can't happen at this time
1212  * Returns non-zero for any other errors
1213  */
1214 static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1215 {
1216         int ret = 0;
1217         bool is_writelock = true;
1218
1219         ret = ufshcd_clock_scaling_prepare(hba);
1220         if (ret)
1221                 return ret;
1222
1223         /* scale down the gear before scaling down clocks */
1224         if (!scale_up) {
1225                 ret = ufshcd_scale_gear(hba, false);
1226                 if (ret)
1227                         goto out_unprepare;
1228         }
1229
1230         ret = ufshcd_scale_clks(hba, scale_up);
1231         if (ret) {
1232                 if (!scale_up)
1233                         ufshcd_scale_gear(hba, true);
1234                 goto out_unprepare;
1235         }
1236
1237         /* scale up the gear after scaling up clocks */
1238         if (scale_up) {
1239                 ret = ufshcd_scale_gear(hba, true);
1240                 if (ret) {
1241                         ufshcd_scale_clks(hba, false);
1242                         goto out_unprepare;
1243                 }
1244         }
1245
1246         /* Enable Write Booster if we have scaled up else disable it */
1247         downgrade_write(&hba->clk_scaling_lock);
1248         is_writelock = false;
1249         ufshcd_wb_toggle(hba, scale_up);
1250
1251 out_unprepare:
1252         ufshcd_clock_scaling_unprepare(hba, is_writelock);
1253         return ret;
1254 }
1255
1256 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1257 {
1258         struct ufs_hba *hba = container_of(work, struct ufs_hba,
1259                                            clk_scaling.suspend_work);
1260         unsigned long irq_flags;
1261
1262         spin_lock_irqsave(hba->host->host_lock, irq_flags);
1263         if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1264                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1265                 return;
1266         }
1267         hba->clk_scaling.is_suspended = true;
1268         spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1269
1270         __ufshcd_suspend_clkscaling(hba);
1271 }
1272
1273 static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1274 {
1275         struct ufs_hba *hba = container_of(work, struct ufs_hba,
1276                                            clk_scaling.resume_work);
1277         unsigned long irq_flags;
1278
1279         spin_lock_irqsave(hba->host->host_lock, irq_flags);
1280         if (!hba->clk_scaling.is_suspended) {
1281                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1282                 return;
1283         }
1284         hba->clk_scaling.is_suspended = false;
1285         spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1286
1287         devfreq_resume_device(hba->devfreq);
1288 }
1289
1290 static int ufshcd_devfreq_target(struct device *dev,
1291                                 unsigned long *freq, u32 flags)
1292 {
1293         int ret = 0;
1294         struct ufs_hba *hba = dev_get_drvdata(dev);
1295         ktime_t start;
1296         bool scale_up, sched_clk_scaling_suspend_work = false;
1297         struct list_head *clk_list = &hba->clk_list_head;
1298         struct ufs_clk_info *clki;
1299         unsigned long irq_flags;
1300
1301         if (!ufshcd_is_clkscaling_supported(hba))
1302                 return -EINVAL;
1303
1304         clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1305         /* Override with the closest supported frequency */
1306         *freq = (unsigned long) clk_round_rate(clki->clk, *freq);
1307         spin_lock_irqsave(hba->host->host_lock, irq_flags);
1308         if (ufshcd_eh_in_progress(hba)) {
1309                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1310                 return 0;
1311         }
1312
1313         if (!hba->clk_scaling.active_reqs)
1314                 sched_clk_scaling_suspend_work = true;
1315
1316         if (list_empty(clk_list)) {
1317                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1318                 goto out;
1319         }
1320
1321         /* Decide based on the rounded-off frequency and update */
1322         scale_up = (*freq == clki->max_freq) ? true : false;
1323         if (!scale_up)
1324                 *freq = clki->min_freq;
1325         /* Update the frequency */
1326         if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1327                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1328                 ret = 0;
1329                 goto out; /* no state change required */
1330         }
1331         spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1332
1333         start = ktime_get();
1334         ret = ufshcd_devfreq_scale(hba, scale_up);
1335
1336         trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1337                 (scale_up ? "up" : "down"),
1338                 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1339
1340 out:
1341         if (sched_clk_scaling_suspend_work)
1342                 queue_work(hba->clk_scaling.workq,
1343                            &hba->clk_scaling.suspend_work);
1344
1345         return ret;
1346 }
1347
1348 static bool ufshcd_is_busy(struct request *req, void *priv, bool reserved)
1349 {
1350         int *busy = priv;
1351
1352         WARN_ON_ONCE(reserved);
1353         (*busy)++;
1354         return false;
1355 }
1356
1357 /* Whether or not any tag is in use by a request that is in progress. */
1358 static bool ufshcd_any_tag_in_use(struct ufs_hba *hba)
1359 {
1360         struct request_queue *q = hba->cmd_queue;
1361         int busy = 0;
1362
1363         blk_mq_tagset_busy_iter(q->tag_set, ufshcd_is_busy, &busy);
1364         return busy;
1365 }
1366
1367 static int ufshcd_devfreq_get_dev_status(struct device *dev,
1368                 struct devfreq_dev_status *stat)
1369 {
1370         struct ufs_hba *hba = dev_get_drvdata(dev);
1371         struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1372         unsigned long flags;
1373         struct list_head *clk_list = &hba->clk_list_head;
1374         struct ufs_clk_info *clki;
1375         ktime_t curr_t;
1376
1377         if (!ufshcd_is_clkscaling_supported(hba))
1378                 return -EINVAL;
1379
1380         memset(stat, 0, sizeof(*stat));
1381
1382         spin_lock_irqsave(hba->host->host_lock, flags);
1383         curr_t = ktime_get();
1384         if (!scaling->window_start_t)
1385                 goto start_window;
1386
1387         clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1388         /*
1389          * If current frequency is 0, then the ondemand governor considers
1390          * there's no initial frequency set. And it always requests to set
1391          * to max. frequency.
1392          */
1393         stat->current_frequency = clki->curr_freq;
1394         if (scaling->is_busy_started)
1395                 scaling->tot_busy_t += ktime_us_delta(curr_t,
1396                                 scaling->busy_start_t);
1397
1398         stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t);
1399         stat->busy_time = scaling->tot_busy_t;
1400 start_window:
1401         scaling->window_start_t = curr_t;
1402         scaling->tot_busy_t = 0;
1403
1404         if (hba->outstanding_reqs) {
1405                 scaling->busy_start_t = curr_t;
1406                 scaling->is_busy_started = true;
1407         } else {
1408                 scaling->busy_start_t = 0;
1409                 scaling->is_busy_started = false;
1410         }
1411         spin_unlock_irqrestore(hba->host->host_lock, flags);
1412         return 0;
1413 }
1414
1415 static int ufshcd_devfreq_init(struct ufs_hba *hba)
1416 {
1417         struct list_head *clk_list = &hba->clk_list_head;
1418         struct ufs_clk_info *clki;
1419         struct devfreq *devfreq;
1420         int ret;
1421
1422         /* Skip devfreq if we don't have any clocks in the list */
1423         if (list_empty(clk_list))
1424                 return 0;
1425
1426         clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1427         dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1428         dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1429
1430         ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile,
1431                                          &hba->vps->ondemand_data);
1432         devfreq = devfreq_add_device(hba->dev,
1433                         &hba->vps->devfreq_profile,
1434                         DEVFREQ_GOV_SIMPLE_ONDEMAND,
1435                         &hba->vps->ondemand_data);
1436         if (IS_ERR(devfreq)) {
1437                 ret = PTR_ERR(devfreq);
1438                 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
1439
1440                 dev_pm_opp_remove(hba->dev, clki->min_freq);
1441                 dev_pm_opp_remove(hba->dev, clki->max_freq);
1442                 return ret;
1443         }
1444
1445         hba->devfreq = devfreq;
1446
1447         return 0;
1448 }
1449
1450 static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1451 {
1452         struct list_head *clk_list = &hba->clk_list_head;
1453         struct ufs_clk_info *clki;
1454
1455         if (!hba->devfreq)
1456                 return;
1457
1458         devfreq_remove_device(hba->devfreq);
1459         hba->devfreq = NULL;
1460
1461         clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1462         dev_pm_opp_remove(hba->dev, clki->min_freq);
1463         dev_pm_opp_remove(hba->dev, clki->max_freq);
1464 }
1465
1466 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1467 {
1468         unsigned long flags;
1469
1470         devfreq_suspend_device(hba->devfreq);
1471         spin_lock_irqsave(hba->host->host_lock, flags);
1472         hba->clk_scaling.window_start_t = 0;
1473         spin_unlock_irqrestore(hba->host->host_lock, flags);
1474 }
1475
1476 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1477 {
1478         unsigned long flags;
1479         bool suspend = false;
1480
1481         cancel_work_sync(&hba->clk_scaling.suspend_work);
1482         cancel_work_sync(&hba->clk_scaling.resume_work);
1483
1484         spin_lock_irqsave(hba->host->host_lock, flags);
1485         if (!hba->clk_scaling.is_suspended) {
1486                 suspend = true;
1487                 hba->clk_scaling.is_suspended = true;
1488         }
1489         spin_unlock_irqrestore(hba->host->host_lock, flags);
1490
1491         if (suspend)
1492                 __ufshcd_suspend_clkscaling(hba);
1493 }
1494
1495 static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1496 {
1497         unsigned long flags;
1498         bool resume = false;
1499
1500         spin_lock_irqsave(hba->host->host_lock, flags);
1501         if (hba->clk_scaling.is_suspended) {
1502                 resume = true;
1503                 hba->clk_scaling.is_suspended = false;
1504         }
1505         spin_unlock_irqrestore(hba->host->host_lock, flags);
1506
1507         if (resume)
1508                 devfreq_resume_device(hba->devfreq);
1509 }
1510
1511 static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1512                 struct device_attribute *attr, char *buf)
1513 {
1514         struct ufs_hba *hba = dev_get_drvdata(dev);
1515
1516         return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled);
1517 }
1518
1519 static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1520                 struct device_attribute *attr, const char *buf, size_t count)
1521 {
1522         struct ufs_hba *hba = dev_get_drvdata(dev);
1523         u32 value;
1524         int err = 0;
1525
1526         if (kstrtou32(buf, 0, &value))
1527                 return -EINVAL;
1528
1529         down(&hba->host_sem);
1530         if (!ufshcd_is_user_access_allowed(hba)) {
1531                 err = -EBUSY;
1532                 goto out;
1533         }
1534
1535         value = !!value;
1536         if (value == hba->clk_scaling.is_enabled)
1537                 goto out;
1538
1539         ufshcd_rpm_get_sync(hba);
1540         ufshcd_hold(hba, false);
1541
1542         hba->clk_scaling.is_enabled = value;
1543
1544         if (value) {
1545                 ufshcd_resume_clkscaling(hba);
1546         } else {
1547                 ufshcd_suspend_clkscaling(hba);
1548                 err = ufshcd_devfreq_scale(hba, true);
1549                 if (err)
1550                         dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1551                                         __func__, err);
1552         }
1553
1554         ufshcd_release(hba);
1555         ufshcd_rpm_put_sync(hba);
1556 out:
1557         up(&hba->host_sem);
1558         return err ? err : count;
1559 }
1560
1561 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba)
1562 {
1563         hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1564         hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1565         sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1566         hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1567         hba->clk_scaling.enable_attr.attr.mode = 0644;
1568         if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1569                 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1570 }
1571
1572 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba)
1573 {
1574         if (hba->clk_scaling.enable_attr.attr.name)
1575                 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
1576 }
1577
1578 static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1579 {
1580         char wq_name[sizeof("ufs_clkscaling_00")];
1581
1582         if (!ufshcd_is_clkscaling_supported(hba))
1583                 return;
1584
1585         if (!hba->clk_scaling.min_gear)
1586                 hba->clk_scaling.min_gear = UFS_HS_G1;
1587
1588         INIT_WORK(&hba->clk_scaling.suspend_work,
1589                   ufshcd_clk_scaling_suspend_work);
1590         INIT_WORK(&hba->clk_scaling.resume_work,
1591                   ufshcd_clk_scaling_resume_work);
1592
1593         snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1594                  hba->host->host_no);
1595         hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1596
1597         hba->clk_scaling.is_initialized = true;
1598 }
1599
1600 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1601 {
1602         if (!hba->clk_scaling.is_initialized)
1603                 return;
1604
1605         ufshcd_remove_clk_scaling_sysfs(hba);
1606         destroy_workqueue(hba->clk_scaling.workq);
1607         ufshcd_devfreq_remove(hba);
1608         hba->clk_scaling.is_initialized = false;
1609 }
1610
1611 static void ufshcd_ungate_work(struct work_struct *work)
1612 {
1613         int ret;
1614         unsigned long flags;
1615         struct ufs_hba *hba = container_of(work, struct ufs_hba,
1616                         clk_gating.ungate_work);
1617
1618         cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1619
1620         spin_lock_irqsave(hba->host->host_lock, flags);
1621         if (hba->clk_gating.state == CLKS_ON) {
1622                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1623                 goto unblock_reqs;
1624         }
1625
1626         spin_unlock_irqrestore(hba->host->host_lock, flags);
1627         ufshcd_hba_vreg_set_hpm(hba);
1628         ufshcd_setup_clocks(hba, true);
1629
1630         ufshcd_enable_irq(hba);
1631
1632         /* Exit from hibern8 */
1633         if (ufshcd_can_hibern8_during_gating(hba)) {
1634                 /* Prevent gating in this path */
1635                 hba->clk_gating.is_suspended = true;
1636                 if (ufshcd_is_link_hibern8(hba)) {
1637                         ret = ufshcd_uic_hibern8_exit(hba);
1638                         if (ret)
1639                                 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1640                                         __func__, ret);
1641                         else
1642                                 ufshcd_set_link_active(hba);
1643                 }
1644                 hba->clk_gating.is_suspended = false;
1645         }
1646 unblock_reqs:
1647         ufshcd_scsi_unblock_requests(hba);
1648 }
1649
1650 /**
1651  * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1652  * Also, exit from hibern8 mode and set the link as active.
1653  * @hba: per adapter instance
1654  * @async: This indicates whether caller should ungate clocks asynchronously.
1655  */
1656 int ufshcd_hold(struct ufs_hba *hba, bool async)
1657 {
1658         int rc = 0;
1659         bool flush_result;
1660         unsigned long flags;
1661
1662         if (!ufshcd_is_clkgating_allowed(hba))
1663                 goto out;
1664         spin_lock_irqsave(hba->host->host_lock, flags);
1665         hba->clk_gating.active_reqs++;
1666
1667 start:
1668         switch (hba->clk_gating.state) {
1669         case CLKS_ON:
1670                 /*
1671                  * Wait for the ungate work to complete if in progress.
1672                  * Though the clocks may be in ON state, the link could
1673                  * still be in hibner8 state if hibern8 is allowed
1674                  * during clock gating.
1675                  * Make sure we exit hibern8 state also in addition to
1676                  * clocks being ON.
1677                  */
1678                 if (ufshcd_can_hibern8_during_gating(hba) &&
1679                     ufshcd_is_link_hibern8(hba)) {
1680                         if (async) {
1681                                 rc = -EAGAIN;
1682                                 hba->clk_gating.active_reqs--;
1683                                 break;
1684                         }
1685                         spin_unlock_irqrestore(hba->host->host_lock, flags);
1686                         flush_result = flush_work(&hba->clk_gating.ungate_work);
1687                         if (hba->clk_gating.is_suspended && !flush_result)
1688                                 goto out;
1689                         spin_lock_irqsave(hba->host->host_lock, flags);
1690                         goto start;
1691                 }
1692                 break;
1693         case REQ_CLKS_OFF:
1694                 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1695                         hba->clk_gating.state = CLKS_ON;
1696                         trace_ufshcd_clk_gating(dev_name(hba->dev),
1697                                                 hba->clk_gating.state);
1698                         break;
1699                 }
1700                 /*
1701                  * If we are here, it means gating work is either done or
1702                  * currently running. Hence, fall through to cancel gating
1703                  * work and to enable clocks.
1704                  */
1705                 fallthrough;
1706         case CLKS_OFF:
1707                 hba->clk_gating.state = REQ_CLKS_ON;
1708                 trace_ufshcd_clk_gating(dev_name(hba->dev),
1709                                         hba->clk_gating.state);
1710                 if (queue_work(hba->clk_gating.clk_gating_workq,
1711                                &hba->clk_gating.ungate_work))
1712                         ufshcd_scsi_block_requests(hba);
1713                 /*
1714                  * fall through to check if we should wait for this
1715                  * work to be done or not.
1716                  */
1717                 fallthrough;
1718         case REQ_CLKS_ON:
1719                 if (async) {
1720                         rc = -EAGAIN;
1721                         hba->clk_gating.active_reqs--;
1722                         break;
1723                 }
1724
1725                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1726                 flush_work(&hba->clk_gating.ungate_work);
1727                 /* Make sure state is CLKS_ON before returning */
1728                 spin_lock_irqsave(hba->host->host_lock, flags);
1729                 goto start;
1730         default:
1731                 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1732                                 __func__, hba->clk_gating.state);
1733                 break;
1734         }
1735         spin_unlock_irqrestore(hba->host->host_lock, flags);
1736 out:
1737         return rc;
1738 }
1739 EXPORT_SYMBOL_GPL(ufshcd_hold);
1740
1741 static void ufshcd_gate_work(struct work_struct *work)
1742 {
1743         struct ufs_hba *hba = container_of(work, struct ufs_hba,
1744                         clk_gating.gate_work.work);
1745         unsigned long flags;
1746         int ret;
1747
1748         spin_lock_irqsave(hba->host->host_lock, flags);
1749         /*
1750          * In case you are here to cancel this work the gating state
1751          * would be marked as REQ_CLKS_ON. In this case save time by
1752          * skipping the gating work and exit after changing the clock
1753          * state to CLKS_ON.
1754          */
1755         if (hba->clk_gating.is_suspended ||
1756                 (hba->clk_gating.state != REQ_CLKS_OFF)) {
1757                 hba->clk_gating.state = CLKS_ON;
1758                 trace_ufshcd_clk_gating(dev_name(hba->dev),
1759                                         hba->clk_gating.state);
1760                 goto rel_lock;
1761         }
1762
1763         if (hba->clk_gating.active_reqs
1764                 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1765                 || ufshcd_any_tag_in_use(hba) || hba->outstanding_tasks
1766                 || hba->active_uic_cmd || hba->uic_async_done)
1767                 goto rel_lock;
1768
1769         spin_unlock_irqrestore(hba->host->host_lock, flags);
1770
1771         /* put the link into hibern8 mode before turning off clocks */
1772         if (ufshcd_can_hibern8_during_gating(hba)) {
1773                 ret = ufshcd_uic_hibern8_enter(hba);
1774                 if (ret) {
1775                         hba->clk_gating.state = CLKS_ON;
1776                         dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
1777                                         __func__, ret);
1778                         trace_ufshcd_clk_gating(dev_name(hba->dev),
1779                                                 hba->clk_gating.state);
1780                         goto out;
1781                 }
1782                 ufshcd_set_link_hibern8(hba);
1783         }
1784
1785         ufshcd_disable_irq(hba);
1786
1787         ufshcd_setup_clocks(hba, false);
1788
1789         /* Put the host controller in low power mode if possible */
1790         ufshcd_hba_vreg_set_lpm(hba);
1791         /*
1792          * In case you are here to cancel this work the gating state
1793          * would be marked as REQ_CLKS_ON. In this case keep the state
1794          * as REQ_CLKS_ON which would anyway imply that clocks are off
1795          * and a request to turn them on is pending. By doing this way,
1796          * we keep the state machine in tact and this would ultimately
1797          * prevent from doing cancel work multiple times when there are
1798          * new requests arriving before the current cancel work is done.
1799          */
1800         spin_lock_irqsave(hba->host->host_lock, flags);
1801         if (hba->clk_gating.state == REQ_CLKS_OFF) {
1802                 hba->clk_gating.state = CLKS_OFF;
1803                 trace_ufshcd_clk_gating(dev_name(hba->dev),
1804                                         hba->clk_gating.state);
1805         }
1806 rel_lock:
1807         spin_unlock_irqrestore(hba->host->host_lock, flags);
1808 out:
1809         return;
1810 }
1811
1812 /* host lock must be held before calling this variant */
1813 static void __ufshcd_release(struct ufs_hba *hba)
1814 {
1815         if (!ufshcd_is_clkgating_allowed(hba))
1816                 return;
1817
1818         hba->clk_gating.active_reqs--;
1819
1820         if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended ||
1821             hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL ||
1822             hba->outstanding_tasks ||
1823             hba->active_uic_cmd || hba->uic_async_done ||
1824             hba->clk_gating.state == CLKS_OFF)
1825                 return;
1826
1827         hba->clk_gating.state = REQ_CLKS_OFF;
1828         trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
1829         queue_delayed_work(hba->clk_gating.clk_gating_workq,
1830                            &hba->clk_gating.gate_work,
1831                            msecs_to_jiffies(hba->clk_gating.delay_ms));
1832 }
1833
1834 void ufshcd_release(struct ufs_hba *hba)
1835 {
1836         unsigned long flags;
1837
1838         spin_lock_irqsave(hba->host->host_lock, flags);
1839         __ufshcd_release(hba);
1840         spin_unlock_irqrestore(hba->host->host_lock, flags);
1841 }
1842 EXPORT_SYMBOL_GPL(ufshcd_release);
1843
1844 static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1845                 struct device_attribute *attr, char *buf)
1846 {
1847         struct ufs_hba *hba = dev_get_drvdata(dev);
1848
1849         return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms);
1850 }
1851
1852 static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1853                 struct device_attribute *attr, const char *buf, size_t count)
1854 {
1855         struct ufs_hba *hba = dev_get_drvdata(dev);
1856         unsigned long flags, value;
1857
1858         if (kstrtoul(buf, 0, &value))
1859                 return -EINVAL;
1860
1861         spin_lock_irqsave(hba->host->host_lock, flags);
1862         hba->clk_gating.delay_ms = value;
1863         spin_unlock_irqrestore(hba->host->host_lock, flags);
1864         return count;
1865 }
1866
1867 static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1868                 struct device_attribute *attr, char *buf)
1869 {
1870         struct ufs_hba *hba = dev_get_drvdata(dev);
1871
1872         return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled);
1873 }
1874
1875 static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1876                 struct device_attribute *attr, const char *buf, size_t count)
1877 {
1878         struct ufs_hba *hba = dev_get_drvdata(dev);
1879         unsigned long flags;
1880         u32 value;
1881
1882         if (kstrtou32(buf, 0, &value))
1883                 return -EINVAL;
1884
1885         value = !!value;
1886
1887         spin_lock_irqsave(hba->host->host_lock, flags);
1888         if (value == hba->clk_gating.is_enabled)
1889                 goto out;
1890
1891         if (value)
1892                 __ufshcd_release(hba);
1893         else
1894                 hba->clk_gating.active_reqs++;
1895
1896         hba->clk_gating.is_enabled = value;
1897 out:
1898         spin_unlock_irqrestore(hba->host->host_lock, flags);
1899         return count;
1900 }
1901
1902 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba)
1903 {
1904         hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1905         hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1906         sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1907         hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
1908         hba->clk_gating.delay_attr.attr.mode = 0644;
1909         if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1910                 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
1911
1912         hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1913         hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1914         sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1915         hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1916         hba->clk_gating.enable_attr.attr.mode = 0644;
1917         if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1918                 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1919 }
1920
1921 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba)
1922 {
1923         if (hba->clk_gating.delay_attr.attr.name)
1924                 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
1925         if (hba->clk_gating.enable_attr.attr.name)
1926                 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
1927 }
1928
1929 static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1930 {
1931         char wq_name[sizeof("ufs_clk_gating_00")];
1932
1933         if (!ufshcd_is_clkgating_allowed(hba))
1934                 return;
1935
1936         hba->clk_gating.state = CLKS_ON;
1937
1938         hba->clk_gating.delay_ms = 150;
1939         INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1940         INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1941
1942         snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
1943                  hba->host->host_no);
1944         hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
1945                                         WQ_MEM_RECLAIM | WQ_HIGHPRI);
1946
1947         ufshcd_init_clk_gating_sysfs(hba);
1948
1949         hba->clk_gating.is_enabled = true;
1950         hba->clk_gating.is_initialized = true;
1951 }
1952
1953 static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1954 {
1955         if (!hba->clk_gating.is_initialized)
1956                 return;
1957         ufshcd_remove_clk_gating_sysfs(hba);
1958         cancel_work_sync(&hba->clk_gating.ungate_work);
1959         cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1960         destroy_workqueue(hba->clk_gating.clk_gating_workq);
1961         hba->clk_gating.is_initialized = false;
1962 }
1963
1964 /* Must be called with host lock acquired */
1965 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1966 {
1967         bool queue_resume_work = false;
1968         ktime_t curr_t = ktime_get();
1969         unsigned long flags;
1970
1971         if (!ufshcd_is_clkscaling_supported(hba))
1972                 return;
1973
1974         spin_lock_irqsave(hba->host->host_lock, flags);
1975         if (!hba->clk_scaling.active_reqs++)
1976                 queue_resume_work = true;
1977
1978         if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) {
1979                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1980                 return;
1981         }
1982
1983         if (queue_resume_work)
1984                 queue_work(hba->clk_scaling.workq,
1985                            &hba->clk_scaling.resume_work);
1986
1987         if (!hba->clk_scaling.window_start_t) {
1988                 hba->clk_scaling.window_start_t = curr_t;
1989                 hba->clk_scaling.tot_busy_t = 0;
1990                 hba->clk_scaling.is_busy_started = false;
1991         }
1992
1993         if (!hba->clk_scaling.is_busy_started) {
1994                 hba->clk_scaling.busy_start_t = curr_t;
1995                 hba->clk_scaling.is_busy_started = true;
1996         }
1997         spin_unlock_irqrestore(hba->host->host_lock, flags);
1998 }
1999
2000 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
2001 {
2002         struct ufs_clk_scaling *scaling = &hba->clk_scaling;
2003         unsigned long flags;
2004
2005         if (!ufshcd_is_clkscaling_supported(hba))
2006                 return;
2007
2008         spin_lock_irqsave(hba->host->host_lock, flags);
2009         hba->clk_scaling.active_reqs--;
2010         if (!hba->outstanding_reqs && scaling->is_busy_started) {
2011                 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
2012                                         scaling->busy_start_t));
2013                 scaling->busy_start_t = 0;
2014                 scaling->is_busy_started = false;
2015         }
2016         spin_unlock_irqrestore(hba->host->host_lock, flags);
2017 }
2018
2019 static inline int ufshcd_monitor_opcode2dir(u8 opcode)
2020 {
2021         if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16)
2022                 return READ;
2023         else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16)
2024                 return WRITE;
2025         else
2026                 return -EINVAL;
2027 }
2028
2029 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba,
2030                                                 struct ufshcd_lrb *lrbp)
2031 {
2032         struct ufs_hba_monitor *m = &hba->monitor;
2033
2034         return (m->enabled && lrbp && lrbp->cmd &&
2035                 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) &&
2036                 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp));
2037 }
2038
2039 static void ufshcd_start_monitor(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2040 {
2041         int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
2042         unsigned long flags;
2043
2044         spin_lock_irqsave(hba->host->host_lock, flags);
2045         if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0)
2046                 hba->monitor.busy_start_ts[dir] = ktime_get();
2047         spin_unlock_irqrestore(hba->host->host_lock, flags);
2048 }
2049
2050 static void ufshcd_update_monitor(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2051 {
2052         int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
2053         unsigned long flags;
2054
2055         spin_lock_irqsave(hba->host->host_lock, flags);
2056         if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) {
2057                 struct request *req = lrbp->cmd->request;
2058                 struct ufs_hba_monitor *m = &hba->monitor;
2059                 ktime_t now, inc, lat;
2060
2061                 now = lrbp->compl_time_stamp;
2062                 inc = ktime_sub(now, m->busy_start_ts[dir]);
2063                 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc);
2064                 m->nr_sec_rw[dir] += blk_rq_sectors(req);
2065
2066                 /* Update latencies */
2067                 m->nr_req[dir]++;
2068                 lat = ktime_sub(now, lrbp->issue_time_stamp);
2069                 m->lat_sum[dir] += lat;
2070                 if (m->lat_max[dir] < lat || !m->lat_max[dir])
2071                         m->lat_max[dir] = lat;
2072                 if (m->lat_min[dir] > lat || !m->lat_min[dir])
2073                         m->lat_min[dir] = lat;
2074
2075                 m->nr_queued[dir]--;
2076                 /* Push forward the busy start of monitor */
2077                 m->busy_start_ts[dir] = now;
2078         }
2079         spin_unlock_irqrestore(hba->host->host_lock, flags);
2080 }
2081
2082 /**
2083  * ufshcd_send_command - Send SCSI or device management commands
2084  * @hba: per adapter instance
2085  * @task_tag: Task tag of the command
2086  */
2087 static inline
2088 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
2089 {
2090         struct ufshcd_lrb *lrbp = &hba->lrb[task_tag];
2091         unsigned long flags;
2092
2093         lrbp->issue_time_stamp = ktime_get();
2094         lrbp->compl_time_stamp = ktime_set(0, 0);
2095         ufshcd_vops_setup_xfer_req(hba, task_tag, (lrbp->cmd ? true : false));
2096         ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND);
2097         ufshcd_clk_scaling_start_busy(hba);
2098         if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
2099                 ufshcd_start_monitor(hba, lrbp);
2100         spin_lock_irqsave(hba->host->host_lock, flags);
2101         set_bit(task_tag, &hba->outstanding_reqs);
2102         ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
2103         spin_unlock_irqrestore(hba->host->host_lock, flags);
2104         /* Make sure that doorbell is committed immediately */
2105         wmb();
2106 }
2107
2108 /**
2109  * ufshcd_copy_sense_data - Copy sense data in case of check condition
2110  * @lrbp: pointer to local reference block
2111  */
2112 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
2113 {
2114         int len;
2115         if (lrbp->sense_buffer &&
2116             ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
2117                 int len_to_copy;
2118
2119                 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
2120                 len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
2121
2122                 memcpy(lrbp->sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
2123                        len_to_copy);
2124         }
2125 }
2126
2127 /**
2128  * ufshcd_copy_query_response() - Copy the Query Response and the data
2129  * descriptor
2130  * @hba: per adapter instance
2131  * @lrbp: pointer to local reference block
2132  */
2133 static
2134 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2135 {
2136         struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2137
2138         memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
2139
2140         /* Get the descriptor */
2141         if (hba->dev_cmd.query.descriptor &&
2142             lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
2143                 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
2144                                 GENERAL_UPIU_REQUEST_SIZE;
2145                 u16 resp_len;
2146                 u16 buf_len;
2147
2148                 /* data segment length */
2149                 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
2150                                                 MASK_QUERY_DATA_SEG_LEN;
2151                 buf_len = be16_to_cpu(
2152                                 hba->dev_cmd.query.request.upiu_req.length);
2153                 if (likely(buf_len >= resp_len)) {
2154                         memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
2155                 } else {
2156                         dev_warn(hba->dev,
2157                                  "%s: rsp size %d is bigger than buffer size %d",
2158                                  __func__, resp_len, buf_len);
2159                         return -EINVAL;
2160                 }
2161         }
2162
2163         return 0;
2164 }
2165
2166 /**
2167  * ufshcd_hba_capabilities - Read controller capabilities
2168  * @hba: per adapter instance
2169  *
2170  * Return: 0 on success, negative on error.
2171  */
2172 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba)
2173 {
2174         int err;
2175
2176         hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
2177
2178         /* nutrs and nutmrs are 0 based values */
2179         hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
2180         hba->nutmrs =
2181         ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
2182
2183         /* Read crypto capabilities */
2184         err = ufshcd_hba_init_crypto_capabilities(hba);
2185         if (err)
2186                 dev_err(hba->dev, "crypto setup failed\n");
2187
2188         return err;
2189 }
2190
2191 /**
2192  * ufshcd_ready_for_uic_cmd - Check if controller is ready
2193  *                            to accept UIC commands
2194  * @hba: per adapter instance
2195  * Return true on success, else false
2196  */
2197 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
2198 {
2199         if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
2200                 return true;
2201         else
2202                 return false;
2203 }
2204
2205 /**
2206  * ufshcd_get_upmcrs - Get the power mode change request status
2207  * @hba: Pointer to adapter instance
2208  *
2209  * This function gets the UPMCRS field of HCS register
2210  * Returns value of UPMCRS field
2211  */
2212 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
2213 {
2214         return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
2215 }
2216
2217 /**
2218  * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer
2219  * @hba: per adapter instance
2220  * @uic_cmd: UIC command
2221  */
2222 static inline void
2223 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2224 {
2225         lockdep_assert_held(&hba->uic_cmd_mutex);
2226
2227         WARN_ON(hba->active_uic_cmd);
2228
2229         hba->active_uic_cmd = uic_cmd;
2230
2231         /* Write Args */
2232         ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2233         ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2234         ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
2235
2236         ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND);
2237
2238         /* Write UIC Cmd */
2239         ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
2240                       REG_UIC_COMMAND);
2241 }
2242
2243 /**
2244  * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command
2245  * @hba: per adapter instance
2246  * @uic_cmd: UIC command
2247  *
2248  * Returns 0 only if success.
2249  */
2250 static int
2251 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2252 {
2253         int ret;
2254         unsigned long flags;
2255
2256         lockdep_assert_held(&hba->uic_cmd_mutex);
2257
2258         if (wait_for_completion_timeout(&uic_cmd->done,
2259                                         msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2260                 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2261         } else {
2262                 ret = -ETIMEDOUT;
2263                 dev_err(hba->dev,
2264                         "uic cmd 0x%x with arg3 0x%x completion timeout\n",
2265                         uic_cmd->command, uic_cmd->argument3);
2266
2267                 if (!uic_cmd->cmd_active) {
2268                         dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n",
2269                                 __func__);
2270                         ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2271                 }
2272         }
2273
2274         spin_lock_irqsave(hba->host->host_lock, flags);
2275         hba->active_uic_cmd = NULL;
2276         spin_unlock_irqrestore(hba->host->host_lock, flags);
2277
2278         return ret;
2279 }
2280
2281 /**
2282  * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2283  * @hba: per adapter instance
2284  * @uic_cmd: UIC command
2285  * @completion: initialize the completion only if this is set to true
2286  *
2287  * Returns 0 only if success.
2288  */
2289 static int
2290 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2291                       bool completion)
2292 {
2293         lockdep_assert_held(&hba->uic_cmd_mutex);
2294         lockdep_assert_held(hba->host->host_lock);
2295
2296         if (!ufshcd_ready_for_uic_cmd(hba)) {
2297                 dev_err(hba->dev,
2298                         "Controller not ready to accept UIC commands\n");
2299                 return -EIO;
2300         }
2301
2302         if (completion)
2303                 init_completion(&uic_cmd->done);
2304
2305         uic_cmd->cmd_active = 1;
2306         ufshcd_dispatch_uic_cmd(hba, uic_cmd);
2307
2308         return 0;
2309 }
2310
2311 /**
2312  * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2313  * @hba: per adapter instance
2314  * @uic_cmd: UIC command
2315  *
2316  * Returns 0 only if success.
2317  */
2318 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2319 {
2320         int ret;
2321         unsigned long flags;
2322
2323         ufshcd_hold(hba, false);
2324         mutex_lock(&hba->uic_cmd_mutex);
2325         ufshcd_add_delay_before_dme_cmd(hba);
2326
2327         spin_lock_irqsave(hba->host->host_lock, flags);
2328         ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
2329         spin_unlock_irqrestore(hba->host->host_lock, flags);
2330         if (!ret)
2331                 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2332
2333         mutex_unlock(&hba->uic_cmd_mutex);
2334
2335         ufshcd_release(hba);
2336         return ret;
2337 }
2338
2339 /**
2340  * ufshcd_map_sg - Map scatter-gather list to prdt
2341  * @hba: per adapter instance
2342  * @lrbp: pointer to local reference block
2343  *
2344  * Returns 0 in case of success, non-zero value in case of failure
2345  */
2346 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2347 {
2348         struct ufshcd_sg_entry *prd_table;
2349         struct scatterlist *sg;
2350         struct scsi_cmnd *cmd;
2351         int sg_segments;
2352         int i;
2353
2354         cmd = lrbp->cmd;
2355         sg_segments = scsi_dma_map(cmd);
2356         if (sg_segments < 0)
2357                 return sg_segments;
2358
2359         if (sg_segments) {
2360
2361                 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2362                         lrbp->utr_descriptor_ptr->prd_table_length =
2363                                 cpu_to_le16((sg_segments *
2364                                         sizeof(struct ufshcd_sg_entry)));
2365                 else
2366                         lrbp->utr_descriptor_ptr->prd_table_length =
2367                                 cpu_to_le16((u16) (sg_segments));
2368
2369                 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
2370
2371                 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2372                         prd_table[i].size  =
2373                                 cpu_to_le32(((u32) sg_dma_len(sg))-1);
2374                         prd_table[i].base_addr =
2375                                 cpu_to_le32(lower_32_bits(sg->dma_address));
2376                         prd_table[i].upper_addr =
2377                                 cpu_to_le32(upper_32_bits(sg->dma_address));
2378                         prd_table[i].reserved = 0;
2379                 }
2380         } else {
2381                 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2382         }
2383
2384         return 0;
2385 }
2386
2387 /**
2388  * ufshcd_enable_intr - enable interrupts
2389  * @hba: per adapter instance
2390  * @intrs: interrupt bits
2391  */
2392 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
2393 {
2394         u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2395
2396         if (hba->ufs_version == ufshci_version(1, 0)) {
2397                 u32 rw;
2398                 rw = set & INTERRUPT_MASK_RW_VER_10;
2399                 set = rw | ((set ^ intrs) & intrs);
2400         } else {
2401                 set |= intrs;
2402         }
2403
2404         ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2405 }
2406
2407 /**
2408  * ufshcd_disable_intr - disable interrupts
2409  * @hba: per adapter instance
2410  * @intrs: interrupt bits
2411  */
2412 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2413 {
2414         u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2415
2416         if (hba->ufs_version == ufshci_version(1, 0)) {
2417                 u32 rw;
2418                 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2419                         ~(intrs & INTERRUPT_MASK_RW_VER_10);
2420                 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2421
2422         } else {
2423                 set &= ~intrs;
2424         }
2425
2426         ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2427 }
2428
2429 /**
2430  * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2431  * descriptor according to request
2432  * @lrbp: pointer to local reference block
2433  * @upiu_flags: flags required in the header
2434  * @cmd_dir: requests data direction
2435  */
2436 static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
2437                         u8 *upiu_flags, enum dma_data_direction cmd_dir)
2438 {
2439         struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2440         u32 data_direction;
2441         u32 dword_0;
2442         u32 dword_1 = 0;
2443         u32 dword_3 = 0;
2444
2445         if (cmd_dir == DMA_FROM_DEVICE) {
2446                 data_direction = UTP_DEVICE_TO_HOST;
2447                 *upiu_flags = UPIU_CMD_FLAGS_READ;
2448         } else if (cmd_dir == DMA_TO_DEVICE) {
2449                 data_direction = UTP_HOST_TO_DEVICE;
2450                 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2451         } else {
2452                 data_direction = UTP_NO_DATA_TRANSFER;
2453                 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2454         }
2455
2456         dword_0 = data_direction | (lrbp->command_type
2457                                 << UPIU_COMMAND_TYPE_OFFSET);
2458         if (lrbp->intr_cmd)
2459                 dword_0 |= UTP_REQ_DESC_INT_CMD;
2460
2461         /* Prepare crypto related dwords */
2462         ufshcd_prepare_req_desc_hdr_crypto(lrbp, &dword_0, &dword_1, &dword_3);
2463
2464         /* Transfer request descriptor header fields */
2465         req_desc->header.dword_0 = cpu_to_le32(dword_0);
2466         req_desc->header.dword_1 = cpu_to_le32(dword_1);
2467         /*
2468          * assigning invalid value for command status. Controller
2469          * updates OCS on command completion, with the command
2470          * status
2471          */
2472         req_desc->header.dword_2 =
2473                 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
2474         req_desc->header.dword_3 = cpu_to_le32(dword_3);
2475
2476         req_desc->prd_table_length = 0;
2477 }
2478
2479 /**
2480  * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2481  * for scsi commands
2482  * @lrbp: local reference block pointer
2483  * @upiu_flags: flags
2484  */
2485 static
2486 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags)
2487 {
2488         struct scsi_cmnd *cmd = lrbp->cmd;
2489         struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2490         unsigned short cdb_len;
2491
2492         /* command descriptor fields */
2493         ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2494                                 UPIU_TRANSACTION_COMMAND, upiu_flags,
2495                                 lrbp->lun, lrbp->task_tag);
2496         ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2497                                 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2498
2499         /* Total EHS length and Data segment length will be zero */
2500         ucd_req_ptr->header.dword_2 = 0;
2501
2502         ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
2503
2504         cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
2505         memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
2506         memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
2507
2508         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2509 }
2510
2511 /**
2512  * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2513  * for query requsts
2514  * @hba: UFS hba
2515  * @lrbp: local reference block pointer
2516  * @upiu_flags: flags
2517  */
2518 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2519                                 struct ufshcd_lrb *lrbp, u8 upiu_flags)
2520 {
2521         struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2522         struct ufs_query *query = &hba->dev_cmd.query;
2523         u16 len = be16_to_cpu(query->request.upiu_req.length);
2524
2525         /* Query request header */
2526         ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2527                         UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2528                         lrbp->lun, lrbp->task_tag);
2529         ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2530                         0, query->request.query_func, 0, 0);
2531
2532         /* Data segment length only need for WRITE_DESC */
2533         if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2534                 ucd_req_ptr->header.dword_2 =
2535                         UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2536         else
2537                 ucd_req_ptr->header.dword_2 = 0;
2538
2539         /* Copy the Query Request buffer as is */
2540         memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2541                         QUERY_OSF_SIZE);
2542
2543         /* Copy the Descriptor */
2544         if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2545                 memcpy(ucd_req_ptr + 1, query->descriptor, len);
2546
2547         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2548 }
2549
2550 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2551 {
2552         struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2553
2554         memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2555
2556         /* command descriptor fields */
2557         ucd_req_ptr->header.dword_0 =
2558                 UPIU_HEADER_DWORD(
2559                         UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
2560         /* clear rest of the fields of basic header */
2561         ucd_req_ptr->header.dword_1 = 0;
2562         ucd_req_ptr->header.dword_2 = 0;
2563
2564         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2565 }
2566
2567 /**
2568  * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU)
2569  *                           for Device Management Purposes
2570  * @hba: per adapter instance
2571  * @lrbp: pointer to local reference block
2572  */
2573 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba,
2574                                       struct ufshcd_lrb *lrbp)
2575 {
2576         u8 upiu_flags;
2577         int ret = 0;
2578
2579         if (hba->ufs_version <= ufshci_version(1, 1))
2580                 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
2581         else
2582                 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2583
2584         ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2585         if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2586                 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2587         else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2588                 ufshcd_prepare_utp_nop_upiu(lrbp);
2589         else
2590                 ret = -EINVAL;
2591
2592         return ret;
2593 }
2594
2595 /**
2596  * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2597  *                         for SCSI Purposes
2598  * @hba: per adapter instance
2599  * @lrbp: pointer to local reference block
2600  */
2601 static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2602 {
2603         u8 upiu_flags;
2604         int ret = 0;
2605
2606         if (hba->ufs_version <= ufshci_version(1, 1))
2607                 lrbp->command_type = UTP_CMD_TYPE_SCSI;
2608         else
2609                 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2610
2611         if (likely(lrbp->cmd)) {
2612                 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2613                                                 lrbp->cmd->sc_data_direction);
2614                 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2615         } else {
2616                 ret = -EINVAL;
2617         }
2618
2619         return ret;
2620 }
2621
2622 /**
2623  * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
2624  * @upiu_wlun_id: UPIU W-LUN id
2625  *
2626  * Returns SCSI W-LUN id
2627  */
2628 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2629 {
2630         return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2631 }
2632
2633 static inline bool is_rpmb_wlun(struct scsi_device *sdev)
2634 {
2635         return sdev->lun == ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN);
2636 }
2637
2638 static inline bool is_device_wlun(struct scsi_device *sdev)
2639 {
2640         return sdev->lun ==
2641                 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN);
2642 }
2643
2644 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i)
2645 {
2646         struct utp_transfer_cmd_desc *cmd_descp = hba->ucdl_base_addr;
2647         struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr;
2648         dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr +
2649                 i * sizeof(struct utp_transfer_cmd_desc);
2650         u16 response_offset = offsetof(struct utp_transfer_cmd_desc,
2651                                        response_upiu);
2652         u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
2653
2654         lrb->utr_descriptor_ptr = utrdlp + i;
2655         lrb->utrd_dma_addr = hba->utrdl_dma_addr +
2656                 i * sizeof(struct utp_transfer_req_desc);
2657         lrb->ucd_req_ptr = (struct utp_upiu_req *)(cmd_descp + i);
2658         lrb->ucd_req_dma_addr = cmd_desc_element_addr;
2659         lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2660         lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset;
2661         lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
2662         lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset;
2663 }
2664
2665 /**
2666  * ufshcd_queuecommand - main entry point for SCSI requests
2667  * @host: SCSI host pointer
2668  * @cmd: command from SCSI Midlayer
2669  *
2670  * Returns 0 for success, non-zero in case of failure
2671  */
2672 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2673 {
2674         struct ufs_hba *hba = shost_priv(host);
2675         int tag = cmd->request->tag;
2676         struct ufshcd_lrb *lrbp;
2677         int err = 0;
2678
2679         WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
2680
2681         if (!down_read_trylock(&hba->clk_scaling_lock))
2682                 return SCSI_MLQUEUE_HOST_BUSY;
2683
2684         switch (hba->ufshcd_state) {
2685         case UFSHCD_STATE_OPERATIONAL:
2686         case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL:
2687                 break;
2688         case UFSHCD_STATE_EH_SCHEDULED_FATAL:
2689                 /*
2690                  * pm_runtime_get_sync() is used at error handling preparation
2691                  * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's
2692                  * PM ops, it can never be finished if we let SCSI layer keep
2693                  * retrying it, which gets err handler stuck forever. Neither
2694                  * can we let the scsi cmd pass through, because UFS is in bad
2695                  * state, the scsi cmd may eventually time out, which will get
2696                  * err handler blocked for too long. So, just fail the scsi cmd
2697                  * sent from PM ops, err handler can recover PM error anyways.
2698                  */
2699                 if (hba->pm_op_in_progress) {
2700                         hba->force_reset = true;
2701                         set_host_byte(cmd, DID_BAD_TARGET);
2702                         cmd->scsi_done(cmd);
2703                         goto out;
2704                 }
2705                 fallthrough;
2706         case UFSHCD_STATE_RESET:
2707                 err = SCSI_MLQUEUE_HOST_BUSY;
2708                 goto out;
2709         case UFSHCD_STATE_ERROR:
2710                 set_host_byte(cmd, DID_ERROR);
2711                 cmd->scsi_done(cmd);
2712                 goto out;
2713         }
2714
2715         hba->req_abort_count = 0;
2716
2717         err = ufshcd_hold(hba, true);
2718         if (err) {
2719                 err = SCSI_MLQUEUE_HOST_BUSY;
2720                 goto out;
2721         }
2722         WARN_ON(ufshcd_is_clkgating_allowed(hba) &&
2723                 (hba->clk_gating.state != CLKS_ON));
2724
2725         if (unlikely(test_bit(tag, &hba->outstanding_reqs))) {
2726                 if (hba->pm_op_in_progress)
2727                         set_host_byte(cmd, DID_BAD_TARGET);
2728                 else
2729                         err = SCSI_MLQUEUE_HOST_BUSY;
2730                 ufshcd_release(hba);
2731                 goto out;
2732         }
2733
2734         lrbp = &hba->lrb[tag];
2735         WARN_ON(lrbp->cmd);
2736         lrbp->cmd = cmd;
2737         lrbp->sense_bufflen = UFS_SENSE_SIZE;
2738         lrbp->sense_buffer = cmd->sense_buffer;
2739         lrbp->task_tag = tag;
2740         lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
2741         lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
2742
2743         ufshcd_prepare_lrbp_crypto(cmd->request, lrbp);
2744
2745         lrbp->req_abort_skip = false;
2746
2747         err = ufshpb_prep(hba, lrbp);
2748         if (err == -EAGAIN) {
2749                 lrbp->cmd = NULL;
2750                 ufshcd_release(hba);
2751                 goto out;
2752         }
2753
2754         ufshcd_comp_scsi_upiu(hba, lrbp);
2755
2756         err = ufshcd_map_sg(hba, lrbp);
2757         if (err) {
2758                 lrbp->cmd = NULL;
2759                 ufshcd_release(hba);
2760                 goto out;
2761         }
2762
2763         ufshcd_send_command(hba, tag);
2764 out:
2765         up_read(&hba->clk_scaling_lock);
2766         return err;
2767 }
2768
2769 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2770                 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2771 {
2772         lrbp->cmd = NULL;
2773         lrbp->sense_bufflen = 0;
2774         lrbp->sense_buffer = NULL;
2775         lrbp->task_tag = tag;
2776         lrbp->lun = 0; /* device management cmd is not specific to any LUN */
2777         lrbp->intr_cmd = true; /* No interrupt aggregation */
2778         ufshcd_prepare_lrbp_crypto(NULL, lrbp);
2779         hba->dev_cmd.type = cmd_type;
2780
2781         return ufshcd_compose_devman_upiu(hba, lrbp);
2782 }
2783
2784 static int
2785 ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2786 {
2787         int err = 0;
2788         unsigned long flags;
2789         u32 mask = 1 << tag;
2790
2791         /* clear outstanding transaction before retry */
2792         spin_lock_irqsave(hba->host->host_lock, flags);
2793         ufshcd_utrl_clear(hba, tag);
2794         spin_unlock_irqrestore(hba->host->host_lock, flags);
2795
2796         /*
2797          * wait for h/w to clear corresponding bit in door-bell.
2798          * max. wait is 1 sec.
2799          */
2800         err = ufshcd_wait_for_register(hba,
2801                         REG_UTP_TRANSFER_REQ_DOOR_BELL,
2802                         mask, ~mask, 1000, 1000);
2803
2804         return err;
2805 }
2806
2807 static int
2808 ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2809 {
2810         struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2811
2812         /* Get the UPIU response */
2813         query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2814                                 UPIU_RSP_CODE_OFFSET;
2815         return query_res->response;
2816 }
2817
2818 /**
2819  * ufshcd_dev_cmd_completion() - handles device management command responses
2820  * @hba: per adapter instance
2821  * @lrbp: pointer to local reference block
2822  */
2823 static int
2824 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2825 {
2826         int resp;
2827         int err = 0;
2828
2829         hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
2830         resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2831
2832         switch (resp) {
2833         case UPIU_TRANSACTION_NOP_IN:
2834                 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2835                         err = -EINVAL;
2836                         dev_err(hba->dev, "%s: unexpected response %x\n",
2837                                         __func__, resp);
2838                 }
2839                 break;
2840         case UPIU_TRANSACTION_QUERY_RSP:
2841                 err = ufshcd_check_query_response(hba, lrbp);
2842                 if (!err)
2843                         err = ufshcd_copy_query_response(hba, lrbp);
2844                 break;
2845         case UPIU_TRANSACTION_REJECT_UPIU:
2846                 /* TODO: handle Reject UPIU Response */
2847                 err = -EPERM;
2848                 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2849                                 __func__);
2850                 break;
2851         default:
2852                 err = -EINVAL;
2853                 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2854                                 __func__, resp);
2855                 break;
2856         }
2857
2858         return err;
2859 }
2860
2861 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2862                 struct ufshcd_lrb *lrbp, int max_timeout)
2863 {
2864         int err = 0;
2865         unsigned long time_left;
2866         unsigned long flags;
2867
2868         time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2869                         msecs_to_jiffies(max_timeout));
2870
2871         spin_lock_irqsave(hba->host->host_lock, flags);
2872         hba->dev_cmd.complete = NULL;
2873         if (likely(time_left)) {
2874                 err = ufshcd_get_tr_ocs(lrbp);
2875                 if (!err)
2876                         err = ufshcd_dev_cmd_completion(hba, lrbp);
2877         }
2878         spin_unlock_irqrestore(hba->host->host_lock, flags);
2879
2880         if (!time_left) {
2881                 err = -ETIMEDOUT;
2882                 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2883                         __func__, lrbp->task_tag);
2884                 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
2885                         /* successfully cleared the command, retry if needed */
2886                         err = -EAGAIN;
2887                 /*
2888                  * in case of an error, after clearing the doorbell,
2889                  * we also need to clear the outstanding_request
2890                  * field in hba
2891                  */
2892                 clear_bit(lrbp->task_tag, &hba->outstanding_reqs);
2893         }
2894
2895         return err;
2896 }
2897
2898 /**
2899  * ufshcd_exec_dev_cmd - API for sending device management requests
2900  * @hba: UFS hba
2901  * @cmd_type: specifies the type (NOP, Query...)
2902  * @timeout: timeout in milliseconds
2903  *
2904  * NOTE: Since there is only one available tag for device management commands,
2905  * it is expected you hold the hba->dev_cmd.lock mutex.
2906  */
2907 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2908                 enum dev_cmd_type cmd_type, int timeout)
2909 {
2910         struct request_queue *q = hba->cmd_queue;
2911         DECLARE_COMPLETION_ONSTACK(wait);
2912         struct request *req;
2913         struct ufshcd_lrb *lrbp;
2914         int err;
2915         int tag;
2916
2917         down_read(&hba->clk_scaling_lock);
2918
2919         /*
2920          * Get free slot, sleep if slots are unavailable.
2921          * Even though we use wait_event() which sleeps indefinitely,
2922          * the maximum wait time is bounded by SCSI request timeout.
2923          */
2924         req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
2925         if (IS_ERR(req)) {
2926                 err = PTR_ERR(req);
2927                 goto out_unlock;
2928         }
2929         tag = req->tag;
2930         WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
2931         /* Set the timeout such that the SCSI error handler is not activated. */
2932         req->timeout = msecs_to_jiffies(2 * timeout);
2933         blk_mq_start_request(req);
2934
2935         if (unlikely(test_bit(tag, &hba->outstanding_reqs))) {
2936                 err = -EBUSY;
2937                 goto out;
2938         }
2939
2940         lrbp = &hba->lrb[tag];
2941         WARN_ON(lrbp->cmd);
2942         err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2943         if (unlikely(err))
2944                 goto out;
2945
2946         hba->dev_cmd.complete = &wait;
2947
2948         ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
2949
2950         ufshcd_send_command(hba, tag);
2951         err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2952         ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
2953                                     (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
2954
2955 out:
2956         blk_put_request(req);
2957 out_unlock:
2958         up_read(&hba->clk_scaling_lock);
2959         return err;
2960 }
2961
2962 /**
2963  * ufshcd_init_query() - init the query response and request parameters
2964  * @hba: per-adapter instance
2965  * @request: address of the request pointer to be initialized
2966  * @response: address of the response pointer to be initialized
2967  * @opcode: operation to perform
2968  * @idn: flag idn to access
2969  * @index: LU number to access
2970  * @selector: query/flag/descriptor further identification
2971  */
2972 static inline void ufshcd_init_query(struct ufs_hba *hba,
2973                 struct ufs_query_req **request, struct ufs_query_res **response,
2974                 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2975 {
2976         *request = &hba->dev_cmd.query.request;
2977         *response = &hba->dev_cmd.query.response;
2978         memset(*request, 0, sizeof(struct ufs_query_req));
2979         memset(*response, 0, sizeof(struct ufs_query_res));
2980         (*request)->upiu_req.opcode = opcode;
2981         (*request)->upiu_req.idn = idn;
2982         (*request)->upiu_req.index = index;
2983         (*request)->upiu_req.selector = selector;
2984 }
2985
2986 static int ufshcd_query_flag_retry(struct ufs_hba *hba,
2987         enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res)
2988 {
2989         int ret;
2990         int retries;
2991
2992         for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
2993                 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res);
2994                 if (ret)
2995                         dev_dbg(hba->dev,
2996                                 "%s: failed with error %d, retries %d\n",
2997                                 __func__, ret, retries);
2998                 else
2999                         break;
3000         }
3001
3002         if (ret)
3003                 dev_err(hba->dev,
3004                         "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
3005                         __func__, opcode, idn, ret, retries);
3006         return ret;
3007 }
3008
3009 /**
3010  * ufshcd_query_flag() - API function for sending flag query requests
3011  * @hba: per-adapter instance
3012  * @opcode: flag query to perform
3013  * @idn: flag idn to access
3014  * @index: flag index to access
3015  * @flag_res: the flag value after the query request completes
3016  *
3017  * Returns 0 for success, non-zero in case of failure
3018  */
3019 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
3020                         enum flag_idn idn, u8 index, bool *flag_res)
3021 {
3022         struct ufs_query_req *request = NULL;
3023         struct ufs_query_res *response = NULL;
3024         int err, selector = 0;
3025         int timeout = QUERY_REQ_TIMEOUT;
3026
3027         BUG_ON(!hba);
3028
3029         ufshcd_hold(hba, false);
3030         mutex_lock(&hba->dev_cmd.lock);
3031         ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3032                         selector);
3033
3034         switch (opcode) {
3035         case UPIU_QUERY_OPCODE_SET_FLAG:
3036         case UPIU_QUERY_OPCODE_CLEAR_FLAG:
3037         case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
3038                 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3039                 break;
3040         case UPIU_QUERY_OPCODE_READ_FLAG:
3041                 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3042                 if (!flag_res) {
3043                         /* No dummy reads */
3044                         dev_err(hba->dev, "%s: Invalid argument for read request\n",
3045                                         __func__);
3046                         err = -EINVAL;
3047                         goto out_unlock;
3048                 }
3049                 break;
3050         default:
3051                 dev_err(hba->dev,
3052                         "%s: Expected query flag opcode but got = %d\n",
3053                         __func__, opcode);
3054                 err = -EINVAL;
3055                 goto out_unlock;
3056         }
3057
3058         err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
3059
3060         if (err) {
3061                 dev_err(hba->dev,
3062                         "%s: Sending flag query for idn %d failed, err = %d\n",
3063                         __func__, idn, err);
3064                 goto out_unlock;
3065         }
3066
3067         if (flag_res)
3068                 *flag_res = (be32_to_cpu(response->upiu_res.value) &
3069                                 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
3070
3071 out_unlock:
3072         mutex_unlock(&hba->dev_cmd.lock);
3073         ufshcd_release(hba);
3074         return err;
3075 }
3076
3077 /**
3078  * ufshcd_query_attr - API function for sending attribute requests
3079  * @hba: per-adapter instance
3080  * @opcode: attribute opcode
3081  * @idn: attribute idn to access
3082  * @index: index field
3083  * @selector: selector field
3084  * @attr_val: the attribute value after the query request completes
3085  *
3086  * Returns 0 for success, non-zero in case of failure
3087 */
3088 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
3089                       enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
3090 {
3091         struct ufs_query_req *request = NULL;
3092         struct ufs_query_res *response = NULL;
3093         int err;
3094
3095         BUG_ON(!hba);
3096
3097         if (!attr_val) {
3098                 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
3099                                 __func__, opcode);
3100                 return -EINVAL;
3101         }
3102
3103         ufshcd_hold(hba, false);
3104
3105         mutex_lock(&hba->dev_cmd.lock);
3106         ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3107                         selector);
3108
3109         switch (opcode) {
3110         case UPIU_QUERY_OPCODE_WRITE_ATTR:
3111                 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3112                 request->upiu_req.value = cpu_to_be32(*attr_val);
3113                 break;
3114         case UPIU_QUERY_OPCODE_READ_ATTR:
3115                 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3116                 break;
3117         default:
3118                 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
3119                                 __func__, opcode);
3120                 err = -EINVAL;
3121                 goto out_unlock;
3122         }
3123
3124         err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3125
3126         if (err) {
3127                 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3128                                 __func__, opcode, idn, index, err);
3129                 goto out_unlock;
3130         }
3131
3132         *attr_val = be32_to_cpu(response->upiu_res.value);
3133
3134 out_unlock:
3135         mutex_unlock(&hba->dev_cmd.lock);
3136         ufshcd_release(hba);
3137         return err;
3138 }
3139
3140 /**
3141  * ufshcd_query_attr_retry() - API function for sending query
3142  * attribute with retries
3143  * @hba: per-adapter instance
3144  * @opcode: attribute opcode
3145  * @idn: attribute idn to access
3146  * @index: index field
3147  * @selector: selector field
3148  * @attr_val: the attribute value after the query request
3149  * completes
3150  *
3151  * Returns 0 for success, non-zero in case of failure
3152 */
3153 int ufshcd_query_attr_retry(struct ufs_hba *hba,
3154         enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
3155         u32 *attr_val)
3156 {
3157         int ret = 0;
3158         u32 retries;
3159
3160         for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3161                 ret = ufshcd_query_attr(hba, opcode, idn, index,
3162                                                 selector, attr_val);
3163                 if (ret)
3164                         dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
3165                                 __func__, ret, retries);
3166                 else
3167                         break;
3168         }
3169
3170         if (ret)
3171                 dev_err(hba->dev,
3172                         "%s: query attribute, idn %d, failed with error %d after %d retires\n",
3173                         __func__, idn, ret, QUERY_REQ_RETRIES);
3174         return ret;
3175 }
3176
3177 static int __ufshcd_query_descriptor(struct ufs_hba *hba,
3178                         enum query_opcode opcode, enum desc_idn idn, u8 index,
3179                         u8 selector, u8 *desc_buf, int *buf_len)
3180 {
3181         struct ufs_query_req *request = NULL;
3182         struct ufs_query_res *response = NULL;
3183         int err;
3184
3185         BUG_ON(!hba);
3186
3187         if (!desc_buf) {
3188                 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
3189                                 __func__, opcode);
3190                 return -EINVAL;
3191         }
3192
3193         if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
3194                 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
3195                                 __func__, *buf_len);
3196                 return -EINVAL;
3197         }
3198
3199         ufshcd_hold(hba, false);
3200
3201         mutex_lock(&hba->dev_cmd.lock);
3202         ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3203                         selector);
3204         hba->dev_cmd.query.descriptor = desc_buf;
3205         request->upiu_req.length = cpu_to_be16(*buf_len);
3206
3207         switch (opcode) {
3208         case UPIU_QUERY_OPCODE_WRITE_DESC:
3209                 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3210                 break;
3211         case UPIU_QUERY_OPCODE_READ_DESC:
3212                 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3213                 break;
3214         default:
3215                 dev_err(hba->dev,
3216                                 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
3217                                 __func__, opcode);
3218                 err = -EINVAL;
3219                 goto out_unlock;
3220         }
3221
3222         err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3223
3224         if (err) {
3225                 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3226                                 __func__, opcode, idn, index, err);
3227                 goto out_unlock;
3228         }
3229
3230         *buf_len = be16_to_cpu(response->upiu_res.length);
3231
3232 out_unlock:
3233         hba->dev_cmd.query.descriptor = NULL;
3234         mutex_unlock(&hba->dev_cmd.lock);
3235         ufshcd_release(hba);
3236         return err;
3237 }
3238
3239 /**
3240  * ufshcd_query_descriptor_retry - API function for sending descriptor requests
3241  * @hba: per-adapter instance
3242  * @opcode: attribute opcode
3243  * @idn: attribute idn to access
3244  * @index: index field
3245  * @selector: selector field
3246  * @desc_buf: the buffer that contains the descriptor
3247  * @buf_len: length parameter passed to the device
3248  *
3249  * Returns 0 for success, non-zero in case of failure.
3250  * The buf_len parameter will contain, on return, the length parameter
3251  * received on the response.
3252  */
3253 int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3254                                   enum query_opcode opcode,
3255                                   enum desc_idn idn, u8 index,
3256                                   u8 selector,
3257                                   u8 *desc_buf, int *buf_len)
3258 {
3259         int err;
3260         int retries;
3261
3262         for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3263                 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3264                                                 selector, desc_buf, buf_len);
3265                 if (!err || err == -EINVAL)
3266                         break;
3267         }
3268
3269         return err;
3270 }
3271
3272 /**
3273  * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
3274  * @hba: Pointer to adapter instance
3275  * @desc_id: descriptor idn value
3276  * @desc_len: mapped desc length (out)
3277  */
3278 void ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
3279                                   int *desc_len)
3280 {
3281         if (desc_id >= QUERY_DESC_IDN_MAX || desc_id == QUERY_DESC_IDN_RFU_0 ||
3282             desc_id == QUERY_DESC_IDN_RFU_1)
3283                 *desc_len = 0;
3284         else
3285                 *desc_len = hba->desc_size[desc_id];
3286 }
3287 EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
3288
3289 static void ufshcd_update_desc_length(struct ufs_hba *hba,
3290                                       enum desc_idn desc_id, int desc_index,
3291                                       unsigned char desc_len)
3292 {
3293         if (hba->desc_size[desc_id] == QUERY_DESC_MAX_SIZE &&
3294             desc_id != QUERY_DESC_IDN_STRING && desc_index != UFS_RPMB_UNIT)
3295                 /* For UFS 3.1, the normal unit descriptor is 10 bytes larger
3296                  * than the RPMB unit, however, both descriptors share the same
3297                  * desc_idn, to cover both unit descriptors with one length, we
3298                  * choose the normal unit descriptor length by desc_index.
3299                  */
3300                 hba->desc_size[desc_id] = desc_len;
3301 }
3302
3303 /**
3304  * ufshcd_read_desc_param - read the specified descriptor parameter
3305  * @hba: Pointer to adapter instance
3306  * @desc_id: descriptor idn value
3307  * @desc_index: descriptor index
3308  * @param_offset: offset of the parameter to read
3309  * @param_read_buf: pointer to buffer where parameter would be read
3310  * @param_size: sizeof(param_read_buf)
3311  *
3312  * Return 0 in case of success, non-zero otherwise
3313  */
3314 int ufshcd_read_desc_param(struct ufs_hba *hba,
3315                            enum desc_idn desc_id,
3316                            int desc_index,
3317                            u8 param_offset,
3318                            u8 *param_read_buf,
3319                            u8 param_size)
3320 {
3321         int ret;
3322         u8 *desc_buf;
3323         int buff_len;
3324         bool is_kmalloc = true;
3325
3326         /* Safety check */
3327         if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
3328                 return -EINVAL;
3329
3330         /* Get the length of descriptor */
3331         ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
3332         if (!buff_len) {
3333                 dev_err(hba->dev, "%s: Failed to get desc length\n", __func__);
3334                 return -EINVAL;
3335         }
3336
3337         if (param_offset >= buff_len) {
3338                 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n",
3339                         __func__, param_offset, desc_id, buff_len);
3340                 return -EINVAL;
3341         }
3342
3343         /* Check whether we need temp memory */
3344         if (param_offset != 0 || param_size < buff_len) {
3345                 desc_buf = kzalloc(buff_len, GFP_KERNEL);
3346                 if (!desc_buf)
3347                         return -ENOMEM;
3348         } else {
3349                 desc_buf = param_read_buf;
3350                 is_kmalloc = false;
3351         }
3352
3353         /* Request for full descriptor */
3354         ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3355                                         desc_id, desc_index, 0,
3356                                         desc_buf, &buff_len);
3357
3358         if (ret) {
3359                 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n",
3360                         __func__, desc_id, desc_index, param_offset, ret);
3361                 goto out;
3362         }
3363
3364         /* Sanity check */
3365         if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3366                 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n",
3367                         __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3368                 ret = -EINVAL;
3369                 goto out;
3370         }
3371
3372         /* Update descriptor length */
3373         buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET];
3374         ufshcd_update_desc_length(hba, desc_id, desc_index, buff_len);
3375
3376         if (is_kmalloc) {
3377                 /* Make sure we don't copy more data than available */
3378                 if (param_offset >= buff_len)
3379                         ret = -EINVAL;
3380                 else
3381                         memcpy(param_read_buf, &desc_buf[param_offset],
3382                                min_t(u32, param_size, buff_len - param_offset));
3383         }
3384 out:
3385         if (is_kmalloc)
3386                 kfree(desc_buf);
3387         return ret;
3388 }
3389
3390 /**
3391  * struct uc_string_id - unicode string
3392  *
3393  * @len: size of this descriptor inclusive
3394  * @type: descriptor type
3395  * @uc: unicode string character
3396  */
3397 struct uc_string_id {
3398         u8 len;
3399         u8 type;
3400         wchar_t uc[];
3401 } __packed;
3402
3403 /* replace non-printable or non-ASCII characters with spaces */
3404 static inline char ufshcd_remove_non_printable(u8 ch)
3405 {
3406         return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3407 }
3408
3409 /**
3410  * ufshcd_read_string_desc - read string descriptor
3411  * @hba: pointer to adapter instance
3412  * @desc_index: descriptor index
3413  * @buf: pointer to buffer where descriptor would be read,
3414  *       the caller should free the memory.
3415  * @ascii: if true convert from unicode to ascii characters
3416  *         null terminated string.
3417  *
3418  * Return:
3419  * *      string size on success.
3420  * *      -ENOMEM: on allocation failure
3421  * *      -EINVAL: on a wrong parameter
3422  */
3423 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
3424                             u8 **buf, bool ascii)
3425 {
3426         struct uc_string_id *uc_str;
3427         u8 *str;
3428         int ret;
3429
3430         if (!buf)
3431                 return -EINVAL;
3432
3433         uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3434         if (!uc_str)
3435                 return -ENOMEM;
3436
3437         ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0,
3438                                      (u8 *)uc_str, QUERY_DESC_MAX_SIZE);
3439         if (ret < 0) {
3440                 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3441                         QUERY_REQ_RETRIES, ret);
3442                 str = NULL;
3443                 goto out;
3444         }
3445
3446         if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3447                 dev_dbg(hba->dev, "String Desc is of zero length\n");
3448                 str = NULL;
3449                 ret = 0;
3450                 goto out;
3451         }
3452
3453         if (ascii) {
3454                 ssize_t ascii_len;
3455                 int i;
3456                 /* remove header and divide by 2 to move from UTF16 to UTF8 */
3457                 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3458                 str = kzalloc(ascii_len, GFP_KERNEL);
3459                 if (!str) {
3460                         ret = -ENOMEM;
3461                         goto out;
3462                 }
3463
3464                 /*
3465                  * the descriptor contains string in UTF16 format
3466                  * we need to convert to utf-8 so it can be displayed
3467                  */
3468                 ret = utf16s_to_utf8s(uc_str->uc,
3469                                       uc_str->len - QUERY_DESC_HDR_SIZE,
3470                                       UTF16_BIG_ENDIAN, str, ascii_len);
3471
3472                 /* replace non-printable or non-ASCII characters with spaces */
3473                 for (i = 0; i < ret; i++)
3474                         str[i] = ufshcd_remove_non_printable(str[i]);
3475
3476                 str[ret++] = '\0';
3477
3478         } else {
3479                 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
3480                 if (!str) {
3481                         ret = -ENOMEM;
3482                         goto out;
3483                 }
3484                 ret = uc_str->len;
3485         }
3486 out:
3487         *buf = str;
3488         kfree(uc_str);
3489         return ret;
3490 }
3491
3492 /**
3493  * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3494  * @hba: Pointer to adapter instance
3495  * @lun: lun id
3496  * @param_offset: offset of the parameter to read
3497  * @param_read_buf: pointer to buffer where parameter would be read
3498  * @param_size: sizeof(param_read_buf)
3499  *
3500  * Return 0 in case of success, non-zero otherwise
3501  */
3502 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3503                                               int lun,
3504                                               enum unit_desc_param param_offset,
3505                                               u8 *param_read_buf,
3506                                               u32 param_size)
3507 {
3508         /*
3509          * Unit descriptors are only available for general purpose LUs (LUN id
3510          * from 0 to 7) and RPMB Well known LU.
3511          */
3512         if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun, param_offset))
3513                 return -EOPNOTSUPP;
3514
3515         return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3516                                       param_offset, param_read_buf, param_size);
3517 }
3518
3519 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
3520 {
3521         int err = 0;
3522         u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3523
3524         if (hba->dev_info.wspecversion >= 0x300) {
3525                 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3526                                 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0,
3527                                 &gating_wait);
3528                 if (err)
3529                         dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
3530                                          err, gating_wait);
3531
3532                 if (gating_wait == 0) {
3533                         gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3534                         dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
3535                                          gating_wait);
3536                 }
3537
3538                 hba->dev_info.clk_gating_wait_us = gating_wait;
3539         }
3540
3541         return err;
3542 }
3543
3544 /**
3545  * ufshcd_memory_alloc - allocate memory for host memory space data structures
3546  * @hba: per adapter instance
3547  *
3548  * 1. Allocate DMA memory for Command Descriptor array
3549  *      Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3550  * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3551  * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3552  *      (UTMRDL)
3553  * 4. Allocate memory for local reference block(lrb).
3554  *
3555  * Returns 0 for success, non-zero in case of failure
3556  */
3557 static int ufshcd_memory_alloc(struct ufs_hba *hba)
3558 {
3559         size_t utmrdl_size, utrdl_size, ucdl_size;
3560
3561         /* Allocate memory for UTP command descriptors */
3562         ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
3563         hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3564                                                   ucdl_size,
3565                                                   &hba->ucdl_dma_addr,
3566                                                   GFP_KERNEL);
3567
3568         /*
3569          * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3570          * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3571          * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3572          * be aligned to 128 bytes as well
3573          */
3574         if (!hba->ucdl_base_addr ||
3575             WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3576                 dev_err(hba->dev,
3577                         "Command Descriptor Memory allocation failed\n");
3578                 goto out;
3579         }
3580
3581         /*
3582          * Allocate memory for UTP Transfer descriptors
3583          * UFSHCI requires 1024 byte alignment of UTRD
3584          */
3585         utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
3586         hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3587                                                    utrdl_size,
3588                                                    &hba->utrdl_dma_addr,
3589                                                    GFP_KERNEL);
3590         if (!hba->utrdl_base_addr ||
3591             WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3592                 dev_err(hba->dev,
3593                         "Transfer Descriptor Memory allocation failed\n");
3594                 goto out;
3595         }
3596
3597         /*
3598          * Allocate memory for UTP Task Management descriptors
3599          * UFSHCI requires 1024 byte alignment of UTMRD
3600          */
3601         utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
3602         hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3603                                                     utmrdl_size,
3604                                                     &hba->utmrdl_dma_addr,
3605                                                     GFP_KERNEL);
3606         if (!hba->utmrdl_base_addr ||
3607             WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3608                 dev_err(hba->dev,
3609                 "Task Management Descriptor Memory allocation failed\n");
3610                 goto out;
3611         }
3612
3613         /* Allocate memory for local reference block */
3614         hba->lrb = devm_kcalloc(hba->dev,
3615                                 hba->nutrs, sizeof(struct ufshcd_lrb),
3616                                 GFP_KERNEL);
3617         if (!hba->lrb) {
3618                 dev_err(hba->dev, "LRB Memory allocation failed\n");
3619                 goto out;
3620         }
3621         return 0;
3622 out:
3623         return -ENOMEM;
3624 }
3625
3626 /**
3627  * ufshcd_host_memory_configure - configure local reference block with
3628  *                              memory offsets
3629  * @hba: per adapter instance
3630  *
3631  * Configure Host memory space
3632  * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3633  * address.
3634  * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3635  * and PRDT offset.
3636  * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3637  * into local reference block.
3638  */
3639 static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3640 {
3641         struct utp_transfer_req_desc *utrdlp;
3642         dma_addr_t cmd_desc_dma_addr;
3643         dma_addr_t cmd_desc_element_addr;
3644         u16 response_offset;
3645         u16 prdt_offset;
3646         int cmd_desc_size;
3647         int i;
3648
3649         utrdlp = hba->utrdl_base_addr;
3650
3651         response_offset =
3652                 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3653         prdt_offset =
3654                 offsetof(struct utp_transfer_cmd_desc, prd_table);
3655
3656         cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3657         cmd_desc_dma_addr = hba->ucdl_dma_addr;
3658
3659         for (i = 0; i < hba->nutrs; i++) {
3660                 /* Configure UTRD with command descriptor base address */
3661                 cmd_desc_element_addr =
3662                                 (cmd_desc_dma_addr + (cmd_desc_size * i));
3663                 utrdlp[i].command_desc_base_addr_lo =
3664                                 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3665                 utrdlp[i].command_desc_base_addr_hi =
3666                                 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3667
3668                 /* Response upiu and prdt offset should be in double words */
3669                 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3670                         utrdlp[i].response_upiu_offset =
3671                                 cpu_to_le16(response_offset);
3672                         utrdlp[i].prd_table_offset =
3673                                 cpu_to_le16(prdt_offset);
3674                         utrdlp[i].response_upiu_length =
3675                                 cpu_to_le16(ALIGNED_UPIU_SIZE);
3676                 } else {
3677                         utrdlp[i].response_upiu_offset =
3678                                 cpu_to_le16(response_offset >> 2);
3679                         utrdlp[i].prd_table_offset =
3680                                 cpu_to_le16(prdt_offset >> 2);
3681                         utrdlp[i].response_upiu_length =
3682                                 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
3683                 }
3684
3685                 ufshcd_init_lrb(hba, &hba->lrb[i], i);
3686         }
3687 }
3688
3689 /**
3690  * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3691  * @hba: per adapter instance
3692  *
3693  * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3694  * in order to initialize the Unipro link startup procedure.
3695  * Once the Unipro links are up, the device connected to the controller
3696  * is detected.
3697  *
3698  * Returns 0 on success, non-zero value on failure
3699  */
3700 static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3701 {
3702         struct uic_command uic_cmd = {0};
3703         int ret;
3704
3705         uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
3706
3707         ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3708         if (ret)
3709                 dev_dbg(hba->dev,
3710                         "dme-link-startup: error code %d\n", ret);
3711         return ret;
3712 }
3713 /**
3714  * ufshcd_dme_reset - UIC command for DME_RESET
3715  * @hba: per adapter instance
3716  *
3717  * DME_RESET command is issued in order to reset UniPro stack.
3718  * This function now deals with cold reset.
3719  *
3720  * Returns 0 on success, non-zero value on failure
3721  */
3722 static int ufshcd_dme_reset(struct ufs_hba *hba)
3723 {
3724         struct uic_command uic_cmd = {0};
3725         int ret;
3726
3727         uic_cmd.command = UIC_CMD_DME_RESET;
3728
3729         ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3730         if (ret)
3731                 dev_err(hba->dev,
3732                         "dme-reset: error code %d\n", ret);
3733
3734         return ret;
3735 }
3736
3737 int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
3738                                int agreed_gear,
3739                                int adapt_val)
3740 {
3741         int ret;
3742
3743         if (agreed_gear != UFS_HS_G4)
3744                 adapt_val = PA_NO_ADAPT;
3745
3746         ret = ufshcd_dme_set(hba,
3747                              UIC_ARG_MIB(PA_TXHSADAPTTYPE),
3748                              adapt_val);
3749         return ret;
3750 }
3751 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt);
3752
3753 /**
3754  * ufshcd_dme_enable - UIC command for DME_ENABLE
3755  * @hba: per adapter instance
3756  *
3757  * DME_ENABLE command is issued in order to enable UniPro stack.
3758  *
3759  * Returns 0 on success, non-zero value on failure
3760  */
3761 static int ufshcd_dme_enable(struct ufs_hba *hba)
3762 {
3763         struct uic_command uic_cmd = {0};
3764         int ret;
3765
3766         uic_cmd.command = UIC_CMD_DME_ENABLE;
3767
3768         ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3769         if (ret)
3770                 dev_err(hba->dev,
3771                         "dme-enable: error code %d\n", ret);
3772
3773         return ret;
3774 }
3775
3776 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3777 {
3778         #define MIN_DELAY_BEFORE_DME_CMDS_US    1000
3779         unsigned long min_sleep_time_us;
3780
3781         if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3782                 return;
3783
3784         /*
3785          * last_dme_cmd_tstamp will be 0 only for 1st call to
3786          * this function
3787          */
3788         if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3789                 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3790         } else {
3791                 unsigned long delta =
3792                         (unsigned long) ktime_to_us(
3793                                 ktime_sub(ktime_get(),
3794                                 hba->last_dme_cmd_tstamp));
3795
3796                 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3797                         min_sleep_time_us =
3798                                 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3799                 else
3800                         return; /* no more delay required */
3801         }
3802
3803         /* allow sleep for extra 50us if needed */
3804         usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3805 }
3806
3807 /**
3808  * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3809  * @hba: per adapter instance
3810  * @attr_sel: uic command argument1
3811  * @attr_set: attribute set type as uic command argument2
3812  * @mib_val: setting value as uic command argument3
3813  * @peer: indicate whether peer or local
3814  *
3815  * Returns 0 on success, non-zero value on failure
3816  */
3817 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3818                         u8 attr_set, u32 mib_val, u8 peer)
3819 {
3820         struct uic_command uic_cmd = {0};
3821         static const char *const action[] = {
3822                 "dme-set",
3823                 "dme-peer-set"
3824         };
3825         const char *set = action[!!peer];
3826         int ret;
3827         int retries = UFS_UIC_COMMAND_RETRIES;
3828
3829         uic_cmd.command = peer ?
3830                 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3831         uic_cmd.argument1 = attr_sel;
3832         uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3833         uic_cmd.argument3 = mib_val;
3834
3835         do {
3836                 /* for peer attributes we retry upon failure */
3837                 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3838                 if (ret)
3839                         dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3840                                 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3841         } while (ret && peer && --retries);
3842
3843         if (ret)
3844                 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
3845                         set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3846                         UFS_UIC_COMMAND_RETRIES - retries);
3847
3848         return ret;
3849 }
3850 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3851
3852 /**
3853  * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3854  * @hba: per adapter instance
3855  * @attr_sel: uic command argument1
3856  * @mib_val: the value of the attribute as returned by the UIC command
3857  * @peer: indicate whether peer or local
3858  *
3859  * Returns 0 on success, non-zero value on failure
3860  */
3861 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3862                         u32 *mib_val, u8 peer)
3863 {
3864         struct uic_command uic_cmd = {0};
3865         static const char *const action[] = {
3866                 "dme-get",
3867                 "dme-peer-get"
3868         };
3869         const char *get = action[!!peer];
3870         int ret;
3871         int retries = UFS_UIC_COMMAND_RETRIES;
3872         struct ufs_pa_layer_attr orig_pwr_info;
3873         struct ufs_pa_layer_attr temp_pwr_info;
3874         bool pwr_mode_change = false;
3875
3876         if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3877                 orig_pwr_info = hba->pwr_info;
3878                 temp_pwr_info = orig_pwr_info;
3879
3880                 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3881                     orig_pwr_info.pwr_rx == FAST_MODE) {
3882                         temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3883                         temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3884                         pwr_mode_change = true;
3885                 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3886                     orig_pwr_info.pwr_rx == SLOW_MODE) {
3887                         temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3888                         temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3889                         pwr_mode_change = true;
3890                 }
3891                 if (pwr_mode_change) {
3892                         ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3893                         if (ret)
3894                                 goto out;
3895                 }
3896         }
3897
3898         uic_cmd.command = peer ?
3899                 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3900         uic_cmd.argument1 = attr_sel;
3901
3902         do {
3903                 /* for peer attributes we retry upon failure */
3904                 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3905                 if (ret)
3906                         dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3907                                 get, UIC_GET_ATTR_ID(attr_sel), ret);
3908         } while (ret && peer && --retries);
3909
3910         if (ret)
3911                 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
3912                         get, UIC_GET_ATTR_ID(attr_sel),
3913                         UFS_UIC_COMMAND_RETRIES - retries);
3914
3915         if (mib_val && !ret)
3916                 *mib_val = uic_cmd.argument3;
3917
3918         if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3919             && pwr_mode_change)
3920                 ufshcd_change_power_mode(hba, &orig_pwr_info);
3921 out:
3922         return ret;
3923 }
3924 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3925
3926 /**
3927  * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3928  * state) and waits for it to take effect.
3929  *
3930  * @hba: per adapter instance
3931  * @cmd: UIC command to execute
3932  *
3933  * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3934  * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3935  * and device UniPro link and hence it's final completion would be indicated by
3936  * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3937  * addition to normal UIC command completion Status (UCCS). This function only
3938  * returns after the relevant status bits indicate the completion.
3939  *
3940  * Returns 0 on success, non-zero value on failure
3941  */
3942 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
3943 {
3944         DECLARE_COMPLETION_ONSTACK(uic_async_done);
3945         unsigned long flags;
3946         u8 status;
3947         int ret;
3948         bool reenable_intr = false;
3949
3950         mutex_lock(&hba->uic_cmd_mutex);
3951         ufshcd_add_delay_before_dme_cmd(hba);
3952
3953         spin_lock_irqsave(hba->host->host_lock, flags);
3954         if (ufshcd_is_link_broken(hba)) {
3955                 ret = -ENOLINK;
3956                 goto out_unlock;
3957         }
3958         hba->uic_async_done = &uic_async_done;
3959         if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3960                 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3961                 /*
3962                  * Make sure UIC command completion interrupt is disabled before
3963                  * issuing UIC command.
3964                  */
3965                 wmb();
3966                 reenable_intr = true;
3967         }
3968         ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3969         spin_unlock_irqrestore(hba->host->host_lock, flags);
3970         if (ret) {
3971                 dev_err(hba->dev,
3972                         "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3973                         cmd->command, cmd->argument3, ret);
3974                 goto out;
3975         }
3976
3977         if (!wait_for_completion_timeout(hba->uic_async_done,
3978                                          msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
3979                 dev_err(hba->dev,
3980                         "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
3981                         cmd->command, cmd->argument3);
3982
3983                 if (!cmd->cmd_active) {
3984                         dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n",
3985                                 __func__);
3986                         goto check_upmcrs;
3987                 }
3988
3989                 ret = -ETIMEDOUT;
3990                 goto out;
3991         }
3992
3993 check_upmcrs:
3994         status = ufshcd_get_upmcrs(hba);
3995         if (status != PWR_LOCAL) {
3996                 dev_err(hba->dev,
3997                         "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
3998                         cmd->command, status);
3999                 ret = (status != PWR_OK) ? status : -1;
4000         }
4001 out:
4002         if (ret) {
4003                 ufshcd_print_host_state(hba);
4004                 ufshcd_print_pwr_info(hba);
4005                 ufshcd_print_evt_hist(hba);
4006         }
4007
4008         spin_lock_irqsave(hba->host->host_lock, flags);
4009         hba->active_uic_cmd = NULL;
4010         hba->uic_async_done = NULL;
4011         if (reenable_intr)
4012                 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
4013         if (ret) {
4014                 ufshcd_set_link_broken(hba);
4015                 ufshcd_schedule_eh_work(hba);
4016         }
4017 out_unlock:
4018         spin_unlock_irqrestore(hba->host->host_lock, flags);
4019         mutex_unlock(&hba->uic_cmd_mutex);
4020
4021         return ret;
4022 }
4023
4024 /**
4025  * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
4026  *                              using DME_SET primitives.
4027  * @hba: per adapter instance
4028  * @mode: powr mode value
4029  *
4030  * Returns 0 on success, non-zero value on failure
4031  */
4032 static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
4033 {
4034         struct uic_command uic_cmd = {0};
4035         int ret;
4036
4037         if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
4038                 ret = ufshcd_dme_set(hba,
4039                                 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
4040                 if (ret) {
4041                         dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
4042                                                 __func__, ret);
4043                         goto out;
4044                 }
4045         }
4046
4047         uic_cmd.command = UIC_CMD_DME_SET;
4048         uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
4049         uic_cmd.argument3 = mode;
4050         ufshcd_hold(hba, false);
4051         ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4052         ufshcd_release(hba);
4053
4054 out:
4055         return ret;
4056 }
4057
4058 int ufshcd_link_recovery(struct ufs_hba *hba)
4059 {
4060         int ret;
4061         unsigned long flags;
4062
4063         spin_lock_irqsave(hba->host->host_lock, flags);
4064         hba->ufshcd_state = UFSHCD_STATE_RESET;
4065         ufshcd_set_eh_in_progress(hba);
4066         spin_unlock_irqrestore(hba->host->host_lock, flags);
4067
4068         /* Reset the attached device */
4069         ufshcd_device_reset(hba);
4070
4071         ret = ufshcd_host_reset_and_restore(hba);
4072
4073         spin_lock_irqsave(hba->host->host_lock, flags);
4074         if (ret)
4075                 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4076         ufshcd_clear_eh_in_progress(hba);
4077         spin_unlock_irqrestore(hba->host->host_lock, flags);
4078
4079         if (ret)
4080                 dev_err(hba->dev, "%s: link recovery failed, err %d",
4081                         __func__, ret);
4082         else
4083                 ufshcd_clear_ua_wluns(hba);
4084
4085         return ret;
4086 }
4087 EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
4088
4089 static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
4090 {
4091         int ret;
4092         struct uic_command uic_cmd = {0};
4093         ktime_t start = ktime_get();
4094
4095         ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
4096
4097         uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
4098         ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4099         trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
4100                              ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4101
4102         if (ret)
4103                 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
4104                         __func__, ret);
4105         else
4106                 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
4107                                                                 POST_CHANGE);
4108
4109         return ret;
4110 }
4111
4112 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
4113 {
4114         struct uic_command uic_cmd = {0};
4115         int ret;
4116         ktime_t start = ktime_get();
4117
4118         ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
4119
4120         uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
4121         ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4122         trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
4123                              ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4124
4125         if (ret) {
4126                 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
4127                         __func__, ret);
4128         } else {
4129                 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
4130                                                                 POST_CHANGE);
4131                 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
4132                 hba->ufs_stats.hibern8_exit_cnt++;
4133         }
4134
4135         return ret;
4136 }
4137 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit);
4138
4139 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
4140 {
4141         unsigned long flags;
4142         bool update = false;
4143
4144         if (!ufshcd_is_auto_hibern8_supported(hba))
4145                 return;
4146
4147         spin_lock_irqsave(hba->host->host_lock, flags);
4148         if (hba->ahit != ahit) {
4149                 hba->ahit = ahit;
4150                 update = true;
4151         }
4152         spin_unlock_irqrestore(hba->host->host_lock, flags);
4153
4154         if (update &&
4155             !pm_runtime_suspended(&hba->sdev_ufs_device->sdev_gendev)) {
4156                 ufshcd_rpm_get_sync(hba);
4157                 ufshcd_hold(hba, false);
4158                 ufshcd_auto_hibern8_enable(hba);
4159                 ufshcd_release(hba);
4160                 ufshcd_rpm_put_sync(hba);
4161         }
4162 }
4163 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
4164
4165 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
4166 {
4167         unsigned long flags;
4168
4169         if (!ufshcd_is_auto_hibern8_supported(hba))
4170                 return;
4171
4172         spin_lock_irqsave(hba->host->host_lock, flags);
4173         ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
4174         spin_unlock_irqrestore(hba->host->host_lock, flags);
4175 }
4176
4177  /**
4178  * ufshcd_init_pwr_info - setting the POR (power on reset)
4179  * values in hba power info
4180  * @hba: per-adapter instance
4181  */
4182 static void ufshcd_init_pwr_info(struct ufs_hba *hba)
4183 {
4184         hba->pwr_info.gear_rx = UFS_PWM_G1;
4185         hba->pwr_info.gear_tx = UFS_PWM_G1;
4186         hba->pwr_info.lane_rx = 1;
4187         hba->pwr_info.lane_tx = 1;
4188         hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
4189         hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
4190         hba->pwr_info.hs_rate = 0;
4191 }
4192
4193 /**
4194  * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
4195  * @hba: per-adapter instance
4196  */
4197 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
4198 {
4199         struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
4200
4201         if (hba->max_pwr_info.is_valid)
4202                 return 0;
4203
4204         pwr_info->pwr_tx = FAST_MODE;
4205         pwr_info->pwr_rx = FAST_MODE;
4206         pwr_info->hs_rate = PA_HS_MODE_B;
4207
4208         /* Get the connected lane count */
4209         ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
4210                         &pwr_info->lane_rx);
4211         ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4212                         &pwr_info->lane_tx);
4213
4214         if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
4215                 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
4216                                 __func__,
4217                                 pwr_info->lane_rx,
4218                                 pwr_info->lane_tx);
4219                 return -EINVAL;
4220         }
4221
4222         /*
4223          * First, get the maximum gears of HS speed.
4224          * If a zero value, it means there is no HSGEAR capability.
4225          * Then, get the maximum gears of PWM speed.
4226          */
4227         ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
4228         if (!pwr_info->gear_rx) {
4229                 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4230                                 &pwr_info->gear_rx);
4231                 if (!pwr_info->gear_rx) {
4232                         dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
4233                                 __func__, pwr_info->gear_rx);
4234                         return -EINVAL;
4235                 }
4236                 pwr_info->pwr_rx = SLOW_MODE;
4237         }
4238
4239         ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
4240                         &pwr_info->gear_tx);
4241         if (!pwr_info->gear_tx) {
4242                 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4243                                 &pwr_info->gear_tx);
4244                 if (!pwr_info->gear_tx) {
4245                         dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
4246                                 __func__, pwr_info->gear_tx);
4247                         return -EINVAL;
4248                 }
4249                 pwr_info->pwr_tx = SLOW_MODE;
4250         }
4251
4252         hba->max_pwr_info.is_valid = true;
4253         return 0;
4254 }
4255
4256 static int ufshcd_change_power_mode(struct ufs_hba *hba,
4257                              struct ufs_pa_layer_attr *pwr_mode)
4258 {
4259         int ret;
4260
4261         /* if already configured to the requested pwr_mode */
4262         if (!hba->force_pmc &&
4263             pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
4264             pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4265             pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4266             pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4267             pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4268             pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4269             pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4270                 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4271                 return 0;
4272         }
4273
4274         /*
4275          * Configure attributes for power mode change with below.
4276          * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4277          * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4278          * - PA_HSSERIES
4279          */
4280         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4281         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4282                         pwr_mode->lane_rx);
4283         if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4284                         pwr_mode->pwr_rx == FAST_MODE)
4285                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
4286         else
4287                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
4288
4289         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4290         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4291                         pwr_mode->lane_tx);
4292         if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4293                         pwr_mode->pwr_tx == FAST_MODE)
4294                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
4295         else
4296                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
4297
4298         if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4299             pwr_mode->pwr_tx == FASTAUTO_MODE ||
4300             pwr_mode->pwr_rx == FAST_MODE ||
4301             pwr_mode->pwr_tx == FAST_MODE)
4302                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4303                                                 pwr_mode->hs_rate);
4304
4305         if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) {
4306                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
4307                                 DL_FC0ProtectionTimeOutVal_Default);
4308                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
4309                                 DL_TC0ReplayTimeOutVal_Default);
4310                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
4311                                 DL_AFC0ReqTimeOutVal_Default);
4312                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
4313                                 DL_FC1ProtectionTimeOutVal_Default);
4314                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
4315                                 DL_TC1ReplayTimeOutVal_Default);
4316                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
4317                                 DL_AFC1ReqTimeOutVal_Default);
4318
4319                 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
4320                                 DL_FC0ProtectionTimeOutVal_Default);
4321                 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
4322                                 DL_TC0ReplayTimeOutVal_Default);
4323                 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
4324                                 DL_AFC0ReqTimeOutVal_Default);
4325         }
4326
4327         ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4328                         | pwr_mode->pwr_tx);
4329
4330         if (ret) {
4331                 dev_err(hba->dev,
4332                         "%s: power mode change failed %d\n", __func__, ret);
4333         } else {
4334                 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4335                                                                 pwr_mode);
4336
4337                 memcpy(&hba->pwr_info, pwr_mode,
4338                         sizeof(struct ufs_pa_layer_attr));
4339         }
4340
4341         return ret;
4342 }
4343
4344 /**
4345  * ufshcd_config_pwr_mode - configure a new power mode
4346  * @hba: per-adapter instance
4347  * @desired_pwr_mode: desired power configuration
4348  */
4349 int ufshcd_config_pwr_mode(struct ufs_hba *hba,
4350                 struct ufs_pa_layer_attr *desired_pwr_mode)
4351 {
4352         struct ufs_pa_layer_attr final_params = { 0 };
4353         int ret;
4354
4355         ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4356                                         desired_pwr_mode, &final_params);
4357
4358         if (ret)
4359                 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4360
4361         ret = ufshcd_change_power_mode(hba, &final_params);
4362
4363         return ret;
4364 }
4365 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
4366
4367 /**
4368  * ufshcd_complete_dev_init() - checks device readiness
4369  * @hba: per-adapter instance
4370  *
4371  * Set fDeviceInit flag and poll until device toggles it.
4372  */
4373 static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4374 {
4375         int err;
4376         bool flag_res = true;
4377         ktime_t timeout;
4378
4379         err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4380                 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL);
4381         if (err) {
4382                 dev_err(hba->dev,
4383                         "%s setting fDeviceInit flag failed with error %d\n",
4384                         __func__, err);
4385                 goto out;
4386         }
4387
4388         /* Poll fDeviceInit flag to be cleared */
4389         timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT);
4390         do {
4391                 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4392                                         QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res);
4393                 if (!flag_res)
4394                         break;
4395                 usleep_range(5000, 10000);
4396         } while (ktime_before(ktime_get(), timeout));
4397
4398         if (err) {
4399                 dev_err(hba->dev,
4400                                 "%s reading fDeviceInit flag failed with error %d\n",
4401                                 __func__, err);
4402         } else if (flag_res) {
4403                 dev_err(hba->dev,
4404                                 "%s fDeviceInit was not cleared by the device\n",
4405                                 __func__);
4406                 err = -EBUSY;
4407         }
4408 out:
4409         return err;
4410 }
4411
4412 /**
4413  * ufshcd_make_hba_operational - Make UFS controller operational
4414  * @hba: per adapter instance
4415  *
4416  * To bring UFS host controller to operational state,
4417  * 1. Enable required interrupts
4418  * 2. Configure interrupt aggregation
4419  * 3. Program UTRL and UTMRL base address
4420  * 4. Configure run-stop-registers
4421  *
4422  * Returns 0 on success, non-zero value on failure
4423  */
4424 int ufshcd_make_hba_operational(struct ufs_hba *hba)
4425 {
4426         int err = 0;
4427         u32 reg;
4428
4429         /* Enable required interrupts */
4430         ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4431
4432         /* Configure interrupt aggregation */
4433         if (ufshcd_is_intr_aggr_allowed(hba))
4434                 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4435         else
4436                 ufshcd_disable_intr_aggr(hba);
4437
4438         /* Configure UTRL and UTMRL base address registers */
4439         ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4440                         REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4441         ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4442                         REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4443         ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4444                         REG_UTP_TASK_REQ_LIST_BASE_L);
4445         ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4446                         REG_UTP_TASK_REQ_LIST_BASE_H);
4447
4448         /*
4449          * Make sure base address and interrupt setup are updated before
4450          * enabling the run/stop registers below.
4451          */
4452         wmb();
4453
4454         /*
4455          * UCRDY, UTMRLDY and UTRLRDY bits must be 1
4456          */
4457         reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
4458         if (!(ufshcd_get_lists_status(reg))) {
4459                 ufshcd_enable_run_stop_reg(hba);
4460         } else {
4461                 dev_err(hba->dev,
4462                         "Host controller not ready to process requests");
4463                 err = -EIO;
4464         }
4465
4466         return err;
4467 }
4468 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational);
4469
4470 /**
4471  * ufshcd_hba_stop - Send controller to reset state
4472  * @hba: per adapter instance
4473  */
4474 void ufshcd_hba_stop(struct ufs_hba *hba)
4475 {
4476         unsigned long flags;
4477         int err;
4478
4479         /*
4480          * Obtain the host lock to prevent that the controller is disabled
4481          * while the UFS interrupt handler is active on another CPU.
4482          */
4483         spin_lock_irqsave(hba->host->host_lock, flags);
4484         ufshcd_writel(hba, CONTROLLER_DISABLE,  REG_CONTROLLER_ENABLE);
4485         spin_unlock_irqrestore(hba->host->host_lock, flags);
4486
4487         err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4488                                         CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4489                                         10, 1);
4490         if (err)
4491                 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4492 }
4493 EXPORT_SYMBOL_GPL(ufshcd_hba_stop);
4494
4495 /**
4496  * ufshcd_hba_execute_hce - initialize the controller
4497  * @hba: per adapter instance
4498  *
4499  * The controller resets itself and controller firmware initialization
4500  * sequence kicks off. When controller is ready it will set
4501  * the Host Controller Enable bit to 1.
4502  *
4503  * Returns 0 on success, non-zero value on failure
4504  */
4505 static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
4506 {
4507         int retry_outer = 3;
4508         int retry_inner;
4509
4510 start:
4511         if (!ufshcd_is_hba_active(hba))
4512                 /* change controller state to "reset state" */
4513                 ufshcd_hba_stop(hba);
4514
4515         /* UniPro link is disabled at this point */
4516         ufshcd_set_link_off(hba);
4517
4518         ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4519
4520         /* start controller initialization sequence */
4521         ufshcd_hba_start(hba);
4522
4523         /*
4524          * To initialize a UFS host controller HCE bit must be set to 1.
4525          * During initialization the HCE bit value changes from 1->0->1.
4526          * When the host controller completes initialization sequence
4527          * it sets the value of HCE bit to 1. The same HCE bit is read back
4528          * to check if the controller has completed initialization sequence.
4529          * So without this delay the value HCE = 1, set in the previous
4530          * instruction might be read back.
4531          * This delay can be changed based on the controller.
4532          */
4533         ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100);
4534
4535         /* wait for the host controller to complete initialization */
4536         retry_inner = 50;
4537         while (ufshcd_is_hba_active(hba)) {
4538                 if (retry_inner) {
4539                         retry_inner--;
4540                 } else {
4541                         dev_err(hba->dev,
4542                                 "Controller enable failed\n");
4543                         if (retry_outer) {
4544                                 retry_outer--;
4545                                 goto start;
4546                         }
4547                         return -EIO;
4548                 }
4549                 usleep_range(1000, 1100);
4550         }
4551
4552         /* enable UIC related interrupts */
4553         ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4554
4555         ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4556
4557         return 0;
4558 }
4559
4560 int ufshcd_hba_enable(struct ufs_hba *hba)
4561 {
4562         int ret;
4563
4564         if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4565                 ufshcd_set_link_off(hba);
4566                 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4567
4568                 /* enable UIC related interrupts */
4569                 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4570                 ret = ufshcd_dme_reset(hba);
4571                 if (!ret) {
4572                         ret = ufshcd_dme_enable(hba);
4573                         if (!ret)
4574                                 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4575                         if (ret)
4576                                 dev_err(hba->dev,
4577                                         "Host controller enable failed with non-hce\n");
4578                 }
4579         } else {
4580                 ret = ufshcd_hba_execute_hce(hba);
4581         }
4582
4583         return ret;
4584 }
4585 EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
4586
4587 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4588 {
4589         int tx_lanes = 0, i, err = 0;
4590
4591         if (!peer)
4592                 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4593                                &tx_lanes);
4594         else
4595                 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4596                                     &tx_lanes);
4597         for (i = 0; i < tx_lanes; i++) {
4598                 if (!peer)
4599                         err = ufshcd_dme_set(hba,
4600                                 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4601                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4602                                         0);
4603                 else
4604                         err = ufshcd_dme_peer_set(hba,
4605                                 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4606                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4607                                         0);
4608                 if (err) {
4609                         dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4610                                 __func__, peer, i, err);
4611                         break;
4612                 }
4613         }
4614
4615         return err;
4616 }
4617
4618 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4619 {
4620         return ufshcd_disable_tx_lcc(hba, true);
4621 }
4622
4623 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val)
4624 {
4625         struct ufs_event_hist *e;
4626
4627         if (id >= UFS_EVT_CNT)
4628                 return;
4629
4630         e = &hba->ufs_stats.event[id];
4631         e->val[e->pos] = val;
4632         e->tstamp[e->pos] = ktime_get();
4633         e->cnt += 1;
4634         e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH;
4635
4636         ufshcd_vops_event_notify(hba, id, &val);
4637 }
4638 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist);
4639
4640 /**
4641  * ufshcd_link_startup - Initialize unipro link startup
4642  * @hba: per adapter instance
4643  *
4644  * Returns 0 for success, non-zero in case of failure
4645  */
4646 static int ufshcd_link_startup(struct ufs_hba *hba)
4647 {
4648         int ret;
4649         int retries = DME_LINKSTARTUP_RETRIES;
4650         bool link_startup_again = false;
4651
4652         /*
4653          * If UFS device isn't active then we will have to issue link startup
4654          * 2 times to make sure the device state move to active.
4655          */
4656         if (!ufshcd_is_ufs_dev_active(hba))
4657                 link_startup_again = true;
4658
4659 link_startup:
4660         do {
4661                 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
4662
4663                 ret = ufshcd_dme_link_startup(hba);
4664
4665                 /* check if device is detected by inter-connect layer */
4666                 if (!ret && !ufshcd_is_device_present(hba)) {
4667                         ufshcd_update_evt_hist(hba,
4668                                                UFS_EVT_LINK_STARTUP_FAIL,
4669                                                0);
4670                         dev_err(hba->dev, "%s: Device not present\n", __func__);
4671                         ret = -ENXIO;
4672                         goto out;
4673                 }
4674
4675                 /*
4676                  * DME link lost indication is only received when link is up,
4677                  * but we can't be sure if the link is up until link startup
4678                  * succeeds. So reset the local Uni-Pro and try again.
4679                  */
4680                 if (ret && ufshcd_hba_enable(hba)) {
4681                         ufshcd_update_evt_hist(hba,
4682                                                UFS_EVT_LINK_STARTUP_FAIL,
4683                                                (u32)ret);
4684                         goto out;
4685                 }
4686         } while (ret && retries--);
4687
4688         if (ret) {
4689                 /* failed to get the link up... retire */
4690                 ufshcd_update_evt_hist(hba,
4691                                        UFS_EVT_LINK_STARTUP_FAIL,
4692                                        (u32)ret);
4693                 goto out;
4694         }
4695
4696         if (link_startup_again) {
4697                 link_startup_again = false;
4698                 retries = DME_LINKSTARTUP_RETRIES;
4699                 goto link_startup;
4700         }
4701
4702         /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4703         ufshcd_init_pwr_info(hba);
4704         ufshcd_print_pwr_info(hba);
4705
4706         if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4707                 ret = ufshcd_disable_device_tx_lcc(hba);
4708                 if (ret)
4709                         goto out;
4710         }
4711
4712         /* Include any host controller configuration via UIC commands */
4713         ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4714         if (ret)
4715                 goto out;
4716
4717         /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */
4718         ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
4719         ret = ufshcd_make_hba_operational(hba);
4720 out:
4721         if (ret) {
4722                 dev_err(hba->dev, "link startup failed %d\n", ret);
4723                 ufshcd_print_host_state(hba);
4724                 ufshcd_print_pwr_info(hba);
4725                 ufshcd_print_evt_hist(hba);
4726         }
4727         return ret;
4728 }
4729
4730 /**
4731  * ufshcd_verify_dev_init() - Verify device initialization
4732  * @hba: per-adapter instance
4733  *
4734  * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4735  * device Transport Protocol (UTP) layer is ready after a reset.
4736  * If the UTP layer at the device side is not initialized, it may
4737  * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4738  * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4739  */
4740 static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4741 {
4742         int err = 0;
4743         int retries;
4744
4745         ufshcd_hold(hba, false);
4746         mutex_lock(&hba->dev_cmd.lock);
4747         for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4748                 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4749                                                NOP_OUT_TIMEOUT);
4750
4751                 if (!err || err == -ETIMEDOUT)
4752                         break;
4753
4754                 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4755         }
4756         mutex_unlock(&hba->dev_cmd.lock);
4757         ufshcd_release(hba);
4758
4759         if (err)
4760                 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4761         return err;
4762 }
4763
4764 /**
4765  * ufshcd_set_queue_depth - set lun queue depth
4766  * @sdev: pointer to SCSI device
4767  *
4768  * Read bLUQueueDepth value and activate scsi tagged command
4769  * queueing. For WLUN, queue depth is set to 1. For best-effort
4770  * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4771  * value that host can queue.
4772  */
4773 static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4774 {
4775         int ret = 0;
4776         u8 lun_qdepth;
4777         struct ufs_hba *hba;
4778
4779         hba = shost_priv(sdev->host);
4780
4781         lun_qdepth = hba->nutrs;
4782         ret = ufshcd_read_unit_desc_param(hba,
4783                                           ufshcd_scsi_to_upiu_lun(sdev->lun),
4784                                           UNIT_DESC_PARAM_LU_Q_DEPTH,
4785                                           &lun_qdepth,
4786                                           sizeof(lun_qdepth));
4787
4788         /* Some WLUN doesn't support unit descriptor */
4789         if (ret == -EOPNOTSUPP)
4790                 lun_qdepth = 1;
4791         else if (!lun_qdepth)
4792                 /* eventually, we can figure out the real queue depth */
4793                 lun_qdepth = hba->nutrs;
4794         else
4795                 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4796
4797         dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4798                         __func__, lun_qdepth);
4799         scsi_change_queue_depth(sdev, lun_qdepth);
4800 }
4801
4802 /*
4803  * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4804  * @hba: per-adapter instance
4805  * @lun: UFS device lun id
4806  * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4807  *
4808  * Returns 0 in case of success and b_lu_write_protect status would be returned
4809  * @b_lu_write_protect parameter.
4810  * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4811  * Returns -EINVAL in case of invalid parameters passed to this function.
4812  */
4813 static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4814                             u8 lun,
4815                             u8 *b_lu_write_protect)
4816 {
4817         int ret;
4818
4819         if (!b_lu_write_protect)
4820                 ret = -EINVAL;
4821         /*
4822          * According to UFS device spec, RPMB LU can't be write
4823          * protected so skip reading bLUWriteProtect parameter for
4824          * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4825          */
4826         else if (lun >= hba->dev_info.max_lu_supported)
4827                 ret = -ENOTSUPP;
4828         else
4829                 ret = ufshcd_read_unit_desc_param(hba,
4830                                           lun,
4831                                           UNIT_DESC_PARAM_LU_WR_PROTECT,
4832                                           b_lu_write_protect,
4833                                           sizeof(*b_lu_write_protect));
4834         return ret;
4835 }
4836
4837 /**
4838  * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4839  * status
4840  * @hba: per-adapter instance
4841  * @sdev: pointer to SCSI device
4842  *
4843  */
4844 static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4845                                                     struct scsi_device *sdev)
4846 {
4847         if (hba->dev_info.f_power_on_wp_en &&
4848             !hba->dev_info.is_lu_power_on_wp) {
4849                 u8 b_lu_write_protect;
4850
4851                 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4852                                       &b_lu_write_protect) &&
4853                     (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4854                         hba->dev_info.is_lu_power_on_wp = true;
4855         }
4856 }
4857
4858 /**
4859  * ufshcd_setup_links - associate link b/w device wlun and other luns
4860  * @sdev: pointer to SCSI device
4861  * @hba: pointer to ufs hba
4862  */
4863 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev)
4864 {
4865         struct device_link *link;
4866
4867         /*
4868          * Device wlun is the supplier & rest of the luns are consumers.
4869          * This ensures that device wlun suspends after all other luns.
4870          */
4871         if (hba->sdev_ufs_device) {
4872                 link = device_link_add(&sdev->sdev_gendev,
4873                                        &hba->sdev_ufs_device->sdev_gendev,
4874                                        DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
4875                 if (!link) {
4876                         dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n",
4877                                 dev_name(&hba->sdev_ufs_device->sdev_gendev));
4878                         return;
4879                 }
4880                 hba->luns_avail--;
4881                 /* Ignore REPORT_LUN wlun probing */
4882                 if (hba->luns_avail == 1) {
4883                         ufshcd_rpm_put(hba);
4884                         return;
4885                 }
4886         } else {
4887                 /*
4888                  * Device wlun is probed. The assumption is that WLUNs are
4889                  * scanned before other LUNs.
4890                  */
4891                 hba->luns_avail--;
4892         }
4893 }
4894
4895 /**
4896  * ufshcd_slave_alloc - handle initial SCSI device configurations
4897  * @sdev: pointer to SCSI device
4898  *
4899  * Returns success
4900  */
4901 static int ufshcd_slave_alloc(struct scsi_device *sdev)
4902 {
4903         struct ufs_hba *hba;
4904
4905         hba = shost_priv(sdev->host);
4906
4907         /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4908         sdev->use_10_for_ms = 1;
4909
4910         /* DBD field should be set to 1 in mode sense(10) */
4911         sdev->set_dbd_for_ms = 1;
4912
4913         /* allow SCSI layer to restart the device in case of errors */
4914         sdev->allow_restart = 1;
4915
4916         /* REPORT SUPPORTED OPERATION CODES is not supported */
4917         sdev->no_report_opcodes = 1;
4918
4919         /* WRITE_SAME command is not supported */
4920         sdev->no_write_same = 1;
4921
4922         ufshcd_set_queue_depth(sdev);
4923
4924         ufshcd_get_lu_power_on_wp_status(hba, sdev);
4925
4926         ufshcd_setup_links(hba, sdev);
4927
4928         return 0;
4929 }
4930
4931 /**
4932  * ufshcd_change_queue_depth - change queue depth
4933  * @sdev: pointer to SCSI device
4934  * @depth: required depth to set
4935  *
4936  * Change queue depth and make sure the max. limits are not crossed.
4937  */
4938 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4939 {
4940         struct ufs_hba *hba = shost_priv(sdev->host);
4941
4942         if (depth > hba->nutrs)
4943                 depth = hba->nutrs;
4944         return scsi_change_queue_depth(sdev, depth);
4945 }
4946
4947 static void ufshcd_hpb_destroy(struct ufs_hba *hba, struct scsi_device *sdev)
4948 {
4949         /* skip well-known LU */
4950         if ((sdev->lun >= UFS_UPIU_MAX_UNIT_NUM_ID) ||
4951             !(hba->dev_info.hpb_enabled) || !ufshpb_is_allowed(hba))
4952                 return;
4953
4954         ufshpb_destroy_lu(hba, sdev);
4955 }
4956
4957 static void ufshcd_hpb_configure(struct ufs_hba *hba, struct scsi_device *sdev)
4958 {
4959         /* skip well-known LU */
4960         if ((sdev->lun >= UFS_UPIU_MAX_UNIT_NUM_ID) ||
4961             !(hba->dev_info.hpb_enabled) || !ufshpb_is_allowed(hba))
4962                 return;
4963
4964         ufshpb_init_hpb_lu(hba, sdev);
4965 }
4966
4967 /**
4968  * ufshcd_slave_configure - adjust SCSI device configurations
4969  * @sdev: pointer to SCSI device
4970  */
4971 static int ufshcd_slave_configure(struct scsi_device *sdev)
4972 {
4973         struct ufs_hba *hba = shost_priv(sdev->host);
4974         struct request_queue *q = sdev->request_queue;
4975
4976         ufshcd_hpb_configure(hba, sdev);
4977
4978         blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
4979         if (hba->quirks & UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE)
4980                 blk_queue_update_dma_alignment(q, PAGE_SIZE - 1);
4981         /*
4982          * Block runtime-pm until all consumers are added.
4983          * Refer ufshcd_setup_links().
4984          */
4985         if (is_device_wlun(sdev))
4986                 pm_runtime_get_noresume(&sdev->sdev_gendev);
4987         else if (ufshcd_is_rpm_autosuspend_allowed(hba))
4988                 sdev->rpm_autosuspend = 1;
4989
4990         ufshcd_crypto_setup_rq_keyslot_manager(hba, q);
4991
4992         return 0;
4993 }
4994
4995 /**
4996  * ufshcd_slave_destroy - remove SCSI device configurations
4997  * @sdev: pointer to SCSI device
4998  */
4999 static void ufshcd_slave_destroy(struct scsi_device *sdev)
5000 {
5001         struct ufs_hba *hba;
5002
5003         hba = shost_priv(sdev->host);
5004
5005         ufshcd_hpb_destroy(hba, sdev);
5006
5007         /* Drop the reference as it won't be needed anymore */
5008         if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
5009                 unsigned long flags;
5010
5011                 spin_lock_irqsave(hba->host->host_lock, flags);
5012                 hba->sdev_ufs_device = NULL;
5013                 spin_unlock_irqrestore(hba->host->host_lock, flags);
5014         }
5015 }
5016
5017 /**
5018  * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
5019  * @lrbp: pointer to local reference block of completed command
5020  * @scsi_status: SCSI command status
5021  *
5022  * Returns value base on SCSI command status
5023  */
5024 static inline int
5025 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
5026 {
5027         int result = 0;
5028
5029         switch (scsi_status) {
5030         case SAM_STAT_CHECK_CONDITION:
5031                 ufshcd_copy_sense_data(lrbp);
5032                 fallthrough;
5033         case SAM_STAT_GOOD:
5034                 result |= DID_OK << 16 | scsi_status;
5035                 break;
5036         case SAM_STAT_TASK_SET_FULL:
5037         case SAM_STAT_BUSY:
5038         case SAM_STAT_TASK_ABORTED:
5039                 ufshcd_copy_sense_data(lrbp);
5040                 result |= scsi_status;
5041                 break;
5042         default:
5043                 result |= DID_ERROR << 16;
5044                 break;
5045         } /* end of switch */
5046
5047         return result;
5048 }
5049
5050 /**
5051  * ufshcd_transfer_rsp_status - Get overall status of the response
5052  * @hba: per adapter instance
5053  * @lrbp: pointer to local reference block of completed command
5054  *
5055  * Returns result of the command to notify SCSI midlayer
5056  */
5057 static inline int
5058 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
5059 {
5060         int result = 0;
5061         int scsi_status;
5062         int ocs;
5063
5064         /* overall command status of utrd */
5065         ocs = ufshcd_get_tr_ocs(lrbp);
5066
5067         if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) {
5068                 if (be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_1) &
5069                                         MASK_RSP_UPIU_RESULT)
5070                         ocs = OCS_SUCCESS;
5071         }
5072
5073         switch (ocs) {
5074         case OCS_SUCCESS:
5075                 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
5076                 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5077                 switch (result) {
5078                 case UPIU_TRANSACTION_RESPONSE:
5079                         /*
5080                          * get the response UPIU result to extract
5081                          * the SCSI command status
5082                          */
5083                         result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
5084
5085                         /*
5086                          * get the result based on SCSI status response
5087                          * to notify the SCSI midlayer of the command status
5088                          */
5089                         scsi_status = result & MASK_SCSI_STATUS;
5090                         result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
5091
5092                         /*
5093                          * Currently we are only supporting BKOPs exception
5094                          * events hence we can ignore BKOPs exception event
5095                          * during power management callbacks. BKOPs exception
5096                          * event is not expected to be raised in runtime suspend
5097                          * callback as it allows the urgent bkops.
5098                          * During system suspend, we are anyway forcefully
5099                          * disabling the bkops and if urgent bkops is needed
5100                          * it will be enabled on system resume. Long term
5101                          * solution could be to abort the system suspend if
5102                          * UFS device needs urgent BKOPs.
5103                          */
5104                         if (!hba->pm_op_in_progress &&
5105                             !ufshcd_eh_in_progress(hba) &&
5106                             ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
5107                                 /* Flushed in suspend */
5108                                 schedule_work(&hba->eeh_work);
5109
5110                         if (scsi_status == SAM_STAT_GOOD)
5111                                 ufshpb_rsp_upiu(hba, lrbp);
5112                         break;
5113                 case UPIU_TRANSACTION_REJECT_UPIU:
5114                         /* TODO: handle Reject UPIU Response */
5115                         result = DID_ERROR << 16;
5116                         dev_err(hba->dev,
5117                                 "Reject UPIU not fully implemented\n");
5118                         break;
5119                 default:
5120                         dev_err(hba->dev,
5121                                 "Unexpected request response code = %x\n",
5122                                 result);
5123                         result = DID_ERROR << 16;
5124                         break;
5125                 }
5126                 break;
5127         case OCS_ABORTED:
5128                 result |= DID_ABORT << 16;
5129                 break;
5130         case OCS_INVALID_COMMAND_STATUS:
5131                 result |= DID_REQUEUE << 16;
5132                 break;
5133         case OCS_INVALID_CMD_TABLE_ATTR:
5134         case OCS_INVALID_PRDT_ATTR:
5135         case OCS_MISMATCH_DATA_BUF_SIZE:
5136         case OCS_MISMATCH_RESP_UPIU_SIZE:
5137         case OCS_PEER_COMM_FAILURE:
5138         case OCS_FATAL_ERROR:
5139         case OCS_DEVICE_FATAL_ERROR:
5140         case OCS_INVALID_CRYPTO_CONFIG:
5141         case OCS_GENERAL_CRYPTO_ERROR:
5142         default:
5143                 result |= DID_ERROR << 16;
5144                 dev_err(hba->dev,
5145                                 "OCS error from controller = %x for tag %d\n",
5146                                 ocs, lrbp->task_tag);
5147                 ufshcd_print_evt_hist(hba);
5148                 ufshcd_print_host_state(hba);
5149                 break;
5150         } /* end of switch */
5151
5152         if ((host_byte(result) != DID_OK) &&
5153             (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs)
5154                 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
5155         return result;
5156 }
5157
5158 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
5159                                          u32 intr_mask)
5160 {
5161         if (!ufshcd_is_auto_hibern8_supported(hba) ||
5162             !ufshcd_is_auto_hibern8_enabled(hba))
5163                 return false;
5164
5165         if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
5166                 return false;
5167
5168         if (hba->active_uic_cmd &&
5169             (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
5170             hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
5171                 return false;
5172
5173         return true;
5174 }
5175
5176 /**
5177  * ufshcd_uic_cmd_compl - handle completion of uic command
5178  * @hba: per adapter instance
5179  * @intr_status: interrupt status generated by the controller
5180  *
5181  * Returns
5182  *  IRQ_HANDLED - If interrupt is valid
5183  *  IRQ_NONE    - If invalid interrupt
5184  */
5185 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
5186 {
5187         irqreturn_t retval = IRQ_NONE;
5188
5189         spin_lock(hba->host->host_lock);
5190         if (ufshcd_is_auto_hibern8_error(hba, intr_status))
5191                 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
5192
5193         if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
5194                 hba->active_uic_cmd->argument2 |=
5195                         ufshcd_get_uic_cmd_result(hba);
5196                 hba->active_uic_cmd->argument3 =
5197                         ufshcd_get_dme_attr_val(hba);
5198                 if (!hba->uic_async_done)
5199                         hba->active_uic_cmd->cmd_active = 0;
5200                 complete(&hba->active_uic_cmd->done);
5201                 retval = IRQ_HANDLED;
5202         }
5203
5204         if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
5205                 hba->active_uic_cmd->cmd_active = 0;
5206                 complete(hba->uic_async_done);
5207                 retval = IRQ_HANDLED;
5208         }
5209
5210         if (retval == IRQ_HANDLED)
5211                 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd,
5212                                              UFS_CMD_COMP);
5213         spin_unlock(hba->host->host_lock);
5214         return retval;
5215 }
5216
5217 /**
5218  * __ufshcd_transfer_req_compl - handle SCSI and query command completion
5219  * @hba: per adapter instance
5220  * @completed_reqs: requests to complete
5221  */
5222 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
5223                                         unsigned long completed_reqs)
5224 {
5225         struct ufshcd_lrb *lrbp;
5226         struct scsi_cmnd *cmd;
5227         int result;
5228         int index;
5229         bool update_scaling = false;
5230
5231         for_each_set_bit(index, &completed_reqs, hba->nutrs) {
5232                 if (!test_and_clear_bit(index, &hba->outstanding_reqs))
5233                         continue;
5234                 lrbp = &hba->lrb[index];
5235                 lrbp->compl_time_stamp = ktime_get();
5236                 cmd = lrbp->cmd;
5237                 if (cmd) {
5238                         if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
5239                                 ufshcd_update_monitor(hba, lrbp);
5240                         ufshcd_add_command_trace(hba, index, UFS_CMD_COMP);
5241                         result = ufshcd_transfer_rsp_status(hba, lrbp);
5242                         scsi_dma_unmap(cmd);
5243                         cmd->result = result;
5244                         /* Mark completed command as NULL in LRB */
5245                         lrbp->cmd = NULL;
5246                         /* Do not touch lrbp after scsi done */
5247                         cmd->scsi_done(cmd);
5248                         ufshcd_release(hba);
5249                         update_scaling = true;
5250                 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
5251                         lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
5252                         if (hba->dev_cmd.complete) {
5253                                 ufshcd_add_command_trace(hba, index,
5254                                                          UFS_DEV_COMP);
5255                                 complete(hba->dev_cmd.complete);
5256                                 update_scaling = true;
5257                         }
5258                 }
5259                 if (update_scaling)
5260                         ufshcd_clk_scaling_update_busy(hba);
5261         }
5262 }
5263
5264 /**
5265  * ufshcd_transfer_req_compl - handle SCSI and query command completion
5266  * @hba: per adapter instance
5267  *
5268  * Returns
5269  *  IRQ_HANDLED - If interrupt is valid
5270  *  IRQ_NONE    - If invalid interrupt
5271  */
5272 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
5273 {
5274         unsigned long completed_reqs, flags;
5275         u32 tr_doorbell;
5276
5277         /* Resetting interrupt aggregation counters first and reading the
5278          * DOOR_BELL afterward allows us to handle all the completed requests.
5279          * In order to prevent other interrupts starvation the DB is read once
5280          * after reset. The down side of this solution is the possibility of
5281          * false interrupt if device completes another request after resetting
5282          * aggregation and before reading the DB.
5283          */
5284         if (ufshcd_is_intr_aggr_allowed(hba) &&
5285             !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
5286                 ufshcd_reset_intr_aggr(hba);
5287
5288         spin_lock_irqsave(hba->host->host_lock, flags);
5289         tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5290         completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
5291         spin_unlock_irqrestore(hba->host->host_lock, flags);
5292
5293         if (completed_reqs) {
5294                 __ufshcd_transfer_req_compl(hba, completed_reqs);
5295                 return IRQ_HANDLED;
5296         } else {
5297                 return IRQ_NONE;
5298         }
5299 }
5300
5301 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask)
5302 {
5303         return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5304                                        QUERY_ATTR_IDN_EE_CONTROL, 0, 0,
5305                                        &ee_ctrl_mask);
5306 }
5307
5308 int ufshcd_write_ee_control(struct ufs_hba *hba)
5309 {
5310         int err;
5311
5312         mutex_lock(&hba->ee_ctrl_mutex);
5313         err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask);
5314         mutex_unlock(&hba->ee_ctrl_mutex);
5315         if (err)
5316                 dev_err(hba->dev, "%s: failed to write ee control %d\n",
5317                         __func__, err);
5318         return err;
5319 }
5320
5321 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, u16 *other_mask,
5322                              u16 set, u16 clr)
5323 {
5324         u16 new_mask, ee_ctrl_mask;
5325         int err = 0;
5326
5327         mutex_lock(&hba->ee_ctrl_mutex);
5328         new_mask = (*mask & ~clr) | set;
5329         ee_ctrl_mask = new_mask | *other_mask;
5330         if (ee_ctrl_mask != hba->ee_ctrl_mask)
5331                 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask);
5332         /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */
5333         if (!err) {
5334                 hba->ee_ctrl_mask = ee_ctrl_mask;
5335                 *mask = new_mask;
5336         }
5337         mutex_unlock(&hba->ee_ctrl_mutex);
5338         return err;
5339 }
5340
5341 /**
5342  * ufshcd_disable_ee - disable exception event
5343  * @hba: per-adapter instance
5344  * @mask: exception event to disable
5345  *
5346  * Disables exception event in the device so that the EVENT_ALERT
5347  * bit is not set.
5348  *
5349  * Returns zero on success, non-zero error value on failure.
5350  */
5351 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
5352 {
5353         return ufshcd_update_ee_drv_mask(hba, 0, mask);
5354 }
5355
5356 /**
5357  * ufshcd_enable_ee - enable exception event
5358  * @hba: per-adapter instance
5359  * @mask: exception event to enable
5360  *
5361  * Enable corresponding exception event in the device to allow
5362  * device to alert host in critical scenarios.
5363  *
5364  * Returns zero on success, non-zero error value on failure.
5365  */
5366 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
5367 {
5368         return ufshcd_update_ee_drv_mask(hba, mask, 0);
5369 }
5370
5371 /**
5372  * ufshcd_enable_auto_bkops - Allow device managed BKOPS
5373  * @hba: per-adapter instance
5374  *
5375  * Allow device to manage background operations on its own. Enabling
5376  * this might lead to inconsistent latencies during normal data transfers
5377  * as the device is allowed to manage its own way of handling background
5378  * operations.
5379  *
5380  * Returns zero on success, non-zero on failure.
5381  */
5382 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
5383 {
5384         int err = 0;
5385
5386         if (hba->auto_bkops_enabled)
5387                 goto out;
5388
5389         err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
5390                         QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5391         if (err) {
5392                 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
5393                                 __func__, err);
5394                 goto out;
5395         }
5396
5397         hba->auto_bkops_enabled = true;
5398         trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
5399
5400         /* No need of URGENT_BKOPS exception from the device */
5401         err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5402         if (err)
5403                 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
5404                                 __func__, err);
5405 out:
5406         return err;
5407 }
5408
5409 /**
5410  * ufshcd_disable_auto_bkops - block device in doing background operations
5411  * @hba: per-adapter instance
5412  *
5413  * Disabling background operations improves command response latency but
5414  * has drawback of device moving into critical state where the device is
5415  * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
5416  * host is idle so that BKOPS are managed effectively without any negative
5417  * impacts.
5418  *
5419  * Returns zero on success, non-zero on failure.
5420  */
5421 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5422 {
5423         int err = 0;
5424
5425         if (!hba->auto_bkops_enabled)
5426                 goto out;
5427
5428         /*
5429          * If host assisted BKOPs is to be enabled, make sure
5430          * urgent bkops exception is allowed.
5431          */
5432         err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5433         if (err) {
5434                 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5435                                 __func__, err);
5436                 goto out;
5437         }
5438
5439         err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
5440                         QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5441         if (err) {
5442                 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5443                                 __func__, err);
5444                 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5445                 goto out;
5446         }
5447
5448         hba->auto_bkops_enabled = false;
5449         trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
5450         hba->is_urgent_bkops_lvl_checked = false;
5451 out:
5452         return err;
5453 }
5454
5455 /**
5456  * ufshcd_force_reset_auto_bkops - force reset auto bkops state
5457  * @hba: per adapter instance
5458  *
5459  * After a device reset the device may toggle the BKOPS_EN flag
5460  * to default value. The s/w tracking variables should be updated
5461  * as well. This function would change the auto-bkops state based on
5462  * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
5463  */
5464 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
5465 {
5466         if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5467                 hba->auto_bkops_enabled = false;
5468                 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5469                 ufshcd_enable_auto_bkops(hba);
5470         } else {
5471                 hba->auto_bkops_enabled = true;
5472                 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5473                 ufshcd_disable_auto_bkops(hba);
5474         }
5475         hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
5476         hba->is_urgent_bkops_lvl_checked = false;
5477 }
5478
5479 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5480 {
5481         return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5482                         QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5483 }
5484
5485 /**
5486  * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
5487  * @hba: per-adapter instance
5488  * @status: bkops_status value
5489  *
5490  * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5491  * flag in the device to permit background operations if the device
5492  * bkops_status is greater than or equal to "status" argument passed to
5493  * this function, disable otherwise.
5494  *
5495  * Returns 0 for success, non-zero in case of failure.
5496  *
5497  * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5498  * to know whether auto bkops is enabled or disabled after this function
5499  * returns control to it.
5500  */
5501 static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5502                              enum bkops_status status)
5503 {
5504         int err;
5505         u32 curr_status = 0;
5506
5507         err = ufshcd_get_bkops_status(hba, &curr_status);
5508         if (err) {
5509                 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5510                                 __func__, err);
5511                 goto out;
5512         } else if (curr_status > BKOPS_STATUS_MAX) {
5513                 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5514                                 __func__, curr_status);
5515                 err = -EINVAL;
5516                 goto out;
5517         }
5518
5519         if (curr_status >= status)
5520                 err = ufshcd_enable_auto_bkops(hba);
5521         else
5522                 err = ufshcd_disable_auto_bkops(hba);
5523 out:
5524         return err;
5525 }
5526
5527 /**
5528  * ufshcd_urgent_bkops - handle urgent bkops exception event
5529  * @hba: per-adapter instance
5530  *
5531  * Enable fBackgroundOpsEn flag in the device to permit background
5532  * operations.
5533  *
5534  * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5535  * and negative error value for any other failure.
5536  */
5537 static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5538 {
5539         return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
5540 }
5541
5542 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5543 {
5544         return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5545                         QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5546 }
5547
5548 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5549 {
5550         int err;
5551         u32 curr_status = 0;
5552
5553         if (hba->is_urgent_bkops_lvl_checked)
5554                 goto enable_auto_bkops;
5555
5556         err = ufshcd_get_bkops_status(hba, &curr_status);
5557         if (err) {
5558                 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5559                                 __func__, err);
5560                 goto out;
5561         }
5562
5563         /*
5564          * We are seeing that some devices are raising the urgent bkops
5565          * exception events even when BKOPS status doesn't indicate performace
5566          * impacted or critical. Handle these device by determining their urgent
5567          * bkops status at runtime.
5568          */
5569         if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5570                 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5571                                 __func__, curr_status);
5572                 /* update the current status as the urgent bkops level */
5573                 hba->urgent_bkops_lvl = curr_status;
5574                 hba->is_urgent_bkops_lvl_checked = true;
5575         }
5576
5577 enable_auto_bkops:
5578         err = ufshcd_enable_auto_bkops(hba);
5579 out:
5580         if (err < 0)
5581                 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5582                                 __func__, err);
5583 }
5584
5585 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn)
5586 {
5587         u8 index;
5588         enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG :
5589                                    UPIU_QUERY_OPCODE_CLEAR_FLAG;
5590
5591         index = ufshcd_wb_get_query_index(hba);
5592         return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL);
5593 }
5594
5595 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable)
5596 {
5597         int ret;
5598
5599         if (!ufshcd_is_wb_allowed(hba))
5600                 return 0;
5601
5602         if (!(enable ^ hba->dev_info.wb_enabled))
5603                 return 0;
5604
5605         ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN);
5606         if (ret) {
5607                 dev_err(hba->dev, "%s Write Booster %s failed %d\n",
5608                         __func__, enable ? "enable" : "disable", ret);
5609                 return ret;
5610         }
5611
5612         hba->dev_info.wb_enabled = enable;
5613         dev_info(hba->dev, "%s Write Booster %s\n",
5614                         __func__, enable ? "enabled" : "disabled");
5615
5616         return ret;
5617 }
5618
5619 static void ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set)
5620 {
5621         int ret;
5622
5623         ret = __ufshcd_wb_toggle(hba, set,
5624                         QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8);
5625         if (ret) {
5626                 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed: %d\n",
5627                         __func__, set ? "enable" : "disable", ret);
5628                 return;
5629         }
5630         dev_dbg(hba->dev, "%s WB-Buf Flush during H8 %s\n",
5631                         __func__, set ? "enabled" : "disabled");
5632 }
5633
5634 static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable)
5635 {
5636         int ret;
5637
5638         if (!ufshcd_is_wb_allowed(hba) ||
5639             hba->dev_info.wb_buf_flush_enabled == enable)
5640                 return;
5641
5642         ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN);
5643         if (ret) {
5644                 dev_err(hba->dev, "%s WB-Buf Flush %s failed %d\n", __func__,
5645                         enable ? "enable" : "disable", ret);
5646                 return;
5647         }
5648
5649         hba->dev_info.wb_buf_flush_enabled = enable;
5650
5651         dev_dbg(hba->dev, "%s WB-Buf Flush %s\n",
5652                         __func__, enable ? "enabled" : "disabled");
5653 }
5654
5655 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba,
5656                                                 u32 avail_buf)
5657 {
5658         u32 cur_buf;
5659         int ret;
5660         u8 index;
5661
5662         index = ufshcd_wb_get_query_index(hba);
5663         ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5664                                               QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE,
5665                                               index, 0, &cur_buf);
5666         if (ret) {
5667                 dev_err(hba->dev, "%s dCurWriteBoosterBufferSize read failed %d\n",
5668                         __func__, ret);
5669                 return false;
5670         }
5671
5672         if (!cur_buf) {
5673                 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n",
5674                          cur_buf);
5675                 return false;
5676         }
5677         /* Let it continue to flush when available buffer exceeds threshold */
5678         if (avail_buf < hba->vps->wb_flush_threshold)
5679                 return true;
5680
5681         return false;
5682 }
5683
5684 static bool ufshcd_wb_need_flush(struct ufs_hba *hba)
5685 {
5686         int ret;
5687         u32 avail_buf;
5688         u8 index;
5689
5690         if (!ufshcd_is_wb_allowed(hba))
5691                 return false;
5692         /*
5693          * The ufs device needs the vcc to be ON to flush.
5694          * With user-space reduction enabled, it's enough to enable flush
5695          * by checking only the available buffer. The threshold
5696          * defined here is > 90% full.
5697          * With user-space preserved enabled, the current-buffer
5698          * should be checked too because the wb buffer size can reduce
5699          * when disk tends to be full. This info is provided by current
5700          * buffer (dCurrentWriteBoosterBufferSize). There's no point in
5701          * keeping vcc on when current buffer is empty.
5702          */
5703         index = ufshcd_wb_get_query_index(hba);
5704         ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5705                                       QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE,
5706                                       index, 0, &avail_buf);
5707         if (ret) {
5708                 dev_warn(hba->dev, "%s dAvailableWriteBoosterBufferSize read failed %d\n",
5709                          __func__, ret);
5710                 return false;
5711         }
5712
5713         if (!hba->dev_info.b_presrv_uspc_en) {
5714                 if (avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10))
5715                         return true;
5716                 return false;
5717         }
5718
5719         return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf);
5720 }
5721
5722 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work)
5723 {
5724         struct ufs_hba *hba = container_of(to_delayed_work(work),
5725                                            struct ufs_hba,
5726                                            rpm_dev_flush_recheck_work);
5727         /*
5728          * To prevent unnecessary VCC power drain after device finishes
5729          * WriteBooster buffer flush or Auto BKOPs, force runtime resume
5730          * after a certain delay to recheck the threshold by next runtime
5731          * suspend.
5732          */
5733         ufshcd_rpm_get_sync(hba);
5734         ufshcd_rpm_put_sync(hba);
5735 }
5736
5737 /**
5738  * ufshcd_exception_event_handler - handle exceptions raised by device
5739  * @work: pointer to work data
5740  *
5741  * Read bExceptionEventStatus attribute from the device and handle the
5742  * exception event accordingly.
5743  */
5744 static void ufshcd_exception_event_handler(struct work_struct *work)
5745 {
5746         struct ufs_hba *hba;
5747         int err;
5748         u32 status = 0;
5749         hba = container_of(work, struct ufs_hba, eeh_work);
5750
5751         ufshcd_scsi_block_requests(hba);
5752         err = ufshcd_get_ee_status(hba, &status);
5753         if (err) {
5754                 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5755                                 __func__, err);
5756                 goto out;
5757         }
5758
5759         trace_ufshcd_exception_event(dev_name(hba->dev), status);
5760
5761         if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS)
5762                 ufshcd_bkops_exception_event_handler(hba);
5763
5764         ufs_debugfs_exception_event(hba, status);
5765 out:
5766         ufshcd_scsi_unblock_requests(hba);
5767         return;
5768 }
5769
5770 /* Complete requests that have door-bell cleared */
5771 static void ufshcd_complete_requests(struct ufs_hba *hba)
5772 {
5773         ufshcd_transfer_req_compl(hba);
5774         ufshcd_tmc_handler(hba);
5775 }
5776
5777 /**
5778  * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
5779  *                              to recover from the DL NAC errors or not.
5780  * @hba: per-adapter instance
5781  *
5782  * Returns true if error handling is required, false otherwise
5783  */
5784 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5785 {
5786         unsigned long flags;
5787         bool err_handling = true;
5788
5789         spin_lock_irqsave(hba->host->host_lock, flags);
5790         /*
5791          * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
5792          * device fatal error and/or DL NAC & REPLAY timeout errors.
5793          */
5794         if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5795                 goto out;
5796
5797         if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5798             ((hba->saved_err & UIC_ERROR) &&
5799              (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5800                 goto out;
5801
5802         if ((hba->saved_err & UIC_ERROR) &&
5803             (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5804                 int err;
5805                 /*
5806                  * wait for 50ms to see if we can get any other errors or not.
5807                  */
5808                 spin_unlock_irqrestore(hba->host->host_lock, flags);
5809                 msleep(50);
5810                 spin_lock_irqsave(hba->host->host_lock, flags);
5811
5812                 /*
5813                  * now check if we have got any other severe errors other than
5814                  * DL NAC error?
5815                  */
5816                 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5817                     ((hba->saved_err & UIC_ERROR) &&
5818                     (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
5819                         goto out;
5820
5821                 /*
5822                  * As DL NAC is the only error received so far, send out NOP
5823                  * command to confirm if link is still active or not.
5824                  *   - If we don't get any response then do error recovery.
5825                  *   - If we get response then clear the DL NAC error bit.
5826                  */
5827
5828                 spin_unlock_irqrestore(hba->host->host_lock, flags);
5829                 err = ufshcd_verify_dev_init(hba);
5830                 spin_lock_irqsave(hba->host->host_lock, flags);
5831
5832                 if (err)
5833                         goto out;
5834
5835                 /* Link seems to be alive hence ignore the DL NAC errors */
5836                 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5837                         hba->saved_err &= ~UIC_ERROR;
5838                 /* clear NAC error */
5839                 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5840                 if (!hba->saved_uic_err)
5841                         err_handling = false;
5842         }
5843 out:
5844         spin_unlock_irqrestore(hba->host->host_lock, flags);
5845         return err_handling;
5846 }
5847
5848 /* host lock must be held before calling this func */
5849 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba)
5850 {
5851         return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
5852                (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK));
5853 }
5854
5855 /* host lock must be held before calling this func */
5856 static inline void ufshcd_schedule_eh_work(struct ufs_hba *hba)
5857 {
5858         /* handle fatal errors only when link is not in error state */
5859         if (hba->ufshcd_state != UFSHCD_STATE_ERROR) {
5860                 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
5861                     ufshcd_is_saved_err_fatal(hba))
5862                         hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL;
5863                 else
5864                         hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL;
5865                 queue_work(hba->eh_wq, &hba->eh_work);
5866         }
5867 }
5868
5869 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow)
5870 {
5871         down_write(&hba->clk_scaling_lock);
5872         hba->clk_scaling.is_allowed = allow;
5873         up_write(&hba->clk_scaling_lock);
5874 }
5875
5876 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend)
5877 {
5878         if (suspend) {
5879                 if (hba->clk_scaling.is_enabled)
5880                         ufshcd_suspend_clkscaling(hba);
5881                 ufshcd_clk_scaling_allow(hba, false);
5882         } else {
5883                 ufshcd_clk_scaling_allow(hba, true);
5884                 if (hba->clk_scaling.is_enabled)
5885                         ufshcd_resume_clkscaling(hba);
5886         }
5887 }
5888
5889 static void ufshcd_err_handling_prepare(struct ufs_hba *hba)
5890 {
5891         ufshcd_rpm_get_sync(hba);
5892         if (pm_runtime_status_suspended(&hba->sdev_ufs_device->sdev_gendev) ||
5893             hba->is_sys_suspended) {
5894                 enum ufs_pm_op pm_op;
5895
5896                 /*
5897                  * Don't assume anything of resume, if
5898                  * resume fails, irq and clocks can be OFF, and powers
5899                  * can be OFF or in LPM.
5900                  */
5901                 ufshcd_setup_hba_vreg(hba, true);
5902                 ufshcd_enable_irq(hba);
5903                 ufshcd_setup_vreg(hba, true);
5904                 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
5905                 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
5906                 ufshcd_hold(hba, false);
5907                 if (!ufshcd_is_clkgating_allowed(hba))
5908                         ufshcd_setup_clocks(hba, true);
5909                 ufshcd_release(hba);
5910                 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM;
5911                 ufshcd_vops_resume(hba, pm_op);
5912         } else {
5913                 ufshcd_hold(hba, false);
5914                 if (ufshcd_is_clkscaling_supported(hba) &&
5915                     hba->clk_scaling.is_enabled)
5916                         ufshcd_suspend_clkscaling(hba);
5917                 ufshcd_clk_scaling_allow(hba, false);
5918         }
5919         ufshcd_scsi_block_requests(hba);
5920         /* Drain ufshcd_queuecommand() */
5921         down_write(&hba->clk_scaling_lock);
5922         up_write(&hba->clk_scaling_lock);
5923         cancel_work_sync(&hba->eeh_work);
5924 }
5925
5926 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba)
5927 {
5928         ufshcd_scsi_unblock_requests(hba);
5929         ufshcd_release(hba);
5930         if (ufshcd_is_clkscaling_supported(hba))
5931                 ufshcd_clk_scaling_suspend(hba, false);
5932         ufshcd_clear_ua_wluns(hba);
5933         ufshcd_rpm_put(hba);
5934 }
5935
5936 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba)
5937 {
5938         return (!hba->is_powered || hba->shutting_down ||
5939                 !hba->sdev_ufs_device ||
5940                 hba->ufshcd_state == UFSHCD_STATE_ERROR ||
5941                 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset ||
5942                    ufshcd_is_link_broken(hba))));
5943 }
5944
5945 #ifdef CONFIG_PM
5946 static void ufshcd_recover_pm_error(struct ufs_hba *hba)
5947 {
5948         struct Scsi_Host *shost = hba->host;
5949         struct scsi_device *sdev;
5950         struct request_queue *q;
5951         int ret;
5952
5953         hba->is_sys_suspended = false;
5954         /*
5955          * Set RPM status of wlun device to RPM_ACTIVE,
5956          * this also clears its runtime error.
5957          */
5958         ret = pm_runtime_set_active(&hba->sdev_ufs_device->sdev_gendev);
5959
5960         /* hba device might have a runtime error otherwise */
5961         if (ret)
5962                 ret = pm_runtime_set_active(hba->dev);
5963         /*
5964          * If wlun device had runtime error, we also need to resume those
5965          * consumer scsi devices in case any of them has failed to be
5966          * resumed due to supplier runtime resume failure. This is to unblock
5967          * blk_queue_enter in case there are bios waiting inside it.
5968          */
5969         if (!ret) {
5970                 shost_for_each_device(sdev, shost) {
5971                         q = sdev->request_queue;
5972                         if (q->dev && (q->rpm_status == RPM_SUSPENDED ||
5973                                        q->rpm_status == RPM_SUSPENDING))
5974                                 pm_request_resume(q->dev);
5975                 }
5976         }
5977 }
5978 #else
5979 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba)
5980 {
5981 }
5982 #endif
5983
5984 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba)
5985 {
5986         struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info;
5987         u32 mode;
5988
5989         ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode);
5990
5991         if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK))
5992                 return true;
5993
5994         if (pwr_info->pwr_tx != (mode & PWRMODE_MASK))
5995                 return true;
5996
5997         return false;
5998 }
5999
6000 /**
6001  * ufshcd_err_handler - handle UFS errors that require s/w attention
6002  * @work: pointer to work structure
6003  */
6004 static void ufshcd_err_handler(struct work_struct *work)
6005 {
6006         struct ufs_hba *hba;
6007         unsigned long flags;
6008         bool err_xfer = false;
6009         bool err_tm = false;
6010         int err = 0, pmc_err;
6011         int tag;
6012         bool needs_reset = false, needs_restore = false;
6013
6014         hba = container_of(work, struct ufs_hba, eh_work);
6015
6016         down(&hba->host_sem);
6017         spin_lock_irqsave(hba->host->host_lock, flags);
6018         if (ufshcd_err_handling_should_stop(hba)) {
6019                 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6020                         hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6021                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6022                 up(&hba->host_sem);
6023                 return;
6024         }
6025         ufshcd_set_eh_in_progress(hba);
6026         spin_unlock_irqrestore(hba->host->host_lock, flags);
6027         ufshcd_err_handling_prepare(hba);
6028         /* Complete requests that have door-bell cleared by h/w */
6029         ufshcd_complete_requests(hba);
6030         spin_lock_irqsave(hba->host->host_lock, flags);
6031         if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6032                 hba->ufshcd_state = UFSHCD_STATE_RESET;
6033         /*
6034          * A full reset and restore might have happened after preparation
6035          * is finished, double check whether we should stop.
6036          */
6037         if (ufshcd_err_handling_should_stop(hba))
6038                 goto skip_err_handling;
6039
6040         if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6041                 bool ret;
6042
6043                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6044                 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
6045                 ret = ufshcd_quirk_dl_nac_errors(hba);
6046                 spin_lock_irqsave(hba->host->host_lock, flags);
6047                 if (!ret && ufshcd_err_handling_should_stop(hba))
6048                         goto skip_err_handling;
6049         }
6050
6051         if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6052             (hba->saved_uic_err &&
6053              (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6054                 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR);
6055
6056                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6057                 ufshcd_print_host_state(hba);
6058                 ufshcd_print_pwr_info(hba);
6059                 ufshcd_print_evt_hist(hba);
6060                 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
6061                 ufshcd_print_trs(hba, hba->outstanding_reqs, pr_prdt);
6062                 spin_lock_irqsave(hba->host->host_lock, flags);
6063         }
6064
6065         /*
6066          * if host reset is required then skip clearing the pending
6067          * transfers forcefully because they will get cleared during
6068          * host reset and restore
6069          */
6070         if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6071             ufshcd_is_saved_err_fatal(hba) ||
6072             ((hba->saved_err & UIC_ERROR) &&
6073              (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
6074                                     UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) {
6075                 needs_reset = true;
6076                 goto do_reset;
6077         }
6078
6079         /*
6080          * If LINERESET was caught, UFS might have been put to PWM mode,
6081          * check if power mode restore is needed.
6082          */
6083         if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) {
6084                 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6085                 if (!hba->saved_uic_err)
6086                         hba->saved_err &= ~UIC_ERROR;
6087                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6088                 if (ufshcd_is_pwr_mode_restore_needed(hba))
6089                         needs_restore = true;
6090                 spin_lock_irqsave(hba->host->host_lock, flags);
6091                 if (!hba->saved_err && !needs_restore)
6092                         goto skip_err_handling;
6093         }
6094
6095         hba->silence_err_logs = true;
6096         /* release lock as clear command might sleep */
6097         spin_unlock_irqrestore(hba->host->host_lock, flags);
6098         /* Clear pending transfer requests */
6099         for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
6100                 if (ufshcd_try_to_abort_task(hba, tag)) {
6101                         err_xfer = true;
6102                         goto lock_skip_pending_xfer_clear;
6103                 }
6104         }
6105
6106         /* Clear pending task management requests */
6107         for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
6108                 if (ufshcd_clear_tm_cmd(hba, tag)) {
6109                         err_tm = true;
6110                         goto lock_skip_pending_xfer_clear;
6111                 }
6112         }
6113
6114 lock_skip_pending_xfer_clear:
6115         /* Complete the requests that are cleared by s/w */
6116         ufshcd_complete_requests(hba);
6117
6118         spin_lock_irqsave(hba->host->host_lock, flags);
6119         hba->silence_err_logs = false;
6120         if (err_xfer || err_tm) {
6121                 needs_reset = true;
6122                 goto do_reset;
6123         }
6124
6125         /*
6126          * After all reqs and tasks are cleared from doorbell,
6127          * now it is safe to retore power mode.
6128          */
6129         if (needs_restore) {
6130                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6131                 /*
6132                  * Hold the scaling lock just in case dev cmds
6133                  * are sent via bsg and/or sysfs.
6134                  */
6135                 down_write(&hba->clk_scaling_lock);
6136                 hba->force_pmc = true;
6137                 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info));
6138                 if (pmc_err) {
6139                         needs_reset = true;
6140                         dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n",
6141                                         __func__, pmc_err);
6142                 }
6143                 hba->force_pmc = false;
6144                 ufshcd_print_pwr_info(hba);
6145                 up_write(&hba->clk_scaling_lock);
6146                 spin_lock_irqsave(hba->host->host_lock, flags);
6147         }
6148
6149 do_reset:
6150         /* Fatal errors need reset */
6151         if (needs_reset) {
6152                 hba->force_reset = false;
6153                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6154                 err = ufshcd_reset_and_restore(hba);
6155                 if (err)
6156                         dev_err(hba->dev, "%s: reset and restore failed with err %d\n",
6157                                         __func__, err);
6158                 else
6159                         ufshcd_recover_pm_error(hba);
6160                 spin_lock_irqsave(hba->host->host_lock, flags);
6161         }
6162
6163 skip_err_handling:
6164         if (!needs_reset) {
6165                 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
6166                         hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6167                 if (hba->saved_err || hba->saved_uic_err)
6168                         dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
6169                             __func__, hba->saved_err, hba->saved_uic_err);
6170         }
6171         ufshcd_clear_eh_in_progress(hba);
6172         spin_unlock_irqrestore(hba->host->host_lock, flags);
6173         ufshcd_err_handling_unprepare(hba);
6174         up(&hba->host_sem);
6175 }
6176
6177 /**
6178  * ufshcd_update_uic_error - check and set fatal UIC error flags.
6179  * @hba: per-adapter instance
6180  *
6181  * Returns
6182  *  IRQ_HANDLED - If interrupt is valid
6183  *  IRQ_NONE    - If invalid interrupt
6184  */
6185 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
6186 {
6187         u32 reg;
6188         irqreturn_t retval = IRQ_NONE;
6189
6190         /* PHY layer error */
6191         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
6192         if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
6193             (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) {
6194                 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg);
6195                 /*
6196                  * To know whether this error is fatal or not, DB timeout
6197                  * must be checked but this error is handled separately.
6198                  */
6199                 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)
6200                         dev_dbg(hba->dev, "%s: UIC Lane error reported\n",
6201                                         __func__);
6202
6203                 /* Got a LINERESET indication. */
6204                 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) {
6205                         struct uic_command *cmd = NULL;
6206
6207                         hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR;
6208                         if (hba->uic_async_done && hba->active_uic_cmd)
6209                                 cmd = hba->active_uic_cmd;
6210                         /*
6211                          * Ignore the LINERESET during power mode change
6212                          * operation via DME_SET command.
6213                          */
6214                         if (cmd && (cmd->command == UIC_CMD_DME_SET))
6215                                 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6216                 }
6217                 retval |= IRQ_HANDLED;
6218         }
6219
6220         /* PA_INIT_ERROR is fatal and needs UIC reset */
6221         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
6222         if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
6223             (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
6224                 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg);
6225
6226                 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
6227                         hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
6228                 else if (hba->dev_quirks &
6229                                 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6230                         if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
6231                                 hba->uic_error |=
6232                                         UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6233                         else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
6234                                 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
6235                 }
6236                 retval |= IRQ_HANDLED;
6237         }
6238
6239         /* UIC NL/TL/DME errors needs software retry */
6240         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
6241         if ((reg & UIC_NETWORK_LAYER_ERROR) &&
6242             (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
6243                 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg);
6244                 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
6245                 retval |= IRQ_HANDLED;
6246         }
6247
6248         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
6249         if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
6250             (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
6251                 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg);
6252                 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
6253                 retval |= IRQ_HANDLED;
6254         }
6255
6256         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
6257         if ((reg & UIC_DME_ERROR) &&
6258             (reg & UIC_DME_ERROR_CODE_MASK)) {
6259                 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg);
6260                 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
6261                 retval |= IRQ_HANDLED;
6262         }
6263
6264         dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
6265                         __func__, hba->uic_error);
6266         return retval;
6267 }
6268
6269 /**
6270  * ufshcd_check_errors - Check for errors that need s/w attention
6271  * @hba: per-adapter instance
6272  * @intr_status: interrupt status generated by the controller
6273  *
6274  * Returns
6275  *  IRQ_HANDLED - If interrupt is valid
6276  *  IRQ_NONE    - If invalid interrupt
6277  */
6278 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status)
6279 {
6280         bool queue_eh_work = false;
6281         irqreturn_t retval = IRQ_NONE;
6282
6283         spin_lock(hba->host->host_lock);
6284         hba->errors |= UFSHCD_ERROR_MASK & intr_status;
6285
6286         if (hba->errors & INT_FATAL_ERRORS) {
6287                 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR,
6288                                        hba->errors);
6289                 queue_eh_work = true;
6290         }
6291
6292         if (hba->errors & UIC_ERROR) {
6293                 hba->uic_error = 0;
6294                 retval = ufshcd_update_uic_error(hba);
6295                 if (hba->uic_error)
6296                         queue_eh_work = true;
6297         }
6298
6299         if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
6300                 dev_err(hba->dev,
6301                         "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
6302                         __func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
6303                         "Enter" : "Exit",
6304                         hba->errors, ufshcd_get_upmcrs(hba));
6305                 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR,
6306                                        hba->errors);
6307                 ufshcd_set_link_broken(hba);
6308                 queue_eh_work = true;
6309         }
6310
6311         if (queue_eh_work) {
6312                 /*
6313                  * update the transfer error masks to sticky bits, let's do this
6314                  * irrespective of current ufshcd_state.
6315                  */
6316                 hba->saved_err |= hba->errors;
6317                 hba->saved_uic_err |= hba->uic_error;
6318
6319                 /* dump controller state before resetting */
6320                 if ((hba->saved_err &
6321                      (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6322                     (hba->saved_uic_err &&
6323                      (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6324                         dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
6325                                         __func__, hba->saved_err,
6326                                         hba->saved_uic_err);
6327                         ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE,
6328                                          "host_regs: ");
6329                         ufshcd_print_pwr_info(hba);
6330                 }
6331                 ufshcd_schedule_eh_work(hba);
6332                 retval |= IRQ_HANDLED;
6333         }
6334         /*
6335          * if (!queue_eh_work) -
6336          * Other errors are either non-fatal where host recovers
6337          * itself without s/w intervention or errors that will be
6338          * handled by the SCSI core layer.
6339          */
6340         hba->errors = 0;
6341         hba->uic_error = 0;
6342         spin_unlock(hba->host->host_lock);
6343         return retval;
6344 }
6345
6346 struct ctm_info {
6347         struct ufs_hba  *hba;
6348         unsigned long   pending;
6349         unsigned int    ncpl;
6350 };
6351
6352 static bool ufshcd_compl_tm(struct request *req, void *priv, bool reserved)
6353 {
6354         struct ctm_info *const ci = priv;
6355         struct completion *c;
6356
6357         WARN_ON_ONCE(reserved);
6358         if (test_bit(req->tag, &ci->pending))
6359                 return true;
6360         ci->ncpl++;
6361         c = req->end_io_data;
6362         if (c)
6363                 complete(c);
6364         return true;
6365 }
6366
6367 /**
6368  * ufshcd_tmc_handler - handle task management function completion
6369  * @hba: per adapter instance
6370  *
6371  * Returns
6372  *  IRQ_HANDLED - If interrupt is valid
6373  *  IRQ_NONE    - If invalid interrupt
6374  */
6375 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
6376 {
6377         unsigned long flags;
6378         struct request_queue *q = hba->tmf_queue;
6379         struct ctm_info ci = {
6380                 .hba     = hba,
6381         };
6382
6383         spin_lock_irqsave(hba->host->host_lock, flags);
6384         ci.pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
6385         blk_mq_tagset_busy_iter(q->tag_set, ufshcd_compl_tm, &ci);
6386         spin_unlock_irqrestore(hba->host->host_lock, flags);
6387
6388         return ci.ncpl ? IRQ_HANDLED : IRQ_NONE;
6389 }
6390
6391 /**
6392  * ufshcd_sl_intr - Interrupt service routine
6393  * @hba: per adapter instance
6394  * @intr_status: contains interrupts generated by the controller
6395  *
6396  * Returns
6397  *  IRQ_HANDLED - If interrupt is valid
6398  *  IRQ_NONE    - If invalid interrupt
6399  */
6400 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
6401 {
6402         irqreturn_t retval = IRQ_NONE;
6403
6404         if (intr_status & UFSHCD_UIC_MASK)
6405                 retval |= ufshcd_uic_cmd_compl(hba, intr_status);
6406
6407         if (intr_status & UFSHCD_ERROR_MASK || hba->errors)
6408                 retval |= ufshcd_check_errors(hba, intr_status);
6409
6410         if (intr_status & UTP_TASK_REQ_COMPL)
6411                 retval |= ufshcd_tmc_handler(hba);
6412
6413         if (intr_status & UTP_TRANSFER_REQ_COMPL)
6414                 retval |= ufshcd_transfer_req_compl(hba);
6415
6416         return retval;
6417 }
6418
6419 /**
6420  * ufshcd_intr - Main interrupt service routine
6421  * @irq: irq number
6422  * @__hba: pointer to adapter instance
6423  *
6424  * Returns
6425  *  IRQ_HANDLED - If interrupt is valid
6426  *  IRQ_NONE    - If invalid interrupt
6427  */
6428 static irqreturn_t ufshcd_intr(int irq, void *__hba)
6429 {
6430         u32 intr_status, enabled_intr_status = 0;
6431         irqreturn_t retval = IRQ_NONE;
6432         struct ufs_hba *hba = __hba;
6433         int retries = hba->nutrs;
6434
6435         intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6436         hba->ufs_stats.last_intr_status = intr_status;
6437         hba->ufs_stats.last_intr_ts = ktime_get();
6438
6439         /*
6440          * There could be max of hba->nutrs reqs in flight and in worst case
6441          * if the reqs get finished 1 by 1 after the interrupt status is
6442          * read, make sure we handle them by checking the interrupt status
6443          * again in a loop until we process all of the reqs before returning.
6444          */
6445         while (intr_status && retries--) {
6446                 enabled_intr_status =
6447                         intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
6448                 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
6449                 if (enabled_intr_status)
6450                         retval |= ufshcd_sl_intr(hba, enabled_intr_status);
6451
6452                 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6453         }
6454
6455         if (enabled_intr_status && retval == IRQ_NONE &&
6456             (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) ||
6457              hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) {
6458                 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n",
6459                                         __func__,
6460                                         intr_status,
6461                                         hba->ufs_stats.last_intr_status,
6462                                         enabled_intr_status);
6463                 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
6464         }
6465
6466         return retval;
6467 }
6468
6469 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
6470 {
6471         int err = 0;
6472         u32 mask = 1 << tag;
6473         unsigned long flags;
6474
6475         if (!test_bit(tag, &hba->outstanding_tasks))
6476                 goto out;
6477
6478         spin_lock_irqsave(hba->host->host_lock, flags);
6479         ufshcd_utmrl_clear(hba, tag);
6480         spin_unlock_irqrestore(hba->host->host_lock, flags);
6481
6482         /* poll for max. 1 sec to clear door bell register by h/w */
6483         err = ufshcd_wait_for_register(hba,
6484                         REG_UTP_TASK_REQ_DOOR_BELL,
6485                         mask, 0, 1000, 1000);
6486 out:
6487         return err;
6488 }
6489
6490 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
6491                 struct utp_task_req_desc *treq, u8 tm_function)
6492 {
6493         struct request_queue *q = hba->tmf_queue;
6494         struct Scsi_Host *host = hba->host;
6495         DECLARE_COMPLETION_ONSTACK(wait);
6496         struct request *req;
6497         unsigned long flags;
6498         int task_tag, err;
6499
6500         /*
6501          * blk_get_request() is used here only to get a free tag.
6502          */
6503         req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
6504         if (IS_ERR(req))
6505                 return PTR_ERR(req);
6506
6507         req->end_io_data = &wait;
6508         ufshcd_hold(hba, false);
6509
6510         spin_lock_irqsave(host->host_lock, flags);
6511         blk_mq_start_request(req);
6512
6513         task_tag = req->tag;
6514         treq->upiu_req.req_header.dword_0 |= cpu_to_be32(task_tag);
6515
6516         memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq));
6517         ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function);
6518
6519         /* send command to the controller */
6520         __set_bit(task_tag, &hba->outstanding_tasks);
6521
6522         ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL);
6523         /* Make sure that doorbell is committed immediately */
6524         wmb();
6525
6526         spin_unlock_irqrestore(host->host_lock, flags);
6527
6528         ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND);
6529
6530         /* wait until the task management command is completed */
6531         err = wait_for_completion_io_timeout(&wait,
6532                         msecs_to_jiffies(TM_CMD_TIMEOUT));
6533         if (!err) {
6534                 /*
6535                  * Make sure that ufshcd_compl_tm() does not trigger a
6536                  * use-after-free.
6537                  */
6538                 req->end_io_data = NULL;
6539                 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR);
6540                 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
6541                                 __func__, tm_function);
6542                 if (ufshcd_clear_tm_cmd(hba, task_tag))
6543                         dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n",
6544                                         __func__, task_tag);
6545                 err = -ETIMEDOUT;
6546         } else {
6547                 err = 0;
6548                 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq));
6549
6550                 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP);
6551         }
6552
6553         spin_lock_irqsave(hba->host->host_lock, flags);
6554         __clear_bit(task_tag, &hba->outstanding_tasks);
6555         spin_unlock_irqrestore(hba->host->host_lock, flags);
6556
6557         ufshcd_release(hba);
6558         blk_put_request(req);
6559
6560         return err;
6561 }
6562
6563 /**
6564  * ufshcd_issue_tm_cmd - issues task management commands to controller
6565  * @hba: per adapter instance
6566  * @lun_id: LUN ID to which TM command is sent
6567  * @task_id: task ID to which the TM command is applicable
6568  * @tm_function: task management function opcode
6569  * @tm_response: task management service response return value
6570  *
6571  * Returns non-zero value on error, zero on success.
6572  */
6573 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
6574                 u8 tm_function, u8 *tm_response)
6575 {
6576         struct utp_task_req_desc treq = { { 0 }, };
6577         int ocs_value, err;
6578
6579         /* Configure task request descriptor */
6580         treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6581         treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6582
6583         /* Configure task request UPIU */
6584         treq.upiu_req.req_header.dword_0 = cpu_to_be32(lun_id << 8) |
6585                                   cpu_to_be32(UPIU_TRANSACTION_TASK_REQ << 24);
6586         treq.upiu_req.req_header.dword_1 = cpu_to_be32(tm_function << 16);
6587
6588         /*
6589          * The host shall provide the same value for LUN field in the basic
6590          * header and for Input Parameter.
6591          */
6592         treq.upiu_req.input_param1 = cpu_to_be32(lun_id);
6593         treq.upiu_req.input_param2 = cpu_to_be32(task_id);
6594
6595         err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
6596         if (err == -ETIMEDOUT)
6597                 return err;
6598
6599         ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6600         if (ocs_value != OCS_SUCCESS)
6601                 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
6602                                 __func__, ocs_value);
6603         else if (tm_response)
6604                 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) &
6605                                 MASK_TM_SERVICE_RESP;
6606         return err;
6607 }
6608
6609 /**
6610  * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
6611  * @hba:        per-adapter instance
6612  * @req_upiu:   upiu request
6613  * @rsp_upiu:   upiu reply
6614  * @desc_buff:  pointer to descriptor buffer, NULL if NA
6615  * @buff_len:   descriptor size, 0 if NA
6616  * @cmd_type:   specifies the type (NOP, Query...)
6617  * @desc_op:    descriptor operation
6618  *
6619  * Those type of requests uses UTP Transfer Request Descriptor - utrd.
6620  * Therefore, it "rides" the device management infrastructure: uses its tag and
6621  * tasks work queues.
6622  *
6623  * Since there is only one available tag for device management commands,
6624  * the caller is expected to hold the hba->dev_cmd.lock mutex.
6625  */
6626 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
6627                                         struct utp_upiu_req *req_upiu,
6628                                         struct utp_upiu_req *rsp_upiu,
6629                                         u8 *desc_buff, int *buff_len,
6630                                         enum dev_cmd_type cmd_type,
6631                                         enum query_opcode desc_op)
6632 {
6633         struct request_queue *q = hba->cmd_queue;
6634         DECLARE_COMPLETION_ONSTACK(wait);
6635         struct request *req;
6636         struct ufshcd_lrb *lrbp;
6637         int err = 0;
6638         int tag;
6639         u8 upiu_flags;
6640
6641         down_read(&hba->clk_scaling_lock);
6642
6643         req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
6644         if (IS_ERR(req)) {
6645                 err = PTR_ERR(req);
6646                 goto out_unlock;
6647         }
6648         tag = req->tag;
6649         WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
6650
6651         if (unlikely(test_bit(tag, &hba->outstanding_reqs))) {
6652                 err = -EBUSY;
6653                 goto out;
6654         }
6655
6656         lrbp = &hba->lrb[tag];
6657         WARN_ON(lrbp->cmd);
6658         lrbp->cmd = NULL;
6659         lrbp->sense_bufflen = 0;
6660         lrbp->sense_buffer = NULL;
6661         lrbp->task_tag = tag;
6662         lrbp->lun = 0;
6663         lrbp->intr_cmd = true;
6664         ufshcd_prepare_lrbp_crypto(NULL, lrbp);
6665         hba->dev_cmd.type = cmd_type;
6666
6667         if (hba->ufs_version <= ufshci_version(1, 1))
6668                 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
6669         else
6670                 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
6671
6672         /* update the task tag in the request upiu */
6673         req_upiu->header.dword_0 |= cpu_to_be32(tag);
6674
6675         ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
6676
6677         /* just copy the upiu request as it is */
6678         memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
6679         if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
6680                 /* The Data Segment Area is optional depending upon the query
6681                  * function value. for WRITE DESCRIPTOR, the data segment
6682                  * follows right after the tsf.
6683                  */
6684                 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
6685                 *buff_len = 0;
6686         }
6687
6688         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
6689
6690         hba->dev_cmd.complete = &wait;
6691
6692         ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
6693
6694         ufshcd_send_command(hba, tag);
6695         /*
6696          * ignore the returning value here - ufshcd_check_query_response is
6697          * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
6698          * read the response directly ignoring all errors.
6699          */
6700         ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
6701
6702         /* just copy the upiu response as it is */
6703         memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
6704         if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
6705                 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
6706                 u16 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
6707                                MASK_QUERY_DATA_SEG_LEN;
6708
6709                 if (*buff_len >= resp_len) {
6710                         memcpy(desc_buff, descp, resp_len);
6711                         *buff_len = resp_len;
6712                 } else {
6713                         dev_warn(hba->dev,
6714                                  "%s: rsp size %d is bigger than buffer size %d",
6715                                  __func__, resp_len, *buff_len);
6716                         *buff_len = 0;
6717                         err = -EINVAL;
6718                 }
6719         }
6720         ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
6721                                     (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
6722
6723 out:
6724         blk_put_request(req);
6725 out_unlock:
6726         up_read(&hba->clk_scaling_lock);
6727         return err;
6728 }
6729
6730 /**
6731  * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
6732  * @hba:        per-adapter instance
6733  * @req_upiu:   upiu request
6734  * @rsp_upiu:   upiu reply - only 8 DW as we do not support scsi commands
6735  * @msgcode:    message code, one of UPIU Transaction Codes Initiator to Target
6736  * @desc_buff:  pointer to descriptor buffer, NULL if NA
6737  * @buff_len:   descriptor size, 0 if NA
6738  * @desc_op:    descriptor operation
6739  *
6740  * Supports UTP Transfer requests (nop and query), and UTP Task
6741  * Management requests.
6742  * It is up to the caller to fill the upiu conent properly, as it will
6743  * be copied without any further input validations.
6744  */
6745 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
6746                              struct utp_upiu_req *req_upiu,
6747                              struct utp_upiu_req *rsp_upiu,
6748                              int msgcode,
6749                              u8 *desc_buff, int *buff_len,
6750                              enum query_opcode desc_op)
6751 {
6752         int err;
6753         enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
6754         struct utp_task_req_desc treq = { { 0 }, };
6755         int ocs_value;
6756         u8 tm_f = be32_to_cpu(req_upiu->header.dword_1) >> 16 & MASK_TM_FUNC;
6757
6758         switch (msgcode) {
6759         case UPIU_TRANSACTION_NOP_OUT:
6760                 cmd_type = DEV_CMD_TYPE_NOP;
6761                 fallthrough;
6762         case UPIU_TRANSACTION_QUERY_REQ:
6763                 ufshcd_hold(hba, false);
6764                 mutex_lock(&hba->dev_cmd.lock);
6765                 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
6766                                                    desc_buff, buff_len,
6767                                                    cmd_type, desc_op);
6768                 mutex_unlock(&hba->dev_cmd.lock);
6769                 ufshcd_release(hba);
6770
6771                 break;
6772         case UPIU_TRANSACTION_TASK_REQ:
6773                 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6774                 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6775
6776                 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu));
6777
6778                 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
6779                 if (err == -ETIMEDOUT)
6780                         break;
6781
6782                 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6783                 if (ocs_value != OCS_SUCCESS) {
6784                         dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
6785                                 ocs_value);
6786                         break;
6787                 }
6788
6789                 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu));
6790
6791                 break;
6792         default:
6793                 err = -EINVAL;
6794
6795                 break;
6796         }
6797
6798         return err;
6799 }
6800
6801 /**
6802  * ufshcd_eh_device_reset_handler - device reset handler registered to
6803  *                                    scsi layer.
6804  * @cmd: SCSI command pointer
6805  *
6806  * Returns SUCCESS/FAILED
6807  */
6808 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
6809 {
6810         struct Scsi_Host *host;
6811         struct ufs_hba *hba;
6812         u32 pos;
6813         int err;
6814         u8 resp = 0xF, lun;
6815
6816         host = cmd->device->host;
6817         hba = shost_priv(host);
6818
6819         lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
6820         err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp);
6821         if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6822                 if (!err)
6823                         err = resp;
6824                 goto out;
6825         }
6826
6827         /* clear the commands that were pending for corresponding LUN */
6828         for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
6829                 if (hba->lrb[pos].lun == lun) {
6830                         err = ufshcd_clear_cmd(hba, pos);
6831                         if (err)
6832                                 break;
6833                         __ufshcd_transfer_req_compl(hba, pos);
6834                 }
6835         }
6836
6837 out:
6838         hba->req_abort_count = 0;
6839         ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err);
6840         if (!err) {
6841                 err = SUCCESS;
6842         } else {
6843                 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
6844                 err = FAILED;
6845         }
6846         return err;
6847 }
6848
6849 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
6850 {
6851         struct ufshcd_lrb *lrbp;
6852         int tag;
6853
6854         for_each_set_bit(tag, &bitmap, hba->nutrs) {
6855                 lrbp = &hba->lrb[tag];
6856                 lrbp->req_abort_skip = true;
6857         }
6858 }
6859
6860 /**
6861  * ufshcd_try_to_abort_task - abort a specific task
6862  * @hba: Pointer to adapter instance
6863  * @tag: Task tag/index to be aborted
6864  *
6865  * Abort the pending command in device by sending UFS_ABORT_TASK task management
6866  * command, and in host controller by clearing the door-bell register. There can
6867  * be race between controller sending the command to the device while abort is
6868  * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
6869  * really issued and then try to abort it.
6870  *
6871  * Returns zero on success, non-zero on failure
6872  */
6873 static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag)
6874 {
6875         struct ufshcd_lrb *lrbp = &hba->lrb[tag];
6876         int err = 0;
6877         int poll_cnt;
6878         u8 resp = 0xF;
6879         u32 reg;
6880
6881         for (poll_cnt = 100; poll_cnt; poll_cnt--) {
6882                 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6883                                 UFS_QUERY_TASK, &resp);
6884                 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
6885                         /* cmd pending in the device */
6886                         dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
6887                                 __func__, tag);
6888                         break;
6889                 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6890                         /*
6891                          * cmd not pending in the device, check if it is
6892                          * in transition.
6893                          */
6894                         dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
6895                                 __func__, tag);
6896                         reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
6897                         if (reg & (1 << tag)) {
6898                                 /* sleep for max. 200us to stabilize */
6899                                 usleep_range(100, 200);
6900                                 continue;
6901                         }
6902                         /* command completed already */
6903                         dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
6904                                 __func__, tag);
6905                         goto out;
6906                 } else {
6907                         dev_err(hba->dev,
6908                                 "%s: no response from device. tag = %d, err %d\n",
6909                                 __func__, tag, err);
6910                         if (!err)
6911                                 err = resp; /* service response error */
6912                         goto out;
6913                 }
6914         }
6915
6916         if (!poll_cnt) {
6917                 err = -EBUSY;
6918                 goto out;
6919         }
6920
6921         err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6922                         UFS_ABORT_TASK, &resp);
6923         if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6924                 if (!err) {
6925                         err = resp; /* service response error */
6926                         dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
6927                                 __func__, tag, err);
6928                 }
6929                 goto out;
6930         }
6931
6932         err = ufshcd_clear_cmd(hba, tag);
6933         if (err)
6934                 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
6935                         __func__, tag, err);
6936
6937 out:
6938         return err;
6939 }
6940
6941 /**
6942  * ufshcd_abort - scsi host template eh_abort_handler callback
6943  * @cmd: SCSI command pointer
6944  *
6945  * Returns SUCCESS/FAILED
6946  */
6947 static int ufshcd_abort(struct scsi_cmnd *cmd)
6948 {
6949         struct Scsi_Host *host = cmd->device->host;
6950         struct ufs_hba *hba = shost_priv(host);
6951         unsigned int tag = cmd->request->tag;
6952         struct ufshcd_lrb *lrbp = &hba->lrb[tag];
6953         unsigned long flags;
6954         int err = 0;
6955         u32 reg;
6956
6957         WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
6958
6959         ufshcd_hold(hba, false);
6960         reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
6961         /* If command is already aborted/completed, return SUCCESS */
6962         if (!(test_bit(tag, &hba->outstanding_reqs))) {
6963                 dev_err(hba->dev,
6964                         "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
6965                         __func__, tag, hba->outstanding_reqs, reg);
6966                 goto out;
6967         }
6968
6969         /* Print Transfer Request of aborted task */
6970         dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
6971
6972         /*
6973          * Print detailed info about aborted request.
6974          * As more than one request might get aborted at the same time,
6975          * print full information only for the first aborted request in order
6976          * to reduce repeated printouts. For other aborted requests only print
6977          * basic details.
6978          */
6979         scsi_print_command(cmd);
6980         if (!hba->req_abort_count) {
6981                 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag);
6982                 ufshcd_print_evt_hist(hba);
6983                 ufshcd_print_host_state(hba);
6984                 ufshcd_print_pwr_info(hba);
6985                 ufshcd_print_trs(hba, 1 << tag, true);
6986         } else {
6987                 ufshcd_print_trs(hba, 1 << tag, false);
6988         }
6989         hba->req_abort_count++;
6990
6991         if (!(reg & (1 << tag))) {
6992                 dev_err(hba->dev,
6993                 "%s: cmd was completed, but without a notifying intr, tag = %d",
6994                 __func__, tag);
6995                 goto cleanup;
6996         }
6997
6998         /*
6999          * Task abort to the device W-LUN is illegal. When this command
7000          * will fail, due to spec violation, scsi err handling next step
7001          * will be to send LU reset which, again, is a spec violation.
7002          * To avoid these unnecessary/illegal steps, first we clean up
7003          * the lrb taken by this cmd and re-set it in outstanding_reqs,
7004          * then queue the eh_work and bail.
7005          */
7006         if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) {
7007                 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun);
7008                 __ufshcd_transfer_req_compl(hba, (1UL << tag));
7009                 set_bit(tag, &hba->outstanding_reqs);
7010                 spin_lock_irqsave(host->host_lock, flags);
7011                 hba->force_reset = true;
7012                 ufshcd_schedule_eh_work(hba);
7013                 spin_unlock_irqrestore(host->host_lock, flags);
7014                 goto out;
7015         }
7016
7017         /* Skip task abort in case previous aborts failed and report failure */
7018         if (lrbp->req_abort_skip)
7019                 err = -EIO;
7020         else
7021                 err = ufshcd_try_to_abort_task(hba, tag);
7022
7023         if (!err) {
7024 cleanup:
7025                 __ufshcd_transfer_req_compl(hba, (1UL << tag));
7026 out:
7027                 err = SUCCESS;
7028         } else {
7029                 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
7030                 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7031                 err = FAILED;
7032         }
7033
7034         /*
7035          * This ufshcd_release() corresponds to the original scsi cmd that got
7036          * aborted here (as we won't get any IRQ for it).
7037          */
7038         ufshcd_release(hba);
7039         return err;
7040 }
7041
7042 /**
7043  * ufshcd_host_reset_and_restore - reset and restore host controller
7044  * @hba: per-adapter instance
7045  *
7046  * Note that host controller reset may issue DME_RESET to
7047  * local and remote (device) Uni-Pro stack and the attributes
7048  * are reset to default state.
7049  *
7050  * Returns zero on success, non-zero on failure
7051  */
7052 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
7053 {
7054         int err;
7055
7056         /*
7057          * Stop the host controller and complete the requests
7058          * cleared by h/w
7059          */
7060         ufshpb_reset_host(hba);
7061         ufshcd_hba_stop(hba);
7062         hba->silence_err_logs = true;
7063         ufshcd_complete_requests(hba);
7064         hba->silence_err_logs = false;
7065
7066         /* scale up clocks to max frequency before full reinitialization */
7067         ufshcd_set_clk_freq(hba, true);
7068
7069         err = ufshcd_hba_enable(hba);
7070
7071         /* Establish the link again and restore the device */
7072         if (!err)
7073                 err = ufshcd_probe_hba(hba, false);
7074
7075         if (err)
7076                 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
7077         ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err);
7078         return err;
7079 }
7080
7081 /**
7082  * ufshcd_reset_and_restore - reset and re-initialize host/device
7083  * @hba: per-adapter instance
7084  *
7085  * Reset and recover device, host and re-establish link. This
7086  * is helpful to recover the communication in fatal error conditions.
7087  *
7088  * Returns zero on success, non-zero on failure
7089  */
7090 static int ufshcd_reset_and_restore(struct ufs_hba *hba)
7091 {
7092         u32 saved_err;
7093         u32 saved_uic_err;
7094         int err = 0;
7095         unsigned long flags;
7096         int retries = MAX_HOST_RESET_RETRIES;
7097
7098         /*
7099          * This is a fresh start, cache and clear saved error first,
7100          * in case new error generated during reset and restore.
7101          */
7102         spin_lock_irqsave(hba->host->host_lock, flags);
7103         saved_err = hba->saved_err;
7104         saved_uic_err = hba->saved_uic_err;
7105         hba->saved_err = 0;
7106         hba->saved_uic_err = 0;
7107         spin_unlock_irqrestore(hba->host->host_lock, flags);
7108
7109         do {
7110                 /* Reset the attached device */
7111                 ufshcd_device_reset(hba);
7112
7113                 err = ufshcd_host_reset_and_restore(hba);
7114         } while (err && --retries);
7115
7116         spin_lock_irqsave(hba->host->host_lock, flags);
7117         /*
7118          * Inform scsi mid-layer that we did reset and allow to handle
7119          * Unit Attention properly.
7120          */
7121         scsi_report_bus_reset(hba->host, 0);
7122         if (err) {
7123                 hba->ufshcd_state = UFSHCD_STATE_ERROR;
7124                 hba->saved_err |= saved_err;
7125                 hba->saved_uic_err |= saved_uic_err;
7126         }
7127         spin_unlock_irqrestore(hba->host->host_lock, flags);
7128
7129         return err;
7130 }
7131
7132 /**
7133  * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
7134  * @cmd: SCSI command pointer
7135  *
7136  * Returns SUCCESS/FAILED
7137  */
7138 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
7139 {
7140         int err = SUCCESS;
7141         unsigned long flags;
7142         struct ufs_hba *hba;
7143
7144         hba = shost_priv(cmd->device->host);
7145
7146         spin_lock_irqsave(hba->host->host_lock, flags);
7147         hba->force_reset = true;
7148         ufshcd_schedule_eh_work(hba);
7149         dev_err(hba->dev, "%s: reset in progress - 1\n", __func__);
7150         spin_unlock_irqrestore(hba->host->host_lock, flags);
7151
7152         flush_work(&hba->eh_work);
7153
7154         spin_lock_irqsave(hba->host->host_lock, flags);
7155         if (hba->ufshcd_state == UFSHCD_STATE_ERROR)
7156                 err = FAILED;
7157         spin_unlock_irqrestore(hba->host->host_lock, flags);
7158
7159         return err;
7160 }
7161
7162 /**
7163  * ufshcd_get_max_icc_level - calculate the ICC level
7164  * @sup_curr_uA: max. current supported by the regulator
7165  * @start_scan: row at the desc table to start scan from
7166  * @buff: power descriptor buffer
7167  *
7168  * Returns calculated max ICC level for specific regulator
7169  */
7170 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
7171 {
7172         int i;
7173         int curr_uA;
7174         u16 data;
7175         u16 unit;
7176
7177         for (i = start_scan; i >= 0; i--) {
7178                 data = be16_to_cpup((__be16 *)&buff[2 * i]);
7179                 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
7180                                                 ATTR_ICC_LVL_UNIT_OFFSET;
7181                 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
7182                 switch (unit) {
7183                 case UFSHCD_NANO_AMP:
7184                         curr_uA = curr_uA / 1000;
7185                         break;
7186                 case UFSHCD_MILI_AMP:
7187                         curr_uA = curr_uA * 1000;
7188                         break;
7189                 case UFSHCD_AMP:
7190                         curr_uA = curr_uA * 1000 * 1000;
7191                         break;
7192                 case UFSHCD_MICRO_AMP:
7193                 default:
7194                         break;
7195                 }
7196                 if (sup_curr_uA >= curr_uA)
7197                         break;
7198         }
7199         if (i < 0) {
7200                 i = 0;
7201                 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
7202         }
7203
7204         return (u32)i;
7205 }
7206
7207 /**
7208  * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level
7209  * In case regulators are not initialized we'll return 0
7210  * @hba: per-adapter instance
7211  * @desc_buf: power descriptor buffer to extract ICC levels from.
7212  * @len: length of desc_buff
7213  *
7214  * Returns calculated ICC level
7215  */
7216 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
7217                                                         u8 *desc_buf, int len)
7218 {
7219         u32 icc_level = 0;
7220
7221         if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
7222                                                 !hba->vreg_info.vccq2) {
7223                 dev_err(hba->dev,
7224                         "%s: Regulator capability was not set, actvIccLevel=%d",
7225                                                         __func__, icc_level);
7226                 goto out;
7227         }
7228
7229         if (hba->vreg_info.vcc->max_uA)
7230                 icc_level = ufshcd_get_max_icc_level(
7231                                 hba->vreg_info.vcc->max_uA,
7232                                 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
7233                                 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
7234
7235         if (hba->vreg_info.vccq->max_uA)
7236                 icc_level = ufshcd_get_max_icc_level(
7237                                 hba->vreg_info.vccq->max_uA,
7238                                 icc_level,
7239                                 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
7240
7241         if (hba->vreg_info.vccq2->max_uA)
7242                 icc_level = ufshcd_get_max_icc_level(
7243                                 hba->vreg_info.vccq2->max_uA,
7244                                 icc_level,
7245                                 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
7246 out:
7247         return icc_level;
7248 }
7249
7250 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba)
7251 {
7252         int ret;
7253         int buff_len = hba->desc_size[QUERY_DESC_IDN_POWER];
7254         u8 *desc_buf;
7255         u32 icc_level;
7256
7257         desc_buf = kmalloc(buff_len, GFP_KERNEL);
7258         if (!desc_buf)
7259                 return;
7260
7261         ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0,
7262                                      desc_buf, buff_len);
7263         if (ret) {
7264                 dev_err(hba->dev,
7265                         "%s: Failed reading power descriptor.len = %d ret = %d",
7266                         __func__, buff_len, ret);
7267                 goto out;
7268         }
7269
7270         icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf,
7271                                                          buff_len);
7272         dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level);
7273
7274         ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
7275                 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
7276
7277         if (ret)
7278                 dev_err(hba->dev,
7279                         "%s: Failed configuring bActiveICCLevel = %d ret = %d",
7280                         __func__, icc_level, ret);
7281
7282 out:
7283         kfree(desc_buf);
7284 }
7285
7286 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev)
7287 {
7288         scsi_autopm_get_device(sdev);
7289         blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev);
7290         if (sdev->rpm_autosuspend)
7291                 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev,
7292                                                  RPM_AUTOSUSPEND_DELAY_MS);
7293         scsi_autopm_put_device(sdev);
7294 }
7295
7296 /**
7297  * ufshcd_scsi_add_wlus - Adds required W-LUs
7298  * @hba: per-adapter instance
7299  *
7300  * UFS device specification requires the UFS devices to support 4 well known
7301  * logical units:
7302  *      "REPORT_LUNS" (address: 01h)
7303  *      "UFS Device" (address: 50h)
7304  *      "RPMB" (address: 44h)
7305  *      "BOOT" (address: 30h)
7306  * UFS device's power management needs to be controlled by "POWER CONDITION"
7307  * field of SSU (START STOP UNIT) command. But this "power condition" field
7308  * will take effect only when its sent to "UFS device" well known logical unit
7309  * hence we require the scsi_device instance to represent this logical unit in
7310  * order for the UFS host driver to send the SSU command for power management.
7311  *
7312  * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
7313  * Block) LU so user space process can control this LU. User space may also
7314  * want to have access to BOOT LU.
7315  *
7316  * This function adds scsi device instances for each of all well known LUs
7317  * (except "REPORT LUNS" LU).
7318  *
7319  * Returns zero on success (all required W-LUs are added successfully),
7320  * non-zero error value on failure (if failed to add any of the required W-LU).
7321  */
7322 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
7323 {
7324         int ret = 0;
7325         struct scsi_device *sdev_boot;
7326
7327         hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
7328                 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
7329         if (IS_ERR(hba->sdev_ufs_device)) {
7330                 ret = PTR_ERR(hba->sdev_ufs_device);
7331                 hba->sdev_ufs_device = NULL;
7332                 goto out;
7333         }
7334         scsi_device_put(hba->sdev_ufs_device);
7335
7336         hba->sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
7337                 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7338         if (IS_ERR(hba->sdev_rpmb)) {
7339                 ret = PTR_ERR(hba->sdev_rpmb);
7340                 goto remove_sdev_ufs_device;
7341         }
7342         ufshcd_blk_pm_runtime_init(hba->sdev_rpmb);
7343         scsi_device_put(hba->sdev_rpmb);
7344
7345         sdev_boot = __scsi_add_device(hba->host, 0, 0,
7346                 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7347         if (IS_ERR(sdev_boot)) {
7348                 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
7349         } else {
7350                 ufshcd_blk_pm_runtime_init(sdev_boot);
7351                 scsi_device_put(sdev_boot);
7352         }
7353         goto out;
7354
7355 remove_sdev_ufs_device:
7356         scsi_remove_device(hba->sdev_ufs_device);
7357 out:
7358         return ret;
7359 }
7360
7361 static void ufshcd_wb_probe(struct ufs_hba *hba, u8 *desc_buf)
7362 {
7363         struct ufs_dev_info *dev_info = &hba->dev_info;
7364         u8 lun;
7365         u32 d_lu_wb_buf_alloc;
7366         u32 ext_ufs_feature;
7367
7368         if (!ufshcd_is_wb_allowed(hba))
7369                 return;
7370         /*
7371          * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or
7372          * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES
7373          * enabled
7374          */
7375         if (!(dev_info->wspecversion >= 0x310 ||
7376               dev_info->wspecversion == 0x220 ||
7377              (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES)))
7378                 goto wb_disabled;
7379
7380         if (hba->desc_size[QUERY_DESC_IDN_DEVICE] <
7381             DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP + 4)
7382                 goto wb_disabled;
7383
7384         ext_ufs_feature = get_unaligned_be32(desc_buf +
7385                                         DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
7386
7387         if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP))
7388                 goto wb_disabled;
7389
7390         /*
7391          * WB may be supported but not configured while provisioning. The spec
7392          * says, in dedicated wb buffer mode, a max of 1 lun would have wb
7393          * buffer configured.
7394          */
7395         dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE];
7396
7397         dev_info->b_presrv_uspc_en =
7398                 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN];
7399
7400         if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) {
7401                 if (!get_unaligned_be32(desc_buf +
7402                                    DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS))
7403                         goto wb_disabled;
7404         } else {
7405                 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) {
7406                         d_lu_wb_buf_alloc = 0;
7407                         ufshcd_read_unit_desc_param(hba,
7408                                         lun,
7409                                         UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS,
7410                                         (u8 *)&d_lu_wb_buf_alloc,
7411                                         sizeof(d_lu_wb_buf_alloc));
7412                         if (d_lu_wb_buf_alloc) {
7413                                 dev_info->wb_dedicated_lu = lun;
7414                                 break;
7415                         }
7416                 }
7417
7418                 if (!d_lu_wb_buf_alloc)
7419                         goto wb_disabled;
7420         }
7421         return;
7422
7423 wb_disabled:
7424         hba->caps &= ~UFSHCD_CAP_WB_EN;
7425 }
7426
7427 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, struct ufs_dev_fix *fixups)
7428 {
7429         struct ufs_dev_fix *f;
7430         struct ufs_dev_info *dev_info = &hba->dev_info;
7431
7432         if (!fixups)
7433                 return;
7434
7435         for (f = fixups; f->quirk; f++) {
7436                 if ((f->wmanufacturerid == dev_info->wmanufacturerid ||
7437                      f->wmanufacturerid == UFS_ANY_VENDOR) &&
7438                      ((dev_info->model &&
7439                        STR_PRFX_EQUAL(f->model, dev_info->model)) ||
7440                       !strcmp(f->model, UFS_ANY_MODEL)))
7441                         hba->dev_quirks |= f->quirk;
7442         }
7443 }
7444 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks);
7445
7446 static void ufs_fixup_device_setup(struct ufs_hba *hba)
7447 {
7448         /* fix by general quirk table */
7449         ufshcd_fixup_dev_quirks(hba, ufs_fixups);
7450
7451         /* allow vendors to fix quirks */
7452         ufshcd_vops_fixup_dev_quirks(hba);
7453 }
7454
7455 static int ufs_get_device_desc(struct ufs_hba *hba)
7456 {
7457         int err;
7458         u8 model_index;
7459         u8 b_ufs_feature_sup;
7460         u8 *desc_buf;
7461         struct ufs_dev_info *dev_info = &hba->dev_info;
7462
7463         desc_buf = kmalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
7464         if (!desc_buf) {
7465                 err = -ENOMEM;
7466                 goto out;
7467         }
7468
7469         err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf,
7470                                      hba->desc_size[QUERY_DESC_IDN_DEVICE]);
7471         if (err) {
7472                 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
7473                         __func__, err);
7474                 goto out;
7475         }
7476
7477         /*
7478          * getting vendor (manufacturerID) and Bank Index in big endian
7479          * format
7480          */
7481         dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
7482                                      desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
7483
7484         /* getting Specification Version in big endian format */
7485         dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
7486                                       desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
7487         b_ufs_feature_sup = desc_buf[DEVICE_DESC_PARAM_UFS_FEAT];
7488
7489         model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
7490
7491         if (dev_info->wspecversion >= UFS_DEV_HPB_SUPPORT_VERSION &&
7492             (b_ufs_feature_sup & UFS_DEV_HPB_SUPPORT)) {
7493                 bool hpb_en = false;
7494
7495                 ufshpb_get_dev_info(hba, desc_buf);
7496
7497                 if (!ufshpb_is_legacy(hba))
7498                         err = ufshcd_query_flag_retry(hba,
7499                                                       UPIU_QUERY_OPCODE_READ_FLAG,
7500                                                       QUERY_FLAG_IDN_HPB_EN, 0,
7501                                                       &hpb_en);
7502
7503                 if (ufshpb_is_legacy(hba) || (!err && hpb_en))
7504                         dev_info->hpb_enabled = true;
7505         }
7506
7507         err = ufshcd_read_string_desc(hba, model_index,
7508                                       &dev_info->model, SD_ASCII_STD);
7509         if (err < 0) {
7510                 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
7511                         __func__, err);
7512                 goto out;
7513         }
7514
7515         hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] +
7516                 desc_buf[DEVICE_DESC_PARAM_NUM_WLU];
7517
7518         ufs_fixup_device_setup(hba);
7519
7520         ufshcd_wb_probe(hba, desc_buf);
7521
7522         /*
7523          * ufshcd_read_string_desc returns size of the string
7524          * reset the error value
7525          */
7526         err = 0;
7527
7528 out:
7529         kfree(desc_buf);
7530         return err;
7531 }
7532
7533 static void ufs_put_device_desc(struct ufs_hba *hba)
7534 {
7535         struct ufs_dev_info *dev_info = &hba->dev_info;
7536
7537         kfree(dev_info->model);
7538         dev_info->model = NULL;
7539 }
7540
7541 /**
7542  * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
7543  * @hba: per-adapter instance
7544  *
7545  * PA_TActivate parameter can be tuned manually if UniPro version is less than
7546  * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
7547  * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
7548  * the hibern8 exit latency.
7549  *
7550  * Returns zero on success, non-zero error value on failure.
7551  */
7552 static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
7553 {
7554         int ret = 0;
7555         u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
7556
7557         ret = ufshcd_dme_peer_get(hba,
7558                                   UIC_ARG_MIB_SEL(
7559                                         RX_MIN_ACTIVATETIME_CAPABILITY,
7560                                         UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7561                                   &peer_rx_min_activatetime);
7562         if (ret)
7563                 goto out;
7564
7565         /* make sure proper unit conversion is applied */
7566         tuned_pa_tactivate =
7567                 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
7568                  / PA_TACTIVATE_TIME_UNIT_US);
7569         ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7570                              tuned_pa_tactivate);
7571
7572 out:
7573         return ret;
7574 }
7575
7576 /**
7577  * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
7578  * @hba: per-adapter instance
7579  *
7580  * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
7581  * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
7582  * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
7583  * This optimal value can help reduce the hibern8 exit latency.
7584  *
7585  * Returns zero on success, non-zero error value on failure.
7586  */
7587 static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
7588 {
7589         int ret = 0;
7590         u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
7591         u32 max_hibern8_time, tuned_pa_hibern8time;
7592
7593         ret = ufshcd_dme_get(hba,
7594                              UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
7595                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
7596                                   &local_tx_hibern8_time_cap);
7597         if (ret)
7598                 goto out;
7599
7600         ret = ufshcd_dme_peer_get(hba,
7601                                   UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
7602                                         UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7603                                   &peer_rx_hibern8_time_cap);
7604         if (ret)
7605                 goto out;
7606
7607         max_hibern8_time = max(local_tx_hibern8_time_cap,
7608                                peer_rx_hibern8_time_cap);
7609         /* make sure proper unit conversion is applied */
7610         tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
7611                                 / PA_HIBERN8_TIME_UNIT_US);
7612         ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
7613                              tuned_pa_hibern8time);
7614 out:
7615         return ret;
7616 }
7617
7618 /**
7619  * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
7620  * less than device PA_TACTIVATE time.
7621  * @hba: per-adapter instance
7622  *
7623  * Some UFS devices require host PA_TACTIVATE to be lower than device
7624  * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
7625  * for such devices.
7626  *
7627  * Returns zero on success, non-zero error value on failure.
7628  */
7629 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
7630 {
7631         int ret = 0;
7632         u32 granularity, peer_granularity;
7633         u32 pa_tactivate, peer_pa_tactivate;
7634         u32 pa_tactivate_us, peer_pa_tactivate_us;
7635         u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
7636
7637         ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7638                                   &granularity);
7639         if (ret)
7640                 goto out;
7641
7642         ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7643                                   &peer_granularity);
7644         if (ret)
7645                 goto out;
7646
7647         if ((granularity < PA_GRANULARITY_MIN_VAL) ||
7648             (granularity > PA_GRANULARITY_MAX_VAL)) {
7649                 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
7650                         __func__, granularity);
7651                 return -EINVAL;
7652         }
7653
7654         if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
7655             (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
7656                 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
7657                         __func__, peer_granularity);
7658                 return -EINVAL;
7659         }
7660
7661         ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
7662         if (ret)
7663                 goto out;
7664
7665         ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
7666                                   &peer_pa_tactivate);
7667         if (ret)
7668                 goto out;
7669
7670         pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
7671         peer_pa_tactivate_us = peer_pa_tactivate *
7672                              gran_to_us_table[peer_granularity - 1];
7673
7674         if (pa_tactivate_us > peer_pa_tactivate_us) {
7675                 u32 new_peer_pa_tactivate;
7676
7677                 new_peer_pa_tactivate = pa_tactivate_us /
7678                                       gran_to_us_table[peer_granularity - 1];
7679                 new_peer_pa_tactivate++;
7680                 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7681                                           new_peer_pa_tactivate);
7682         }
7683
7684 out:
7685         return ret;
7686 }
7687
7688 static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
7689 {
7690         if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
7691                 ufshcd_tune_pa_tactivate(hba);
7692                 ufshcd_tune_pa_hibern8time(hba);
7693         }
7694
7695         ufshcd_vops_apply_dev_quirks(hba);
7696
7697         if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
7698                 /* set 1ms timeout for PA_TACTIVATE */
7699                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
7700
7701         if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
7702                 ufshcd_quirk_tune_host_pa_tactivate(hba);
7703 }
7704
7705 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
7706 {
7707         hba->ufs_stats.hibern8_exit_cnt = 0;
7708         hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
7709         hba->req_abort_count = 0;
7710 }
7711
7712 static int ufshcd_device_geo_params_init(struct ufs_hba *hba)
7713 {
7714         int err;
7715         size_t buff_len;
7716         u8 *desc_buf;
7717
7718         buff_len = hba->desc_size[QUERY_DESC_IDN_GEOMETRY];
7719         desc_buf = kmalloc(buff_len, GFP_KERNEL);
7720         if (!desc_buf) {
7721                 err = -ENOMEM;
7722                 goto out;
7723         }
7724
7725         err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0,
7726                                      desc_buf, buff_len);
7727         if (err) {
7728                 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n",
7729                                 __func__, err);
7730                 goto out;
7731         }
7732
7733         if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1)
7734                 hba->dev_info.max_lu_supported = 32;
7735         else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0)
7736                 hba->dev_info.max_lu_supported = 8;
7737
7738         if (hba->desc_size[QUERY_DESC_IDN_GEOMETRY] >=
7739                 GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS)
7740                 ufshpb_get_geo_info(hba, desc_buf);
7741
7742 out:
7743         kfree(desc_buf);
7744         return err;
7745 }
7746
7747 static struct ufs_ref_clk ufs_ref_clk_freqs[] = {
7748         {19200000, REF_CLK_FREQ_19_2_MHZ},
7749         {26000000, REF_CLK_FREQ_26_MHZ},
7750         {38400000, REF_CLK_FREQ_38_4_MHZ},
7751         {52000000, REF_CLK_FREQ_52_MHZ},
7752         {0, REF_CLK_FREQ_INVAL},
7753 };
7754
7755 static enum ufs_ref_clk_freq
7756 ufs_get_bref_clk_from_hz(unsigned long freq)
7757 {
7758         int i;
7759
7760         for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
7761                 if (ufs_ref_clk_freqs[i].freq_hz == freq)
7762                         return ufs_ref_clk_freqs[i].val;
7763
7764         return REF_CLK_FREQ_INVAL;
7765 }
7766
7767 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
7768 {
7769         unsigned long freq;
7770
7771         freq = clk_get_rate(refclk);
7772
7773         hba->dev_ref_clk_freq =
7774                 ufs_get_bref_clk_from_hz(freq);
7775
7776         if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
7777                 dev_err(hba->dev,
7778                 "invalid ref_clk setting = %ld\n", freq);
7779 }
7780
7781 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
7782 {
7783         int err;
7784         u32 ref_clk;
7785         u32 freq = hba->dev_ref_clk_freq;
7786
7787         err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
7788                         QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
7789
7790         if (err) {
7791                 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
7792                         err);
7793                 goto out;
7794         }
7795
7796         if (ref_clk == freq)
7797                 goto out; /* nothing to update */
7798
7799         err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
7800                         QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
7801
7802         if (err) {
7803                 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
7804                         ufs_ref_clk_freqs[freq].freq_hz);
7805                 goto out;
7806         }
7807
7808         dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
7809                         ufs_ref_clk_freqs[freq].freq_hz);
7810
7811 out:
7812         return err;
7813 }
7814
7815 static int ufshcd_device_params_init(struct ufs_hba *hba)
7816 {
7817         bool flag;
7818         int ret, i;
7819
7820          /* Init device descriptor sizes */
7821         for (i = 0; i < QUERY_DESC_IDN_MAX; i++)
7822                 hba->desc_size[i] = QUERY_DESC_MAX_SIZE;
7823
7824         /* Init UFS geometry descriptor related parameters */
7825         ret = ufshcd_device_geo_params_init(hba);
7826         if (ret)
7827                 goto out;
7828
7829         /* Check and apply UFS device quirks */
7830         ret = ufs_get_device_desc(hba);
7831         if (ret) {
7832                 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
7833                         __func__, ret);
7834                 goto out;
7835         }
7836
7837         ufshcd_get_ref_clk_gating_wait(hba);
7838
7839         if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
7840                         QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag))
7841                 hba->dev_info.f_power_on_wp_en = flag;
7842
7843         /* Probe maximum power mode co-supported by both UFS host and device */
7844         if (ufshcd_get_max_pwr_mode(hba))
7845                 dev_err(hba->dev,
7846                         "%s: Failed getting max supported power mode\n",
7847                         __func__);
7848 out:
7849         return ret;
7850 }
7851
7852 /**
7853  * ufshcd_add_lus - probe and add UFS logical units
7854  * @hba: per-adapter instance
7855  */
7856 static int ufshcd_add_lus(struct ufs_hba *hba)
7857 {
7858         int ret;
7859
7860         /* Add required well known logical units to scsi mid layer */
7861         ret = ufshcd_scsi_add_wlus(hba);
7862         if (ret)
7863                 goto out;
7864
7865         ufshcd_clear_ua_wluns(hba);
7866
7867         /* Initialize devfreq after UFS device is detected */
7868         if (ufshcd_is_clkscaling_supported(hba)) {
7869                 memcpy(&hba->clk_scaling.saved_pwr_info.info,
7870                         &hba->pwr_info,
7871                         sizeof(struct ufs_pa_layer_attr));
7872                 hba->clk_scaling.saved_pwr_info.is_valid = true;
7873                 hba->clk_scaling.is_allowed = true;
7874
7875                 ret = ufshcd_devfreq_init(hba);
7876                 if (ret)
7877                         goto out;
7878
7879                 hba->clk_scaling.is_enabled = true;
7880                 ufshcd_init_clk_scaling_sysfs(hba);
7881         }
7882
7883         ufs_bsg_probe(hba);
7884         ufshpb_init(hba);
7885         scsi_scan_host(hba->host);
7886         pm_runtime_put_sync(hba->dev);
7887
7888 out:
7889         return ret;
7890 }
7891
7892 static int
7893 ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp);
7894
7895 static int ufshcd_clear_ua_wlun(struct ufs_hba *hba, u8 wlun)
7896 {
7897         struct scsi_device *sdp;
7898         unsigned long flags;
7899         int ret = 0;
7900
7901         spin_lock_irqsave(hba->host->host_lock, flags);
7902         if (wlun == UFS_UPIU_UFS_DEVICE_WLUN)
7903                 sdp = hba->sdev_ufs_device;
7904         else if (wlun == UFS_UPIU_RPMB_WLUN)
7905                 sdp = hba->sdev_rpmb;
7906         else
7907                 BUG();
7908         if (sdp) {
7909                 ret = scsi_device_get(sdp);
7910                 if (!ret && !scsi_device_online(sdp)) {
7911                         ret = -ENODEV;
7912                         scsi_device_put(sdp);
7913                 }
7914         } else {
7915                 ret = -ENODEV;
7916         }
7917         spin_unlock_irqrestore(hba->host->host_lock, flags);
7918         if (ret)
7919                 goto out_err;
7920
7921         ret = ufshcd_send_request_sense(hba, sdp);
7922         scsi_device_put(sdp);
7923 out_err:
7924         if (ret)
7925                 dev_err(hba->dev, "%s: UAC clear LU=%x ret = %d\n",
7926                                 __func__, wlun, ret);
7927         return ret;
7928 }
7929
7930 static int ufshcd_clear_ua_wluns(struct ufs_hba *hba)
7931 {
7932         int ret = 0;
7933
7934         if (!hba->wlun_dev_clr_ua)
7935                 goto out;
7936
7937         ret = ufshcd_clear_ua_wlun(hba, UFS_UPIU_UFS_DEVICE_WLUN);
7938         if (!ret)
7939                 ret = ufshcd_clear_ua_wlun(hba, UFS_UPIU_RPMB_WLUN);
7940         if (!ret)
7941                 hba->wlun_dev_clr_ua = false;
7942 out:
7943         if (ret)
7944                 dev_err(hba->dev, "%s: Failed to clear UAC WLUNS ret = %d\n",
7945                                 __func__, ret);
7946         return ret;
7947 }
7948
7949 /**
7950  * ufshcd_probe_hba - probe hba to detect device and initialize it
7951  * @hba: per-adapter instance
7952  * @init_dev_params: whether or not to call ufshcd_device_params_init().
7953  *
7954  * Execute link-startup and verify device initialization
7955  */
7956 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params)
7957 {
7958         int ret;
7959         unsigned long flags;
7960         ktime_t start = ktime_get();
7961
7962         hba->ufshcd_state = UFSHCD_STATE_RESET;
7963
7964         ret = ufshcd_link_startup(hba);
7965         if (ret)
7966                 goto out;
7967
7968         /* Debug counters initialization */
7969         ufshcd_clear_dbg_ufs_stats(hba);
7970
7971         /* UniPro link is active now */
7972         ufshcd_set_link_active(hba);
7973
7974         /* Verify device initialization by sending NOP OUT UPIU */
7975         ret = ufshcd_verify_dev_init(hba);
7976         if (ret)
7977                 goto out;
7978
7979         /* Initiate UFS initialization, and waiting until completion */
7980         ret = ufshcd_complete_dev_init(hba);
7981         if (ret)
7982                 goto out;
7983
7984         /*
7985          * Initialize UFS device parameters used by driver, these
7986          * parameters are associated with UFS descriptors.
7987          */
7988         if (init_dev_params) {
7989                 ret = ufshcd_device_params_init(hba);
7990                 if (ret)
7991                         goto out;
7992         }
7993
7994         ufshcd_tune_unipro_params(hba);
7995
7996         /* UFS device is also active now */
7997         ufshcd_set_ufs_dev_active(hba);
7998         ufshcd_force_reset_auto_bkops(hba);
7999         hba->wlun_dev_clr_ua = true;
8000         hba->wlun_rpmb_clr_ua = true;
8001
8002         /* Gear up to HS gear if supported */
8003         if (hba->max_pwr_info.is_valid) {
8004                 /*
8005                  * Set the right value to bRefClkFreq before attempting to
8006                  * switch to HS gears.
8007                  */
8008                 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
8009                         ufshcd_set_dev_ref_clk(hba);
8010                 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8011                 if (ret) {
8012                         dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
8013                                         __func__, ret);
8014                         goto out;
8015                 }
8016                 ufshcd_print_pwr_info(hba);
8017         }
8018
8019         /*
8020          * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec)
8021          * and for removable UFS card as well, hence always set the parameter.
8022          * Note: Error handler may issue the device reset hence resetting
8023          * bActiveICCLevel as well so it is always safe to set this here.
8024          */
8025         ufshcd_set_active_icc_lvl(hba);
8026
8027         ufshcd_wb_config(hba);
8028         if (hba->ee_usr_mask)
8029                 ufshcd_write_ee_control(hba);
8030         /* Enable Auto-Hibernate if configured */
8031         ufshcd_auto_hibern8_enable(hba);
8032
8033         ufshpb_reset(hba);
8034 out:
8035         spin_lock_irqsave(hba->host->host_lock, flags);
8036         if (ret)
8037                 hba->ufshcd_state = UFSHCD_STATE_ERROR;
8038         else if (hba->ufshcd_state == UFSHCD_STATE_RESET)
8039                 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
8040         spin_unlock_irqrestore(hba->host->host_lock, flags);
8041
8042         trace_ufshcd_init(dev_name(hba->dev), ret,
8043                 ktime_to_us(ktime_sub(ktime_get(), start)),
8044                 hba->curr_dev_pwr_mode, hba->uic_link_state);
8045         return ret;
8046 }
8047
8048 /**
8049  * ufshcd_async_scan - asynchronous execution for probing hba
8050  * @data: data pointer to pass to this function
8051  * @cookie: cookie data
8052  */
8053 static void ufshcd_async_scan(void *data, async_cookie_t cookie)
8054 {
8055         struct ufs_hba *hba = (struct ufs_hba *)data;
8056         int ret;
8057
8058         down(&hba->host_sem);
8059         /* Initialize hba, detect and initialize UFS device */
8060         ret = ufshcd_probe_hba(hba, true);
8061         up(&hba->host_sem);
8062         if (ret)
8063                 goto out;
8064
8065         /* Probe and add UFS logical units  */
8066         ret = ufshcd_add_lus(hba);
8067 out:
8068         /*
8069          * If we failed to initialize the device or the device is not
8070          * present, turn off the power/clocks etc.
8071          */
8072         if (ret) {
8073                 pm_runtime_put_sync(hba->dev);
8074                 ufshcd_hba_exit(hba);
8075         }
8076 }
8077
8078 static const struct attribute_group *ufshcd_driver_groups[] = {
8079         &ufs_sysfs_unit_descriptor_group,
8080         &ufs_sysfs_lun_attributes_group,
8081 #ifdef CONFIG_SCSI_UFS_HPB
8082         &ufs_sysfs_hpb_stat_group,
8083         &ufs_sysfs_hpb_param_group,
8084 #endif
8085         NULL,
8086 };
8087
8088 static struct ufs_hba_variant_params ufs_hba_vps = {
8089         .hba_enable_delay_us            = 1000,
8090         .wb_flush_threshold             = UFS_WB_BUF_REMAIN_PERCENT(40),
8091         .devfreq_profile.polling_ms     = 100,
8092         .devfreq_profile.target         = ufshcd_devfreq_target,
8093         .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status,
8094         .ondemand_data.upthreshold      = 70,
8095         .ondemand_data.downdifferential = 5,
8096 };
8097
8098 static struct scsi_host_template ufshcd_driver_template = {
8099         .module                 = THIS_MODULE,
8100         .name                   = UFSHCD,
8101         .proc_name              = UFSHCD,
8102         .queuecommand           = ufshcd_queuecommand,
8103         .slave_alloc            = ufshcd_slave_alloc,
8104         .slave_configure        = ufshcd_slave_configure,
8105         .slave_destroy          = ufshcd_slave_destroy,
8106         .change_queue_depth     = ufshcd_change_queue_depth,
8107         .eh_abort_handler       = ufshcd_abort,
8108         .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
8109         .eh_host_reset_handler   = ufshcd_eh_host_reset_handler,
8110         .this_id                = -1,
8111         .sg_tablesize           = SG_ALL,
8112         .cmd_per_lun            = UFSHCD_CMD_PER_LUN,
8113         .can_queue              = UFSHCD_CAN_QUEUE,
8114         .max_segment_size       = PRDT_DATA_BYTE_COUNT_MAX,
8115         .max_host_blocked       = 1,
8116         .track_queue_depth      = 1,
8117         .sdev_groups            = ufshcd_driver_groups,
8118         .dma_boundary           = PAGE_SIZE - 1,
8119         .rpm_autosuspend_delay  = RPM_AUTOSUSPEND_DELAY_MS,
8120 };
8121
8122 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
8123                                    int ua)
8124 {
8125         int ret;
8126
8127         if (!vreg)
8128                 return 0;
8129
8130         /*
8131          * "set_load" operation shall be required on those regulators
8132          * which specifically configured current limitation. Otherwise
8133          * zero max_uA may cause unexpected behavior when regulator is
8134          * enabled or set as high power mode.
8135          */
8136         if (!vreg->max_uA)
8137                 return 0;
8138
8139         ret = regulator_set_load(vreg->reg, ua);
8140         if (ret < 0) {
8141                 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
8142                                 __func__, vreg->name, ua, ret);
8143         }
8144
8145         return ret;
8146 }
8147
8148 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
8149                                          struct ufs_vreg *vreg)
8150 {
8151         return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
8152 }
8153
8154 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
8155                                          struct ufs_vreg *vreg)
8156 {
8157         if (!vreg)
8158                 return 0;
8159
8160         return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
8161 }
8162
8163 static int ufshcd_config_vreg(struct device *dev,
8164                 struct ufs_vreg *vreg, bool on)
8165 {
8166         int ret = 0;
8167         struct regulator *reg;
8168         const char *name;
8169         int min_uV, uA_load;
8170
8171         BUG_ON(!vreg);
8172
8173         reg = vreg->reg;
8174         name = vreg->name;
8175
8176         if (regulator_count_voltages(reg) > 0) {
8177                 uA_load = on ? vreg->max_uA : 0;
8178                 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
8179                 if (ret)
8180                         goto out;
8181
8182                 if (vreg->min_uV && vreg->max_uV) {
8183                         min_uV = on ? vreg->min_uV : 0;
8184                         ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
8185                         if (ret)
8186                                 dev_err(dev,
8187                                         "%s: %s set voltage failed, err=%d\n",
8188                                         __func__, name, ret);
8189                 }
8190         }
8191 out:
8192         return ret;
8193 }
8194
8195 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
8196 {
8197         int ret = 0;
8198
8199         if (!vreg || vreg->enabled)
8200                 goto out;
8201
8202         ret = ufshcd_config_vreg(dev, vreg, true);
8203         if (!ret)
8204                 ret = regulator_enable(vreg->reg);
8205
8206         if (!ret)
8207                 vreg->enabled = true;
8208         else
8209                 dev_err(dev, "%s: %s enable failed, err=%d\n",
8210                                 __func__, vreg->name, ret);
8211 out:
8212         return ret;
8213 }
8214
8215 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
8216 {
8217         int ret = 0;
8218
8219         if (!vreg || !vreg->enabled || vreg->always_on)
8220                 goto out;
8221
8222         ret = regulator_disable(vreg->reg);
8223
8224         if (!ret) {
8225                 /* ignore errors on applying disable config */
8226                 ufshcd_config_vreg(dev, vreg, false);
8227                 vreg->enabled = false;
8228         } else {
8229                 dev_err(dev, "%s: %s disable failed, err=%d\n",
8230                                 __func__, vreg->name, ret);
8231         }
8232 out:
8233         return ret;
8234 }
8235
8236 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
8237 {
8238         int ret = 0;
8239         struct device *dev = hba->dev;
8240         struct ufs_vreg_info *info = &hba->vreg_info;
8241
8242         ret = ufshcd_toggle_vreg(dev, info->vcc, on);
8243         if (ret)
8244                 goto out;
8245
8246         ret = ufshcd_toggle_vreg(dev, info->vccq, on);
8247         if (ret)
8248                 goto out;
8249
8250         ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
8251
8252 out:
8253         if (ret) {
8254                 ufshcd_toggle_vreg(dev, info->vccq2, false);
8255                 ufshcd_toggle_vreg(dev, info->vccq, false);
8256                 ufshcd_toggle_vreg(dev, info->vcc, false);
8257         }
8258         return ret;
8259 }
8260
8261 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
8262 {
8263         struct ufs_vreg_info *info = &hba->vreg_info;
8264
8265         return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
8266 }
8267
8268 static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
8269 {
8270         int ret = 0;
8271
8272         if (!vreg)
8273                 goto out;
8274
8275         vreg->reg = devm_regulator_get(dev, vreg->name);
8276         if (IS_ERR(vreg->reg)) {
8277                 ret = PTR_ERR(vreg->reg);
8278                 dev_err(dev, "%s: %s get failed, err=%d\n",
8279                                 __func__, vreg->name, ret);
8280         }
8281 out:
8282         return ret;
8283 }
8284
8285 static int ufshcd_init_vreg(struct ufs_hba *hba)
8286 {
8287         int ret = 0;
8288         struct device *dev = hba->dev;
8289         struct ufs_vreg_info *info = &hba->vreg_info;
8290
8291         ret = ufshcd_get_vreg(dev, info->vcc);
8292         if (ret)
8293                 goto out;
8294
8295         ret = ufshcd_get_vreg(dev, info->vccq);
8296         if (!ret)
8297                 ret = ufshcd_get_vreg(dev, info->vccq2);
8298 out:
8299         return ret;
8300 }
8301
8302 static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
8303 {
8304         struct ufs_vreg_info *info = &hba->vreg_info;
8305
8306         if (info)
8307                 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
8308
8309         return 0;
8310 }
8311
8312 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
8313 {
8314         int ret = 0;
8315         struct ufs_clk_info *clki;
8316         struct list_head *head = &hba->clk_list_head;
8317         unsigned long flags;
8318         ktime_t start = ktime_get();
8319         bool clk_state_changed = false;
8320
8321         if (list_empty(head))
8322                 goto out;
8323
8324         ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
8325         if (ret)
8326                 return ret;
8327
8328         list_for_each_entry(clki, head, list) {
8329                 if (!IS_ERR_OR_NULL(clki->clk)) {
8330                         /*
8331                          * Don't disable clocks which are needed
8332                          * to keep the link active.
8333                          */
8334                         if (ufshcd_is_link_active(hba) &&
8335                             clki->keep_link_active)
8336                                 continue;
8337
8338                         clk_state_changed = on ^ clki->enabled;
8339                         if (on && !clki->enabled) {
8340                                 ret = clk_prepare_enable(clki->clk);
8341                                 if (ret) {
8342                                         dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
8343                                                 __func__, clki->name, ret);
8344                                         goto out;
8345                                 }
8346                         } else if (!on && clki->enabled) {
8347                                 clk_disable_unprepare(clki->clk);
8348                         }
8349                         clki->enabled = on;
8350                         dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
8351                                         clki->name, on ? "en" : "dis");
8352                 }
8353         }
8354
8355         ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
8356         if (ret)
8357                 return ret;
8358
8359 out:
8360         if (ret) {
8361                 list_for_each_entry(clki, head, list) {
8362                         if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
8363                                 clk_disable_unprepare(clki->clk);
8364                 }
8365         } else if (!ret && on) {
8366                 spin_lock_irqsave(hba->host->host_lock, flags);
8367                 hba->clk_gating.state = CLKS_ON;
8368                 trace_ufshcd_clk_gating(dev_name(hba->dev),
8369                                         hba->clk_gating.state);
8370                 spin_unlock_irqrestore(hba->host->host_lock, flags);
8371         }
8372
8373         if (clk_state_changed)
8374                 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
8375                         (on ? "on" : "off"),
8376                         ktime_to_us(ktime_sub(ktime_get(), start)), ret);
8377         return ret;
8378 }
8379
8380 static int ufshcd_init_clocks(struct ufs_hba *hba)
8381 {
8382         int ret = 0;
8383         struct ufs_clk_info *clki;
8384         struct device *dev = hba->dev;
8385         struct list_head *head = &hba->clk_list_head;
8386
8387         if (list_empty(head))
8388                 goto out;
8389
8390         list_for_each_entry(clki, head, list) {
8391                 if (!clki->name)
8392                         continue;
8393
8394                 clki->clk = devm_clk_get(dev, clki->name);
8395                 if (IS_ERR(clki->clk)) {
8396                         ret = PTR_ERR(clki->clk);
8397                         dev_err(dev, "%s: %s clk get failed, %d\n",
8398                                         __func__, clki->name, ret);
8399                         goto out;
8400                 }
8401
8402                 /*
8403                  * Parse device ref clk freq as per device tree "ref_clk".
8404                  * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
8405                  * in ufshcd_alloc_host().
8406                  */
8407                 if (!strcmp(clki->name, "ref_clk"))
8408                         ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
8409
8410                 if (clki->max_freq) {
8411                         ret = clk_set_rate(clki->clk, clki->max_freq);
8412                         if (ret) {
8413                                 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
8414                                         __func__, clki->name,
8415                                         clki->max_freq, ret);
8416                                 goto out;
8417                         }
8418                         clki->curr_freq = clki->max_freq;
8419                 }
8420                 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
8421                                 clki->name, clk_get_rate(clki->clk));
8422         }
8423 out:
8424         return ret;
8425 }
8426
8427 static int ufshcd_variant_hba_init(struct ufs_hba *hba)
8428 {
8429         int err = 0;
8430
8431         if (!hba->vops)
8432                 goto out;
8433
8434         err = ufshcd_vops_init(hba);
8435         if (err)
8436                 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
8437                         __func__, ufshcd_get_var_name(hba), err);
8438 out:
8439         return err;
8440 }
8441
8442 static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
8443 {
8444         if (!hba->vops)
8445                 return;
8446
8447         ufshcd_vops_exit(hba);
8448 }
8449
8450 static int ufshcd_hba_init(struct ufs_hba *hba)
8451 {
8452         int err;
8453
8454         /*
8455          * Handle host controller power separately from the UFS device power
8456          * rails as it will help controlling the UFS host controller power
8457          * collapse easily which is different than UFS device power collapse.
8458          * Also, enable the host controller power before we go ahead with rest
8459          * of the initialization here.
8460          */
8461         err = ufshcd_init_hba_vreg(hba);
8462         if (err)
8463                 goto out;
8464
8465         err = ufshcd_setup_hba_vreg(hba, true);
8466         if (err)
8467                 goto out;
8468
8469         err = ufshcd_init_clocks(hba);
8470         if (err)
8471                 goto out_disable_hba_vreg;
8472
8473         err = ufshcd_setup_clocks(hba, true);
8474         if (err)
8475                 goto out_disable_hba_vreg;
8476
8477         err = ufshcd_init_vreg(hba);
8478         if (err)
8479                 goto out_disable_clks;
8480
8481         err = ufshcd_setup_vreg(hba, true);
8482         if (err)
8483                 goto out_disable_clks;
8484
8485         err = ufshcd_variant_hba_init(hba);
8486         if (err)
8487                 goto out_disable_vreg;
8488
8489         ufs_debugfs_hba_init(hba);
8490
8491         hba->is_powered = true;
8492         goto out;
8493
8494 out_disable_vreg:
8495         ufshcd_setup_vreg(hba, false);
8496 out_disable_clks:
8497         ufshcd_setup_clocks(hba, false);
8498 out_disable_hba_vreg:
8499         ufshcd_setup_hba_vreg(hba, false);
8500 out:
8501         return err;
8502 }
8503
8504 static void ufshcd_hba_exit(struct ufs_hba *hba)
8505 {
8506         if (hba->is_powered) {
8507                 ufshcd_exit_clk_scaling(hba);
8508                 ufshcd_exit_clk_gating(hba);
8509                 if (hba->eh_wq)
8510                         destroy_workqueue(hba->eh_wq);
8511                 ufs_debugfs_hba_exit(hba);
8512                 ufshcd_variant_hba_exit(hba);
8513                 ufshcd_setup_vreg(hba, false);
8514                 ufshcd_setup_clocks(hba, false);
8515                 ufshcd_setup_hba_vreg(hba, false);
8516                 hba->is_powered = false;
8517                 ufs_put_device_desc(hba);
8518         }
8519 }
8520
8521 static int
8522 ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
8523 {
8524         unsigned char cmd[6] = {REQUEST_SENSE,
8525                                 0,
8526                                 0,
8527                                 0,
8528                                 UFS_SENSE_SIZE,
8529                                 0};
8530         char *buffer;
8531         int ret;
8532
8533         buffer = kzalloc(UFS_SENSE_SIZE, GFP_KERNEL);
8534         if (!buffer) {
8535                 ret = -ENOMEM;
8536                 goto out;
8537         }
8538
8539         ret = scsi_execute(sdp, cmd, DMA_FROM_DEVICE, buffer,
8540                         UFS_SENSE_SIZE, NULL, NULL,
8541                         msecs_to_jiffies(1000), 3, 0, RQF_PM, NULL);
8542         if (ret)
8543                 pr_err("%s: failed with err %d\n", __func__, ret);
8544
8545         kfree(buffer);
8546 out:
8547         return ret;
8548 }
8549
8550 /**
8551  * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
8552  *                           power mode
8553  * @hba: per adapter instance
8554  * @pwr_mode: device power mode to set
8555  *
8556  * Returns 0 if requested power mode is set successfully
8557  * Returns non-zero if failed to set the requested power mode
8558  */
8559 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
8560                                      enum ufs_dev_pwr_mode pwr_mode)
8561 {
8562         unsigned char cmd[6] = { START_STOP };
8563         struct scsi_sense_hdr sshdr;
8564         struct scsi_device *sdp;
8565         unsigned long flags;
8566         int ret;
8567
8568         spin_lock_irqsave(hba->host->host_lock, flags);
8569         sdp = hba->sdev_ufs_device;
8570         if (sdp) {
8571                 ret = scsi_device_get(sdp);
8572                 if (!ret && !scsi_device_online(sdp)) {
8573                         ret = -ENODEV;
8574                         scsi_device_put(sdp);
8575                 }
8576         } else {
8577                 ret = -ENODEV;
8578         }
8579         spin_unlock_irqrestore(hba->host->host_lock, flags);
8580
8581         if (ret)
8582                 return ret;
8583
8584         /*
8585          * If scsi commands fail, the scsi mid-layer schedules scsi error-
8586          * handling, which would wait for host to be resumed. Since we know
8587          * we are functional while we are here, skip host resume in error
8588          * handling context.
8589          */
8590         hba->host->eh_noresume = 1;
8591         if (hba->wlun_dev_clr_ua)
8592                 ufshcd_clear_ua_wlun(hba, UFS_UPIU_UFS_DEVICE_WLUN);
8593
8594         cmd[4] = pwr_mode << 4;
8595
8596         /*
8597          * Current function would be generally called from the power management
8598          * callbacks hence set the RQF_PM flag so that it doesn't resume the
8599          * already suspended childs.
8600          */
8601         ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
8602                         START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
8603         if (ret) {
8604                 sdev_printk(KERN_WARNING, sdp,
8605                             "START_STOP failed for power mode: %d, result %x\n",
8606                             pwr_mode, ret);
8607                 if (ret > 0 && scsi_sense_valid(&sshdr))
8608                         scsi_print_sense_hdr(sdp, NULL, &sshdr);
8609         }
8610
8611         if (!ret)
8612                 hba->curr_dev_pwr_mode = pwr_mode;
8613
8614         scsi_device_put(sdp);
8615         hba->host->eh_noresume = 0;
8616         return ret;
8617 }
8618
8619 static int ufshcd_link_state_transition(struct ufs_hba *hba,
8620                                         enum uic_link_state req_link_state,
8621                                         int check_for_bkops)
8622 {
8623         int ret = 0;
8624
8625         if (req_link_state == hba->uic_link_state)
8626                 return 0;
8627
8628         if (req_link_state == UIC_LINK_HIBERN8_STATE) {
8629                 ret = ufshcd_uic_hibern8_enter(hba);
8630                 if (!ret) {
8631                         ufshcd_set_link_hibern8(hba);
8632                 } else {
8633                         dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
8634                                         __func__, ret);
8635                         goto out;
8636                 }
8637         }
8638         /*
8639          * If autobkops is enabled, link can't be turned off because
8640          * turning off the link would also turn off the device, except in the
8641          * case of DeepSleep where the device is expected to remain powered.
8642          */
8643         else if ((req_link_state == UIC_LINK_OFF_STATE) &&
8644                  (!check_for_bkops || !hba->auto_bkops_enabled)) {
8645                 /*
8646                  * Let's make sure that link is in low power mode, we are doing
8647                  * this currently by putting the link in Hibern8. Otherway to
8648                  * put the link in low power mode is to send the DME end point
8649                  * to device and then send the DME reset command to local
8650                  * unipro. But putting the link in hibern8 is much faster.
8651                  *
8652                  * Note also that putting the link in Hibern8 is a requirement
8653                  * for entering DeepSleep.
8654                  */
8655                 ret = ufshcd_uic_hibern8_enter(hba);
8656                 if (ret) {
8657                         dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
8658                                         __func__, ret);
8659                         goto out;
8660                 }
8661                 /*
8662                  * Change controller state to "reset state" which
8663                  * should also put the link in off/reset state
8664                  */
8665                 ufshcd_hba_stop(hba);
8666                 /*
8667                  * TODO: Check if we need any delay to make sure that
8668                  * controller is reset
8669                  */
8670                 ufshcd_set_link_off(hba);
8671         }
8672
8673 out:
8674         return ret;
8675 }
8676
8677 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
8678 {
8679         bool vcc_off = false;
8680
8681         /*
8682          * It seems some UFS devices may keep drawing more than sleep current
8683          * (atleast for 500us) from UFS rails (especially from VCCQ rail).
8684          * To avoid this situation, add 2ms delay before putting these UFS
8685          * rails in LPM mode.
8686          */
8687         if (!ufshcd_is_link_active(hba) &&
8688             hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
8689                 usleep_range(2000, 2100);
8690
8691         /*
8692          * If UFS device is either in UFS_Sleep turn off VCC rail to save some
8693          * power.
8694          *
8695          * If UFS device and link is in OFF state, all power supplies (VCC,
8696          * VCCQ, VCCQ2) can be turned off if power on write protect is not
8697          * required. If UFS link is inactive (Hibern8 or OFF state) and device
8698          * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
8699          *
8700          * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
8701          * in low power state which would save some power.
8702          *
8703          * If Write Booster is enabled and the device needs to flush the WB
8704          * buffer OR if bkops status is urgent for WB, keep Vcc on.
8705          */
8706         if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8707             !hba->dev_info.is_lu_power_on_wp) {
8708                 ufshcd_setup_vreg(hba, false);
8709                 vcc_off = true;
8710         } else if (!ufshcd_is_ufs_dev_active(hba)) {
8711                 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
8712                 vcc_off = true;
8713                 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) {
8714                         ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8715                         ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
8716                 }
8717         }
8718
8719         /*
8720          * Some UFS devices require delay after VCC power rail is turned-off.
8721          */
8722         if (vcc_off && hba->vreg_info.vcc &&
8723                 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)
8724                 usleep_range(5000, 5100);
8725 }
8726
8727 #ifdef CONFIG_PM
8728 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
8729 {
8730         int ret = 0;
8731
8732         if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8733             !hba->dev_info.is_lu_power_on_wp) {
8734                 ret = ufshcd_setup_vreg(hba, true);
8735         } else if (!ufshcd_is_ufs_dev_active(hba)) {
8736                 if (!ufshcd_is_link_active(hba)) {
8737                         ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
8738                         if (ret)
8739                                 goto vcc_disable;
8740                         ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
8741                         if (ret)
8742                                 goto vccq_lpm;
8743                 }
8744                 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
8745         }
8746         goto out;
8747
8748 vccq_lpm:
8749         ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8750 vcc_disable:
8751         ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
8752 out:
8753         return ret;
8754 }
8755 #endif /* CONFIG_PM */
8756
8757 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
8758 {
8759         if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
8760                 ufshcd_setup_hba_vreg(hba, false);
8761 }
8762
8763 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
8764 {
8765         if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
8766                 ufshcd_setup_hba_vreg(hba, true);
8767 }
8768
8769 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
8770 {
8771         int ret = 0;
8772         int check_for_bkops;
8773         enum ufs_pm_level pm_lvl;
8774         enum ufs_dev_pwr_mode req_dev_pwr_mode;
8775         enum uic_link_state req_link_state;
8776
8777         hba->pm_op_in_progress = true;
8778         if (pm_op != UFS_SHUTDOWN_PM) {
8779                 pm_lvl = pm_op == UFS_RUNTIME_PM ?
8780                          hba->rpm_lvl : hba->spm_lvl;
8781                 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
8782                 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
8783         } else {
8784                 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
8785                 req_link_state = UIC_LINK_OFF_STATE;
8786         }
8787
8788         ufshpb_suspend(hba);
8789
8790         /*
8791          * If we can't transition into any of the low power modes
8792          * just gate the clocks.
8793          */
8794         ufshcd_hold(hba, false);
8795         hba->clk_gating.is_suspended = true;
8796
8797         if (ufshcd_is_clkscaling_supported(hba))
8798                 ufshcd_clk_scaling_suspend(hba, true);
8799
8800         if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
8801                         req_link_state == UIC_LINK_ACTIVE_STATE) {
8802                 goto vops_suspend;
8803         }
8804
8805         if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
8806             (req_link_state == hba->uic_link_state))
8807                 goto enable_scaling;
8808
8809         /* UFS device & link must be active before we enter in this function */
8810         if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
8811                 ret = -EINVAL;
8812                 goto enable_scaling;
8813         }
8814
8815         if (pm_op == UFS_RUNTIME_PM) {
8816                 if (ufshcd_can_autobkops_during_suspend(hba)) {
8817                         /*
8818                          * The device is idle with no requests in the queue,
8819                          * allow background operations if bkops status shows
8820                          * that performance might be impacted.
8821                          */
8822                         ret = ufshcd_urgent_bkops(hba);
8823                         if (ret)
8824                                 goto enable_scaling;
8825                 } else {
8826                         /* make sure that auto bkops is disabled */
8827                         ufshcd_disable_auto_bkops(hba);
8828                 }
8829                 /*
8830                  * If device needs to do BKOP or WB buffer flush during
8831                  * Hibern8, keep device power mode as "active power mode"
8832                  * and VCC supply.
8833                  */
8834                 hba->dev_info.b_rpm_dev_flush_capable =
8835                         hba->auto_bkops_enabled ||
8836                         (((req_link_state == UIC_LINK_HIBERN8_STATE) ||
8837                         ((req_link_state == UIC_LINK_ACTIVE_STATE) &&
8838                         ufshcd_is_auto_hibern8_enabled(hba))) &&
8839                         ufshcd_wb_need_flush(hba));
8840         }
8841
8842         flush_work(&hba->eeh_work);
8843
8844         if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {
8845                 if (pm_op != UFS_RUNTIME_PM)
8846                         /* ensure that bkops is disabled */
8847                         ufshcd_disable_auto_bkops(hba);
8848
8849                 if (!hba->dev_info.b_rpm_dev_flush_capable) {
8850                         ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
8851                         if (ret)
8852                                 goto enable_scaling;
8853                 }
8854         }
8855
8856         /*
8857          * In the case of DeepSleep, the device is expected to remain powered
8858          * with the link off, so do not check for bkops.
8859          */
8860         check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba);
8861         ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops);
8862         if (ret)
8863                 goto set_dev_active;
8864
8865 vops_suspend:
8866         /*
8867          * Call vendor specific suspend callback. As these callbacks may access
8868          * vendor specific host controller register space call them before the
8869          * host clocks are ON.
8870          */
8871         ret = ufshcd_vops_suspend(hba, pm_op);
8872         if (ret)
8873                 goto set_link_active;
8874         goto out;
8875
8876 set_link_active:
8877         /*
8878          * Device hardware reset is required to exit DeepSleep. Also, for
8879          * DeepSleep, the link is off so host reset and restore will be done
8880          * further below.
8881          */
8882         if (ufshcd_is_ufs_dev_deepsleep(hba)) {
8883                 ufshcd_device_reset(hba);
8884                 WARN_ON(!ufshcd_is_link_off(hba));
8885         }
8886         if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
8887                 ufshcd_set_link_active(hba);
8888         else if (ufshcd_is_link_off(hba))
8889                 ufshcd_host_reset_and_restore(hba);
8890 set_dev_active:
8891         /* Can also get here needing to exit DeepSleep */
8892         if (ufshcd_is_ufs_dev_deepsleep(hba)) {
8893                 ufshcd_device_reset(hba);
8894                 ufshcd_host_reset_and_restore(hba);
8895         }
8896         if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
8897                 ufshcd_disable_auto_bkops(hba);
8898 enable_scaling:
8899         if (ufshcd_is_clkscaling_supported(hba))
8900                 ufshcd_clk_scaling_suspend(hba, false);
8901
8902         hba->dev_info.b_rpm_dev_flush_capable = false;
8903 out:
8904         if (hba->dev_info.b_rpm_dev_flush_capable) {
8905                 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work,
8906                         msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS));
8907         }
8908
8909         if (ret) {
8910                 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret);
8911                 hba->clk_gating.is_suspended = false;
8912                 ufshcd_release(hba);
8913                 ufshpb_resume(hba);
8914         }
8915         hba->pm_op_in_progress = false;
8916         return ret;
8917 }
8918
8919 #ifdef CONFIG_PM
8920 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
8921 {
8922         int ret;
8923         enum uic_link_state old_link_state = hba->uic_link_state;
8924
8925         hba->pm_op_in_progress = true;
8926
8927         /*
8928          * Call vendor specific resume callback. As these callbacks may access
8929          * vendor specific host controller register space call them when the
8930          * host clocks are ON.
8931          */
8932         ret = ufshcd_vops_resume(hba, pm_op);
8933         if (ret)
8934                 goto out;
8935
8936         /* For DeepSleep, the only supported option is to have the link off */
8937         WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba));
8938
8939         if (ufshcd_is_link_hibern8(hba)) {
8940                 ret = ufshcd_uic_hibern8_exit(hba);
8941                 if (!ret) {
8942                         ufshcd_set_link_active(hba);
8943                 } else {
8944                         dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
8945                                         __func__, ret);
8946                         goto vendor_suspend;
8947                 }
8948         } else if (ufshcd_is_link_off(hba)) {
8949                 /*
8950                  * A full initialization of the host and the device is
8951                  * required since the link was put to off during suspend.
8952                  * Note, in the case of DeepSleep, the device will exit
8953                  * DeepSleep due to device reset.
8954                  */
8955                 ret = ufshcd_reset_and_restore(hba);
8956                 /*
8957                  * ufshcd_reset_and_restore() should have already
8958                  * set the link state as active
8959                  */
8960                 if (ret || !ufshcd_is_link_active(hba))
8961                         goto vendor_suspend;
8962         }
8963
8964         if (!ufshcd_is_ufs_dev_active(hba)) {
8965                 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
8966                 if (ret)
8967                         goto set_old_link_state;
8968         }
8969
8970         if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
8971                 ufshcd_enable_auto_bkops(hba);
8972         else
8973                 /*
8974                  * If BKOPs operations are urgently needed at this moment then
8975                  * keep auto-bkops enabled or else disable it.
8976                  */
8977                 ufshcd_urgent_bkops(hba);
8978
8979         if (hba->ee_usr_mask)
8980                 ufshcd_write_ee_control(hba);
8981
8982         if (ufshcd_is_clkscaling_supported(hba))
8983                 ufshcd_clk_scaling_suspend(hba, false);
8984
8985         if (hba->dev_info.b_rpm_dev_flush_capable) {
8986                 hba->dev_info.b_rpm_dev_flush_capable = false;
8987                 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work);
8988         }
8989
8990         /* Enable Auto-Hibernate if configured */
8991         ufshcd_auto_hibern8_enable(hba);
8992
8993         ufshpb_resume(hba);
8994         goto out;
8995
8996 set_old_link_state:
8997         ufshcd_link_state_transition(hba, old_link_state, 0);
8998 vendor_suspend:
8999         ufshcd_vops_suspend(hba, pm_op);
9000 out:
9001         if (ret)
9002                 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret);
9003         hba->clk_gating.is_suspended = false;
9004         ufshcd_release(hba);
9005         hba->pm_op_in_progress = false;
9006         return ret;
9007 }
9008
9009 static int ufshcd_wl_runtime_suspend(struct device *dev)
9010 {
9011         struct scsi_device *sdev = to_scsi_device(dev);
9012         struct ufs_hba *hba;
9013         int ret;
9014         ktime_t start = ktime_get();
9015
9016         hba = shost_priv(sdev->host);
9017
9018         ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM);
9019         if (ret)
9020                 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9021
9022         trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret,
9023                 ktime_to_us(ktime_sub(ktime_get(), start)),
9024                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9025
9026         return ret;
9027 }
9028
9029 static int ufshcd_wl_runtime_resume(struct device *dev)
9030 {
9031         struct scsi_device *sdev = to_scsi_device(dev);
9032         struct ufs_hba *hba;
9033         int ret = 0;
9034         ktime_t start = ktime_get();
9035
9036         hba = shost_priv(sdev->host);
9037
9038         ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM);
9039         if (ret)
9040                 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9041
9042         trace_ufshcd_wl_runtime_resume(dev_name(dev), ret,
9043                 ktime_to_us(ktime_sub(ktime_get(), start)),
9044                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9045
9046         return ret;
9047 }
9048 #endif
9049
9050 #ifdef CONFIG_PM_SLEEP
9051 static int ufshcd_wl_suspend(struct device *dev)
9052 {
9053         struct scsi_device *sdev = to_scsi_device(dev);
9054         struct ufs_hba *hba;
9055         int ret = 0;
9056         ktime_t start = ktime_get();
9057
9058         hba = shost_priv(sdev->host);
9059         down(&hba->host_sem);
9060
9061         if (pm_runtime_suspended(dev))
9062                 goto out;
9063
9064         ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM);
9065         if (ret) {
9066                 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__,  ret);
9067                 up(&hba->host_sem);
9068         }
9069
9070 out:
9071         if (!ret)
9072                 hba->is_sys_suspended = true;
9073         trace_ufshcd_wl_suspend(dev_name(dev), ret,
9074                 ktime_to_us(ktime_sub(ktime_get(), start)),
9075                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9076
9077         return ret;
9078 }
9079
9080 static int ufshcd_wl_resume(struct device *dev)
9081 {
9082         struct scsi_device *sdev = to_scsi_device(dev);
9083         struct ufs_hba *hba;
9084         int ret = 0;
9085         ktime_t start = ktime_get();
9086
9087         hba = shost_priv(sdev->host);
9088
9089         if (pm_runtime_suspended(dev))
9090                 goto out;
9091
9092         ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM);
9093         if (ret)
9094                 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9095 out:
9096         trace_ufshcd_wl_resume(dev_name(dev), ret,
9097                 ktime_to_us(ktime_sub(ktime_get(), start)),
9098                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9099         if (!ret)
9100                 hba->is_sys_suspended = false;
9101         up(&hba->host_sem);
9102         return ret;
9103 }
9104 #endif
9105
9106 static void ufshcd_wl_shutdown(struct device *dev)
9107 {
9108         struct scsi_device *sdev = to_scsi_device(dev);
9109         struct ufs_hba *hba;
9110
9111         hba = shost_priv(sdev->host);
9112
9113         down(&hba->host_sem);
9114         hba->shutting_down = true;
9115         up(&hba->host_sem);
9116
9117         /* Turn on everything while shutting down */
9118         ufshcd_rpm_get_sync(hba);
9119         scsi_device_quiesce(sdev);
9120         shost_for_each_device(sdev, hba->host) {
9121                 if (sdev == hba->sdev_ufs_device)
9122                         continue;
9123                 scsi_device_quiesce(sdev);
9124         }
9125         __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
9126 }
9127
9128 /**
9129  * ufshcd_suspend - helper function for suspend operations
9130  * @hba: per adapter instance
9131  *
9132  * This function will put disable irqs, turn off clocks
9133  * and set vreg and hba-vreg in lpm mode.
9134  */
9135 static int ufshcd_suspend(struct ufs_hba *hba)
9136 {
9137         int ret;
9138
9139         if (!hba->is_powered)
9140                 return 0;
9141         /*
9142          * Disable the host irq as host controller as there won't be any
9143          * host controller transaction expected till resume.
9144          */
9145         ufshcd_disable_irq(hba);
9146         ret = ufshcd_setup_clocks(hba, false);
9147         if (ret) {
9148                 ufshcd_enable_irq(hba);
9149                 return ret;
9150         }
9151         if (ufshcd_is_clkgating_allowed(hba)) {
9152                 hba->clk_gating.state = CLKS_OFF;
9153                 trace_ufshcd_clk_gating(dev_name(hba->dev),
9154                                         hba->clk_gating.state);
9155         }
9156
9157         ufshcd_vreg_set_lpm(hba);
9158         /* Put the host controller in low power mode if possible */
9159         ufshcd_hba_vreg_set_lpm(hba);
9160         return ret;
9161 }
9162
9163 #ifdef CONFIG_PM
9164 /**
9165  * ufshcd_resume - helper function for resume operations
9166  * @hba: per adapter instance
9167  *
9168  * This function basically turns on the regulators, clocks and
9169  * irqs of the hba.
9170  *
9171  * Returns 0 for success and non-zero for failure
9172  */
9173 static int ufshcd_resume(struct ufs_hba *hba)
9174 {
9175         int ret;
9176
9177         if (!hba->is_powered)
9178                 return 0;
9179
9180         ufshcd_hba_vreg_set_hpm(hba);
9181         ret = ufshcd_vreg_set_hpm(hba);
9182         if (ret)
9183                 goto out;
9184
9185         /* Make sure clocks are enabled before accessing controller */
9186         ret = ufshcd_setup_clocks(hba, true);
9187         if (ret)
9188                 goto disable_vreg;
9189
9190         /* enable the host irq as host controller would be active soon */
9191         ufshcd_enable_irq(hba);
9192         goto out;
9193
9194 disable_vreg:
9195         ufshcd_vreg_set_lpm(hba);
9196 out:
9197         if (ret)
9198                 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret);
9199         return ret;
9200 }
9201 #endif /* CONFIG_PM */
9202
9203 #ifdef CONFIG_PM_SLEEP
9204 /**
9205  * ufshcd_system_suspend - system suspend callback
9206  * @dev: Device associated with the UFS controller.
9207  *
9208  * Executed before putting the system into a sleep state in which the contents
9209  * of main memory are preserved.
9210  *
9211  * Returns 0 for success and non-zero for failure
9212  */
9213 int ufshcd_system_suspend(struct device *dev)
9214 {
9215         struct ufs_hba *hba = dev_get_drvdata(dev);
9216         int ret = 0;
9217         ktime_t start = ktime_get();
9218
9219         if (pm_runtime_suspended(hba->dev))
9220                 goto out;
9221
9222         ret = ufshcd_suspend(hba);
9223 out:
9224         trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
9225                 ktime_to_us(ktime_sub(ktime_get(), start)),
9226                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9227         return ret;
9228 }
9229 EXPORT_SYMBOL(ufshcd_system_suspend);
9230
9231 /**
9232  * ufshcd_system_resume - system resume callback
9233  * @dev: Device associated with the UFS controller.
9234  *
9235  * Executed after waking the system up from a sleep state in which the contents
9236  * of main memory were preserved.
9237  *
9238  * Returns 0 for success and non-zero for failure
9239  */
9240 int ufshcd_system_resume(struct device *dev)
9241 {
9242         struct ufs_hba *hba = dev_get_drvdata(dev);
9243         ktime_t start = ktime_get();
9244         int ret = 0;
9245
9246         if (pm_runtime_suspended(hba->dev))
9247                 goto out;
9248
9249         ret = ufshcd_resume(hba);
9250
9251 out:
9252         trace_ufshcd_system_resume(dev_name(hba->dev), ret,
9253                 ktime_to_us(ktime_sub(ktime_get(), start)),
9254                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9255
9256         return ret;
9257 }
9258 EXPORT_SYMBOL(ufshcd_system_resume);
9259 #endif /* CONFIG_PM_SLEEP */
9260
9261 #ifdef CONFIG_PM
9262 /**
9263  * ufshcd_runtime_suspend - runtime suspend callback
9264  * @dev: Device associated with the UFS controller.
9265  *
9266  * Check the description of ufshcd_suspend() function for more details.
9267  *
9268  * Returns 0 for success and non-zero for failure
9269  */
9270 int ufshcd_runtime_suspend(struct device *dev)
9271 {
9272         struct ufs_hba *hba = dev_get_drvdata(dev);
9273         int ret;
9274         ktime_t start = ktime_get();
9275
9276         ret = ufshcd_suspend(hba);
9277
9278         trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
9279                 ktime_to_us(ktime_sub(ktime_get(), start)),
9280                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9281         return ret;
9282 }
9283 EXPORT_SYMBOL(ufshcd_runtime_suspend);
9284
9285 /**
9286  * ufshcd_runtime_resume - runtime resume routine
9287  * @dev: Device associated with the UFS controller.
9288  *
9289  * This function basically brings controller
9290  * to active state. Following operations are done in this function:
9291  *
9292  * 1. Turn on all the controller related clocks
9293  * 2. Turn ON VCC rail
9294  */
9295 int ufshcd_runtime_resume(struct device *dev)
9296 {
9297         struct ufs_hba *hba = dev_get_drvdata(dev);
9298         int ret;
9299         ktime_t start = ktime_get();
9300
9301         ret = ufshcd_resume(hba);
9302
9303         trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
9304                 ktime_to_us(ktime_sub(ktime_get(), start)),
9305                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9306         return ret;
9307 }
9308 EXPORT_SYMBOL(ufshcd_runtime_resume);
9309 #endif /* CONFIG_PM */
9310
9311 /**
9312  * ufshcd_shutdown - shutdown routine
9313  * @hba: per adapter instance
9314  *
9315  * This function would turn off both UFS device and UFS hba
9316  * regulators. It would also disable clocks.
9317  *
9318  * Returns 0 always to allow force shutdown even in case of errors.
9319  */
9320 int ufshcd_shutdown(struct ufs_hba *hba)
9321 {
9322         if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
9323                 goto out;
9324
9325         pm_runtime_get_sync(hba->dev);
9326
9327         ufshcd_suspend(hba);
9328 out:
9329         hba->is_powered = false;
9330         /* allow force shutdown even in case of errors */
9331         return 0;
9332 }
9333 EXPORT_SYMBOL(ufshcd_shutdown);
9334
9335 /**
9336  * ufshcd_remove - de-allocate SCSI host and host memory space
9337  *              data structure memory
9338  * @hba: per adapter instance
9339  */
9340 void ufshcd_remove(struct ufs_hba *hba)
9341 {
9342         if (hba->sdev_ufs_device)
9343                 ufshcd_rpm_get_sync(hba);
9344         ufs_bsg_remove(hba);
9345         ufshpb_remove(hba);
9346         ufs_sysfs_remove_nodes(hba->dev);
9347         blk_cleanup_queue(hba->tmf_queue);
9348         blk_mq_free_tag_set(&hba->tmf_tag_set);
9349         blk_cleanup_queue(hba->cmd_queue);
9350         scsi_remove_host(hba->host);
9351         /* disable interrupts */
9352         ufshcd_disable_intr(hba, hba->intr_mask);
9353         ufshcd_hba_stop(hba);
9354         ufshcd_hba_exit(hba);
9355 }
9356 EXPORT_SYMBOL_GPL(ufshcd_remove);
9357
9358 /**
9359  * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
9360  * @hba: pointer to Host Bus Adapter (HBA)
9361  */
9362 void ufshcd_dealloc_host(struct ufs_hba *hba)
9363 {
9364         scsi_host_put(hba->host);
9365 }
9366 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
9367
9368 /**
9369  * ufshcd_set_dma_mask - Set dma mask based on the controller
9370  *                       addressing capability
9371  * @hba: per adapter instance
9372  *
9373  * Returns 0 for success, non-zero for failure
9374  */
9375 static int ufshcd_set_dma_mask(struct ufs_hba *hba)
9376 {
9377         if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
9378                 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
9379                         return 0;
9380         }
9381         return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
9382 }
9383
9384 /**
9385  * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
9386  * @dev: pointer to device handle
9387  * @hba_handle: driver private handle
9388  * Returns 0 on success, non-zero value on failure
9389  */
9390 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
9391 {
9392         struct Scsi_Host *host;
9393         struct ufs_hba *hba;
9394         int err = 0;
9395
9396         if (!dev) {
9397                 dev_err(dev,
9398                 "Invalid memory reference for dev is NULL\n");
9399                 err = -ENODEV;
9400                 goto out_error;
9401         }
9402
9403         host = scsi_host_alloc(&ufshcd_driver_template,
9404                                 sizeof(struct ufs_hba));
9405         if (!host) {
9406                 dev_err(dev, "scsi_host_alloc failed\n");
9407                 err = -ENOMEM;
9408                 goto out_error;
9409         }
9410         hba = shost_priv(host);
9411         hba->host = host;
9412         hba->dev = dev;
9413         *hba_handle = hba;
9414         hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
9415
9416         INIT_LIST_HEAD(&hba->clk_list_head);
9417
9418 out_error:
9419         return err;
9420 }
9421 EXPORT_SYMBOL(ufshcd_alloc_host);
9422
9423 /* This function exists because blk_mq_alloc_tag_set() requires this. */
9424 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
9425                                      const struct blk_mq_queue_data *qd)
9426 {
9427         WARN_ON_ONCE(true);
9428         return BLK_STS_NOTSUPP;
9429 }
9430
9431 static const struct blk_mq_ops ufshcd_tmf_ops = {
9432         .queue_rq = ufshcd_queue_tmf,
9433 };
9434
9435 /**
9436  * ufshcd_init - Driver initialization routine
9437  * @hba: per-adapter instance
9438  * @mmio_base: base register address
9439  * @irq: Interrupt line of device
9440  * Returns 0 on success, non-zero value on failure
9441  */
9442 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
9443 {
9444         int err;
9445         struct Scsi_Host *host = hba->host;
9446         struct device *dev = hba->dev;
9447         char eh_wq_name[sizeof("ufs_eh_wq_00")];
9448
9449         if (!mmio_base) {
9450                 dev_err(hba->dev,
9451                 "Invalid memory reference for mmio_base is NULL\n");
9452                 err = -ENODEV;
9453                 goto out_error;
9454         }
9455
9456         hba->mmio_base = mmio_base;
9457         hba->irq = irq;
9458         hba->vps = &ufs_hba_vps;
9459
9460         err = ufshcd_hba_init(hba);
9461         if (err)
9462                 goto out_error;
9463
9464         /* Read capabilities registers */
9465         err = ufshcd_hba_capabilities(hba);
9466         if (err)
9467                 goto out_disable;
9468
9469         /* Get UFS version supported by the controller */
9470         hba->ufs_version = ufshcd_get_ufs_version(hba);
9471
9472         /* Get Interrupt bit mask per version */
9473         hba->intr_mask = ufshcd_get_intr_mask(hba);
9474
9475         err = ufshcd_set_dma_mask(hba);
9476         if (err) {
9477                 dev_err(hba->dev, "set dma mask failed\n");
9478                 goto out_disable;
9479         }
9480
9481         /* Allocate memory for host memory space */
9482         err = ufshcd_memory_alloc(hba);
9483         if (err) {
9484                 dev_err(hba->dev, "Memory allocation failed\n");
9485                 goto out_disable;
9486         }
9487
9488         /* Configure LRB */
9489         ufshcd_host_memory_configure(hba);
9490
9491         host->can_queue = hba->nutrs;
9492         host->cmd_per_lun = hba->nutrs;
9493         host->max_id = UFSHCD_MAX_ID;
9494         host->max_lun = UFS_MAX_LUNS;
9495         host->max_channel = UFSHCD_MAX_CHANNEL;
9496         host->unique_id = host->host_no;
9497         host->max_cmd_len = UFS_CDB_SIZE;
9498
9499         hba->max_pwr_info.is_valid = false;
9500
9501         /* Initialize work queues */
9502         snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d",
9503                  hba->host->host_no);
9504         hba->eh_wq = create_singlethread_workqueue(eh_wq_name);
9505         if (!hba->eh_wq) {
9506                 dev_err(hba->dev, "%s: failed to create eh workqueue\n",
9507                                 __func__);
9508                 err = -ENOMEM;
9509                 goto out_disable;
9510         }
9511         INIT_WORK(&hba->eh_work, ufshcd_err_handler);
9512         INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
9513
9514         sema_init(&hba->host_sem, 1);
9515
9516         /* Initialize UIC command mutex */
9517         mutex_init(&hba->uic_cmd_mutex);
9518
9519         /* Initialize mutex for device management commands */
9520         mutex_init(&hba->dev_cmd.lock);
9521
9522         /* Initialize mutex for exception event control */
9523         mutex_init(&hba->ee_ctrl_mutex);
9524
9525         init_rwsem(&hba->clk_scaling_lock);
9526
9527         ufshcd_init_clk_gating(hba);
9528
9529         ufshcd_init_clk_scaling(hba);
9530
9531         /*
9532          * In order to avoid any spurious interrupt immediately after
9533          * registering UFS controller interrupt handler, clear any pending UFS
9534          * interrupt status and disable all the UFS interrupts.
9535          */
9536         ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
9537                       REG_INTERRUPT_STATUS);
9538         ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
9539         /*
9540          * Make sure that UFS interrupts are disabled and any pending interrupt
9541          * status is cleared before registering UFS interrupt handler.
9542          */
9543         mb();
9544
9545         /* IRQ registration */
9546         err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
9547         if (err) {
9548                 dev_err(hba->dev, "request irq failed\n");
9549                 goto out_disable;
9550         } else {
9551                 hba->is_irq_enabled = true;
9552         }
9553
9554         err = scsi_add_host(host, hba->dev);
9555         if (err) {
9556                 dev_err(hba->dev, "scsi_add_host failed\n");
9557                 goto out_disable;
9558         }
9559
9560         hba->cmd_queue = blk_mq_init_queue(&hba->host->tag_set);
9561         if (IS_ERR(hba->cmd_queue)) {
9562                 err = PTR_ERR(hba->cmd_queue);
9563                 goto out_remove_scsi_host;
9564         }
9565
9566         hba->tmf_tag_set = (struct blk_mq_tag_set) {
9567                 .nr_hw_queues   = 1,
9568                 .queue_depth    = hba->nutmrs,
9569                 .ops            = &ufshcd_tmf_ops,
9570                 .flags          = BLK_MQ_F_NO_SCHED,
9571         };
9572         err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
9573         if (err < 0)
9574                 goto free_cmd_queue;
9575         hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set);
9576         if (IS_ERR(hba->tmf_queue)) {
9577                 err = PTR_ERR(hba->tmf_queue);
9578                 goto free_tmf_tag_set;
9579         }
9580
9581         /* Reset the attached device */
9582         ufshcd_device_reset(hba);
9583
9584         ufshcd_init_crypto(hba);
9585
9586         /* Host controller enable */
9587         err = ufshcd_hba_enable(hba);
9588         if (err) {
9589                 dev_err(hba->dev, "Host controller enable failed\n");
9590                 ufshcd_print_evt_hist(hba);
9591                 ufshcd_print_host_state(hba);
9592                 goto free_tmf_queue;
9593         }
9594
9595         /*
9596          * Set the default power management level for runtime and system PM.
9597          * Default power saving mode is to keep UFS link in Hibern8 state
9598          * and UFS device in sleep state.
9599          */
9600         hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
9601                                                 UFS_SLEEP_PWR_MODE,
9602                                                 UIC_LINK_HIBERN8_STATE);
9603         hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
9604                                                 UFS_SLEEP_PWR_MODE,
9605                                                 UIC_LINK_HIBERN8_STATE);
9606
9607         INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work,
9608                           ufshcd_rpm_dev_flush_recheck_work);
9609
9610         /* Set the default auto-hiberate idle timer value to 150 ms */
9611         if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
9612                 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
9613                             FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
9614         }
9615
9616         /* Hold auto suspend until async scan completes */
9617         pm_runtime_get_sync(dev);
9618         atomic_set(&hba->scsi_block_reqs_cnt, 0);
9619         /*
9620          * We are assuming that device wasn't put in sleep/power-down
9621          * state exclusively during the boot stage before kernel.
9622          * This assumption helps avoid doing link startup twice during
9623          * ufshcd_probe_hba().
9624          */
9625         ufshcd_set_ufs_dev_active(hba);
9626
9627         async_schedule(ufshcd_async_scan, hba);
9628         ufs_sysfs_add_nodes(hba->dev);
9629
9630         device_enable_async_suspend(dev);
9631         return 0;
9632
9633 free_tmf_queue:
9634         blk_cleanup_queue(hba->tmf_queue);
9635 free_tmf_tag_set:
9636         blk_mq_free_tag_set(&hba->tmf_tag_set);
9637 free_cmd_queue:
9638         blk_cleanup_queue(hba->cmd_queue);
9639 out_remove_scsi_host:
9640         scsi_remove_host(hba->host);
9641 out_disable:
9642         hba->is_irq_enabled = false;
9643         ufshcd_hba_exit(hba);
9644 out_error:
9645         return err;
9646 }
9647 EXPORT_SYMBOL_GPL(ufshcd_init);
9648
9649 void ufshcd_resume_complete(struct device *dev)
9650 {
9651         struct ufs_hba *hba = dev_get_drvdata(dev);
9652
9653         if (hba->complete_put) {
9654                 ufshcd_rpm_put(hba);
9655                 hba->complete_put = false;
9656         }
9657         if (hba->rpmb_complete_put) {
9658                 ufshcd_rpmb_rpm_put(hba);
9659                 hba->rpmb_complete_put = false;
9660         }
9661 }
9662 EXPORT_SYMBOL_GPL(ufshcd_resume_complete);
9663
9664 int ufshcd_suspend_prepare(struct device *dev)
9665 {
9666         struct ufs_hba *hba = dev_get_drvdata(dev);
9667         int ret;
9668
9669         /*
9670          * SCSI assumes that runtime-pm and system-pm for scsi drivers
9671          * are same. And it doesn't wake up the device for system-suspend
9672          * if it's runtime suspended. But ufs doesn't follow that.
9673          * Refer ufshcd_resume_complete()
9674          */
9675         if (hba->sdev_ufs_device) {
9676                 ret = ufshcd_rpm_get_sync(hba);
9677                 if (ret < 0 && ret != -EACCES) {
9678                         ufshcd_rpm_put(hba);
9679                         return ret;
9680                 }
9681                 hba->complete_put = true;
9682         }
9683         if (hba->sdev_rpmb) {
9684                 ufshcd_rpmb_rpm_get_sync(hba);
9685                 hba->rpmb_complete_put = true;
9686         }
9687         return 0;
9688 }
9689 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare);
9690
9691 #ifdef CONFIG_PM_SLEEP
9692 static int ufshcd_wl_poweroff(struct device *dev)
9693 {
9694         struct scsi_device *sdev = to_scsi_device(dev);
9695         struct ufs_hba *hba = shost_priv(sdev->host);
9696
9697         __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
9698         return 0;
9699 }
9700 #endif
9701
9702 static int ufshcd_wl_probe(struct device *dev)
9703 {
9704         struct scsi_device *sdev = to_scsi_device(dev);
9705
9706         if (!is_device_wlun(sdev))
9707                 return -ENODEV;
9708
9709         blk_pm_runtime_init(sdev->request_queue, dev);
9710         pm_runtime_set_autosuspend_delay(dev, 0);
9711         pm_runtime_allow(dev);
9712
9713         return  0;
9714 }
9715
9716 static int ufshcd_wl_remove(struct device *dev)
9717 {
9718         pm_runtime_forbid(dev);
9719         return 0;
9720 }
9721
9722 static const struct dev_pm_ops ufshcd_wl_pm_ops = {
9723 #ifdef CONFIG_PM_SLEEP
9724         .suspend = ufshcd_wl_suspend,
9725         .resume = ufshcd_wl_resume,
9726         .freeze = ufshcd_wl_suspend,
9727         .thaw = ufshcd_wl_resume,
9728         .poweroff = ufshcd_wl_poweroff,
9729         .restore = ufshcd_wl_resume,
9730 #endif
9731         SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL)
9732 };
9733
9734 /*
9735  * ufs_dev_wlun_template - describes ufs device wlun
9736  * ufs-device wlun - used to send pm commands
9737  * All luns are consumers of ufs-device wlun.
9738  *
9739  * Currently, no sd driver is present for wluns.
9740  * Hence the no specific pm operations are performed.
9741  * With ufs design, SSU should be sent to ufs-device wlun.
9742  * Hence register a scsi driver for ufs wluns only.
9743  */
9744 static struct scsi_driver ufs_dev_wlun_template = {
9745         .gendrv = {
9746                 .name = "ufs_device_wlun",
9747                 .owner = THIS_MODULE,
9748                 .probe = ufshcd_wl_probe,
9749                 .remove = ufshcd_wl_remove,
9750                 .pm = &ufshcd_wl_pm_ops,
9751                 .shutdown = ufshcd_wl_shutdown,
9752         },
9753 };
9754
9755 static int ufshcd_rpmb_probe(struct device *dev)
9756 {
9757         return is_rpmb_wlun(to_scsi_device(dev)) ? 0 : -ENODEV;
9758 }
9759
9760 static inline int ufshcd_clear_rpmb_uac(struct ufs_hba *hba)
9761 {
9762         int ret = 0;
9763
9764         if (!hba->wlun_rpmb_clr_ua)
9765                 return 0;
9766         ret = ufshcd_clear_ua_wlun(hba, UFS_UPIU_RPMB_WLUN);
9767         if (!ret)
9768                 hba->wlun_rpmb_clr_ua = 0;
9769         return ret;
9770 }
9771
9772 #ifdef CONFIG_PM
9773 static int ufshcd_rpmb_resume(struct device *dev)
9774 {
9775         struct ufs_hba *hba = wlun_dev_to_hba(dev);
9776
9777         if (hba->sdev_rpmb)
9778                 ufshcd_clear_rpmb_uac(hba);
9779         return 0;
9780 }
9781 #endif
9782
9783 static const struct dev_pm_ops ufs_rpmb_pm_ops = {
9784         SET_RUNTIME_PM_OPS(NULL, ufshcd_rpmb_resume, NULL)
9785         SET_SYSTEM_SLEEP_PM_OPS(NULL, ufshcd_rpmb_resume)
9786 };
9787
9788 /* ufs_rpmb_wlun_template - Describes UFS RPMB WLUN. Used only to send UAC. */
9789 static struct scsi_driver ufs_rpmb_wlun_template = {
9790         .gendrv = {
9791                 .name = "ufs_rpmb_wlun",
9792                 .owner = THIS_MODULE,
9793                 .probe = ufshcd_rpmb_probe,
9794                 .pm = &ufs_rpmb_pm_ops,
9795         },
9796 };
9797
9798 static int __init ufshcd_core_init(void)
9799 {
9800         int ret;
9801
9802         ufs_debugfs_init();
9803
9804         ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv);
9805         if (ret)
9806                 goto debugfs_exit;
9807
9808         ret = scsi_register_driver(&ufs_rpmb_wlun_template.gendrv);
9809         if (ret)
9810                 goto unregister;
9811
9812         return ret;
9813 unregister:
9814         scsi_unregister_driver(&ufs_dev_wlun_template.gendrv);
9815 debugfs_exit:
9816         ufs_debugfs_exit();
9817         return ret;
9818 }
9819
9820 static void __exit ufshcd_core_exit(void)
9821 {
9822         ufs_debugfs_exit();
9823         scsi_unregister_driver(&ufs_rpmb_wlun_template.gendrv);
9824         scsi_unregister_driver(&ufs_dev_wlun_template.gendrv);
9825 }
9826
9827 module_init(ufshcd_core_init);
9828 module_exit(ufshcd_core_exit);
9829
9830 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
9831 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
9832 MODULE_DESCRIPTION("Generic UFS host controller driver Core");
9833 MODULE_LICENSE("GPL");
9834 MODULE_VERSION(UFSHCD_DRIVER_VERSION);