1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Universal Flash Storage Host controller Platform bus based glue driver
4 * Copyright (C) 2011-2013 Samsung India Software Operations
7 * Santosh Yaraganavi <santosh.sy@samsung.com>
8 * Vinayak Holikatti <h.vinayak@samsung.com>
11 #include <linux/platform_device.h>
12 #include <linux/pm_runtime.h>
16 #include "ufshcd-pltfrm.h"
19 #define UFSHCD_DEFAULT_LANES_PER_DIRECTION 2
21 static int ufshcd_parse_clock_info(struct ufs_hba *hba)
26 struct device *dev = hba->dev;
27 struct device_node *np = dev->of_node;
30 struct ufs_clk_info *clki;
37 cnt = of_property_count_strings(np, "clock-names");
38 if (!cnt || (cnt == -EINVAL)) {
39 dev_info(dev, "%s: Unable to find clocks, assuming enabled\n",
42 dev_err(dev, "%s: count clock strings failed, err %d\n",
50 if (!of_get_property(np, "freq-table-hz", &len)) {
51 dev_info(dev, "freq-table-hz property not specified\n");
58 sz = len / sizeof(*clkfreq);
60 dev_err(dev, "%s len mismatch\n", "freq-table-hz");
65 clkfreq = devm_kcalloc(dev, sz, sizeof(*clkfreq),
72 ret = of_property_read_u32_array(np, "freq-table-hz",
74 if (ret && (ret != -EINVAL)) {
75 dev_err(dev, "%s: error reading array %d\n",
76 "freq-table-hz", ret);
80 for (i = 0; i < sz; i += 2) {
81 ret = of_property_read_string_index(np,
82 "clock-names", i/2, (const char **)&name);
86 clki = devm_kzalloc(dev, sizeof(*clki), GFP_KERNEL);
92 clki->min_freq = clkfreq[i];
93 clki->max_freq = clkfreq[i+1];
94 clki->name = kstrdup(name, GFP_KERNEL);
95 dev_dbg(dev, "%s: min %u max %u name %s\n", "freq-table-hz",
96 clki->min_freq, clki->max_freq, clki->name);
97 list_add_tail(&clki->list, &hba->clk_list_head);
103 #define MAX_PROP_SIZE 32
104 static int ufshcd_populate_vreg(struct device *dev, const char *name,
105 struct ufs_vreg **out_vreg)
108 char prop_name[MAX_PROP_SIZE];
109 struct ufs_vreg *vreg = NULL;
110 struct device_node *np = dev->of_node;
113 dev_err(dev, "%s: non DT initialization\n", __func__);
117 snprintf(prop_name, MAX_PROP_SIZE, "%s-supply", name);
118 if (!of_parse_phandle(np, prop_name, 0)) {
119 dev_info(dev, "%s: Unable to find %s regulator, assuming enabled\n",
120 __func__, prop_name);
124 vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL);
128 vreg->name = kstrdup(name, GFP_KERNEL);
130 snprintf(prop_name, MAX_PROP_SIZE, "%s-max-microamp", name);
131 if (of_property_read_u32(np, prop_name, &vreg->max_uA)) {
132 dev_info(dev, "%s: unable to find %s\n", __func__, prop_name);
136 if (!strcmp(name, "vcc")) {
137 if (of_property_read_bool(np, "vcc-supply-1p8")) {
138 vreg->min_uV = UFS_VREG_VCC_1P8_MIN_UV;
139 vreg->max_uV = UFS_VREG_VCC_1P8_MAX_UV;
141 vreg->min_uV = UFS_VREG_VCC_MIN_UV;
142 vreg->max_uV = UFS_VREG_VCC_MAX_UV;
144 } else if (!strcmp(name, "vccq")) {
145 vreg->min_uV = UFS_VREG_VCCQ_MIN_UV;
146 vreg->max_uV = UFS_VREG_VCCQ_MAX_UV;
147 } else if (!strcmp(name, "vccq2")) {
148 vreg->min_uV = UFS_VREG_VCCQ2_MIN_UV;
149 vreg->max_uV = UFS_VREG_VCCQ2_MAX_UV;
161 * ufshcd_parse_regulator_info - get regulator info from device tree
162 * @hba: per adapter instance
164 * Get regulator info from device tree for vcc, vccq, vccq2 power supplies.
165 * If any of the supplies are not defined it is assumed that they are always-on
166 * and hence return zero. If the property is defined but parsing is failed
167 * then return corresponding error.
169 static int ufshcd_parse_regulator_info(struct ufs_hba *hba)
172 struct device *dev = hba->dev;
173 struct ufs_vreg_info *info = &hba->vreg_info;
175 err = ufshcd_populate_vreg(dev, "vdd-hba", &info->vdd_hba);
179 err = ufshcd_populate_vreg(dev, "vcc", &info->vcc);
183 err = ufshcd_populate_vreg(dev, "vccq", &info->vccq);
187 err = ufshcd_populate_vreg(dev, "vccq2", &info->vccq2);
194 * ufshcd_pltfrm_suspend - suspend power management function
195 * @dev: pointer to device handle
197 * Returns 0 if successful
198 * Returns non-zero otherwise
200 int ufshcd_pltfrm_suspend(struct device *dev)
202 return ufshcd_system_suspend(dev_get_drvdata(dev));
204 EXPORT_SYMBOL_GPL(ufshcd_pltfrm_suspend);
207 * ufshcd_pltfrm_resume - resume power management function
208 * @dev: pointer to device handle
210 * Returns 0 if successful
211 * Returns non-zero otherwise
213 int ufshcd_pltfrm_resume(struct device *dev)
215 return ufshcd_system_resume(dev_get_drvdata(dev));
217 EXPORT_SYMBOL_GPL(ufshcd_pltfrm_resume);
219 int ufshcd_pltfrm_runtime_suspend(struct device *dev)
221 return ufshcd_runtime_suspend(dev_get_drvdata(dev));
223 EXPORT_SYMBOL_GPL(ufshcd_pltfrm_runtime_suspend);
225 int ufshcd_pltfrm_runtime_resume(struct device *dev)
227 return ufshcd_runtime_resume(dev_get_drvdata(dev));
229 EXPORT_SYMBOL_GPL(ufshcd_pltfrm_runtime_resume);
231 int ufshcd_pltfrm_runtime_idle(struct device *dev)
233 return ufshcd_runtime_idle(dev_get_drvdata(dev));
235 EXPORT_SYMBOL_GPL(ufshcd_pltfrm_runtime_idle);
237 #endif /* CONFIG_PM */
239 void ufshcd_pltfrm_shutdown(struct platform_device *pdev)
241 ufshcd_shutdown((struct ufs_hba *)platform_get_drvdata(pdev));
243 EXPORT_SYMBOL_GPL(ufshcd_pltfrm_shutdown);
245 static void ufshcd_init_lanes_per_dir(struct ufs_hba *hba)
247 struct device *dev = hba->dev;
250 ret = of_property_read_u32(dev->of_node, "lanes-per-direction",
251 &hba->lanes_per_direction);
254 "%s: failed to read lanes-per-direction, ret=%d\n",
256 hba->lanes_per_direction = UFSHCD_DEFAULT_LANES_PER_DIRECTION;
261 * ufshcd_get_pwr_dev_param - get finally agreed attributes for
263 * @pltfrm_param: pointer to platform parameters
264 * @dev_max: pointer to device attributes
265 * @agreed_pwr: returned agreed attributes
267 * Returns 0 on success, non-zero value on failure
269 int ufshcd_get_pwr_dev_param(struct ufs_dev_params *pltfrm_param,
270 struct ufs_pa_layer_attr *dev_max,
271 struct ufs_pa_layer_attr *agreed_pwr)
275 bool is_dev_sup_hs = false;
276 bool is_pltfrm_max_hs = false;
278 if (dev_max->pwr_rx == FAST_MODE)
279 is_dev_sup_hs = true;
281 if (pltfrm_param->desired_working_mode == UFS_HS_MODE) {
282 is_pltfrm_max_hs = true;
283 min_pltfrm_gear = min_t(u32, pltfrm_param->hs_rx_gear,
284 pltfrm_param->hs_tx_gear);
286 min_pltfrm_gear = min_t(u32, pltfrm_param->pwm_rx_gear,
287 pltfrm_param->pwm_tx_gear);
291 * device doesn't support HS but
292 * pltfrm_param->desired_working_mode is HS,
293 * thus device and pltfrm_param don't agree
295 if (!is_dev_sup_hs && is_pltfrm_max_hs) {
296 pr_info("%s: device doesn't support HS\n",
299 } else if (is_dev_sup_hs && is_pltfrm_max_hs) {
301 * since device supports HS, it supports FAST_MODE.
302 * since pltfrm_param->desired_working_mode is also HS
303 * then final decision (FAST/FASTAUTO) is done according
304 * to pltfrm_params as it is the restricting factor
306 agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_hs;
307 agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
310 * here pltfrm_param->desired_working_mode is PWM.
311 * it doesn't matter whether device supports HS or PWM,
312 * in both cases pltfrm_param->desired_working_mode will
315 agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_pwm;
316 agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
320 * we would like tx to work in the minimum number of lanes
321 * between device capability and vendor preferences.
322 * the same decision will be made for rx
324 agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
325 pltfrm_param->tx_lanes);
326 agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
327 pltfrm_param->rx_lanes);
329 /* device maximum gear is the minimum between device rx and tx gears */
330 min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
333 * if both device capabilities and vendor pre-defined preferences are
334 * both HS or both PWM then set the minimum gear to be the chosen
336 * if one is PWM and one is HS then the one that is PWM get to decide
337 * what is the gear, as it is the one that also decided previously what
338 * pwr the device will be configured to.
340 if ((is_dev_sup_hs && is_pltfrm_max_hs) ||
341 (!is_dev_sup_hs && !is_pltfrm_max_hs)) {
342 agreed_pwr->gear_rx =
343 min_t(u32, min_dev_gear, min_pltfrm_gear);
344 } else if (!is_dev_sup_hs) {
345 agreed_pwr->gear_rx = min_dev_gear;
347 agreed_pwr->gear_rx = min_pltfrm_gear;
349 agreed_pwr->gear_tx = agreed_pwr->gear_rx;
351 agreed_pwr->hs_rate = pltfrm_param->hs_rate;
355 EXPORT_SYMBOL_GPL(ufshcd_get_pwr_dev_param);
358 * ufshcd_pltfrm_init - probe routine of the driver
359 * @pdev: pointer to Platform device handle
360 * @vops: pointer to variant ops
362 * Returns 0 on success, non-zero value on failure
364 int ufshcd_pltfrm_init(struct platform_device *pdev,
365 const struct ufs_hba_variant_ops *vops)
368 void __iomem *mmio_base;
370 struct device *dev = &pdev->dev;
372 mmio_base = devm_platform_ioremap_resource(pdev, 0);
373 if (IS_ERR(mmio_base)) {
374 err = PTR_ERR(mmio_base);
378 irq = platform_get_irq(pdev, 0);
384 err = ufshcd_alloc_host(dev, &hba);
386 dev_err(&pdev->dev, "Allocation failed\n");
392 err = ufshcd_parse_clock_info(hba);
394 dev_err(&pdev->dev, "%s: clock parse failed %d\n",
398 err = ufshcd_parse_regulator_info(hba);
400 dev_err(&pdev->dev, "%s: regulator init failed %d\n",
405 ufshcd_init_lanes_per_dir(hba);
407 err = ufshcd_init(hba, mmio_base, irq);
409 dev_err(dev, "Initialization failed\n");
413 platform_set_drvdata(pdev, hba);
415 pm_runtime_set_active(&pdev->dev);
416 pm_runtime_enable(&pdev->dev);
421 ufshcd_dealloc_host(hba);
425 EXPORT_SYMBOL_GPL(ufshcd_pltfrm_init);
427 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
428 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
429 MODULE_DESCRIPTION("UFS host controller Platform bus based glue driver");
430 MODULE_LICENSE("GPL");
431 MODULE_VERSION(UFSHCD_DRIVER_VERSION);