drivers/scsi/ufs/ufs-qcom.c

   1 /*
   2  * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #include <linux/time.h>
  16 #include <linux/of.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/phy/phy.h>
  19 #include <linux/reset-controller.h>
  20
  21 #include "ufshcd.h"
  22 #include "ufshcd-pltfrm.h"
  23 #include "unipro.h"
  24 #include "ufs-qcom.h"
  25 #include "ufshci.h"
  26 #include "ufs_quirks.h"
  27 #define UFS_QCOM_DEFAULT_DBG_PRINT_EN   \
  28         (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
  29
  30 enum {
  31         TSTBUS_UAWM,
  32         TSTBUS_UARM,
  33         TSTBUS_TXUC,
  34         TSTBUS_RXUC,
  35         TSTBUS_DFC,
  36         TSTBUS_TRLUT,
  37         TSTBUS_TMRLUT,
  38         TSTBUS_OCSC,
  39         TSTBUS_UTP_HCI,
  40         TSTBUS_COMBINED,
  41         TSTBUS_WRAPPER,
  42         TSTBUS_UNIPRO,
  43         TSTBUS_MAX,
  44 };
  45
  46 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
  47
  48 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote);
  49 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
  50 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
  51                                                        u32 clk_cycles);
  52
  53 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
  54 {
  55         return container_of(rcd, struct ufs_qcom_host, rcdev);
  56 }
  57
  58 static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
  59                                        const char *prefix, void *priv)
  60 {
  61         ufshcd_dump_regs(hba, offset, len * 4, prefix);
  62 }
  63
  64 static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
  65 {
  66         int err = 0;
  67
  68         err = ufshcd_dme_get(hba,
  69                         UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes);
  70         if (err)
  71                 dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
  72                                 __func__, err);
  73
  74         return err;
  75 }
  76
  77 static int ufs_qcom_host_clk_get(struct device *dev,
  78                 const char *name, struct clk **clk_out, bool optional)
  79 {
  80         struct clk *clk;
  81         int err = 0;
  82
  83         clk = devm_clk_get(dev, name);
  84         if (!IS_ERR(clk)) {
  85                 *clk_out = clk;
  86                 return 0;
  87         }
  88
  89         err = PTR_ERR(clk);
  90
  91         if (optional && err == -ENOENT) {
  92                 *clk_out = NULL;
  93                 return 0;
  94         }
  95
  96         if (err != -EPROBE_DEFER)
  97                 dev_err(dev, "failed to get %s err %d\n", name, err);
  98
  99         return err;
 100 }
 101
 102 static int ufs_qcom_host_clk_enable(struct device *dev,
 103                 const char *name, struct clk *clk)
 104 {
 105         int err = 0;
 106
 107         err = clk_prepare_enable(clk);
 108         if (err)
 109                 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
 110
 111         return err;
 112 }
 113
 114 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
 115 {
 116         if (!host->is_lane_clks_enabled)
 117                 return;
 118
 119         clk_disable_unprepare(host->tx_l1_sync_clk);
 120         clk_disable_unprepare(host->tx_l0_sync_clk);
 121         clk_disable_unprepare(host->rx_l1_sync_clk);
 122         clk_disable_unprepare(host->rx_l0_sync_clk);
 123
 124         host->is_lane_clks_enabled = false;
 125 }
 126
 127 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
 128 {
 129         int err = 0;
 130         struct device *dev = host->hba->dev;
 131
 132         if (host->is_lane_clks_enabled)
 133                 return 0;
 134
 135         err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
 136                 host->rx_l0_sync_clk);
 137         if (err)
 138                 goto out;
 139
 140         err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
 141                 host->tx_l0_sync_clk);
 142         if (err)
 143                 goto disable_rx_l0;
 144
 145         err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
 146                         host->rx_l1_sync_clk);
 147         if (err)
 148                 goto disable_tx_l0;
 149
 150         err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
 151                         host->tx_l1_sync_clk);
 152         if (err)
 153                 goto disable_rx_l1;
 154
 155         host->is_lane_clks_enabled = true;
 156         goto out;
 157
 158 disable_rx_l1:
 159         clk_disable_unprepare(host->rx_l1_sync_clk);
 160 disable_tx_l0:
 161         clk_disable_unprepare(host->tx_l0_sync_clk);
 162 disable_rx_l0:
 163         clk_disable_unprepare(host->rx_l0_sync_clk);
 164 out:
 165         return err;
 166 }
 167
 168 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
 169 {
 170         int err = 0;
 171         struct device *dev = host->hba->dev;
 172
 173         err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk",
 174                                         &host->rx_l0_sync_clk, false);
 175         if (err)
 176                 goto out;
 177
 178         err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk",
 179                                         &host->tx_l0_sync_clk, false);
 180         if (err)
 181                 goto out;
 182
 183         /* In case of single lane per direction, don't read lane1 clocks */
 184         if (host->hba->lanes_per_direction > 1) {
 185                 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
 186                         &host->rx_l1_sync_clk, false);
 187                 if (err)
 188                         goto out;
 189
 190                 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
 191                         &host->tx_l1_sync_clk, true);
 192         }
 193 out:
 194         return err;
 195 }
 196
 197 static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
 198 {
 199         u32 tx_lanes;
 200
 201         return ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
 202 }
 203
 204 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
 205 {
 206         int err;
 207         u32 tx_fsm_val = 0;
 208         unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
 209
 210         do {
 211                 err = ufshcd_dme_get(hba,
 212                                 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
 213                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
 214                                 &tx_fsm_val);
 215                 if (err || tx_fsm_val == TX_FSM_HIBERN8)
 216                         break;
 217
 218                 /* sleep for max. 200us */
 219                 usleep_range(100, 200);
 220         } while (time_before(jiffies, timeout));
 221
 222         /*
 223          * we might have scheduled out for long during polling so
 224          * check the state again.
 225          */
 226         if (time_after(jiffies, timeout))
 227                 err = ufshcd_dme_get(hba,
 228                                 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
 229                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
 230                                 &tx_fsm_val);
 231
 232         if (err) {
 233                 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
 234                                 __func__, err);
 235         } else if (tx_fsm_val != TX_FSM_HIBERN8) {
 236                 err = tx_fsm_val;
 237                 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
 238                                 __func__, err);
 239         }
 240
 241         return err;
 242 }
 243
 244 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
 245 {
 246         ufshcd_rmwl(host->hba, QUNIPRO_SEL,
 247                    ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
 248                    REG_UFS_CFG1);
 249         /* make sure above configuration is applied before we return */
 250         mb();
 251 }
 252
 253 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
 254 {
 255         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 256         struct phy *phy = host->generic_phy;
 257         int ret = 0;
 258         bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
 259                                                         ? true : false;
 260
 261         if (is_rate_B)
 262                 phy_set_mode(phy, PHY_MODE_UFS_HS_B);
 263
 264         /* phy initialization - calibrate the phy */
 265         ret = phy_init(phy);
 266         if (ret) {
 267                 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
 268                         __func__, ret);
 269                 goto out;
 270         }
 271
 272         /* power on phy - start serdes and phy's power and clocks */
 273         ret = phy_power_on(phy);
 274         if (ret) {
 275                 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
 276                         __func__, ret);
 277                 goto out_disable_phy;
 278         }
 279
 280         ufs_qcom_select_unipro_mode(host);
 281
 282         return 0;
 283
 284 out_disable_phy:
 285         phy_exit(phy);
 286 out:
 287         return ret;
 288 }
 289
 290 /*
 291  * The UTP controller has a number of internal clock gating cells (CGCs).
 292  * Internal hardware sub-modules within the UTP controller control the CGCs.
 293  * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
 294  * in a specific operation, UTP controller CGCs are by default disabled and
 295  * this function enables them (after every UFS link startup) to save some power
 296  * leakage.
 297  */
 298 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
 299 {
 300         ufshcd_writel(hba,
 301                 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
 302                 REG_UFS_CFG2);
 303
 304         /* Ensure that HW clock gating is enabled before next operations */
 305         mb();
 306 }
 307
 308 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
 309                                       enum ufs_notify_change_status status)
 310 {
 311         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 312         int err = 0;
 313
 314         switch (status) {
 315         case PRE_CHANGE:
 316                 ufs_qcom_power_up_sequence(hba);
 317                 /*
 318                  * The PHY PLL output is the source of tx/rx lane symbol
 319                  * clocks, hence, enable the lane clocks only after PHY
 320                  * is initialized.
 321                  */
 322                 err = ufs_qcom_enable_lane_clks(host);
 323                 break;
 324         case POST_CHANGE:
 325                 /* check if UFS PHY moved from DISABLED to HIBERN8 */
 326                 err = ufs_qcom_check_hibern8(hba);
 327                 ufs_qcom_enable_hw_clk_gating(hba);
 328
 329                 break;
 330         default:
 331                 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
 332                 err = -EINVAL;
 333                 break;
 334         }
 335         return err;
 336 }
 337
 338 /**
 339  * Returns zero for success and non-zero in case of a failure
 340  */
 341 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
 342                                u32 hs, u32 rate, bool update_link_startup_timer)
 343 {
 344         int ret = 0;
 345         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 346         struct ufs_clk_info *clki;
 347         u32 core_clk_period_in_ns;
 348         u32 tx_clk_cycles_per_us = 0;
 349         unsigned long core_clk_rate = 0;
 350         u32 core_clk_cycles_per_us = 0;
 351
 352         static u32 pwm_fr_table[][2] = {
 353                 {UFS_PWM_G1, 0x1},
 354                 {UFS_PWM_G2, 0x1},
 355                 {UFS_PWM_G3, 0x1},
 356                 {UFS_PWM_G4, 0x1},
 357         };
 358
 359         static u32 hs_fr_table_rA[][2] = {
 360                 {UFS_HS_G1, 0x1F},
 361                 {UFS_HS_G2, 0x3e},
 362                 {UFS_HS_G3, 0x7D},
 363         };
 364
 365         static u32 hs_fr_table_rB[][2] = {
 366                 {UFS_HS_G1, 0x24},
 367                 {UFS_HS_G2, 0x49},
 368                 {UFS_HS_G3, 0x92},
 369         };
 370
 371         /*
 372          * The Qunipro controller does not use following registers:
 373          * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
 374          * UFS_REG_PA_LINK_STARTUP_TIMER
 375          * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
 376          * Aggregation logic.
 377         */
 378         if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
 379                 goto out;
 380
 381         if (gear == 0) {
 382                 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
 383                 goto out_error;
 384         }
 385
 386         list_for_each_entry(clki, &hba->clk_list_head, list) {
 387                 if (!strcmp(clki->name, "core_clk"))
 388                         core_clk_rate = clk_get_rate(clki->clk);
 389         }
 390
 391         /* If frequency is smaller than 1MHz, set to 1MHz */
 392         if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
 393                 core_clk_rate = DEFAULT_CLK_RATE_HZ;
 394
 395         core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
 396         if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
 397                 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
 398                 /*
 399                  * make sure above write gets applied before we return from
 400                  * this function.
 401                  */
 402                 mb();
 403         }
 404
 405         if (ufs_qcom_cap_qunipro(host))
 406                 goto out;
 407
 408         core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
 409         core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
 410         core_clk_period_in_ns &= MASK_CLK_NS_REG;
 411
 412         switch (hs) {
 413         case FASTAUTO_MODE:
 414         case FAST_MODE:
 415                 if (rate == PA_HS_MODE_A) {
 416                         if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
 417                                 dev_err(hba->dev,
 418                                         "%s: index %d exceeds table size %zu\n",
 419                                         __func__, gear,
 420                                         ARRAY_SIZE(hs_fr_table_rA));
 421                                 goto out_error;
 422                         }
 423                         tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
 424                 } else if (rate == PA_HS_MODE_B) {
 425                         if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
 426                                 dev_err(hba->dev,
 427                                         "%s: index %d exceeds table size %zu\n",
 428                                         __func__, gear,
 429                                         ARRAY_SIZE(hs_fr_table_rB));
 430                                 goto out_error;
 431                         }
 432                         tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
 433                 } else {
 434                         dev_err(hba->dev, "%s: invalid rate = %d\n",
 435                                 __func__, rate);
 436                         goto out_error;
 437                 }
 438                 break;
 439         case SLOWAUTO_MODE:
 440         case SLOW_MODE:
 441                 if (gear > ARRAY_SIZE(pwm_fr_table)) {
 442                         dev_err(hba->dev,
 443                                         "%s: index %d exceeds table size %zu\n",
 444                                         __func__, gear,
 445                                         ARRAY_SIZE(pwm_fr_table));
 446                         goto out_error;
 447                 }
 448                 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
 449                 break;
 450         case UNCHANGED:
 451         default:
 452                 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
 453                 goto out_error;
 454         }
 455
 456         if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
 457             (core_clk_period_in_ns | tx_clk_cycles_per_us)) {
 458                 /* this register 2 fields shall be written at once */
 459                 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
 460                               REG_UFS_TX_SYMBOL_CLK_NS_US);
 461                 /*
 462                  * make sure above write gets applied before we return from
 463                  * this function.
 464                  */
 465                 mb();
 466         }
 467
 468         if (update_link_startup_timer) {
 469                 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
 470                               REG_UFS_PA_LINK_STARTUP_TIMER);
 471                 /*
 472                  * make sure that this configuration is applied before
 473                  * we return
 474                  */
 475                 mb();
 476         }
 477         goto out;
 478
 479 out_error:
 480         ret = -EINVAL;
 481 out:
 482         return ret;
 483 }
 484
 485 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
 486                                         enum ufs_notify_change_status status)
 487 {
 488         int err = 0;
 489         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 490
 491         switch (status) {
 492         case PRE_CHANGE:
 493                 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
 494                                         0, true)) {
 495                         dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
 496                                 __func__);
 497                         err = -EINVAL;
 498                         goto out;
 499                 }
 500
 501                 if (ufs_qcom_cap_qunipro(host))
 502                         /*
 503                          * set unipro core clock cycles to 150 & clear clock
 504                          * divider
 505                          */
 506                         err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
 507                                                                           150);
 508
 509                 /*
 510                  * Some UFS devices (and may be host) have issues if LCC is
 511                  * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
 512                  * before link startup which will make sure that both host
 513                  * and device TX LCC are disabled once link startup is
 514                  * completed.
 515                  */
 516                 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
 517                         err = ufshcd_dme_set(hba,
 518                                         UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE),
 519                                         0);
 520
 521                 break;
 522         case POST_CHANGE:
 523                 ufs_qcom_link_startup_post_change(hba);
 524                 break;
 525         default:
 526                 break;
 527         }
 528
 529 out:
 530         return err;
 531 }
 532
 533 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 534 {
 535         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 536         struct phy *phy = host->generic_phy;
 537         int ret = 0;
 538
 539         if (ufs_qcom_is_link_off(hba)) {
 540                 /*
 541                  * Disable the tx/rx lane symbol clocks before PHY is
 542                  * powered down as the PLL source should be disabled
 543                  * after downstream clocks are disabled.
 544                  */
 545                 ufs_qcom_disable_lane_clks(host);
 546                 phy_power_off(phy);
 547
 548         } else if (!ufs_qcom_is_link_active(hba)) {
 549                 ufs_qcom_disable_lane_clks(host);
 550         }
 551
 552         return ret;
 553 }
 554
 555 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 556 {
 557         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 558         struct phy *phy = host->generic_phy;
 559         int err;
 560
 561         if (ufs_qcom_is_link_off(hba)) {
 562                 err = phy_power_on(phy);
 563                 if (err) {
 564                         dev_err(hba->dev, "%s: failed PHY power on: %d\n",
 565                                 __func__, err);
 566                         return err;
 567                 }
 568
 569                 err = ufs_qcom_enable_lane_clks(host);
 570                 if (err)
 571                         return err;
 572
 573         } else if (!ufs_qcom_is_link_active(hba)) {
 574                 err = ufs_qcom_enable_lane_clks(host);
 575                 if (err)
 576                         return err;
 577         }
 578
 579         hba->is_sys_suspended = false;
 580         return 0;
 581 }
 582
 583 struct ufs_qcom_dev_params {
 584         u32 pwm_rx_gear;        /* pwm rx gear to work in */
 585         u32 pwm_tx_gear;        /* pwm tx gear to work in */
 586         u32 hs_rx_gear;         /* hs rx gear to work in */
 587         u32 hs_tx_gear;         /* hs tx gear to work in */
 588         u32 rx_lanes;           /* number of rx lanes */
 589         u32 tx_lanes;           /* number of tx lanes */
 590         u32 rx_pwr_pwm;         /* rx pwm working pwr */
 591         u32 tx_pwr_pwm;         /* tx pwm working pwr */
 592         u32 rx_pwr_hs;          /* rx hs working pwr */
 593         u32 tx_pwr_hs;          /* tx hs working pwr */
 594         u32 hs_rate;            /* rate A/B to work in HS */
 595         u32 desired_working_mode;
 596 };
 597
 598 static int ufs_qcom_get_pwr_dev_param(struct ufs_qcom_dev_params *qcom_param,
 599                                       struct ufs_pa_layer_attr *dev_max,
 600                                       struct ufs_pa_layer_attr *agreed_pwr)
 601 {
 602         int min_qcom_gear;
 603         int min_dev_gear;
 604         bool is_dev_sup_hs = false;
 605         bool is_qcom_max_hs = false;
 606
 607         if (dev_max->pwr_rx == FAST_MODE)
 608                 is_dev_sup_hs = true;
 609
 610         if (qcom_param->desired_working_mode == FAST) {
 611                 is_qcom_max_hs = true;
 612                 min_qcom_gear = min_t(u32, qcom_param->hs_rx_gear,
 613                                       qcom_param->hs_tx_gear);
 614         } else {
 615                 min_qcom_gear = min_t(u32, qcom_param->pwm_rx_gear,
 616                                       qcom_param->pwm_tx_gear);
 617         }
 618
 619         /*
 620          * device doesn't support HS but qcom_param->desired_working_mode is
 621          * HS, thus device and qcom_param don't agree
 622          */
 623         if (!is_dev_sup_hs && is_qcom_max_hs) {
 624                 pr_err("%s: failed to agree on power mode (device doesn't support HS but requested power is HS)\n",
 625                         __func__);
 626                 return -ENOTSUPP;
 627         } else if (is_dev_sup_hs && is_qcom_max_hs) {
 628                 /*
 629                  * since device supports HS, it supports FAST_MODE.
 630                  * since qcom_param->desired_working_mode is also HS
 631                  * then final decision (FAST/FASTAUTO) is done according
 632                  * to qcom_params as it is the restricting factor
 633                  */
 634                 agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
 635                                                 qcom_param->rx_pwr_hs;
 636         } else {
 637                 /*
 638                  * here qcom_param->desired_working_mode is PWM.
 639                  * it doesn't matter whether device supports HS or PWM,
 640                  * in both cases qcom_param->desired_working_mode will
 641                  * determine the mode
 642                  */
 643                  agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
 644                                                 qcom_param->rx_pwr_pwm;
 645         }
 646
 647         /*
 648          * we would like tx to work in the minimum number of lanes
 649          * between device capability and vendor preferences.
 650          * the same decision will be made for rx
 651          */
 652         agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
 653                                                 qcom_param->tx_lanes);
 654         agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
 655                                                 qcom_param->rx_lanes);
 656
 657         /* device maximum gear is the minimum between device rx and tx gears */
 658         min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
 659
 660         /*
 661          * if both device capabilities and vendor pre-defined preferences are
 662          * both HS or both PWM then set the minimum gear to be the chosen
 663          * working gear.
 664          * if one is PWM and one is HS then the one that is PWM get to decide
 665          * what is the gear, as it is the one that also decided previously what
 666          * pwr the device will be configured to.
 667          */
 668         if ((is_dev_sup_hs && is_qcom_max_hs) ||
 669             (!is_dev_sup_hs && !is_qcom_max_hs))
 670                 agreed_pwr->gear_rx = agreed_pwr->gear_tx =
 671                         min_t(u32, min_dev_gear, min_qcom_gear);
 672         else if (!is_dev_sup_hs)
 673                 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_dev_gear;
 674         else
 675                 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_qcom_gear;
 676
 677         agreed_pwr->hs_rate = qcom_param->hs_rate;
 678         return 0;
 679 }
 680
 681 #ifdef CONFIG_MSM_BUS_SCALING
 682 static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
 683                 const char *speed_mode)
 684 {
 685         struct device *dev = host->hba->dev;
 686         struct device_node *np = dev->of_node;
 687         int err;
 688         const char *key = "qcom,bus-vector-names";
 689
 690         if (!speed_mode) {
 691                 err = -EINVAL;
 692                 goto out;
 693         }
 694
 695         if (host->bus_vote.is_max_bw_needed && !!strcmp(speed_mode, "MIN"))
 696                 err = of_property_match_string(np, key, "MAX");
 697         else
 698                 err = of_property_match_string(np, key, speed_mode);
 699
 700 out:
 701         if (err < 0)
 702                 dev_err(dev, "%s: Invalid %s mode %d\n",
 703                                 __func__, speed_mode, err);
 704         return err;
 705 }
 706
 707 static void ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result)
 708 {
 709         int gear = max_t(u32, p->gear_rx, p->gear_tx);
 710         int lanes = max_t(u32, p->lane_rx, p->lane_tx);
 711         int pwr;
 712
 713         /* default to PWM Gear 1, Lane 1 if power mode is not initialized */
 714         if (!gear)
 715                 gear = 1;
 716
 717         if (!lanes)
 718                 lanes = 1;
 719
 720         if (!p->pwr_rx && !p->pwr_tx) {
 721                 pwr = SLOWAUTO_MODE;
 722                 snprintf(result, BUS_VECTOR_NAME_LEN, "MIN");
 723         } else if (p->pwr_rx == FAST_MODE || p->pwr_rx == FASTAUTO_MODE ||
 724                  p->pwr_tx == FAST_MODE || p->pwr_tx == FASTAUTO_MODE) {
 725                 pwr = FAST_MODE;
 726                 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_R%s_G%d_L%d", "HS",
 727                          p->hs_rate == PA_HS_MODE_B ? "B" : "A", gear, lanes);
 728         } else {
 729                 pwr = SLOW_MODE;
 730                 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_G%d_L%d",
 731                          "PWM", gear, lanes);
 732         }
 733 }
 734
 735 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
 736 {
 737         int err = 0;
 738
 739         if (vote != host->bus_vote.curr_vote) {
 740                 err = msm_bus_scale_client_update_request(
 741                                 host->bus_vote.client_handle, vote);
 742                 if (err) {
 743                         dev_err(host->hba->dev,
 744                                 "%s: msm_bus_scale_client_update_request() failed: bus_client_handle=0x%x, vote=%d, err=%d\n",
 745                                 __func__, host->bus_vote.client_handle,
 746                                 vote, err);
 747                         goto out;
 748                 }
 749
 750                 host->bus_vote.curr_vote = vote;
 751         }
 752 out:
 753         return err;
 754 }
 755
 756 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
 757 {
 758         int vote;
 759         int err = 0;
 760         char mode[BUS_VECTOR_NAME_LEN];
 761
 762         ufs_qcom_get_speed_mode(&host->dev_req_params, mode);
 763
 764         vote = ufs_qcom_get_bus_vote(host, mode);
 765         if (vote >= 0)
 766                 err = ufs_qcom_set_bus_vote(host, vote);
 767         else
 768                 err = vote;
 769
 770         if (err)
 771                 dev_err(host->hba->dev, "%s: failed %d\n", __func__, err);
 772         else
 773                 host->bus_vote.saved_vote = vote;
 774         return err;
 775 }
 776
 777 static ssize_t
 778 show_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
 779                         char *buf)
 780 {
 781         struct ufs_hba *hba = dev_get_drvdata(dev);
 782         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 783
 784         return snprintf(buf, PAGE_SIZE, "%u\n",
 785                         host->bus_vote.is_max_bw_needed);
 786 }
 787
 788 static ssize_t
 789 store_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
 790                 const char *buf, size_t count)
 791 {
 792         struct ufs_hba *hba = dev_get_drvdata(dev);
 793         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 794         uint32_t value;
 795
 796         if (!kstrtou32(buf, 0, &value)) {
 797                 host->bus_vote.is_max_bw_needed = !!value;
 798                 ufs_qcom_update_bus_bw_vote(host);
 799         }
 800
 801         return count;
 802 }
 803
 804 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
 805 {
 806         int err;
 807         struct msm_bus_scale_pdata *bus_pdata;
 808         struct device *dev = host->hba->dev;
 809         struct platform_device *pdev = to_platform_device(dev);
 810         struct device_node *np = dev->of_node;
 811
 812         bus_pdata = msm_bus_cl_get_pdata(pdev);
 813         if (!bus_pdata) {
 814                 dev_err(dev, "%s: failed to get bus vectors\n", __func__);
 815                 err = -ENODATA;
 816                 goto out;
 817         }
 818
 819         err = of_property_count_strings(np, "qcom,bus-vector-names");
 820         if (err < 0 || err != bus_pdata->num_usecases) {
 821                 dev_err(dev, "%s: qcom,bus-vector-names not specified correctly %d\n",
 822                                 __func__, err);
 823                 goto out;
 824         }
 825
 826         host->bus_vote.client_handle = msm_bus_scale_register_client(bus_pdata);
 827         if (!host->bus_vote.client_handle) {
 828                 dev_err(dev, "%s: msm_bus_scale_register_client failed\n",
 829                                 __func__);
 830                 err = -EFAULT;
 831                 goto out;
 832         }
 833
 834         /* cache the vote index for minimum and maximum bandwidth */
 835         host->bus_vote.min_bw_vote = ufs_qcom_get_bus_vote(host, "MIN");
 836         host->bus_vote.max_bw_vote = ufs_qcom_get_bus_vote(host, "MAX");
 837
 838         host->bus_vote.max_bus_bw.show = show_ufs_to_mem_max_bus_bw;
 839         host->bus_vote.max_bus_bw.store = store_ufs_to_mem_max_bus_bw;
 840         sysfs_attr_init(&host->bus_vote.max_bus_bw.attr);
 841         host->bus_vote.max_bus_bw.attr.name = "max_bus_bw";
 842         host->bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR;
 843         err = device_create_file(dev, &host->bus_vote.max_bus_bw);
 844 out:
 845         return err;
 846 }
 847 #else /* CONFIG_MSM_BUS_SCALING */
 848 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
 849 {
 850         return 0;
 851 }
 852
 853 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
 854 {
 855         return 0;
 856 }
 857
 858 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
 859 {
 860         return 0;
 861 }
 862 #endif /* CONFIG_MSM_BUS_SCALING */
 863
 864 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
 865 {
 866         if (host->dev_ref_clk_ctrl_mmio &&
 867             (enable ^ host->is_dev_ref_clk_enabled)) {
 868                 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
 869
 870                 if (enable)
 871                         temp |= host->dev_ref_clk_en_mask;
 872                 else
 873                         temp &= ~host->dev_ref_clk_en_mask;
 874
 875                 /*
 876                  * If we are here to disable this clock it might be immediately
 877                  * after entering into hibern8 in which case we need to make
 878                  * sure that device ref_clk is active at least 1us after the
 879                  * hibern8 enter.
 880                  */
 881                 if (!enable)
 882                         udelay(1);
 883
 884                 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
 885
 886                 /* ensure that ref_clk is enabled/disabled before we return */
 887                 wmb();
 888
 889                 /*
 890                  * If we call hibern8 exit after this, we need to make sure that
 891                  * device ref_clk is stable for at least 1us before the hibern8
 892                  * exit command.
 893                  */
 894                 if (enable)
 895                         udelay(1);
 896
 897                 host->is_dev_ref_clk_enabled = enable;
 898         }
 899 }
 900
 901 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
 902                                 enum ufs_notify_change_status status,
 903                                 struct ufs_pa_layer_attr *dev_max_params,
 904                                 struct ufs_pa_layer_attr *dev_req_params)
 905 {
 906         u32 val;
 907         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 908         struct ufs_qcom_dev_params ufs_qcom_cap;
 909         int ret = 0;
 910
 911         if (!dev_req_params) {
 912                 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
 913                 ret = -EINVAL;
 914                 goto out;
 915         }
 916
 917         switch (status) {
 918         case PRE_CHANGE:
 919                 ufs_qcom_cap.tx_lanes = UFS_QCOM_LIMIT_NUM_LANES_TX;
 920                 ufs_qcom_cap.rx_lanes = UFS_QCOM_LIMIT_NUM_LANES_RX;
 921                 ufs_qcom_cap.hs_rx_gear = UFS_QCOM_LIMIT_HSGEAR_RX;
 922                 ufs_qcom_cap.hs_tx_gear = UFS_QCOM_LIMIT_HSGEAR_TX;
 923                 ufs_qcom_cap.pwm_rx_gear = UFS_QCOM_LIMIT_PWMGEAR_RX;
 924                 ufs_qcom_cap.pwm_tx_gear = UFS_QCOM_LIMIT_PWMGEAR_TX;
 925                 ufs_qcom_cap.rx_pwr_pwm = UFS_QCOM_LIMIT_RX_PWR_PWM;
 926                 ufs_qcom_cap.tx_pwr_pwm = UFS_QCOM_LIMIT_TX_PWR_PWM;
 927                 ufs_qcom_cap.rx_pwr_hs = UFS_QCOM_LIMIT_RX_PWR_HS;
 928                 ufs_qcom_cap.tx_pwr_hs = UFS_QCOM_LIMIT_TX_PWR_HS;
 929                 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
 930                 ufs_qcom_cap.desired_working_mode =
 931                                         UFS_QCOM_LIMIT_DESIRED_MODE;
 932
 933                 if (host->hw_ver.major == 0x1) {
 934                         /*
 935                          * HS-G3 operations may not reliably work on legacy QCOM
 936                          * UFS host controller hardware even though capability
 937                          * exchange during link startup phase may end up
 938                          * negotiating maximum supported gear as G3.
 939                          * Hence downgrade the maximum supported gear to HS-G2.
 940                          */
 941                         if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2)
 942                                 ufs_qcom_cap.hs_tx_gear = UFS_HS_G2;
 943                         if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2)
 944                                 ufs_qcom_cap.hs_rx_gear = UFS_HS_G2;
 945                 }
 946
 947                 ret = ufs_qcom_get_pwr_dev_param(&ufs_qcom_cap,
 948                                                  dev_max_params,
 949                                                  dev_req_params);
 950                 if (ret) {
 951                         pr_err("%s: failed to determine capabilities\n",
 952                                         __func__);
 953                         goto out;
 954                 }
 955
 956                 /* enable the device ref clock before changing to HS mode */
 957                 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
 958                         ufshcd_is_hs_mode(dev_req_params))
 959                         ufs_qcom_dev_ref_clk_ctrl(host, true);
 960                 break;
 961         case POST_CHANGE:
 962                 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
 963                                         dev_req_params->pwr_rx,
 964                                         dev_req_params->hs_rate, false)) {
 965                         dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
 966                                 __func__);
 967                         /*
 968                          * we return error code at the end of the routine,
 969                          * but continue to configure UFS_PHY_TX_LANE_ENABLE
 970                          * and bus voting as usual
 971                          */
 972                         ret = -EINVAL;
 973                 }
 974
 975                 val = ~(MAX_U32 << dev_req_params->lane_tx);
 976
 977                 /* cache the power mode parameters to use internally */
 978                 memcpy(&host->dev_req_params,
 979                                 dev_req_params, sizeof(*dev_req_params));
 980                 ufs_qcom_update_bus_bw_vote(host);
 981
 982                 /* disable the device ref clock if entered PWM mode */
 983                 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
 984                         !ufshcd_is_hs_mode(dev_req_params))
 985                         ufs_qcom_dev_ref_clk_ctrl(host, false);
 986                 break;
 987         default:
 988                 ret = -EINVAL;
 989                 break;
 990         }
 991 out:
 992         return ret;
 993 }
 994
 995 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
 996 {
 997         int err;
 998         u32 pa_vs_config_reg1;
 999
1000         err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
1001                              &pa_vs_config_reg1);
1002         if (err)
1003                 goto out;
1004
1005         /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
1006         err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
1007                             (pa_vs_config_reg1 | (1 << 12)));
1008
1009 out:
1010         return err;
1011 }
1012
1013 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
1014 {
1015         int err = 0;
1016
1017         if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
1018                 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
1019
1020         return err;
1021 }
1022
1023 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
1024 {
1025         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1026
1027         if (host->hw_ver.major == 0x1)
1028                 return UFSHCI_VERSION_11;
1029         else
1030                 return UFSHCI_VERSION_20;
1031 }
1032
1033 /**
1034  * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
1035  * @hba: host controller instance
1036  *
1037  * QCOM UFS host controller might have some non standard behaviours (quirks)
1038  * than what is specified by UFSHCI specification. Advertise all such
1039  * quirks to standard UFS host controller driver so standard takes them into
1040  * account.
1041  */
1042 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
1043 {
1044         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1045
1046         if (host->hw_ver.major == 0x01) {
1047                 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1048                             | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
1049                             | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
1050
1051                 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
1052                         hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
1053
1054                 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
1055         }
1056
1057         if (host->hw_ver.major == 0x2) {
1058                 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
1059
1060                 if (!ufs_qcom_cap_qunipro(host))
1061                         /* Legacy UniPro mode still need following quirks */
1062                         hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1063                                 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
1064                                 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
1065         }
1066 }
1067
1068 static void ufs_qcom_set_caps(struct ufs_hba *hba)
1069 {
1070         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1071
1072         hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1073         hba->caps |= UFSHCD_CAP_CLK_SCALING;
1074         hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1075
1076         if (host->hw_ver.major >= 0x2) {
1077                 host->caps = UFS_QCOM_CAP_QUNIPRO |
1078                              UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE;
1079         }
1080 }
1081
1082 /**
1083  * ufs_qcom_setup_clocks - enables/disable clocks
1084  * @hba: host controller instance
1085  * @on: If true, enable clocks else disable them.
1086  * @status: PRE_CHANGE or POST_CHANGE notify
1087  *
1088  * Returns 0 on success, non-zero on failure.
1089  */
1090 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
1091                                  enum ufs_notify_change_status status)
1092 {
1093         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1094         int err;
1095         int vote = 0;
1096
1097         /*
1098          * In case ufs_qcom_init() is not yet done, simply ignore.
1099          * This ufs_qcom_setup_clocks() shall be called from
1100          * ufs_qcom_init() after init is done.
1101          */
1102         if (!host)
1103                 return 0;
1104
1105         if (on && (status == POST_CHANGE)) {
1106                 /* enable the device ref clock for HS mode*/
1107                 if (ufshcd_is_hs_mode(&hba->pwr_info))
1108                         ufs_qcom_dev_ref_clk_ctrl(host, true);
1109                 vote = host->bus_vote.saved_vote;
1110                 if (vote == host->bus_vote.min_bw_vote)
1111                         ufs_qcom_update_bus_bw_vote(host);
1112
1113         } else if (!on && (status == PRE_CHANGE)) {
1114                 if (!ufs_qcom_is_link_active(hba)) {
1115                         /* disable device ref_clk */
1116                         ufs_qcom_dev_ref_clk_ctrl(host, false);
1117                 }
1118
1119                 vote = host->bus_vote.min_bw_vote;
1120         }
1121
1122         err = ufs_qcom_set_bus_vote(host, vote);
1123         if (err)
1124                 dev_err(hba->dev, "%s: set bus vote failed %d\n",
1125                                 __func__, err);
1126
1127         return err;
1128 }
1129
1130 static int
1131 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
1132 {
1133         struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1134
1135         /* Currently this code only knows about a single reset. */
1136         WARN_ON(id);
1137         ufs_qcom_assert_reset(host->hba);
1138         /* provide 1ms delay to let the reset pulse propagate. */
1139         usleep_range(1000, 1100);
1140         return 0;
1141 }
1142
1143 static int
1144 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
1145 {
1146         struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1147
1148         /* Currently this code only knows about a single reset. */
1149         WARN_ON(id);
1150         ufs_qcom_deassert_reset(host->hba);
1151
1152         /*
1153          * after reset deassertion, phy will need all ref clocks,
1154          * voltage, current to settle down before starting serdes.
1155          */
1156         usleep_range(1000, 1100);
1157         return 0;
1158 }
1159
1160 static const struct reset_control_ops ufs_qcom_reset_ops = {
1161         .assert = ufs_qcom_reset_assert,
1162         .deassert = ufs_qcom_reset_deassert,
1163 };
1164
1165 #define ANDROID_BOOT_DEV_MAX    30
1166 static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
1167
1168 #ifndef MODULE
1169 static int __init get_android_boot_dev(char *str)
1170 {
1171         strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX);
1172         return 1;
1173 }
1174 __setup("androidboot.bootdevice=", get_android_boot_dev);
1175 #endif
1176
1177 /**
1178  * ufs_qcom_init - bind phy with controller
1179  * @hba: host controller instance
1180  *
1181  * Binds PHY with controller and powers up PHY enabling clocks
1182  * and regulators.
1183  *
1184  * Returns -EPROBE_DEFER if binding fails, returns negative error
1185  * on phy power up failure and returns zero on success.
1186  */
1187 static int ufs_qcom_init(struct ufs_hba *hba)
1188 {
1189         int err;
1190         struct device *dev = hba->dev;
1191         struct platform_device *pdev = to_platform_device(dev);
1192         struct ufs_qcom_host *host;
1193         struct resource *res;
1194
1195         if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
1196                 return -ENODEV;
1197
1198         host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1199         if (!host) {
1200                 err = -ENOMEM;
1201                 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
1202                 goto out;
1203         }
1204
1205         /* Make a two way bind between the qcom host and the hba */
1206         host->hba = hba;
1207         ufshcd_set_variant(hba, host);
1208
1209         /* Fire up the reset controller. Failure here is non-fatal. */
1210         host->rcdev.of_node = dev->of_node;
1211         host->rcdev.ops = &ufs_qcom_reset_ops;
1212         host->rcdev.owner = dev->driver->owner;
1213         host->rcdev.nr_resets = 1;
1214         err = devm_reset_controller_register(dev, &host->rcdev);
1215         if (err) {
1216                 dev_warn(dev, "Failed to register reset controller\n");
1217                 err = 0;
1218         }
1219
1220         /*
1221          * voting/devoting device ref_clk source is time consuming hence
1222          * skip devoting it during aggressive clock gating. This clock
1223          * will still be gated off during runtime suspend.
1224          */
1225         host->generic_phy = devm_phy_get(dev, "ufsphy");
1226
1227         if (host->generic_phy == ERR_PTR(-EPROBE_DEFER)) {
1228                 /*
1229                  * UFS driver might be probed before the phy driver does.
1230                  * In that case we would like to return EPROBE_DEFER code.
1231                  */
1232                 err = -EPROBE_DEFER;
1233                 dev_warn(dev, "%s: required phy device. hasn't probed yet. err = %d\n",
1234                         __func__, err);
1235                 goto out_variant_clear;
1236         } else if (IS_ERR(host->generic_phy)) {
1237                 err = PTR_ERR(host->generic_phy);
1238                 dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
1239                 goto out_variant_clear;
1240         }
1241
1242         err = ufs_qcom_bus_register(host);
1243         if (err)
1244                 goto out_variant_clear;
1245
1246         ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1247                 &host->hw_ver.minor, &host->hw_ver.step);
1248
1249         /*
1250          * for newer controllers, device reference clock control bit has
1251          * moved inside UFS controller register address space itself.
1252          */
1253         if (host->hw_ver.major >= 0x02) {
1254                 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1255                 host->dev_ref_clk_en_mask = BIT(26);
1256         } else {
1257                 /* "dev_ref_clk_ctrl_mem" is optional resource */
1258                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1259                 if (res) {
1260                         host->dev_ref_clk_ctrl_mmio =
1261                                         devm_ioremap_resource(dev, res);
1262                         if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) {
1263                                 dev_warn(dev,
1264                                         "%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n",
1265                                         __func__,
1266                                         PTR_ERR(host->dev_ref_clk_ctrl_mmio));
1267                                 host->dev_ref_clk_ctrl_mmio = NULL;
1268                         }
1269                         host->dev_ref_clk_en_mask = BIT(5);
1270                 }
1271         }
1272
1273         err = ufs_qcom_init_lane_clks(host);
1274         if (err)
1275                 goto out_variant_clear;
1276
1277         ufs_qcom_set_caps(hba);
1278         ufs_qcom_advertise_quirks(hba);
1279
1280         ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1281
1282         if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
1283                 ufs_qcom_hosts[hba->dev->id] = host;
1284
1285         host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
1286         ufs_qcom_get_default_testbus_cfg(host);
1287         err = ufs_qcom_testbus_config(host);
1288         if (err) {
1289                 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1290                                 __func__, err);
1291                 err = 0;
1292         }
1293
1294         goto out;
1295
1296 out_variant_clear:
1297         ufshcd_set_variant(hba, NULL);
1298 out:
1299         return err;
1300 }
1301
1302 static void ufs_qcom_exit(struct ufs_hba *hba)
1303 {
1304         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1305
1306         ufs_qcom_disable_lane_clks(host);
1307         phy_power_off(host->generic_phy);
1308         phy_exit(host->generic_phy);
1309 }
1310
1311 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
1312                                                        u32 clk_cycles)
1313 {
1314         int err;
1315         u32 core_clk_ctrl_reg;
1316
1317         if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
1318                 return -EINVAL;
1319
1320         err = ufshcd_dme_get(hba,
1321                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1322                             &core_clk_ctrl_reg);
1323         if (err)
1324                 goto out;
1325
1326         core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
1327         core_clk_ctrl_reg |= clk_cycles;
1328
1329         /* Clear CORE_CLK_DIV_EN */
1330         core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1331
1332         err = ufshcd_dme_set(hba,
1333                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1334                             core_clk_ctrl_reg);
1335 out:
1336         return err;
1337 }
1338
1339 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1340 {
1341         /* nothing to do as of now */
1342         return 0;
1343 }
1344
1345 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1346 {
1347         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1348
1349         if (!ufs_qcom_cap_qunipro(host))
1350                 return 0;
1351
1352         /* set unipro core clock cycles to 150 and clear clock divider */
1353         return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);
1354 }
1355
1356 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1357 {
1358         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1359         int err;
1360         u32 core_clk_ctrl_reg;
1361
1362         if (!ufs_qcom_cap_qunipro(host))
1363                 return 0;
1364
1365         err = ufshcd_dme_get(hba,
1366                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1367                             &core_clk_ctrl_reg);
1368
1369         /* make sure CORE_CLK_DIV_EN is cleared */
1370         if (!err &&
1371             (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1372                 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1373                 err = ufshcd_dme_set(hba,
1374                                     UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1375                                     core_clk_ctrl_reg);
1376         }
1377
1378         return err;
1379 }
1380
1381 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1382 {
1383         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1384
1385         if (!ufs_qcom_cap_qunipro(host))
1386                 return 0;
1387
1388         /* set unipro core clock cycles to 75 and clear clock divider */
1389         return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);
1390 }
1391
1392 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1393                 bool scale_up, enum ufs_notify_change_status status)
1394 {
1395         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1396         struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1397         int err = 0;
1398
1399         if (status == PRE_CHANGE) {
1400                 if (scale_up)
1401                         err = ufs_qcom_clk_scale_up_pre_change(hba);
1402                 else
1403                         err = ufs_qcom_clk_scale_down_pre_change(hba);
1404         } else {
1405                 if (scale_up)
1406                         err = ufs_qcom_clk_scale_up_post_change(hba);
1407                 else
1408                         err = ufs_qcom_clk_scale_down_post_change(hba);
1409
1410                 if (err || !dev_req_params)
1411                         goto out;
1412
1413                 ufs_qcom_cfg_timers(hba,
1414                                     dev_req_params->gear_rx,
1415                                     dev_req_params->pwr_rx,
1416                                     dev_req_params->hs_rate,
1417                                     false);
1418                 ufs_qcom_update_bus_bw_vote(host);
1419         }
1420
1421 out:
1422         return err;
1423 }
1424
1425 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
1426                 void *priv, void (*print_fn)(struct ufs_hba *hba,
1427                 int offset, int num_regs, const char *str, void *priv))
1428 {
1429         u32 reg;
1430         struct ufs_qcom_host *host;
1431
1432         if (unlikely(!hba)) {
1433                 pr_err("%s: hba is NULL\n", __func__);
1434                 return;
1435         }
1436         if (unlikely(!print_fn)) {
1437                 dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);
1438                 return;
1439         }
1440
1441         host = ufshcd_get_variant(hba);
1442         if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
1443                 return;
1444
1445         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1446         print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);
1447
1448         reg = ufshcd_readl(hba, REG_UFS_CFG1);
1449         reg |= UTP_DBG_RAMS_EN;
1450         ufshcd_writel(hba, reg, REG_UFS_CFG1);
1451
1452         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1453         print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);
1454
1455         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1456         print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);
1457
1458         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1459         print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);
1460
1461         /* clear bit 17 - UTP_DBG_RAMS_EN */
1462         ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1463
1464         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1465         print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);
1466
1467         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1468         print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);
1469
1470         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1471         print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);
1472
1473         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1474         print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);
1475
1476         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1477         print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);
1478
1479         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1480         print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);
1481
1482         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1483         print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);
1484 }
1485
1486 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1487 {
1488         if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {
1489                 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1490                                 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1491                 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1492         } else {
1493                 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);
1494                 ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
1495         }
1496 }
1497
1498 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1499 {
1500         /* provide a legal default configuration */
1501         host->testbus.select_major = TSTBUS_UNIPRO;
1502         host->testbus.select_minor = 37;
1503 }
1504
1505 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1506 {
1507         if (host->testbus.select_major >= TSTBUS_MAX) {
1508                 dev_err(host->hba->dev,
1509                         "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1510                         __func__, host->testbus.select_major);
1511                 return false;
1512         }
1513
1514         return true;
1515 }
1516
1517 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1518 {
1519         int reg;
1520         int offset;
1521         u32 mask = TEST_BUS_SUB_SEL_MASK;
1522
1523         if (!host)
1524                 return -EINVAL;
1525
1526         if (!ufs_qcom_testbus_cfg_is_ok(host))
1527                 return -EPERM;
1528
1529         switch (host->testbus.select_major) {
1530         case TSTBUS_UAWM:
1531                 reg = UFS_TEST_BUS_CTRL_0;
1532                 offset = 24;
1533                 break;
1534         case TSTBUS_UARM:
1535                 reg = UFS_TEST_BUS_CTRL_0;
1536                 offset = 16;
1537                 break;
1538         case TSTBUS_TXUC:
1539                 reg = UFS_TEST_BUS_CTRL_0;
1540                 offset = 8;
1541                 break;
1542         case TSTBUS_RXUC:
1543                 reg = UFS_TEST_BUS_CTRL_0;
1544                 offset = 0;
1545                 break;
1546         case TSTBUS_DFC:
1547                 reg = UFS_TEST_BUS_CTRL_1;
1548                 offset = 24;
1549                 break;
1550         case TSTBUS_TRLUT:
1551                 reg = UFS_TEST_BUS_CTRL_1;
1552                 offset = 16;
1553                 break;
1554         case TSTBUS_TMRLUT:
1555                 reg = UFS_TEST_BUS_CTRL_1;
1556                 offset = 8;
1557                 break;
1558         case TSTBUS_OCSC:
1559                 reg = UFS_TEST_BUS_CTRL_1;
1560                 offset = 0;
1561                 break;
1562         case TSTBUS_WRAPPER:
1563                 reg = UFS_TEST_BUS_CTRL_2;
1564                 offset = 16;
1565                 break;
1566         case TSTBUS_COMBINED:
1567                 reg = UFS_TEST_BUS_CTRL_2;
1568                 offset = 8;
1569                 break;
1570         case TSTBUS_UTP_HCI:
1571                 reg = UFS_TEST_BUS_CTRL_2;
1572                 offset = 0;
1573                 break;
1574         case TSTBUS_UNIPRO:
1575                 reg = UFS_UNIPRO_CFG;
1576                 offset = 20;
1577                 mask = 0xFFF;
1578                 break;
1579         /*
1580          * No need for a default case, since
1581          * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1582          * is legal
1583          */
1584         }
1585         mask <<= offset;
1586
1587         pm_runtime_get_sync(host->hba->dev);
1588         ufshcd_hold(host->hba, false);
1589         ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1590                     (u32)host->testbus.select_major << 19,
1591                     REG_UFS_CFG1);
1592         ufshcd_rmwl(host->hba, mask,
1593                     (u32)host->testbus.select_minor << offset,
1594                     reg);
1595         ufs_qcom_enable_test_bus(host);
1596         /*
1597          * Make sure the test bus configuration is
1598          * committed before returning.
1599          */
1600         mb();
1601         ufshcd_release(host->hba);
1602         pm_runtime_put_sync(host->hba->dev);
1603
1604         return 0;
1605 }
1606
1607 static void ufs_qcom_testbus_read(struct ufs_hba *hba)
1608 {
1609         ufshcd_dump_regs(hba, UFS_TEST_BUS, 4, "UFS_TEST_BUS ");
1610 }
1611
1612 static void ufs_qcom_print_unipro_testbus(struct ufs_hba *hba)
1613 {
1614         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1615         u32 *testbus = NULL;
1616         int i, nminor = 256, testbus_len = nminor * sizeof(u32);
1617
1618         testbus = kmalloc(testbus_len, GFP_KERNEL);
1619         if (!testbus)
1620                 return;
1621
1622         host->testbus.select_major = TSTBUS_UNIPRO;
1623         for (i = 0; i < nminor; i++) {
1624                 host->testbus.select_minor = i;
1625                 ufs_qcom_testbus_config(host);
1626                 testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS);
1627         }
1628         print_hex_dump(KERN_ERR, "UNIPRO_TEST_BUS ", DUMP_PREFIX_OFFSET,
1629                         16, 4, testbus, testbus_len, false);
1630         kfree(testbus);
1631 }
1632
1633 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1634 {
1635         ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1636                          "HCI Vendor Specific Registers ");
1637
1638         /* sleep a bit intermittently as we are dumping too much data */
1639         ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);
1640         usleep_range(1000, 1100);
1641         ufs_qcom_testbus_read(hba);
1642         usleep_range(1000, 1100);
1643         ufs_qcom_print_unipro_testbus(hba);
1644         usleep_range(1000, 1100);
1645 }
1646
1647 /**
1648  * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1649  *
1650  * The variant operations configure the necessary controller and PHY
1651  * handshake during initialization.
1652  */
1653 static struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1654         .name                   = "qcom",
1655         .init                   = ufs_qcom_init,
1656         .exit                   = ufs_qcom_exit,
1657         .get_ufs_hci_version    = ufs_qcom_get_ufs_hci_version,
1658         .clk_scale_notify       = ufs_qcom_clk_scale_notify,
1659         .setup_clocks           = ufs_qcom_setup_clocks,
1660         .hce_enable_notify      = ufs_qcom_hce_enable_notify,
1661         .link_startup_notify    = ufs_qcom_link_startup_notify,
1662         .pwr_change_notify      = ufs_qcom_pwr_change_notify,
1663         .apply_dev_quirks       = ufs_qcom_apply_dev_quirks,
1664         .suspend                = ufs_qcom_suspend,
1665         .resume                 = ufs_qcom_resume,
1666         .dbg_register_dump      = ufs_qcom_dump_dbg_regs,
1667 };
1668
1669 /**
1670  * ufs_qcom_probe - probe routine of the driver
1671  * @pdev: pointer to Platform device handle
1672  *
1673  * Return zero for success and non-zero for failure
1674  */
1675 static int ufs_qcom_probe(struct platform_device *pdev)
1676 {
1677         int err;
1678         struct device *dev = &pdev->dev;
1679
1680         /* Perform generic probe */
1681         err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1682         if (err)
1683                 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1684
1685         return err;
1686 }
1687
1688 /**
1689  * ufs_qcom_remove - set driver_data of the device to NULL
1690  * @pdev: pointer to platform device handle
1691  *
1692  * Always returns 0
1693  */
1694 static int ufs_qcom_remove(struct platform_device *pdev)
1695 {
1696         struct ufs_hba *hba =  platform_get_drvdata(pdev);
1697
1698         pm_runtime_get_sync(&(pdev)->dev);
1699         ufshcd_remove(hba);
1700         return 0;
1701 }
1702
1703 static const struct of_device_id ufs_qcom_of_match[] = {
1704         { .compatible = "qcom,ufshc"},
1705         {},
1706 };
1707 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1708
1709 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1710         .suspend        = ufshcd_pltfrm_suspend,
1711         .resume         = ufshcd_pltfrm_resume,
1712         .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
1713         .runtime_resume  = ufshcd_pltfrm_runtime_resume,
1714         .runtime_idle    = ufshcd_pltfrm_runtime_idle,
1715 };
1716
1717 static struct platform_driver ufs_qcom_pltform = {
1718         .probe  = ufs_qcom_probe,
1719         .remove = ufs_qcom_remove,
1720         .shutdown = ufshcd_pltfrm_shutdown,
1721         .driver = {
1722                 .name   = "ufshcd-qcom",
1723                 .pm     = &ufs_qcom_pm_ops,
1724                 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1725         },
1726 };
1727 module_platform_driver(ufs_qcom_pltform);
1728
1729 MODULE_LICENSE("GPL v2");