2 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 #include <linux/time.h>
17 #include <linux/platform_device.h>
18 #include <linux/phy/phy.h>
21 #include "ufshcd-pltfrm.h"
25 #include "ufs_quirks.h"
26 #define UFS_QCOM_DEFAULT_DBG_PRINT_EN \
27 (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
45 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
47 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote);
48 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
49 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
52 static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
53 const char *prefix, void *priv)
55 ufshcd_dump_regs(hba, offset, len * 4, prefix);
58 static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
62 err = ufshcd_dme_get(hba,
63 UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes);
65 dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
71 static int ufs_qcom_host_clk_get(struct device *dev,
72 const char *name, struct clk **clk_out, bool optional)
77 clk = devm_clk_get(dev, name);
85 if (optional && err == -ENOENT) {
90 if (err != -EPROBE_DEFER)
91 dev_err(dev, "failed to get %s err %d\n", name, err);
96 static int ufs_qcom_host_clk_enable(struct device *dev,
97 const char *name, struct clk *clk)
101 err = clk_prepare_enable(clk);
103 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
108 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
110 if (!host->is_lane_clks_enabled)
113 clk_disable_unprepare(host->tx_l1_sync_clk);
114 clk_disable_unprepare(host->tx_l0_sync_clk);
115 clk_disable_unprepare(host->rx_l1_sync_clk);
116 clk_disable_unprepare(host->rx_l0_sync_clk);
118 host->is_lane_clks_enabled = false;
121 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
124 struct device *dev = host->hba->dev;
126 if (host->is_lane_clks_enabled)
129 err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
130 host->rx_l0_sync_clk);
134 err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
135 host->tx_l0_sync_clk);
139 err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
140 host->rx_l1_sync_clk);
144 err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
145 host->tx_l1_sync_clk);
149 host->is_lane_clks_enabled = true;
153 clk_disable_unprepare(host->rx_l1_sync_clk);
155 clk_disable_unprepare(host->tx_l0_sync_clk);
157 clk_disable_unprepare(host->rx_l0_sync_clk);
162 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
165 struct device *dev = host->hba->dev;
167 err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk",
168 &host->rx_l0_sync_clk, false);
172 err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk",
173 &host->tx_l0_sync_clk, false);
177 /* In case of single lane per direction, don't read lane1 clocks */
178 if (host->hba->lanes_per_direction > 1) {
179 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
180 &host->rx_l1_sync_clk, false);
184 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
185 &host->tx_l1_sync_clk, true);
191 static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
195 return ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
198 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
202 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
205 err = ufshcd_dme_get(hba,
206 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
207 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
209 if (err || tx_fsm_val == TX_FSM_HIBERN8)
212 /* sleep for max. 200us */
213 usleep_range(100, 200);
214 } while (time_before(jiffies, timeout));
217 * we might have scheduled out for long during polling so
218 * check the state again.
220 if (time_after(jiffies, timeout))
221 err = ufshcd_dme_get(hba,
222 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
223 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
227 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
229 } else if (tx_fsm_val != TX_FSM_HIBERN8) {
231 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
238 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
240 ufshcd_rmwl(host->hba, QUNIPRO_SEL,
241 ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
243 /* make sure above configuration is applied before we return */
247 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
249 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
250 struct phy *phy = host->generic_phy;
252 bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
256 phy_set_mode(phy, PHY_MODE_UFS_HS_B);
258 /* Assert PHY reset and apply PHY calibration values */
259 ufs_qcom_assert_reset(hba);
260 /* provide 1ms delay to let the reset pulse propagate */
261 usleep_range(1000, 1100);
263 /* phy initialization - calibrate the phy */
266 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
271 /* De-assert PHY reset and start serdes */
272 ufs_qcom_deassert_reset(hba);
275 * after reset deassertion, phy will need all ref clocks,
276 * voltage, current to settle down before starting serdes.
278 usleep_range(1000, 1100);
280 /* power on phy - start serdes and phy's power and clocks */
281 ret = phy_power_on(phy);
283 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
285 goto out_disable_phy;
288 ufs_qcom_select_unipro_mode(host);
293 ufs_qcom_assert_reset(hba);
300 * The UTP controller has a number of internal clock gating cells (CGCs).
301 * Internal hardware sub-modules within the UTP controller control the CGCs.
302 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
303 * in a specific operation, UTP controller CGCs are by default disabled and
304 * this function enables them (after every UFS link startup) to save some power
307 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
310 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
313 /* Ensure that HW clock gating is enabled before next operations */
317 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
318 enum ufs_notify_change_status status)
320 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
325 ufs_qcom_power_up_sequence(hba);
327 * The PHY PLL output is the source of tx/rx lane symbol
328 * clocks, hence, enable the lane clocks only after PHY
331 err = ufs_qcom_enable_lane_clks(host);
334 /* check if UFS PHY moved from DISABLED to HIBERN8 */
335 err = ufs_qcom_check_hibern8(hba);
336 ufs_qcom_enable_hw_clk_gating(hba);
340 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
348 * Returns zero for success and non-zero in case of a failure
350 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
351 u32 hs, u32 rate, bool update_link_startup_timer)
354 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
355 struct ufs_clk_info *clki;
356 u32 core_clk_period_in_ns;
357 u32 tx_clk_cycles_per_us = 0;
358 unsigned long core_clk_rate = 0;
359 u32 core_clk_cycles_per_us = 0;
361 static u32 pwm_fr_table[][2] = {
368 static u32 hs_fr_table_rA[][2] = {
374 static u32 hs_fr_table_rB[][2] = {
381 * The Qunipro controller does not use following registers:
382 * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
383 * UFS_REG_PA_LINK_STARTUP_TIMER
384 * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
387 if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
391 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
395 list_for_each_entry(clki, &hba->clk_list_head, list) {
396 if (!strcmp(clki->name, "core_clk"))
397 core_clk_rate = clk_get_rate(clki->clk);
400 /* If frequency is smaller than 1MHz, set to 1MHz */
401 if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
402 core_clk_rate = DEFAULT_CLK_RATE_HZ;
404 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
405 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
406 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
408 * make sure above write gets applied before we return from
414 if (ufs_qcom_cap_qunipro(host))
417 core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
418 core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
419 core_clk_period_in_ns &= MASK_CLK_NS_REG;
424 if (rate == PA_HS_MODE_A) {
425 if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
427 "%s: index %d exceeds table size %zu\n",
429 ARRAY_SIZE(hs_fr_table_rA));
432 tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
433 } else if (rate == PA_HS_MODE_B) {
434 if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
436 "%s: index %d exceeds table size %zu\n",
438 ARRAY_SIZE(hs_fr_table_rB));
441 tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
443 dev_err(hba->dev, "%s: invalid rate = %d\n",
450 if (gear > ARRAY_SIZE(pwm_fr_table)) {
452 "%s: index %d exceeds table size %zu\n",
454 ARRAY_SIZE(pwm_fr_table));
457 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
461 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
465 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
466 (core_clk_period_in_ns | tx_clk_cycles_per_us)) {
467 /* this register 2 fields shall be written at once */
468 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
469 REG_UFS_TX_SYMBOL_CLK_NS_US);
471 * make sure above write gets applied before we return from
477 if (update_link_startup_timer) {
478 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
479 REG_UFS_PA_LINK_STARTUP_TIMER);
481 * make sure that this configuration is applied before
494 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
495 enum ufs_notify_change_status status)
498 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
502 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
504 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
510 if (ufs_qcom_cap_qunipro(host))
512 * set unipro core clock cycles to 150 & clear clock
515 err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
519 * Some UFS devices (and may be host) have issues if LCC is
520 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
521 * before link startup which will make sure that both host
522 * and device TX LCC are disabled once link startup is
525 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
526 err = ufshcd_dme_set(hba,
527 UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE),
532 ufs_qcom_link_startup_post_change(hba);
542 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
544 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
545 struct phy *phy = host->generic_phy;
548 if (ufs_qcom_is_link_off(hba)) {
550 * Disable the tx/rx lane symbol clocks before PHY is
551 * powered down as the PLL source should be disabled
552 * after downstream clocks are disabled.
554 ufs_qcom_disable_lane_clks(host);
557 /* Assert PHY soft reset */
558 ufs_qcom_assert_reset(hba);
563 * If UniPro link is not active, PHY ref_clk, main PHY analog power
564 * rail and low noise analog power rail for PLL can be switched off.
566 if (!ufs_qcom_is_link_active(hba)) {
567 ufs_qcom_disable_lane_clks(host);
575 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
577 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
578 struct phy *phy = host->generic_phy;
581 err = phy_power_on(phy);
583 dev_err(hba->dev, "%s: failed enabling regs, err = %d\n",
588 err = ufs_qcom_enable_lane_clks(host);
592 hba->is_sys_suspended = false;
598 struct ufs_qcom_dev_params {
599 u32 pwm_rx_gear; /* pwm rx gear to work in */
600 u32 pwm_tx_gear; /* pwm tx gear to work in */
601 u32 hs_rx_gear; /* hs rx gear to work in */
602 u32 hs_tx_gear; /* hs tx gear to work in */
603 u32 rx_lanes; /* number of rx lanes */
604 u32 tx_lanes; /* number of tx lanes */
605 u32 rx_pwr_pwm; /* rx pwm working pwr */
606 u32 tx_pwr_pwm; /* tx pwm working pwr */
607 u32 rx_pwr_hs; /* rx hs working pwr */
608 u32 tx_pwr_hs; /* tx hs working pwr */
609 u32 hs_rate; /* rate A/B to work in HS */
610 u32 desired_working_mode;
613 static int ufs_qcom_get_pwr_dev_param(struct ufs_qcom_dev_params *qcom_param,
614 struct ufs_pa_layer_attr *dev_max,
615 struct ufs_pa_layer_attr *agreed_pwr)
619 bool is_dev_sup_hs = false;
620 bool is_qcom_max_hs = false;
622 if (dev_max->pwr_rx == FAST_MODE)
623 is_dev_sup_hs = true;
625 if (qcom_param->desired_working_mode == FAST) {
626 is_qcom_max_hs = true;
627 min_qcom_gear = min_t(u32, qcom_param->hs_rx_gear,
628 qcom_param->hs_tx_gear);
630 min_qcom_gear = min_t(u32, qcom_param->pwm_rx_gear,
631 qcom_param->pwm_tx_gear);
635 * device doesn't support HS but qcom_param->desired_working_mode is
636 * HS, thus device and qcom_param don't agree
638 if (!is_dev_sup_hs && is_qcom_max_hs) {
639 pr_err("%s: failed to agree on power mode (device doesn't support HS but requested power is HS)\n",
642 } else if (is_dev_sup_hs && is_qcom_max_hs) {
644 * since device supports HS, it supports FAST_MODE.
645 * since qcom_param->desired_working_mode is also HS
646 * then final decision (FAST/FASTAUTO) is done according
647 * to qcom_params as it is the restricting factor
649 agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
650 qcom_param->rx_pwr_hs;
653 * here qcom_param->desired_working_mode is PWM.
654 * it doesn't matter whether device supports HS or PWM,
655 * in both cases qcom_param->desired_working_mode will
658 agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
659 qcom_param->rx_pwr_pwm;
663 * we would like tx to work in the minimum number of lanes
664 * between device capability and vendor preferences.
665 * the same decision will be made for rx
667 agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
668 qcom_param->tx_lanes);
669 agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
670 qcom_param->rx_lanes);
672 /* device maximum gear is the minimum between device rx and tx gears */
673 min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
676 * if both device capabilities and vendor pre-defined preferences are
677 * both HS or both PWM then set the minimum gear to be the chosen
679 * if one is PWM and one is HS then the one that is PWM get to decide
680 * what is the gear, as it is the one that also decided previously what
681 * pwr the device will be configured to.
683 if ((is_dev_sup_hs && is_qcom_max_hs) ||
684 (!is_dev_sup_hs && !is_qcom_max_hs))
685 agreed_pwr->gear_rx = agreed_pwr->gear_tx =
686 min_t(u32, min_dev_gear, min_qcom_gear);
687 else if (!is_dev_sup_hs)
688 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_dev_gear;
690 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_qcom_gear;
692 agreed_pwr->hs_rate = qcom_param->hs_rate;
696 #ifdef CONFIG_MSM_BUS_SCALING
697 static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
698 const char *speed_mode)
700 struct device *dev = host->hba->dev;
701 struct device_node *np = dev->of_node;
703 const char *key = "qcom,bus-vector-names";
710 if (host->bus_vote.is_max_bw_needed && !!strcmp(speed_mode, "MIN"))
711 err = of_property_match_string(np, key, "MAX");
713 err = of_property_match_string(np, key, speed_mode);
717 dev_err(dev, "%s: Invalid %s mode %d\n",
718 __func__, speed_mode, err);
722 static void ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result)
724 int gear = max_t(u32, p->gear_rx, p->gear_tx);
725 int lanes = max_t(u32, p->lane_rx, p->lane_tx);
728 /* default to PWM Gear 1, Lane 1 if power mode is not initialized */
735 if (!p->pwr_rx && !p->pwr_tx) {
737 snprintf(result, BUS_VECTOR_NAME_LEN, "MIN");
738 } else if (p->pwr_rx == FAST_MODE || p->pwr_rx == FASTAUTO_MODE ||
739 p->pwr_tx == FAST_MODE || p->pwr_tx == FASTAUTO_MODE) {
741 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_R%s_G%d_L%d", "HS",
742 p->hs_rate == PA_HS_MODE_B ? "B" : "A", gear, lanes);
745 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_G%d_L%d",
750 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
754 if (vote != host->bus_vote.curr_vote) {
755 err = msm_bus_scale_client_update_request(
756 host->bus_vote.client_handle, vote);
758 dev_err(host->hba->dev,
759 "%s: msm_bus_scale_client_update_request() failed: bus_client_handle=0x%x, vote=%d, err=%d\n",
760 __func__, host->bus_vote.client_handle,
765 host->bus_vote.curr_vote = vote;
771 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
775 char mode[BUS_VECTOR_NAME_LEN];
777 ufs_qcom_get_speed_mode(&host->dev_req_params, mode);
779 vote = ufs_qcom_get_bus_vote(host, mode);
781 err = ufs_qcom_set_bus_vote(host, vote);
786 dev_err(host->hba->dev, "%s: failed %d\n", __func__, err);
788 host->bus_vote.saved_vote = vote;
793 show_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
796 struct ufs_hba *hba = dev_get_drvdata(dev);
797 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
799 return snprintf(buf, PAGE_SIZE, "%u\n",
800 host->bus_vote.is_max_bw_needed);
804 store_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
805 const char *buf, size_t count)
807 struct ufs_hba *hba = dev_get_drvdata(dev);
808 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
811 if (!kstrtou32(buf, 0, &value)) {
812 host->bus_vote.is_max_bw_needed = !!value;
813 ufs_qcom_update_bus_bw_vote(host);
819 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
822 struct msm_bus_scale_pdata *bus_pdata;
823 struct device *dev = host->hba->dev;
824 struct platform_device *pdev = to_platform_device(dev);
825 struct device_node *np = dev->of_node;
827 bus_pdata = msm_bus_cl_get_pdata(pdev);
829 dev_err(dev, "%s: failed to get bus vectors\n", __func__);
834 err = of_property_count_strings(np, "qcom,bus-vector-names");
835 if (err < 0 || err != bus_pdata->num_usecases) {
836 dev_err(dev, "%s: qcom,bus-vector-names not specified correctly %d\n",
841 host->bus_vote.client_handle = msm_bus_scale_register_client(bus_pdata);
842 if (!host->bus_vote.client_handle) {
843 dev_err(dev, "%s: msm_bus_scale_register_client failed\n",
849 /* cache the vote index for minimum and maximum bandwidth */
850 host->bus_vote.min_bw_vote = ufs_qcom_get_bus_vote(host, "MIN");
851 host->bus_vote.max_bw_vote = ufs_qcom_get_bus_vote(host, "MAX");
853 host->bus_vote.max_bus_bw.show = show_ufs_to_mem_max_bus_bw;
854 host->bus_vote.max_bus_bw.store = store_ufs_to_mem_max_bus_bw;
855 sysfs_attr_init(&host->bus_vote.max_bus_bw.attr);
856 host->bus_vote.max_bus_bw.attr.name = "max_bus_bw";
857 host->bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR;
858 err = device_create_file(dev, &host->bus_vote.max_bus_bw);
862 #else /* CONFIG_MSM_BUS_SCALING */
863 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
868 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
873 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
877 #endif /* CONFIG_MSM_BUS_SCALING */
879 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
881 if (host->dev_ref_clk_ctrl_mmio &&
882 (enable ^ host->is_dev_ref_clk_enabled)) {
883 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
886 temp |= host->dev_ref_clk_en_mask;
888 temp &= ~host->dev_ref_clk_en_mask;
891 * If we are here to disable this clock it might be immediately
892 * after entering into hibern8 in which case we need to make
893 * sure that device ref_clk is active at least 1us after the
899 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
901 /* ensure that ref_clk is enabled/disabled before we return */
905 * If we call hibern8 exit after this, we need to make sure that
906 * device ref_clk is stable for at least 1us before the hibern8
912 host->is_dev_ref_clk_enabled = enable;
916 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
917 enum ufs_notify_change_status status,
918 struct ufs_pa_layer_attr *dev_max_params,
919 struct ufs_pa_layer_attr *dev_req_params)
922 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
923 struct ufs_qcom_dev_params ufs_qcom_cap;
926 if (!dev_req_params) {
927 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
934 ufs_qcom_cap.tx_lanes = UFS_QCOM_LIMIT_NUM_LANES_TX;
935 ufs_qcom_cap.rx_lanes = UFS_QCOM_LIMIT_NUM_LANES_RX;
936 ufs_qcom_cap.hs_rx_gear = UFS_QCOM_LIMIT_HSGEAR_RX;
937 ufs_qcom_cap.hs_tx_gear = UFS_QCOM_LIMIT_HSGEAR_TX;
938 ufs_qcom_cap.pwm_rx_gear = UFS_QCOM_LIMIT_PWMGEAR_RX;
939 ufs_qcom_cap.pwm_tx_gear = UFS_QCOM_LIMIT_PWMGEAR_TX;
940 ufs_qcom_cap.rx_pwr_pwm = UFS_QCOM_LIMIT_RX_PWR_PWM;
941 ufs_qcom_cap.tx_pwr_pwm = UFS_QCOM_LIMIT_TX_PWR_PWM;
942 ufs_qcom_cap.rx_pwr_hs = UFS_QCOM_LIMIT_RX_PWR_HS;
943 ufs_qcom_cap.tx_pwr_hs = UFS_QCOM_LIMIT_TX_PWR_HS;
944 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
945 ufs_qcom_cap.desired_working_mode =
946 UFS_QCOM_LIMIT_DESIRED_MODE;
948 if (host->hw_ver.major == 0x1) {
950 * HS-G3 operations may not reliably work on legacy QCOM
951 * UFS host controller hardware even though capability
952 * exchange during link startup phase may end up
953 * negotiating maximum supported gear as G3.
954 * Hence downgrade the maximum supported gear to HS-G2.
956 if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2)
957 ufs_qcom_cap.hs_tx_gear = UFS_HS_G2;
958 if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2)
959 ufs_qcom_cap.hs_rx_gear = UFS_HS_G2;
962 ret = ufs_qcom_get_pwr_dev_param(&ufs_qcom_cap,
966 pr_err("%s: failed to determine capabilities\n",
971 /* enable the device ref clock before changing to HS mode */
972 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
973 ufshcd_is_hs_mode(dev_req_params))
974 ufs_qcom_dev_ref_clk_ctrl(host, true);
977 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
978 dev_req_params->pwr_rx,
979 dev_req_params->hs_rate, false)) {
980 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
983 * we return error code at the end of the routine,
984 * but continue to configure UFS_PHY_TX_LANE_ENABLE
985 * and bus voting as usual
990 val = ~(MAX_U32 << dev_req_params->lane_tx);
992 /* cache the power mode parameters to use internally */
993 memcpy(&host->dev_req_params,
994 dev_req_params, sizeof(*dev_req_params));
995 ufs_qcom_update_bus_bw_vote(host);
997 /* disable the device ref clock if entered PWM mode */
998 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
999 !ufshcd_is_hs_mode(dev_req_params))
1000 ufs_qcom_dev_ref_clk_ctrl(host, false);
1010 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
1013 u32 pa_vs_config_reg1;
1015 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
1016 &pa_vs_config_reg1);
1020 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
1021 err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
1022 (pa_vs_config_reg1 | (1 << 12)));
1028 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
1032 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
1033 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
1038 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
1040 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1042 if (host->hw_ver.major == 0x1)
1043 return UFSHCI_VERSION_11;
1045 return UFSHCI_VERSION_20;
1049 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
1050 * @hba: host controller instance
1052 * QCOM UFS host controller might have some non standard behaviours (quirks)
1053 * than what is specified by UFSHCI specification. Advertise all such
1054 * quirks to standard UFS host controller driver so standard takes them into
1057 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
1059 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1061 if (host->hw_ver.major == 0x01) {
1062 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1063 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
1064 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
1066 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
1067 hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
1069 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
1072 if (host->hw_ver.major == 0x2) {
1073 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
1075 if (!ufs_qcom_cap_qunipro(host))
1076 /* Legacy UniPro mode still need following quirks */
1077 hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1078 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
1079 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
1083 static void ufs_qcom_set_caps(struct ufs_hba *hba)
1085 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1087 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1088 hba->caps |= UFSHCD_CAP_CLK_SCALING;
1089 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1091 if (host->hw_ver.major >= 0x2) {
1092 host->caps = UFS_QCOM_CAP_QUNIPRO |
1093 UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE;
1098 * ufs_qcom_setup_clocks - enables/disable clocks
1099 * @hba: host controller instance
1100 * @on: If true, enable clocks else disable them.
1101 * @status: PRE_CHANGE or POST_CHANGE notify
1103 * Returns 0 on success, non-zero on failure.
1105 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
1106 enum ufs_notify_change_status status)
1108 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1113 * In case ufs_qcom_init() is not yet done, simply ignore.
1114 * This ufs_qcom_setup_clocks() shall be called from
1115 * ufs_qcom_init() after init is done.
1120 if (on && (status == POST_CHANGE)) {
1121 phy_power_on(host->generic_phy);
1123 /* enable the device ref clock for HS mode*/
1124 if (ufshcd_is_hs_mode(&hba->pwr_info))
1125 ufs_qcom_dev_ref_clk_ctrl(host, true);
1126 vote = host->bus_vote.saved_vote;
1127 if (vote == host->bus_vote.min_bw_vote)
1128 ufs_qcom_update_bus_bw_vote(host);
1130 } else if (!on && (status == PRE_CHANGE)) {
1131 if (!ufs_qcom_is_link_active(hba)) {
1132 /* disable device ref_clk */
1133 ufs_qcom_dev_ref_clk_ctrl(host, false);
1135 /* powering off PHY during aggressive clk gating */
1136 phy_power_off(host->generic_phy);
1139 vote = host->bus_vote.min_bw_vote;
1142 err = ufs_qcom_set_bus_vote(host, vote);
1144 dev_err(hba->dev, "%s: set bus vote failed %d\n",
1150 #define ANDROID_BOOT_DEV_MAX 30
1151 static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
1154 static int __init get_android_boot_dev(char *str)
1156 strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX);
1159 __setup("androidboot.bootdevice=", get_android_boot_dev);
1163 * ufs_qcom_init - bind phy with controller
1164 * @hba: host controller instance
1166 * Binds PHY with controller and powers up PHY enabling clocks
1169 * Returns -EPROBE_DEFER if binding fails, returns negative error
1170 * on phy power up failure and returns zero on success.
1172 static int ufs_qcom_init(struct ufs_hba *hba)
1175 struct device *dev = hba->dev;
1176 struct platform_device *pdev = to_platform_device(dev);
1177 struct ufs_qcom_host *host;
1178 struct resource *res;
1180 if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
1183 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1186 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
1190 /* Make a two way bind between the qcom host and the hba */
1192 ufshcd_set_variant(hba, host);
1195 * voting/devoting device ref_clk source is time consuming hence
1196 * skip devoting it during aggressive clock gating. This clock
1197 * will still be gated off during runtime suspend.
1199 host->generic_phy = devm_phy_get(dev, "ufsphy");
1201 if (host->generic_phy == ERR_PTR(-EPROBE_DEFER)) {
1203 * UFS driver might be probed before the phy driver does.
1204 * In that case we would like to return EPROBE_DEFER code.
1206 err = -EPROBE_DEFER;
1207 dev_warn(dev, "%s: required phy device. hasn't probed yet. err = %d\n",
1209 goto out_variant_clear;
1210 } else if (IS_ERR(host->generic_phy)) {
1211 err = PTR_ERR(host->generic_phy);
1212 dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
1213 goto out_variant_clear;
1216 err = ufs_qcom_bus_register(host);
1218 goto out_variant_clear;
1220 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1221 &host->hw_ver.minor, &host->hw_ver.step);
1224 * for newer controllers, device reference clock control bit has
1225 * moved inside UFS controller register address space itself.
1227 if (host->hw_ver.major >= 0x02) {
1228 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1229 host->dev_ref_clk_en_mask = BIT(26);
1231 /* "dev_ref_clk_ctrl_mem" is optional resource */
1232 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1234 host->dev_ref_clk_ctrl_mmio =
1235 devm_ioremap_resource(dev, res);
1236 if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) {
1238 "%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n",
1240 PTR_ERR(host->dev_ref_clk_ctrl_mmio));
1241 host->dev_ref_clk_ctrl_mmio = NULL;
1243 host->dev_ref_clk_en_mask = BIT(5);
1247 err = ufs_qcom_init_lane_clks(host);
1249 goto out_variant_clear;
1251 ufs_qcom_set_caps(hba);
1252 ufs_qcom_advertise_quirks(hba);
1254 ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1256 if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
1257 ufs_qcom_hosts[hba->dev->id] = host;
1259 host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
1260 ufs_qcom_get_default_testbus_cfg(host);
1261 err = ufs_qcom_testbus_config(host);
1263 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1271 ufshcd_set_variant(hba, NULL);
1276 static void ufs_qcom_exit(struct ufs_hba *hba)
1278 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1280 ufs_qcom_disable_lane_clks(host);
1281 phy_power_off(host->generic_phy);
1282 phy_exit(host->generic_phy);
1285 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
1289 u32 core_clk_ctrl_reg;
1291 if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
1294 err = ufshcd_dme_get(hba,
1295 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1296 &core_clk_ctrl_reg);
1300 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
1301 core_clk_ctrl_reg |= clk_cycles;
1303 /* Clear CORE_CLK_DIV_EN */
1304 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1306 err = ufshcd_dme_set(hba,
1307 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1313 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1315 /* nothing to do as of now */
1319 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1321 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1323 if (!ufs_qcom_cap_qunipro(host))
1326 /* set unipro core clock cycles to 150 and clear clock divider */
1327 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);
1330 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1332 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1334 u32 core_clk_ctrl_reg;
1336 if (!ufs_qcom_cap_qunipro(host))
1339 err = ufshcd_dme_get(hba,
1340 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1341 &core_clk_ctrl_reg);
1343 /* make sure CORE_CLK_DIV_EN is cleared */
1345 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1346 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1347 err = ufshcd_dme_set(hba,
1348 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1355 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1357 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1359 if (!ufs_qcom_cap_qunipro(host))
1362 /* set unipro core clock cycles to 75 and clear clock divider */
1363 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);
1366 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1367 bool scale_up, enum ufs_notify_change_status status)
1369 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1370 struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1373 if (status == PRE_CHANGE) {
1375 err = ufs_qcom_clk_scale_up_pre_change(hba);
1377 err = ufs_qcom_clk_scale_down_pre_change(hba);
1380 err = ufs_qcom_clk_scale_up_post_change(hba);
1382 err = ufs_qcom_clk_scale_down_post_change(hba);
1384 if (err || !dev_req_params)
1387 ufs_qcom_cfg_timers(hba,
1388 dev_req_params->gear_rx,
1389 dev_req_params->pwr_rx,
1390 dev_req_params->hs_rate,
1392 ufs_qcom_update_bus_bw_vote(host);
1399 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
1400 void *priv, void (*print_fn)(struct ufs_hba *hba,
1401 int offset, int num_regs, const char *str, void *priv))
1404 struct ufs_qcom_host *host;
1406 if (unlikely(!hba)) {
1407 pr_err("%s: hba is NULL\n", __func__);
1410 if (unlikely(!print_fn)) {
1411 dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);
1415 host = ufshcd_get_variant(hba);
1416 if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
1419 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1420 print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);
1422 reg = ufshcd_readl(hba, REG_UFS_CFG1);
1423 reg |= UTP_DBG_RAMS_EN;
1424 ufshcd_writel(hba, reg, REG_UFS_CFG1);
1426 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1427 print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);
1429 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1430 print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);
1432 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1433 print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);
1435 /* clear bit 17 - UTP_DBG_RAMS_EN */
1436 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1438 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1439 print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);
1441 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1442 print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);
1444 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1445 print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);
1447 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1448 print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);
1450 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1451 print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);
1453 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1454 print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);
1456 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1457 print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);
1460 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1462 if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {
1463 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1464 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1465 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1467 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);
1468 ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
1472 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1474 /* provide a legal default configuration */
1475 host->testbus.select_major = TSTBUS_UNIPRO;
1476 host->testbus.select_minor = 37;
1479 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1481 if (host->testbus.select_major >= TSTBUS_MAX) {
1482 dev_err(host->hba->dev,
1483 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1484 __func__, host->testbus.select_major);
1491 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1495 u32 mask = TEST_BUS_SUB_SEL_MASK;
1500 if (!ufs_qcom_testbus_cfg_is_ok(host))
1503 switch (host->testbus.select_major) {
1505 reg = UFS_TEST_BUS_CTRL_0;
1509 reg = UFS_TEST_BUS_CTRL_0;
1513 reg = UFS_TEST_BUS_CTRL_0;
1517 reg = UFS_TEST_BUS_CTRL_0;
1521 reg = UFS_TEST_BUS_CTRL_1;
1525 reg = UFS_TEST_BUS_CTRL_1;
1529 reg = UFS_TEST_BUS_CTRL_1;
1533 reg = UFS_TEST_BUS_CTRL_1;
1536 case TSTBUS_WRAPPER:
1537 reg = UFS_TEST_BUS_CTRL_2;
1540 case TSTBUS_COMBINED:
1541 reg = UFS_TEST_BUS_CTRL_2;
1544 case TSTBUS_UTP_HCI:
1545 reg = UFS_TEST_BUS_CTRL_2;
1549 reg = UFS_UNIPRO_CFG;
1554 * No need for a default case, since
1555 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1561 pm_runtime_get_sync(host->hba->dev);
1562 ufshcd_hold(host->hba, false);
1563 ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1564 (u32)host->testbus.select_major << 19,
1566 ufshcd_rmwl(host->hba, mask,
1567 (u32)host->testbus.select_minor << offset,
1569 ufs_qcom_enable_test_bus(host);
1571 * Make sure the test bus configuration is
1572 * committed before returning.
1575 ufshcd_release(host->hba);
1576 pm_runtime_put_sync(host->hba->dev);
1581 static void ufs_qcom_testbus_read(struct ufs_hba *hba)
1583 ufshcd_dump_regs(hba, UFS_TEST_BUS, 4, "UFS_TEST_BUS ");
1586 static void ufs_qcom_print_unipro_testbus(struct ufs_hba *hba)
1588 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1589 u32 *testbus = NULL;
1590 int i, nminor = 256, testbus_len = nminor * sizeof(u32);
1592 testbus = kmalloc(testbus_len, GFP_KERNEL);
1596 host->testbus.select_major = TSTBUS_UNIPRO;
1597 for (i = 0; i < nminor; i++) {
1598 host->testbus.select_minor = i;
1599 ufs_qcom_testbus_config(host);
1600 testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS);
1602 print_hex_dump(KERN_ERR, "UNIPRO_TEST_BUS ", DUMP_PREFIX_OFFSET,
1603 16, 4, testbus, testbus_len, false);
1607 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1609 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1610 "HCI Vendor Specific Registers ");
1612 /* sleep a bit intermittently as we are dumping too much data */
1613 ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);
1614 usleep_range(1000, 1100);
1615 ufs_qcom_testbus_read(hba);
1616 usleep_range(1000, 1100);
1617 ufs_qcom_print_unipro_testbus(hba);
1618 usleep_range(1000, 1100);
1622 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1624 * The variant operations configure the necessary controller and PHY
1625 * handshake during initialization.
1627 static struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1629 .init = ufs_qcom_init,
1630 .exit = ufs_qcom_exit,
1631 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version,
1632 .clk_scale_notify = ufs_qcom_clk_scale_notify,
1633 .setup_clocks = ufs_qcom_setup_clocks,
1634 .hce_enable_notify = ufs_qcom_hce_enable_notify,
1635 .link_startup_notify = ufs_qcom_link_startup_notify,
1636 .pwr_change_notify = ufs_qcom_pwr_change_notify,
1637 .apply_dev_quirks = ufs_qcom_apply_dev_quirks,
1638 .suspend = ufs_qcom_suspend,
1639 .resume = ufs_qcom_resume,
1640 .dbg_register_dump = ufs_qcom_dump_dbg_regs,
1644 * ufs_qcom_probe - probe routine of the driver
1645 * @pdev: pointer to Platform device handle
1647 * Return zero for success and non-zero for failure
1649 static int ufs_qcom_probe(struct platform_device *pdev)
1652 struct device *dev = &pdev->dev;
1654 /* Perform generic probe */
1655 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1657 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1663 * ufs_qcom_remove - set driver_data of the device to NULL
1664 * @pdev: pointer to platform device handle
1668 static int ufs_qcom_remove(struct platform_device *pdev)
1670 struct ufs_hba *hba = platform_get_drvdata(pdev);
1672 pm_runtime_get_sync(&(pdev)->dev);
1677 static const struct of_device_id ufs_qcom_of_match[] = {
1678 { .compatible = "qcom,ufshc"},
1681 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1683 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1684 .suspend = ufshcd_pltfrm_suspend,
1685 .resume = ufshcd_pltfrm_resume,
1686 .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
1687 .runtime_resume = ufshcd_pltfrm_runtime_resume,
1688 .runtime_idle = ufshcd_pltfrm_runtime_idle,
1691 static struct platform_driver ufs_qcom_pltform = {
1692 .probe = ufs_qcom_probe,
1693 .remove = ufs_qcom_remove,
1694 .shutdown = ufshcd_pltfrm_shutdown,
1696 .name = "ufshcd-qcom",
1697 .pm = &ufs_qcom_pm_ops,
1698 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1701 module_platform_driver(ufs_qcom_pltform);
1703 MODULE_LICENSE("GPL v2");