drivers/scsi/ufs/ufs-qcom.c

   1 /*
   2  * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #include <linux/time.h>
  16 #include <linux/of.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/phy/phy.h>
  19 #include <linux/reset-controller.h>
  20
  21 #include "ufshcd.h"
  22 #include "ufshcd-pltfrm.h"
  23 #include "unipro.h"
  24 #include "ufs-qcom.h"
  25 #include "ufshci.h"
  26 #include "ufs_quirks.h"
  27 #define UFS_QCOM_DEFAULT_DBG_PRINT_EN   \
  28         (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
  29
  30 enum {
  31         TSTBUS_UAWM,
  32         TSTBUS_UARM,
  33         TSTBUS_TXUC,
  34         TSTBUS_RXUC,
  35         TSTBUS_DFC,
  36         TSTBUS_TRLUT,
  37         TSTBUS_TMRLUT,
  38         TSTBUS_OCSC,
  39         TSTBUS_UTP_HCI,
  40         TSTBUS_COMBINED,
  41         TSTBUS_WRAPPER,
  42         TSTBUS_UNIPRO,
  43         TSTBUS_MAX,
  44 };
  45
  46 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
  47
  48 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote);
  49 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
  50 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
  51                                                        u32 clk_cycles);
  52
  53 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
  54 {
  55         return container_of(rcd, struct ufs_qcom_host, rcdev);
  56 }
  57
  58 static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
  59                                        const char *prefix, void *priv)
  60 {
  61         ufshcd_dump_regs(hba, offset, len * 4, prefix);
  62 }
  63
  64 static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
  65 {
  66         int err = 0;
  67
  68         err = ufshcd_dme_get(hba,
  69                         UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes);
  70         if (err)
  71                 dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
  72                                 __func__, err);
  73
  74         return err;
  75 }
  76
  77 static int ufs_qcom_host_clk_get(struct device *dev,
  78                 const char *name, struct clk **clk_out, bool optional)
  79 {
  80         struct clk *clk;
  81         int err = 0;
  82
  83         clk = devm_clk_get(dev, name);
  84         if (!IS_ERR(clk)) {
  85                 *clk_out = clk;
  86                 return 0;
  87         }
  88
  89         err = PTR_ERR(clk);
  90
  91         if (optional && err == -ENOENT) {
  92                 *clk_out = NULL;
  93                 return 0;
  94         }
  95
  96         if (err != -EPROBE_DEFER)
  97                 dev_err(dev, "failed to get %s err %d\n", name, err);
  98
  99         return err;
 100 }
 101
 102 static int ufs_qcom_host_clk_enable(struct device *dev,
 103                 const char *name, struct clk *clk)
 104 {
 105         int err = 0;
 106
 107         err = clk_prepare_enable(clk);
 108         if (err)
 109                 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
 110
 111         return err;
 112 }
 113
 114 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
 115 {
 116         if (!host->is_lane_clks_enabled)
 117                 return;
 118
 119         clk_disable_unprepare(host->tx_l1_sync_clk);
 120         clk_disable_unprepare(host->tx_l0_sync_clk);
 121         clk_disable_unprepare(host->rx_l1_sync_clk);
 122         clk_disable_unprepare(host->rx_l0_sync_clk);
 123
 124         host->is_lane_clks_enabled = false;
 125 }
 126
 127 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
 128 {
 129         int err = 0;
 130         struct device *dev = host->hba->dev;
 131
 132         if (host->is_lane_clks_enabled)
 133                 return 0;
 134
 135         err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
 136                 host->rx_l0_sync_clk);
 137         if (err)
 138                 goto out;
 139
 140         err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
 141                 host->tx_l0_sync_clk);
 142         if (err)
 143                 goto disable_rx_l0;
 144
 145         err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
 146                         host->rx_l1_sync_clk);
 147         if (err)
 148                 goto disable_tx_l0;
 149
 150         err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
 151                         host->tx_l1_sync_clk);
 152         if (err)
 153                 goto disable_rx_l1;
 154
 155         host->is_lane_clks_enabled = true;
 156         goto out;
 157
 158 disable_rx_l1:
 159         clk_disable_unprepare(host->rx_l1_sync_clk);
 160 disable_tx_l0:
 161         clk_disable_unprepare(host->tx_l0_sync_clk);
 162 disable_rx_l0:
 163         clk_disable_unprepare(host->rx_l0_sync_clk);
 164 out:
 165         return err;
 166 }
 167
 168 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
 169 {
 170         int err = 0;
 171         struct device *dev = host->hba->dev;
 172
 173         err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk",
 174                                         &host->rx_l0_sync_clk, false);
 175         if (err)
 176                 goto out;
 177
 178         err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk",
 179                                         &host->tx_l0_sync_clk, false);
 180         if (err)
 181                 goto out;
 182
 183         /* In case of single lane per direction, don't read lane1 clocks */
 184         if (host->hba->lanes_per_direction > 1) {
 185                 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
 186                         &host->rx_l1_sync_clk, false);
 187                 if (err)
 188                         goto out;
 189
 190                 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
 191                         &host->tx_l1_sync_clk, true);
 192         }
 193 out:
 194         return err;
 195 }
 196
 197 static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
 198 {
 199         u32 tx_lanes;
 200
 201         return ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
 202 }
 203
 204 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
 205 {
 206         int err;
 207         u32 tx_fsm_val = 0;
 208         unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
 209
 210         do {
 211                 err = ufshcd_dme_get(hba,
 212                                 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
 213                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
 214                                 &tx_fsm_val);
 215                 if (err || tx_fsm_val == TX_FSM_HIBERN8)
 216                         break;
 217
 218                 /* sleep for max. 200us */
 219                 usleep_range(100, 200);
 220         } while (time_before(jiffies, timeout));
 221
 222         /*
 223          * we might have scheduled out for long during polling so
 224          * check the state again.
 225          */
 226         if (time_after(jiffies, timeout))
 227                 err = ufshcd_dme_get(hba,
 228                                 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
 229                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
 230                                 &tx_fsm_val);
 231
 232         if (err) {
 233                 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
 234                                 __func__, err);
 235         } else if (tx_fsm_val != TX_FSM_HIBERN8) {
 236                 err = tx_fsm_val;
 237                 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
 238                                 __func__, err);
 239         }
 240
 241         return err;
 242 }
 243
 244 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
 245 {
 246         ufshcd_rmwl(host->hba, QUNIPRO_SEL,
 247                    ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
 248                    REG_UFS_CFG1);
 249         /* make sure above configuration is applied before we return */
 250         mb();
 251 }
 252
 253 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
 254 {
 255         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 256         struct phy *phy = host->generic_phy;
 257         int ret = 0;
 258         bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
 259                                                         ? true : false;
 260
 261         if (is_rate_B)
 262                 phy_set_mode(phy, PHY_MODE_UFS_HS_B);
 263
 264         /* phy initialization - calibrate the phy */
 265         ret = phy_init(phy);
 266         if (ret) {
 267                 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
 268                         __func__, ret);
 269                 goto out;
 270         }
 271
 272         /* power on phy - start serdes and phy's power and clocks */
 273         ret = phy_power_on(phy);
 274         if (ret) {
 275                 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
 276                         __func__, ret);
 277                 goto out_disable_phy;
 278         }
 279
 280         ufs_qcom_select_unipro_mode(host);
 281
 282         return 0;
 283
 284 out_disable_phy:
 285         phy_exit(phy);
 286 out:
 287         return ret;
 288 }
 289
 290 /*
 291  * The UTP controller has a number of internal clock gating cells (CGCs).
 292  * Internal hardware sub-modules within the UTP controller control the CGCs.
 293  * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
 294  * in a specific operation, UTP controller CGCs are by default disabled and
 295  * this function enables them (after every UFS link startup) to save some power
 296  * leakage.
 297  */
 298 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
 299 {
 300         ufshcd_writel(hba,
 301                 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
 302                 REG_UFS_CFG2);
 303
 304         /* Ensure that HW clock gating is enabled before next operations */
 305         mb();
 306 }
 307
 308 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
 309                                       enum ufs_notify_change_status status)
 310 {
 311         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 312         int err = 0;
 313
 314         switch (status) {
 315         case PRE_CHANGE:
 316                 ufs_qcom_power_up_sequence(hba);
 317                 /*
 318                  * The PHY PLL output is the source of tx/rx lane symbol
 319                  * clocks, hence, enable the lane clocks only after PHY
 320                  * is initialized.
 321                  */
 322                 err = ufs_qcom_enable_lane_clks(host);
 323                 break;
 324         case POST_CHANGE:
 325                 /* check if UFS PHY moved from DISABLED to HIBERN8 */
 326                 err = ufs_qcom_check_hibern8(hba);
 327                 ufs_qcom_enable_hw_clk_gating(hba);
 328
 329                 break;
 330         default:
 331                 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
 332                 err = -EINVAL;
 333                 break;
 334         }
 335         return err;
 336 }
 337
 338 /**
 339  * Returns zero for success and non-zero in case of a failure
 340  */
 341 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
 342                                u32 hs, u32 rate, bool update_link_startup_timer)
 343 {
 344         int ret = 0;
 345         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 346         struct ufs_clk_info *clki;
 347         u32 core_clk_period_in_ns;
 348         u32 tx_clk_cycles_per_us = 0;
 349         unsigned long core_clk_rate = 0;
 350         u32 core_clk_cycles_per_us = 0;
 351
 352         static u32 pwm_fr_table[][2] = {
 353                 {UFS_PWM_G1, 0x1},
 354                 {UFS_PWM_G2, 0x1},
 355                 {UFS_PWM_G3, 0x1},
 356                 {UFS_PWM_G4, 0x1},
 357         };
 358
 359         static u32 hs_fr_table_rA[][2] = {
 360                 {UFS_HS_G1, 0x1F},
 361                 {UFS_HS_G2, 0x3e},
 362                 {UFS_HS_G3, 0x7D},
 363         };
 364
 365         static u32 hs_fr_table_rB[][2] = {
 366                 {UFS_HS_G1, 0x24},
 367                 {UFS_HS_G2, 0x49},
 368                 {UFS_HS_G3, 0x92},
 369         };
 370
 371         /*
 372          * The Qunipro controller does not use following registers:
 373          * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
 374          * UFS_REG_PA_LINK_STARTUP_TIMER
 375          * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
 376          * Aggregation logic.
 377         */
 378         if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
 379                 goto out;
 380
 381         if (gear == 0) {
 382                 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
 383                 goto out_error;
 384         }
 385
 386         list_for_each_entry(clki, &hba->clk_list_head, list) {
 387                 if (!strcmp(clki->name, "core_clk"))
 388                         core_clk_rate = clk_get_rate(clki->clk);
 389         }
 390
 391         /* If frequency is smaller than 1MHz, set to 1MHz */
 392         if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
 393                 core_clk_rate = DEFAULT_CLK_RATE_HZ;
 394
 395         core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
 396         if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
 397                 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
 398                 /*
 399                  * make sure above write gets applied before we return from
 400                  * this function.
 401                  */
 402                 mb();
 403         }
 404
 405         if (ufs_qcom_cap_qunipro(host))
 406                 goto out;
 407
 408         core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
 409         core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
 410         core_clk_period_in_ns &= MASK_CLK_NS_REG;
 411
 412         switch (hs) {
 413         case FASTAUTO_MODE:
 414         case FAST_MODE:
 415                 if (rate == PA_HS_MODE_A) {
 416                         if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
 417                                 dev_err(hba->dev,
 418                                         "%s: index %d exceeds table size %zu\n",
 419                                         __func__, gear,
 420                                         ARRAY_SIZE(hs_fr_table_rA));
 421                                 goto out_error;
 422                         }
 423                         tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
 424                 } else if (rate == PA_HS_MODE_B) {
 425                         if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
 426                                 dev_err(hba->dev,
 427                                         "%s: index %d exceeds table size %zu\n",
 428                                         __func__, gear,
 429                                         ARRAY_SIZE(hs_fr_table_rB));
 430                                 goto out_error;
 431                         }
 432                         tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
 433                 } else {
 434                         dev_err(hba->dev, "%s: invalid rate = %d\n",
 435                                 __func__, rate);
 436                         goto out_error;
 437                 }
 438                 break;
 439         case SLOWAUTO_MODE:
 440         case SLOW_MODE:
 441                 if (gear > ARRAY_SIZE(pwm_fr_table)) {
 442                         dev_err(hba->dev,
 443                                         "%s: index %d exceeds table size %zu\n",
 444                                         __func__, gear,
 445                                         ARRAY_SIZE(pwm_fr_table));
 446                         goto out_error;
 447                 }
 448                 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
 449                 break;
 450         case UNCHANGED:
 451         default:
 452                 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
 453                 goto out_error;
 454         }
 455
 456         if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
 457             (core_clk_period_in_ns | tx_clk_cycles_per_us)) {
 458                 /* this register 2 fields shall be written at once */
 459                 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
 460                               REG_UFS_TX_SYMBOL_CLK_NS_US);
 461                 /*
 462                  * make sure above write gets applied before we return from
 463                  * this function.
 464                  */
 465                 mb();
 466         }
 467
 468         if (update_link_startup_timer) {
 469                 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
 470                               REG_UFS_PA_LINK_STARTUP_TIMER);
 471                 /*
 472                  * make sure that this configuration is applied before
 473                  * we return
 474                  */
 475                 mb();
 476         }
 477         goto out;
 478
 479 out_error:
 480         ret = -EINVAL;
 481 out:
 482         return ret;
 483 }
 484
 485 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
 486                                         enum ufs_notify_change_status status)
 487 {
 488         int err = 0;
 489         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 490
 491         switch (status) {
 492         case PRE_CHANGE:
 493                 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
 494                                         0, true)) {
 495                         dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
 496                                 __func__);
 497                         err = -EINVAL;
 498                         goto out;
 499                 }
 500
 501                 if (ufs_qcom_cap_qunipro(host))
 502                         /*
 503                          * set unipro core clock cycles to 150 & clear clock
 504                          * divider
 505                          */
 506                         err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
 507                                                                           150);
 508
 509                 /*
 510                  * Some UFS devices (and may be host) have issues if LCC is
 511                  * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
 512                  * before link startup which will make sure that both host
 513                  * and device TX LCC are disabled once link startup is
 514                  * completed.
 515                  */
 516                 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
 517                         err = ufshcd_dme_set(hba,
 518                                         UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE),
 519                                         0);
 520
 521                 break;
 522         case POST_CHANGE:
 523                 ufs_qcom_link_startup_post_change(hba);
 524                 break;
 525         default:
 526                 break;
 527         }
 528
 529 out:
 530         return err;
 531 }
 532
 533 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 534 {
 535         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 536         struct phy *phy = host->generic_phy;
 537         int ret = 0;
 538
 539         if (ufs_qcom_is_link_off(hba)) {
 540                 /*
 541                  * Disable the tx/rx lane symbol clocks before PHY is
 542                  * powered down as the PLL source should be disabled
 543                  * after downstream clocks are disabled.
 544                  */
 545                 ufs_qcom_disable_lane_clks(host);
 546                 phy_power_off(phy);
 547                 goto out;
 548         }
 549
 550         /*
 551          * If UniPro link is not active, PHY ref_clk, main PHY analog power
 552          * rail and low noise analog power rail for PLL can be switched off.
 553          */
 554         if (!ufs_qcom_is_link_active(hba)) {
 555                 ufs_qcom_disable_lane_clks(host);
 556                 phy_power_off(phy);
 557         }
 558
 559 out:
 560         return ret;
 561 }
 562
 563 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 564 {
 565         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 566         struct phy *phy = host->generic_phy;
 567         int err;
 568
 569         err = phy_power_on(phy);
 570         if (err) {
 571                 dev_err(hba->dev, "%s: failed enabling regs, err = %d\n",
 572                         __func__, err);
 573                 goto out;
 574         }
 575
 576         err = ufs_qcom_enable_lane_clks(host);
 577         if (err)
 578                 goto out;
 579
 580         hba->is_sys_suspended = false;
 581
 582 out:
 583         return err;
 584 }
 585
 586 struct ufs_qcom_dev_params {
 587         u32 pwm_rx_gear;        /* pwm rx gear to work in */
 588         u32 pwm_tx_gear;        /* pwm tx gear to work in */
 589         u32 hs_rx_gear;         /* hs rx gear to work in */
 590         u32 hs_tx_gear;         /* hs tx gear to work in */
 591         u32 rx_lanes;           /* number of rx lanes */
 592         u32 tx_lanes;           /* number of tx lanes */
 593         u32 rx_pwr_pwm;         /* rx pwm working pwr */
 594         u32 tx_pwr_pwm;         /* tx pwm working pwr */
 595         u32 rx_pwr_hs;          /* rx hs working pwr */
 596         u32 tx_pwr_hs;          /* tx hs working pwr */
 597         u32 hs_rate;            /* rate A/B to work in HS */
 598         u32 desired_working_mode;
 599 };
 600
 601 static int ufs_qcom_get_pwr_dev_param(struct ufs_qcom_dev_params *qcom_param,
 602                                       struct ufs_pa_layer_attr *dev_max,
 603                                       struct ufs_pa_layer_attr *agreed_pwr)
 604 {
 605         int min_qcom_gear;
 606         int min_dev_gear;
 607         bool is_dev_sup_hs = false;
 608         bool is_qcom_max_hs = false;
 609
 610         if (dev_max->pwr_rx == FAST_MODE)
 611                 is_dev_sup_hs = true;
 612
 613         if (qcom_param->desired_working_mode == FAST) {
 614                 is_qcom_max_hs = true;
 615                 min_qcom_gear = min_t(u32, qcom_param->hs_rx_gear,
 616                                       qcom_param->hs_tx_gear);
 617         } else {
 618                 min_qcom_gear = min_t(u32, qcom_param->pwm_rx_gear,
 619                                       qcom_param->pwm_tx_gear);
 620         }
 621
 622         /*
 623          * device doesn't support HS but qcom_param->desired_working_mode is
 624          * HS, thus device and qcom_param don't agree
 625          */
 626         if (!is_dev_sup_hs && is_qcom_max_hs) {
 627                 pr_err("%s: failed to agree on power mode (device doesn't support HS but requested power is HS)\n",
 628                         __func__);
 629                 return -ENOTSUPP;
 630         } else if (is_dev_sup_hs && is_qcom_max_hs) {
 631                 /*
 632                  * since device supports HS, it supports FAST_MODE.
 633                  * since qcom_param->desired_working_mode is also HS
 634                  * then final decision (FAST/FASTAUTO) is done according
 635                  * to qcom_params as it is the restricting factor
 636                  */
 637                 agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
 638                                                 qcom_param->rx_pwr_hs;
 639         } else {
 640                 /*
 641                  * here qcom_param->desired_working_mode is PWM.
 642                  * it doesn't matter whether device supports HS or PWM,
 643                  * in both cases qcom_param->desired_working_mode will
 644                  * determine the mode
 645                  */
 646                  agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
 647                                                 qcom_param->rx_pwr_pwm;
 648         }
 649
 650         /*
 651          * we would like tx to work in the minimum number of lanes
 652          * between device capability and vendor preferences.
 653          * the same decision will be made for rx
 654          */
 655         agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
 656                                                 qcom_param->tx_lanes);
 657         agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
 658                                                 qcom_param->rx_lanes);
 659
 660         /* device maximum gear is the minimum between device rx and tx gears */
 661         min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
 662
 663         /*
 664          * if both device capabilities and vendor pre-defined preferences are
 665          * both HS or both PWM then set the minimum gear to be the chosen
 666          * working gear.
 667          * if one is PWM and one is HS then the one that is PWM get to decide
 668          * what is the gear, as it is the one that also decided previously what
 669          * pwr the device will be configured to.
 670          */
 671         if ((is_dev_sup_hs && is_qcom_max_hs) ||
 672             (!is_dev_sup_hs && !is_qcom_max_hs))
 673                 agreed_pwr->gear_rx = agreed_pwr->gear_tx =
 674                         min_t(u32, min_dev_gear, min_qcom_gear);
 675         else if (!is_dev_sup_hs)
 676                 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_dev_gear;
 677         else
 678                 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_qcom_gear;
 679
 680         agreed_pwr->hs_rate = qcom_param->hs_rate;
 681         return 0;
 682 }
 683
 684 #ifdef CONFIG_MSM_BUS_SCALING
 685 static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
 686                 const char *speed_mode)
 687 {
 688         struct device *dev = host->hba->dev;
 689         struct device_node *np = dev->of_node;
 690         int err;
 691         const char *key = "qcom,bus-vector-names";
 692
 693         if (!speed_mode) {
 694                 err = -EINVAL;
 695                 goto out;
 696         }
 697
 698         if (host->bus_vote.is_max_bw_needed && !!strcmp(speed_mode, "MIN"))
 699                 err = of_property_match_string(np, key, "MAX");
 700         else
 701                 err = of_property_match_string(np, key, speed_mode);
 702
 703 out:
 704         if (err < 0)
 705                 dev_err(dev, "%s: Invalid %s mode %d\n",
 706                                 __func__, speed_mode, err);
 707         return err;
 708 }
 709
 710 static void ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result)
 711 {
 712         int gear = max_t(u32, p->gear_rx, p->gear_tx);
 713         int lanes = max_t(u32, p->lane_rx, p->lane_tx);
 714         int pwr;
 715
 716         /* default to PWM Gear 1, Lane 1 if power mode is not initialized */
 717         if (!gear)
 718                 gear = 1;
 719
 720         if (!lanes)
 721                 lanes = 1;
 722
 723         if (!p->pwr_rx && !p->pwr_tx) {
 724                 pwr = SLOWAUTO_MODE;
 725                 snprintf(result, BUS_VECTOR_NAME_LEN, "MIN");
 726         } else if (p->pwr_rx == FAST_MODE || p->pwr_rx == FASTAUTO_MODE ||
 727                  p->pwr_tx == FAST_MODE || p->pwr_tx == FASTAUTO_MODE) {
 728                 pwr = FAST_MODE;
 729                 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_R%s_G%d_L%d", "HS",
 730                          p->hs_rate == PA_HS_MODE_B ? "B" : "A", gear, lanes);
 731         } else {
 732                 pwr = SLOW_MODE;
 733                 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_G%d_L%d",
 734                          "PWM", gear, lanes);
 735         }
 736 }
 737
 738 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
 739 {
 740         int err = 0;
 741
 742         if (vote != host->bus_vote.curr_vote) {
 743                 err = msm_bus_scale_client_update_request(
 744                                 host->bus_vote.client_handle, vote);
 745                 if (err) {
 746                         dev_err(host->hba->dev,
 747                                 "%s: msm_bus_scale_client_update_request() failed: bus_client_handle=0x%x, vote=%d, err=%d\n",
 748                                 __func__, host->bus_vote.client_handle,
 749                                 vote, err);
 750                         goto out;
 751                 }
 752
 753                 host->bus_vote.curr_vote = vote;
 754         }
 755 out:
 756         return err;
 757 }
 758
 759 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
 760 {
 761         int vote;
 762         int err = 0;
 763         char mode[BUS_VECTOR_NAME_LEN];
 764
 765         ufs_qcom_get_speed_mode(&host->dev_req_params, mode);
 766
 767         vote = ufs_qcom_get_bus_vote(host, mode);
 768         if (vote >= 0)
 769                 err = ufs_qcom_set_bus_vote(host, vote);
 770         else
 771                 err = vote;
 772
 773         if (err)
 774                 dev_err(host->hba->dev, "%s: failed %d\n", __func__, err);
 775         else
 776                 host->bus_vote.saved_vote = vote;
 777         return err;
 778 }
 779
 780 static ssize_t
 781 show_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
 782                         char *buf)
 783 {
 784         struct ufs_hba *hba = dev_get_drvdata(dev);
 785         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 786
 787         return snprintf(buf, PAGE_SIZE, "%u\n",
 788                         host->bus_vote.is_max_bw_needed);
 789 }
 790
 791 static ssize_t
 792 store_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
 793                 const char *buf, size_t count)
 794 {
 795         struct ufs_hba *hba = dev_get_drvdata(dev);
 796         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 797         uint32_t value;
 798
 799         if (!kstrtou32(buf, 0, &value)) {
 800                 host->bus_vote.is_max_bw_needed = !!value;
 801                 ufs_qcom_update_bus_bw_vote(host);
 802         }
 803
 804         return count;
 805 }
 806
 807 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
 808 {
 809         int err;
 810         struct msm_bus_scale_pdata *bus_pdata;
 811         struct device *dev = host->hba->dev;
 812         struct platform_device *pdev = to_platform_device(dev);
 813         struct device_node *np = dev->of_node;
 814
 815         bus_pdata = msm_bus_cl_get_pdata(pdev);
 816         if (!bus_pdata) {
 817                 dev_err(dev, "%s: failed to get bus vectors\n", __func__);
 818                 err = -ENODATA;
 819                 goto out;
 820         }
 821
 822         err = of_property_count_strings(np, "qcom,bus-vector-names");
 823         if (err < 0 || err != bus_pdata->num_usecases) {
 824                 dev_err(dev, "%s: qcom,bus-vector-names not specified correctly %d\n",
 825                                 __func__, err);
 826                 goto out;
 827         }
 828
 829         host->bus_vote.client_handle = msm_bus_scale_register_client(bus_pdata);
 830         if (!host->bus_vote.client_handle) {
 831                 dev_err(dev, "%s: msm_bus_scale_register_client failed\n",
 832                                 __func__);
 833                 err = -EFAULT;
 834                 goto out;
 835         }
 836
 837         /* cache the vote index for minimum and maximum bandwidth */
 838         host->bus_vote.min_bw_vote = ufs_qcom_get_bus_vote(host, "MIN");
 839         host->bus_vote.max_bw_vote = ufs_qcom_get_bus_vote(host, "MAX");
 840
 841         host->bus_vote.max_bus_bw.show = show_ufs_to_mem_max_bus_bw;
 842         host->bus_vote.max_bus_bw.store = store_ufs_to_mem_max_bus_bw;
 843         sysfs_attr_init(&host->bus_vote.max_bus_bw.attr);
 844         host->bus_vote.max_bus_bw.attr.name = "max_bus_bw";
 845         host->bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR;
 846         err = device_create_file(dev, &host->bus_vote.max_bus_bw);
 847 out:
 848         return err;
 849 }
 850 #else /* CONFIG_MSM_BUS_SCALING */
 851 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
 852 {
 853         return 0;
 854 }
 855
 856 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
 857 {
 858         return 0;
 859 }
 860
 861 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
 862 {
 863         return 0;
 864 }
 865 #endif /* CONFIG_MSM_BUS_SCALING */
 866
 867 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
 868 {
 869         if (host->dev_ref_clk_ctrl_mmio &&
 870             (enable ^ host->is_dev_ref_clk_enabled)) {
 871                 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
 872
 873                 if (enable)
 874                         temp |= host->dev_ref_clk_en_mask;
 875                 else
 876                         temp &= ~host->dev_ref_clk_en_mask;
 877
 878                 /*
 879                  * If we are here to disable this clock it might be immediately
 880                  * after entering into hibern8 in which case we need to make
 881                  * sure that device ref_clk is active at least 1us after the
 882                  * hibern8 enter.
 883                  */
 884                 if (!enable)
 885                         udelay(1);
 886
 887                 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
 888
 889                 /* ensure that ref_clk is enabled/disabled before we return */
 890                 wmb();
 891
 892                 /*
 893                  * If we call hibern8 exit after this, we need to make sure that
 894                  * device ref_clk is stable for at least 1us before the hibern8
 895                  * exit command.
 896                  */
 897                 if (enable)
 898                         udelay(1);
 899
 900                 host->is_dev_ref_clk_enabled = enable;
 901         }
 902 }
 903
 904 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
 905                                 enum ufs_notify_change_status status,
 906                                 struct ufs_pa_layer_attr *dev_max_params,
 907                                 struct ufs_pa_layer_attr *dev_req_params)
 908 {
 909         u32 val;
 910         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 911         struct ufs_qcom_dev_params ufs_qcom_cap;
 912         int ret = 0;
 913
 914         if (!dev_req_params) {
 915                 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
 916                 ret = -EINVAL;
 917                 goto out;
 918         }
 919
 920         switch (status) {
 921         case PRE_CHANGE:
 922                 ufs_qcom_cap.tx_lanes = UFS_QCOM_LIMIT_NUM_LANES_TX;
 923                 ufs_qcom_cap.rx_lanes = UFS_QCOM_LIMIT_NUM_LANES_RX;
 924                 ufs_qcom_cap.hs_rx_gear = UFS_QCOM_LIMIT_HSGEAR_RX;
 925                 ufs_qcom_cap.hs_tx_gear = UFS_QCOM_LIMIT_HSGEAR_TX;
 926                 ufs_qcom_cap.pwm_rx_gear = UFS_QCOM_LIMIT_PWMGEAR_RX;
 927                 ufs_qcom_cap.pwm_tx_gear = UFS_QCOM_LIMIT_PWMGEAR_TX;
 928                 ufs_qcom_cap.rx_pwr_pwm = UFS_QCOM_LIMIT_RX_PWR_PWM;
 929                 ufs_qcom_cap.tx_pwr_pwm = UFS_QCOM_LIMIT_TX_PWR_PWM;
 930                 ufs_qcom_cap.rx_pwr_hs = UFS_QCOM_LIMIT_RX_PWR_HS;
 931                 ufs_qcom_cap.tx_pwr_hs = UFS_QCOM_LIMIT_TX_PWR_HS;
 932                 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
 933                 ufs_qcom_cap.desired_working_mode =
 934                                         UFS_QCOM_LIMIT_DESIRED_MODE;
 935
 936                 if (host->hw_ver.major == 0x1) {
 937                         /*
 938                          * HS-G3 operations may not reliably work on legacy QCOM
 939                          * UFS host controller hardware even though capability
 940                          * exchange during link startup phase may end up
 941                          * negotiating maximum supported gear as G3.
 942                          * Hence downgrade the maximum supported gear to HS-G2.
 943                          */
 944                         if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2)
 945                                 ufs_qcom_cap.hs_tx_gear = UFS_HS_G2;
 946                         if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2)
 947                                 ufs_qcom_cap.hs_rx_gear = UFS_HS_G2;
 948                 }
 949
 950                 ret = ufs_qcom_get_pwr_dev_param(&ufs_qcom_cap,
 951                                                  dev_max_params,
 952                                                  dev_req_params);
 953                 if (ret) {
 954                         pr_err("%s: failed to determine capabilities\n",
 955                                         __func__);
 956                         goto out;
 957                 }
 958
 959                 /* enable the device ref clock before changing to HS mode */
 960                 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
 961                         ufshcd_is_hs_mode(dev_req_params))
 962                         ufs_qcom_dev_ref_clk_ctrl(host, true);
 963                 break;
 964         case POST_CHANGE:
 965                 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
 966                                         dev_req_params->pwr_rx,
 967                                         dev_req_params->hs_rate, false)) {
 968                         dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
 969                                 __func__);
 970                         /*
 971                          * we return error code at the end of the routine,
 972                          * but continue to configure UFS_PHY_TX_LANE_ENABLE
 973                          * and bus voting as usual
 974                          */
 975                         ret = -EINVAL;
 976                 }
 977
 978                 val = ~(MAX_U32 << dev_req_params->lane_tx);
 979
 980                 /* cache the power mode parameters to use internally */
 981                 memcpy(&host->dev_req_params,
 982                                 dev_req_params, sizeof(*dev_req_params));
 983                 ufs_qcom_update_bus_bw_vote(host);
 984
 985                 /* disable the device ref clock if entered PWM mode */
 986                 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
 987                         !ufshcd_is_hs_mode(dev_req_params))
 988                         ufs_qcom_dev_ref_clk_ctrl(host, false);
 989                 break;
 990         default:
 991                 ret = -EINVAL;
 992                 break;
 993         }
 994 out:
 995         return ret;
 996 }
 997
 998 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
 999 {
1000         int err;
1001         u32 pa_vs_config_reg1;
1002
1003         err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
1004                              &pa_vs_config_reg1);
1005         if (err)
1006                 goto out;
1007
1008         /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
1009         err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
1010                             (pa_vs_config_reg1 | (1 << 12)));
1011
1012 out:
1013         return err;
1014 }
1015
1016 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
1017 {
1018         int err = 0;
1019
1020         if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
1021                 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
1022
1023         return err;
1024 }
1025
1026 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
1027 {
1028         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1029
1030         if (host->hw_ver.major == 0x1)
1031                 return UFSHCI_VERSION_11;
1032         else
1033                 return UFSHCI_VERSION_20;
1034 }
1035
1036 /**
1037  * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
1038  * @hba: host controller instance
1039  *
1040  * QCOM UFS host controller might have some non standard behaviours (quirks)
1041  * than what is specified by UFSHCI specification. Advertise all such
1042  * quirks to standard UFS host controller driver so standard takes them into
1043  * account.
1044  */
1045 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
1046 {
1047         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1048
1049         if (host->hw_ver.major == 0x01) {
1050                 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1051                             | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
1052                             | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
1053
1054                 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
1055                         hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
1056
1057                 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
1058         }
1059
1060         if (host->hw_ver.major == 0x2) {
1061                 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
1062
1063                 if (!ufs_qcom_cap_qunipro(host))
1064                         /* Legacy UniPro mode still need following quirks */
1065                         hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1066                                 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
1067                                 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
1068         }
1069 }
1070
1071 static void ufs_qcom_set_caps(struct ufs_hba *hba)
1072 {
1073         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1074
1075         hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1076         hba->caps |= UFSHCD_CAP_CLK_SCALING;
1077         hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1078
1079         if (host->hw_ver.major >= 0x2) {
1080                 host->caps = UFS_QCOM_CAP_QUNIPRO |
1081                              UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE;
1082         }
1083 }
1084
1085 /**
1086  * ufs_qcom_setup_clocks - enables/disable clocks
1087  * @hba: host controller instance
1088  * @on: If true, enable clocks else disable them.
1089  * @status: PRE_CHANGE or POST_CHANGE notify
1090  *
1091  * Returns 0 on success, non-zero on failure.
1092  */
1093 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
1094                                  enum ufs_notify_change_status status)
1095 {
1096         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1097         int err;
1098         int vote = 0;
1099
1100         /*
1101          * In case ufs_qcom_init() is not yet done, simply ignore.
1102          * This ufs_qcom_setup_clocks() shall be called from
1103          * ufs_qcom_init() after init is done.
1104          */
1105         if (!host)
1106                 return 0;
1107
1108         if (on && (status == POST_CHANGE)) {
1109                 phy_power_on(host->generic_phy);
1110
1111                 /* enable the device ref clock for HS mode*/
1112                 if (ufshcd_is_hs_mode(&hba->pwr_info))
1113                         ufs_qcom_dev_ref_clk_ctrl(host, true);
1114                 vote = host->bus_vote.saved_vote;
1115                 if (vote == host->bus_vote.min_bw_vote)
1116                         ufs_qcom_update_bus_bw_vote(host);
1117
1118         } else if (!on && (status == PRE_CHANGE)) {
1119                 if (!ufs_qcom_is_link_active(hba)) {
1120                         /* disable device ref_clk */
1121                         ufs_qcom_dev_ref_clk_ctrl(host, false);
1122
1123                         /* powering off PHY during aggressive clk gating */
1124                         phy_power_off(host->generic_phy);
1125                 }
1126
1127                 vote = host->bus_vote.min_bw_vote;
1128         }
1129
1130         err = ufs_qcom_set_bus_vote(host, vote);
1131         if (err)
1132                 dev_err(hba->dev, "%s: set bus vote failed %d\n",
1133                                 __func__, err);
1134
1135         return err;
1136 }
1137
1138 static int
1139 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
1140 {
1141         struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1142
1143         /* Currently this code only knows about a single reset. */
1144         WARN_ON(id);
1145         ufs_qcom_assert_reset(host->hba);
1146         /* provide 1ms delay to let the reset pulse propagate. */
1147         usleep_range(1000, 1100);
1148         return 0;
1149 }
1150
1151 static int
1152 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
1153 {
1154         struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1155
1156         /* Currently this code only knows about a single reset. */
1157         WARN_ON(id);
1158         ufs_qcom_deassert_reset(host->hba);
1159
1160         /*
1161          * after reset deassertion, phy will need all ref clocks,
1162          * voltage, current to settle down before starting serdes.
1163          */
1164         usleep_range(1000, 1100);
1165         return 0;
1166 }
1167
1168 static const struct reset_control_ops ufs_qcom_reset_ops = {
1169         .assert = ufs_qcom_reset_assert,
1170         .deassert = ufs_qcom_reset_deassert,
1171 };
1172
1173 #define ANDROID_BOOT_DEV_MAX    30
1174 static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
1175
1176 #ifndef MODULE
1177 static int __init get_android_boot_dev(char *str)
1178 {
1179         strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX);
1180         return 1;
1181 }
1182 __setup("androidboot.bootdevice=", get_android_boot_dev);
1183 #endif
1184
1185 /**
1186  * ufs_qcom_init - bind phy with controller
1187  * @hba: host controller instance
1188  *
1189  * Binds PHY with controller and powers up PHY enabling clocks
1190  * and regulators.
1191  *
1192  * Returns -EPROBE_DEFER if binding fails, returns negative error
1193  * on phy power up failure and returns zero on success.
1194  */
1195 static int ufs_qcom_init(struct ufs_hba *hba)
1196 {
1197         int err;
1198         struct device *dev = hba->dev;
1199         struct platform_device *pdev = to_platform_device(dev);
1200         struct ufs_qcom_host *host;
1201         struct resource *res;
1202
1203         if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
1204                 return -ENODEV;
1205
1206         host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1207         if (!host) {
1208                 err = -ENOMEM;
1209                 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
1210                 goto out;
1211         }
1212
1213         /* Make a two way bind between the qcom host and the hba */
1214         host->hba = hba;
1215         ufshcd_set_variant(hba, host);
1216
1217         /* Fire up the reset controller. Failure here is non-fatal. */
1218         host->rcdev.of_node = dev->of_node;
1219         host->rcdev.ops = &ufs_qcom_reset_ops;
1220         host->rcdev.owner = dev->driver->owner;
1221         host->rcdev.nr_resets = 1;
1222         err = devm_reset_controller_register(dev, &host->rcdev);
1223         if (err) {
1224                 dev_warn(dev, "Failed to register reset controller\n");
1225                 err = 0;
1226         }
1227
1228         /*
1229          * voting/devoting device ref_clk source is time consuming hence
1230          * skip devoting it during aggressive clock gating. This clock
1231          * will still be gated off during runtime suspend.
1232          */
1233         host->generic_phy = devm_phy_get(dev, "ufsphy");
1234
1235         if (host->generic_phy == ERR_PTR(-EPROBE_DEFER)) {
1236                 /*
1237                  * UFS driver might be probed before the phy driver does.
1238                  * In that case we would like to return EPROBE_DEFER code.
1239                  */
1240                 err = -EPROBE_DEFER;
1241                 dev_warn(dev, "%s: required phy device. hasn't probed yet. err = %d\n",
1242                         __func__, err);
1243                 goto out_variant_clear;
1244         } else if (IS_ERR(host->generic_phy)) {
1245                 err = PTR_ERR(host->generic_phy);
1246                 dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
1247                 goto out_variant_clear;
1248         }
1249
1250         err = ufs_qcom_bus_register(host);
1251         if (err)
1252                 goto out_variant_clear;
1253
1254         ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1255                 &host->hw_ver.minor, &host->hw_ver.step);
1256
1257         /*
1258          * for newer controllers, device reference clock control bit has
1259          * moved inside UFS controller register address space itself.
1260          */
1261         if (host->hw_ver.major >= 0x02) {
1262                 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1263                 host->dev_ref_clk_en_mask = BIT(26);
1264         } else {
1265                 /* "dev_ref_clk_ctrl_mem" is optional resource */
1266                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1267                 if (res) {
1268                         host->dev_ref_clk_ctrl_mmio =
1269                                         devm_ioremap_resource(dev, res);
1270                         if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) {
1271                                 dev_warn(dev,
1272                                         "%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n",
1273                                         __func__,
1274                                         PTR_ERR(host->dev_ref_clk_ctrl_mmio));
1275                                 host->dev_ref_clk_ctrl_mmio = NULL;
1276                         }
1277                         host->dev_ref_clk_en_mask = BIT(5);
1278                 }
1279         }
1280
1281         err = ufs_qcom_init_lane_clks(host);
1282         if (err)
1283                 goto out_variant_clear;
1284
1285         ufs_qcom_set_caps(hba);
1286         ufs_qcom_advertise_quirks(hba);
1287
1288         ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1289
1290         if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
1291                 ufs_qcom_hosts[hba->dev->id] = host;
1292
1293         host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
1294         ufs_qcom_get_default_testbus_cfg(host);
1295         err = ufs_qcom_testbus_config(host);
1296         if (err) {
1297                 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1298                                 __func__, err);
1299                 err = 0;
1300         }
1301
1302         goto out;
1303
1304 out_variant_clear:
1305         ufshcd_set_variant(hba, NULL);
1306 out:
1307         return err;
1308 }
1309
1310 static void ufs_qcom_exit(struct ufs_hba *hba)
1311 {
1312         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1313
1314         ufs_qcom_disable_lane_clks(host);
1315         phy_power_off(host->generic_phy);
1316         phy_exit(host->generic_phy);
1317 }
1318
1319 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
1320                                                        u32 clk_cycles)
1321 {
1322         int err;
1323         u32 core_clk_ctrl_reg;
1324
1325         if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
1326                 return -EINVAL;
1327
1328         err = ufshcd_dme_get(hba,
1329                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1330                             &core_clk_ctrl_reg);
1331         if (err)
1332                 goto out;
1333
1334         core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
1335         core_clk_ctrl_reg |= clk_cycles;
1336
1337         /* Clear CORE_CLK_DIV_EN */
1338         core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1339
1340         err = ufshcd_dme_set(hba,
1341                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1342                             core_clk_ctrl_reg);
1343 out:
1344         return err;
1345 }
1346
1347 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1348 {
1349         /* nothing to do as of now */
1350         return 0;
1351 }
1352
1353 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1354 {
1355         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1356
1357         if (!ufs_qcom_cap_qunipro(host))
1358                 return 0;
1359
1360         /* set unipro core clock cycles to 150 and clear clock divider */
1361         return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);
1362 }
1363
1364 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1365 {
1366         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1367         int err;
1368         u32 core_clk_ctrl_reg;
1369
1370         if (!ufs_qcom_cap_qunipro(host))
1371                 return 0;
1372
1373         err = ufshcd_dme_get(hba,
1374                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1375                             &core_clk_ctrl_reg);
1376
1377         /* make sure CORE_CLK_DIV_EN is cleared */
1378         if (!err &&
1379             (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1380                 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1381                 err = ufshcd_dme_set(hba,
1382                                     UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1383                                     core_clk_ctrl_reg);
1384         }
1385
1386         return err;
1387 }
1388
1389 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1390 {
1391         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1392
1393         if (!ufs_qcom_cap_qunipro(host))
1394                 return 0;
1395
1396         /* set unipro core clock cycles to 75 and clear clock divider */
1397         return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);
1398 }
1399
1400 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1401                 bool scale_up, enum ufs_notify_change_status status)
1402 {
1403         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1404         struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1405         int err = 0;
1406
1407         if (status == PRE_CHANGE) {
1408                 if (scale_up)
1409                         err = ufs_qcom_clk_scale_up_pre_change(hba);
1410                 else
1411                         err = ufs_qcom_clk_scale_down_pre_change(hba);
1412         } else {
1413                 if (scale_up)
1414                         err = ufs_qcom_clk_scale_up_post_change(hba);
1415                 else
1416                         err = ufs_qcom_clk_scale_down_post_change(hba);
1417
1418                 if (err || !dev_req_params)
1419                         goto out;
1420
1421                 ufs_qcom_cfg_timers(hba,
1422                                     dev_req_params->gear_rx,
1423                                     dev_req_params->pwr_rx,
1424                                     dev_req_params->hs_rate,
1425                                     false);
1426                 ufs_qcom_update_bus_bw_vote(host);
1427         }
1428
1429 out:
1430         return err;
1431 }
1432
1433 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
1434                 void *priv, void (*print_fn)(struct ufs_hba *hba,
1435                 int offset, int num_regs, const char *str, void *priv))
1436 {
1437         u32 reg;
1438         struct ufs_qcom_host *host;
1439
1440         if (unlikely(!hba)) {
1441                 pr_err("%s: hba is NULL\n", __func__);
1442                 return;
1443         }
1444         if (unlikely(!print_fn)) {
1445                 dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);
1446                 return;
1447         }
1448
1449         host = ufshcd_get_variant(hba);
1450         if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
1451                 return;
1452
1453         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1454         print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);
1455
1456         reg = ufshcd_readl(hba, REG_UFS_CFG1);
1457         reg |= UTP_DBG_RAMS_EN;
1458         ufshcd_writel(hba, reg, REG_UFS_CFG1);
1459
1460         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1461         print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);
1462
1463         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1464         print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);
1465
1466         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1467         print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);
1468
1469         /* clear bit 17 - UTP_DBG_RAMS_EN */
1470         ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1471
1472         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1473         print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);
1474
1475         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1476         print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);
1477
1478         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1479         print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);
1480
1481         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1482         print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);
1483
1484         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1485         print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);
1486
1487         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1488         print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);
1489
1490         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1491         print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);
1492 }
1493
1494 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1495 {
1496         if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {
1497                 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1498                                 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1499                 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1500         } else {
1501                 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);
1502                 ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
1503         }
1504 }
1505
1506 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1507 {
1508         /* provide a legal default configuration */
1509         host->testbus.select_major = TSTBUS_UNIPRO;
1510         host->testbus.select_minor = 37;
1511 }
1512
1513 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1514 {
1515         if (host->testbus.select_major >= TSTBUS_MAX) {
1516                 dev_err(host->hba->dev,
1517                         "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1518                         __func__, host->testbus.select_major);
1519                 return false;
1520         }
1521
1522         return true;
1523 }
1524
1525 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1526 {
1527         int reg;
1528         int offset;
1529         u32 mask = TEST_BUS_SUB_SEL_MASK;
1530
1531         if (!host)
1532                 return -EINVAL;
1533
1534         if (!ufs_qcom_testbus_cfg_is_ok(host))
1535                 return -EPERM;
1536
1537         switch (host->testbus.select_major) {
1538         case TSTBUS_UAWM:
1539                 reg = UFS_TEST_BUS_CTRL_0;
1540                 offset = 24;
1541                 break;
1542         case TSTBUS_UARM:
1543                 reg = UFS_TEST_BUS_CTRL_0;
1544                 offset = 16;
1545                 break;
1546         case TSTBUS_TXUC:
1547                 reg = UFS_TEST_BUS_CTRL_0;
1548                 offset = 8;
1549                 break;
1550         case TSTBUS_RXUC:
1551                 reg = UFS_TEST_BUS_CTRL_0;
1552                 offset = 0;
1553                 break;
1554         case TSTBUS_DFC:
1555                 reg = UFS_TEST_BUS_CTRL_1;
1556                 offset = 24;
1557                 break;
1558         case TSTBUS_TRLUT:
1559                 reg = UFS_TEST_BUS_CTRL_1;
1560                 offset = 16;
1561                 break;
1562         case TSTBUS_TMRLUT:
1563                 reg = UFS_TEST_BUS_CTRL_1;
1564                 offset = 8;
1565                 break;
1566         case TSTBUS_OCSC:
1567                 reg = UFS_TEST_BUS_CTRL_1;
1568                 offset = 0;
1569                 break;
1570         case TSTBUS_WRAPPER:
1571                 reg = UFS_TEST_BUS_CTRL_2;
1572                 offset = 16;
1573                 break;
1574         case TSTBUS_COMBINED:
1575                 reg = UFS_TEST_BUS_CTRL_2;
1576                 offset = 8;
1577                 break;
1578         case TSTBUS_UTP_HCI:
1579                 reg = UFS_TEST_BUS_CTRL_2;
1580                 offset = 0;
1581                 break;
1582         case TSTBUS_UNIPRO:
1583                 reg = UFS_UNIPRO_CFG;
1584                 offset = 20;
1585                 mask = 0xFFF;
1586                 break;
1587         /*
1588          * No need for a default case, since
1589          * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1590          * is legal
1591          */
1592         }
1593         mask <<= offset;
1594
1595         pm_runtime_get_sync(host->hba->dev);
1596         ufshcd_hold(host->hba, false);
1597         ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1598                     (u32)host->testbus.select_major << 19,
1599                     REG_UFS_CFG1);
1600         ufshcd_rmwl(host->hba, mask,
1601                     (u32)host->testbus.select_minor << offset,
1602                     reg);
1603         ufs_qcom_enable_test_bus(host);
1604         /*
1605          * Make sure the test bus configuration is
1606          * committed before returning.
1607          */
1608         mb();
1609         ufshcd_release(host->hba);
1610         pm_runtime_put_sync(host->hba->dev);
1611
1612         return 0;
1613 }
1614
1615 static void ufs_qcom_testbus_read(struct ufs_hba *hba)
1616 {
1617         ufshcd_dump_regs(hba, UFS_TEST_BUS, 4, "UFS_TEST_BUS ");
1618 }
1619
1620 static void ufs_qcom_print_unipro_testbus(struct ufs_hba *hba)
1621 {
1622         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1623         u32 *testbus = NULL;
1624         int i, nminor = 256, testbus_len = nminor * sizeof(u32);
1625
1626         testbus = kmalloc(testbus_len, GFP_KERNEL);
1627         if (!testbus)
1628                 return;
1629
1630         host->testbus.select_major = TSTBUS_UNIPRO;
1631         for (i = 0; i < nminor; i++) {
1632                 host->testbus.select_minor = i;
1633                 ufs_qcom_testbus_config(host);
1634                 testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS);
1635         }
1636         print_hex_dump(KERN_ERR, "UNIPRO_TEST_BUS ", DUMP_PREFIX_OFFSET,
1637                         16, 4, testbus, testbus_len, false);
1638         kfree(testbus);
1639 }
1640
1641 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1642 {
1643         ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1644                          "HCI Vendor Specific Registers ");
1645
1646         /* sleep a bit intermittently as we are dumping too much data */
1647         ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);
1648         usleep_range(1000, 1100);
1649         ufs_qcom_testbus_read(hba);
1650         usleep_range(1000, 1100);
1651         ufs_qcom_print_unipro_testbus(hba);
1652         usleep_range(1000, 1100);
1653 }
1654
1655 /**
1656  * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1657  *
1658  * The variant operations configure the necessary controller and PHY
1659  * handshake during initialization.
1660  */
1661 static struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1662         .name                   = "qcom",
1663         .init                   = ufs_qcom_init,
1664         .exit                   = ufs_qcom_exit,
1665         .get_ufs_hci_version    = ufs_qcom_get_ufs_hci_version,
1666         .clk_scale_notify       = ufs_qcom_clk_scale_notify,
1667         .setup_clocks           = ufs_qcom_setup_clocks,
1668         .hce_enable_notify      = ufs_qcom_hce_enable_notify,
1669         .link_startup_notify    = ufs_qcom_link_startup_notify,
1670         .pwr_change_notify      = ufs_qcom_pwr_change_notify,
1671         .apply_dev_quirks       = ufs_qcom_apply_dev_quirks,
1672         .suspend                = ufs_qcom_suspend,
1673         .resume                 = ufs_qcom_resume,
1674         .dbg_register_dump      = ufs_qcom_dump_dbg_regs,
1675 };
1676
1677 /**
1678  * ufs_qcom_probe - probe routine of the driver
1679  * @pdev: pointer to Platform device handle
1680  *
1681  * Return zero for success and non-zero for failure
1682  */
1683 static int ufs_qcom_probe(struct platform_device *pdev)
1684 {
1685         int err;
1686         struct device *dev = &pdev->dev;
1687
1688         /* Perform generic probe */
1689         err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1690         if (err)
1691                 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1692
1693         return err;
1694 }
1695
1696 /**
1697  * ufs_qcom_remove - set driver_data of the device to NULL
1698  * @pdev: pointer to platform device handle
1699  *
1700  * Always returns 0
1701  */
1702 static int ufs_qcom_remove(struct platform_device *pdev)
1703 {
1704         struct ufs_hba *hba =  platform_get_drvdata(pdev);
1705
1706         pm_runtime_get_sync(&(pdev)->dev);
1707         ufshcd_remove(hba);
1708         return 0;
1709 }
1710
1711 static const struct of_device_id ufs_qcom_of_match[] = {
1712         { .compatible = "qcom,ufshc"},
1713         {},
1714 };
1715 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1716
1717 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1718         .suspend        = ufshcd_pltfrm_suspend,
1719         .resume         = ufshcd_pltfrm_resume,
1720         .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
1721         .runtime_resume  = ufshcd_pltfrm_runtime_resume,
1722         .runtime_idle    = ufshcd_pltfrm_runtime_idle,
1723 };
1724
1725 static struct platform_driver ufs_qcom_pltform = {
1726         .probe  = ufs_qcom_probe,
1727         .remove = ufs_qcom_remove,
1728         .shutdown = ufshcd_pltfrm_shutdown,
1729         .driver = {
1730                 .name   = "ufshcd-qcom",
1731                 .pm     = &ufs_qcom_pm_ops,
1732                 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1733         },
1734 };
1735 module_platform_driver(ufs_qcom_pltform);
1736
1737 MODULE_LICENSE("GPL v2");