1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 MediaTek Inc.
5 * Stanley Chu <stanley.chu@mediatek.com>
6 * Peter Wang <peter.wang@mediatek.com>
9 #include <linux/arm-smccc.h>
10 #include <linux/bitfield.h>
12 #include <linux/of_address.h>
13 #include <linux/phy/phy.h>
14 #include <linux/platform_device.h>
15 #include <linux/soc/mediatek/mtk_sip_svc.h>
18 #include "ufshcd-pltfrm.h"
19 #include "ufs_quirks.h"
21 #include "ufs-mediatek.h"
23 #define ufs_mtk_smc(cmd, val, res) \
24 arm_smccc_smc(MTK_SIP_UFS_CONTROL, \
25 cmd, val, 0, 0, 0, 0, 0, &(res))
27 #define ufs_mtk_ref_clk_notify(on, res) \
28 ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, on, res)
30 #define ufs_mtk_device_reset_ctrl(high, res) \
31 ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, high, res)
33 static struct ufs_dev_fix ufs_mtk_dev_fixups[] = {
34 UFS_FIX(UFS_VENDOR_SKHYNIX, "H9HQ21AFAMZDAR",
35 UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES),
39 static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
45 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
47 (1 << RX_SYMBOL_CLK_GATE_EN) |
48 (1 << SYS_CLK_GATE_EN) |
49 (1 << TX_CLK_GATE_EN);
51 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
54 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);
55 tmp = tmp & ~(1 << TX_SYMBOL_CLK_REQ_FORCE);
57 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);
60 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
61 tmp = tmp & ~((1 << RX_SYMBOL_CLK_GATE_EN) |
62 (1 << SYS_CLK_GATE_EN) |
63 (1 << TX_CLK_GATE_EN));
65 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
68 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);
69 tmp = tmp | (1 << TX_SYMBOL_CLK_REQ_FORCE);
71 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);
75 static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
76 enum ufs_notify_change_status status)
78 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
80 if (status == PRE_CHANGE) {
82 hba->vps->hba_enable_delay_us = 0;
84 hba->vps->hba_enable_delay_us = 600;
90 static int ufs_mtk_bind_mphy(struct ufs_hba *hba)
92 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
93 struct device *dev = hba->dev;
94 struct device_node *np = dev->of_node;
97 host->mphy = devm_of_phy_get_by_index(dev, np, 0);
99 if (host->mphy == ERR_PTR(-EPROBE_DEFER)) {
101 * UFS driver might be probed before the phy driver does.
102 * In that case we would like to return EPROBE_DEFER code.
106 "%s: required phy hasn't probed yet. err = %d\n",
108 } else if (IS_ERR(host->mphy)) {
109 err = PTR_ERR(host->mphy);
110 dev_info(dev, "%s: PHY get failed %d\n", __func__, err);
119 static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on)
121 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
122 struct arm_smccc_res res;
123 unsigned long timeout;
126 if (host->ref_clk_enabled == on)
130 ufs_mtk_ref_clk_notify(on, res);
131 ufshcd_delay_us(host->ref_clk_ungating_wait_us, 10);
132 ufshcd_writel(hba, REFCLK_REQUEST, REG_UFS_REFCLK_CTRL);
134 ufshcd_writel(hba, REFCLK_RELEASE, REG_UFS_REFCLK_CTRL);
138 timeout = jiffies + msecs_to_jiffies(REFCLK_REQ_TIMEOUT_MS);
140 value = ufshcd_readl(hba, REG_UFS_REFCLK_CTRL);
142 /* Wait until ack bit equals to req bit */
143 if (((value & REFCLK_ACK) >> 1) == (value & REFCLK_REQUEST))
146 usleep_range(100, 200);
147 } while (time_before(jiffies, timeout));
149 dev_err(hba->dev, "missing ack of refclk req, reg: 0x%x\n", value);
151 ufs_mtk_ref_clk_notify(host->ref_clk_enabled, res);
156 host->ref_clk_enabled = on;
158 ufshcd_delay_us(host->ref_clk_gating_wait_us, 10);
159 ufs_mtk_ref_clk_notify(on, res);
165 static void ufs_mtk_setup_ref_clk_wait_us(struct ufs_hba *hba,
166 u16 gating_us, u16 ungating_us)
168 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
170 if (hba->dev_info.clk_gating_wait_us) {
171 host->ref_clk_gating_wait_us =
172 hba->dev_info.clk_gating_wait_us;
174 host->ref_clk_gating_wait_us = gating_us;
177 host->ref_clk_ungating_wait_us = ungating_us;
180 static u32 ufs_mtk_link_get_state(struct ufs_hba *hba)
184 ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
185 val = ufshcd_readl(hba, REG_UFS_PROBE);
192 * ufs_mtk_setup_clocks - enables/disable clocks
193 * @hba: host controller instance
194 * @on: If true, enable clocks else disable them.
195 * @status: PRE_CHANGE or POST_CHANGE notify
197 * Returns 0 on success, non-zero on failure.
199 static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on,
200 enum ufs_notify_change_status status)
202 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
206 * In case ufs_mtk_init() is not yet done, simply ignore.
207 * This ufs_mtk_setup_clocks() shall be called from
208 * ufs_mtk_init() after init is done.
213 if (!on && status == PRE_CHANGE) {
214 if (!ufshcd_is_link_active(hba)) {
215 ufs_mtk_setup_ref_clk(hba, on);
216 ret = phy_power_off(host->mphy);
219 * Gate ref-clk if link state is in Hibern8
220 * triggered by Auto-Hibern8.
222 if (!ufshcd_can_hibern8_during_gating(hba) &&
223 ufshcd_is_auto_hibern8_enabled(hba) &&
224 ufs_mtk_link_get_state(hba) ==
226 ufs_mtk_setup_ref_clk(hba, on);
228 } else if (on && status == POST_CHANGE) {
229 ret = phy_power_on(host->mphy);
230 ufs_mtk_setup_ref_clk(hba, on);
237 * ufs_mtk_init - find other essential mmio bases
238 * @hba: host controller instance
240 * Binds PHY with controller and powers up PHY enabling clocks
243 * Returns -EPROBE_DEFER if binding fails, returns negative error
244 * on phy power up failure and returns zero on success.
246 static int ufs_mtk_init(struct ufs_hba *hba)
248 struct ufs_mtk_host *host;
249 struct device *dev = hba->dev;
252 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
255 dev_info(dev, "%s: no memory for mtk ufs host\n", __func__);
260 ufshcd_set_variant(hba, host);
262 err = ufs_mtk_bind_mphy(hba);
264 goto out_variant_clear;
266 /* Enable runtime autosuspend */
267 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
269 /* Enable clock-gating */
270 hba->caps |= UFSHCD_CAP_CLK_GATING;
272 /* Enable WriteBooster */
273 hba->caps |= UFSHCD_CAP_WB_EN;
274 hba->vps->wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(80);
277 * ufshcd_vops_init() is invoked after
278 * ufshcd_setup_clock(true) in ufshcd_hba_init() thus
279 * phy clock setup is skipped.
281 * Enable phy clocks specifically here.
283 ufs_mtk_setup_clocks(hba, true, POST_CHANGE);
288 ufshcd_set_variant(hba, NULL);
293 static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
294 struct ufs_pa_layer_attr *dev_max_params,
295 struct ufs_pa_layer_attr *dev_req_params)
297 struct ufs_dev_params host_cap;
300 host_cap.tx_lanes = UFS_MTK_LIMIT_NUM_LANES_TX;
301 host_cap.rx_lanes = UFS_MTK_LIMIT_NUM_LANES_RX;
302 host_cap.hs_rx_gear = UFS_MTK_LIMIT_HSGEAR_RX;
303 host_cap.hs_tx_gear = UFS_MTK_LIMIT_HSGEAR_TX;
304 host_cap.pwm_rx_gear = UFS_MTK_LIMIT_PWMGEAR_RX;
305 host_cap.pwm_tx_gear = UFS_MTK_LIMIT_PWMGEAR_TX;
306 host_cap.rx_pwr_pwm = UFS_MTK_LIMIT_RX_PWR_PWM;
307 host_cap.tx_pwr_pwm = UFS_MTK_LIMIT_TX_PWR_PWM;
308 host_cap.rx_pwr_hs = UFS_MTK_LIMIT_RX_PWR_HS;
309 host_cap.tx_pwr_hs = UFS_MTK_LIMIT_TX_PWR_HS;
310 host_cap.hs_rate = UFS_MTK_LIMIT_HS_RATE;
311 host_cap.desired_working_mode =
312 UFS_MTK_LIMIT_DESIRED_MODE;
314 ret = ufshcd_get_pwr_dev_param(&host_cap,
318 pr_info("%s: failed to determine capabilities\n",
325 static int ufs_mtk_pwr_change_notify(struct ufs_hba *hba,
326 enum ufs_notify_change_status stage,
327 struct ufs_pa_layer_attr *dev_max_params,
328 struct ufs_pa_layer_attr *dev_req_params)
334 ret = ufs_mtk_pre_pwr_change(hba, dev_max_params,
347 static int ufs_mtk_unipro_set_pm(struct ufs_hba *hba, u32 lpm)
350 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
352 ret = ufshcd_dme_set(hba,
353 UIC_ARG_MIB_SEL(VS_UNIPROPOWERDOWNCONTROL, 0),
356 host->unipro_lpm = lpm;
361 static int ufs_mtk_pre_link(struct ufs_hba *hba)
366 ufs_mtk_unipro_set_pm(hba, 0);
369 * Setting PA_Local_TX_LCC_Enable to 0 before link startup
370 * to make sure that both host and device TX LCC are disabled
371 * once link startup is completed.
373 ret = ufshcd_disable_host_tx_lcc(hba);
377 /* disable deep stall */
378 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
384 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
389 static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
394 if (ufshcd_is_clkgating_allowed(hba)) {
395 if (ufshcd_is_auto_hibern8_supported(hba) && hba->ahit)
396 ah_ms = FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK,
400 spin_lock_irqsave(hba->host->host_lock, flags);
401 hba->clk_gating.delay_ms = ah_ms + 5;
402 spin_unlock_irqrestore(hba->host->host_lock, flags);
406 static int ufs_mtk_post_link(struct ufs_hba *hba)
408 /* enable unipro clock gating feature */
409 ufs_mtk_cfg_unipro_cg(hba, true);
411 /* configure auto-hibern8 timer to 10ms */
412 if (ufshcd_is_auto_hibern8_supported(hba)) {
413 ufshcd_auto_hibern8_update(hba,
414 FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 10) |
415 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3));
418 ufs_mtk_setup_clk_gating(hba);
423 static int ufs_mtk_link_startup_notify(struct ufs_hba *hba,
424 enum ufs_notify_change_status stage)
430 ret = ufs_mtk_pre_link(hba);
433 ret = ufs_mtk_post_link(hba);
443 static void ufs_mtk_device_reset(struct ufs_hba *hba)
445 struct arm_smccc_res res;
447 ufs_mtk_device_reset_ctrl(0, res);
450 * The reset signal is active low. UFS devices shall detect
451 * more than or equal to 1us of positive or negative RST_n
454 * To be on safe side, keep the reset low for at least 10us.
456 usleep_range(10, 15);
458 ufs_mtk_device_reset_ctrl(1, res);
460 /* Some devices may need time to respond to rst_n */
461 usleep_range(10000, 15000);
463 dev_info(hba->dev, "device reset done\n");
466 static int ufs_mtk_link_set_hpm(struct ufs_hba *hba)
470 err = ufshcd_hba_enable(hba);
474 err = ufs_mtk_unipro_set_pm(hba, 0);
478 err = ufshcd_uic_hibern8_exit(hba);
480 ufshcd_set_link_active(hba);
484 err = ufshcd_make_hba_operational(hba);
491 static int ufs_mtk_link_set_lpm(struct ufs_hba *hba)
495 err = ufs_mtk_unipro_set_pm(hba, 1);
497 /* Resume UniPro state for following error recovery */
498 ufs_mtk_unipro_set_pm(hba, 0);
505 static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
508 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
510 if (ufshcd_is_link_hibern8(hba)) {
511 err = ufs_mtk_link_set_lpm(hba);
514 * Set link as off state enforcedly to trigger
515 * ufshcd_host_reset_and_restore() in ufshcd_suspend()
516 * for completed host reset.
518 ufshcd_set_link_off(hba);
523 if (!ufshcd_is_link_active(hba))
524 phy_power_off(host->mphy);
529 static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
531 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
534 if (!ufshcd_is_link_active(hba))
535 phy_power_on(host->mphy);
537 if (ufshcd_is_link_hibern8(hba)) {
538 err = ufs_mtk_link_set_hpm(hba);
540 err = ufshcd_link_recovery(hba);
548 static void ufs_mtk_dbg_register_dump(struct ufs_hba *hba)
550 ufshcd_dump_regs(hba, REG_UFS_REFCLK_CTRL, 0x4, "Ref-Clk Ctrl ");
552 ufshcd_dump_regs(hba, REG_UFS_EXTREG, 0x4, "Ext Reg ");
554 ufshcd_dump_regs(hba, REG_UFS_MPHYCTRL,
555 REG_UFS_REJECT_MON - REG_UFS_MPHYCTRL + 4,
558 /* Direct debugging information to REG_MTK_PROBE */
559 ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
560 ufshcd_dump_regs(hba, REG_UFS_PROBE, 0x4, "Debug Probe ");
563 static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba)
565 struct ufs_dev_info *dev_info = &hba->dev_info;
566 u16 mid = dev_info->wmanufacturerid;
568 if (mid == UFS_VENDOR_SAMSUNG)
569 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6);
572 * Decide waiting time before gating reference clock and
573 * after ungating reference clock according to vendors'
576 if (mid == UFS_VENDOR_SAMSUNG)
577 ufs_mtk_setup_ref_clk_wait_us(hba, 1, 1);
578 else if (mid == UFS_VENDOR_SKHYNIX)
579 ufs_mtk_setup_ref_clk_wait_us(hba, 30, 30);
580 else if (mid == UFS_VENDOR_TOSHIBA)
581 ufs_mtk_setup_ref_clk_wait_us(hba, 100, 32);
586 static void ufs_mtk_fixup_dev_quirks(struct ufs_hba *hba)
588 struct ufs_dev_info *dev_info = &hba->dev_info;
589 u16 mid = dev_info->wmanufacturerid;
591 ufshcd_fixup_dev_quirks(hba, ufs_mtk_dev_fixups);
593 if (mid == UFS_VENDOR_SAMSUNG)
594 hba->dev_quirks &= ~UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE;
598 * struct ufs_hba_mtk_vops - UFS MTK specific variant operations
600 * The variant operations configure the necessary controller and PHY
601 * handshake during initialization.
603 static struct ufs_hba_variant_ops ufs_hba_mtk_vops = {
604 .name = "mediatek.ufshci",
605 .init = ufs_mtk_init,
606 .setup_clocks = ufs_mtk_setup_clocks,
607 .hce_enable_notify = ufs_mtk_hce_enable_notify,
608 .link_startup_notify = ufs_mtk_link_startup_notify,
609 .pwr_change_notify = ufs_mtk_pwr_change_notify,
610 .apply_dev_quirks = ufs_mtk_apply_dev_quirks,
611 .fixup_dev_quirks = ufs_mtk_fixup_dev_quirks,
612 .suspend = ufs_mtk_suspend,
613 .resume = ufs_mtk_resume,
614 .dbg_register_dump = ufs_mtk_dbg_register_dump,
615 .device_reset = ufs_mtk_device_reset,
619 * ufs_mtk_probe - probe routine of the driver
620 * @pdev: pointer to Platform device handle
622 * Return zero for success and non-zero for failure
624 static int ufs_mtk_probe(struct platform_device *pdev)
627 struct device *dev = &pdev->dev;
629 /* perform generic probe */
630 err = ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops);
632 dev_info(dev, "probe failed %d\n", err);
638 * ufs_mtk_remove - set driver_data of the device to NULL
639 * @pdev: pointer to platform device handle
643 static int ufs_mtk_remove(struct platform_device *pdev)
645 struct ufs_hba *hba = platform_get_drvdata(pdev);
647 pm_runtime_get_sync(&(pdev)->dev);
652 static const struct of_device_id ufs_mtk_of_match[] = {
653 { .compatible = "mediatek,mt8183-ufshci"},
657 static const struct dev_pm_ops ufs_mtk_pm_ops = {
658 .suspend = ufshcd_pltfrm_suspend,
659 .resume = ufshcd_pltfrm_resume,
660 .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
661 .runtime_resume = ufshcd_pltfrm_runtime_resume,
662 .runtime_idle = ufshcd_pltfrm_runtime_idle,
665 static struct platform_driver ufs_mtk_pltform = {
666 .probe = ufs_mtk_probe,
667 .remove = ufs_mtk_remove,
668 .shutdown = ufshcd_pltfrm_shutdown,
670 .name = "ufshcd-mtk",
671 .pm = &ufs_mtk_pm_ops,
672 .of_match_table = ufs_mtk_of_match,
676 MODULE_AUTHOR("Stanley Chu <stanley.chu@mediatek.com>");
677 MODULE_AUTHOR("Peter Wang <peter.wang@mediatek.com>");
678 MODULE_DESCRIPTION("MediaTek UFS Host Driver");
679 MODULE_LICENSE("GPL v2");
681 module_platform_driver(ufs_mtk_pltform);