1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 MediaTek Inc.
5 * Stanley Chu <stanley.chu@mediatek.com>
6 * Peter Wang <peter.wang@mediatek.com>
9 #include <linux/arm-smccc.h>
10 #include <linux/bitfield.h>
12 #include <linux/of_address.h>
13 #include <linux/of_device.h>
14 #include <linux/phy/phy.h>
15 #include <linux/platform_device.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/reset.h>
18 #include <linux/soc/mediatek/mtk_sip_svc.h>
21 #include "ufshcd-crypto.h"
22 #include "ufshcd-pltfrm.h"
23 #include "ufs_quirks.h"
25 #include "ufs-mediatek.h"
27 #define CREATE_TRACE_POINTS
28 #include "ufs-mediatek-trace.h"
30 #define ufs_mtk_smc(cmd, val, res) \
31 arm_smccc_smc(MTK_SIP_UFS_CONTROL, \
32 cmd, val, 0, 0, 0, 0, 0, &(res))
34 #define ufs_mtk_va09_pwr_ctrl(res, on) \
35 ufs_mtk_smc(UFS_MTK_SIP_VA09_PWR_CTRL, on, res)
37 #define ufs_mtk_crypto_ctrl(res, enable) \
38 ufs_mtk_smc(UFS_MTK_SIP_CRYPTO_CTRL, enable, res)
40 #define ufs_mtk_ref_clk_notify(on, res) \
41 ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, on, res)
43 #define ufs_mtk_device_reset_ctrl(high, res) \
44 ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, high, res)
46 static struct ufs_dev_fix ufs_mtk_dev_fixups[] = {
47 UFS_FIX(UFS_VENDOR_MICRON, UFS_ANY_MODEL,
48 UFS_DEVICE_QUIRK_DELAY_AFTER_LPM),
49 UFS_FIX(UFS_VENDOR_SKHYNIX, "H9HQ21AFAMZDAR",
50 UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES),
54 static const struct of_device_id ufs_mtk_of_match[] = {
55 { .compatible = "mediatek,mt8183-ufshci" },
59 static bool ufs_mtk_is_boost_crypt_enabled(struct ufs_hba *hba)
61 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
63 return !!(host->caps & UFS_MTK_CAP_BOOST_CRYPT_ENGINE);
66 static bool ufs_mtk_is_va09_supported(struct ufs_hba *hba)
68 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
70 return !!(host->caps & UFS_MTK_CAP_VA09_PWR_CTRL);
73 static bool ufs_mtk_is_broken_vcc(struct ufs_hba *hba)
75 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
77 return !!(host->caps & UFS_MTK_CAP_BROKEN_VCC);
80 static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
86 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
88 (1 << RX_SYMBOL_CLK_GATE_EN) |
89 (1 << SYS_CLK_GATE_EN) |
90 (1 << TX_CLK_GATE_EN);
92 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
95 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);
96 tmp = tmp & ~(1 << TX_SYMBOL_CLK_REQ_FORCE);
98 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);
101 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
102 tmp = tmp & ~((1 << RX_SYMBOL_CLK_GATE_EN) |
103 (1 << SYS_CLK_GATE_EN) |
104 (1 << TX_CLK_GATE_EN));
106 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
109 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);
110 tmp = tmp | (1 << TX_SYMBOL_CLK_REQ_FORCE);
112 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);
116 static void ufs_mtk_crypto_enable(struct ufs_hba *hba)
118 struct arm_smccc_res res;
120 ufs_mtk_crypto_ctrl(res, 1);
122 dev_info(hba->dev, "%s: crypto enable failed, err: %lu\n",
124 hba->caps &= ~UFSHCD_CAP_CRYPTO;
128 static void ufs_mtk_host_reset(struct ufs_hba *hba)
130 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
132 reset_control_assert(host->hci_reset);
133 reset_control_assert(host->crypto_reset);
134 reset_control_assert(host->unipro_reset);
136 usleep_range(100, 110);
138 reset_control_deassert(host->unipro_reset);
139 reset_control_deassert(host->crypto_reset);
140 reset_control_deassert(host->hci_reset);
143 static void ufs_mtk_init_reset_control(struct ufs_hba *hba,
144 struct reset_control **rc,
147 *rc = devm_reset_control_get(hba->dev, str);
149 dev_info(hba->dev, "Failed to get reset control %s: %ld\n",
155 static void ufs_mtk_init_reset(struct ufs_hba *hba)
157 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
159 ufs_mtk_init_reset_control(hba, &host->hci_reset,
161 ufs_mtk_init_reset_control(hba, &host->unipro_reset,
163 ufs_mtk_init_reset_control(hba, &host->crypto_reset,
167 static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
168 enum ufs_notify_change_status status)
170 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
173 if (status == PRE_CHANGE) {
174 if (host->unipro_lpm) {
175 hba->vps->hba_enable_delay_us = 0;
177 hba->vps->hba_enable_delay_us = 600;
178 ufs_mtk_host_reset(hba);
181 if (hba->caps & UFSHCD_CAP_CRYPTO)
182 ufs_mtk_crypto_enable(hba);
184 if (host->caps & UFS_MTK_CAP_DISABLE_AH8) {
185 spin_lock_irqsave(hba->host->host_lock, flags);
186 ufshcd_writel(hba, 0,
187 REG_AUTO_HIBERNATE_IDLE_TIMER);
188 spin_unlock_irqrestore(hba->host->host_lock,
191 hba->capabilities &= ~MASK_AUTO_HIBERN8_SUPPORT;
199 static int ufs_mtk_bind_mphy(struct ufs_hba *hba)
201 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
202 struct device *dev = hba->dev;
203 struct device_node *np = dev->of_node;
206 host->mphy = devm_of_phy_get_by_index(dev, np, 0);
208 if (host->mphy == ERR_PTR(-EPROBE_DEFER)) {
210 * UFS driver might be probed before the phy driver does.
211 * In that case we would like to return EPROBE_DEFER code.
215 "%s: required phy hasn't probed yet. err = %d\n",
217 } else if (IS_ERR(host->mphy)) {
218 err = PTR_ERR(host->mphy);
219 if (err != -ENODEV) {
220 dev_info(dev, "%s: PHY get failed %d\n", __func__,
228 * Allow unbound mphy because not every platform needs specific
237 static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on)
239 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
240 struct arm_smccc_res res;
241 ktime_t timeout, time_checked;
244 if (host->ref_clk_enabled == on)
248 ufs_mtk_ref_clk_notify(on, res);
249 ufshcd_delay_us(host->ref_clk_ungating_wait_us, 10);
250 ufshcd_writel(hba, REFCLK_REQUEST, REG_UFS_REFCLK_CTRL);
252 ufshcd_writel(hba, REFCLK_RELEASE, REG_UFS_REFCLK_CTRL);
256 timeout = ktime_add_us(ktime_get(), REFCLK_REQ_TIMEOUT_US);
258 time_checked = ktime_get();
259 value = ufshcd_readl(hba, REG_UFS_REFCLK_CTRL);
261 /* Wait until ack bit equals to req bit */
262 if (((value & REFCLK_ACK) >> 1) == (value & REFCLK_REQUEST))
265 usleep_range(100, 200);
266 } while (ktime_before(time_checked, timeout));
268 dev_err(hba->dev, "missing ack of refclk req, reg: 0x%x\n", value);
270 ufs_mtk_ref_clk_notify(host->ref_clk_enabled, res);
275 host->ref_clk_enabled = on;
277 ufshcd_delay_us(host->ref_clk_gating_wait_us, 10);
278 ufs_mtk_ref_clk_notify(on, res);
284 static void ufs_mtk_setup_ref_clk_wait_us(struct ufs_hba *hba,
285 u16 gating_us, u16 ungating_us)
287 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
289 if (hba->dev_info.clk_gating_wait_us) {
290 host->ref_clk_gating_wait_us =
291 hba->dev_info.clk_gating_wait_us;
293 host->ref_clk_gating_wait_us = gating_us;
296 host->ref_clk_ungating_wait_us = ungating_us;
299 static int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state,
300 unsigned long max_wait_ms)
302 ktime_t timeout, time_checked;
305 timeout = ktime_add_ms(ktime_get(), max_wait_ms);
307 time_checked = ktime_get();
308 ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
309 val = ufshcd_readl(hba, REG_UFS_PROBE);
315 /* Sleep for max. 200us */
316 usleep_range(100, 200);
317 } while (ktime_before(time_checked, timeout));
325 static int ufs_mtk_mphy_power_on(struct ufs_hba *hba, bool on)
327 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
328 struct phy *mphy = host->mphy;
329 struct arm_smccc_res res;
332 if (!mphy || !(on ^ host->mphy_powered_on))
336 if (ufs_mtk_is_va09_supported(hba)) {
337 ret = regulator_enable(host->reg_va09);
340 /* wait 200 us to stablize VA09 */
341 usleep_range(200, 210);
342 ufs_mtk_va09_pwr_ctrl(res, 1);
347 if (ufs_mtk_is_va09_supported(hba)) {
348 ufs_mtk_va09_pwr_ctrl(res, 0);
349 ret = regulator_disable(host->reg_va09);
357 "failed to %s va09: %d\n",
358 on ? "enable" : "disable",
361 host->mphy_powered_on = on;
367 static int ufs_mtk_get_host_clk(struct device *dev, const char *name,
368 struct clk **clk_out)
373 clk = devm_clk_get(dev, name);
382 static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
384 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
385 struct ufs_mtk_crypt_cfg *cfg;
386 struct regulator *reg;
389 if (!ufs_mtk_is_boost_crypt_enabled(hba))
393 volt = cfg->vcore_volt;
394 reg = cfg->reg_vcore;
396 ret = clk_prepare_enable(cfg->clk_crypt_mux);
398 dev_info(hba->dev, "clk_prepare_enable(): %d\n",
404 ret = regulator_set_voltage(reg, volt, INT_MAX);
407 "failed to set vcore to %d\n", volt);
411 ret = clk_set_parent(cfg->clk_crypt_mux,
412 cfg->clk_crypt_perf);
415 "failed to set clk_crypt_perf\n");
416 regulator_set_voltage(reg, 0, INT_MAX);
420 ret = clk_set_parent(cfg->clk_crypt_mux,
424 "failed to set clk_crypt_lp\n");
428 ret = regulator_set_voltage(reg, 0, INT_MAX);
431 "failed to set vcore to MIN\n");
435 clk_disable_unprepare(cfg->clk_crypt_mux);
438 static int ufs_mtk_init_host_clk(struct ufs_hba *hba, const char *name,
443 ret = ufs_mtk_get_host_clk(hba->dev, name, clk);
445 dev_info(hba->dev, "%s: failed to get %s: %d", __func__,
452 static void ufs_mtk_init_boost_crypt(struct ufs_hba *hba)
454 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
455 struct ufs_mtk_crypt_cfg *cfg;
456 struct device *dev = hba->dev;
457 struct regulator *reg;
460 host->crypt = devm_kzalloc(dev, sizeof(*(host->crypt)),
465 reg = devm_regulator_get_optional(dev, "dvfsrc-vcore");
467 dev_info(dev, "failed to get dvfsrc-vcore: %ld",
472 if (of_property_read_u32(dev->of_node, "boost-crypt-vcore-min",
474 dev_info(dev, "failed to get boost-crypt-vcore-min");
479 if (ufs_mtk_init_host_clk(hba, "crypt_mux",
480 &cfg->clk_crypt_mux))
483 if (ufs_mtk_init_host_clk(hba, "crypt_lp",
487 if (ufs_mtk_init_host_clk(hba, "crypt_perf",
488 &cfg->clk_crypt_perf))
491 cfg->reg_vcore = reg;
492 cfg->vcore_volt = volt;
493 host->caps |= UFS_MTK_CAP_BOOST_CRYPT_ENGINE;
499 static void ufs_mtk_init_va09_pwr_ctrl(struct ufs_hba *hba)
501 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
503 host->reg_va09 = regulator_get(hba->dev, "va09");
505 dev_info(hba->dev, "failed to get va09");
507 host->caps |= UFS_MTK_CAP_VA09_PWR_CTRL;
510 static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
512 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
513 struct device_node *np = hba->dev->of_node;
515 if (of_property_read_bool(np, "mediatek,ufs-boost-crypt"))
516 ufs_mtk_init_boost_crypt(hba);
518 if (of_property_read_bool(np, "mediatek,ufs-support-va09"))
519 ufs_mtk_init_va09_pwr_ctrl(hba);
521 if (of_property_read_bool(np, "mediatek,ufs-disable-ah8"))
522 host->caps |= UFS_MTK_CAP_DISABLE_AH8;
524 if (of_property_read_bool(np, "mediatek,ufs-broken-vcc"))
525 host->caps |= UFS_MTK_CAP_BROKEN_VCC;
527 dev_info(hba->dev, "caps: 0x%x", host->caps);
530 static void ufs_mtk_scale_perf(struct ufs_hba *hba, bool up)
532 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
534 ufs_mtk_boost_crypt(hba, up);
535 ufs_mtk_setup_ref_clk(hba, up);
538 phy_power_on(host->mphy);
540 phy_power_off(host->mphy);
544 * ufs_mtk_setup_clocks - enables/disable clocks
545 * @hba: host controller instance
546 * @on: If true, enable clocks else disable them.
547 * @status: PRE_CHANGE or POST_CHANGE notify
549 * Returns 0 on success, non-zero on failure.
551 static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on,
552 enum ufs_notify_change_status status)
554 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
555 bool clk_pwr_off = false;
559 * In case ufs_mtk_init() is not yet done, simply ignore.
560 * This ufs_mtk_setup_clocks() shall be called from
561 * ufs_mtk_init() after init is done.
566 if (!on && status == PRE_CHANGE) {
567 if (ufshcd_is_link_off(hba)) {
569 } else if (ufshcd_is_link_hibern8(hba) ||
570 (!ufshcd_can_hibern8_during_gating(hba) &&
571 ufshcd_is_auto_hibern8_enabled(hba))) {
573 * Gate ref-clk and poweroff mphy if link state is in
574 * OFF or Hibern8 by either Auto-Hibern8 or
575 * ufshcd_link_state_transition().
577 ret = ufs_mtk_wait_link_state(hba,
585 ufs_mtk_scale_perf(hba, false);
586 } else if (on && status == POST_CHANGE) {
587 ufs_mtk_scale_perf(hba, true);
593 static void ufs_mtk_get_controller_version(struct ufs_hba *hba)
595 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
598 if (host->hw_ver.major)
601 /* Set default (minimum) version anyway */
602 host->hw_ver.major = 2;
604 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_LOCALVERINFO), &ver);
606 if (ver >= UFS_UNIPRO_VER_1_8)
607 host->hw_ver.major = 3;
612 * ufs_mtk_init - find other essential mmio bases
613 * @hba: host controller instance
615 * Binds PHY with controller and powers up PHY enabling clocks
618 * Returns -EPROBE_DEFER if binding fails, returns negative error
619 * on phy power up failure and returns zero on success.
621 static int ufs_mtk_init(struct ufs_hba *hba)
623 const struct of_device_id *id;
624 struct device *dev = hba->dev;
625 struct ufs_mtk_host *host;
628 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
631 dev_info(dev, "%s: no memory for mtk ufs host\n", __func__);
636 ufshcd_set_variant(hba, host);
638 id = of_match_device(ufs_mtk_of_match, dev);
644 /* Initialize host capability */
645 ufs_mtk_init_host_caps(hba);
647 err = ufs_mtk_bind_mphy(hba);
649 goto out_variant_clear;
651 ufs_mtk_init_reset(hba);
653 /* Enable runtime autosuspend */
654 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
656 /* Enable clock-gating */
657 hba->caps |= UFSHCD_CAP_CLK_GATING;
659 /* Enable inline encryption */
660 hba->caps |= UFSHCD_CAP_CRYPTO;
662 /* Enable WriteBooster */
663 hba->caps |= UFSHCD_CAP_WB_EN;
664 hba->quirks |= UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL;
665 hba->vps->wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(80);
667 if (host->caps & UFS_MTK_CAP_DISABLE_AH8)
668 hba->caps |= UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
671 * ufshcd_vops_init() is invoked after
672 * ufshcd_setup_clock(true) in ufshcd_hba_init() thus
673 * phy clock setup is skipped.
675 * Enable phy clocks specifically here.
677 ufs_mtk_mphy_power_on(hba, true);
678 ufs_mtk_setup_clocks(hba, true, POST_CHANGE);
683 ufshcd_set_variant(hba, NULL);
688 static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
689 struct ufs_pa_layer_attr *dev_max_params,
690 struct ufs_pa_layer_attr *dev_req_params)
692 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
693 struct ufs_dev_params host_cap;
696 ufshcd_init_pwr_dev_param(&host_cap);
697 host_cap.hs_rx_gear = UFS_HS_G4;
698 host_cap.hs_tx_gear = UFS_HS_G4;
700 ret = ufshcd_get_pwr_dev_param(&host_cap,
704 pr_info("%s: failed to determine capabilities\n",
708 if (host->hw_ver.major >= 3) {
709 ret = ufshcd_dme_configure_adapt(hba,
710 dev_req_params->gear_tx,
717 static int ufs_mtk_pwr_change_notify(struct ufs_hba *hba,
718 enum ufs_notify_change_status stage,
719 struct ufs_pa_layer_attr *dev_max_params,
720 struct ufs_pa_layer_attr *dev_req_params)
726 ret = ufs_mtk_pre_pwr_change(hba, dev_max_params,
739 static int ufs_mtk_unipro_set_lpm(struct ufs_hba *hba, bool lpm)
742 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
744 ret = ufshcd_dme_set(hba,
745 UIC_ARG_MIB_SEL(VS_UNIPROPOWERDOWNCONTROL, 0),
749 * Forcibly set as non-LPM mode if UIC commands is failed
750 * to use default hba_enable_delay_us value for re-enabling
753 host->unipro_lpm = lpm;
759 static int ufs_mtk_pre_link(struct ufs_hba *hba)
764 ufs_mtk_get_controller_version(hba);
766 ret = ufs_mtk_unipro_set_lpm(hba, false);
771 * Setting PA_Local_TX_LCC_Enable to 0 before link startup
772 * to make sure that both host and device TX LCC are disabled
773 * once link startup is completed.
775 ret = ufshcd_disable_host_tx_lcc(hba);
779 /* disable deep stall */
780 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
786 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
791 static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
796 if (ufshcd_is_clkgating_allowed(hba)) {
797 if (ufshcd_is_auto_hibern8_supported(hba) && hba->ahit)
798 ah_ms = FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK,
802 spin_lock_irqsave(hba->host->host_lock, flags);
803 hba->clk_gating.delay_ms = ah_ms + 5;
804 spin_unlock_irqrestore(hba->host->host_lock, flags);
808 static int ufs_mtk_post_link(struct ufs_hba *hba)
810 /* enable unipro clock gating feature */
811 ufs_mtk_cfg_unipro_cg(hba, true);
813 /* configure auto-hibern8 timer to 10ms */
814 if (ufshcd_is_auto_hibern8_supported(hba)) {
815 ufshcd_auto_hibern8_update(hba,
816 FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 10) |
817 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3));
820 ufs_mtk_setup_clk_gating(hba);
825 static int ufs_mtk_link_startup_notify(struct ufs_hba *hba,
826 enum ufs_notify_change_status stage)
832 ret = ufs_mtk_pre_link(hba);
835 ret = ufs_mtk_post_link(hba);
845 static int ufs_mtk_device_reset(struct ufs_hba *hba)
847 struct arm_smccc_res res;
849 ufs_mtk_device_reset_ctrl(0, res);
852 * The reset signal is active low. UFS devices shall detect
853 * more than or equal to 1us of positive or negative RST_n
856 * To be on safe side, keep the reset low for at least 10us.
858 usleep_range(10, 15);
860 ufs_mtk_device_reset_ctrl(1, res);
862 /* Some devices may need time to respond to rst_n */
863 usleep_range(10000, 15000);
865 dev_info(hba->dev, "device reset done\n");
870 static int ufs_mtk_link_set_hpm(struct ufs_hba *hba)
874 err = ufshcd_hba_enable(hba);
878 err = ufs_mtk_unipro_set_lpm(hba, false);
882 err = ufshcd_uic_hibern8_exit(hba);
884 ufshcd_set_link_active(hba);
888 err = ufshcd_make_hba_operational(hba);
895 static int ufs_mtk_link_set_lpm(struct ufs_hba *hba)
899 err = ufs_mtk_unipro_set_lpm(hba, true);
901 /* Resume UniPro state for following error recovery */
902 ufs_mtk_unipro_set_lpm(hba, false);
909 static void ufs_mtk_vreg_set_lpm(struct ufs_hba *hba, bool lpm)
911 if (!hba->vreg_info.vccq2 || !hba->vreg_info.vcc)
914 if (lpm && !hba->vreg_info.vcc->enabled)
915 regulator_set_mode(hba->vreg_info.vccq2->reg,
916 REGULATOR_MODE_IDLE);
918 regulator_set_mode(hba->vreg_info.vccq2->reg,
919 REGULATOR_MODE_NORMAL);
922 static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
926 if (ufshcd_is_link_hibern8(hba)) {
927 err = ufs_mtk_link_set_lpm(hba);
932 if (!ufshcd_is_link_active(hba)) {
934 * Make sure no error will be returned to prevent
935 * ufshcd_suspend() re-enabling regulators while vreg is still
938 ufs_mtk_vreg_set_lpm(hba, true);
939 err = ufs_mtk_mphy_power_on(hba, false);
947 * Set link as off state enforcedly to trigger
948 * ufshcd_host_reset_and_restore() in ufshcd_suspend()
949 * for completed host reset.
951 ufshcd_set_link_off(hba);
955 static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
959 err = ufs_mtk_mphy_power_on(hba, true);
963 ufs_mtk_vreg_set_lpm(hba, false);
965 if (ufshcd_is_link_hibern8(hba)) {
966 err = ufs_mtk_link_set_hpm(hba);
973 return ufshcd_link_recovery(hba);
976 static void ufs_mtk_dbg_register_dump(struct ufs_hba *hba)
978 ufshcd_dump_regs(hba, REG_UFS_REFCLK_CTRL, 0x4, "Ref-Clk Ctrl ");
980 ufshcd_dump_regs(hba, REG_UFS_EXTREG, 0x4, "Ext Reg ");
982 ufshcd_dump_regs(hba, REG_UFS_MPHYCTRL,
983 REG_UFS_REJECT_MON - REG_UFS_MPHYCTRL + 4,
986 /* Direct debugging information to REG_MTK_PROBE */
987 ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
988 ufshcd_dump_regs(hba, REG_UFS_PROBE, 0x4, "Debug Probe ");
991 static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba)
993 struct ufs_dev_info *dev_info = &hba->dev_info;
994 u16 mid = dev_info->wmanufacturerid;
996 if (mid == UFS_VENDOR_SAMSUNG)
997 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6);
1000 * Decide waiting time before gating reference clock and
1001 * after ungating reference clock according to vendors'
1004 if (mid == UFS_VENDOR_SAMSUNG)
1005 ufs_mtk_setup_ref_clk_wait_us(hba, 1, 1);
1006 else if (mid == UFS_VENDOR_SKHYNIX)
1007 ufs_mtk_setup_ref_clk_wait_us(hba, 30, 30);
1008 else if (mid == UFS_VENDOR_TOSHIBA)
1009 ufs_mtk_setup_ref_clk_wait_us(hba, 100, 32);
1014 static void ufs_mtk_fixup_dev_quirks(struct ufs_hba *hba)
1016 ufshcd_fixup_dev_quirks(hba, ufs_mtk_dev_fixups);
1018 if (ufs_mtk_is_broken_vcc(hba) && hba->vreg_info.vcc &&
1019 (hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)) {
1020 hba->vreg_info.vcc->always_on = true;
1022 * VCC will be kept always-on thus we don't
1023 * need any delay during regulator operations
1025 hba->dev_quirks &= ~(UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
1026 UFS_DEVICE_QUIRK_DELAY_AFTER_LPM);
1030 static void ufs_mtk_event_notify(struct ufs_hba *hba,
1031 enum ufs_event_type evt, void *data)
1033 unsigned int val = *(u32 *)data;
1035 trace_ufs_mtk_event(evt, val);
1039 * struct ufs_hba_mtk_vops - UFS MTK specific variant operations
1041 * The variant operations configure the necessary controller and PHY
1042 * handshake during initialization.
1044 static const struct ufs_hba_variant_ops ufs_hba_mtk_vops = {
1045 .name = "mediatek.ufshci",
1046 .init = ufs_mtk_init,
1047 .setup_clocks = ufs_mtk_setup_clocks,
1048 .hce_enable_notify = ufs_mtk_hce_enable_notify,
1049 .link_startup_notify = ufs_mtk_link_startup_notify,
1050 .pwr_change_notify = ufs_mtk_pwr_change_notify,
1051 .apply_dev_quirks = ufs_mtk_apply_dev_quirks,
1052 .fixup_dev_quirks = ufs_mtk_fixup_dev_quirks,
1053 .suspend = ufs_mtk_suspend,
1054 .resume = ufs_mtk_resume,
1055 .dbg_register_dump = ufs_mtk_dbg_register_dump,
1056 .device_reset = ufs_mtk_device_reset,
1057 .event_notify = ufs_mtk_event_notify,
1061 * ufs_mtk_probe - probe routine of the driver
1062 * @pdev: pointer to Platform device handle
1064 * Return zero for success and non-zero for failure
1066 static int ufs_mtk_probe(struct platform_device *pdev)
1069 struct device *dev = &pdev->dev;
1071 /* perform generic probe */
1072 err = ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops);
1074 dev_info(dev, "probe failed %d\n", err);
1080 * ufs_mtk_remove - set driver_data of the device to NULL
1081 * @pdev: pointer to platform device handle
1085 static int ufs_mtk_remove(struct platform_device *pdev)
1087 struct ufs_hba *hba = platform_get_drvdata(pdev);
1089 pm_runtime_get_sync(&(pdev)->dev);
1094 static const struct dev_pm_ops ufs_mtk_pm_ops = {
1095 .suspend = ufshcd_pltfrm_suspend,
1096 .resume = ufshcd_pltfrm_resume,
1097 .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
1098 .runtime_resume = ufshcd_pltfrm_runtime_resume,
1099 .runtime_idle = ufshcd_pltfrm_runtime_idle,
1102 static struct platform_driver ufs_mtk_pltform = {
1103 .probe = ufs_mtk_probe,
1104 .remove = ufs_mtk_remove,
1105 .shutdown = ufshcd_pltfrm_shutdown,
1107 .name = "ufshcd-mtk",
1108 .pm = &ufs_mtk_pm_ops,
1109 .of_match_table = ufs_mtk_of_match,
1113 MODULE_AUTHOR("Stanley Chu <stanley.chu@mediatek.com>");
1114 MODULE_AUTHOR("Peter Wang <peter.wang@mediatek.com>");
1115 MODULE_DESCRIPTION("MediaTek UFS Host Driver");
1116 MODULE_LICENSE("GPL v2");
1118 module_platform_driver(ufs_mtk_pltform);