2 * HiSilicon Hixxxx UFS Driver
4 * Copyright (c) 2016-2017 Linaro Ltd.
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
7 * Released under the GPLv2 only.
8 * SPDX-License-Identifier: GPL-2.0
11 #include <linux/time.h>
13 #include <linux/of_address.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset.h>
19 #include "ufshcd-pltfrm.h"
23 #include "ufs_quirks.h"
25 static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
30 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
33 err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0),
35 err |= ufshcd_dme_get(hba,
36 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1);
37 if (err || (tx_fsm_val_0 == TX_FSM_HIBERN8 &&
38 tx_fsm_val_1 == TX_FSM_HIBERN8))
41 /* sleep for max. 200us */
42 usleep_range(100, 200);
43 } while (time_before(jiffies, timeout));
46 * we might have scheduled out for long during polling so
47 * check the state again.
49 if (time_after(jiffies, timeout)) {
50 err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0),
52 err |= ufshcd_dme_get(hba,
53 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1);
57 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
59 } else if (tx_fsm_val_0 != TX_FSM_HIBERN8 ||
60 tx_fsm_val_1 != TX_FSM_HIBERN8) {
62 dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n",
63 __func__, tx_fsm_val_0, tx_fsm_val_1);
69 static void ufs_hisi_clk_init(struct ufs_hba *hba)
71 struct ufs_hisi_host *host = ufshcd_get_variant(hba);
73 ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
74 if (ufs_sys_ctrl_readl(host, PHY_CLK_CTRL) & BIT_SYSCTRL_REF_CLOCK_EN)
77 ufs_sys_ctrl_clr_bits(host, BIT_UFS_REFCLK_SRC_SEl, UFS_SYSCTRL);
78 ufs_sys_ctrl_clr_bits(host, BIT_UFS_REFCLK_ISO_EN, PHY_ISO_EN);
79 /* open mphy ref clk */
80 ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
83 static void ufs_hisi_soc_init(struct ufs_hba *hba)
85 struct ufs_hisi_host *host = ufshcd_get_variant(hba);
88 if (!IS_ERR(host->rst))
89 reset_control_assert(host->rst);
92 ufs_sys_ctrl_set_bits(host, BIT_UFS_PSW_MTCMOS_EN, PSW_POWER_CTRL);
94 /* notify PWR ready */
95 ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_PWR_READY, HC_LP_CTRL);
96 ufs_sys_ctrl_writel(host, MASK_UFS_DEVICE_RESET | 0,
97 UFS_DEVICE_RESET_CTRL);
99 reg = ufs_sys_ctrl_readl(host, PHY_CLK_CTRL);
100 reg = (reg & ~MASK_SYSCTRL_CFG_CLOCK_FREQ) | UFS_FREQ_CFG_CLK;
101 /* set cfg clk freq */
102 ufs_sys_ctrl_writel(host, reg, PHY_CLK_CTRL);
103 /* set ref clk freq */
104 ufs_sys_ctrl_clr_bits(host, MASK_SYSCTRL_REF_CLOCK_SEL, PHY_CLK_CTRL);
105 /* bypass ufs clk gate */
106 ufs_sys_ctrl_set_bits(host, MASK_UFS_CLK_GATE_BYPASS,
108 ufs_sys_ctrl_set_bits(host, MASK_UFS_SYSCRTL_BYPASS, UFS_SYSCTRL);
111 ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_PSW_CLK_EN, PSW_CLK_CTRL);
112 /* disable ufshc iso */
113 ufs_sys_ctrl_clr_bits(host, BIT_UFS_PSW_ISO_CTRL, PSW_POWER_CTRL);
114 /* disable phy iso */
115 ufs_sys_ctrl_clr_bits(host, BIT_UFS_PHY_ISO_CTRL, PHY_ISO_EN);
116 /* notice iso disable */
117 ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_LP_ISOL_EN, HC_LP_CTRL);
119 /* disable lp_reset_n */
120 ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_LP_RESET_N, RESET_CTRL_EN);
123 ufs_sys_ctrl_writel(host, MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET,
124 UFS_DEVICE_RESET_CTRL);
129 * enable the fix of linereset recovery,
130 * and enable rx_reset/tx_rest beat
131 * enable ref_clk_en override(bit5) &
132 * override value = 1(bit4), with mask
134 ufs_sys_ctrl_writel(host, 0x03300330, UFS_DEVICE_RESET_CTRL);
136 if (!IS_ERR(host->rst))
137 reset_control_deassert(host->rst);
140 static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
142 struct ufs_hisi_host *host = ufshcd_get_variant(hba);
147 /* Unipro VS_mphy_disable */
148 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x1);
150 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x156A, 0x0), 0x2);
152 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8114, 0x0), 0x1);
153 /* MPHY CBOVRCTRL2 */
154 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8121, 0x0), 0x2D);
155 /* MPHY CBOVRCTRL3 */
156 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8122, 0x0), 0x1);
158 if (host->caps & UFS_HISI_CAP_PHY10nm) {
159 /* MPHY CBOVRCTRL4 */
160 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8127, 0x0), 0x98);
161 /* MPHY CBOVRCTRL5 */
162 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8128, 0x0), 0x1);
165 /* Unipro VS_MphyCfgUpdt */
166 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
167 /* MPHY RXOVRCTRL4 rx0 */
168 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x4), 0x58);
169 /* MPHY RXOVRCTRL4 rx1 */
170 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800D, 0x5), 0x58);
171 /* MPHY RXOVRCTRL5 rx0 */
172 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x4), 0xB);
173 /* MPHY RXOVRCTRL5 rx1 */
174 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800E, 0x5), 0xB);
175 /* MPHY RXSQCONTROL rx0 */
176 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x4), 0x1);
177 /* MPHY RXSQCONTROL rx1 */
178 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x5), 0x1);
179 /* Unipro VS_MphyCfgUpdt */
180 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
182 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8113, 0x0), 0x1);
183 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
185 if (host->caps & UFS_HISI_CAP_PHY10nm) {
186 /* RX_Hibern8Time_Capability*/
187 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, 0x4), 0xA);
188 /* RX_Hibern8Time_Capability*/
189 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, 0x5), 0xA);
190 /* RX_Min_ActivateTime */
191 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x4), 0xA);
192 /* RX_Min_ActivateTime*/
193 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x5), 0xA);
196 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x4), 0x7);
198 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x5), 0x7);
201 /* Gear3 Synclength */
202 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x4), 0x4F);
203 /* Gear3 Synclength */
204 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x5), 0x4F);
205 /* Gear2 Synclength */
206 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0094, 0x4), 0x4F);
207 /* Gear2 Synclength */
208 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0094, 0x5), 0x4F);
209 /* Gear1 Synclength */
210 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008B, 0x4), 0x4F);
211 /* Gear1 Synclength */
212 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008B, 0x5), 0x4F);
214 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, 0x0), 0x5);
216 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x000F, 0x1), 0x5);
218 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
219 /* Unipro VS_mphy_disable */
220 ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), &value);
223 "Warring!!! Unipro VS_mphy_disable is 0x%x\n", value);
225 /* Unipro VS_mphy_disable */
226 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x0);
227 err = ufs_hisi_check_hibern8(hba);
229 dev_err(hba->dev, "ufs_hisi_check_hibern8 error\n");
231 if (!(host->caps & UFS_HISI_CAP_PHY10nm))
232 ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV);
234 /* disable auto H8 */
235 reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER);
236 reg = reg & (~UFS_AHIT_AH8ITV_MASK);
237 ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER);
239 /* Unipro PA_Local_TX_LCC_Enable */
240 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x155E, 0x0), 0x0);
241 /* close Unipro VS_Mk2ExtnSupport */
242 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), 0x0);
243 ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xD0AB, 0x0), &value);
245 /* Ensure close success */
246 dev_info(hba->dev, "WARN: close VS_Mk2ExtnSupport failed\n");
252 static int ufs_hisi_link_startup_post_change(struct ufs_hba *hba)
254 struct ufs_hisi_host *host = ufshcd_get_variant(hba);
256 /* Unipro DL_AFC0CreditThreshold */
257 ufshcd_dme_set(hba, UIC_ARG_MIB(0x2044), 0x0);
258 /* Unipro DL_TC0OutAckThreshold */
259 ufshcd_dme_set(hba, UIC_ARG_MIB(0x2045), 0x0);
260 /* Unipro DL_TC0TXFCThreshold */
261 ufshcd_dme_set(hba, UIC_ARG_MIB(0x2040), 0x9);
263 /* not bypass ufs clk gate */
264 ufs_sys_ctrl_clr_bits(host, MASK_UFS_CLK_GATE_BYPASS,
266 ufs_sys_ctrl_clr_bits(host, MASK_UFS_SYSCRTL_BYPASS,
269 /* select received symbol cnt */
270 ufshcd_dme_set(hba, UIC_ARG_MIB(0xd09a), 0x80000000);
271 /* reset counter0 and enable */
272 ufshcd_dme_set(hba, UIC_ARG_MIB(0xd09c), 0x00000005);
277 static int ufs_hisi_link_startup_notify(struct ufs_hba *hba,
278 enum ufs_notify_change_status status)
284 err = ufs_hisi_link_startup_pre_change(hba);
287 err = ufs_hisi_link_startup_post_change(hba);
296 static void ufs_hisi_set_dev_cap(struct ufs_dev_params *hisi_param)
298 hisi_param->rx_lanes = UFS_HISI_LIMIT_NUM_LANES_RX;
299 hisi_param->tx_lanes = UFS_HISI_LIMIT_NUM_LANES_TX;
300 hisi_param->hs_rx_gear = UFS_HISI_LIMIT_HSGEAR_RX;
301 hisi_param->hs_tx_gear = UFS_HISI_LIMIT_HSGEAR_TX;
302 hisi_param->pwm_rx_gear = UFS_HISI_LIMIT_PWMGEAR_RX;
303 hisi_param->pwm_tx_gear = UFS_HISI_LIMIT_PWMGEAR_TX;
304 hisi_param->rx_pwr_pwm = UFS_HISI_LIMIT_RX_PWR_PWM;
305 hisi_param->tx_pwr_pwm = UFS_HISI_LIMIT_TX_PWR_PWM;
306 hisi_param->rx_pwr_hs = UFS_HISI_LIMIT_RX_PWR_HS;
307 hisi_param->tx_pwr_hs = UFS_HISI_LIMIT_TX_PWR_HS;
308 hisi_param->hs_rate = UFS_HISI_LIMIT_HS_RATE;
309 hisi_param->desired_working_mode = UFS_HISI_LIMIT_DESIRED_MODE;
312 static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba)
314 struct ufs_hisi_host *host = ufshcd_get_variant(hba);
316 if (host->caps & UFS_HISI_CAP_PHY10nm) {
318 * Boston platform need to set SaveConfigTime to 0x13,
319 * and change sync length to maximum value
321 /* VS_DebugSaveConfigTime */
322 ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0xD0A0), 0x13);
324 ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1552), 0x4f);
326 ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1554), 0x4f);
328 ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1556), 0x4f);
330 ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a7), 0xA);
332 ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a8), 0xA);
333 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd085, 0x0), 0x01);
336 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME) {
337 pr_info("ufs flash device must set VS_DebugSaveConfigTime 0x10\n");
338 /* VS_DebugSaveConfigTime */
339 ufshcd_dme_set(hba, UIC_ARG_MIB(0xD0A0), 0x10);
341 ufshcd_dme_set(hba, UIC_ARG_MIB(0x1556), 0x48);
345 ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A8), 0x1);
347 ufshcd_dme_set(hba, UIC_ARG_MIB(0x155c), 0x0);
348 /*PA_PWRModeUserData0 = 8191, default is 0*/
349 ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b0), 8191);
350 /*PA_PWRModeUserData1 = 65535, default is 0*/
351 ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b1), 65535);
352 /*PA_PWRModeUserData2 = 32767, default is 0*/
353 ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b2), 32767);
354 /*DME_FC0ProtectionTimeOutVal = 8191, default is 0*/
355 ufshcd_dme_set(hba, UIC_ARG_MIB(0xd041), 8191);
356 /*DME_TC0ReplayTimeOutVal = 65535, default is 0*/
357 ufshcd_dme_set(hba, UIC_ARG_MIB(0xd042), 65535);
358 /*DME_AFC0ReqTimeOutVal = 32767, default is 0*/
359 ufshcd_dme_set(hba, UIC_ARG_MIB(0xd043), 32767);
360 /*PA_PWRModeUserData3 = 8191, default is 0*/
361 ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b3), 8191);
362 /*PA_PWRModeUserData4 = 65535, default is 0*/
363 ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b4), 65535);
364 /*PA_PWRModeUserData5 = 32767, default is 0*/
365 ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b5), 32767);
366 /*DME_FC1ProtectionTimeOutVal = 8191, default is 0*/
367 ufshcd_dme_set(hba, UIC_ARG_MIB(0xd044), 8191);
368 /*DME_TC1ReplayTimeOutVal = 65535, default is 0*/
369 ufshcd_dme_set(hba, UIC_ARG_MIB(0xd045), 65535);
370 /*DME_AFC1ReqTimeOutVal = 32767, default is 0*/
371 ufshcd_dme_set(hba, UIC_ARG_MIB(0xd046), 32767);
374 static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba,
375 enum ufs_notify_change_status status,
376 struct ufs_pa_layer_attr *dev_max_params,
377 struct ufs_pa_layer_attr *dev_req_params)
379 struct ufs_dev_params ufs_hisi_cap;
382 if (!dev_req_params) {
384 "%s: incoming dev_req_params is NULL\n", __func__);
391 ufs_hisi_set_dev_cap(&ufs_hisi_cap);
392 ret = ufshcd_get_pwr_dev_param(&ufs_hisi_cap,
393 dev_max_params, dev_req_params);
396 "%s: failed to determine capabilities\n", __func__);
400 ufs_hisi_pwr_change_pre_change(hba);
412 static int ufs_hisi_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
414 struct ufs_hisi_host *host = ufshcd_get_variant(hba);
416 if (ufshcd_is_runtime_pm(pm_op))
419 if (host->in_suspend) {
424 ufs_sys_ctrl_clr_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
426 /* set ref_dig_clk override of PHY PCS to 0 */
427 ufs_sys_ctrl_writel(host, 0x00100000, UFS_DEVICE_RESET_CTRL);
429 host->in_suspend = true;
434 static int ufs_hisi_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
436 struct ufs_hisi_host *host = ufshcd_get_variant(hba);
438 if (!host->in_suspend)
441 /* set ref_dig_clk override of PHY PCS to 1 */
442 ufs_sys_ctrl_writel(host, 0x00100010, UFS_DEVICE_RESET_CTRL);
444 ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
446 host->in_suspend = false;
450 static int ufs_hisi_get_resource(struct ufs_hisi_host *host)
452 struct resource *mem_res;
453 struct device *dev = host->hba->dev;
454 struct platform_device *pdev = to_platform_device(dev);
456 /* get resource of ufs sys ctrl */
457 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
458 host->ufs_sys_ctrl = devm_ioremap_resource(dev, mem_res);
459 if (IS_ERR(host->ufs_sys_ctrl))
460 return PTR_ERR(host->ufs_sys_ctrl);
465 static void ufs_hisi_set_pm_lvl(struct ufs_hba *hba)
467 hba->rpm_lvl = UFS_PM_LVL_1;
468 hba->spm_lvl = UFS_PM_LVL_3;
472 * ufs_hisi_init_common
473 * @hba: host controller instance
475 static int ufs_hisi_init_common(struct ufs_hba *hba)
478 struct device *dev = hba->dev;
479 struct ufs_hisi_host *host;
481 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
486 ufshcd_set_variant(hba, host);
488 host->rst = devm_reset_control_get(dev, "rst");
489 if (IS_ERR(host->rst)) {
490 dev_err(dev, "%s: failed to get reset control\n", __func__);
491 return PTR_ERR(host->rst);
494 ufs_hisi_set_pm_lvl(hba);
496 err = ufs_hisi_get_resource(host);
498 ufshcd_set_variant(hba, NULL);
505 static int ufs_hi3660_init(struct ufs_hba *hba)
508 struct device *dev = hba->dev;
510 ret = ufs_hisi_init_common(hba);
512 dev_err(dev, "%s: ufs common init fail\n", __func__);
516 ufs_hisi_clk_init(hba);
518 ufs_hisi_soc_init(hba);
523 static int ufs_hi3670_init(struct ufs_hba *hba)
526 struct device *dev = hba->dev;
527 struct ufs_hisi_host *host;
529 ret = ufs_hisi_init_common(hba);
531 dev_err(dev, "%s: ufs common init fail\n", __func__);
535 ufs_hisi_clk_init(hba);
537 ufs_hisi_soc_init(hba);
539 /* Add cap for 10nm PHY variant on HI3670 SoC */
540 host = ufshcd_get_variant(hba);
541 host->caps |= UFS_HISI_CAP_PHY10nm;
546 static const struct ufs_hba_variant_ops ufs_hba_hi3660_vops = {
548 .init = ufs_hi3660_init,
549 .link_startup_notify = ufs_hisi_link_startup_notify,
550 .pwr_change_notify = ufs_hisi_pwr_change_notify,
551 .suspend = ufs_hisi_suspend,
552 .resume = ufs_hisi_resume,
555 static const struct ufs_hba_variant_ops ufs_hba_hi3670_vops = {
557 .init = ufs_hi3670_init,
558 .link_startup_notify = ufs_hisi_link_startup_notify,
559 .pwr_change_notify = ufs_hisi_pwr_change_notify,
560 .suspend = ufs_hisi_suspend,
561 .resume = ufs_hisi_resume,
564 static const struct of_device_id ufs_hisi_of_match[] = {
565 { .compatible = "hisilicon,hi3660-ufs", .data = &ufs_hba_hi3660_vops },
566 { .compatible = "hisilicon,hi3670-ufs", .data = &ufs_hba_hi3670_vops },
570 MODULE_DEVICE_TABLE(of, ufs_hisi_of_match);
572 static int ufs_hisi_probe(struct platform_device *pdev)
574 const struct of_device_id *of_id;
576 of_id = of_match_node(ufs_hisi_of_match, pdev->dev.of_node);
578 return ufshcd_pltfrm_init(pdev, of_id->data);
581 static int ufs_hisi_remove(struct platform_device *pdev)
583 struct ufs_hba *hba = platform_get_drvdata(pdev);
589 static const struct dev_pm_ops ufs_hisi_pm_ops = {
590 .suspend = ufshcd_pltfrm_suspend,
591 .resume = ufshcd_pltfrm_resume,
592 .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
593 .runtime_resume = ufshcd_pltfrm_runtime_resume,
594 .runtime_idle = ufshcd_pltfrm_runtime_idle,
597 static struct platform_driver ufs_hisi_pltform = {
598 .probe = ufs_hisi_probe,
599 .remove = ufs_hisi_remove,
600 .shutdown = ufshcd_pltfrm_shutdown,
602 .name = "ufshcd-hisi",
603 .pm = &ufs_hisi_pm_ops,
604 .of_match_table = of_match_ptr(ufs_hisi_of_match),
607 module_platform_driver(ufs_hisi_pltform);
609 MODULE_LICENSE("GPL");
610 MODULE_ALIAS("platform:ufshcd-hisi");
611 MODULE_DESCRIPTION("HiSilicon Hixxxx UFS Driver");