1 // SPDX-License-Identifier: GPL-2.0-only
3 * Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
5 * Sun3 DMA routines added by Sam Creasey (sammy@sammy.net)
7 * VME support added by Sam Creasey
9 * TODO: modify this driver to support multiple Sun3 SCSI VME boards
11 * Adapted from mac_scsinew.c:
14 * Generic Macintosh NCR5380 driver
16 * Copyright 1998, Michael Schmitz <mschmitz@lbl.gov>
18 * derived in part from:
21 * Generic Generic NCR5380 driver
23 * Copyright 1995, Russell King
26 #include <linux/types.h>
27 #include <linux/delay.h>
28 #include <linux/module.h>
29 #include <linux/ioport.h>
30 #include <linux/init.h>
31 #include <linux/blkdev.h>
32 #include <linux/platform_device.h>
37 #include <scsi/scsi_host.h>
39 /* minimum number of bytes to do dma on */
40 #define DMA_MIN_SIZE 129
42 /* Definitions for the core NCR5380 driver. */
44 #define NCR5380_implementation_fields /* none */
46 #define NCR5380_read(reg) in_8(hostdata->io + (reg))
47 #define NCR5380_write(reg, value) out_8(hostdata->io + (reg), value)
49 #define NCR5380_queue_command sun3scsi_queue_command
50 #define NCR5380_host_reset sun3scsi_host_reset
51 #define NCR5380_abort sun3scsi_abort
52 #define NCR5380_info sun3scsi_info
54 #define NCR5380_dma_xfer_len sun3scsi_dma_xfer_len
55 #define NCR5380_dma_recv_setup sun3scsi_dma_count
56 #define NCR5380_dma_send_setup sun3scsi_dma_count
57 #define NCR5380_dma_residual sun3scsi_dma_residual
61 /* dma regs start at regbase + 8, directly after the NCR regs */
62 struct sun3_dma_regs {
63 unsigned short dma_addr_hi; /* vme only */
64 unsigned short dma_addr_lo; /* vme only */
65 unsigned short dma_count_hi; /* vme only */
66 unsigned short dma_count_lo; /* vme only */
67 unsigned short udc_data; /* udc dma data reg (obio only) */
68 unsigned short udc_addr; /* uda dma addr reg (obio only) */
69 unsigned short fifo_data; /* fifo data reg,
70 * holds extra byte on odd dma reads
72 unsigned short fifo_count;
73 unsigned short csr; /* control/status reg */
74 unsigned short bpack_hi; /* vme only */
75 unsigned short bpack_lo; /* vme only */
76 unsigned short ivect; /* vme only */
77 unsigned short fifo_count_hi; /* vme only */
80 /* ucd chip specific regs - live in dvma space */
81 struct sun3_udc_regs {
82 unsigned short rsel; /* select regs to load */
83 unsigned short addr_hi; /* high word of addr */
84 unsigned short addr_lo; /* low word */
85 unsigned short count; /* words to be xfer'd */
86 unsigned short mode_hi; /* high word of channel mode */
87 unsigned short mode_lo; /* low word of channel mode */
90 /* addresses of the udc registers */
92 #define UDC_CSR 0x2e /* command/status */
93 #define UDC_CHN_HI 0x26 /* chain high word */
94 #define UDC_CHN_LO 0x22 /* chain lo word */
95 #define UDC_CURA_HI 0x1a /* cur reg A high */
96 #define UDC_CURA_LO 0x0a /* cur reg A low */
97 #define UDC_CURB_HI 0x12 /* cur reg B high */
98 #define UDC_CURB_LO 0x02 /* cur reg B low */
99 #define UDC_MODE_HI 0x56 /* mode reg high */
100 #define UDC_MODE_LO 0x52 /* mode reg low */
101 #define UDC_COUNT 0x32 /* words to xfer */
103 /* some udc commands */
105 #define UDC_CHN_START 0xa0 /* start chain */
106 #define UDC_INT_ENABLE 0x32 /* channel 1 int on */
109 #define UDC_MODE_HIWORD 0x40
110 #define UDC_MODE_LSEND 0xc2
111 #define UDC_MODE_LRECV 0xd2
113 /* udc reg selections */
114 #define UDC_RSEL_SEND 0x282
115 #define UDC_RSEL_RECV 0x182
117 /* bits in csr reg */
118 #define CSR_DMA_ACTIVE 0x8000
119 #define CSR_DMA_CONFLICT 0x4000
120 #define CSR_DMA_BUSERR 0x2000
122 #define CSR_FIFO_EMPTY 0x400 /* fifo flushed? */
123 #define CSR_SDB_INT 0x200 /* sbc interrupt pending */
124 #define CSR_DMA_INT 0x100 /* dma interrupt pending */
126 #define CSR_LEFT 0xc0
127 #define CSR_LEFT_3 0xc0
128 #define CSR_LEFT_2 0x80
129 #define CSR_LEFT_1 0x40
130 #define CSR_PACK_ENABLE 0x20
132 #define CSR_DMA_ENABLE 0x10
134 #define CSR_SEND 0x8 /* 1 = send 0 = recv */
135 #define CSR_FIFO 0x2 /* reset fifo */
136 #define CSR_INTR 0x4 /* interrupt enable */
139 #define VME_DATA24 0x3d00
141 extern int sun3_map_test(unsigned long, char *);
143 static int setup_can_queue = -1;
144 module_param(setup_can_queue, int, 0);
145 static int setup_cmd_per_lun = -1;
146 module_param(setup_cmd_per_lun, int, 0);
147 static int setup_sg_tablesize = -1;
148 module_param(setup_sg_tablesize, int, 0);
149 static int setup_hostid = -1;
150 module_param(setup_hostid, int, 0);
152 /* ms to wait after hitting dma regs */
153 #define SUN3_DMA_DELAY 10
155 /* dvma buffer to allocate -- 32k should hopefully be more than sufficient */
156 #define SUN3_DVMA_BUFSIZE 0xe000
158 static struct scsi_cmnd *sun3_dma_setup_done;
159 static volatile struct sun3_dma_regs *dregs;
160 static struct sun3_udc_regs *udc_regs;
161 static unsigned char *sun3_dma_orig_addr;
162 static unsigned long sun3_dma_orig_count;
163 static int sun3_dma_active;
164 static unsigned long last_residual;
166 #ifndef SUN3_SCSI_VME
167 /* dma controller register access functions */
169 static inline unsigned short sun3_udc_read(unsigned char reg)
173 dregs->udc_addr = UDC_CSR;
174 udelay(SUN3_DMA_DELAY);
175 ret = dregs->udc_data;
176 udelay(SUN3_DMA_DELAY);
181 static inline void sun3_udc_write(unsigned short val, unsigned char reg)
183 dregs->udc_addr = reg;
184 udelay(SUN3_DMA_DELAY);
185 dregs->udc_data = val;
186 udelay(SUN3_DMA_DELAY);
190 // safe bits for the CSR
191 #define CSR_GOOD 0x060f
193 static irqreturn_t scsi_sun3_intr(int irq, void *dev)
195 struct Scsi_Host *instance = dev;
196 unsigned short csr = dregs->csr;
200 dregs->csr &= ~CSR_DMA_ENABLE;
203 if(csr & ~CSR_GOOD) {
204 if (csr & CSR_DMA_BUSERR)
205 shost_printk(KERN_ERR, instance, "bus error in DMA\n");
206 if (csr & CSR_DMA_CONFLICT)
207 shost_printk(KERN_ERR, instance, "DMA conflict\n");
211 if(csr & (CSR_SDB_INT | CSR_DMA_INT)) {
212 NCR5380_intr(irq, dev);
216 return IRQ_RETVAL(handled);
219 /* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */
220 static int sun3scsi_dma_setup(struct NCR5380_hostdata *hostdata,
221 unsigned char *data, int count, int write_flag)
225 if(sun3_dma_orig_addr != NULL)
226 dvma_unmap(sun3_dma_orig_addr);
229 addr = (void *)dvma_map_vme((unsigned long) data, count);
231 addr = (void *)dvma_map((unsigned long) data, count);
234 sun3_dma_orig_addr = addr;
235 sun3_dma_orig_count = count;
237 #ifndef SUN3_SCSI_VME
238 dregs->fifo_count = 0;
239 sun3_udc_write(UDC_RESET, UDC_CSR);
242 dregs->csr &= ~CSR_FIFO;
243 dregs->csr |= CSR_FIFO;
248 dregs->csr |= CSR_SEND;
250 dregs->csr &= ~CSR_SEND;
253 dregs->csr |= CSR_PACK_ENABLE;
255 dregs->dma_addr_hi = ((unsigned long)addr >> 16);
256 dregs->dma_addr_lo = ((unsigned long)addr & 0xffff);
258 dregs->dma_count_hi = 0;
259 dregs->dma_count_lo = 0;
260 dregs->fifo_count_hi = 0;
261 dregs->fifo_count = 0;
263 /* byte count for fifo */
264 dregs->fifo_count = count;
266 sun3_udc_write(UDC_RESET, UDC_CSR);
269 dregs->csr &= ~CSR_FIFO;
270 dregs->csr |= CSR_FIFO;
272 if(dregs->fifo_count != count) {
273 shost_printk(KERN_ERR, hostdata->host,
274 "FIFO mismatch %04x not %04x\n",
275 dregs->fifo_count, (unsigned int) count);
276 NCR5380_dprint(NDEBUG_DMA, hostdata->host);
280 udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8);
281 udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff);
282 udc_regs->count = count/2; /* count in words */
283 udc_regs->mode_hi = UDC_MODE_HIWORD;
287 udc_regs->mode_lo = UDC_MODE_LSEND;
288 udc_regs->rsel = UDC_RSEL_SEND;
290 udc_regs->mode_lo = UDC_MODE_LRECV;
291 udc_regs->rsel = UDC_RSEL_RECV;
294 /* announce location of regs block */
295 sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8),
298 sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO);
300 /* set dma master on */
301 sun3_udc_write(0xd, UDC_MODE);
303 /* interrupt enable */
304 sun3_udc_write(UDC_INT_ENABLE, UDC_CSR);
311 static int sun3scsi_dma_count(struct NCR5380_hostdata *hostdata,
312 unsigned char *data, int count)
317 static inline int sun3scsi_dma_recv_setup(struct NCR5380_hostdata *hostdata,
318 unsigned char *data, int count)
320 return sun3scsi_dma_setup(hostdata, data, count, 0);
323 static inline int sun3scsi_dma_send_setup(struct NCR5380_hostdata *hostdata,
324 unsigned char *data, int count)
326 return sun3scsi_dma_setup(hostdata, data, count, 1);
329 static int sun3scsi_dma_residual(struct NCR5380_hostdata *hostdata)
331 return last_residual;
334 static int sun3scsi_dma_xfer_len(struct NCR5380_hostdata *hostdata,
335 struct scsi_cmnd *cmd)
337 int wanted_len = cmd->SCp.this_residual;
339 if (wanted_len < DMA_MIN_SIZE || blk_rq_is_passthrough(cmd->request))
345 static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data)
352 dregs->dma_count_hi = (sun3_dma_orig_count >> 16);
353 dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff);
355 dregs->fifo_count_hi = (sun3_dma_orig_count >> 16);
356 dregs->fifo_count = (sun3_dma_orig_count & 0xffff);
358 /* if(!(csr & CSR_DMA_ENABLE))
359 * dregs->csr |= CSR_DMA_ENABLE;
362 sun3_udc_write(UDC_CHN_START, UDC_CSR);
368 /* clean up after our dma is done */
369 static int sun3scsi_dma_finish(int write_flag)
371 unsigned short __maybe_unused count;
378 dregs->csr &= ~CSR_DMA_ENABLE;
380 fifo = dregs->fifo_count;
382 if ((fifo > 0) && (fifo < sun3_dma_orig_count))
386 last_residual = fifo;
387 /* empty bytes from the fifo which didn't make it */
388 if ((!write_flag) && (dregs->csr & CSR_LEFT)) {
389 unsigned char *vaddr;
391 vaddr = (unsigned char *)dvma_vmetov(sun3_dma_orig_addr);
393 vaddr += (sun3_dma_orig_count - fifo);
396 switch (dregs->csr & CSR_LEFT) {
398 *vaddr = (dregs->bpack_lo & 0xff00) >> 8;
403 *vaddr = (dregs->bpack_hi & 0x00ff);
408 *vaddr = (dregs->bpack_hi & 0xff00) >> 8;
413 // check to empty the fifo on a read
415 int tmo = 20000; /* .2 sec */
418 if(dregs->csr & CSR_FIFO_EMPTY)
422 printk("sun3scsi: fifo failed to empty!\n");
429 dregs->udc_addr = 0x32;
430 udelay(SUN3_DMA_DELAY);
431 count = 2 * dregs->udc_data;
432 udelay(SUN3_DMA_DELAY);
434 fifo = dregs->fifo_count;
435 last_residual = fifo;
437 /* empty bytes from the fifo which didn't make it */
438 if((!write_flag) && (count - fifo) == 2) {
440 unsigned char *vaddr;
442 data = dregs->fifo_data;
443 vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr);
445 vaddr += (sun3_dma_orig_count - fifo);
447 vaddr[-2] = (data & 0xff00) >> 8;
448 vaddr[-1] = (data & 0xff);
452 dvma_unmap(sun3_dma_orig_addr);
453 sun3_dma_orig_addr = NULL;
456 dregs->dma_addr_hi = 0;
457 dregs->dma_addr_lo = 0;
458 dregs->dma_count_hi = 0;
459 dregs->dma_count_lo = 0;
461 dregs->fifo_count = 0;
462 dregs->fifo_count_hi = 0;
464 dregs->csr &= ~CSR_SEND;
465 /* dregs->csr |= CSR_DMA_ENABLE; */
467 sun3_udc_write(UDC_RESET, UDC_CSR);
468 dregs->fifo_count = 0;
469 dregs->csr &= ~CSR_SEND;
472 dregs->csr &= ~CSR_FIFO;
473 dregs->csr |= CSR_FIFO;
476 sun3_dma_setup_done = NULL;
485 #define SUN3_SCSI_NAME "Sun3 NCR5380 VME SCSI"
486 #define DRV_MODULE_NAME "sun3_scsi_vme"
488 #define SUN3_SCSI_NAME "Sun3 NCR5380 SCSI"
489 #define DRV_MODULE_NAME "sun3_scsi"
492 #define PFX DRV_MODULE_NAME ": "
494 static struct scsi_host_template sun3_scsi_template = {
495 .module = THIS_MODULE,
496 .proc_name = DRV_MODULE_NAME,
497 .name = SUN3_SCSI_NAME,
498 .info = sun3scsi_info,
499 .queuecommand = sun3scsi_queue_command,
500 .eh_abort_handler = sun3scsi_abort,
501 .eh_host_reset_handler = sun3scsi_host_reset,
506 .dma_boundary = PAGE_SIZE - 1,
507 .cmd_size = NCR5380_CMD_SIZE,
510 static int __init sun3_scsi_probe(struct platform_device *pdev)
512 struct Scsi_Host *instance;
513 struct NCR5380_hostdata *hostdata;
515 struct resource *irq, *mem;
516 void __iomem *ioaddr;
522 if (setup_can_queue > 0)
523 sun3_scsi_template.can_queue = setup_can_queue;
524 if (setup_cmd_per_lun > 0)
525 sun3_scsi_template.cmd_per_lun = setup_cmd_per_lun;
526 if (setup_sg_tablesize > 0)
527 sun3_scsi_template.sg_tablesize = setup_sg_tablesize;
528 if (setup_hostid >= 0)
529 sun3_scsi_template.this_id = setup_hostid & 7;
533 for (i = 0; i < 2; i++) {
536 irq = platform_get_resource(pdev, IORESOURCE_IRQ, i);
537 mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
541 ioaddr = sun3_ioremap(mem->start, resource_size(mem),
542 SUN3_PAGE_TYPE_VME16);
543 dregs = (struct sun3_dma_regs *)(ioaddr + 8);
545 if (sun3_map_test((unsigned long)dregs, &x)) {
546 unsigned short oldcsr;
550 udelay(SUN3_DMA_DELAY);
551 if (dregs->csr == 0x1400)
563 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
564 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
568 ioaddr = ioremap(mem->start, resource_size(mem));
569 dregs = (struct sun3_dma_regs *)(ioaddr + 8);
571 udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs));
573 pr_err(PFX "couldn't allocate DVMA memory!\n");
579 instance = scsi_host_alloc(&sun3_scsi_template,
580 sizeof(struct NCR5380_hostdata));
586 instance->irq = irq->start;
588 hostdata = shost_priv(instance);
589 hostdata->base = mem->start;
590 hostdata->io = ioaddr;
592 error = NCR5380_init(instance, host_flags);
596 error = request_irq(instance->irq, scsi_sun3_intr, 0,
597 "NCR5380", instance);
599 pr_err(PFX "scsi%d: IRQ %d not free, bailing out\n",
600 instance->host_no, instance->irq);
605 udelay(SUN3_DMA_DELAY);
606 dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR;
607 udelay(SUN3_DMA_DELAY);
608 dregs->fifo_count = 0;
610 dregs->fifo_count_hi = 0;
611 dregs->dma_addr_hi = 0;
612 dregs->dma_addr_lo = 0;
613 dregs->dma_count_hi = 0;
614 dregs->dma_count_lo = 0;
616 dregs->ivect = VME_DATA24 | (instance->irq & 0xff);
619 NCR5380_maybe_reset_bus(instance);
621 error = scsi_add_host(instance, NULL);
625 platform_set_drvdata(pdev, instance);
627 scsi_scan_host(instance);
631 free_irq(instance->irq, instance);
633 NCR5380_exit(instance);
635 scsi_host_put(instance);
643 static int __exit sun3_scsi_remove(struct platform_device *pdev)
645 struct Scsi_Host *instance = platform_get_drvdata(pdev);
646 struct NCR5380_hostdata *hostdata = shost_priv(instance);
647 void __iomem *ioaddr = hostdata->io;
649 scsi_remove_host(instance);
650 free_irq(instance->irq, instance);
651 NCR5380_exit(instance);
652 scsi_host_put(instance);
659 static struct platform_driver sun3_scsi_driver = {
660 .remove = __exit_p(sun3_scsi_remove),
662 .name = DRV_MODULE_NAME,
666 module_platform_driver_probe(sun3_scsi_driver, sun3_scsi_probe);
668 MODULE_ALIAS("platform:" DRV_MODULE_NAME);
669 MODULE_LICENSE("GPL");