drivers/scsi/smartpqi/smartpqi.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  *    driver for Microchip PQI-based storage controllers
   4  *    Copyright (c) 2019-2021 Microchip Technology Inc. and its subsidiaries
   5  *    Copyright (c) 2016-2018 Microsemi Corporation
   6  *    Copyright (c) 2016 PMC-Sierra, Inc.
   7  *
   8  *    Questions/Comments/Bugfixes to storagedev@microchip.com
   9  *
  10  */
  11
  12 #include <linux/io-64-nonatomic-lo-hi.h>
  13
  14 #if !defined(_SMARTPQI_H)
  15 #define _SMARTPQI_H
  16
  17 #include <scsi/scsi_host.h>
  18 #include <linux/bsg-lib.h>
  19
  20 #pragma pack(1)
  21
  22 #define PQI_DEVICE_SIGNATURE    "PQI DREG"
  23
  24 /* This structure is defined by the PQI specification. */
  25 struct pqi_device_registers {
  26         __le64  signature;
  27         u8      function_and_status_code;
  28         u8      reserved[7];
  29         u8      max_admin_iq_elements;
  30         u8      max_admin_oq_elements;
  31         u8      admin_iq_element_length;        /* in 16-byte units */
  32         u8      admin_oq_element_length;        /* in 16-byte units */
  33         __le16  max_reset_timeout;              /* in 100-millisecond units */
  34         u8      reserved1[2];
  35         __le32  legacy_intx_status;
  36         __le32  legacy_intx_mask_set;
  37         __le32  legacy_intx_mask_clear;
  38         u8      reserved2[28];
  39         __le32  device_status;
  40         u8      reserved3[4];
  41         __le64  admin_iq_pi_offset;
  42         __le64  admin_oq_ci_offset;
  43         __le64  admin_iq_element_array_addr;
  44         __le64  admin_oq_element_array_addr;
  45         __le64  admin_iq_ci_addr;
  46         __le64  admin_oq_pi_addr;
  47         u8      admin_iq_num_elements;
  48         u8      admin_oq_num_elements;
  49         __le16  admin_queue_int_msg_num;
  50         u8      reserved4[4];
  51         __le32  device_error;
  52         u8      reserved5[4];
  53         __le64  error_details;
  54         __le32  device_reset;
  55         __le32  power_action;
  56         u8      reserved6[104];
  57 };
  58
  59 /*
  60  * controller registers
  61  *
  62  * These are defined by the Microchip implementation.
  63  *
  64  * Some registers (those named sis_*) are only used when in
  65  * legacy SIS mode before we transition the controller into
  66  * PQI mode.  There are a number of other SIS mode registers,
  67  * but we don't use them, so only the SIS registers that we
  68  * care about are defined here.  The offsets mentioned in the
  69  * comments are the offsets from the PCIe BAR 0.
  70  */
  71 struct pqi_ctrl_registers {
  72         u8      reserved[0x20];
  73         __le32  sis_host_to_ctrl_doorbell;              /* 20h */
  74         u8      reserved1[0x34 - (0x20 + sizeof(__le32))];
  75         __le32  sis_interrupt_mask;                     /* 34h */
  76         u8      reserved2[0x9c - (0x34 + sizeof(__le32))];
  77         __le32  sis_ctrl_to_host_doorbell;              /* 9Ch */
  78         u8      reserved3[0xa0 - (0x9c + sizeof(__le32))];
  79         __le32  sis_ctrl_to_host_doorbell_clear;        /* A0h */
  80         u8      reserved4[0xb0 - (0xa0 + sizeof(__le32))];
  81         __le32  sis_driver_scratch;                     /* B0h */
  82         __le32  sis_product_identifier;                 /* B4h */
  83         u8      reserved5[0xbc - (0xb4 + sizeof(__le32))];
  84         __le32  sis_firmware_status;                    /* BCh */
  85         u8      reserved6[0xcc - (0xbc + sizeof(__le32))];
  86         __le32  sis_ctrl_shutdown_reason_code;          /* CCh */
  87         u8      reserved7[0x1000 - (0xcc + sizeof(__le32))];
  88         __le32  sis_mailbox[8];                         /* 1000h */
  89         u8      reserved8[0x4000 - (0x1000 + (sizeof(__le32) * 8))];
  90         /*
  91          * The PQI spec states that the PQI registers should be at
  92          * offset 0 from the PCIe BAR 0.  However, we can't map
  93          * them at offset 0 because that would break compatibility
  94          * with the SIS registers.  So we map them at offset 4000h.
  95          */
  96         struct pqi_device_registers pqi_registers;      /* 4000h */
  97 };
  98
  99 #if ((HZ) < 1000)
 100 #define PQI_HZ  1000
 101 #else
 102 #define PQI_HZ  (HZ)
 103 #endif
 104
 105 #define PQI_DEVICE_REGISTERS_OFFSET     0x4000
 106
 107 /* shutdown reasons for taking the controller offline */
 108 enum pqi_ctrl_shutdown_reason {
 109         PQI_IQ_NOT_DRAINED_TIMEOUT = 1,
 110         PQI_LUN_RESET_TIMEOUT = 2,
 111         PQI_IO_PENDING_POST_LUN_RESET_TIMEOUT = 3,
 112         PQI_NO_HEARTBEAT = 4,
 113         PQI_FIRMWARE_KERNEL_NOT_UP = 5,
 114         PQI_OFA_RESPONSE_TIMEOUT = 6,
 115         PQI_INVALID_REQ_ID = 7,
 116         PQI_UNMATCHED_REQ_ID = 8,
 117         PQI_IO_PI_OUT_OF_RANGE = 9,
 118         PQI_EVENT_PI_OUT_OF_RANGE = 10,
 119         PQI_UNEXPECTED_IU_TYPE = 11
 120 };
 121
 122 enum pqi_io_path {
 123         RAID_PATH = 0,
 124         AIO_PATH = 1
 125 };
 126
 127 enum pqi_irq_mode {
 128         IRQ_MODE_NONE,
 129         IRQ_MODE_INTX,
 130         IRQ_MODE_MSIX
 131 };
 132
 133 struct pqi_sg_descriptor {
 134         __le64  address;
 135         __le32  length;
 136         __le32  flags;
 137 };
 138
 139 /* manifest constants for the flags field of pqi_sg_descriptor */
 140 #define CISS_SG_LAST    0x40000000
 141 #define CISS_SG_CHAIN   0x80000000
 142
 143 struct pqi_iu_header {
 144         u8      iu_type;
 145         u8      reserved;
 146         __le16  iu_length;      /* in bytes - does not include the length */
 147                                 /* of this header */
 148         __le16  response_queue_id;      /* specifies the OQ where the */
 149                                         /* response IU is to be delivered */
 150         u16     driver_flags;   /* reserved for driver use */
 151 };
 152
 153 /* manifest constants for pqi_iu_header.driver_flags */
 154 #define PQI_DRIVER_NONBLOCKABLE_REQUEST         0x1
 155
 156 /*
 157  * According to the PQI spec, the IU header is only the first 4 bytes of our
 158  * pqi_iu_header structure.
 159  */
 160 #define PQI_REQUEST_HEADER_LENGTH       4
 161
 162 struct pqi_general_admin_request {
 163         struct pqi_iu_header header;
 164         __le16  request_id;
 165         u8      function_code;
 166         union {
 167                 struct {
 168                         u8      reserved[33];
 169                         __le32  buffer_length;
 170                         struct pqi_sg_descriptor sg_descriptor;
 171                 } report_device_capability;
 172
 173                 struct {
 174                         u8      reserved;
 175                         __le16  queue_id;
 176                         u8      reserved1[2];
 177                         __le64  element_array_addr;
 178                         __le64  ci_addr;
 179                         __le16  num_elements;
 180                         __le16  element_length;
 181                         u8      queue_protocol;
 182                         u8      reserved2[23];
 183                         __le32  vendor_specific;
 184                 } create_operational_iq;
 185
 186                 struct {
 187                         u8      reserved;
 188                         __le16  queue_id;
 189                         u8      reserved1[2];
 190                         __le64  element_array_addr;
 191                         __le64  pi_addr;
 192                         __le16  num_elements;
 193                         __le16  element_length;
 194                         u8      queue_protocol;
 195                         u8      reserved2[3];
 196                         __le16  int_msg_num;
 197                         __le16  coalescing_count;
 198                         __le32  min_coalescing_time;
 199                         __le32  max_coalescing_time;
 200                         u8      reserved3[8];
 201                         __le32  vendor_specific;
 202                 } create_operational_oq;
 203
 204                 struct {
 205                         u8      reserved;
 206                         __le16  queue_id;
 207                         u8      reserved1[50];
 208                 } delete_operational_queue;
 209
 210                 struct {
 211                         u8      reserved;
 212                         __le16  queue_id;
 213                         u8      reserved1[46];
 214                         __le32  vendor_specific;
 215                 } change_operational_iq_properties;
 216
 217         } data;
 218 };
 219
 220 struct pqi_general_admin_response {
 221         struct pqi_iu_header header;
 222         __le16  request_id;
 223         u8      function_code;
 224         u8      status;
 225         union {
 226                 struct {
 227                         u8      status_descriptor[4];
 228                         __le64  iq_pi_offset;
 229                         u8      reserved[40];
 230                 } create_operational_iq;
 231
 232                 struct {
 233                         u8      status_descriptor[4];
 234                         __le64  oq_ci_offset;
 235                         u8      reserved[40];
 236                 } create_operational_oq;
 237         } data;
 238 };
 239
 240 struct pqi_iu_layer_descriptor {
 241         u8      inbound_spanning_supported : 1;
 242         u8      reserved : 7;
 243         u8      reserved1[5];
 244         __le16  max_inbound_iu_length;
 245         u8      outbound_spanning_supported : 1;
 246         u8      reserved2 : 7;
 247         u8      reserved3[5];
 248         __le16  max_outbound_iu_length;
 249 };
 250
 251 struct pqi_device_capability {
 252         __le16  data_length;
 253         u8      reserved[6];
 254         u8      iq_arbitration_priority_support_bitmask;
 255         u8      maximum_aw_a;
 256         u8      maximum_aw_b;
 257         u8      maximum_aw_c;
 258         u8      max_arbitration_burst : 3;
 259         u8      reserved1 : 4;
 260         u8      iqa : 1;
 261         u8      reserved2[2];
 262         u8      iq_freeze : 1;
 263         u8      reserved3 : 7;
 264         __le16  max_inbound_queues;
 265         __le16  max_elements_per_iq;
 266         u8      reserved4[4];
 267         __le16  max_iq_element_length;
 268         __le16  min_iq_element_length;
 269         u8      reserved5[2];
 270         __le16  max_outbound_queues;
 271         __le16  max_elements_per_oq;
 272         __le16  intr_coalescing_time_granularity;
 273         __le16  max_oq_element_length;
 274         __le16  min_oq_element_length;
 275         u8      reserved6[24];
 276         struct pqi_iu_layer_descriptor iu_layer_descriptors[32];
 277 };
 278
 279 #define PQI_MAX_EMBEDDED_SG_DESCRIPTORS         4
 280 #define PQI_MAX_EMBEDDED_R56_SG_DESCRIPTORS     3
 281
 282 struct pqi_raid_path_request {
 283         struct pqi_iu_header header;
 284         __le16  request_id;
 285         __le16  nexus_id;
 286         __le32  buffer_length;
 287         u8      lun_number[8];
 288         __le16  protocol_specific;
 289         u8      data_direction : 2;
 290         u8      partial : 1;
 291         u8      reserved1 : 4;
 292         u8      fence : 1;
 293         __le16  error_index;
 294         u8      reserved2;
 295         u8      task_attribute : 3;
 296         u8      command_priority : 4;
 297         u8      reserved3 : 1;
 298         u8      reserved4 : 2;
 299         u8      additional_cdb_bytes_usage : 3;
 300         u8      reserved5 : 3;
 301         u8      cdb[16];
 302         u8      reserved6[12];
 303         __le32  timeout;
 304         struct pqi_sg_descriptor sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS];
 305 };
 306
 307 struct pqi_aio_path_request {
 308         struct pqi_iu_header header;
 309         __le16  request_id;
 310         u8      reserved1[2];
 311         __le32  nexus_id;
 312         __le32  buffer_length;
 313         u8      data_direction : 2;
 314         u8      partial : 1;
 315         u8      memory_type : 1;
 316         u8      fence : 1;
 317         u8      encryption_enable : 1;
 318         u8      reserved2 : 2;
 319         u8      task_attribute : 3;
 320         u8      command_priority : 4;
 321         u8      reserved3 : 1;
 322         __le16  data_encryption_key_index;
 323         __le32  encrypt_tweak_lower;
 324         __le32  encrypt_tweak_upper;
 325         u8      cdb[16];
 326         __le16  error_index;
 327         u8      num_sg_descriptors;
 328         u8      cdb_length;
 329         u8      lun_number[8];
 330         u8      reserved4[4];
 331         struct pqi_sg_descriptor sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS];
 332 };
 333
 334 #define PQI_RAID1_NVME_XFER_LIMIT       (32 * 1024)     /* 32 KiB */
 335
 336 struct pqi_aio_r1_path_request {
 337         struct pqi_iu_header header;
 338         __le16  request_id;
 339         __le16  volume_id;      /* ID of the RAID volume */
 340         __le32  it_nexus_1;     /* IT nexus of the 1st drive in the RAID volume */
 341         __le32  it_nexus_2;     /* IT nexus of the 2nd drive in the RAID volume */
 342         __le32  it_nexus_3;     /* IT nexus of the 3rd drive in the RAID volume */
 343         __le32  data_length;    /* total bytes to read/write */
 344         u8      data_direction : 2;
 345         u8      partial : 1;
 346         u8      memory_type : 1;
 347         u8      fence : 1;
 348         u8      encryption_enable : 1;
 349         u8      reserved : 2;
 350         u8      task_attribute : 3;
 351         u8      command_priority : 4;
 352         u8      reserved2 : 1;
 353         __le16  data_encryption_key_index;
 354         u8      cdb[16];
 355         __le16  error_index;
 356         u8      num_sg_descriptors;
 357         u8      cdb_length;
 358         u8      num_drives;     /* number of drives in the RAID volume (2 or 3) */
 359         u8      reserved3[3];
 360         __le32  encrypt_tweak_lower;
 361         __le32  encrypt_tweak_upper;
 362         struct pqi_sg_descriptor sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS];
 363 };
 364
 365 #define PQI_DEFAULT_MAX_WRITE_RAID_5_6                  (8 * 1024U)
 366 #define PQI_DEFAULT_MAX_TRANSFER_ENCRYPTED_SAS_SATA     (~0U)
 367 #define PQI_DEFAULT_MAX_TRANSFER_ENCRYPTED_NVME         (32 * 1024U)
 368
 369 struct pqi_aio_r56_path_request {
 370         struct pqi_iu_header header;
 371         __le16  request_id;
 372         __le16  volume_id;              /* ID of the RAID volume */
 373         __le32  data_it_nexus;          /* IT nexus for the data drive */
 374         __le32  p_parity_it_nexus;      /* IT nexus for the P parity drive */
 375         __le32  q_parity_it_nexus;      /* IT nexus for the Q parity drive */
 376         __le32  data_length;            /* total bytes to read/write */
 377         u8      data_direction : 2;
 378         u8      partial : 1;
 379         u8      mem_type : 1;           /* 0 = PCIe, 1 = DDR */
 380         u8      fence : 1;
 381         u8      encryption_enable : 1;
 382         u8      reserved : 2;
 383         u8      task_attribute : 3;
 384         u8      command_priority : 4;
 385         u8      reserved1 : 1;
 386         __le16  data_encryption_key_index;
 387         u8      cdb[16];
 388         __le16  error_index;
 389         u8      num_sg_descriptors;
 390         u8      cdb_length;
 391         u8      xor_multiplier;
 392         u8      reserved2[3];
 393         __le32  encrypt_tweak_lower;
 394         __le32  encrypt_tweak_upper;
 395         __le64  row;                    /* row = logical LBA/blocks per row */
 396         u8      reserved3[8];
 397         struct pqi_sg_descriptor sg_descriptors[PQI_MAX_EMBEDDED_R56_SG_DESCRIPTORS];
 398 };
 399
 400 struct pqi_io_response {
 401         struct pqi_iu_header header;
 402         __le16  request_id;
 403         __le16  error_index;
 404         u8      reserved2[4];
 405 };
 406
 407 struct pqi_general_management_request {
 408         struct pqi_iu_header header;
 409         __le16  request_id;
 410         union {
 411                 struct {
 412                         u8      reserved[2];
 413                         __le32  buffer_length;
 414                         struct pqi_sg_descriptor sg_descriptors[3];
 415                 } report_event_configuration;
 416
 417                 struct {
 418                         __le16  global_event_oq_id;
 419                         __le32  buffer_length;
 420                         struct pqi_sg_descriptor sg_descriptors[3];
 421                 } set_event_configuration;
 422         } data;
 423 };
 424
 425 struct pqi_event_descriptor {
 426         u8      event_type;
 427         u8      reserved;
 428         __le16  oq_id;
 429 };
 430
 431 struct pqi_event_config {
 432         u8      reserved[2];
 433         u8      num_event_descriptors;
 434         u8      reserved1;
 435         struct pqi_event_descriptor descriptors[];
 436 };
 437
 438 #define PQI_MAX_EVENT_DESCRIPTORS       255
 439
 440 #define PQI_EVENT_OFA_MEMORY_ALLOCATION 0x0
 441 #define PQI_EVENT_OFA_QUIESCE           0x1
 442 #define PQI_EVENT_OFA_CANCELED          0x2
 443
 444 struct pqi_event_response {
 445         struct pqi_iu_header header;
 446         u8      event_type;
 447         u8      reserved2 : 7;
 448         u8      request_acknowledge : 1;
 449         __le16  event_id;
 450         __le32  additional_event_id;
 451         union {
 452                 struct {
 453                         __le32  bytes_requested;
 454                         u8      reserved[12];
 455                 } ofa_memory_allocation;
 456
 457                 struct {
 458                         __le16  reason;         /* reason for cancellation */
 459                         u8      reserved[14];
 460                 } ofa_cancelled;
 461         } data;
 462 };
 463
 464 struct pqi_event_acknowledge_request {
 465         struct pqi_iu_header header;
 466         u8      event_type;
 467         u8      reserved2;
 468         __le16  event_id;
 469         __le32  additional_event_id;
 470 };
 471
 472 struct pqi_task_management_request {
 473         struct pqi_iu_header header;
 474         __le16  request_id;
 475         __le16  nexus_id;
 476         u8      reserved[2];
 477         __le16  timeout;
 478         u8      lun_number[8];
 479         __le16  protocol_specific;
 480         __le16  outbound_queue_id_to_manage;
 481         __le16  request_id_to_manage;
 482         u8      task_management_function;
 483         u8      reserved2 : 7;
 484         u8      fence : 1;
 485 };
 486
 487 #define SOP_TASK_MANAGEMENT_LUN_RESET   0x8
 488
 489 struct pqi_task_management_response {
 490         struct pqi_iu_header header;
 491         __le16  request_id;
 492         __le16  nexus_id;
 493         u8      additional_response_info[3];
 494         u8      response_code;
 495 };
 496
 497 struct pqi_vendor_general_request {
 498         struct pqi_iu_header header;
 499         __le16  request_id;
 500         __le16  function_code;
 501         union {
 502                 struct {
 503                         __le16  first_section;
 504                         __le16  last_section;
 505                         u8      reserved[48];
 506                 } config_table_update;
 507
 508                 struct {
 509                         __le64  buffer_address;
 510                         __le32  buffer_length;
 511                         u8      reserved[40];
 512                 } ofa_memory_allocation;
 513         } data;
 514 };
 515
 516 struct pqi_vendor_general_response {
 517         struct pqi_iu_header header;
 518         __le16  request_id;
 519         __le16  function_code;
 520         __le16  status;
 521         u8      reserved[2];
 522 };
 523
 524 #define PQI_VENDOR_GENERAL_CONFIG_TABLE_UPDATE  0
 525 #define PQI_VENDOR_GENERAL_HOST_MEMORY_UPDATE   1
 526
 527 #define PQI_OFA_VERSION                 1
 528 #define PQI_OFA_SIGNATURE               "OFA_QRM"
 529 #define PQI_OFA_MAX_SG_DESCRIPTORS      64
 530
 531 struct pqi_ofa_memory {
 532         __le64  signature;      /* "OFA_QRM" */
 533         __le16  version;        /* version of this struct (1 = 1st version) */
 534         u8      reserved[62];
 535         __le32  bytes_allocated;        /* total allocated memory in bytes */
 536         __le16  num_memory_descriptors;
 537         u8      reserved1[2];
 538         struct pqi_sg_descriptor sg_descriptor[PQI_OFA_MAX_SG_DESCRIPTORS];
 539 };
 540
 541 struct pqi_aio_error_info {
 542         u8      status;
 543         u8      service_response;
 544         u8      data_present;
 545         u8      reserved;
 546         __le32  residual_count;
 547         __le16  data_length;
 548         __le16  reserved1;
 549         u8      data[256];
 550 };
 551
 552 struct pqi_raid_error_info {
 553         u8      data_in_result;
 554         u8      data_out_result;
 555         u8      reserved[3];
 556         u8      status;
 557         __le16  status_qualifier;
 558         __le16  sense_data_length;
 559         __le16  response_data_length;
 560         __le32  data_in_transferred;
 561         __le32  data_out_transferred;
 562         u8      data[256];
 563 };
 564
 565 #define PQI_REQUEST_IU_TASK_MANAGEMENT                  0x13
 566 #define PQI_REQUEST_IU_RAID_PATH_IO                     0x14
 567 #define PQI_REQUEST_IU_AIO_PATH_IO                      0x15
 568 #define PQI_REQUEST_IU_AIO_PATH_RAID5_IO                0x18
 569 #define PQI_REQUEST_IU_AIO_PATH_RAID6_IO                0x19
 570 #define PQI_REQUEST_IU_AIO_PATH_RAID1_IO                0x1A
 571 #define PQI_REQUEST_IU_GENERAL_ADMIN                    0x60
 572 #define PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG       0x72
 573 #define PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG          0x73
 574 #define PQI_REQUEST_IU_VENDOR_GENERAL                   0x75
 575 #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT         0xf6
 576
 577 #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT              0x81
 578 #define PQI_RESPONSE_IU_TASK_MANAGEMENT                 0x93
 579 #define PQI_RESPONSE_IU_GENERAL_ADMIN                   0xe0
 580 #define PQI_RESPONSE_IU_RAID_PATH_IO_SUCCESS            0xf0
 581 #define PQI_RESPONSE_IU_AIO_PATH_IO_SUCCESS             0xf1
 582 #define PQI_RESPONSE_IU_RAID_PATH_IO_ERROR              0xf2
 583 #define PQI_RESPONSE_IU_AIO_PATH_IO_ERROR               0xf3
 584 #define PQI_RESPONSE_IU_AIO_PATH_DISABLED               0xf4
 585 #define PQI_RESPONSE_IU_VENDOR_EVENT                    0xf5
 586 #define PQI_RESPONSE_IU_VENDOR_GENERAL                  0xf7
 587
 588 #define PQI_GENERAL_ADMIN_FUNCTION_REPORT_DEVICE_CAPABILITY     0x0
 589 #define PQI_GENERAL_ADMIN_FUNCTION_CREATE_IQ                    0x10
 590 #define PQI_GENERAL_ADMIN_FUNCTION_CREATE_OQ                    0x11
 591 #define PQI_GENERAL_ADMIN_FUNCTION_DELETE_IQ                    0x12
 592 #define PQI_GENERAL_ADMIN_FUNCTION_DELETE_OQ                    0x13
 593 #define PQI_GENERAL_ADMIN_FUNCTION_CHANGE_IQ_PROPERTY           0x14
 594
 595 #define PQI_GENERAL_ADMIN_STATUS_SUCCESS        0x0
 596
 597 #define PQI_IQ_PROPERTY_IS_AIO_QUEUE    0x1
 598
 599 #define PQI_GENERAL_ADMIN_IU_LENGTH             0x3c
 600 #define PQI_PROTOCOL_SOP                        0x0
 601
 602 #define PQI_DATA_IN_OUT_GOOD                                    0x0
 603 #define PQI_DATA_IN_OUT_UNDERFLOW                               0x1
 604 #define PQI_DATA_IN_OUT_BUFFER_ERROR                            0x40
 605 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW                         0x41
 606 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA         0x42
 607 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE                  0x43
 608 #define PQI_DATA_IN_OUT_PCIE_FABRIC_ERROR                       0x60
 609 #define PQI_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT                 0x61
 610 #define PQI_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED           0x62
 611 #define PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST_RECEIVED       0x63
 612 #define PQI_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED                  0x64
 613 #define PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST                0x65
 614 #define PQI_DATA_IN_OUT_PCIE_ACS_VIOLATION                      0x66
 615 #define PQI_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED                 0x67
 616 #define PQI_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ               0x6F
 617 #define PQI_DATA_IN_OUT_ERROR                                   0xf0
 618 #define PQI_DATA_IN_OUT_PROTOCOL_ERROR                          0xf1
 619 #define PQI_DATA_IN_OUT_HARDWARE_ERROR                          0xf2
 620 #define PQI_DATA_IN_OUT_UNSOLICITED_ABORT                       0xf3
 621 #define PQI_DATA_IN_OUT_ABORTED                                 0xf4
 622 #define PQI_DATA_IN_OUT_TIMEOUT                                 0xf5
 623
 624 #define CISS_CMD_STATUS_SUCCESS                 0x0
 625 #define CISS_CMD_STATUS_TARGET_STATUS           0x1
 626 #define CISS_CMD_STATUS_DATA_UNDERRUN           0x2
 627 #define CISS_CMD_STATUS_DATA_OVERRUN            0x3
 628 #define CISS_CMD_STATUS_INVALID                 0x4
 629 #define CISS_CMD_STATUS_PROTOCOL_ERROR          0x5
 630 #define CISS_CMD_STATUS_HARDWARE_ERROR          0x6
 631 #define CISS_CMD_STATUS_CONNECTION_LOST         0x7
 632 #define CISS_CMD_STATUS_ABORTED                 0x8
 633 #define CISS_CMD_STATUS_ABORT_FAILED            0x9
 634 #define CISS_CMD_STATUS_UNSOLICITED_ABORT       0xa
 635 #define CISS_CMD_STATUS_TIMEOUT                 0xb
 636 #define CISS_CMD_STATUS_UNABORTABLE             0xc
 637 #define CISS_CMD_STATUS_TMF                     0xd
 638 #define CISS_CMD_STATUS_AIO_DISABLED            0xe
 639
 640 #define PQI_CMD_STATUS_ABORTED  CISS_CMD_STATUS_ABORTED
 641
 642 #define PQI_NUM_EVENT_QUEUE_ELEMENTS    32
 643 #define PQI_EVENT_OQ_ELEMENT_LENGTH     sizeof(struct pqi_event_response)
 644
 645 #define PQI_EVENT_TYPE_HOTPLUG                  0x1
 646 #define PQI_EVENT_TYPE_HARDWARE                 0x2
 647 #define PQI_EVENT_TYPE_PHYSICAL_DEVICE          0x4
 648 #define PQI_EVENT_TYPE_LOGICAL_DEVICE           0x5
 649 #define PQI_EVENT_TYPE_OFA                      0xfb
 650 #define PQI_EVENT_TYPE_AIO_STATE_CHANGE         0xfd
 651 #define PQI_EVENT_TYPE_AIO_CONFIG_CHANGE        0xfe
 652
 653 #pragma pack()
 654
 655 #define PQI_ERROR_BUFFER_ELEMENT_LENGTH         \
 656         sizeof(struct pqi_raid_error_info)
 657
 658 /* these values are based on our implementation */
 659 #define PQI_ADMIN_IQ_NUM_ELEMENTS               8
 660 #define PQI_ADMIN_OQ_NUM_ELEMENTS               20
 661 #define PQI_ADMIN_IQ_ELEMENT_LENGTH             64
 662 #define PQI_ADMIN_OQ_ELEMENT_LENGTH             64
 663
 664 #define PQI_OPERATIONAL_IQ_ELEMENT_LENGTH       128
 665 #define PQI_OPERATIONAL_OQ_ELEMENT_LENGTH       16
 666
 667 #define PQI_MIN_MSIX_VECTORS            1
 668 #define PQI_MAX_MSIX_VECTORS            64
 669
 670 /* these values are defined by the PQI spec */
 671 #define PQI_MAX_NUM_ELEMENTS_ADMIN_QUEUE        255
 672 #define PQI_MAX_NUM_ELEMENTS_OPERATIONAL_QUEUE  65535
 673
 674 #define PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT       64
 675 #define PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT      16
 676 #define PQI_ADMIN_INDEX_ALIGNMENT               64
 677 #define PQI_OPERATIONAL_INDEX_ALIGNMENT         4
 678
 679 #define PQI_MIN_OPERATIONAL_QUEUE_ID            1
 680 #define PQI_MAX_OPERATIONAL_QUEUE_ID            65535
 681
 682 #define PQI_AIO_SERV_RESPONSE_COMPLETE          0
 683 #define PQI_AIO_SERV_RESPONSE_FAILURE           1
 684 #define PQI_AIO_SERV_RESPONSE_TMF_COMPLETE      2
 685 #define PQI_AIO_SERV_RESPONSE_TMF_SUCCEEDED     3
 686 #define PQI_AIO_SERV_RESPONSE_TMF_REJECTED      4
 687 #define PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN 5
 688
 689 #define PQI_AIO_STATUS_IO_ERROR                 0x1
 690 #define PQI_AIO_STATUS_IO_ABORTED               0x2
 691 #define PQI_AIO_STATUS_NO_PATH_TO_DEVICE        0x3
 692 #define PQI_AIO_STATUS_INVALID_DEVICE           0x4
 693 #define PQI_AIO_STATUS_AIO_PATH_DISABLED        0xe
 694 #define PQI_AIO_STATUS_UNDERRUN                 0x51
 695 #define PQI_AIO_STATUS_OVERRUN                  0x75
 696
 697 typedef u32 pqi_index_t;
 698
 699 /* SOP data direction flags */
 700 #define SOP_NO_DIRECTION_FLAG   0
 701 #define SOP_WRITE_FLAG          1       /* host writes data to Data-Out */
 702                                         /* buffer */
 703 #define SOP_READ_FLAG           2       /* host receives data from Data-In */
 704                                         /* buffer */
 705 #define SOP_BIDIRECTIONAL       3       /* data is transferred from the */
 706                                         /* Data-Out buffer and data is */
 707                                         /* transferred to the Data-In buffer */
 708
 709 #define SOP_TASK_ATTRIBUTE_SIMPLE               0
 710 #define SOP_TASK_ATTRIBUTE_HEAD_OF_QUEUE        1
 711 #define SOP_TASK_ATTRIBUTE_ORDERED              2
 712 #define SOP_TASK_ATTRIBUTE_ACA                  4
 713
 714 #define SOP_TMF_COMPLETE                0x0
 715 #define SOP_TMF_REJECTED                0x4
 716 #define SOP_TMF_FUNCTION_SUCCEEDED      0x8
 717
 718 /* additional CDB bytes usage field codes */
 719 #define SOP_ADDITIONAL_CDB_BYTES_0      0       /* 16-byte CDB */
 720 #define SOP_ADDITIONAL_CDB_BYTES_4      1       /* 20-byte CDB */
 721 #define SOP_ADDITIONAL_CDB_BYTES_8      2       /* 24-byte CDB */
 722 #define SOP_ADDITIONAL_CDB_BYTES_12     3       /* 28-byte CDB */
 723 #define SOP_ADDITIONAL_CDB_BYTES_16     4       /* 32-byte CDB */
 724
 725 /*
 726  * The purpose of this structure is to obtain proper alignment of objects in
 727  * an admin queue pair.
 728  */
 729 struct pqi_admin_queues_aligned {
 730         __aligned(PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT)
 731                 u8      iq_element_array[PQI_ADMIN_IQ_ELEMENT_LENGTH]
 732                                         [PQI_ADMIN_IQ_NUM_ELEMENTS];
 733         __aligned(PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT)
 734                 u8      oq_element_array[PQI_ADMIN_OQ_ELEMENT_LENGTH]
 735                                         [PQI_ADMIN_OQ_NUM_ELEMENTS];
 736         __aligned(PQI_ADMIN_INDEX_ALIGNMENT) pqi_index_t iq_ci;
 737         __aligned(PQI_ADMIN_INDEX_ALIGNMENT) pqi_index_t oq_pi;
 738 };
 739
 740 struct pqi_admin_queues {
 741         void            *iq_element_array;
 742         void            *oq_element_array;
 743         pqi_index_t __iomem *iq_ci;
 744         pqi_index_t __iomem *oq_pi;
 745         dma_addr_t      iq_element_array_bus_addr;
 746         dma_addr_t      oq_element_array_bus_addr;
 747         dma_addr_t      iq_ci_bus_addr;
 748         dma_addr_t      oq_pi_bus_addr;
 749         __le32 __iomem  *iq_pi;
 750         pqi_index_t     iq_pi_copy;
 751         __le32 __iomem  *oq_ci;
 752         pqi_index_t     oq_ci_copy;
 753         struct task_struct *task;
 754         u16             int_msg_num;
 755 };
 756
 757 struct pqi_queue_group {
 758         struct pqi_ctrl_info *ctrl_info;        /* backpointer */
 759         u16             iq_id[2];
 760         u16             oq_id;
 761         u16             int_msg_num;
 762         void            *iq_element_array[2];
 763         void            *oq_element_array;
 764         dma_addr_t      iq_element_array_bus_addr[2];
 765         dma_addr_t      oq_element_array_bus_addr;
 766         __le32 __iomem  *iq_pi[2];
 767         pqi_index_t     iq_pi_copy[2];
 768         pqi_index_t __iomem *iq_ci[2];
 769         pqi_index_t __iomem *oq_pi;
 770         dma_addr_t      iq_ci_bus_addr[2];
 771         dma_addr_t      oq_pi_bus_addr;
 772         __le32 __iomem  *oq_ci;
 773         pqi_index_t     oq_ci_copy;
 774         spinlock_t      submit_lock[2]; /* protect submission queue */
 775         struct list_head request_list[2];
 776 };
 777
 778 struct pqi_event_queue {
 779         u16             oq_id;
 780         u16             int_msg_num;
 781         void            *oq_element_array;
 782         pqi_index_t __iomem *oq_pi;
 783         dma_addr_t      oq_element_array_bus_addr;
 784         dma_addr_t      oq_pi_bus_addr;
 785         __le32 __iomem  *oq_ci;
 786         pqi_index_t     oq_ci_copy;
 787 };
 788
 789 #define PQI_DEFAULT_QUEUE_GROUP         0
 790 #define PQI_MAX_QUEUE_GROUPS            PQI_MAX_MSIX_VECTORS
 791
 792 struct pqi_encryption_info {
 793         u16     data_encryption_key_index;
 794         u32     encrypt_tweak_lower;
 795         u32     encrypt_tweak_upper;
 796 };
 797
 798 #pragma pack(1)
 799
 800 #define PQI_CONFIG_TABLE_SIGNATURE      "CFGTABLE"
 801 #define PQI_CONFIG_TABLE_MAX_LENGTH     ((u16)~0)
 802
 803 /* configuration table section IDs */
 804 #define PQI_CONFIG_TABLE_ALL_SECTIONS                   (-1)
 805 #define PQI_CONFIG_TABLE_SECTION_GENERAL_INFO           0
 806 #define PQI_CONFIG_TABLE_SECTION_FIRMWARE_FEATURES      1
 807 #define PQI_CONFIG_TABLE_SECTION_FIRMWARE_ERRATA        2
 808 #define PQI_CONFIG_TABLE_SECTION_DEBUG                  3
 809 #define PQI_CONFIG_TABLE_SECTION_HEARTBEAT              4
 810 #define PQI_CONFIG_TABLE_SECTION_SOFT_RESET             5
 811
 812 struct pqi_config_table {
 813         u8      signature[8];           /* "CFGTABLE" */
 814         __le32  first_section_offset;   /* offset in bytes from the base */
 815                                         /* address of this table to the */
 816                                         /* first section */
 817 };
 818
 819 struct pqi_config_table_section_header {
 820         __le16  section_id;             /* as defined by the */
 821                                         /* PQI_CONFIG_TABLE_SECTION_* */
 822                                         /* manifest constants above */
 823         __le16  next_section_offset;    /* offset in bytes from base */
 824                                         /* address of the table of the */
 825                                         /* next section or 0 if last entry */
 826 };
 827
 828 struct pqi_config_table_general_info {
 829         struct pqi_config_table_section_header header;
 830         __le32  section_length;         /* size of this section in bytes */
 831                                         /* including the section header */
 832         __le32  max_outstanding_requests;       /* max. outstanding */
 833                                                 /* commands supported by */
 834                                                 /* the controller */
 835         __le32  max_sg_size;            /* max. transfer size of a single */
 836                                         /* command */
 837         __le32  max_sg_per_request;     /* max. number of scatter-gather */
 838                                         /* entries supported in a single */
 839                                         /* command */
 840 };
 841
 842 struct pqi_config_table_firmware_features {
 843         struct pqi_config_table_section_header header;
 844         __le16  num_elements;
 845         u8      features_supported[];
 846 /*      u8      features_requested_by_host[]; */
 847 /*      u8      features_enabled[]; */
 848 /* The 2 fields below are only valid if the MAX_KNOWN_FEATURE bit is set. */
 849 /*      __le16  firmware_max_known_feature; */
 850 /*      __le16  host_max_known_feature; */
 851 };
 852
 853 #define PQI_FIRMWARE_FEATURE_OFA                                0
 854 #define PQI_FIRMWARE_FEATURE_SMP                                1
 855 #define PQI_FIRMWARE_FEATURE_MAX_KNOWN_FEATURE                  2
 856 #define PQI_FIRMWARE_FEATURE_RAID_0_READ_BYPASS                 3
 857 #define PQI_FIRMWARE_FEATURE_RAID_1_READ_BYPASS                 4
 858 #define PQI_FIRMWARE_FEATURE_RAID_5_READ_BYPASS                 5
 859 #define PQI_FIRMWARE_FEATURE_RAID_6_READ_BYPASS                 6
 860 #define PQI_FIRMWARE_FEATURE_RAID_0_WRITE_BYPASS                7
 861 #define PQI_FIRMWARE_FEATURE_RAID_1_WRITE_BYPASS                8
 862 #define PQI_FIRMWARE_FEATURE_RAID_5_WRITE_BYPASS                9
 863 #define PQI_FIRMWARE_FEATURE_RAID_6_WRITE_BYPASS                10
 864 #define PQI_FIRMWARE_FEATURE_SOFT_RESET_HANDSHAKE               11
 865 #define PQI_FIRMWARE_FEATURE_UNIQUE_SATA_WWN                    12
 866 #define PQI_FIRMWARE_FEATURE_RAID_IU_TIMEOUT                    13
 867 #define PQI_FIRMWARE_FEATURE_TMF_IU_TIMEOUT                     14
 868 #define PQI_FIRMWARE_FEATURE_RAID_BYPASS_ON_ENCRYPTED_NVME      15
 869 #define PQI_FIRMWARE_FEATURE_UNIQUE_WWID_IN_REPORT_PHYS_LUN     16
 870 #define PQI_FIRMWARE_FEATURE_FW_TRIAGE                          17
 871 #define PQI_FIRMWARE_FEATURE_RPL_EXTENDED_FORMAT_4_5            18
 872 #define PQI_FIRMWARE_FEATURE_MAXIMUM                            18
 873
 874 struct pqi_config_table_debug {
 875         struct pqi_config_table_section_header header;
 876         __le32  scratchpad;
 877 };
 878
 879 struct pqi_config_table_heartbeat {
 880         struct pqi_config_table_section_header header;
 881         __le32  heartbeat_counter;
 882 };
 883
 884 struct pqi_config_table_soft_reset {
 885         struct pqi_config_table_section_header header;
 886         u8 soft_reset_status;
 887 };
 888
 889 #define PQI_SOFT_RESET_INITIATE         0x1
 890 #define PQI_SOFT_RESET_ABORT            0x2
 891
 892 enum pqi_soft_reset_status {
 893         RESET_INITIATE_FIRMWARE,
 894         RESET_INITIATE_DRIVER,
 895         RESET_ABORT,
 896         RESET_NORESPONSE,
 897         RESET_TIMEDOUT
 898 };
 899
 900 union pqi_reset_register {
 901         struct {
 902                 u32     reset_type : 3;
 903                 u32     reserved : 2;
 904                 u32     reset_action : 3;
 905                 u32     hold_in_pd1 : 1;
 906                 u32     reserved2 : 23;
 907         } bits;
 908         u32     all_bits;
 909 };
 910
 911 #define PQI_RESET_ACTION_RESET          0x1
 912
 913 #define PQI_RESET_TYPE_NO_RESET         0x0
 914 #define PQI_RESET_TYPE_SOFT_RESET       0x1
 915 #define PQI_RESET_TYPE_FIRM_RESET       0x2
 916 #define PQI_RESET_TYPE_HARD_RESET       0x3
 917
 918 #define PQI_RESET_ACTION_COMPLETED      0x2
 919
 920 #define PQI_RESET_POLL_INTERVAL_MSECS   100
 921
 922 #define PQI_MAX_OUTSTANDING_REQUESTS            ((u32)~0)
 923 #define PQI_MAX_OUTSTANDING_REQUESTS_KDUMP      32
 924 #define PQI_MAX_TRANSFER_SIZE                   (1024U * 1024U)
 925 #define PQI_MAX_TRANSFER_SIZE_KDUMP             (512 * 1024U)
 926
 927 #define RAID_MAP_MAX_ENTRIES            1024
 928
 929 #define PQI_PHYSICAL_DEVICE_BUS         0
 930 #define PQI_RAID_VOLUME_BUS             1
 931 #define PQI_HBA_BUS                     2
 932 #define PQI_EXTERNAL_RAID_VOLUME_BUS    3
 933 #define PQI_MAX_BUS                     PQI_EXTERNAL_RAID_VOLUME_BUS
 934 #define PQI_VSEP_CISS_BTL               379
 935
 936 struct report_lun_header {
 937         __be32  list_length;
 938         u8      flags;
 939         u8      reserved[3];
 940 };
 941
 942 /* for flags field of struct report_lun_header */
 943 #define CISS_REPORT_LOG_FLAG_UNIQUE_LUN_ID      (1 << 0)
 944 #define CISS_REPORT_LOG_FLAG_QUEUE_DEPTH        (1 << 5)
 945 #define CISS_REPORT_LOG_FLAG_DRIVE_TYPE_MIX     (1 << 6)
 946
 947 #define CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_2         0x2
 948 #define CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_4         0x4
 949 #define CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_MASK      0xf
 950
 951 struct report_log_lun {
 952         u8      lunid[8];
 953         u8      volume_id[16];
 954 };
 955
 956 struct report_log_lun_list {
 957         struct report_lun_header header;
 958         struct report_log_lun lun_entries[1];
 959 };
 960
 961 struct report_phys_lun_8byte_wwid {
 962         u8      lunid[8];
 963         __be64  wwid;
 964         u8      device_type;
 965         u8      device_flags;
 966         u8      lun_count;      /* number of LUNs in a multi-LUN device */
 967         u8      redundant_paths;
 968         u32     aio_handle;
 969 };
 970
 971 struct report_phys_lun_16byte_wwid {
 972         u8      lunid[8];
 973         u8      wwid[16];
 974         u8      device_type;
 975         u8      device_flags;
 976         u8      lun_count;      /* number of LUNs in a multi-LUN device */
 977         u8      redundant_paths;
 978         u32     aio_handle;
 979 };
 980
 981 /* for device_flags field of struct report_phys_lun_extended_entry */
 982 #define CISS_REPORT_PHYS_DEV_FLAG_AIO_ENABLED   0x8
 983
 984 struct report_phys_lun_8byte_wwid_list {
 985         struct report_lun_header header;
 986         struct report_phys_lun_8byte_wwid lun_entries[1];
 987 };
 988
 989 struct report_phys_lun_16byte_wwid_list {
 990         struct report_lun_header header;
 991         struct report_phys_lun_16byte_wwid lun_entries[1];
 992 };
 993
 994 struct raid_map_disk_data {
 995         u32     aio_handle;
 996         u8      xor_mult[2];
 997         u8      reserved[2];
 998 };
 999
1000 /* for flags field of RAID map */
1001 #define RAID_MAP_ENCRYPTION_ENABLED     0x1
1002
1003 struct raid_map {
1004         __le32  structure_size;         /* size of entire structure in bytes */
1005         __le32  volume_blk_size;        /* bytes / block in the volume */
1006         __le64  volume_blk_cnt;         /* logical blocks on the volume */
1007         u8      phys_blk_shift;         /* shift factor to convert between */
1008                                         /* units of logical blocks and */
1009                                         /* physical disk blocks */
1010         u8      parity_rotation_shift;  /* shift factor to convert between */
1011                                         /* units of logical stripes and */
1012                                         /* physical stripes */
1013         __le16  strip_size;             /* blocks used on each disk / stripe */
1014         __le64  disk_starting_blk;      /* first disk block used in volume */
1015         __le64  disk_blk_cnt;           /* disk blocks used by volume / disk */
1016         __le16  data_disks_per_row;     /* data disk entries / row in the map */
1017         __le16  metadata_disks_per_row; /* mirror/parity disk entries / row */
1018                                         /* in the map */
1019         __le16  row_cnt;                /* rows in each layout map */
1020         __le16  layout_map_count;       /* layout maps (1 map per */
1021                                         /* mirror parity group) */
1022         __le16  flags;
1023         __le16  data_encryption_key_index;
1024         u8      reserved[16];
1025         struct raid_map_disk_data disk_data[RAID_MAP_MAX_ENTRIES];
1026 };
1027
1028 #pragma pack()
1029
1030 struct pqi_scsi_dev_raid_map_data {
1031         bool    is_write;
1032         u8      raid_level;
1033         u32     map_index;
1034         u64     first_block;
1035         u64     last_block;
1036         u32     data_length;
1037         u32     block_cnt;
1038         u32     blocks_per_row;
1039         u64     first_row;
1040         u64     last_row;
1041         u32     first_row_offset;
1042         u32     last_row_offset;
1043         u32     first_column;
1044         u32     last_column;
1045         u64     r5or6_first_row;
1046         u64     r5or6_last_row;
1047         u32     r5or6_first_row_offset;
1048         u32     r5or6_last_row_offset;
1049         u32     r5or6_first_column;
1050         u32     r5or6_last_column;
1051         u16     data_disks_per_row;
1052         u32     total_disks_per_row;
1053         u16     layout_map_count;
1054         u32     stripesize;
1055         u16     strip_size;
1056         u32     first_group;
1057         u32     last_group;
1058         u32     map_row;
1059         u32     aio_handle;
1060         u64     disk_block;
1061         u32     disk_block_cnt;
1062         u8      cdb[16];
1063         u8      cdb_length;
1064
1065         /* RAID 1 specific */
1066 #define NUM_RAID1_MAP_ENTRIES   3
1067         u32     num_it_nexus_entries;
1068         u32     it_nexus[NUM_RAID1_MAP_ENTRIES];
1069
1070         /* RAID 5 / RAID 6 specific */
1071         u32     p_parity_it_nexus;      /* aio_handle */
1072         u32     q_parity_it_nexus;      /* aio_handle */
1073         u8      xor_mult;
1074         u64     row;
1075         u64     stripe_lba;
1076         u32     p_index;
1077         u32     q_index;
1078 };
1079
1080 #define RAID_CTLR_LUNID         "\0\0\0\0\0\0\0\0"
1081
1082 #define NUM_STREAMS_PER_LUN     8
1083
1084 struct pqi_stream_data {
1085         u64     next_lba;
1086         u32     last_accessed;
1087 };
1088
1089 struct pqi_scsi_dev {
1090         int     devtype;                /* as reported by INQUIRY commmand */
1091         u8      device_type;            /* as reported by */
1092                                         /* BMIC_IDENTIFY_PHYSICAL_DEVICE */
1093                                         /* only valid for devtype = TYPE_DISK */
1094         int     bus;
1095         int     target;
1096         int     lun;
1097         u8      scsi3addr[8];
1098         u8      wwid[16];
1099         u8      volume_id[16];
1100         u8      is_physical_device : 1;
1101         u8      is_external_raid_device : 1;
1102         u8      is_expander_smp_device : 1;
1103         u8      target_lun_valid : 1;
1104         u8      device_gone : 1;
1105         u8      new_device : 1;
1106         u8      keep_device : 1;
1107         u8      volume_offline : 1;
1108         u8      rescan : 1;
1109         u8      ignore_device : 1;
1110         bool    aio_enabled;            /* only valid for physical disks */
1111         bool    in_remove;
1112         bool    device_offline;
1113         u8      vendor[8];              /* bytes 8-15 of inquiry data */
1114         u8      model[16];              /* bytes 16-31 of inquiry data */
1115         u64     sas_address;
1116         u8      raid_level;
1117         u16     queue_depth;            /* max. queue_depth for this device */
1118         u16     advertised_queue_depth;
1119         u32     aio_handle;
1120         u8      volume_status;
1121         u8      active_path_index;
1122         u8      path_map;
1123         u8      bay;
1124         u8      box_index;
1125         u8      phys_box_on_bus;
1126         u8      phy_connected_dev_type;
1127         u8      box[8];
1128         u16     phys_connector[8];
1129         u8      phy_id;
1130         bool    raid_bypass_configured; /* RAID bypass configured */
1131         bool    raid_bypass_enabled;    /* RAID bypass enabled */
1132         u32     next_bypass_group;
1133         struct raid_map *raid_map;      /* RAID bypass map */
1134         u32     max_transfer_encrypted;
1135
1136         struct pqi_sas_port *sas_port;
1137         struct scsi_device *sdev;
1138
1139         struct list_head scsi_device_list_entry;
1140         struct list_head new_device_list_entry;
1141         struct list_head add_list_entry;
1142         struct list_head delete_list_entry;
1143
1144         struct pqi_stream_data stream_data[NUM_STREAMS_PER_LUN];
1145         atomic_t scsi_cmds_outstanding;
1146         atomic_t raid_bypass_cnt;
1147         u8      page_83_identifier[16];
1148 };
1149
1150 /* VPD inquiry pages */
1151 #define CISS_VPD_LV_DEVICE_GEOMETRY     0xc1    /* vendor-specific page */
1152 #define CISS_VPD_LV_BYPASS_STATUS       0xc2    /* vendor-specific page */
1153 #define CISS_VPD_LV_STATUS              0xc3    /* vendor-specific page */
1154
1155 #define VPD_PAGE        (1 << 8)
1156
1157 #pragma pack(1)
1158
1159 /* structure for CISS_VPD_LV_STATUS */
1160 struct ciss_vpd_logical_volume_status {
1161         u8      peripheral_info;
1162         u8      page_code;
1163         u8      reserved;
1164         u8      page_length;
1165         u8      volume_status;
1166         u8      reserved2[3];
1167         __be32  flags;
1168 };
1169
1170 #pragma pack()
1171
1172 /* constants for volume_status field of ciss_vpd_logical_volume_status */
1173 #define CISS_LV_OK                                      0
1174 #define CISS_LV_FAILED                                  1
1175 #define CISS_LV_NOT_CONFIGURED                          2
1176 #define CISS_LV_DEGRADED                                3
1177 #define CISS_LV_READY_FOR_RECOVERY                      4
1178 #define CISS_LV_UNDERGOING_RECOVERY                     5
1179 #define CISS_LV_WRONG_PHYSICAL_DRIVE_REPLACED           6
1180 #define CISS_LV_PHYSICAL_DRIVE_CONNECTION_PROBLEM       7
1181 #define CISS_LV_HARDWARE_OVERHEATING                    8
1182 #define CISS_LV_HARDWARE_HAS_OVERHEATED                 9
1183 #define CISS_LV_UNDERGOING_EXPANSION                    10
1184 #define CISS_LV_NOT_AVAILABLE                           11
1185 #define CISS_LV_QUEUED_FOR_EXPANSION                    12
1186 #define CISS_LV_DISABLED_SCSI_ID_CONFLICT               13
1187 #define CISS_LV_EJECTED                                 14
1188 #define CISS_LV_UNDERGOING_ERASE                        15
1189 /* state 16 not used */
1190 #define CISS_LV_READY_FOR_PREDICTIVE_SPARE_REBUILD      17
1191 #define CISS_LV_UNDERGOING_RPI                          18
1192 #define CISS_LV_PENDING_RPI                             19
1193 #define CISS_LV_ENCRYPTED_NO_KEY                        20
1194 /* state 21 not used */
1195 #define CISS_LV_UNDERGOING_ENCRYPTION                   22
1196 #define CISS_LV_UNDERGOING_ENCRYPTION_REKEYING          23
1197 #define CISS_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER   24
1198 #define CISS_LV_PENDING_ENCRYPTION                      25
1199 #define CISS_LV_PENDING_ENCRYPTION_REKEYING             26
1200 #define CISS_LV_NOT_SUPPORTED                           27
1201 #define CISS_LV_STATUS_UNAVAILABLE                      255
1202
1203 /* constants for flags field of ciss_vpd_logical_volume_status */
1204 #define CISS_LV_FLAGS_NO_HOST_IO        0x1     /* volume not available for */
1205                                                 /* host I/O */
1206
1207 /* for SAS hosts and SAS expanders */
1208 struct pqi_sas_node {
1209         struct device *parent_dev;
1210         struct list_head port_list_head;
1211 };
1212
1213 struct pqi_sas_port {
1214         struct list_head port_list_entry;
1215         u64     sas_address;
1216         struct pqi_scsi_dev *device;
1217         struct sas_port *port;
1218         int     next_phy_index;
1219         struct list_head phy_list_head;
1220         struct pqi_sas_node *parent_node;
1221         struct sas_rphy *rphy;
1222 };
1223
1224 struct pqi_sas_phy {
1225         struct list_head phy_list_entry;
1226         struct sas_phy *phy;
1227         struct pqi_sas_port *parent_port;
1228         bool    added_to_port;
1229 };
1230
1231 struct pqi_io_request {
1232         atomic_t        refcount;
1233         u16             index;
1234         void (*io_complete_callback)(struct pqi_io_request *io_request,
1235                 void *context);
1236         void            *context;
1237         u8              raid_bypass : 1;
1238         int             status;
1239         struct pqi_queue_group *queue_group;
1240         struct scsi_cmnd *scmd;
1241         void            *error_info;
1242         struct pqi_sg_descriptor *sg_chain_buffer;
1243         dma_addr_t      sg_chain_buffer_dma_handle;
1244         void            *iu;
1245         struct list_head request_list_entry;
1246 };
1247
1248 #define PQI_NUM_SUPPORTED_EVENTS        7
1249
1250 struct pqi_event {
1251         bool    pending;
1252         u8      event_type;
1253         u16     event_id;
1254         u32     additional_event_id;
1255 };
1256
1257 #define PQI_RESERVED_IO_SLOTS_LUN_RESET                 1
1258 #define PQI_RESERVED_IO_SLOTS_EVENT_ACK                 PQI_NUM_SUPPORTED_EVENTS
1259 #define PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS      3
1260 #define PQI_RESERVED_IO_SLOTS                           \
1261         (PQI_RESERVED_IO_SLOTS_LUN_RESET + PQI_RESERVED_IO_SLOTS_EVENT_ACK + \
1262         PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS)
1263
1264 #define PQI_CTRL_PRODUCT_ID_GEN1        0
1265 #define PQI_CTRL_PRODUCT_ID_GEN2        7
1266 #define PQI_CTRL_PRODUCT_REVISION_A     0
1267 #define PQI_CTRL_PRODUCT_REVISION_B     1
1268
1269 struct pqi_ctrl_info {
1270         unsigned int    ctrl_id;
1271         struct pci_dev  *pci_dev;
1272         char            firmware_version[32];
1273         char            serial_number[17];
1274         char            model[17];
1275         char            vendor[9];
1276         u8              product_id;
1277         u8              product_revision;
1278         void __iomem    *iomem_base;
1279         struct pqi_ctrl_registers __iomem *registers;
1280         struct pqi_device_registers __iomem *pqi_registers;
1281         u32             max_sg_entries;
1282         u32             config_table_offset;
1283         u32             config_table_length;
1284         u16             max_inbound_queues;
1285         u16             max_elements_per_iq;
1286         u16             max_iq_element_length;
1287         u16             max_outbound_queues;
1288         u16             max_elements_per_oq;
1289         u16             max_oq_element_length;
1290         u32             max_transfer_size;
1291         u32             max_outstanding_requests;
1292         u32             max_io_slots;
1293         unsigned int    scsi_ml_can_queue;
1294         unsigned short  sg_tablesize;
1295         unsigned int    max_sectors;
1296         u32             error_buffer_length;
1297         void            *error_buffer;
1298         dma_addr_t      error_buffer_dma_handle;
1299         size_t          sg_chain_buffer_length;
1300         unsigned int    num_queue_groups;
1301         u16             max_hw_queue_index;
1302         u16             num_elements_per_iq;
1303         u16             num_elements_per_oq;
1304         u16             max_inbound_iu_length_per_firmware;
1305         u16             max_inbound_iu_length;
1306         unsigned int    max_sg_per_iu;
1307         unsigned int    max_sg_per_r56_iu;
1308         void            *admin_queue_memory_base;
1309         u32             admin_queue_memory_length;
1310         dma_addr_t      admin_queue_memory_base_dma_handle;
1311         void            *queue_memory_base;
1312         u32             queue_memory_length;
1313         dma_addr_t      queue_memory_base_dma_handle;
1314         struct pqi_admin_queues admin_queues;
1315         struct pqi_queue_group queue_groups[PQI_MAX_QUEUE_GROUPS];
1316         struct pqi_event_queue event_queue;
1317         enum pqi_irq_mode irq_mode;
1318         int             max_msix_vectors;
1319         int             num_msix_vectors_enabled;
1320         int             num_msix_vectors_initialized;
1321         int             event_irq;
1322         struct Scsi_Host *scsi_host;
1323
1324         struct mutex    scan_mutex;
1325         struct mutex    lun_reset_mutex;
1326         bool            controller_online;
1327         bool            block_requests;
1328         bool            scan_blocked;
1329         u8              inbound_spanning_supported : 1;
1330         u8              outbound_spanning_supported : 1;
1331         u8              pqi_mode_enabled : 1;
1332         u8              pqi_reset_quiesce_supported : 1;
1333         u8              soft_reset_handshake_supported : 1;
1334         u8              raid_iu_timeout_supported : 1;
1335         u8              tmf_iu_timeout_supported : 1;
1336         u8              unique_wwid_in_report_phys_lun_supported : 1;
1337         u8              firmware_triage_supported : 1;
1338         u8              rpl_extended_format_4_5_supported : 1;
1339         u8              enable_r1_writes : 1;
1340         u8              enable_r5_writes : 1;
1341         u8              enable_r6_writes : 1;
1342         u8              lv_drive_type_mix_valid : 1;
1343         u8              enable_stream_detection : 1;
1344
1345         u8              ciss_report_log_flags;
1346         u32             max_transfer_encrypted_sas_sata;
1347         u32             max_transfer_encrypted_nvme;
1348         u32             max_write_raid_5_6;
1349         u32             max_write_raid_1_10_2drive;
1350         u32             max_write_raid_1_10_3drive;
1351
1352         struct list_head scsi_device_list;
1353         spinlock_t      scsi_device_list_lock;
1354
1355         struct delayed_work rescan_work;
1356         struct delayed_work update_time_work;
1357
1358         struct pqi_sas_node *sas_host;
1359         u64             sas_address;
1360
1361         struct pqi_io_request *io_request_pool;
1362         u16             next_io_request_slot;
1363
1364         struct pqi_event events[PQI_NUM_SUPPORTED_EVENTS];
1365         struct work_struct event_work;
1366
1367         atomic_t        num_interrupts;
1368         int             previous_num_interrupts;
1369         u32             previous_heartbeat_count;
1370         __le32 __iomem  *heartbeat_counter;
1371         u8 __iomem      *soft_reset_status;
1372         struct timer_list heartbeat_timer;
1373         struct work_struct ctrl_offline_work;
1374
1375         struct semaphore sync_request_sem;
1376         atomic_t        num_busy_threads;
1377         atomic_t        num_blocked_threads;
1378         wait_queue_head_t block_requests_wait;
1379
1380         struct mutex    ofa_mutex;
1381         struct pqi_ofa_memory *pqi_ofa_mem_virt_addr;
1382         dma_addr_t      pqi_ofa_mem_dma_handle;
1383         void            **pqi_ofa_chunk_virt_addr;
1384         struct work_struct ofa_memory_alloc_work;
1385         struct work_struct ofa_quiesce_work;
1386         u32             ofa_bytes_requested;
1387         u16             ofa_cancel_reason;
1388 };
1389
1390 enum pqi_ctrl_mode {
1391         SIS_MODE = 0,
1392         PQI_MODE
1393 };
1394
1395 /*
1396  * assume worst case: SATA queue depth of 31 minus 4 internal firmware commands
1397  */
1398 #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH       27
1399
1400 /* CISS commands */
1401 #define CISS_READ               0xc0
1402 #define CISS_REPORT_LOG         0xc2    /* Report Logical LUNs */
1403 #define CISS_REPORT_PHYS        0xc3    /* Report Physical LUNs */
1404 #define CISS_GET_RAID_MAP       0xc8
1405
1406 /* BMIC commands */
1407 #define BMIC_IDENTIFY_CONTROLLER                0x11
1408 #define BMIC_IDENTIFY_PHYSICAL_DEVICE           0x15
1409 #define BMIC_READ                               0x26
1410 #define BMIC_WRITE                              0x27
1411 #define BMIC_SENSE_FEATURE                      0x61
1412 #define BMIC_SENSE_CONTROLLER_PARAMETERS        0x64
1413 #define BMIC_SENSE_SUBSYSTEM_INFORMATION        0x66
1414 #define BMIC_CSMI_PASSTHRU                      0x68
1415 #define BMIC_WRITE_HOST_WELLNESS                0xa5
1416 #define BMIC_FLUSH_CACHE                        0xc2
1417 #define BMIC_SET_DIAG_OPTIONS                   0xf4
1418 #define BMIC_SENSE_DIAG_OPTIONS                 0xf5
1419
1420 #define CSMI_CC_SAS_SMP_PASSTHRU                0x17
1421
1422 #define SA_FLUSH_CACHE                          0x1
1423
1424 #define MASKED_DEVICE(lunid)                    ((lunid)[3] & 0xc0)
1425 #define CISS_GET_LEVEL_2_BUS(lunid)             ((lunid)[7] & 0x3f)
1426 #define CISS_GET_LEVEL_2_TARGET(lunid)          ((lunid)[6])
1427 #define CISS_GET_DRIVE_NUMBER(lunid)            \
1428         (((CISS_GET_LEVEL_2_BUS((lunid)) - 1) << 8) + \
1429         CISS_GET_LEVEL_2_TARGET((lunid)))
1430
1431 #define LV_GET_DRIVE_TYPE_MIX(lunid)            ((lunid)[6])
1432
1433 #define LV_DRIVE_TYPE_MIX_UNKNOWN               0
1434 #define LV_DRIVE_TYPE_MIX_NO_RESTRICTION        1
1435 #define LV_DRIVE_TYPE_MIX_SAS_HDD_ONLY          2
1436 #define LV_DRIVE_TYPE_MIX_SATA_HDD_ONLY         3
1437 #define LV_DRIVE_TYPE_MIX_SAS_OR_SATA_SSD_ONLY  4
1438 #define LV_DRIVE_TYPE_MIX_SAS_SSD_ONLY          5
1439 #define LV_DRIVE_TYPE_MIX_SATA_SSD_ONLY         6
1440 #define LV_DRIVE_TYPE_MIX_SAS_ONLY              7
1441 #define LV_DRIVE_TYPE_MIX_SATA_ONLY             8
1442 #define LV_DRIVE_TYPE_MIX_NVME_ONLY             9
1443
1444 #define NO_TIMEOUT              ((unsigned long) -1)
1445
1446 #pragma pack(1)
1447
1448 struct bmic_identify_controller {
1449         u8      configured_logical_drive_count;
1450         __le32  configuration_signature;
1451         u8      firmware_version_short[4];
1452         u8      reserved[145];
1453         __le16  extended_logical_unit_count;
1454         u8      reserved1[34];
1455         __le16  firmware_build_number;
1456         u8      reserved2[8];
1457         u8      vendor_id[8];
1458         u8      product_id[16];
1459         u8      reserved3[62];
1460         __le32  extra_controller_flags;
1461         u8      reserved4[2];
1462         u8      controller_mode;
1463         u8      spare_part_number[32];
1464         u8      firmware_version_long[32];
1465 };
1466
1467 /* constants for extra_controller_flags field of bmic_identify_controller */
1468 #define BMIC_IDENTIFY_EXTRA_FLAGS_LONG_FW_VERSION_SUPPORTED     0x20000000
1469
1470 struct bmic_sense_subsystem_info {
1471         u8      reserved[44];
1472         u8      ctrl_serial_number[16];
1473 };
1474
1475 /* constants for device_type field */
1476 #define SA_DEVICE_TYPE_SATA             0x1
1477 #define SA_DEVICE_TYPE_SAS              0x2
1478 #define SA_DEVICE_TYPE_EXPANDER_SMP     0x5
1479 #define SA_DEVICE_TYPE_SES              0x6
1480 #define SA_DEVICE_TYPE_CONTROLLER       0x7
1481 #define SA_DEVICE_TYPE_NVME             0x9
1482
1483 struct bmic_identify_physical_device {
1484         u8      scsi_bus;               /* SCSI Bus number on controller */
1485         u8      scsi_id;                /* SCSI ID on this bus */
1486         __le16  block_size;             /* sector size in bytes */
1487         __le32  total_blocks;           /* number for sectors on drive */
1488         __le32  reserved_blocks;        /* controller reserved (RIS) */
1489         u8      model[40];              /* Physical Drive Model */
1490         u8      serial_number[40];      /* Drive Serial Number */
1491         u8      firmware_revision[8];   /* drive firmware revision */
1492         u8      scsi_inquiry_bits;      /* inquiry byte 7 bits */
1493         u8      compaq_drive_stamp;     /* 0 means drive not stamped */
1494         u8      last_failure_reason;
1495         u8      flags;
1496         u8      more_flags;
1497         u8      scsi_lun;               /* SCSI LUN for phys drive */
1498         u8      yet_more_flags;
1499         u8      even_more_flags;
1500         __le32  spi_speed_rules;
1501         u8      phys_connector[2];      /* connector number on controller */
1502         u8      phys_box_on_bus;        /* phys enclosure this drive resides */
1503         u8      phys_bay_in_box;        /* phys drv bay this drive resides */
1504         __le32  rpm;                    /* drive rotational speed in RPM */
1505         u8      device_type;            /* type of drive */
1506         u8      sata_version;           /* only valid when device_type = */
1507                                         /* SA_DEVICE_TYPE_SATA */
1508         __le64  big_total_block_count;
1509         __le64  ris_starting_lba;
1510         __le32  ris_size;
1511         u8      wwid[20];
1512         u8      controller_phy_map[32];
1513         __le16  phy_count;
1514         u8      phy_connected_dev_type[256];
1515         u8      phy_to_drive_bay_num[256];
1516         __le16  phy_to_attached_dev_index[256];
1517         u8      box_index;
1518         u8      reserved;
1519         __le16  extra_physical_drive_flags;
1520         u8      negotiated_link_rate[256];
1521         u8      phy_to_phy_map[256];
1522         u8      redundant_path_present_map;
1523         u8      redundant_path_failure_map;
1524         u8      active_path_number;
1525         __le16  alternate_paths_phys_connector[8];
1526         u8      alternate_paths_phys_box_on_port[8];
1527         u8      multi_lun_device_lun_count;
1528         u8      minimum_good_fw_revision[8];
1529         u8      unique_inquiry_bytes[20];
1530         u8      current_temperature_degrees;
1531         u8      temperature_threshold_degrees;
1532         u8      max_temperature_degrees;
1533         u8      logical_blocks_per_phys_block_exp;
1534         __le16  current_queue_depth_limit;
1535         u8      switch_name[10];
1536         __le16  switch_port;
1537         u8      alternate_paths_switch_name[40];
1538         u8      alternate_paths_switch_port[8];
1539         __le16  power_on_hours;
1540         __le16  percent_endurance_used;
1541         u8      drive_authentication;
1542         u8      smart_carrier_authentication;
1543         u8      smart_carrier_app_fw_version;
1544         u8      smart_carrier_bootloader_fw_version;
1545         u8      sanitize_flags;
1546         u8      encryption_key_flags;
1547         u8      encryption_key_name[64];
1548         __le32  misc_drive_flags;
1549         __le16  dek_index;
1550         __le16  hba_drive_encryption_flags;
1551         __le16  max_overwrite_time;
1552         __le16  max_block_erase_time;
1553         __le16  max_crypto_erase_time;
1554         u8      connector_info[5];
1555         u8      connector_name[8][8];
1556         u8      page_83_identifier[16];
1557         u8      maximum_link_rate[256];
1558         u8      negotiated_physical_link_rate[256];
1559         u8      box_connector_name[8];
1560         u8      padding_to_multiple_of_512[9];
1561 };
1562
1563 #define BMIC_SENSE_FEATURE_IO_PAGE              0x8
1564 #define BMIC_SENSE_FEATURE_IO_PAGE_AIO_SUBPAGE  0x2
1565
1566 struct bmic_sense_feature_buffer_header {
1567         u8      page_code;
1568         u8      subpage_code;
1569         __le16  buffer_length;
1570 };
1571
1572 struct bmic_sense_feature_page_header {
1573         u8      page_code;
1574         u8      subpage_code;
1575         __le16  page_length;
1576 };
1577
1578 struct bmic_sense_feature_io_page_aio_subpage {
1579         struct bmic_sense_feature_page_header header;
1580         u8      firmware_read_support;
1581         u8      driver_read_support;
1582         u8      firmware_write_support;
1583         u8      driver_write_support;
1584         __le16  max_transfer_encrypted_sas_sata;
1585         __le16  max_transfer_encrypted_nvme;
1586         __le16  max_write_raid_5_6;
1587         __le16  max_write_raid_1_10_2drive;
1588         __le16  max_write_raid_1_10_3drive;
1589 };
1590
1591 struct bmic_smp_request {
1592         u8      frame_type;
1593         u8      function;
1594         u8      allocated_response_length;
1595         u8      request_length;
1596         u8      additional_request_bytes[1016];
1597 };
1598
1599 struct  bmic_smp_response {
1600         u8      frame_type;
1601         u8      function;
1602         u8      function_result;
1603         u8      response_length;
1604         u8      additional_response_bytes[1016];
1605 };
1606
1607 struct bmic_csmi_ioctl_header {
1608         __le32  header_length;
1609         u8      signature[8];
1610         __le32  timeout;
1611         __le32  control_code;
1612         __le32  return_code;
1613         __le32  length;
1614 };
1615
1616 struct bmic_csmi_smp_passthru {
1617         u8      phy_identifier;
1618         u8      port_identifier;
1619         u8      connection_rate;
1620         u8      reserved;
1621         __be64  destination_sas_address;
1622         __le32  request_length;
1623         struct bmic_smp_request request;
1624         u8      connection_status;
1625         u8      reserved1[3];
1626         __le32  response_length;
1627         struct bmic_smp_response response;
1628 };
1629
1630 struct bmic_csmi_smp_passthru_buffer {
1631         struct bmic_csmi_ioctl_header ioctl_header;
1632         struct bmic_csmi_smp_passthru parameters;
1633 };
1634
1635 struct bmic_flush_cache {
1636         u8      disable_flag;
1637         u8      system_power_action;
1638         u8      ndu_flush;
1639         u8      shutdown_event;
1640         u8      reserved[28];
1641 };
1642
1643 /* for shutdown_event member of struct bmic_flush_cache */
1644 enum bmic_flush_cache_shutdown_event {
1645         NONE_CACHE_FLUSH_ONLY = 0,
1646         SHUTDOWN = 1,
1647         HIBERNATE = 2,
1648         SUSPEND = 3,
1649         RESTART = 4
1650 };
1651
1652 struct bmic_diag_options {
1653         __le32 options;
1654 };
1655
1656 #pragma pack()
1657
1658 static inline struct pqi_ctrl_info *shost_to_hba(struct Scsi_Host *shost)
1659 {
1660         void *hostdata = shost_priv(shost);
1661
1662         return *((struct pqi_ctrl_info **)hostdata);
1663 }
1664
1665 void pqi_sas_smp_handler(struct bsg_job *job, struct Scsi_Host *shost,
1666         struct sas_rphy *rphy);
1667
1668 int pqi_add_sas_host(struct Scsi_Host *shost, struct pqi_ctrl_info *ctrl_info);
1669 void pqi_delete_sas_host(struct pqi_ctrl_info *ctrl_info);
1670 int pqi_add_sas_device(struct pqi_sas_node *pqi_sas_node,
1671         struct pqi_scsi_dev *device);
1672 void pqi_remove_sas_device(struct pqi_scsi_dev *device);
1673 struct pqi_scsi_dev *pqi_find_device_by_sas_rphy(
1674         struct pqi_ctrl_info *ctrl_info, struct sas_rphy *rphy);
1675 void pqi_prep_for_scsi_done(struct scsi_cmnd *scmd);
1676 int pqi_csmi_smp_passthru(struct pqi_ctrl_info *ctrl_info,
1677         struct bmic_csmi_smp_passthru_buffer *buffer, size_t buffer_length,
1678         struct pqi_raid_error_info *error_info);
1679
1680 extern struct sas_function_template pqi_sas_transport_functions;
1681
1682 #endif /* _SMARTPQI_H */