1 // SPDX-License-Identifier: GPL-2.0-only
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
7 #include <linux/delay.h>
8 #include <linux/io-64-nonatomic-lo-hi.h>
10 #include <linux/ratelimit.h>
11 #include <linux/vmalloc.h>
12 #include <scsi/scsi_tcq.h>
14 #define MASK(n) ((1ULL<<(n))-1)
15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
16 ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
18 ((addr >> 25) & 0x3ff))
19 #define MS_WIN(addr) (addr & 0x0ffc0000)
20 #define QLA82XX_PCI_MN_2M (0)
21 #define QLA82XX_PCI_MS_2M (0x80000)
22 #define QLA82XX_PCI_OCM0_2M (0xc0000)
23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
24 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
25 #define BLOCK_PROTECT_BITS 0x0F
27 /* CRB window related */
28 #define CRB_BLK(off) ((off >> 20) & 0x3f)
29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30 #define CRB_WINDOW_2M (0x130060)
31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
32 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
35 #define CRB_INDIRECT_2M (0x1e0000UL)
37 #define MAX_CRB_XFORM 60
38 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
39 static int qla82xx_crb_table_initialized;
41 #define qla82xx_crb_addr_transform(name) \
42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
45 const int MD_MIU_TEST_AGT_RDDATA[] = {
46 0x410000A8, 0x410000AC,
47 0x410000B8, 0x410000BC
50 static void qla82xx_crb_addr_transform_setup(void)
52 qla82xx_crb_addr_transform(XDMA);
53 qla82xx_crb_addr_transform(TIMR);
54 qla82xx_crb_addr_transform(SRE);
55 qla82xx_crb_addr_transform(SQN3);
56 qla82xx_crb_addr_transform(SQN2);
57 qla82xx_crb_addr_transform(SQN1);
58 qla82xx_crb_addr_transform(SQN0);
59 qla82xx_crb_addr_transform(SQS3);
60 qla82xx_crb_addr_transform(SQS2);
61 qla82xx_crb_addr_transform(SQS1);
62 qla82xx_crb_addr_transform(SQS0);
63 qla82xx_crb_addr_transform(RPMX7);
64 qla82xx_crb_addr_transform(RPMX6);
65 qla82xx_crb_addr_transform(RPMX5);
66 qla82xx_crb_addr_transform(RPMX4);
67 qla82xx_crb_addr_transform(RPMX3);
68 qla82xx_crb_addr_transform(RPMX2);
69 qla82xx_crb_addr_transform(RPMX1);
70 qla82xx_crb_addr_transform(RPMX0);
71 qla82xx_crb_addr_transform(ROMUSB);
72 qla82xx_crb_addr_transform(SN);
73 qla82xx_crb_addr_transform(QMN);
74 qla82xx_crb_addr_transform(QMS);
75 qla82xx_crb_addr_transform(PGNI);
76 qla82xx_crb_addr_transform(PGND);
77 qla82xx_crb_addr_transform(PGN3);
78 qla82xx_crb_addr_transform(PGN2);
79 qla82xx_crb_addr_transform(PGN1);
80 qla82xx_crb_addr_transform(PGN0);
81 qla82xx_crb_addr_transform(PGSI);
82 qla82xx_crb_addr_transform(PGSD);
83 qla82xx_crb_addr_transform(PGS3);
84 qla82xx_crb_addr_transform(PGS2);
85 qla82xx_crb_addr_transform(PGS1);
86 qla82xx_crb_addr_transform(PGS0);
87 qla82xx_crb_addr_transform(PS);
88 qla82xx_crb_addr_transform(PH);
89 qla82xx_crb_addr_transform(NIU);
90 qla82xx_crb_addr_transform(I2Q);
91 qla82xx_crb_addr_transform(EG);
92 qla82xx_crb_addr_transform(MN);
93 qla82xx_crb_addr_transform(MS);
94 qla82xx_crb_addr_transform(CAS2);
95 qla82xx_crb_addr_transform(CAS1);
96 qla82xx_crb_addr_transform(CAS0);
97 qla82xx_crb_addr_transform(CAM);
98 qla82xx_crb_addr_transform(C2C1);
99 qla82xx_crb_addr_transform(C2C0);
100 qla82xx_crb_addr_transform(SMB);
101 qla82xx_crb_addr_transform(OCM0);
103 * Used only in P3 just define it for P2 also.
105 qla82xx_crb_addr_transform(I2C0);
107 qla82xx_crb_table_initialized = 1;
110 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
112 {{{1, 0x0100000, 0x0102000, 0x120000},
113 {1, 0x0110000, 0x0120000, 0x130000},
114 {1, 0x0120000, 0x0122000, 0x124000},
115 {1, 0x0130000, 0x0132000, 0x126000},
116 {1, 0x0140000, 0x0142000, 0x128000},
117 {1, 0x0150000, 0x0152000, 0x12a000},
118 {1, 0x0160000, 0x0170000, 0x110000},
119 {1, 0x0170000, 0x0172000, 0x12e000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {1, 0x01e0000, 0x01e0800, 0x122000},
127 {0, 0x0000000, 0x0000000, 0x000000} } } ,
128 {{{1, 0x0200000, 0x0210000, 0x180000} } },
130 {{{1, 0x0400000, 0x0401000, 0x169000} } },
131 {{{1, 0x0500000, 0x0510000, 0x140000} } },
132 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
133 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
134 {{{1, 0x0800000, 0x0802000, 0x170000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {1, 0x08f0000, 0x08f2000, 0x172000} } },
150 {{{1, 0x0900000, 0x0902000, 0x174000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {1, 0x09f0000, 0x09f2000, 0x176000} } },
166 {{{0, 0x0a00000, 0x0a02000, 0x178000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
182 {{{0, 0x0b00000, 0x0b02000, 0x17c000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {0, 0x0000000, 0x0000000, 0x000000},
194 {0, 0x0000000, 0x0000000, 0x000000},
195 {0, 0x0000000, 0x0000000, 0x000000},
196 {0, 0x0000000, 0x0000000, 0x000000},
197 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
198 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
199 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
200 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
201 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
202 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
203 {{{1, 0x1100000, 0x1101000, 0x160000} } },
204 {{{1, 0x1200000, 0x1201000, 0x161000} } },
205 {{{1, 0x1300000, 0x1301000, 0x162000} } },
206 {{{1, 0x1400000, 0x1401000, 0x163000} } },
207 {{{1, 0x1500000, 0x1501000, 0x165000} } },
208 {{{1, 0x1600000, 0x1601000, 0x166000} } },
215 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
216 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
217 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
219 {{{1, 0x2100000, 0x2102000, 0x120000},
220 {1, 0x2110000, 0x2120000, 0x130000},
221 {1, 0x2120000, 0x2122000, 0x124000},
222 {1, 0x2130000, 0x2132000, 0x126000},
223 {1, 0x2140000, 0x2142000, 0x128000},
224 {1, 0x2150000, 0x2152000, 0x12a000},
225 {1, 0x2160000, 0x2170000, 0x110000},
226 {1, 0x2170000, 0x2172000, 0x12e000},
227 {0, 0x0000000, 0x0000000, 0x000000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000},
230 {0, 0x0000000, 0x0000000, 0x000000},
231 {0, 0x0000000, 0x0000000, 0x000000},
232 {0, 0x0000000, 0x0000000, 0x000000},
233 {0, 0x0000000, 0x0000000, 0x000000},
234 {0, 0x0000000, 0x0000000, 0x000000} } },
235 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
241 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
242 {{{1, 0x2900000, 0x2901000, 0x16b000} } },
243 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
244 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
245 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
246 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
247 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
248 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
249 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
250 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
251 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
252 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
254 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
255 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
256 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
257 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
258 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
259 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
262 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
263 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
264 {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
268 * top 12 bits of crb internal address (hub, agent)
270 static unsigned qla82xx_crb_hub_agt[64] = {
272 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
273 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
296 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
299 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
300 QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
302 QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
304 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
305 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
311 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
318 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
321 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
324 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
325 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
326 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
327 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
329 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
330 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
331 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
333 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
338 static char *q_dev_state[] = {
349 char *qdev_state(uint32_t dev_state)
351 return q_dev_state[dev_state];
355 * In: 'off_in' is offset from CRB space in 128M pci map
356 * Out: 'off_out' is 2M pci map addr
357 * side effect: lock crb window
360 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong off_in,
361 void __iomem **off_out)
364 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
366 ha->crb_win = CRB_HI(off_in);
367 writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase);
369 /* Read back value to make sure write has gone through before trying
372 win_read = rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase);
373 if (win_read != ha->crb_win) {
374 ql_dbg(ql_dbg_p3p, vha, 0xb000,
375 "%s: Written crbwin (0x%x) "
376 "!= Read crbwin (0x%x), off=0x%lx.\n",
377 __func__, ha->crb_win, win_read, off_in);
379 *off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
383 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong off_in,
384 void __iomem **off_out)
386 struct crb_128M_2M_sub_block_map *m;
388 if (off_in >= QLA82XX_CRB_MAX)
391 if (off_in >= QLA82XX_PCI_CAMQM && off_in < QLA82XX_PCI_CAMQM_2M_END) {
392 *off_out = (off_in - QLA82XX_PCI_CAMQM) +
393 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
397 if (off_in < QLA82XX_PCI_CRBSPACE)
400 off_in -= QLA82XX_PCI_CRBSPACE;
403 m = &crb_128M_2M_map[CRB_BLK(off_in)].sub_block[CRB_SUBBLK(off_in)];
405 if (m->valid && (m->start_128M <= off_in) && (m->end_128M > off_in)) {
406 *off_out = off_in + m->start_2M - m->start_128M + ha->nx_pcibase;
409 /* Not in direct map, use crb window */
410 *off_out = (void __iomem *)off_in;
414 #define CRB_WIN_LOCK_TIMEOUT 100000000
415 static int qla82xx_crb_win_lock(struct qla_hw_data *ha)
417 int done = 0, timeout = 0;
420 /* acquire semaphore3 from PCI HW block */
421 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
424 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
428 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
433 qla82xx_wr_32(struct qla_hw_data *ha, ulong off_in, u32 data)
436 unsigned long flags = 0;
439 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
445 write_lock_irqsave(&ha->hw_lock, flags);
447 qla82xx_crb_win_lock(ha);
448 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
451 writel(data, (void __iomem *)off);
454 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
456 write_unlock_irqrestore(&ha->hw_lock, flags);
463 qla82xx_rd_32(struct qla_hw_data *ha, ulong off_in)
466 unsigned long flags = 0;
470 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
476 write_lock_irqsave(&ha->hw_lock, flags);
478 qla82xx_crb_win_lock(ha);
479 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
481 data = rd_reg_dword(off);
484 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
486 write_unlock_irqrestore(&ha->hw_lock, flags);
493 * Context: task, might sleep
495 int qla82xx_idc_lock(struct qla_hw_data *ha)
497 const int delay_ms = 100, timeout_ms = 2000;
503 /* acquire semaphore5 from PCI HW block */
504 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
507 if (WARN_ON_ONCE(total >= timeout_ms))
517 void qla82xx_idc_unlock(struct qla_hw_data *ha)
519 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
523 * check memory access boundary.
524 * used by test agent. support ddr access only for now
527 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
528 unsigned long long addr, int size)
530 if (!addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
531 QLA82XX_ADDR_DDR_NET_MAX) ||
532 !addr_in_range(addr + size - 1, QLA82XX_ADDR_DDR_NET,
533 QLA82XX_ADDR_DDR_NET_MAX) ||
534 ((size != 1) && (size != 2) && (size != 4) && (size != 8)))
540 static int qla82xx_pci_set_window_warning_count;
543 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
547 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
549 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
550 QLA82XX_ADDR_DDR_NET_MAX)) {
551 /* DDR network side */
552 window = MN_WIN(addr);
553 ha->ddr_mn_window = window;
555 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
556 win_read = qla82xx_rd_32(ha,
557 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
558 if ((win_read << 17) != window) {
559 ql_dbg(ql_dbg_p3p, vha, 0xb003,
560 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n",
561 __func__, window, win_read);
563 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
564 } else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
565 QLA82XX_ADDR_OCM0_MAX)) {
568 if ((addr & 0x00ff800) == 0xff800) {
569 ql_log(ql_log_warn, vha, 0xb004,
570 "%s: QM access not handled.\n", __func__);
573 window = OCM_WIN(addr);
574 ha->ddr_mn_window = window;
576 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
577 win_read = qla82xx_rd_32(ha,
578 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
579 temp1 = ((window & 0x1FF) << 7) |
580 ((window & 0x0FFFE0000) >> 17);
581 if (win_read != temp1) {
582 ql_log(ql_log_warn, vha, 0xb005,
583 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n",
584 __func__, temp1, win_read);
586 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
588 } else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET,
589 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
590 /* QDR network side */
591 window = MS_WIN(addr);
592 ha->qdr_sn_window = window;
594 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window);
595 win_read = qla82xx_rd_32(ha,
596 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
597 if (win_read != window) {
598 ql_log(ql_log_warn, vha, 0xb006,
599 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n",
600 __func__, window, win_read);
602 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
605 * peg gdb frequently accesses memory that doesn't exist,
606 * this limits the chit chat so debugging isn't slowed down.
608 if ((qla82xx_pci_set_window_warning_count++ < 8) ||
609 (qla82xx_pci_set_window_warning_count%64 == 0)) {
610 ql_log(ql_log_warn, vha, 0xb007,
611 "%s: Warning:%s Unknown address range!.\n",
612 __func__, QLA2XXX_DRIVER_NAME);
619 /* check if address is in the same windows as the previous access */
620 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha,
621 unsigned long long addr)
624 unsigned long long qdr_max;
626 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
628 /* DDR network side */
629 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
630 QLA82XX_ADDR_DDR_NET_MAX))
632 else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
633 QLA82XX_ADDR_OCM0_MAX))
635 else if (addr_in_range(addr, QLA82XX_ADDR_OCM1,
636 QLA82XX_ADDR_OCM1_MAX))
638 else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) {
639 /* QDR network side */
640 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
641 if (ha->qdr_sn_window == window)
647 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
648 u64 off, void *data, int size)
651 void __iomem *addr = NULL;
654 uint8_t __iomem *mem_ptr = NULL;
655 unsigned long mem_base;
656 unsigned long mem_page;
657 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
659 write_lock_irqsave(&ha->hw_lock, flags);
662 * If attempting to access unknown address or straddle hw windows,
665 start = qla82xx_pci_set_window(ha, off);
666 if ((start == -1UL) ||
667 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
668 write_unlock_irqrestore(&ha->hw_lock, flags);
669 ql_log(ql_log_fatal, vha, 0xb008,
670 "%s out of bound pci memory "
671 "access, offset is 0x%llx.\n",
672 QLA2XXX_DRIVER_NAME, off);
676 write_unlock_irqrestore(&ha->hw_lock, flags);
677 mem_base = pci_resource_start(ha->pdev, 0);
678 mem_page = start & PAGE_MASK;
679 /* Map two pages whenever user tries to access addresses in two
682 if (mem_page != ((start + size - 1) & PAGE_MASK))
683 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
685 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
686 if (mem_ptr == NULL) {
691 addr += start & (PAGE_SIZE - 1);
692 write_lock_irqsave(&ha->hw_lock, flags);
696 *(u8 *)data = readb(addr);
699 *(u16 *)data = readw(addr);
702 *(u32 *)data = readl(addr);
705 *(u64 *)data = readq(addr);
711 write_unlock_irqrestore(&ha->hw_lock, flags);
719 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
720 u64 off, void *data, int size)
723 void __iomem *addr = NULL;
726 uint8_t __iomem *mem_ptr = NULL;
727 unsigned long mem_base;
728 unsigned long mem_page;
729 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
731 write_lock_irqsave(&ha->hw_lock, flags);
734 * If attempting to access unknown address or straddle hw windows,
737 start = qla82xx_pci_set_window(ha, off);
738 if ((start == -1UL) ||
739 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
740 write_unlock_irqrestore(&ha->hw_lock, flags);
741 ql_log(ql_log_fatal, vha, 0xb009,
742 "%s out of bound memory "
743 "access, offset is 0x%llx.\n",
744 QLA2XXX_DRIVER_NAME, off);
748 write_unlock_irqrestore(&ha->hw_lock, flags);
749 mem_base = pci_resource_start(ha->pdev, 0);
750 mem_page = start & PAGE_MASK;
751 /* Map two pages whenever user tries to access addresses in two
754 if (mem_page != ((start + size - 1) & PAGE_MASK))
755 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
757 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
762 addr += start & (PAGE_SIZE - 1);
763 write_lock_irqsave(&ha->hw_lock, flags);
767 writeb(*(u8 *)data, addr);
770 writew(*(u16 *)data, addr);
773 writel(*(u32 *)data, addr);
776 writeq(*(u64 *)data, addr);
782 write_unlock_irqrestore(&ha->hw_lock, flags);
788 #define MTU_FUDGE_FACTOR 100
790 qla82xx_decode_crb_addr(unsigned long addr)
793 unsigned long base_addr, offset, pci_base;
795 if (!qla82xx_crb_table_initialized)
796 qla82xx_crb_addr_transform_setup();
798 pci_base = ADDR_ERROR;
799 base_addr = addr & 0xfff00000;
800 offset = addr & 0x000fffff;
802 for (i = 0; i < MAX_CRB_XFORM; i++) {
803 if (crb_addr_xform[i] == base_addr) {
808 if (pci_base == ADDR_ERROR)
810 return pci_base + offset;
813 static long rom_max_timeout = 100;
814 static long qla82xx_rom_lock_timeout = 100;
817 qla82xx_rom_lock(struct qla_hw_data *ha)
819 int done = 0, timeout = 0;
820 uint32_t lock_owner = 0;
821 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
824 /* acquire semaphore2 from PCI HW block */
825 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
828 if (timeout >= qla82xx_rom_lock_timeout) {
829 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
830 ql_dbg(ql_dbg_p3p, vha, 0xb157,
831 "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d",
832 __func__, ha->portnum, lock_owner);
837 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum);
842 qla82xx_rom_unlock(struct qla_hw_data *ha)
844 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff);
845 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
849 qla82xx_wait_rom_busy(struct qla_hw_data *ha)
853 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
856 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
859 if (timeout >= rom_max_timeout) {
860 ql_dbg(ql_dbg_p3p, vha, 0xb00a,
861 "%s: Timeout reached waiting for rom busy.\n",
862 QLA2XXX_DRIVER_NAME);
870 qla82xx_wait_rom_done(struct qla_hw_data *ha)
874 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
877 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
880 if (timeout >= rom_max_timeout) {
881 ql_dbg(ql_dbg_p3p, vha, 0xb00b,
882 "%s: Timeout reached waiting for rom done.\n",
883 QLA2XXX_DRIVER_NAME);
891 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
893 uint32_t off_value, rval = 0;
895 wrt_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000);
897 /* Read back value to make sure write has gone through */
898 rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase);
899 off_value = (off & 0x0000FFFF);
902 wrt_reg_dword(off_value + CRB_INDIRECT_2M + ha->nx_pcibase,
905 rval = rd_reg_dword(off_value + CRB_INDIRECT_2M +
912 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
914 /* Dword reads to flash. */
915 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1);
916 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE +
917 (addr & 0x0000FFFF), 0, 0);
923 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
926 uint32_t lock_owner = 0;
927 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
929 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
934 if (loops >= 50000) {
935 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
936 ql_log(ql_log_fatal, vha, 0x00b9,
937 "Failed to acquire SEM2 lock, Lock Owner %u.\n",
941 ret = qla82xx_do_rom_fast_read(ha, addr, valp);
942 qla82xx_rom_unlock(ha);
947 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
949 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
951 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
952 qla82xx_wait_rom_busy(ha);
953 if (qla82xx_wait_rom_done(ha)) {
954 ql_log(ql_log_warn, vha, 0xb00c,
955 "Error waiting for rom done.\n");
958 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
963 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
967 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
969 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
970 for (i = 0; i < 50000; i++) {
971 ret = qla82xx_read_status_reg(ha, &val);
972 if (ret < 0 || (val & 1) == 0)
977 ql_log(ql_log_warn, vha, 0xb00d,
978 "Timeout reached waiting for write finish.\n");
983 qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
987 qla82xx_wait_rom_busy(ha);
988 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
989 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN);
990 qla82xx_wait_rom_busy(ha);
991 if (qla82xx_wait_rom_done(ha))
993 if (qla82xx_read_status_reg(ha, &val) != 0)
1001 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
1003 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1005 if (qla82xx_flash_set_write_enable(ha))
1007 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val);
1008 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1);
1009 if (qla82xx_wait_rom_done(ha)) {
1010 ql_log(ql_log_warn, vha, 0xb00e,
1011 "Error waiting for rom done.\n");
1014 return qla82xx_flash_wait_write_finish(ha);
1018 qla82xx_write_disable_flash(struct qla_hw_data *ha)
1020 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1022 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
1023 if (qla82xx_wait_rom_done(ha)) {
1024 ql_log(ql_log_warn, vha, 0xb00f,
1025 "Error waiting for rom done.\n");
1032 ql82xx_rom_lock_d(struct qla_hw_data *ha)
1035 uint32_t lock_owner = 0;
1036 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1038 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1043 if (loops >= 50000) {
1044 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
1045 ql_log(ql_log_warn, vha, 0xb010,
1046 "ROM lock failed, Lock Owner %u.\n", lock_owner);
1053 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
1057 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1059 ret = ql82xx_rom_lock_d(ha);
1061 ql_log(ql_log_warn, vha, 0xb011,
1062 "ROM lock failed.\n");
1066 ret = qla82xx_flash_set_write_enable(ha);
1070 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data);
1071 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr);
1072 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
1073 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP);
1074 qla82xx_wait_rom_busy(ha);
1075 if (qla82xx_wait_rom_done(ha)) {
1076 ql_log(ql_log_warn, vha, 0xb012,
1077 "Error waiting for rom done.\n");
1082 ret = qla82xx_flash_wait_write_finish(ha);
1085 qla82xx_rom_unlock(ha);
1089 /* This routine does CRB initialize sequence
1090 * to put the ISP into operational state
1093 qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
1097 struct crb_addr_pair *buf;
1100 struct qla_hw_data *ha = vha->hw;
1102 struct crb_addr_pair {
1107 /* Halt all the individual PEGs and other blocks of the ISP */
1108 qla82xx_rom_lock(ha);
1110 /* disable all I2Q */
1111 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
1112 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
1113 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
1114 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1115 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1116 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
1118 /* disable all niu interrupts */
1119 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1120 /* disable xge rx/tx */
1121 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1122 /* disable xg1 rx/tx */
1123 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
1124 /* disable sideband mac */
1125 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1126 /* disable ap0 mac */
1127 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1128 /* disable ap1 mac */
1129 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
1132 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1133 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1136 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1139 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1140 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1141 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1142 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1143 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1144 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1147 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1148 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1149 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1150 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1151 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1155 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
1156 /* don't reset CAM block on reset */
1157 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1159 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1160 qla82xx_rom_unlock(ha);
1162 /* Read the signature value from the flash.
1163 * Offset 0: Contain signature (0xcafecafe)
1164 * Offset 4: Offset and number of addr/value pairs
1165 * that present in CRB initialize sequence
1168 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1169 qla82xx_rom_fast_read(ha, 4, &n) != 0) {
1170 ql_log(ql_log_fatal, vha, 0x006e,
1171 "Error Reading crb_init area: n: %08x.\n", n);
1175 /* Offset in flash = lower 16 bits
1176 * Number of entries = upper 16 bits
1178 offset = n & 0xffffU;
1179 n = (n >> 16) & 0xffffU;
1181 /* number of addr/value pair should not exceed 1024 entries */
1183 ql_log(ql_log_fatal, vha, 0x0071,
1184 "Card flash not initialized:n=0x%x.\n", n);
1188 ql_log(ql_log_info, vha, 0x0072,
1189 "%d CRB init values found in ROM.\n", n);
1191 buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
1193 ql_log(ql_log_fatal, vha, 0x010c,
1194 "Unable to allocate memory.\n");
1198 for (i = 0; i < n; i++) {
1199 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1200 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) {
1209 for (i = 0; i < n; i++) {
1210 /* Translate internal CRB initialization
1211 * address to PCI bus address
1213 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1214 QLA82XX_PCI_CRBSPACE;
1215 /* Not all CRB addr/value pair to be written,
1216 * some of them are skipped
1219 /* skipping cold reboot MAGIC */
1220 if (off == QLA82XX_CAM_RAM(0x1fc))
1223 /* do not reset PCI */
1224 if (off == (ROMUSB_GLB + 0xbc))
1227 /* skip core clock, so that firmware can increase the clock */
1228 if (off == (ROMUSB_GLB + 0xc8))
1231 /* skip the function enable register */
1232 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1235 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1238 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1241 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1244 if (off == ADDR_ERROR) {
1245 ql_log(ql_log_fatal, vha, 0x0116,
1246 "Unknown addr: 0x%08lx.\n", buf[i].addr);
1250 qla82xx_wr_32(ha, off, buf[i].data);
1252 /* ISP requires much bigger delay to settle down,
1253 * else crb_window returns 0xffffffff
1255 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1258 /* ISP requires millisec delay between
1259 * successive CRB register updation
1266 /* Resetting the data and instruction cache */
1267 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1268 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1269 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1271 /* Clear all protocol processing engines */
1272 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1273 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1274 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1275 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1276 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1277 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1278 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1279 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1284 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
1285 u64 off, void *data, int size)
1287 int i, j, ret = 0, loop, sz[2], off0;
1288 int scale, shift_amount, startword;
1290 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1293 * If not MN, go check for MS or invalid.
1295 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1296 mem_crb = QLA82XX_CRB_QDR_NET;
1298 mem_crb = QLA82XX_CRB_DDR_NET;
1299 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1300 return qla82xx_pci_mem_write_direct(ha,
1305 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1306 sz[1] = size - sz[0];
1308 off8 = off & 0xfffffff0;
1309 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1312 startword = (off & 0xf)/8;
1314 for (i = 0; i < loop; i++) {
1315 if (qla82xx_pci_mem_read_2M(ha, off8 +
1316 (i << shift_amount), &word[i * scale], 8))
1322 tmpw = *((uint8_t *)data);
1325 tmpw = *((uint16_t *)data);
1328 tmpw = *((uint32_t *)data);
1332 tmpw = *((uint64_t *)data);
1337 word[startword] = tmpw;
1340 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1341 word[startword] |= tmpw << (off0 * 8);
1344 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1345 word[startword+1] |= tmpw >> (sz[0] * 8);
1348 for (i = 0; i < loop; i++) {
1349 temp = off8 + (i << shift_amount);
1350 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1352 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1353 temp = word[i * scale] & 0xffffffff;
1354 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1355 temp = (word[i * scale] >> 32) & 0xffffffff;
1356 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1357 temp = word[i*scale + 1] & 0xffffffff;
1358 qla82xx_wr_32(ha, mem_crb +
1359 MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
1360 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1361 qla82xx_wr_32(ha, mem_crb +
1362 MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
1364 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1365 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1366 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1367 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1369 for (j = 0; j < MAX_CTL_CHECK; j++) {
1370 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1371 if ((temp & MIU_TA_CTL_BUSY) == 0)
1375 if (j >= MAX_CTL_CHECK) {
1376 if (printk_ratelimit())
1377 dev_err(&ha->pdev->dev,
1378 "failed to write through agent.\n");
1388 qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
1392 long flashaddr = ha->flt_region_bootload << 2;
1393 long memaddr = BOOTLD_START;
1397 size = (IMAGE_START - BOOTLD_START) / 8;
1399 for (i = 0; i < size; i++) {
1400 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1401 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) {
1404 data = ((u64)high << 32) | low ;
1405 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1409 if (i % 0x1000 == 0)
1413 read_lock(&ha->hw_lock);
1414 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1415 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1416 read_unlock(&ha->hw_lock);
1421 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha,
1422 u64 off, void *data, int size)
1424 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1427 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1430 * If not MN, go check for MS or invalid.
1433 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1434 mem_crb = QLA82XX_CRB_QDR_NET;
1436 mem_crb = QLA82XX_CRB_DDR_NET;
1437 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1438 return qla82xx_pci_mem_read_direct(ha,
1442 off8 = off & 0xfffffff0;
1443 off0[0] = off & 0xf;
1444 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1446 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1448 sz[1] = size - sz[0];
1450 for (i = 0; i < loop; i++) {
1451 temp = off8 + (i << shift_amount);
1452 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1454 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1455 temp = MIU_TA_CTL_ENABLE;
1456 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1457 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1458 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1460 for (j = 0; j < MAX_CTL_CHECK; j++) {
1461 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1462 if ((temp & MIU_TA_CTL_BUSY) == 0)
1466 if (j >= MAX_CTL_CHECK) {
1467 if (printk_ratelimit())
1468 dev_err(&ha->pdev->dev,
1469 "failed to read through agent.\n");
1473 start = off0[i] >> 2;
1474 end = (off0[i] + sz[i] - 1) >> 2;
1475 for (k = start; k <= end; k++) {
1476 temp = qla82xx_rd_32(ha,
1477 mem_crb + MIU_TEST_AGT_RDDATA(k));
1478 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1482 if (j >= MAX_CTL_CHECK)
1485 if ((off0[0] & 7) == 0) {
1488 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1489 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1494 *(uint8_t *)data = val;
1497 *(uint16_t *)data = val;
1500 *(uint32_t *)data = val;
1503 *(uint64_t *)data = val;
1510 static struct qla82xx_uri_table_desc *
1511 qla82xx_get_table_desc(const u8 *unirom, int section)
1514 struct qla82xx_uri_table_desc *directory =
1515 (struct qla82xx_uri_table_desc *)&unirom[0];
1518 uint32_t entries = le32_to_cpu(directory->num_entries);
1520 for (i = 0; i < entries; i++) {
1521 offset = le32_to_cpu(directory->findex) +
1522 (i * le32_to_cpu(directory->entry_size));
1523 tab_type = get_unaligned_le32((u32 *)&unirom[offset] + 8);
1525 if (tab_type == section)
1526 return (struct qla82xx_uri_table_desc *)&unirom[offset];
1532 static struct qla82xx_uri_data_desc *
1533 qla82xx_get_data_desc(struct qla_hw_data *ha,
1534 u32 section, u32 idx_offset)
1536 const u8 *unirom = ha->hablob->fw->data;
1537 int idx = get_unaligned_le32((u32 *)&unirom[ha->file_prd_off] +
1539 struct qla82xx_uri_table_desc *tab_desc = NULL;
1542 tab_desc = qla82xx_get_table_desc(unirom, section);
1546 offset = le32_to_cpu(tab_desc->findex) +
1547 (le32_to_cpu(tab_desc->entry_size) * idx);
1549 return (struct qla82xx_uri_data_desc *)&unirom[offset];
1553 qla82xx_get_bootld_offset(struct qla_hw_data *ha)
1555 u32 offset = BOOTLD_START;
1556 struct qla82xx_uri_data_desc *uri_desc = NULL;
1558 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1559 uri_desc = qla82xx_get_data_desc(ha,
1560 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF);
1562 offset = le32_to_cpu(uri_desc->findex);
1565 return (u8 *)&ha->hablob->fw->data[offset];
1568 static u32 qla82xx_get_fw_size(struct qla_hw_data *ha)
1570 struct qla82xx_uri_data_desc *uri_desc = NULL;
1572 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1573 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1574 QLA82XX_URI_FIRMWARE_IDX_OFF);
1576 return le32_to_cpu(uri_desc->size);
1579 return get_unaligned_le32(&ha->hablob->fw->data[FW_SIZE_OFFSET]);
1583 qla82xx_get_fw_offs(struct qla_hw_data *ha)
1585 u32 offset = IMAGE_START;
1586 struct qla82xx_uri_data_desc *uri_desc = NULL;
1588 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1589 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1590 QLA82XX_URI_FIRMWARE_IDX_OFF);
1592 offset = le32_to_cpu(uri_desc->findex);
1595 return (u8 *)&ha->hablob->fw->data[offset];
1598 /* PCI related functions */
1599 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region)
1601 unsigned long val = 0;
1609 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
1610 val = control + QLA82XX_MSIX_TBL_SPACE;
1618 qla82xx_iospace_config(struct qla_hw_data *ha)
1622 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) {
1623 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c,
1624 "Failed to reserver selected regions.\n");
1625 goto iospace_error_exit;
1628 /* Use MMIO operations for all accesses. */
1629 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1630 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d,
1631 "Region #0 not an MMIO resource, aborting.\n");
1632 goto iospace_error_exit;
1635 len = pci_resource_len(ha->pdev, 0);
1636 ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len);
1637 if (!ha->nx_pcibase) {
1638 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e,
1639 "Cannot remap pcibase MMIO, aborting.\n");
1640 goto iospace_error_exit;
1643 /* Mapping of IO base pointer */
1644 if (IS_QLA8044(ha)) {
1645 ha->iobase = ha->nx_pcibase;
1646 } else if (IS_QLA82XX(ha)) {
1647 ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11);
1651 ha->nxdb_wr_ptr = ioremap((pci_resource_start(ha->pdev, 4) +
1652 (ha->pdev->devfn << 12)), 4);
1653 if (!ha->nxdb_wr_ptr) {
1654 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f,
1655 "Cannot remap MMIO, aborting.\n");
1656 goto iospace_error_exit;
1659 /* Mapping of IO base pointer,
1660 * door bell read and write pointer
1662 ha->nxdb_rd_ptr = ha->nx_pcibase + (512 * 1024) +
1663 (ha->pdev->devfn * 8);
1665 ha->nxdb_wr_ptr = (void __iomem *)(ha->pdev->devfn == 6 ?
1666 QLA82XX_CAMRAM_DB1 :
1667 QLA82XX_CAMRAM_DB2);
1670 ha->max_req_queues = ha->max_rsp_queues = 1;
1671 ha->msix_count = ha->max_rsp_queues + 1;
1672 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006,
1673 "nx_pci_base=%p iobase=%p "
1674 "max_req_queues=%d msix_count=%d.\n",
1675 ha->nx_pcibase, ha->iobase,
1676 ha->max_req_queues, ha->msix_count);
1677 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010,
1678 "nx_pci_base=%p iobase=%p "
1679 "max_req_queues=%d msix_count=%d.\n",
1680 ha->nx_pcibase, ha->iobase,
1681 ha->max_req_queues, ha->msix_count);
1688 /* GS related functions */
1690 /* Initialization related functions */
1693 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1696 * Returns 0 on success.
1699 qla82xx_pci_config(scsi_qla_host_t *vha)
1701 struct qla_hw_data *ha = vha->hw;
1704 pci_set_master(ha->pdev);
1705 ret = pci_set_mwi(ha->pdev);
1706 ha->chip_revision = ha->pdev->revision;
1707 ql_dbg(ql_dbg_init, vha, 0x0043,
1708 "Chip revision:%d; pci_set_mwi() returned %d.\n",
1709 ha->chip_revision, ret);
1714 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1717 * Returns 0 on success.
1720 qla82xx_reset_chip(scsi_qla_host_t *vha)
1722 struct qla_hw_data *ha = vha->hw;
1724 ha->isp_ops->disable_intrs(ha);
1729 void qla82xx_config_rings(struct scsi_qla_host *vha)
1731 struct qla_hw_data *ha = vha->hw;
1732 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1733 struct init_cb_81xx *icb;
1734 struct req_que *req = ha->req_q_map[0];
1735 struct rsp_que *rsp = ha->rsp_q_map[0];
1737 /* Setup ring parameters in initialization control block. */
1738 icb = (struct init_cb_81xx *)ha->init_cb;
1739 icb->request_q_outpointer = cpu_to_le16(0);
1740 icb->response_q_inpointer = cpu_to_le16(0);
1741 icb->request_q_length = cpu_to_le16(req->length);
1742 icb->response_q_length = cpu_to_le16(rsp->length);
1743 put_unaligned_le64(req->dma, &icb->request_q_address);
1744 put_unaligned_le64(rsp->dma, &icb->response_q_address);
1746 wrt_reg_dword(®->req_q_out[0], 0);
1747 wrt_reg_dword(®->rsp_q_in[0], 0);
1748 wrt_reg_dword(®->rsp_q_out[0], 0);
1752 qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
1755 u32 i, flashaddr, size;
1758 size = (IMAGE_START - BOOTLD_START) / 8;
1760 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha);
1761 flashaddr = BOOTLD_START;
1763 for (i = 0; i < size; i++) {
1764 data = cpu_to_le64(ptr64[i]);
1765 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1770 flashaddr = FLASH_ADDR_START;
1771 size = qla82xx_get_fw_size(ha) / 8;
1772 ptr64 = (u64 *)qla82xx_get_fw_offs(ha);
1774 for (i = 0; i < size; i++) {
1775 data = cpu_to_le64(ptr64[i]);
1777 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1783 /* Write a magic value to CAMRAM register
1784 * at a specified offset to indicate
1785 * that all data is written and
1786 * ready for firmware to initialize.
1788 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC);
1790 read_lock(&ha->hw_lock);
1791 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1792 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1793 read_unlock(&ha->hw_lock);
1798 qla82xx_set_product_offset(struct qla_hw_data *ha)
1800 struct qla82xx_uri_table_desc *ptab_desc = NULL;
1801 const uint8_t *unirom = ha->hablob->fw->data;
1804 uint32_t flags, file_chiprev, offset;
1805 uint8_t chiprev = ha->chip_revision;
1806 /* Hardcoding mn_present flag for P3P */
1810 ptab_desc = qla82xx_get_table_desc(unirom,
1811 QLA82XX_URI_DIR_SECT_PRODUCT_TBL);
1815 entries = le32_to_cpu(ptab_desc->num_entries);
1817 for (i = 0; i < entries; i++) {
1818 offset = le32_to_cpu(ptab_desc->findex) +
1819 (i * le32_to_cpu(ptab_desc->entry_size));
1820 flags = le32_to_cpu(*((__le32 *)&unirom[offset] +
1821 QLA82XX_URI_FLAGS_OFF));
1822 file_chiprev = le32_to_cpu(*((__le32 *)&unirom[offset] +
1823 QLA82XX_URI_CHIP_REV_OFF));
1825 flagbit = mn_present ? 1 : 2;
1827 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) {
1828 ha->file_prd_off = offset;
1836 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
1840 struct qla_hw_data *ha = vha->hw;
1841 const struct firmware *fw = ha->hablob->fw;
1843 ha->fw_type = fw_type;
1845 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1846 if (qla82xx_set_product_offset(ha))
1849 min_size = QLA82XX_URI_FW_MIN_SIZE;
1851 val = get_unaligned_le32(&fw->data[QLA82XX_FW_MAGIC_OFFSET]);
1852 if (val != QLA82XX_BDINFO_MAGIC)
1855 min_size = QLA82XX_FW_MIN_SIZE;
1858 if (fw->size < min_size)
1864 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
1868 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1871 read_lock(&ha->hw_lock);
1872 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE);
1873 read_unlock(&ha->hw_lock);
1876 case PHAN_INITIALIZE_COMPLETE:
1877 case PHAN_INITIALIZE_ACK:
1879 case PHAN_INITIALIZE_FAILED:
1884 ql_log(ql_log_info, vha, 0x00a8,
1885 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n",
1890 } while (--retries);
1892 ql_log(ql_log_fatal, vha, 0x00a9,
1893 "Cmd Peg initialization failed: 0x%x.\n", val);
1895 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1896 read_lock(&ha->hw_lock);
1897 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
1898 read_unlock(&ha->hw_lock);
1899 return QLA_FUNCTION_FAILED;
1903 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
1907 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1910 read_lock(&ha->hw_lock);
1911 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE);
1912 read_unlock(&ha->hw_lock);
1915 case PHAN_INITIALIZE_COMPLETE:
1916 case PHAN_INITIALIZE_ACK:
1918 case PHAN_INITIALIZE_FAILED:
1923 ql_log(ql_log_info, vha, 0x00ab,
1924 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n",
1929 } while (--retries);
1931 ql_log(ql_log_fatal, vha, 0x00ac,
1932 "Rcv Peg initialization failed: 0x%x.\n", val);
1933 read_lock(&ha->hw_lock);
1934 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED);
1935 read_unlock(&ha->hw_lock);
1936 return QLA_FUNCTION_FAILED;
1939 /* ISR related functions */
1940 static struct qla82xx_legacy_intr_set legacy_intr[] =
1941 QLA82XX_LEGACY_INTR_CONFIG;
1944 * qla82xx_mbx_completion() - Process mailbox command completions.
1945 * @ha: SCSI driver HA context
1946 * @mb0: Mailbox0 register
1949 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
1952 __le16 __iomem *wptr;
1953 struct qla_hw_data *ha = vha->hw;
1954 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1956 wptr = ®->mailbox_out[1];
1958 /* Load return mailbox registers. */
1959 ha->flags.mbox_int = 1;
1960 ha->mailbox_out[0] = mb0;
1962 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
1963 ha->mailbox_out[cnt] = rd_reg_word(wptr);
1968 ql_dbg(ql_dbg_async, vha, 0x5053,
1969 "MBX pointer ERROR.\n");
1973 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
1974 * @irq: interrupt number
1975 * @dev_id: SCSI driver HA context
1977 * Called by system whenever the host adapter generates an interrupt.
1979 * Returns handled flag.
1982 qla82xx_intr_handler(int irq, void *dev_id)
1984 scsi_qla_host_t *vha;
1985 struct qla_hw_data *ha;
1986 struct rsp_que *rsp;
1987 struct device_reg_82xx __iomem *reg;
1988 int status = 0, status1 = 0;
1989 unsigned long flags;
1994 rsp = (struct rsp_que *) dev_id;
1996 ql_log(ql_log_info, NULL, 0xb053,
1997 "%s: NULL response queue pointer.\n", __func__);
2002 if (!ha->flags.msi_enabled) {
2003 status = qla82xx_rd_32(ha, ISR_INT_VECTOR);
2004 if (!(status & ha->nx_legacy_intr.int_vec_bit))
2007 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG);
2008 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1))
2012 /* clear the interrupt */
2013 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
2015 /* read twice to ensure write is flushed */
2016 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2017 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2019 reg = &ha->iobase->isp82;
2021 spin_lock_irqsave(&ha->hardware_lock, flags);
2022 vha = pci_get_drvdata(ha->pdev);
2023 for (iter = 1; iter--; ) {
2025 if (rd_reg_dword(®->host_int)) {
2026 stat = rd_reg_dword(®->host_status);
2028 switch (stat & 0xff) {
2033 qla82xx_mbx_completion(vha, MSW(stat));
2034 status |= MBX_INTERRUPT;
2038 mb[1] = rd_reg_word(®->mailbox_out[1]);
2039 mb[2] = rd_reg_word(®->mailbox_out[2]);
2040 mb[3] = rd_reg_word(®->mailbox_out[3]);
2041 qla2x00_async_event(vha, rsp, mb);
2044 qla24xx_process_response_queue(vha, rsp);
2047 ql_dbg(ql_dbg_async, vha, 0x5054,
2048 "Unrecognized interrupt type (%d).\n",
2053 wrt_reg_dword(®->host_int, 0);
2056 qla2x00_handle_mbx_completion(ha, status);
2057 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2059 if (!ha->flags.msi_enabled)
2060 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2066 qla82xx_msix_default(int irq, void *dev_id)
2068 scsi_qla_host_t *vha;
2069 struct qla_hw_data *ha;
2070 struct rsp_que *rsp;
2071 struct device_reg_82xx __iomem *reg;
2073 unsigned long flags;
2075 uint32_t host_int = 0;
2078 rsp = (struct rsp_que *) dev_id;
2081 "%s(): NULL response queue pointer.\n", __func__);
2086 reg = &ha->iobase->isp82;
2088 spin_lock_irqsave(&ha->hardware_lock, flags);
2089 vha = pci_get_drvdata(ha->pdev);
2091 host_int = rd_reg_dword(®->host_int);
2092 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2095 stat = rd_reg_dword(®->host_status);
2097 switch (stat & 0xff) {
2102 qla82xx_mbx_completion(vha, MSW(stat));
2103 status |= MBX_INTERRUPT;
2107 mb[1] = rd_reg_word(®->mailbox_out[1]);
2108 mb[2] = rd_reg_word(®->mailbox_out[2]);
2109 mb[3] = rd_reg_word(®->mailbox_out[3]);
2110 qla2x00_async_event(vha, rsp, mb);
2113 qla24xx_process_response_queue(vha, rsp);
2116 ql_dbg(ql_dbg_async, vha, 0x5041,
2117 "Unrecognized interrupt type (%d).\n",
2122 wrt_reg_dword(®->host_int, 0);
2125 qla2x00_handle_mbx_completion(ha, status);
2126 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2132 qla82xx_msix_rsp_q(int irq, void *dev_id)
2134 scsi_qla_host_t *vha;
2135 struct qla_hw_data *ha;
2136 struct rsp_que *rsp;
2137 struct device_reg_82xx __iomem *reg;
2138 unsigned long flags;
2139 uint32_t host_int = 0;
2141 rsp = (struct rsp_que *) dev_id;
2144 "%s(): NULL response queue pointer.\n", __func__);
2149 reg = &ha->iobase->isp82;
2150 spin_lock_irqsave(&ha->hardware_lock, flags);
2151 vha = pci_get_drvdata(ha->pdev);
2152 host_int = rd_reg_dword(®->host_int);
2153 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2155 qla24xx_process_response_queue(vha, rsp);
2156 wrt_reg_dword(®->host_int, 0);
2158 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2163 qla82xx_poll(int irq, void *dev_id)
2165 scsi_qla_host_t *vha;
2166 struct qla_hw_data *ha;
2167 struct rsp_que *rsp;
2168 struct device_reg_82xx __iomem *reg;
2171 uint32_t host_int = 0;
2173 unsigned long flags;
2175 rsp = (struct rsp_que *) dev_id;
2178 "%s(): NULL response queue pointer.\n", __func__);
2183 reg = &ha->iobase->isp82;
2184 spin_lock_irqsave(&ha->hardware_lock, flags);
2185 vha = pci_get_drvdata(ha->pdev);
2187 host_int = rd_reg_dword(®->host_int);
2188 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2191 stat = rd_reg_dword(®->host_status);
2192 switch (stat & 0xff) {
2197 qla82xx_mbx_completion(vha, MSW(stat));
2198 status |= MBX_INTERRUPT;
2202 mb[1] = rd_reg_word(®->mailbox_out[1]);
2203 mb[2] = rd_reg_word(®->mailbox_out[2]);
2204 mb[3] = rd_reg_word(®->mailbox_out[3]);
2205 qla2x00_async_event(vha, rsp, mb);
2208 qla24xx_process_response_queue(vha, rsp);
2211 ql_dbg(ql_dbg_p3p, vha, 0xb013,
2212 "Unrecognized interrupt type (%d).\n",
2216 wrt_reg_dword(®->host_int, 0);
2219 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2223 qla82xx_enable_intrs(struct qla_hw_data *ha)
2225 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2227 qla82xx_mbx_intr_enable(vha);
2228 spin_lock_irq(&ha->hardware_lock);
2230 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0);
2232 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2233 spin_unlock_irq(&ha->hardware_lock);
2234 ha->interrupts_on = 1;
2238 qla82xx_disable_intrs(struct qla_hw_data *ha)
2240 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2242 if (ha->interrupts_on)
2243 qla82xx_mbx_intr_disable(vha);
2245 spin_lock_irq(&ha->hardware_lock);
2247 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1);
2249 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2250 spin_unlock_irq(&ha->hardware_lock);
2251 ha->interrupts_on = 0;
2254 void qla82xx_init_flags(struct qla_hw_data *ha)
2256 struct qla82xx_legacy_intr_set *nx_legacy_intr;
2258 /* ISP 8021 initializations */
2259 rwlock_init(&ha->hw_lock);
2260 ha->qdr_sn_window = -1;
2261 ha->ddr_mn_window = -1;
2262 ha->curr_window = 255;
2263 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2264 nx_legacy_intr = &legacy_intr[ha->portnum];
2265 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit;
2266 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg;
2267 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg;
2268 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg;
2272 qla82xx_set_idc_version(scsi_qla_host_t *vha)
2275 uint32_t drv_active;
2276 struct qla_hw_data *ha = vha->hw;
2278 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2279 if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) {
2280 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
2281 QLA82XX_IDC_VERSION);
2282 ql_log(ql_log_info, vha, 0xb082,
2283 "IDC version updated to %d\n", QLA82XX_IDC_VERSION);
2285 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION);
2286 if (idc_ver != QLA82XX_IDC_VERSION)
2287 ql_log(ql_log_info, vha, 0xb083,
2288 "qla2xxx driver IDC version %d is not compatible "
2289 "with IDC version %d of the other drivers\n",
2290 QLA82XX_IDC_VERSION, idc_ver);
2295 qla82xx_set_drv_active(scsi_qla_host_t *vha)
2297 uint32_t drv_active;
2298 struct qla_hw_data *ha = vha->hw;
2300 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2302 /* If reset value is all FF's, initialize DRV_ACTIVE */
2303 if (drv_active == 0xffffffff) {
2304 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE,
2305 QLA82XX_DRV_NOT_ACTIVE);
2306 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2308 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2309 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2313 qla82xx_clear_drv_active(struct qla_hw_data *ha)
2315 uint32_t drv_active;
2317 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2318 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2319 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2323 qla82xx_need_reset(struct qla_hw_data *ha)
2328 if (ha->flags.nic_core_reset_owner)
2331 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2332 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2338 qla82xx_set_rst_ready(struct qla_hw_data *ha)
2341 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2343 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2345 /* If reset value is all FF's, initialize DRV_STATE */
2346 if (drv_state == 0xffffffff) {
2347 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY);
2348 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2350 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2351 ql_dbg(ql_dbg_init, vha, 0x00bb,
2352 "drv_state = 0x%08x.\n", drv_state);
2353 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2357 qla82xx_clear_rst_ready(struct qla_hw_data *ha)
2361 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2362 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2363 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2367 qla82xx_set_qsnt_ready(struct qla_hw_data *ha)
2369 uint32_t qsnt_state;
2371 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2372 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2373 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2377 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha)
2379 struct qla_hw_data *ha = vha->hw;
2380 uint32_t qsnt_state;
2382 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2383 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2384 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2388 qla82xx_load_fw(scsi_qla_host_t *vha)
2391 struct fw_blob *blob;
2392 struct qla_hw_data *ha = vha->hw;
2394 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) {
2395 ql_log(ql_log_fatal, vha, 0x009f,
2396 "Error during CRB initialization.\n");
2397 return QLA_FUNCTION_FAILED;
2401 /* Bring QM and CAMRAM out of reset */
2402 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
2403 rst &= ~((1 << 28) | (1 << 24));
2404 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
2408 * 1) Operational firmware residing in flash.
2409 * 2) Firmware via request-firmware interface (.bin file).
2411 if (ql2xfwloadbin == 2)
2414 ql_log(ql_log_info, vha, 0x00a0,
2415 "Attempting to load firmware from flash.\n");
2417 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) {
2418 ql_log(ql_log_info, vha, 0x00a1,
2419 "Firmware loaded successfully from flash.\n");
2422 ql_log(ql_log_warn, vha, 0x0108,
2423 "Firmware load from flash failed.\n");
2427 ql_log(ql_log_info, vha, 0x00a2,
2428 "Attempting to load firmware from blob.\n");
2430 /* Load firmware blob. */
2431 blob = ha->hablob = qla2x00_request_firmware(vha);
2433 ql_log(ql_log_fatal, vha, 0x00a3,
2434 "Firmware image not present.\n");
2435 goto fw_load_failed;
2438 /* Validating firmware blob */
2439 if (qla82xx_validate_firmware_blob(vha,
2440 QLA82XX_FLASH_ROMIMAGE)) {
2441 /* Fallback to URI format */
2442 if (qla82xx_validate_firmware_blob(vha,
2443 QLA82XX_UNIFIED_ROMIMAGE)) {
2444 ql_log(ql_log_fatal, vha, 0x00a4,
2445 "No valid firmware image found.\n");
2446 return QLA_FUNCTION_FAILED;
2450 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) {
2451 ql_log(ql_log_info, vha, 0x00a5,
2452 "Firmware loaded successfully from binary blob.\n");
2456 ql_log(ql_log_fatal, vha, 0x00a6,
2457 "Firmware load failed for binary blob.\n");
2462 return QLA_FUNCTION_FAILED;
2466 qla82xx_start_firmware(scsi_qla_host_t *vha)
2469 struct qla_hw_data *ha = vha->hw;
2471 /* scrub dma mask expansion register */
2472 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE);
2474 /* Put both the PEG CMD and RCV PEG to default state
2475 * of 0 before resetting the hardware
2477 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
2478 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
2480 /* Overwrite stale initialization register values */
2481 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
2482 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
2484 if (qla82xx_load_fw(vha) != QLA_SUCCESS) {
2485 ql_log(ql_log_fatal, vha, 0x00a7,
2486 "Error trying to start fw.\n");
2487 return QLA_FUNCTION_FAILED;
2490 /* Handshake with the card before we register the devices. */
2491 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) {
2492 ql_log(ql_log_fatal, vha, 0x00aa,
2493 "Error during card handshake.\n");
2494 return QLA_FUNCTION_FAILED;
2497 /* Negotiated Link width */
2498 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
2499 ha->link_width = (lnk >> 4) & 0x3f;
2501 /* Synchronize with Receive peg */
2502 return qla82xx_check_rcvpeg_state(ha);
2506 qla82xx_read_flash_data(scsi_qla_host_t *vha, __le32 *dwptr, uint32_t faddr,
2511 struct qla_hw_data *ha = vha->hw;
2513 /* Dword reads to flash. */
2514 for (i = 0; i < length/4; i++, faddr += 4) {
2515 if (qla82xx_rom_fast_read(ha, faddr, &val)) {
2516 ql_log(ql_log_warn, vha, 0x0106,
2517 "Do ROM fast read failed.\n");
2520 dwptr[i] = cpu_to_le32(val);
2527 qla82xx_unprotect_flash(struct qla_hw_data *ha)
2531 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2533 ret = ql82xx_rom_lock_d(ha);
2535 ql_log(ql_log_warn, vha, 0xb014,
2536 "ROM Lock failed.\n");
2540 ret = qla82xx_read_status_reg(ha, &val);
2542 goto done_unprotect;
2544 val &= ~(BLOCK_PROTECT_BITS << 2);
2545 ret = qla82xx_write_status_reg(ha, val);
2547 val |= (BLOCK_PROTECT_BITS << 2);
2548 qla82xx_write_status_reg(ha, val);
2551 if (qla82xx_write_disable_flash(ha) != 0)
2552 ql_log(ql_log_warn, vha, 0xb015,
2553 "Write disable failed.\n");
2556 qla82xx_rom_unlock(ha);
2561 qla82xx_protect_flash(struct qla_hw_data *ha)
2565 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2567 ret = ql82xx_rom_lock_d(ha);
2569 ql_log(ql_log_warn, vha, 0xb016,
2570 "ROM Lock failed.\n");
2574 ret = qla82xx_read_status_reg(ha, &val);
2578 val |= (BLOCK_PROTECT_BITS << 2);
2579 /* LOCK all sectors */
2580 ret = qla82xx_write_status_reg(ha, val);
2582 ql_log(ql_log_warn, vha, 0xb017,
2583 "Write status register failed.\n");
2585 if (qla82xx_write_disable_flash(ha) != 0)
2586 ql_log(ql_log_warn, vha, 0xb018,
2587 "Write disable failed.\n");
2589 qla82xx_rom_unlock(ha);
2594 qla82xx_erase_sector(struct qla_hw_data *ha, int addr)
2597 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2599 ret = ql82xx_rom_lock_d(ha);
2601 ql_log(ql_log_warn, vha, 0xb019,
2602 "ROM Lock failed.\n");
2606 qla82xx_flash_set_write_enable(ha);
2607 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
2608 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
2609 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE);
2611 if (qla82xx_wait_rom_done(ha)) {
2612 ql_log(ql_log_warn, vha, 0xb01a,
2613 "Error waiting for rom done.\n");
2617 ret = qla82xx_flash_wait_write_finish(ha);
2619 qla82xx_rom_unlock(ha);
2624 * Address and length are byte address
2627 qla82xx_read_optrom_data(struct scsi_qla_host *vha, void *buf,
2628 uint32_t offset, uint32_t length)
2630 scsi_block_requests(vha->host);
2631 qla82xx_read_flash_data(vha, buf, offset, length);
2632 scsi_unblock_requests(vha->host);
2637 qla82xx_write_flash_data(struct scsi_qla_host *vha, __le32 *dwptr,
2638 uint32_t faddr, uint32_t dwords)
2643 dma_addr_t optrom_dma;
2644 void *optrom = NULL;
2646 struct qla_hw_data *ha = vha->hw;
2650 /* Prepare burst-capable write on supported ISPs. */
2651 if (page_mode && !(faddr & 0xfff) &&
2652 dwords > OPTROM_BURST_DWORDS) {
2653 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2654 &optrom_dma, GFP_KERNEL);
2656 ql_log(ql_log_warn, vha, 0xb01b,
2657 "Unable to allocate memory "
2658 "for optrom burst write (%x KB).\n",
2659 OPTROM_BURST_SIZE / 1024);
2663 rest_addr = ha->fdt_block_size - 1;
2665 ret = qla82xx_unprotect_flash(ha);
2667 ql_log(ql_log_warn, vha, 0xb01c,
2668 "Unable to unprotect flash for update.\n");
2672 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
2673 /* Are we at the beginning of a sector? */
2674 if ((faddr & rest_addr) == 0) {
2676 ret = qla82xx_erase_sector(ha, faddr);
2678 ql_log(ql_log_warn, vha, 0xb01d,
2679 "Unable to erase sector: address=%x.\n",
2685 /* Go with burst-write. */
2686 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
2687 /* Copy data to DMA'ble buffer. */
2688 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
2690 ret = qla2x00_load_ram(vha, optrom_dma,
2691 (ha->flash_data_off | faddr),
2692 OPTROM_BURST_DWORDS);
2693 if (ret != QLA_SUCCESS) {
2694 ql_log(ql_log_warn, vha, 0xb01e,
2695 "Unable to burst-write optrom segment "
2696 "(%x/%x/%llx).\n", ret,
2697 (ha->flash_data_off | faddr),
2698 (unsigned long long)optrom_dma);
2699 ql_log(ql_log_warn, vha, 0xb01f,
2700 "Reverting to slow-write.\n");
2702 dma_free_coherent(&ha->pdev->dev,
2703 OPTROM_BURST_SIZE, optrom, optrom_dma);
2706 liter += OPTROM_BURST_DWORDS - 1;
2707 faddr += OPTROM_BURST_DWORDS - 1;
2708 dwptr += OPTROM_BURST_DWORDS - 1;
2713 ret = qla82xx_write_flash_dword(ha, faddr,
2714 le32_to_cpu(*dwptr));
2716 ql_dbg(ql_dbg_p3p, vha, 0xb020,
2717 "Unable to program flash address=%x data=%x.\n",
2723 ret = qla82xx_protect_flash(ha);
2725 ql_log(ql_log_warn, vha, 0xb021,
2726 "Unable to protect flash after update.\n");
2729 dma_free_coherent(&ha->pdev->dev,
2730 OPTROM_BURST_SIZE, optrom, optrom_dma);
2735 qla82xx_write_optrom_data(struct scsi_qla_host *vha, void *buf,
2736 uint32_t offset, uint32_t length)
2741 scsi_block_requests(vha->host);
2742 rval = qla82xx_write_flash_data(vha, buf, offset, length >> 2);
2743 scsi_unblock_requests(vha->host);
2745 /* Convert return ISP82xx to generic */
2747 rval = QLA_FUNCTION_FAILED;
2754 qla82xx_start_iocbs(scsi_qla_host_t *vha)
2756 struct qla_hw_data *ha = vha->hw;
2757 struct req_que *req = ha->req_q_map[0];
2760 /* Adjust ring index. */
2762 if (req->ring_index == req->length) {
2763 req->ring_index = 0;
2764 req->ring_ptr = req->ring;
2768 dbval = 0x04 | (ha->portnum << 5);
2770 dbval = dbval | (req->id << 8) | (req->ring_index << 16);
2772 qla82xx_wr_32(ha, (unsigned long)ha->nxdb_wr_ptr, dbval);
2774 wrt_reg_dword(ha->nxdb_wr_ptr, dbval);
2776 while (rd_reg_dword(ha->nxdb_rd_ptr) != dbval) {
2777 wrt_reg_dword(ha->nxdb_wr_ptr, dbval);
2784 qla82xx_rom_lock_recovery(struct qla_hw_data *ha)
2786 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2787 uint32_t lock_owner = 0;
2789 if (qla82xx_rom_lock(ha)) {
2790 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
2791 /* Someone else is holding the lock. */
2792 ql_log(ql_log_info, vha, 0xb022,
2793 "Resetting rom_lock, Lock Owner %u.\n", lock_owner);
2796 * Either we got the lock, or someone
2797 * else died while holding it.
2798 * In either case, unlock.
2800 qla82xx_rom_unlock(ha);
2804 * qla82xx_device_bootstrap
2805 * Initialize device, set DEV_READY, start fw
2808 * IDC lock must be held upon entry
2815 qla82xx_device_bootstrap(scsi_qla_host_t *vha)
2817 int rval = QLA_SUCCESS;
2819 uint32_t old_count, count;
2820 struct qla_hw_data *ha = vha->hw;
2823 need_reset = qla82xx_need_reset(ha);
2826 /* We are trying to perform a recovery here. */
2827 if (ha->flags.isp82xx_fw_hung)
2828 qla82xx_rom_lock_recovery(ha);
2830 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2831 for (i = 0; i < 10; i++) {
2833 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2834 if (count != old_count) {
2839 qla82xx_rom_lock_recovery(ha);
2842 /* set to DEV_INITIALIZING */
2843 ql_log(ql_log_info, vha, 0x009e,
2844 "HW State: INITIALIZING.\n");
2845 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
2847 qla82xx_idc_unlock(ha);
2848 rval = qla82xx_start_firmware(vha);
2849 qla82xx_idc_lock(ha);
2851 if (rval != QLA_SUCCESS) {
2852 ql_log(ql_log_fatal, vha, 0x00ad,
2853 "HW State: FAILED.\n");
2854 qla82xx_clear_drv_active(ha);
2855 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED);
2860 ql_log(ql_log_info, vha, 0x00ae,
2861 "HW State: READY.\n");
2862 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
2868 * qla82xx_need_qsnt_handler
2869 * Code to start quiescence sequence
2872 * IDC lock must be held upon entry
2878 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha)
2880 struct qla_hw_data *ha = vha->hw;
2881 uint32_t dev_state, drv_state, drv_active;
2882 unsigned long reset_timeout;
2884 if (vha->flags.online) {
2885 /*Block any further I/O and wait for pending cmnds to complete*/
2886 qla2x00_quiesce_io(vha);
2889 /* Set the quiescence ready bit */
2890 qla82xx_set_qsnt_ready(ha);
2892 /*wait for 30 secs for other functions to ack */
2893 reset_timeout = jiffies + (30 * HZ);
2895 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2896 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2897 /* Its 2 that is written when qsnt is acked, moving one bit */
2898 drv_active = drv_active << 0x01;
2900 while (drv_state != drv_active) {
2902 if (time_after_eq(jiffies, reset_timeout)) {
2903 /* quiescence timeout, other functions didn't ack
2904 * changing the state to DEV_READY
2906 ql_log(ql_log_info, vha, 0xb023,
2907 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d "
2908 "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME,
2909 drv_active, drv_state);
2910 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2912 ql_log(ql_log_info, vha, 0xb025,
2913 "HW State: DEV_READY.\n");
2914 qla82xx_idc_unlock(ha);
2915 qla2x00_perform_loop_resync(vha);
2916 qla82xx_idc_lock(ha);
2918 qla82xx_clear_qsnt_ready(vha);
2922 qla82xx_idc_unlock(ha);
2924 qla82xx_idc_lock(ha);
2926 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2927 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2928 drv_active = drv_active << 0x01;
2930 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2931 /* everyone acked so set the state to DEV_QUIESCENCE */
2932 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
2933 ql_log(ql_log_info, vha, 0xb026,
2934 "HW State: DEV_QUIESCENT.\n");
2935 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT);
2940 * qla82xx_wait_for_state_change
2941 * Wait for device state to change from given current state
2944 * IDC lock must not be held upon entry
2947 * Changed device state.
2950 qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state)
2952 struct qla_hw_data *ha = vha->hw;
2957 qla82xx_idc_lock(ha);
2958 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2959 qla82xx_idc_unlock(ha);
2960 } while (dev_state == curr_state);
2966 qla8xxx_dev_failed_handler(scsi_qla_host_t *vha)
2968 struct qla_hw_data *ha = vha->hw;
2970 /* Disable the board */
2971 ql_log(ql_log_fatal, vha, 0x00b8,
2972 "Disabling the board.\n");
2974 if (IS_QLA82XX(ha)) {
2975 qla82xx_clear_drv_active(ha);
2976 qla82xx_idc_unlock(ha);
2977 } else if (IS_QLA8044(ha)) {
2978 qla8044_clear_drv_active(ha);
2979 qla8044_idc_unlock(ha);
2982 /* Set DEV_FAILED flag to disable timer */
2983 vha->device_flags |= DFLG_DEV_FAILED;
2984 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
2985 qla2x00_mark_all_devices_lost(vha);
2986 vha->flags.online = 0;
2987 vha->flags.init_done = 0;
2991 * qla82xx_need_reset_handler
2992 * Code to start reset sequence
2995 * IDC lock must be held upon entry
3002 qla82xx_need_reset_handler(scsi_qla_host_t *vha)
3004 uint32_t dev_state, drv_state, drv_active;
3005 uint32_t active_mask = 0;
3006 unsigned long reset_timeout;
3007 struct qla_hw_data *ha = vha->hw;
3008 struct req_que *req = ha->req_q_map[0];
3010 if (vha->flags.online) {
3011 qla82xx_idc_unlock(ha);
3012 qla2x00_abort_isp_cleanup(vha);
3013 ha->isp_ops->get_flash_version(vha, req->ring);
3014 ha->isp_ops->nvram_config(vha);
3015 qla82xx_idc_lock(ha);
3018 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3019 if (!ha->flags.nic_core_reset_owner) {
3020 ql_dbg(ql_dbg_p3p, vha, 0xb028,
3021 "reset_acknowledged by 0x%x\n", ha->portnum);
3022 qla82xx_set_rst_ready(ha);
3024 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
3025 drv_active &= active_mask;
3026 ql_dbg(ql_dbg_p3p, vha, 0xb029,
3027 "active_mask: 0x%08x\n", active_mask);
3030 /* wait for 10 seconds for reset ack from all functions */
3031 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
3033 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3034 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3035 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3037 ql_dbg(ql_dbg_p3p, vha, 0xb02a,
3038 "drv_state: 0x%08x, drv_active: 0x%08x, "
3039 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3040 drv_state, drv_active, dev_state, active_mask);
3042 while (drv_state != drv_active &&
3043 dev_state != QLA8XXX_DEV_INITIALIZING) {
3044 if (time_after_eq(jiffies, reset_timeout)) {
3045 ql_log(ql_log_warn, vha, 0x00b5,
3046 "Reset timeout.\n");
3049 qla82xx_idc_unlock(ha);
3051 qla82xx_idc_lock(ha);
3052 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3053 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3054 if (ha->flags.nic_core_reset_owner)
3055 drv_active &= active_mask;
3056 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3059 ql_dbg(ql_dbg_p3p, vha, 0xb02b,
3060 "drv_state: 0x%08x, drv_active: 0x%08x, "
3061 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3062 drv_state, drv_active, dev_state, active_mask);
3064 ql_log(ql_log_info, vha, 0x00b6,
3065 "Device state is 0x%x = %s.\n",
3067 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3069 /* Force to DEV_COLD unless someone else is starting a reset */
3070 if (dev_state != QLA8XXX_DEV_INITIALIZING &&
3071 dev_state != QLA8XXX_DEV_COLD) {
3072 ql_log(ql_log_info, vha, 0x00b7,
3073 "HW State: COLD/RE-INIT.\n");
3074 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
3075 qla82xx_set_rst_ready(ha);
3077 if (qla82xx_md_collect(vha))
3078 ql_log(ql_log_warn, vha, 0xb02c,
3079 "Minidump not collected.\n");
3081 ql_log(ql_log_warn, vha, 0xb04f,
3082 "Minidump disabled.\n");
3087 qla82xx_check_md_needed(scsi_qla_host_t *vha)
3089 struct qla_hw_data *ha = vha->hw;
3090 uint16_t fw_major_version, fw_minor_version, fw_subminor_version;
3091 int rval = QLA_SUCCESS;
3093 fw_major_version = ha->fw_major_version;
3094 fw_minor_version = ha->fw_minor_version;
3095 fw_subminor_version = ha->fw_subminor_version;
3097 rval = qla2x00_get_fw_version(vha);
3098 if (rval != QLA_SUCCESS)
3102 if (!ha->fw_dumped) {
3103 if ((fw_major_version != ha->fw_major_version ||
3104 fw_minor_version != ha->fw_minor_version ||
3105 fw_subminor_version != ha->fw_subminor_version) ||
3106 (ha->prev_minidump_failed)) {
3107 ql_dbg(ql_dbg_p3p, vha, 0xb02d,
3108 "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n",
3109 fw_major_version, fw_minor_version,
3110 fw_subminor_version,
3111 ha->fw_major_version,
3112 ha->fw_minor_version,
3113 ha->fw_subminor_version,
3114 ha->prev_minidump_failed);
3115 /* Release MiniDump resources */
3116 qla82xx_md_free(vha);
3117 /* ALlocate MiniDump resources */
3118 qla82xx_md_prep(vha);
3121 ql_log(ql_log_info, vha, 0xb02e,
3122 "Firmware dump available to retrieve\n");
3129 qla82xx_check_fw_alive(scsi_qla_host_t *vha)
3131 uint32_t fw_heartbeat_counter;
3134 fw_heartbeat_counter = qla82xx_rd_32(vha->hw,
3135 QLA82XX_PEG_ALIVE_COUNTER);
3136 /* all 0xff, assume AER/EEH in progress, ignore */
3137 if (fw_heartbeat_counter == 0xffffffff) {
3138 ql_dbg(ql_dbg_timer, vha, 0x6003,
3139 "FW heartbeat counter is 0xffffffff, "
3140 "returning status=%d.\n", status);
3143 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
3144 vha->seconds_since_last_heartbeat++;
3145 /* FW not alive after 2 seconds */
3146 if (vha->seconds_since_last_heartbeat == 2) {
3147 vha->seconds_since_last_heartbeat = 0;
3151 vha->seconds_since_last_heartbeat = 0;
3152 vha->fw_heartbeat_counter = fw_heartbeat_counter;
3154 ql_dbg(ql_dbg_timer, vha, 0x6004,
3155 "Returning status=%d.\n", status);
3160 * qla82xx_device_state_handler
3161 * Main state handler
3164 * IDC lock must be held upon entry
3171 qla82xx_device_state_handler(scsi_qla_host_t *vha)
3174 uint32_t old_dev_state;
3175 int rval = QLA_SUCCESS;
3176 unsigned long dev_init_timeout;
3177 struct qla_hw_data *ha = vha->hw;
3180 qla82xx_idc_lock(ha);
3181 if (!vha->flags.init_done) {
3182 qla82xx_set_drv_active(vha);
3183 qla82xx_set_idc_version(vha);
3186 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3187 old_dev_state = dev_state;
3188 ql_log(ql_log_info, vha, 0x009b,
3189 "Device state is 0x%x = %s.\n",
3191 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3193 /* wait for 30 seconds for device to go ready */
3194 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
3198 if (time_after_eq(jiffies, dev_init_timeout)) {
3199 ql_log(ql_log_fatal, vha, 0x009c,
3200 "Device init failed.\n");
3201 rval = QLA_FUNCTION_FAILED;
3204 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3205 if (old_dev_state != dev_state) {
3207 old_dev_state = dev_state;
3209 if (loopcount < 5) {
3210 ql_log(ql_log_info, vha, 0x009d,
3211 "Device state is 0x%x = %s.\n",
3213 dev_state < MAX_STATES ? qdev_state(dev_state) :
3217 switch (dev_state) {
3218 case QLA8XXX_DEV_READY:
3219 ha->flags.nic_core_reset_owner = 0;
3221 case QLA8XXX_DEV_COLD:
3222 rval = qla82xx_device_bootstrap(vha);
3224 case QLA8XXX_DEV_INITIALIZING:
3225 qla82xx_idc_unlock(ha);
3227 qla82xx_idc_lock(ha);
3229 case QLA8XXX_DEV_NEED_RESET:
3230 if (!ql2xdontresethba)
3231 qla82xx_need_reset_handler(vha);
3233 qla82xx_idc_unlock(ha);
3235 qla82xx_idc_lock(ha);
3237 dev_init_timeout = jiffies +
3238 (ha->fcoe_dev_init_timeout * HZ);
3240 case QLA8XXX_DEV_NEED_QUIESCENT:
3241 qla82xx_need_qsnt_handler(vha);
3242 /* Reset timeout value after quiescence handler */
3243 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout
3246 case QLA8XXX_DEV_QUIESCENT:
3247 /* Owner will exit and other will wait for the state
3250 if (ha->flags.quiesce_owner)
3253 qla82xx_idc_unlock(ha);
3255 qla82xx_idc_lock(ha);
3257 /* Reset timeout value after quiescence handler */
3258 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout
3261 case QLA8XXX_DEV_FAILED:
3262 qla8xxx_dev_failed_handler(vha);
3263 rval = QLA_FUNCTION_FAILED;
3266 qla82xx_idc_unlock(ha);
3268 qla82xx_idc_lock(ha);
3273 qla82xx_idc_unlock(ha);
3278 static int qla82xx_check_temp(scsi_qla_host_t *vha)
3280 uint32_t temp, temp_state, temp_val;
3281 struct qla_hw_data *ha = vha->hw;
3283 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE);
3284 temp_state = qla82xx_get_temp_state(temp);
3285 temp_val = qla82xx_get_temp_val(temp);
3287 if (temp_state == QLA82XX_TEMP_PANIC) {
3288 ql_log(ql_log_warn, vha, 0x600e,
3289 "Device temperature %d degrees C exceeds "
3290 " maximum allowed. Hardware has been shut down.\n",
3293 } else if (temp_state == QLA82XX_TEMP_WARN) {
3294 ql_log(ql_log_warn, vha, 0x600f,
3295 "Device temperature %d degrees C exceeds "
3296 "operating range. Immediate action needed.\n",
3302 int qla82xx_read_temperature(scsi_qla_host_t *vha)
3306 temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE);
3307 return qla82xx_get_temp_val(temp);
3310 void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha)
3312 struct qla_hw_data *ha = vha->hw;
3314 if (ha->flags.mbox_busy) {
3315 ha->flags.mbox_int = 1;
3316 ha->flags.mbox_busy = 0;
3317 ql_log(ql_log_warn, vha, 0x6010,
3318 "Doing premature completion of mbx command.\n");
3319 if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags))
3320 complete(&ha->mbx_intr_comp);
3324 void qla82xx_watchdog(scsi_qla_host_t *vha)
3326 uint32_t dev_state, halt_status;
3327 struct qla_hw_data *ha = vha->hw;
3329 /* don't poll if reset is going on */
3330 if (!ha->flags.nic_core_reset_hdlr_active) {
3331 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3332 if (qla82xx_check_temp(vha)) {
3333 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3334 ha->flags.isp82xx_fw_hung = 1;
3335 qla82xx_clear_pending_mbx(vha);
3336 } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
3337 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
3338 ql_log(ql_log_warn, vha, 0x6001,
3339 "Adapter reset needed.\n");
3340 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
3341 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
3342 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
3343 ql_log(ql_log_warn, vha, 0x6002,
3344 "Quiescent needed.\n");
3345 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
3346 } else if (dev_state == QLA8XXX_DEV_FAILED &&
3347 !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) &&
3348 vha->flags.online == 1) {
3349 ql_log(ql_log_warn, vha, 0xb055,
3350 "Adapter state is failed. Offlining.\n");
3351 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3352 ha->flags.isp82xx_fw_hung = 1;
3353 qla82xx_clear_pending_mbx(vha);
3355 if (qla82xx_check_fw_alive(vha)) {
3356 ql_dbg(ql_dbg_timer, vha, 0x6011,
3357 "disabling pause transmit on port 0 & 1.\n");
3358 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
3359 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1);
3360 halt_status = qla82xx_rd_32(ha,
3361 QLA82XX_PEG_HALT_STATUS1);
3362 ql_log(ql_log_info, vha, 0x6005,
3363 "dumping hw/fw registers:.\n "
3364 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n "
3365 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n "
3366 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n "
3367 " PEG_NET_4_PC: 0x%x.\n", halt_status,
3368 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2),
3370 QLA82XX_CRB_PEG_NET_0 + 0x3c),
3372 QLA82XX_CRB_PEG_NET_1 + 0x3c),
3374 QLA82XX_CRB_PEG_NET_2 + 0x3c),
3376 QLA82XX_CRB_PEG_NET_3 + 0x3c),
3378 QLA82XX_CRB_PEG_NET_4 + 0x3c));
3379 if (((halt_status & 0x1fffff00) >> 8) == 0x67)
3380 ql_log(ql_log_warn, vha, 0xb052,
3381 "Firmware aborted with "
3382 "error code 0x00006700. Device is "
3384 if (halt_status & HALT_STATUS_UNRECOVERABLE) {
3385 set_bit(ISP_UNRECOVERABLE,
3388 ql_log(ql_log_info, vha, 0x6006,
3389 "Detect abort needed.\n");
3390 set_bit(ISP_ABORT_NEEDED,
3393 ha->flags.isp82xx_fw_hung = 1;
3394 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n");
3395 qla82xx_clear_pending_mbx(vha);
3401 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
3404 struct qla_hw_data *ha = vha->hw;
3407 rval = qla82xx_device_state_handler(vha);
3408 else if (IS_QLA8044(ha)) {
3409 qla8044_idc_lock(ha);
3410 /* Decide the reset ownership */
3411 qla83xx_reset_ownership(vha);
3412 qla8044_idc_unlock(ha);
3413 rval = qla8044_device_state_handler(vha);
3419 qla82xx_set_reset_owner(scsi_qla_host_t *vha)
3421 struct qla_hw_data *ha = vha->hw;
3422 uint32_t dev_state = 0;
3425 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3426 else if (IS_QLA8044(ha))
3427 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
3429 if (dev_state == QLA8XXX_DEV_READY) {
3430 ql_log(ql_log_info, vha, 0xb02f,
3431 "HW State: NEED RESET\n");
3432 if (IS_QLA82XX(ha)) {
3433 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3434 QLA8XXX_DEV_NEED_RESET);
3435 ha->flags.nic_core_reset_owner = 1;
3436 ql_dbg(ql_dbg_p3p, vha, 0xb030,
3437 "reset_owner is 0x%x\n", ha->portnum);
3438 } else if (IS_QLA8044(ha))
3439 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
3440 QLA8XXX_DEV_NEED_RESET);
3442 ql_log(ql_log_info, vha, 0xb031,
3443 "Device state is 0x%x = %s.\n",
3445 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3450 * Resets ISP and aborts all outstanding commands.
3453 * ha = adapter block pointer.
3459 qla82xx_abort_isp(scsi_qla_host_t *vha)
3462 struct qla_hw_data *ha = vha->hw;
3464 if (vha->device_flags & DFLG_DEV_FAILED) {
3465 ql_log(ql_log_warn, vha, 0x8024,
3466 "Device in failed state, exiting.\n");
3469 ha->flags.nic_core_reset_hdlr_active = 1;
3471 qla82xx_idc_lock(ha);
3472 qla82xx_set_reset_owner(vha);
3473 qla82xx_idc_unlock(ha);
3476 rval = qla82xx_device_state_handler(vha);
3477 else if (IS_QLA8044(ha)) {
3478 qla8044_idc_lock(ha);
3479 /* Decide the reset ownership */
3480 qla83xx_reset_ownership(vha);
3481 qla8044_idc_unlock(ha);
3482 rval = qla8044_device_state_handler(vha);
3485 qla82xx_idc_lock(ha);
3486 qla82xx_clear_rst_ready(ha);
3487 qla82xx_idc_unlock(ha);
3489 if (rval == QLA_SUCCESS) {
3490 ha->flags.isp82xx_fw_hung = 0;
3491 ha->flags.nic_core_reset_hdlr_active = 0;
3492 qla82xx_restart_isp(vha);
3496 vha->flags.online = 1;
3497 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
3498 if (ha->isp_abort_cnt == 0) {
3499 ql_log(ql_log_warn, vha, 0x8027,
3500 "ISP error recover failed - board "
3503 * The next call disables the board
3506 ha->isp_ops->reset_adapter(vha);
3507 vha->flags.online = 0;
3508 clear_bit(ISP_ABORT_RETRY,
3511 } else { /* schedule another ISP abort */
3512 ha->isp_abort_cnt--;
3513 ql_log(ql_log_warn, vha, 0x8036,
3514 "ISP abort - retry remaining %d.\n",
3516 rval = QLA_FUNCTION_FAILED;
3519 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
3520 ql_dbg(ql_dbg_taskm, vha, 0x8029,
3521 "ISP error recovery - retrying (%d) more times.\n",
3523 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3524 rval = QLA_FUNCTION_FAILED;
3531 * qla82xx_fcoe_ctx_reset
3532 * Perform a quick reset and aborts all outstanding commands.
3533 * This will only perform an FCoE context reset and avoids a full blown
3537 * ha = adapter block pointer.
3538 * is_reset_path = flag for identifying the reset path.
3543 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha)
3545 int rval = QLA_FUNCTION_FAILED;
3547 if (vha->flags.online) {
3548 /* Abort all outstanding commands, so as to be requeued later */
3549 qla2x00_abort_isp_cleanup(vha);
3552 /* Stop currently executing firmware.
3553 * This will destroy existing FCoE context at the F/W end.
3555 qla2x00_try_to_stop_firmware(vha);
3557 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
3558 rval = qla82xx_restart_isp(vha);
3564 * qla2x00_wait_for_fcoe_ctx_reset
3565 * Wait till the FCoE context is reset.
3568 * Does context switching here.
3569 * Release SPIN_LOCK (if any) before calling this routine.
3572 * Success (fcoe_ctx reset is done) : 0
3573 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1
3575 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha)
3577 int status = QLA_FUNCTION_FAILED;
3578 unsigned long wait_reset;
3580 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
3581 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
3582 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
3583 && time_before(jiffies, wait_reset)) {
3585 set_current_state(TASK_UNINTERRUPTIBLE);
3586 schedule_timeout(HZ);
3588 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) &&
3589 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
3590 status = QLA_SUCCESS;
3594 ql_dbg(ql_dbg_p3p, vha, 0xb027,
3595 "%s: status=%d.\n", __func__, status);
3601 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha)
3603 int i, fw_state = 0;
3604 unsigned long flags;
3605 struct qla_hw_data *ha = vha->hw;
3607 /* Check if 82XX firmware is alive or not
3608 * We may have arrived here from NEED_RESET
3611 if (!ha->flags.isp82xx_fw_hung) {
3612 for (i = 0; i < 2; i++) {
3615 fw_state = qla82xx_check_fw_alive(vha);
3616 else if (IS_QLA8044(ha))
3617 fw_state = qla8044_check_fw_alive(vha);
3619 ha->flags.isp82xx_fw_hung = 1;
3620 qla82xx_clear_pending_mbx(vha);
3625 ql_dbg(ql_dbg_init, vha, 0x00b0,
3626 "Entered %s fw_hung=%d.\n",
3627 __func__, ha->flags.isp82xx_fw_hung);
3629 /* Abort all commands gracefully if fw NOT hung */
3630 if (!ha->flags.isp82xx_fw_hung) {
3633 struct req_que *req;
3635 spin_lock_irqsave(&ha->hardware_lock, flags);
3636 for (que = 0; que < ha->max_req_queues; que++) {
3637 req = ha->req_q_map[que];
3640 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
3641 sp = req->outstanding_cmds[cnt];
3643 if ((!sp->u.scmd.crc_ctx ||
3645 SRB_FCP_CMND_DMA_VALID)) &&
3646 !ha->flags.isp82xx_fw_hung) {
3647 spin_unlock_irqrestore(
3648 &ha->hardware_lock, flags);
3649 if (ha->isp_ops->abort_command(sp)) {
3650 ql_log(ql_log_info, vha,
3652 "mbx abort failed.\n");
3654 ql_log(ql_log_info, vha,
3656 "mbx abort success.\n");
3658 spin_lock_irqsave(&ha->hardware_lock, flags);
3663 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3665 /* Wait for pending cmds (physical and virtual) to complete */
3666 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0,
3667 WAIT_HOST) == QLA_SUCCESS) {
3668 ql_dbg(ql_dbg_init, vha, 0x00b3,
3670 "pending commands.\n");
3677 /* Minidump related functions */
3679 qla82xx_minidump_process_control(scsi_qla_host_t *vha,
3680 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3682 struct qla_hw_data *ha = vha->hw;
3683 struct qla82xx_md_entry_crb *crb_entry;
3684 uint32_t read_value, opcode, poll_time;
3685 uint32_t addr, index, crb_addr;
3686 unsigned long wtime;
3687 struct qla82xx_md_template_hdr *tmplt_hdr;
3688 uint32_t rval = QLA_SUCCESS;
3691 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
3692 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr;
3693 crb_addr = crb_entry->addr;
3695 for (i = 0; i < crb_entry->op_count; i++) {
3696 opcode = crb_entry->crb_ctrl.opcode;
3697 if (opcode & QLA82XX_DBG_OPCODE_WR) {
3698 qla82xx_md_rw_32(ha, crb_addr,
3699 crb_entry->value_1, 1);
3700 opcode &= ~QLA82XX_DBG_OPCODE_WR;
3703 if (opcode & QLA82XX_DBG_OPCODE_RW) {
3704 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3705 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3706 opcode &= ~QLA82XX_DBG_OPCODE_RW;
3709 if (opcode & QLA82XX_DBG_OPCODE_AND) {
3710 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3711 read_value &= crb_entry->value_2;
3712 opcode &= ~QLA82XX_DBG_OPCODE_AND;
3713 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3714 read_value |= crb_entry->value_3;
3715 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3717 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3720 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3721 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3722 read_value |= crb_entry->value_3;
3723 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3724 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3727 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
3728 poll_time = crb_entry->crb_strd.poll_timeout;
3729 wtime = jiffies + poll_time;
3730 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3733 if ((read_value & crb_entry->value_2)
3734 == crb_entry->value_1)
3736 else if (time_after_eq(jiffies, wtime)) {
3737 /* capturing dump failed */
3738 rval = QLA_FUNCTION_FAILED;
3741 read_value = qla82xx_md_rw_32(ha,
3744 opcode &= ~QLA82XX_DBG_OPCODE_POLL;
3747 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
3748 if (crb_entry->crb_strd.state_index_a) {
3749 index = crb_entry->crb_strd.state_index_a;
3750 addr = tmplt_hdr->saved_state_array[index];
3754 read_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3755 index = crb_entry->crb_ctrl.state_index_v;
3756 tmplt_hdr->saved_state_array[index] = read_value;
3757 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
3760 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
3761 if (crb_entry->crb_strd.state_index_a) {
3762 index = crb_entry->crb_strd.state_index_a;
3763 addr = tmplt_hdr->saved_state_array[index];
3767 if (crb_entry->crb_ctrl.state_index_v) {
3768 index = crb_entry->crb_ctrl.state_index_v;
3770 tmplt_hdr->saved_state_array[index];
3772 read_value = crb_entry->value_1;
3774 qla82xx_md_rw_32(ha, addr, read_value, 1);
3775 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
3778 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
3779 index = crb_entry->crb_ctrl.state_index_v;
3780 read_value = tmplt_hdr->saved_state_array[index];
3781 read_value <<= crb_entry->crb_ctrl.shl;
3782 read_value >>= crb_entry->crb_ctrl.shr;
3783 if (crb_entry->value_2)
3784 read_value &= crb_entry->value_2;
3785 read_value |= crb_entry->value_3;
3786 read_value += crb_entry->value_1;
3787 tmplt_hdr->saved_state_array[index] = read_value;
3788 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
3790 crb_addr += crb_entry->crb_strd.addr_stride;
3796 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha,
3797 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3799 struct qla_hw_data *ha = vha->hw;
3800 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3801 struct qla82xx_md_entry_rdocm *ocm_hdr;
3802 __le32 *data_ptr = *d_ptr;
3804 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr;
3805 r_addr = ocm_hdr->read_addr;
3806 r_stride = ocm_hdr->read_addr_stride;
3807 loop_cnt = ocm_hdr->op_count;
3809 for (i = 0; i < loop_cnt; i++) {
3810 r_value = rd_reg_dword(r_addr + ha->nx_pcibase);
3811 *data_ptr++ = cpu_to_le32(r_value);
3818 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha,
3819 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3821 struct qla_hw_data *ha = vha->hw;
3822 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
3823 struct qla82xx_md_entry_mux *mux_hdr;
3824 __le32 *data_ptr = *d_ptr;
3826 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr;
3827 r_addr = mux_hdr->read_addr;
3828 s_addr = mux_hdr->select_addr;
3829 s_stride = mux_hdr->select_value_stride;
3830 s_value = mux_hdr->select_value;
3831 loop_cnt = mux_hdr->op_count;
3833 for (i = 0; i < loop_cnt; i++) {
3834 qla82xx_md_rw_32(ha, s_addr, s_value, 1);
3835 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3836 *data_ptr++ = cpu_to_le32(s_value);
3837 *data_ptr++ = cpu_to_le32(r_value);
3838 s_value += s_stride;
3844 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha,
3845 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3847 struct qla_hw_data *ha = vha->hw;
3848 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3849 struct qla82xx_md_entry_crb *crb_hdr;
3850 __le32 *data_ptr = *d_ptr;
3852 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr;
3853 r_addr = crb_hdr->addr;
3854 r_stride = crb_hdr->crb_strd.addr_stride;
3855 loop_cnt = crb_hdr->op_count;
3857 for (i = 0; i < loop_cnt; i++) {
3858 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3859 *data_ptr++ = cpu_to_le32(r_addr);
3860 *data_ptr++ = cpu_to_le32(r_value);
3867 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha,
3868 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3870 struct qla_hw_data *ha = vha->hw;
3871 uint32_t addr, r_addr, c_addr, t_r_addr;
3872 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3873 unsigned long p_wait, w_time, p_mask;
3874 uint32_t c_value_w, c_value_r;
3875 struct qla82xx_md_entry_cache *cache_hdr;
3876 int rval = QLA_FUNCTION_FAILED;
3877 __le32 *data_ptr = *d_ptr;
3879 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3880 loop_count = cache_hdr->op_count;
3881 r_addr = cache_hdr->read_addr;
3882 c_addr = cache_hdr->control_addr;
3883 c_value_w = cache_hdr->cache_ctrl.write_value;
3885 t_r_addr = cache_hdr->tag_reg_addr;
3886 t_value = cache_hdr->addr_ctrl.init_tag_value;
3887 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3888 p_wait = cache_hdr->cache_ctrl.poll_wait;
3889 p_mask = cache_hdr->cache_ctrl.poll_mask;
3891 for (i = 0; i < loop_count; i++) {
3892 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3894 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3897 w_time = jiffies + p_wait;
3899 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0);
3900 if ((c_value_r & p_mask) == 0)
3902 else if (time_after_eq(jiffies, w_time)) {
3903 /* capturing dump failed */
3904 ql_dbg(ql_dbg_p3p, vha, 0xb032,
3905 "c_value_r: 0x%x, poll_mask: 0x%lx, "
3907 c_value_r, p_mask, w_time);
3914 for (k = 0; k < r_cnt; k++) {
3915 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3916 *data_ptr++ = cpu_to_le32(r_value);
3917 addr += cache_hdr->read_ctrl.read_addr_stride;
3919 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3926 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha,
3927 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3929 struct qla_hw_data *ha = vha->hw;
3930 uint32_t addr, r_addr, c_addr, t_r_addr;
3931 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3933 struct qla82xx_md_entry_cache *cache_hdr;
3934 __le32 *data_ptr = *d_ptr;
3936 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3937 loop_count = cache_hdr->op_count;
3938 r_addr = cache_hdr->read_addr;
3939 c_addr = cache_hdr->control_addr;
3940 c_value_w = cache_hdr->cache_ctrl.write_value;
3942 t_r_addr = cache_hdr->tag_reg_addr;
3943 t_value = cache_hdr->addr_ctrl.init_tag_value;
3944 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3946 for (i = 0; i < loop_count; i++) {
3947 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3948 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3950 for (k = 0; k < r_cnt; k++) {
3951 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3952 *data_ptr++ = cpu_to_le32(r_value);
3953 addr += cache_hdr->read_ctrl.read_addr_stride;
3955 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3961 qla82xx_minidump_process_queue(scsi_qla_host_t *vha,
3962 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3964 struct qla_hw_data *ha = vha->hw;
3965 uint32_t s_addr, r_addr;
3966 uint32_t r_stride, r_value, r_cnt, qid = 0;
3967 uint32_t i, k, loop_cnt;
3968 struct qla82xx_md_entry_queue *q_hdr;
3969 __le32 *data_ptr = *d_ptr;
3971 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr;
3972 s_addr = q_hdr->select_addr;
3973 r_cnt = q_hdr->rd_strd.read_addr_cnt;
3974 r_stride = q_hdr->rd_strd.read_addr_stride;
3975 loop_cnt = q_hdr->op_count;
3977 for (i = 0; i < loop_cnt; i++) {
3978 qla82xx_md_rw_32(ha, s_addr, qid, 1);
3979 r_addr = q_hdr->read_addr;
3980 for (k = 0; k < r_cnt; k++) {
3981 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3982 *data_ptr++ = cpu_to_le32(r_value);
3985 qid += q_hdr->q_strd.queue_id_stride;
3991 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha,
3992 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3994 struct qla_hw_data *ha = vha->hw;
3995 uint32_t r_addr, r_value;
3996 uint32_t i, loop_cnt;
3997 struct qla82xx_md_entry_rdrom *rom_hdr;
3998 __le32 *data_ptr = *d_ptr;
4000 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr;
4001 r_addr = rom_hdr->read_addr;
4002 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
4004 for (i = 0; i < loop_cnt; i++) {
4005 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW,
4006 (r_addr & 0xFFFF0000), 1);
4007 r_value = qla82xx_md_rw_32(ha,
4008 MD_DIRECT_ROM_READ_BASE +
4009 (r_addr & 0x0000FFFF), 0, 0);
4010 *data_ptr++ = cpu_to_le32(r_value);
4011 r_addr += sizeof(uint32_t);
4017 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha,
4018 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
4020 struct qla_hw_data *ha = vha->hw;
4021 uint32_t r_addr, r_value, r_data;
4022 uint32_t i, j, loop_cnt;
4023 struct qla82xx_md_entry_rdmem *m_hdr;
4024 unsigned long flags;
4025 int rval = QLA_FUNCTION_FAILED;
4026 __le32 *data_ptr = *d_ptr;
4028 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr;
4029 r_addr = m_hdr->read_addr;
4030 loop_cnt = m_hdr->read_data_size/16;
4033 ql_log(ql_log_warn, vha, 0xb033,
4034 "Read addr 0x%x not 16 bytes aligned\n", r_addr);
4038 if (m_hdr->read_data_size % 16) {
4039 ql_log(ql_log_warn, vha, 0xb034,
4040 "Read data[0x%x] not multiple of 16 bytes\n",
4041 m_hdr->read_data_size);
4045 ql_dbg(ql_dbg_p3p, vha, 0xb035,
4046 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
4047 __func__, r_addr, m_hdr->read_data_size, loop_cnt);
4049 write_lock_irqsave(&ha->hw_lock, flags);
4050 for (i = 0; i < loop_cnt; i++) {
4051 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1);
4053 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1);
4054 r_value = MIU_TA_CTL_ENABLE;
4055 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4056 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
4057 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4059 for (j = 0; j < MAX_CTL_CHECK; j++) {
4060 r_value = qla82xx_md_rw_32(ha,
4061 MD_MIU_TEST_AGT_CTRL, 0, 0);
4062 if ((r_value & MIU_TA_CTL_BUSY) == 0)
4066 if (j >= MAX_CTL_CHECK) {
4067 printk_ratelimited(KERN_ERR
4068 "failed to read through agent\n");
4069 write_unlock_irqrestore(&ha->hw_lock, flags);
4073 for (j = 0; j < 4; j++) {
4074 r_data = qla82xx_md_rw_32(ha,
4075 MD_MIU_TEST_AGT_RDDATA[j], 0, 0);
4076 *data_ptr++ = cpu_to_le32(r_data);
4080 write_unlock_irqrestore(&ha->hw_lock, flags);
4086 qla82xx_validate_template_chksum(scsi_qla_host_t *vha)
4088 struct qla_hw_data *ha = vha->hw;
4089 uint64_t chksum = 0;
4090 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr;
4091 int count = ha->md_template_size/sizeof(uint32_t);
4095 while (chksum >> 32)
4096 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32);
4101 qla82xx_mark_entry_skipped(scsi_qla_host_t *vha,
4102 qla82xx_md_entry_hdr_t *entry_hdr, int index)
4104 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
4105 ql_dbg(ql_dbg_p3p, vha, 0xb036,
4106 "Skipping entry[%d]: "
4107 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4108 index, entry_hdr->entry_type,
4109 entry_hdr->d_ctrl.entry_capture_mask);
4113 qla82xx_md_collect(scsi_qla_host_t *vha)
4115 struct qla_hw_data *ha = vha->hw;
4116 int no_entry_hdr = 0;
4117 qla82xx_md_entry_hdr_t *entry_hdr;
4118 struct qla82xx_md_template_hdr *tmplt_hdr;
4120 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0;
4121 int i = 0, rval = QLA_FUNCTION_FAILED;
4123 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4124 data_ptr = ha->md_dump;
4126 if (ha->fw_dumped) {
4127 ql_log(ql_log_warn, vha, 0xb037,
4128 "Firmware has been previously dumped (%p) "
4129 "-- ignoring request.\n", ha->fw_dump);
4133 ha->fw_dumped = false;
4135 if (!ha->md_tmplt_hdr || !ha->md_dump) {
4136 ql_log(ql_log_warn, vha, 0xb038,
4137 "Memory not allocated for minidump capture\n");
4141 if (ha->flags.isp82xx_no_md_cap) {
4142 ql_log(ql_log_warn, vha, 0xb054,
4143 "Forced reset from application, "
4144 "ignore minidump capture\n");
4145 ha->flags.isp82xx_no_md_cap = 0;
4149 if (qla82xx_validate_template_chksum(vha)) {
4150 ql_log(ql_log_info, vha, 0xb039,
4151 "Template checksum validation error\n");
4155 no_entry_hdr = tmplt_hdr->num_of_entries;
4156 ql_dbg(ql_dbg_p3p, vha, 0xb03a,
4157 "No of entry headers in Template: 0x%x\n", no_entry_hdr);
4159 ql_dbg(ql_dbg_p3p, vha, 0xb03b,
4160 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
4162 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
4164 /* Validate whether required debug level is set */
4165 if ((f_capture_mask & 0x3) != 0x3) {
4166 ql_log(ql_log_warn, vha, 0xb03c,
4167 "Minimum required capture mask[0x%x] level not set\n",
4171 tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
4173 tmplt_hdr->driver_info[0] = vha->host_no;
4174 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) |
4175 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) |
4176 QLA_DRIVER_BETA_VER;
4178 total_data_size = ha->md_dump_size;
4180 ql_dbg(ql_dbg_p3p, vha, 0xb03d,
4181 "Total minidump data_size 0x%x to be captured\n", total_data_size);
4183 /* Check whether template obtained is valid */
4184 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) {
4185 ql_log(ql_log_warn, vha, 0xb04e,
4186 "Bad template header entry type: 0x%x obtained\n",
4187 tmplt_hdr->entry_type);
4191 entry_hdr = (qla82xx_md_entry_hdr_t *)
4192 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
4194 /* Walk through the entry headers */
4195 for (i = 0; i < no_entry_hdr; i++) {
4197 if (data_collected > total_data_size) {
4198 ql_log(ql_log_warn, vha, 0xb03e,
4199 "More MiniDump data collected: [0x%x]\n",
4204 if (!(entry_hdr->d_ctrl.entry_capture_mask &
4206 entry_hdr->d_ctrl.driver_flags |=
4207 QLA82XX_DBG_SKIPPED_FLAG;
4208 ql_dbg(ql_dbg_p3p, vha, 0xb03f,
4209 "Skipping entry[%d]: "
4210 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4211 i, entry_hdr->entry_type,
4212 entry_hdr->d_ctrl.entry_capture_mask);
4213 goto skip_nxt_entry;
4216 ql_dbg(ql_dbg_p3p, vha, 0xb040,
4217 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n"
4218 "entry_type: 0x%x, capture_mask: 0x%x\n",
4219 __func__, i, data_ptr, entry_hdr,
4220 entry_hdr->entry_type,
4221 entry_hdr->d_ctrl.entry_capture_mask);
4223 ql_dbg(ql_dbg_p3p, vha, 0xb041,
4224 "Data collected: [0x%x], Dump size left:[0x%x]\n",
4225 data_collected, (ha->md_dump_size - data_collected));
4227 /* Decode the entry type and take
4228 * required action to capture debug data */
4229 switch (entry_hdr->entry_type) {
4231 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4234 rval = qla82xx_minidump_process_control(vha,
4235 entry_hdr, &data_ptr);
4236 if (rval != QLA_SUCCESS) {
4237 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4242 qla82xx_minidump_process_rdcrb(vha,
4243 entry_hdr, &data_ptr);
4246 rval = qla82xx_minidump_process_rdmem(vha,
4247 entry_hdr, &data_ptr);
4248 if (rval != QLA_SUCCESS) {
4249 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4255 qla82xx_minidump_process_rdrom(vha,
4256 entry_hdr, &data_ptr);
4262 rval = qla82xx_minidump_process_l2tag(vha,
4263 entry_hdr, &data_ptr);
4264 if (rval != QLA_SUCCESS) {
4265 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4271 qla82xx_minidump_process_l1cache(vha,
4272 entry_hdr, &data_ptr);
4275 qla82xx_minidump_process_rdocm(vha,
4276 entry_hdr, &data_ptr);
4279 qla82xx_minidump_process_rdmux(vha,
4280 entry_hdr, &data_ptr);
4283 qla82xx_minidump_process_queue(vha,
4284 entry_hdr, &data_ptr);
4288 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4292 ql_dbg(ql_dbg_p3p, vha, 0xb042,
4293 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr);
4295 data_collected = (uint8_t *)data_ptr -
4296 (uint8_t *)ha->md_dump;
4298 entry_hdr = (qla82xx_md_entry_hdr_t *)
4299 (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
4302 if (data_collected != total_data_size) {
4303 ql_dbg(ql_dbg_p3p, vha, 0xb043,
4304 "MiniDump data mismatch: Data collected: [0x%x],"
4305 "total_data_size:[0x%x]\n",
4306 data_collected, total_data_size);
4310 ql_log(ql_log_info, vha, 0xb044,
4311 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
4312 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
4313 ha->fw_dumped = true;
4314 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
4321 qla82xx_md_alloc(scsi_qla_host_t *vha)
4323 struct qla_hw_data *ha = vha->hw;
4325 struct qla82xx_md_template_hdr *tmplt_hdr;
4327 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4329 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) {
4330 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF;
4331 ql_log(ql_log_info, vha, 0xb045,
4332 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n",
4336 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) {
4337 if (i & ql2xmdcapmask)
4338 ha->md_dump_size += tmplt_hdr->capture_size_array[k];
4342 ql_log(ql_log_warn, vha, 0xb046,
4343 "Firmware dump previously allocated.\n");
4347 ha->md_dump = vmalloc(ha->md_dump_size);
4348 if (ha->md_dump == NULL) {
4349 ql_log(ql_log_warn, vha, 0xb047,
4350 "Unable to allocate memory for Minidump size "
4351 "(0x%x).\n", ha->md_dump_size);
4358 qla82xx_md_free(scsi_qla_host_t *vha)
4360 struct qla_hw_data *ha = vha->hw;
4362 /* Release the template header allocated */
4363 if (ha->md_tmplt_hdr) {
4364 ql_log(ql_log_info, vha, 0xb048,
4365 "Free MiniDump template: %p, size (%d KB)\n",
4366 ha->md_tmplt_hdr, ha->md_template_size / 1024);
4367 dma_free_coherent(&ha->pdev->dev, ha->md_template_size,
4368 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4369 ha->md_tmplt_hdr = NULL;
4372 /* Release the template data buffer allocated */
4374 ql_log(ql_log_info, vha, 0xb049,
4375 "Free MiniDump memory: %p, size (%d KB)\n",
4376 ha->md_dump, ha->md_dump_size / 1024);
4378 ha->md_dump_size = 0;
4384 qla82xx_md_prep(scsi_qla_host_t *vha)
4386 struct qla_hw_data *ha = vha->hw;
4389 /* Get Minidump template size */
4390 rval = qla82xx_md_get_template_size(vha);
4391 if (rval == QLA_SUCCESS) {
4392 ql_log(ql_log_info, vha, 0xb04a,
4393 "MiniDump Template size obtained (%d KB)\n",
4394 ha->md_template_size / 1024);
4396 /* Get Minidump template */
4398 rval = qla8044_md_get_template(vha);
4400 rval = qla82xx_md_get_template(vha);
4402 if (rval == QLA_SUCCESS) {
4403 ql_dbg(ql_dbg_p3p, vha, 0xb04b,
4404 "MiniDump Template obtained\n");
4406 /* Allocate memory for minidump */
4407 rval = qla82xx_md_alloc(vha);
4408 if (rval == QLA_SUCCESS)
4409 ql_log(ql_log_info, vha, 0xb04c,
4410 "MiniDump memory allocated (%d KB)\n",
4411 ha->md_dump_size / 1024);
4413 ql_log(ql_log_info, vha, 0xb04d,
4414 "Free MiniDump template: %p, size: (%d KB)\n",
4416 ha->md_template_size / 1024);
4417 dma_free_coherent(&ha->pdev->dev,
4418 ha->md_template_size,
4419 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4420 ha->md_tmplt_hdr = NULL;
4428 qla82xx_beacon_on(struct scsi_qla_host *vha)
4432 struct qla_hw_data *ha = vha->hw;
4434 qla82xx_idc_lock(ha);
4435 rval = qla82xx_mbx_beacon_ctl(vha, 1);
4438 ql_log(ql_log_warn, vha, 0xb050,
4439 "mbx set led config failed in %s\n", __func__);
4442 ha->beacon_blink_led = 1;
4444 qla82xx_idc_unlock(ha);
4449 qla82xx_beacon_off(struct scsi_qla_host *vha)
4453 struct qla_hw_data *ha = vha->hw;
4455 qla82xx_idc_lock(ha);
4456 rval = qla82xx_mbx_beacon_ctl(vha, 0);
4459 ql_log(ql_log_warn, vha, 0xb051,
4460 "mbx set led config failed in %s\n", __func__);
4463 ha->beacon_blink_led = 0;
4465 qla82xx_idc_unlock(ha);
4470 qla82xx_fw_dump(scsi_qla_host_t *vha)
4472 struct qla_hw_data *ha = vha->hw;
4474 if (!ha->allow_cna_fw_dump)
4477 scsi_block_requests(vha->host);
4478 ha->flags.isp82xx_no_md_cap = 1;
4479 qla82xx_idc_lock(ha);
4480 qla82xx_set_reset_owner(vha);
4481 qla82xx_idc_unlock(ha);
4482 qla2x00_wait_for_chip_reset(vha);
4483 scsi_unblock_requests(vha->host);