1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
9 #include <linux/kernel.h>
10 #include <linux/init.h>
11 #include <linux/types.h>
12 #include <linux/module.h>
13 #include <linux/list.h>
14 #include <linux/pci.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/completion.h>
22 #include <linux/interrupt.h>
23 #include <linux/workqueue.h>
24 #include <linux/firmware.h>
25 #include <linux/aer.h>
26 #include <linux/mutex.h>
27 #include <linux/btree.h>
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_transport_fc.h>
34 #include <scsi/scsi_bsg_fc.h>
36 #include <uapi/scsi/fc/fc_els.h>
38 /* Big endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */
45 /* Little endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */
57 #define QLA2XXX_DRIVER_NAME "qla2xxx"
58 #define QLA2XXX_APIDEV "ql2xapidev"
59 #define QLA2XXX_MANUFACTURER "QLogic Corporation"
62 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
63 * but that's fine as we don't look at the last 24 ones for
66 #define MAILBOX_REGISTER_COUNT_2100 8
67 #define MAILBOX_REGISTER_COUNT_2200 24
68 #define MAILBOX_REGISTER_COUNT 32
70 #define QLA2200A_RISC_ROM_VER 4
74 #include "qla_settings.h"
76 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR)
79 * Data bit definitions
97 #define BIT_16 0x10000
98 #define BIT_17 0x20000
99 #define BIT_18 0x40000
100 #define BIT_19 0x80000
101 #define BIT_20 0x100000
102 #define BIT_21 0x200000
103 #define BIT_22 0x400000
104 #define BIT_23 0x800000
105 #define BIT_24 0x1000000
106 #define BIT_25 0x2000000
107 #define BIT_26 0x4000000
108 #define BIT_27 0x8000000
109 #define BIT_28 0x10000000
110 #define BIT_29 0x20000000
111 #define BIT_30 0x40000000
112 #define BIT_31 0x80000000
114 #define LSB(x) ((uint8_t)(x))
115 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
117 #define LSW(x) ((uint16_t)(x))
118 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
120 #define LSD(x) ((uint32_t)((uint64_t)(x)))
121 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
123 static inline uint32_t make_handle(uint16_t x, uint16_t y)
125 return ((uint32_t)x << 16) | y;
132 static inline u8 rd_reg_byte(const volatile u8 __iomem *addr)
137 static inline u16 rd_reg_word(const volatile __le16 __iomem *addr)
142 static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr)
147 static inline u8 rd_reg_byte_relaxed(const volatile u8 __iomem *addr)
149 return readb_relaxed(addr);
152 static inline u16 rd_reg_word_relaxed(const volatile __le16 __iomem *addr)
154 return readw_relaxed(addr);
157 static inline u32 rd_reg_dword_relaxed(const volatile __le32 __iomem *addr)
159 return readl_relaxed(addr);
162 static inline void wrt_reg_byte(volatile u8 __iomem *addr, u8 data)
164 return writeb(data, addr);
167 static inline void wrt_reg_word(volatile __le16 __iomem *addr, u16 data)
169 return writew(data, addr);
172 static inline void wrt_reg_dword(volatile __le32 __iomem *addr, u32 data)
174 return writel(data, addr);
178 * ISP83XX specific remote register addresses
180 #define QLA83XX_LED_PORT0 0x00201320
181 #define QLA83XX_LED_PORT1 0x00201328
182 #define QLA83XX_IDC_DEV_STATE 0x22102384
183 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380
184 #define QLA83XX_IDC_MINOR_VERSION 0x22102398
185 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388
186 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c
187 #define QLA83XX_IDC_CONTROL 0x22102390
188 #define QLA83XX_IDC_AUDIT 0x22102394
189 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
190 #define QLA83XX_DRIVER_LOCKID 0x22102104
191 #define QLA83XX_DRIVER_LOCK 0x8111c028
192 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c
193 #define QLA83XX_FLASH_LOCKID 0x22102100
194 #define QLA83XX_FLASH_LOCK 0x8111c010
195 #define QLA83XX_FLASH_UNLOCK 0x8111c014
196 #define QLA83XX_DEV_PARTINFO1 0x221023e0
197 #define QLA83XX_DEV_PARTINFO2 0x221023e4
198 #define QLA83XX_FW_HEARTBEAT 0x221020b0
199 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8
200 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac
202 /* 83XX: Macros defining 8200 AEN Reason codes */
203 #define IDC_DEVICE_STATE_CHANGE BIT_0
204 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
205 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2
206 #define IDC_HEARTBEAT_FAILURE BIT_3
208 /* 83XX: Macros defining 8200 AEN Error-levels */
209 #define ERR_LEVEL_NON_FATAL 0x1
210 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2
211 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
213 /* 83XX: Macros for IDC Version */
214 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
215 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
217 /* 83XX: Macros for scheduling dpc tasks */
218 #define QLA83XX_NIC_CORE_RESET 0x1
219 #define QLA83XX_IDC_STATE_HANDLER 0x2
220 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
222 /* 83XX: Macros for defining IDC-Control bits */
223 #define QLA83XX_IDC_RESET_DISABLED BIT_0
224 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
226 /* 83XX: Macros for different timeouts */
227 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
228 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
229 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
231 /* 83XX: Macros for defining class in DEV-Partition Info register */
232 #define QLA83XX_CLASS_TYPE_NONE 0x0
233 #define QLA83XX_CLASS_TYPE_NIC 0x1
234 #define QLA83XX_CLASS_TYPE_FCOE 0x2
235 #define QLA83XX_CLASS_TYPE_ISCSI 0x3
237 /* 83XX: Macros for IDC Lock-Recovery stages */
238 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
241 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
243 /* 83XX: Macros for IDC Audit type */
244 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
245 * dev-state change to NEED-RESET
248 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
249 * reset-recovery completion is
252 /* ISP2031: Values for laser on/off */
253 #define PORT_0_2031 0x00201340
254 #define PORT_1_2031 0x00201350
255 #define LASER_ON_2031 0x01800100
256 #define LASER_OFF_2031 0x01800180
259 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
262 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
263 #define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr))
266 * Fibre Channel device definitions.
268 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
269 #define MAX_FIBRE_DEVICES_2100 512
270 #define MAX_FIBRE_DEVICES_2400 2048
271 #define MAX_FIBRE_DEVICES_LOOP 128
272 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
273 #define LOOPID_MAP_SIZE (ha->max_fibre_devices)
274 #define MAX_FIBRE_LUNS 0xFFFF
275 #define MAX_HOST_COUNT 16
278 * Host adapter default definitions.
280 #define MAX_BUSES 1 /* We only have one bus today */
282 #define MAX_LUNS MAX_FIBRE_LUNS
283 #define MAX_CMDS_PER_LUN 255
286 * Fibre Channel device definitions.
288 #define SNS_LAST_LOOP_ID_2100 0xfe
289 #define SNS_LAST_LOOP_ID_2300 0x7ff
291 #define LAST_LOCAL_LOOP_ID 0x7d
292 #define SNS_FL_PORT 0x7e
293 #define FABRIC_CONTROLLER 0x7f
294 #define SIMPLE_NAME_SERVER 0x80
295 #define SNS_FIRST_LOOP_ID 0x81
296 #define MANAGEMENT_SERVER 0xfe
297 #define BROADCAST 0xff
300 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
301 * valid range of an N-PORT id is 0 through 0x7ef.
303 #define NPH_LAST_HANDLE 0x7ee
304 #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */
305 #define NPH_SNS 0x7fc /* FFFFFC */
306 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
307 #define NPH_F_PORT 0x7fe /* FFFFFE */
308 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
310 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER)
312 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
315 struct name_list_extended {
316 struct get_name_list_extended *l;
318 struct list_head fcports;
323 * Timeout timer counts in seconds
325 #define PORT_RETRY_TIME 1
326 #define LOOP_DOWN_TIMEOUT 60
327 #define LOOP_DOWN_TIME 255 /* 240 */
328 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
330 #define DEFAULT_OUTSTANDING_COMMANDS 4096
331 #define MIN_OUTSTANDING_COMMANDS 128
333 /* ISP request and response entry counts (37-65535) */
334 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
335 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
336 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
337 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */
338 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/
339 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
340 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
341 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
342 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
343 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
344 #define FW_DEF_EXCHANGES_CNT 2048
345 #define FW_MAX_EXCHANGES_CNT (32 * 1024)
346 #define REDUCE_EXCHANGES_CNT (8 * 1024)
355 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
356 uint32_t request_sense_length;
357 uint32_t fw_sense_length;
358 uint8_t *request_sense_ptr;
359 struct ct6_dsd *ct6_ctx;
360 struct crc_context *crc_ctx;
364 * SRB flag definitions
366 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
367 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
368 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
369 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
370 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
371 #define SRB_WAKEUP_ON_COMP BIT_6
372 #define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */
374 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
375 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
378 * 24 bit port ID type definition.
388 #elif defined(__LITTLE_ENDIAN)
393 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
398 #define INVALID_PORT_ID 0xFFFFFF
400 static inline le_id_t be_id_to_le(be_id_t id)
404 res.domain = id.domain;
406 res.al_pa = id.al_pa;
411 static inline be_id_t le_id_to_be(le_id_t id)
415 res.domain = id.domain;
417 res.al_pa = id.al_pa;
422 static inline port_id_t be_to_port_id(be_id_t id)
426 res.b.domain = id.domain;
427 res.b.area = id.area;
428 res.b.al_pa = id.al_pa;
434 static inline be_id_t port_id_to_be_id(port_id_t port_id)
438 res.domain = port_id.b.domain;
439 res.area = port_id.b.area;
440 res.al_pa = port_id.b.al_pa;
445 struct els_logo_payload {
450 uint8_t wwpn[WWN_SIZE];
453 struct els_plogi_payload {
456 __be32 data[112 / 4];
466 u32 req_allocated_size;
467 u32 rsp_allocated_size;
480 #define SRB_LOGIN_RETRIED BIT_0
481 #define SRB_LOGIN_COND_PLOGI BIT_1
482 #define SRB_LOGIN_SKIP_PRLI BIT_2
483 #define SRB_LOGIN_NVME_PRLI BIT_3
484 #define SRB_LOGIN_PRLI_ONLY BIT_4
489 #define ELS_DCMD_TIMEOUT 20
490 #define ELS_DCMD_LOGO 0x5
493 struct completion comp;
494 struct els_logo_payload *els_logo_pyld;
495 dma_addr_t els_logo_pyld_dma;
498 #define ELS_DCMD_PLOGI 0x3
501 struct completion comp;
502 struct els_plogi_payload *els_plogi_pyld;
503 struct els_plogi_payload *els_resp_pyld;
506 dma_addr_t els_plogi_pyld_dma;
507 dma_addr_t els_resp_pyld_dma;
514 * Values for flags field below are as
515 * defined in tsk_mgmt_entry struct
516 * for control_flags field in qla_fw.h.
521 struct completion comp;
525 #define SRB_FXDISC_REQ_DMA_VALID BIT_0
526 #define SRB_FXDISC_RESP_DMA_VALID BIT_1
527 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2
528 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3
529 #define FXDISC_TIMEOUT 20
535 dma_addr_t req_dma_handle;
536 dma_addr_t rsp_dma_handle;
538 __le32 adapter_id_hi;
539 __le16 req_func_type;
541 __le32 req_data_extra;
545 struct completion fxiocb_comp;
553 struct completion comp;
556 #define MAX_IOCB_MB_REG 28
557 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
559 u16 in_mb[MAX_IOCB_MB_REG]; /* from FW */
560 u16 out_mb[MAX_IOCB_MB_REG]; /* to FW */
562 dma_addr_t out_dma, in_dma;
563 struct completion comp;
567 struct imm_ntfy_from_isp *ntfy;
575 /* These are only used with ls4 requests */
580 enum nvmefc_fcp_datadir dir;
582 uint32_t timeout_sec;
583 struct list_head entry;
591 struct timer_list timer;
592 void (*timeout)(void *);
595 /* Values for srb_ctx type */
596 #define SRB_LOGIN_CMD 1
597 #define SRB_LOGOUT_CMD 2
598 #define SRB_ELS_CMD_RPT 3
599 #define SRB_ELS_CMD_HST 4
601 #define SRB_ADISC_CMD 6
603 #define SRB_SCSI_CMD 8
604 #define SRB_BIDI_CMD 9
605 #define SRB_FXIOCB_DCMD 10
606 #define SRB_FXIOCB_BCMD 11
607 #define SRB_ABT_CMD 12
608 #define SRB_ELS_DCMD 13
609 #define SRB_MB_IOCB 14
610 #define SRB_CT_PTHRU_CMD 15
611 #define SRB_NACK_PLOGI 16
612 #define SRB_NACK_PRLI 17
613 #define SRB_NACK_LOGO 18
614 #define SRB_NVME_CMD 19
615 #define SRB_NVME_LS 20
616 #define SRB_PRLI_CMD 21
617 #define SRB_CTRL_VP 22
618 #define SRB_PRLO_CMD 23
623 TYPE_TGT_TMCMD, /* task management */
626 struct iocb_resource {
634 * Do not move cmd_type field, it needs to
635 * line up with qla_tgt_cmd->cmd_type
639 struct iocb_resource iores;
640 struct kref cmd_kref; /* need to migrate ref_count over to this */
642 wait_queue_head_t nvme_ls_waitq;
643 struct fc_port *fcport;
644 struct scsi_qla_host *vha;
645 unsigned int start_timer:1;
652 struct qla_qpair *qpair;
654 struct list_head elem;
655 u32 gen1; /* scratch */
656 u32 gen2; /* scratch */
659 struct completion *comp;
661 struct srb_iocb iocb_cmd;
662 struct bsg_job *bsg_job;
666 * Report completion status @res and call sp_put(@sp). @res is
667 * an NVMe status code, a SCSI result (e.g. DID_OK << 16) or a
668 * QLA_* status value.
670 void (*done)(struct srb *sp, int res);
671 /* Stop the timer and free @sp. Only used by the FCP code. */
672 void (*free)(struct srb *sp);
674 * Call nvme_private->fd->done() and free @sp. Only used by the NVMe
677 void (*put_fn)(struct kref *kref);
680 #define GET_CMD_SP(sp) (sp->u.scmd.cmd)
682 #define GET_CMD_SENSE_LEN(sp) \
683 (sp->u.scmd.request_sense_length)
684 #define SET_CMD_SENSE_LEN(sp, len) \
685 (sp->u.scmd.request_sense_length = len)
686 #define GET_CMD_SENSE_PTR(sp) \
687 (sp->u.scmd.request_sense_ptr)
688 #define SET_CMD_SENSE_PTR(sp, ptr) \
689 (sp->u.scmd.request_sense_ptr = ptr)
690 #define GET_FW_SENSE_LEN(sp) \
691 (sp->u.scmd.fw_sense_length)
692 #define SET_FW_SENSE_LEN(sp, len) \
693 (sp->u.scmd.fw_sense_length = len)
701 uint32_t transfer_size;
702 uint32_t iteration_count;
706 * ISP I/O Register Set structure definitions.
708 struct device_reg_2xxx {
709 __le16 flash_address; /* Flash BIOS address */
710 __le16 flash_data; /* Flash BIOS data */
711 __le16 unused_1[1]; /* Gap */
712 __le16 ctrl_status; /* Control/Status */
713 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
714 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
715 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
717 __le16 ictrl; /* Interrupt control */
718 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
719 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
721 __le16 istatus; /* Interrupt status */
722 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
724 __le16 semaphore; /* Semaphore */
725 __le16 nvram; /* NVRAM register. */
726 #define NVR_DESELECT 0
727 #define NVR_BUSY BIT_15
728 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
729 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
730 #define NVR_DATA_IN BIT_3
731 #define NVR_DATA_OUT BIT_2
732 #define NVR_SELECT BIT_1
733 #define NVR_CLOCK BIT_0
735 #define NVR_WAIT_CNT 20000
747 __le16 unused_2[59]; /* Gap */
748 } __attribute__((packed)) isp2100;
751 __le16 req_q_in; /* In-Pointer */
752 __le16 req_q_out; /* Out-Pointer */
754 __le16 rsp_q_in; /* In-Pointer */
755 __le16 rsp_q_out; /* Out-Pointer */
757 /* RISC to Host Status */
759 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
760 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
762 /* Host to Host Semaphore */
763 __le16 host_semaphore;
764 __le16 unused_3[17]; /* Gap */
798 __le16 unused_4[10]; /* Gap */
799 } __attribute__((packed)) isp2300;
802 __le16 fpm_diag_config;
803 __le16 unused_5[0x4]; /* Gap */
805 __le16 unused_5_1; /* Gap */
806 __le16 pcr; /* Processor Control Register. */
807 __le16 unused_6[0x5]; /* Gap */
808 __le16 mctr; /* Memory Configuration and Timing. */
809 __le16 unused_7[0x3]; /* Gap */
810 __le16 fb_cmd_2100; /* Unused on 23XX */
811 __le16 unused_8[0x3]; /* Gap */
812 __le16 hccr; /* Host command & control register. */
813 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
814 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
816 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
817 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
818 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
819 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
820 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
821 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
822 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
823 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
825 __le16 unused_9[5]; /* Gap */
826 __le16 gpiod; /* GPIO Data register. */
827 __le16 gpioe; /* GPIO Enable register. */
828 #define GPIO_LED_MASK 0x00C0
829 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
830 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
831 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
832 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
833 #define GPIO_LED_ALL_OFF 0x0000
834 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
835 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
839 __le16 unused_10[8]; /* Gap */
855 __le16 mailbox23; /* Also probe reg. */
856 } __attribute__((packed)) isp2200;
860 struct device_reg_25xxmq {
870 struct device_reg_fx00 {
871 __le32 mailbox0; /* 00 */
872 __le32 mailbox1; /* 04 */
873 __le32 mailbox2; /* 08 */
874 __le32 mailbox3; /* 0C */
875 __le32 mailbox4; /* 10 */
876 __le32 mailbox5; /* 14 */
877 __le32 mailbox6; /* 18 */
878 __le32 mailbox7; /* 1C */
879 __le32 mailbox8; /* 20 */
880 __le32 mailbox9; /* 24 */
881 __le32 mailbox10; /* 28 */
912 __le32 req_q_in; /* A0 - Request Queue In-Pointer */
913 __le32 req_q_out; /* A4 - Request Queue Out-Pointer */
914 /* Response Queue. */
915 __le32 rsp_q_in; /* A8 - Response Queue In-Pointer */
916 __le32 rsp_q_out; /* AC - Response Queue Out-Pointer */
917 /* Init values shadowed on FW Up Event */
918 __le32 initval0; /* B0 */
919 __le32 initval1; /* B4 */
920 __le32 initval2; /* B8 */
921 __le32 initval3; /* BC */
922 __le32 initval4; /* C0 */
923 __le32 initval5; /* C4 */
924 __le32 initval6; /* C8 */
925 __le32 initval7; /* CC */
926 __le32 fwheartbeat; /* D0 */
927 __le32 pseudoaen; /* D4 */
933 struct device_reg_2xxx isp;
934 struct device_reg_24xx isp24;
935 struct device_reg_25xxmq isp25mq;
936 struct device_reg_82xx isp82;
937 struct device_reg_fx00 ispfx00;
938 } __iomem device_reg_t;
940 #define ISP_REQ_Q_IN(ha, reg) \
941 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
942 &(reg)->u.isp2100.mailbox4 : \
943 &(reg)->u.isp2300.req_q_in)
944 #define ISP_REQ_Q_OUT(ha, reg) \
945 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
946 &(reg)->u.isp2100.mailbox4 : \
947 &(reg)->u.isp2300.req_q_out)
948 #define ISP_RSP_Q_IN(ha, reg) \
949 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
950 &(reg)->u.isp2100.mailbox5 : \
951 &(reg)->u.isp2300.rsp_q_in)
952 #define ISP_RSP_Q_OUT(ha, reg) \
953 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
954 &(reg)->u.isp2100.mailbox5 : \
955 &(reg)->u.isp2300.rsp_q_out)
957 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
958 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
960 #define MAILBOX_REG(ha, reg, num) \
961 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
963 &(reg)->u.isp2100.mailbox0 + (num) : \
964 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
965 &(reg)->u.isp2300.mailbox0 + (num))
966 #define RD_MAILBOX_REG(ha, reg, num) \
967 rd_reg_word(MAILBOX_REG(ha, reg, num))
968 #define WRT_MAILBOX_REG(ha, reg, num, data) \
969 wrt_reg_word(MAILBOX_REG(ha, reg, num), data)
971 #define FB_CMD_REG(ha, reg) \
972 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
973 &(reg)->fb_cmd_2100 : \
974 &(reg)->u.isp2300.fb_cmd)
975 #define RD_FB_CMD_REG(ha, reg) \
976 rd_reg_word(FB_CMD_REG(ha, reg))
977 #define WRT_FB_CMD_REG(ha, reg, data) \
978 wrt_reg_word(FB_CMD_REG(ha, reg), data)
981 uint32_t out_mb; /* outbound from driver */
982 uint32_t in_mb; /* Incoming from RISC */
983 uint16_t mb[MAILBOX_REGISTER_COUNT];
988 #define MBX_DMA_IN BIT_0
989 #define MBX_DMA_OUT BIT_1
990 #define IOCTL_CMD BIT_2
994 uint32_t out_mb; /* outbound from driver */
995 uint32_t in_mb; /* Incoming from RISC */
996 uint32_t mb[MAILBOX_REGISTER_COUNT];
1001 #define MBX_DMA_IN BIT_0
1002 #define MBX_DMA_OUT BIT_1
1003 #define IOCTL_CMD BIT_2
1007 #define MBX_TOV_SECONDS 30
1010 * ISP product identification definitions in mailboxes after reset.
1012 #define PROD_ID_1 0x4953
1013 #define PROD_ID_2 0x0000
1014 #define PROD_ID_2a 0x5020
1015 #define PROD_ID_3 0x2020
1018 * ISP mailbox Self-Test status codes
1020 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
1021 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
1022 #define MBS_BUSY 4 /* Busy. */
1025 * ISP mailbox command complete status codes
1027 #define MBS_COMMAND_COMPLETE 0x4000
1028 #define MBS_INVALID_COMMAND 0x4001
1029 #define MBS_HOST_INTERFACE_ERROR 0x4002
1030 #define MBS_TEST_FAILED 0x4003
1031 #define MBS_COMMAND_ERROR 0x4005
1032 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
1033 #define MBS_PORT_ID_USED 0x4007
1034 #define MBS_LOOP_ID_USED 0x4008
1035 #define MBS_ALL_IDS_IN_USE 0x4009
1036 #define MBS_NOT_LOGGED_IN 0x400A
1037 #define MBS_LINK_DOWN_ERROR 0x400B
1038 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
1040 static inline bool qla2xxx_is_valid_mbs(unsigned int mbs)
1042 return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR;
1046 * ISP mailbox asynchronous event status codes
1048 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
1049 #define MBA_RESET 0x8001 /* Reset Detected. */
1050 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
1051 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
1052 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
1053 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
1054 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
1056 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
1057 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
1058 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
1059 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
1060 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
1061 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
1062 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
1063 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
1064 #define MBA_CONGN_NOTI_RECV 0x801e /* Congestion Notification Received */
1065 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
1066 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
1067 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
1068 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
1069 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
1070 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
1071 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
1072 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
1074 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
1075 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
1076 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
1077 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
1078 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
1079 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
1080 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
1081 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
1082 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
1083 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
1084 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
1085 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
1086 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
1087 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
1088 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */
1089 #define MBA_FW_STARTING 0x8051 /* Firmware starting */
1090 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */
1091 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */
1092 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */
1093 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */
1094 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */
1095 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */
1096 #define MBA_TRANS_REMOVE 0x8131 /* Transceiver Removal */
1097 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */
1098 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change
1100 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */
1101 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */
1102 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */
1103 /* 83XX FCoE specific */
1104 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
1106 /* Interrupt type codes */
1107 #define INTR_ROM_MB_SUCCESS 0x1
1108 #define INTR_ROM_MB_FAILED 0x2
1109 #define INTR_MB_SUCCESS 0x10
1110 #define INTR_MB_FAILED 0x11
1111 #define INTR_ASYNC_EVENT 0x12
1112 #define INTR_RSP_QUE_UPDATE 0x13
1113 #define INTR_RSP_QUE_UPDATE_83XX 0x14
1114 #define INTR_ATIO_QUE_UPDATE 0x1C
1115 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D
1116 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E
1118 /* ISP mailbox loopback echo diagnostic error code */
1119 #define MBS_LB_RESET 0x17
1121 * Firmware options 1, 2, 3.
1123 #define FO1_AE_ON_LIPF8 BIT_0
1124 #define FO1_AE_ALL_LIP_RESET BIT_1
1125 #define FO1_CTIO_RETRY BIT_3
1126 #define FO1_DISABLE_LIP_F7_SW BIT_4
1127 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
1128 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
1129 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
1130 #define FO1_SET_EMPHASIS_SWING BIT_8
1131 #define FO1_AE_AUTO_BYPASS BIT_9
1132 #define FO1_ENABLE_PURE_IOCB BIT_10
1133 #define FO1_AE_PLOGI_RJT BIT_11
1134 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
1135 #define FO1_AE_QUEUE_FULL BIT_13
1137 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
1138 #define FO2_REV_LOOPBACK BIT_1
1140 #define FO3_ENABLE_EMERG_IOCB BIT_0
1141 #define FO3_AE_RND_ERROR BIT_1
1143 /* 24XX additional firmware options */
1144 #define ADD_FO_COUNT 3
1145 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
1146 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
1148 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
1150 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
1153 * ISP mailbox commands
1155 #define MBC_LOAD_RAM 1 /* Load RAM. */
1156 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
1157 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
1158 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
1159 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
1160 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
1161 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
1162 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
1163 #define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */
1164 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
1165 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
1166 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
1167 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
1168 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
1169 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
1170 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
1171 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
1172 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
1173 #define MBC_RESET 0x18 /* Reset. */
1174 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
1175 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */
1176 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
1177 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
1178 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
1179 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
1180 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/
1181 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
1182 #define MBC_SET_GET_FC_LED_CONFIG 0x3b /* Set/Get FC LED config */
1183 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
1184 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
1185 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
1186 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
1187 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
1188 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
1189 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
1190 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
1191 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
1192 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
1193 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
1194 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
1195 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
1196 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
1197 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */
1198 #define MBC_DATA_RATE 0x5d /* Data Rate */
1199 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
1200 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
1201 /* Initialization Procedure */
1202 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
1203 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
1204 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
1205 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
1206 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
1207 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
1208 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
1209 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
1210 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
1211 #define MBC_LIP_RESET 0x6c /* LIP reset. */
1212 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
1214 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
1215 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
1216 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
1217 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
1218 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
1219 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
1220 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
1221 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
1222 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
1223 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
1224 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
1227 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones
1228 * should be defined with MBC_MR_*
1230 #define MBC_MR_DRV_SHUTDOWN 0x6A
1233 * ISP24xx mailbox commands
1235 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */
1236 #define MBC_READ_SERDES 0x4 /* Read serdes word. */
1237 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */
1238 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
1239 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
1240 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
1241 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
1242 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
1243 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
1244 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
1245 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
1246 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
1247 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */
1248 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
1249 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
1250 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
1251 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
1252 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
1253 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
1254 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */
1255 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
1256 #define MBC_PORT_RESET 0x120 /* Port Reset */
1257 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
1258 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
1261 * ISP81xx mailbox commands
1263 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
1266 * ISP8044 mailbox commands
1268 #define MBC_SET_GET_ETH_SERDES_REG 0x150
1269 #define HCS_WRITE_SERDES 0x3
1270 #define HCS_READ_SERDES 0x4
1272 /* Firmware return data sizes */
1273 #define FCAL_MAP_SIZE 128
1275 /* Mailbox bit definitions for out_mb and in_mb */
1276 #define MBX_31 BIT_31
1277 #define MBX_30 BIT_30
1278 #define MBX_29 BIT_29
1279 #define MBX_28 BIT_28
1280 #define MBX_27 BIT_27
1281 #define MBX_26 BIT_26
1282 #define MBX_25 BIT_25
1283 #define MBX_24 BIT_24
1284 #define MBX_23 BIT_23
1285 #define MBX_22 BIT_22
1286 #define MBX_21 BIT_21
1287 #define MBX_20 BIT_20
1288 #define MBX_19 BIT_19
1289 #define MBX_18 BIT_18
1290 #define MBX_17 BIT_17
1291 #define MBX_16 BIT_16
1292 #define MBX_15 BIT_15
1293 #define MBX_14 BIT_14
1294 #define MBX_13 BIT_13
1295 #define MBX_12 BIT_12
1296 #define MBX_11 BIT_11
1297 #define MBX_10 BIT_10
1309 #define RNID_TYPE_ELS_CMD 0x5
1310 #define RNID_TYPE_PORT_LOGIN 0x7
1311 #define RNID_BUFFER_CREDITS 0x8
1312 #define RNID_TYPE_SET_VERSION 0x9
1313 #define RNID_TYPE_ASIC_TEMP 0xC
1315 #define ELS_CMD_MAP_SIZE 32
1318 * Firmware state codes from get firmware state mailbox command
1320 #define FSTATE_CONFIG_WAIT 0
1321 #define FSTATE_WAIT_AL_PA 1
1322 #define FSTATE_WAIT_LOGIN 2
1323 #define FSTATE_READY 3
1324 #define FSTATE_LOSS_OF_SYNC 4
1325 #define FSTATE_ERROR 5
1326 #define FSTATE_REINIT 6
1327 #define FSTATE_NON_PART 7
1329 #define FSTATE_CONFIG_CORRECT 0
1330 #define FSTATE_P2P_RCV_LIP 1
1331 #define FSTATE_P2P_CHOOSE_LOOP 2
1332 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
1333 #define FSTATE_FATAL_ERROR 4
1334 #define FSTATE_LOOP_BACK_CONN 5
1336 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
1337 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00
1338 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
1339 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1340 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1341 #define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED
1342 #define QLA27XX_DEFAULT_IMAGE 0
1343 #define QLA27XX_PRIMARY_IMAGE 1
1344 #define QLA27XX_SECONDARY_IMAGE 2
1347 * Port Database structure definition
1348 * Little endian except where noted.
1350 #define PORT_DATABASE_SIZE 128 /* bytes */
1354 uint8_t master_state;
1355 uint8_t slave_state;
1356 uint8_t reserved[2];
1357 uint8_t hard_address;
1360 uint8_t node_name[WWN_SIZE];
1361 uint8_t port_name[WWN_SIZE];
1362 __le16 execution_throttle;
1363 uint16_t execution_count;
1364 uint8_t reset_count;
1366 uint16_t resource_allocation;
1367 uint16_t current_allocation;
1368 uint16_t queue_head;
1369 uint16_t queue_tail;
1370 uint16_t transmit_execution_list_next;
1371 uint16_t transmit_execution_list_previous;
1372 uint16_t common_features;
1373 uint16_t total_concurrent_sequences;
1374 uint16_t RO_by_information_category;
1377 uint16_t receive_data_size;
1378 uint16_t concurrent_sequences;
1379 uint16_t open_sequences_per_exchange;
1380 uint16_t lun_abort_flags;
1381 uint16_t lun_stop_flags;
1382 uint16_t stop_queue_head;
1383 uint16_t stop_queue_tail;
1384 uint16_t port_retry_timer;
1385 uint16_t next_sequence_id;
1386 uint16_t frame_count;
1387 uint16_t PRLI_payload_length;
1388 uint8_t prli_svc_param_word_0[2]; /* Big endian */
1389 /* Bits 15-0 of word 0 */
1390 uint8_t prli_svc_param_word_3[2]; /* Big endian */
1391 /* Bits 15-0 of word 3 */
1393 uint16_t extended_lun_info_list_pointer;
1394 uint16_t extended_lun_stop_list_pointer;
1398 * Port database slave/master states
1400 #define PD_STATE_DISCOVERY 0
1401 #define PD_STATE_WAIT_DISCOVERY_ACK 1
1402 #define PD_STATE_PORT_LOGIN 2
1403 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1404 #define PD_STATE_PROCESS_LOGIN 4
1405 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1406 #define PD_STATE_PORT_LOGGED_IN 6
1407 #define PD_STATE_PORT_UNAVAILABLE 7
1408 #define PD_STATE_PROCESS_LOGOUT 8
1409 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1410 #define PD_STATE_PORT_LOGOUT 10
1411 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1414 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1415 #define QLA_ZIO_DISABLED 0
1416 #define QLA_ZIO_DEFAULT_TIMER 2
1419 * ISP Initialization Control Block.
1420 * Little endian except where noted.
1422 #define ICB_VERSION 1
1428 * LSB BIT 0 = Enable Hard Loop Id
1429 * LSB BIT 1 = Enable Fairness
1430 * LSB BIT 2 = Enable Full-Duplex
1431 * LSB BIT 3 = Enable Fast Posting
1432 * LSB BIT 4 = Enable Target Mode
1433 * LSB BIT 5 = Disable Initiator Mode
1434 * LSB BIT 6 = Enable ADISC
1435 * LSB BIT 7 = Enable Target Inquiry Data
1437 * MSB BIT 0 = Enable PDBC Notify
1438 * MSB BIT 1 = Non Participating LIP
1439 * MSB BIT 2 = Descending Loop ID Search
1440 * MSB BIT 3 = Acquire Loop ID in LIPA
1441 * MSB BIT 4 = Stop PortQ on Full Status
1442 * MSB BIT 5 = Full Login after LIP
1443 * MSB BIT 6 = Node Name Option
1444 * MSB BIT 7 = Ext IFWCB enable bit
1446 uint8_t firmware_options[2];
1448 __le16 frame_payload_size;
1449 __le16 max_iocb_allocation;
1450 __le16 execution_throttle;
1451 uint8_t retry_count;
1452 uint8_t retry_delay; /* unused */
1453 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1454 uint16_t hard_address;
1455 uint8_t inquiry_data;
1456 uint8_t login_timeout;
1457 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1459 __le16 request_q_outpointer;
1460 __le16 response_q_inpointer;
1461 __le16 request_q_length;
1462 __le16 response_q_length;
1463 __le64 request_q_address __packed;
1464 __le64 response_q_address __packed;
1467 uint8_t command_resource_count;
1468 uint8_t immediate_notify_resource_count;
1470 uint8_t reserved_2[2];
1473 * LSB BIT 0 = Timer Operation mode bit 0
1474 * LSB BIT 1 = Timer Operation mode bit 1
1475 * LSB BIT 2 = Timer Operation mode bit 2
1476 * LSB BIT 3 = Timer Operation mode bit 3
1477 * LSB BIT 4 = Init Config Mode bit 0
1478 * LSB BIT 5 = Init Config Mode bit 1
1479 * LSB BIT 6 = Init Config Mode bit 2
1480 * LSB BIT 7 = Enable Non part on LIHA failure
1482 * MSB BIT 0 = Enable class 2
1483 * MSB BIT 1 = Enable ACK0
1486 * MSB BIT 4 = FC Tape Enable
1487 * MSB BIT 5 = Enable FC Confirm
1488 * MSB BIT 6 = Enable command queuing in target mode
1489 * MSB BIT 7 = No Logo On Link Down
1491 uint8_t add_firmware_options[2];
1493 uint8_t response_accumulation_timer;
1494 uint8_t interrupt_delay_timer;
1497 * LSB BIT 0 = Enable Read xfr_rdy
1498 * LSB BIT 1 = Soft ID only
1501 * LSB BIT 4 = FCP RSP Payload [0]
1502 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1503 * LSB BIT 6 = Enable Out-of-Order frame handling
1504 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1506 * MSB BIT 0 = Sbus enable - 2300
1510 * MSB BIT 4 = LED mode
1511 * MSB BIT 5 = enable 50 ohm termination
1512 * MSB BIT 6 = Data Rate (2300 only)
1513 * MSB BIT 7 = Data Rate (2300 only)
1515 uint8_t special_options[2];
1517 uint8_t reserved_3[26];
1520 /* Special Features Control Block */
1525 * BIT 15-14 = Reserved
1526 * BIT_13 = SAN Congestion Management (1 - Enabled, 0 - Disabled)
1527 * BIT_12 = Remote Write Optimization (1 - Enabled, 0 - Disabled)
1528 * BIT 11-0 = Reserved
1531 uint8_t reserved1[32];
1532 uint16_t discard_OHRB_timeout_value;
1533 uint16_t remote_write_opt_queue_num;
1534 uint8_t reserved2[40];
1535 uint8_t scm_related_parameter[16];
1536 uint8_t reserved3[32];
1540 * Get Link Status mailbox command return buffer.
1542 #define GLSO_SEND_RPS BIT_0
1543 #define GLSO_USE_DID BIT_3
1545 struct link_statistics {
1546 __le32 link_fail_cnt;
1547 __le32 loss_sync_cnt;
1548 __le32 loss_sig_cnt;
1549 __le32 prim_seq_err_cnt;
1550 __le32 inval_xmit_word_cnt;
1551 __le32 inval_crc_cnt;
1554 __le32 link_down_loop_init_tmo;
1555 __le32 link_down_los;
1556 __le32 link_down_loss_rcv_clk;
1557 uint32_t reserved0[5];
1558 __le32 port_cfg_chg;
1559 uint32_t reserved1[11];
1563 __le32 els_proto_err;
1567 __le32 discarded_frames;
1568 __le32 dropped_frames;
1571 uint32_t reserved4[4];
1575 __le32 seq_frm_miss;
1581 __le64 fpm_recv_word_cnt;
1582 __le64 fpm_disc_word_cnt;
1583 __le64 fpm_xmit_word_cnt;
1584 uint32_t reserved6[70];
1588 * NVRAM Command values.
1590 #define NV_START_BIT BIT_2
1591 #define NV_WRITE_OP (BIT_26+BIT_24)
1592 #define NV_READ_OP (BIT_26+BIT_25)
1593 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1594 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1595 #define NV_DELAY_COUNT 10
1598 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
1605 uint8_t nvram_version;
1609 * NVRAM RISC parameter block
1611 uint8_t parameter_block_version;
1615 * LSB BIT 0 = Enable Hard Loop Id
1616 * LSB BIT 1 = Enable Fairness
1617 * LSB BIT 2 = Enable Full-Duplex
1618 * LSB BIT 3 = Enable Fast Posting
1619 * LSB BIT 4 = Enable Target Mode
1620 * LSB BIT 5 = Disable Initiator Mode
1621 * LSB BIT 6 = Enable ADISC
1622 * LSB BIT 7 = Enable Target Inquiry Data
1624 * MSB BIT 0 = Enable PDBC Notify
1625 * MSB BIT 1 = Non Participating LIP
1626 * MSB BIT 2 = Descending Loop ID Search
1627 * MSB BIT 3 = Acquire Loop ID in LIPA
1628 * MSB BIT 4 = Stop PortQ on Full Status
1629 * MSB BIT 5 = Full Login after LIP
1630 * MSB BIT 6 = Node Name Option
1631 * MSB BIT 7 = Ext IFWCB enable bit
1633 uint8_t firmware_options[2];
1635 __le16 frame_payload_size;
1636 __le16 max_iocb_allocation;
1637 __le16 execution_throttle;
1638 uint8_t retry_count;
1639 uint8_t retry_delay; /* unused */
1640 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1641 uint16_t hard_address;
1642 uint8_t inquiry_data;
1643 uint8_t login_timeout;
1644 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1647 * LSB BIT 0 = Timer Operation mode bit 0
1648 * LSB BIT 1 = Timer Operation mode bit 1
1649 * LSB BIT 2 = Timer Operation mode bit 2
1650 * LSB BIT 3 = Timer Operation mode bit 3
1651 * LSB BIT 4 = Init Config Mode bit 0
1652 * LSB BIT 5 = Init Config Mode bit 1
1653 * LSB BIT 6 = Init Config Mode bit 2
1654 * LSB BIT 7 = Enable Non part on LIHA failure
1656 * MSB BIT 0 = Enable class 2
1657 * MSB BIT 1 = Enable ACK0
1660 * MSB BIT 4 = FC Tape Enable
1661 * MSB BIT 5 = Enable FC Confirm
1662 * MSB BIT 6 = Enable command queuing in target mode
1663 * MSB BIT 7 = No Logo On Link Down
1665 uint8_t add_firmware_options[2];
1667 uint8_t response_accumulation_timer;
1668 uint8_t interrupt_delay_timer;
1671 * LSB BIT 0 = Enable Read xfr_rdy
1672 * LSB BIT 1 = Soft ID only
1675 * LSB BIT 4 = FCP RSP Payload [0]
1676 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1677 * LSB BIT 6 = Enable Out-of-Order frame handling
1678 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1680 * MSB BIT 0 = Sbus enable - 2300
1684 * MSB BIT 4 = LED mode
1685 * MSB BIT 5 = enable 50 ohm termination
1686 * MSB BIT 6 = Data Rate (2300 only)
1687 * MSB BIT 7 = Data Rate (2300 only)
1689 uint8_t special_options[2];
1691 /* Reserved for expanded RISC parameter block */
1692 uint8_t reserved_2[22];
1695 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1696 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1697 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1698 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1699 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1700 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1701 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1702 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1704 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1705 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1706 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1707 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1708 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1709 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1710 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1711 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1713 * LSB BIT 0 = Output Swing 1G bit 0
1714 * LSB BIT 1 = Output Swing 1G bit 1
1715 * LSB BIT 2 = Output Swing 1G bit 2
1716 * LSB BIT 3 = Output Emphasis 1G bit 0
1717 * LSB BIT 4 = Output Emphasis 1G bit 1
1718 * LSB BIT 5 = Output Swing 2G bit 0
1719 * LSB BIT 6 = Output Swing 2G bit 1
1720 * LSB BIT 7 = Output Swing 2G bit 2
1722 * MSB BIT 0 = Output Emphasis 2G bit 0
1723 * MSB BIT 1 = Output Emphasis 2G bit 1
1724 * MSB BIT 2 = Output Enable
1731 uint8_t seriallink_options[4];
1734 * NVRAM host parameter block
1736 * LSB BIT 0 = Enable spinup delay
1737 * LSB BIT 1 = Disable BIOS
1738 * LSB BIT 2 = Enable Memory Map BIOS
1739 * LSB BIT 3 = Enable Selectable Boot
1740 * LSB BIT 4 = Disable RISC code load
1741 * LSB BIT 5 = Set cache line size 1
1742 * LSB BIT 6 = PCI Parity Disable
1743 * LSB BIT 7 = Enable extended logging
1745 * MSB BIT 0 = Enable 64bit addressing
1746 * MSB BIT 1 = Enable lip reset
1747 * MSB BIT 2 = Enable lip full login
1748 * MSB BIT 3 = Enable target reset
1749 * MSB BIT 4 = Enable database storage
1750 * MSB BIT 5 = Enable cache flush read
1751 * MSB BIT 6 = Enable database load
1752 * MSB BIT 7 = Enable alternate WWN
1756 uint8_t boot_node_name[WWN_SIZE];
1757 uint8_t boot_lun_number;
1758 uint8_t reset_delay;
1759 uint8_t port_down_retry_count;
1760 uint8_t boot_id_number;
1761 __le16 max_luns_per_target;
1762 uint8_t fcode_boot_port_name[WWN_SIZE];
1763 uint8_t alternate_port_name[WWN_SIZE];
1764 uint8_t alternate_node_name[WWN_SIZE];
1767 * BIT 0 = Selective Login
1768 * BIT 1 = Alt-Boot Enable
1770 * BIT 3 = Boot Order List
1772 * BIT 5 = Selective LUN
1776 uint8_t efi_parameters;
1778 uint8_t link_down_timeout;
1780 uint8_t adapter_id[16];
1782 uint8_t alt1_boot_node_name[WWN_SIZE];
1783 uint16_t alt1_boot_lun_number;
1784 uint8_t alt2_boot_node_name[WWN_SIZE];
1785 uint16_t alt2_boot_lun_number;
1786 uint8_t alt3_boot_node_name[WWN_SIZE];
1787 uint16_t alt3_boot_lun_number;
1788 uint8_t alt4_boot_node_name[WWN_SIZE];
1789 uint16_t alt4_boot_lun_number;
1790 uint8_t alt5_boot_node_name[WWN_SIZE];
1791 uint16_t alt5_boot_lun_number;
1792 uint8_t alt6_boot_node_name[WWN_SIZE];
1793 uint16_t alt6_boot_lun_number;
1794 uint8_t alt7_boot_node_name[WWN_SIZE];
1795 uint16_t alt7_boot_lun_number;
1797 uint8_t reserved_3[2];
1799 /* Offset 200-215 : Model Number */
1800 uint8_t model_number[16];
1802 /* OEM related items */
1803 uint8_t oem_specific[16];
1806 * NVRAM Adapter Features offset 232-239
1808 * LSB BIT 0 = External GBIC
1809 * LSB BIT 1 = Risc RAM parity
1810 * LSB BIT 2 = Buffer Plus Module
1811 * LSB BIT 3 = Multi Chip Adapter
1812 * LSB BIT 4 = Internal connector
1826 uint8_t adapter_features[2];
1828 uint8_t reserved_4[16];
1830 /* Subsystem vendor ID for ISP2200 */
1831 uint16_t subsystem_vendor_id_2200;
1833 /* Subsystem device ID for ISP2200 */
1834 uint16_t subsystem_device_id_2200;
1841 * ISP queue - response queue entry definition.
1844 uint8_t entry_type; /* Entry type. */
1845 uint8_t entry_count; /* Entry count. */
1846 uint8_t sys_define; /* System defined. */
1847 uint8_t entry_status; /* Entry Status. */
1848 uint32_t handle; /* System defined handle */
1851 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1855 * ISP queue - ATIO queue entry definition.
1858 uint8_t entry_type; /* Entry type. */
1859 uint8_t entry_count; /* Entry count. */
1860 __le16 attr_n_length;
1863 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */
1874 #define SET_TARGET_ID(ha, to, from) \
1876 if (HAS_EXTENDED_IDS(ha)) \
1877 to.extended = cpu_to_le16(from); \
1879 to.id.standard = (uint8_t)from; \
1883 * ISP queue - command entry structure definition.
1885 #define COMMAND_TYPE 0x11 /* Command entry */
1887 uint8_t entry_type; /* Entry type. */
1888 uint8_t entry_count; /* Entry count. */
1889 uint8_t sys_define; /* System defined. */
1890 uint8_t entry_status; /* Entry Status. */
1891 uint32_t handle; /* System handle. */
1892 target_id_t target; /* SCSI ID */
1893 __le16 lun; /* SCSI LUN */
1894 __le16 control_flags; /* Control flags. */
1895 #define CF_WRITE BIT_6
1896 #define CF_READ BIT_5
1897 #define CF_SIMPLE_TAG BIT_3
1898 #define CF_ORDERED_TAG BIT_2
1899 #define CF_HEAD_TAG BIT_1
1900 uint16_t reserved_1;
1901 __le16 timeout; /* Command timeout. */
1902 __le16 dseg_count; /* Data segment count. */
1903 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1904 __le32 byte_count; /* Total byte count. */
1906 struct dsd32 dsd32[3];
1907 struct dsd64 dsd64[2];
1912 * ISP queue - 64-Bit addressing, command entry structure definition.
1914 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1916 uint8_t entry_type; /* Entry type. */
1917 uint8_t entry_count; /* Entry count. */
1918 uint8_t sys_define; /* System defined. */
1919 uint8_t entry_status; /* Entry Status. */
1920 uint32_t handle; /* System handle. */
1921 target_id_t target; /* SCSI ID */
1922 __le16 lun; /* SCSI LUN */
1923 __le16 control_flags; /* Control flags. */
1924 uint16_t reserved_1;
1925 __le16 timeout; /* Command timeout. */
1926 __le16 dseg_count; /* Data segment count. */
1927 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1928 uint32_t byte_count; /* Total byte count. */
1929 struct dsd64 dsd[2];
1930 } cmd_a64_entry_t, request_t;
1933 * ISP queue - continuation entry structure definition.
1935 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1937 uint8_t entry_type; /* Entry type. */
1938 uint8_t entry_count; /* Entry count. */
1939 uint8_t sys_define; /* System defined. */
1940 uint8_t entry_status; /* Entry Status. */
1942 struct dsd32 dsd[7];
1946 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1948 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1950 uint8_t entry_type; /* Entry type. */
1951 uint8_t entry_count; /* Entry count. */
1952 uint8_t sys_define; /* System defined. */
1953 uint8_t entry_status; /* Entry Status. */
1954 struct dsd64 dsd[5];
1957 #define PO_MODE_DIF_INSERT 0
1958 #define PO_MODE_DIF_REMOVE 1
1959 #define PO_MODE_DIF_PASS 2
1960 #define PO_MODE_DIF_REPLACE 3
1961 #define PO_MODE_DIF_TCP_CKSUM 6
1962 #define PO_ENABLE_INCR_GUARD_SEED BIT_3
1963 #define PO_DISABLE_GUARD_CHECK BIT_4
1964 #define PO_DISABLE_INCR_REF_TAG BIT_5
1965 #define PO_DIS_HEADER_MODE BIT_7
1966 #define PO_ENABLE_DIF_BUNDLING BIT_8
1967 #define PO_DIS_FRAME_MODE BIT_9
1968 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */
1969 #define PO_DIS_VALD_APP_REF_ESC BIT_11
1971 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */
1972 #define PO_DIS_REF_TAG_REPL BIT_13
1973 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */
1974 #define PO_DIS_REF_TAG_VALD BIT_15
1977 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
1979 struct crc_context {
1980 uint32_t handle; /* System handle. */
1983 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
1984 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
1985 __le16 guard_seed; /* Initial Guard Seed */
1986 __le16 prot_opts; /* Requested Data Protection Mode */
1987 __le16 blk_size; /* Data size in bytes */
1988 __le16 runt_blk_guard; /* Guard value for runt block (tape
1990 __le32 byte_count; /* Total byte count/ total data
1994 uint32_t reserved_1;
1995 uint16_t reserved_2;
1996 uint16_t reserved_3;
1997 uint32_t reserved_4;
1998 struct dsd64 data_dsd[1];
1999 uint32_t reserved_5[2];
2000 uint32_t reserved_6;
2003 __le32 dif_byte_count; /* Total DIF byte
2005 uint16_t reserved_1;
2006 __le16 dseg_count; /* Data segment count */
2007 uint32_t reserved_2;
2008 struct dsd64 data_dsd[1];
2009 struct dsd64 dif_dsd;
2013 struct fcp_cmnd fcp_cmnd;
2014 dma_addr_t crc_ctx_dma;
2015 /* List of DMA context transfers */
2016 struct list_head dsd_list;
2018 /* List of DIF Bundling context DMA address */
2019 struct list_head ldif_dsd_list;
2022 struct list_head ldif_dma_hndl_list;
2025 /* This structure should not exceed 512 bytes */
2028 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
2029 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
2032 * ISP queue - status entry structure definition.
2034 #define STATUS_TYPE 0x03 /* Status entry. */
2036 uint8_t entry_type; /* Entry type. */
2037 uint8_t entry_count; /* Entry count. */
2038 uint8_t sys_define; /* System defined. */
2039 uint8_t entry_status; /* Entry Status. */
2040 uint32_t handle; /* System handle. */
2041 __le16 scsi_status; /* SCSI status. */
2042 __le16 comp_status; /* Completion status. */
2043 __le16 state_flags; /* State flags. */
2044 __le16 status_flags; /* Status flags. */
2045 __le16 rsp_info_len; /* Response Info Length. */
2046 __le16 req_sense_length; /* Request sense data length. */
2047 __le32 residual_length; /* Residual transfer length. */
2048 uint8_t rsp_info[8]; /* FCP response information. */
2049 uint8_t req_sense_data[32]; /* Request sense data. */
2053 * Status entry entry status
2055 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
2056 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
2057 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
2058 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
2059 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
2060 #define RF_BUSY BIT_1 /* Busy */
2061 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
2062 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
2063 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
2067 * Status entry SCSI status bit definitions.
2069 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
2070 #define SS_RESIDUAL_UNDER BIT_11
2071 #define SS_RESIDUAL_OVER BIT_10
2072 #define SS_SENSE_LEN_VALID BIT_9
2073 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
2074 #define SS_SCSI_STATUS_BYTE 0xff
2076 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
2077 #define SS_BUSY_CONDITION BIT_3
2078 #define SS_CONDITION_MET BIT_2
2079 #define SS_CHECK_CONDITION BIT_1
2082 * Status entry completion status
2084 #define CS_COMPLETE 0x0 /* No errors */
2085 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
2086 #define CS_DMA 0x2 /* A DMA direction error. */
2087 #define CS_TRANSPORT 0x3 /* Transport error. */
2088 #define CS_RESET 0x4 /* SCSI bus reset occurred */
2089 #define CS_ABORTED 0x5 /* System aborted command. */
2090 #define CS_TIMEOUT 0x6 /* Timeout error. */
2091 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
2092 #define CS_DIF_ERROR 0xC /* DIF error detected */
2094 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
2095 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
2096 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
2097 /* (selection timeout) */
2098 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
2099 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
2100 #define CS_PORT_BUSY 0x2B /* Port Busy */
2101 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
2102 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request
2104 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
2105 #define CS_UNKNOWN 0x81 /* Driver defined */
2106 #define CS_RETRY 0x82 /* Driver defined */
2107 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
2109 #define CS_BIDIR_RD_OVERRUN 0x700
2110 #define CS_BIDIR_RD_WR_OVERRUN 0x707
2111 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
2112 #define CS_BIDIR_RD_UNDERRUN 0x1500
2113 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
2114 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515
2115 #define CS_BIDIR_DMA 0x200
2117 * Status entry status flags
2119 #define SF_ABTS_TERMINATED BIT_10
2120 #define SF_LOGOUT_SENT BIT_13
2123 * ISP queue - status continuation entry structure definition.
2125 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
2127 uint8_t entry_type; /* Entry type. */
2128 uint8_t entry_count; /* Entry count. */
2129 uint8_t sys_define; /* System defined. */
2130 uint8_t entry_status; /* Entry Status. */
2131 uint8_t data[60]; /* data */
2135 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
2136 * structure definition.
2138 #define STATUS_TYPE_21 0x21 /* Status entry. */
2140 uint8_t entry_type; /* Entry type. */
2141 uint8_t entry_count; /* Entry count. */
2142 uint8_t handle_count; /* Handle count. */
2143 uint8_t entry_status; /* Entry Status. */
2144 uint32_t handle[15]; /* System handles. */
2148 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
2149 * structure definition.
2151 #define STATUS_TYPE_22 0x22 /* Status entry. */
2153 uint8_t entry_type; /* Entry type. */
2154 uint8_t entry_count; /* Entry count. */
2155 uint8_t handle_count; /* Handle count. */
2156 uint8_t entry_status; /* Entry Status. */
2157 uint16_t handle[30]; /* System handles. */
2161 * ISP queue - marker entry structure definition.
2163 #define MARKER_TYPE 0x04 /* Marker entry. */
2165 uint8_t entry_type; /* Entry type. */
2166 uint8_t entry_count; /* Entry count. */
2167 uint8_t handle_count; /* Handle count. */
2168 uint8_t entry_status; /* Entry Status. */
2169 uint32_t sys_define_2; /* System defined. */
2170 target_id_t target; /* SCSI ID */
2171 uint8_t modifier; /* Modifier (7-0). */
2172 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
2173 #define MK_SYNC_ID 1 /* Synchronize ID */
2174 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
2175 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
2176 /* clear port changed, */
2177 /* use sequence number. */
2179 __le16 sequence_number; /* Sequence number of event */
2180 __le16 lun; /* SCSI LUN */
2181 uint8_t reserved_2[48];
2185 * ISP queue - Management Server entry structure definition.
2187 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
2189 uint8_t entry_type; /* Entry type. */
2190 uint8_t entry_count; /* Entry count. */
2191 uint8_t handle_count; /* Handle count. */
2192 uint8_t entry_status; /* Entry Status. */
2193 uint32_t handle1; /* System handle. */
2194 target_id_t loop_id;
2196 __le16 control_flags; /* Control flags. */
2199 __le16 cmd_dsd_count;
2200 __le16 total_dsd_count;
2206 __le32 rsp_bytecount;
2207 __le32 req_bytecount;
2208 struct dsd64 req_dsd;
2209 struct dsd64 rsp_dsd;
2212 #define SCM_EDC_ACC_RECEIVED BIT_6
2213 #define SCM_RDF_ACC_RECEIVED BIT_7
2216 * ISP queue - Mailbox Command entry structure definition.
2218 #define MBX_IOCB_TYPE 0x39
2221 uint8_t entry_count;
2222 uint8_t sys_define1;
2223 /* Use sys_define1 for source type */
2224 #define SOURCE_SCSI 0x00
2225 #define SOURCE_IP 0x01
2226 #define SOURCE_VI 0x02
2227 #define SOURCE_SCTP 0x03
2228 #define SOURCE_MP 0x04
2229 #define SOURCE_MPIOCTL 0x05
2230 #define SOURCE_ASYNC_IOCB 0x07
2232 uint8_t entry_status;
2235 target_id_t loop_id;
2239 __le16 status_flags;
2241 uint32_t sys_define2[2];
2251 uint32_t reserved_2[2];
2252 uint8_t node_name[WWN_SIZE];
2253 uint8_t port_name[WWN_SIZE];
2256 #ifndef IMMED_NOTIFY_TYPE
2257 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */
2259 * ISP queue - immediate notify entry structure definition.
2260 * This is sent by the ISP to the Target driver.
2261 * This IOCB would have report of events sent by the
2262 * initiator, that needs to be handled by the target
2263 * driver immediately.
2265 struct imm_ntfy_from_isp {
2266 uint8_t entry_type; /* Entry type. */
2267 uint8_t entry_count; /* Entry count. */
2268 uint8_t sys_define; /* System defined. */
2269 uint8_t entry_status; /* Entry Status. */
2272 __le32 sys_define_2; /* System defined. */
2277 __le16 status_modifier;
2282 __le32 srr_rel_offs;
2284 #define SRR_IU_DATA_IN 0x1
2285 #define SRR_IU_DATA_OUT 0x5
2286 #define SRR_IU_STATUS 0x7
2288 uint8_t reserved_2[28];
2292 __le16 nport_handle;
2293 uint16_t reserved_2;
2295 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
2296 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
2299 uint8_t status_subcode;
2301 __le32 exchange_address;
2302 __le32 srr_rel_offs;
2307 uint8_t node_name[8];
2308 } plogi; /* PLOGI/ADISC/PDISC */
2310 /* PRLI word 3 bit 0-15 */
2317 __le16 nport_handle;
2321 uint8_t port_name[8];
2324 uint32_t reserved_5;
2329 uint16_t reserved_7;
2335 * ISP request and response queue entry sizes
2337 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
2338 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
2343 * Switch info gathering structure.
2347 uint8_t node_name[WWN_SIZE];
2348 uint8_t port_name[WWN_SIZE];
2349 uint8_t fabric_port_name[WWN_SIZE];
2352 uint8_t fc4_features;
2356 #define FC4_TYPE_FCP_SCSI 0x08
2357 #define FC4_TYPE_NVME 0x28
2358 #define FC4_TYPE_OTHER 0x0
2359 #define FC4_TYPE_UNKNOWN 0xff
2361 /* mailbox command 4G & above */
2362 struct mbx_24xx_entry {
2364 uint8_t entry_count;
2365 uint8_t sys_define1;
2366 uint8_t entry_status;
2371 #define IOCB_SIZE 64
2374 * Fibre channel port type.
2383 FCT_NVME_INITIATOR = 0x10,
2384 FCT_NVME_TARGET = 0x20,
2385 FCT_NVME_DISCOVERY = 0x40,
2389 enum qla_sess_deletion {
2390 QLA_SESS_DELETION_NONE = 0,
2391 QLA_SESS_DELETION_IN_PROGRESS,
2395 enum qlt_plogi_link_t {
2396 QLT_PLOGI_LINK_SAME_WWN,
2397 QLT_PLOGI_LINK_CONFLICT,
2401 struct qlt_plogi_ack_t {
2402 struct list_head list;
2403 struct imm_ntfy_from_isp iocb;
2409 struct ct_sns_desc {
2410 struct ct_sns_pkt *ct_sns;
2411 dma_addr_t ct_sns_dma;
2414 enum discovery_state {
2427 enum login_state { /* FW control Target side */
2428 DSC_LS_LLIOCB_SENT = 2,
2433 DSC_LS_PORT_UNAVAIL,
2434 DSC_LS_PRLO_PEND = 9,
2438 enum rscn_addr_format {
2446 * Fibre channel port structure.
2448 typedef struct fc_port {
2449 struct list_head list;
2450 struct scsi_qla_host *vha;
2452 unsigned int conf_compl_supported:1;
2453 unsigned int deleted:2;
2454 unsigned int free_pending:1;
2455 unsigned int local:1;
2456 unsigned int logout_on_delete:1;
2457 unsigned int logo_ack_needed:1;
2458 unsigned int keep_nport_handle:1;
2459 unsigned int send_els_logo:1;
2460 unsigned int login_pause:1;
2461 unsigned int login_succ:1;
2462 unsigned int query:1;
2463 unsigned int id_changed:1;
2464 unsigned int scan_needed:1;
2465 unsigned int n2n_flag:1;
2466 unsigned int explicit_logout:1;
2467 unsigned int prli_pend_timer:1;
2470 uint8_t node_name[WWN_SIZE];
2471 uint8_t port_name[WWN_SIZE];
2474 uint16_t old_loop_id;
2476 struct completion nvme_del_done;
2477 uint32_t nvme_prli_service_param;
2478 #define NVME_PRLI_SP_PI_CTRL BIT_9
2479 #define NVME_PRLI_SP_SLER BIT_8
2480 #define NVME_PRLI_SP_CONF BIT_7
2481 #define NVME_PRLI_SP_INITIATOR BIT_5
2482 #define NVME_PRLI_SP_TARGET BIT_4
2483 #define NVME_PRLI_SP_DISCOVERY BIT_3
2484 #define NVME_PRLI_SP_FIRST_BURST BIT_0
2486 uint32_t nvme_first_burst_size;
2487 #define NVME_FLAG_REGISTERED 4
2488 #define NVME_FLAG_DELETING 2
2489 #define NVME_FLAG_RESETTING 1
2491 struct fc_port *conflict;
2492 unsigned char logout_completed;
2495 struct se_session *se_sess;
2496 struct kref sess_kref;
2497 struct qla_tgt *tgt;
2498 unsigned long expires;
2499 struct list_head del_list_entry;
2500 struct work_struct free_work;
2501 struct work_struct reg_work;
2502 uint64_t jiffies_at_registration;
2503 unsigned long prli_expired;
2504 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
2507 uint16_t old_tgt_id;
2508 uint16_t sec_since_registration;
2512 uint8_t fabric_port_name[WWN_SIZE];
2515 fc_port_type_t port_type;
2522 struct fc_rport *rport, *drport;
2523 u32 supported_classes;
2526 uint8_t fc4_features;
2529 unsigned long last_queue_full;
2530 unsigned long last_ramp_up;
2534 struct nvme_fc_remote_port *nvme_remote_port;
2536 unsigned long retry_delay_timestamp;
2537 struct qla_tgt_sess *tgt_session;
2538 struct ct_sns_desc ct_desc;
2539 enum discovery_state disc_state;
2540 atomic_t shadow_disc_state;
2541 enum discovery_state next_disc_state;
2542 enum login_state fw_login_state;
2543 unsigned long dm_login_expire;
2544 unsigned long plogi_nack_done_deadline;
2546 u32 login_gen, last_login_gen;
2547 u32 rscn_gen, last_rscn_gen;
2549 struct list_head gnl_entry;
2550 struct work_struct del_work;
2552 u8 current_login_state;
2553 u8 last_login_state;
2554 u16 n2n_link_reset_cnt;
2557 struct dentry *dfs_rport_dir;
2561 FC4_PRIORITY_NVME = 1,
2562 FC4_PRIORITY_FCP = 2,
2565 #define QLA_FCPORT_SCAN 1
2566 #define QLA_FCPORT_FOUND 2
2573 u8 port_name[WWN_SIZE];
2580 * Fibre channel port/lun states.
2582 #define FCS_UNCONFIGURED 1
2583 #define FCS_DEVICE_DEAD 2
2584 #define FCS_DEVICE_LOST 3
2585 #define FCS_ONLINE 4
2587 extern const char *const port_state_str[5];
2589 static const char * const port_dstate_str[] = {
2605 #define FCF_FABRIC_DEVICE BIT_0
2606 #define FCF_LOGIN_NEEDED BIT_1
2607 #define FCF_FCP2_DEVICE BIT_2
2608 #define FCF_ASYNC_SENT BIT_3
2609 #define FCF_CONF_COMP_SUPPORTED BIT_4
2610 #define FCF_ASYNC_ACTIVE BIT_5
2612 /* No loop ID flag. */
2613 #define FC_NO_LOOP_ID 0x1000
2618 * NOTE: All structures are big-endian in form.
2621 #define CT_REJECT_RESPONSE 0x8001
2622 #define CT_ACCEPT_RESPONSE 0x8002
2623 #define CT_REASON_INVALID_COMMAND_CODE 0x01
2624 #define CT_REASON_CANNOT_PERFORM 0x09
2625 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2626 #define CT_EXPL_ALREADY_REGISTERED 0x10
2627 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
2628 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
2629 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
2630 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
2631 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
2632 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
2633 #define CT_EXPL_HBA_NOT_REGISTERED 0x17
2634 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
2635 #define CT_EXPL_PORT_NOT_REGISTERED 0x21
2636 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
2637 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
2639 #define NS_N_PORT_TYPE 0x01
2640 #define NS_NL_PORT_TYPE 0x02
2641 #define NS_NX_PORT_TYPE 0x7F
2643 #define GA_NXT_CMD 0x100
2644 #define GA_NXT_REQ_SIZE (16 + 4)
2645 #define GA_NXT_RSP_SIZE (16 + 620)
2647 #define GPN_FT_CMD 0x172
2648 #define GPN_FT_REQ_SIZE (16 + 4)
2649 #define GNN_FT_CMD 0x173
2650 #define GNN_FT_REQ_SIZE (16 + 4)
2652 #define GID_PT_CMD 0x1A1
2653 #define GID_PT_REQ_SIZE (16 + 4)
2655 #define GPN_ID_CMD 0x112
2656 #define GPN_ID_REQ_SIZE (16 + 4)
2657 #define GPN_ID_RSP_SIZE (16 + 8)
2659 #define GNN_ID_CMD 0x113
2660 #define GNN_ID_REQ_SIZE (16 + 4)
2661 #define GNN_ID_RSP_SIZE (16 + 8)
2663 #define GFT_ID_CMD 0x117
2664 #define GFT_ID_REQ_SIZE (16 + 4)
2665 #define GFT_ID_RSP_SIZE (16 + 32)
2667 #define GID_PN_CMD 0x121
2668 #define GID_PN_REQ_SIZE (16 + 8)
2669 #define GID_PN_RSP_SIZE (16 + 4)
2671 #define RFT_ID_CMD 0x217
2672 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
2673 #define RFT_ID_RSP_SIZE 16
2675 #define RFF_ID_CMD 0x21F
2676 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2677 #define RFF_ID_RSP_SIZE 16
2679 #define RNN_ID_CMD 0x213
2680 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
2681 #define RNN_ID_RSP_SIZE 16
2683 #define RSNN_NN_CMD 0x239
2684 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2685 #define RSNN_NN_RSP_SIZE 16
2687 #define GFPN_ID_CMD 0x11C
2688 #define GFPN_ID_REQ_SIZE (16 + 4)
2689 #define GFPN_ID_RSP_SIZE (16 + 8)
2691 #define GPSC_CMD 0x127
2692 #define GPSC_REQ_SIZE (16 + 8)
2693 #define GPSC_RSP_SIZE (16 + 2 + 2)
2695 #define GFF_ID_CMD 0x011F
2696 #define GFF_ID_REQ_SIZE (16 + 4)
2697 #define GFF_ID_RSP_SIZE (16 + 128)
2700 * FDMI HBA attribute types.
2702 #define FDMI1_HBA_ATTR_COUNT 9
2703 #define FDMI2_HBA_ATTR_COUNT 17
2705 #define FDMI_HBA_NODE_NAME 0x1
2706 #define FDMI_HBA_MANUFACTURER 0x2
2707 #define FDMI_HBA_SERIAL_NUMBER 0x3
2708 #define FDMI_HBA_MODEL 0x4
2709 #define FDMI_HBA_MODEL_DESCRIPTION 0x5
2710 #define FDMI_HBA_HARDWARE_VERSION 0x6
2711 #define FDMI_HBA_DRIVER_VERSION 0x7
2712 #define FDMI_HBA_OPTION_ROM_VERSION 0x8
2713 #define FDMI_HBA_FIRMWARE_VERSION 0x9
2714 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2715 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2717 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
2718 #define FDMI_HBA_VENDOR_SPECIFIC_INFO 0xd
2719 #define FDMI_HBA_NUM_PORTS 0xe
2720 #define FDMI_HBA_FABRIC_NAME 0xf
2721 #define FDMI_HBA_BOOT_BIOS_NAME 0x10
2722 #define FDMI_HBA_VENDOR_IDENTIFIER 0xe0
2724 struct ct_fdmi_hba_attr {
2728 uint8_t node_name[WWN_SIZE];
2729 uint8_t manufacturer[64];
2730 uint8_t serial_num[32];
2731 uint8_t model[16+1];
2732 uint8_t model_desc[80];
2733 uint8_t hw_version[32];
2734 uint8_t driver_version[32];
2735 uint8_t orom_version[16];
2736 uint8_t fw_version[32];
2737 uint8_t os_version[128];
2740 uint8_t sym_name[256];
2741 __be32 vendor_specific_info;
2743 uint8_t fabric_name[WWN_SIZE];
2744 uint8_t bios_name[32];
2745 uint8_t vendor_identifier[8];
2749 struct ct_fdmi1_hba_attributes {
2751 struct ct_fdmi_hba_attr entry[FDMI1_HBA_ATTR_COUNT];
2754 struct ct_fdmi2_hba_attributes {
2756 struct ct_fdmi_hba_attr entry[FDMI2_HBA_ATTR_COUNT];
2760 * FDMI Port attribute types.
2762 #define FDMI1_PORT_ATTR_COUNT 6
2763 #define FDMI2_PORT_ATTR_COUNT 16
2764 #define FDMI2_SMARTSAN_PORT_ATTR_COUNT 23
2766 #define FDMI_PORT_FC4_TYPES 0x1
2767 #define FDMI_PORT_SUPPORT_SPEED 0x2
2768 #define FDMI_PORT_CURRENT_SPEED 0x3
2769 #define FDMI_PORT_MAX_FRAME_SIZE 0x4
2770 #define FDMI_PORT_OS_DEVICE_NAME 0x5
2771 #define FDMI_PORT_HOST_NAME 0x6
2773 #define FDMI_PORT_NODE_NAME 0x7
2774 #define FDMI_PORT_NAME 0x8
2775 #define FDMI_PORT_SYM_NAME 0x9
2776 #define FDMI_PORT_TYPE 0xa
2777 #define FDMI_PORT_SUPP_COS 0xb
2778 #define FDMI_PORT_FABRIC_NAME 0xc
2779 #define FDMI_PORT_FC4_TYPE 0xd
2780 #define FDMI_PORT_STATE 0x101
2781 #define FDMI_PORT_COUNT 0x102
2782 #define FDMI_PORT_IDENTIFIER 0x103
2784 #define FDMI_SMARTSAN_SERVICE 0xF100
2785 #define FDMI_SMARTSAN_GUID 0xF101
2786 #define FDMI_SMARTSAN_VERSION 0xF102
2787 #define FDMI_SMARTSAN_PROD_NAME 0xF103
2788 #define FDMI_SMARTSAN_PORT_INFO 0xF104
2789 #define FDMI_SMARTSAN_QOS_SUPPORT 0xF105
2790 #define FDMI_SMARTSAN_SECURITY_SUPPORT 0xF106
2792 #define FDMI_PORT_SPEED_1GB 0x1
2793 #define FDMI_PORT_SPEED_2GB 0x2
2794 #define FDMI_PORT_SPEED_10GB 0x4
2795 #define FDMI_PORT_SPEED_4GB 0x8
2796 #define FDMI_PORT_SPEED_8GB 0x10
2797 #define FDMI_PORT_SPEED_16GB 0x20
2798 #define FDMI_PORT_SPEED_32GB 0x40
2799 #define FDMI_PORT_SPEED_64GB 0x80
2800 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
2802 #define FC_CLASS_2 0x04
2803 #define FC_CLASS_3 0x08
2804 #define FC_CLASS_2_3 0x0C
2806 struct ct_fdmi_port_attr {
2810 uint8_t fc4_types[32];
2813 __be32 max_frame_size;
2814 uint8_t os_dev_name[32];
2815 uint8_t host_name[256];
2817 uint8_t node_name[WWN_SIZE];
2818 uint8_t port_name[WWN_SIZE];
2819 uint8_t port_sym_name[128];
2821 __be32 port_supported_cos;
2822 uint8_t fabric_name[WWN_SIZE];
2823 uint8_t port_fc4_type[32];
2828 uint8_t smartsan_service[24];
2829 uint8_t smartsan_guid[16];
2830 uint8_t smartsan_version[24];
2831 uint8_t smartsan_prod_name[16];
2832 __be32 smartsan_port_info;
2833 __be32 smartsan_qos_support;
2834 __be32 smartsan_security_support;
2838 struct ct_fdmi1_port_attributes {
2840 struct ct_fdmi_port_attr entry[FDMI1_PORT_ATTR_COUNT];
2843 struct ct_fdmi2_port_attributes {
2845 struct ct_fdmi_port_attr entry[FDMI2_PORT_ATTR_COUNT];
2848 #define FDMI_ATTR_TYPELEN(obj) \
2849 (sizeof((obj)->type) + sizeof((obj)->len))
2851 #define FDMI_ATTR_ALIGNMENT(len) \
2854 /* FDMI register call options */
2855 #define CALLOPT_FDMI1 0
2856 #define CALLOPT_FDMI2 1
2857 #define CALLOPT_FDMI2_SMARTSAN 2
2859 /* FDMI definitions. */
2860 #define GRHL_CMD 0x100
2861 #define GHAT_CMD 0x101
2862 #define GRPL_CMD 0x102
2863 #define GPAT_CMD 0x110
2865 #define RHBA_CMD 0x200
2866 #define RHBA_RSP_SIZE 16
2868 #define RHAT_CMD 0x201
2870 #define RPRT_CMD 0x210
2871 #define RPRT_RSP_SIZE 24
2873 #define RPA_CMD 0x211
2874 #define RPA_RSP_SIZE 16
2875 #define SMARTSAN_RPA_RSP_SIZE 24
2877 #define DHBA_CMD 0x300
2878 #define DHBA_REQ_SIZE (16 + 8)
2879 #define DHBA_RSP_SIZE 16
2881 #define DHAT_CMD 0x301
2882 #define DPRT_CMD 0x310
2883 #define DPA_CMD 0x311
2885 /* CT command header -- request/response common fields */
2895 /* CT command request */
2897 struct ct_cmd_hdr header;
2899 __be16 max_rsp_size;
2900 uint8_t fragment_id;
2901 uint8_t reserved[3];
2904 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
2927 uint8_t fc4_types[32];
2934 uint8_t fc4_feature;
2941 uint8_t node_name[8];
2945 uint8_t node_name[8];
2947 uint8_t sym_node_name[255];
2951 uint8_t hba_identifier[8];
2955 uint8_t hba_identifier[8];
2957 uint8_t port_name[8];
2958 struct ct_fdmi2_hba_attributes attrs;
2962 uint8_t hba_identifier[8];
2963 struct ct_fdmi1_hba_attributes attrs;
2967 uint8_t port_name[8];
2968 struct ct_fdmi2_port_attributes attrs;
2972 uint8_t hba_identifier[8];
2973 uint8_t port_name[8];
2974 struct ct_fdmi2_port_attributes attrs;
2978 uint8_t port_name[8];
2982 uint8_t port_name[8];
2986 uint8_t port_name[8];
2990 uint8_t port_name[8];
2994 uint8_t port_name[8];
3003 uint8_t port_name[8];
3008 /* CT command response header */
3010 struct ct_cmd_hdr header;
3013 uint8_t fragment_id;
3014 uint8_t reason_code;
3015 uint8_t explanation_code;
3016 uint8_t vendor_unique;
3019 struct ct_sns_gid_pt_data {
3020 uint8_t control_byte;
3024 /* It's the same for both GPN_FT and GNN_FT */
3025 struct ct_sns_gpnft_rsp {
3027 struct ct_cmd_hdr header;
3030 uint8_t fragment_id;
3031 uint8_t reason_code;
3032 uint8_t explanation_code;
3033 uint8_t vendor_unique;
3035 /* Assume the largest number of targets for the union */
3036 struct ct_sns_gpn_ft_data {
3044 /* CT command response */
3046 struct ct_rsp_hdr header;
3052 uint8_t port_name[8];
3053 uint8_t sym_port_name_len;
3054 uint8_t sym_port_name[255];
3055 uint8_t node_name[8];
3056 uint8_t sym_node_name_len;
3057 uint8_t sym_node_name[255];
3058 uint8_t init_proc_assoc[8];
3059 uint8_t node_ip_addr[16];
3060 uint8_t class_of_service[4];
3061 uint8_t fc4_types[32];
3062 uint8_t ip_address[16];
3063 uint8_t fabric_port_name[8];
3065 uint8_t hard_address[3];
3069 /* Assume the largest number of targets for the union */
3070 struct ct_sns_gid_pt_data
3071 entries[MAX_FIBRE_DEVICES_MAX];
3075 uint8_t port_name[8];
3079 uint8_t node_name[8];
3083 uint8_t fc4_types[32];
3087 uint32_t entry_count;
3088 uint8_t port_name[8];
3089 struct ct_fdmi1_hba_attributes attrs;
3093 uint8_t port_name[8];
3101 #define GFF_FCP_SCSI_OFFSET 7
3102 #define GFF_NVME_OFFSET 23 /* type = 28h */
3104 uint8_t fc4_features[128];
3115 struct ct_sns_req req;
3116 struct ct_sns_rsp rsp;
3120 struct ct_sns_gpnft_pkt {
3122 struct ct_sns_req req;
3123 struct ct_sns_gpnft_rsp rsp;
3128 SF_SCANNING = BIT_0,
3133 FS_FC4TYPE_FCP = BIT_0,
3134 FS_FC4TYPE_NVME = BIT_1,
3135 FS_FCP_IS_N2N = BIT_7,
3138 struct fab_scan_rp {
3140 enum fc4type_t fc4type;
3146 struct fab_scan_rp *l;
3149 #define MAX_SCAN_RETRIES 5
3150 enum scan_flags_t scan_flags;
3151 struct delayed_work scan_work;
3155 * SNS command structures -- for 2200 compatibility.
3157 #define RFT_ID_SNS_SCMD_LEN 22
3158 #define RFT_ID_SNS_CMD_SIZE 60
3159 #define RFT_ID_SNS_DATA_SIZE 16
3161 #define RNN_ID_SNS_SCMD_LEN 10
3162 #define RNN_ID_SNS_CMD_SIZE 36
3163 #define RNN_ID_SNS_DATA_SIZE 16
3165 #define GA_NXT_SNS_SCMD_LEN 6
3166 #define GA_NXT_SNS_CMD_SIZE 28
3167 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
3169 #define GID_PT_SNS_SCMD_LEN 6
3170 #define GID_PT_SNS_CMD_SIZE 28
3172 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
3175 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
3177 #define GPN_ID_SNS_SCMD_LEN 6
3178 #define GPN_ID_SNS_CMD_SIZE 28
3179 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
3181 #define GNN_ID_SNS_SCMD_LEN 6
3182 #define GNN_ID_SNS_CMD_SIZE 28
3183 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
3185 struct sns_cmd_pkt {
3188 __le16 buffer_length;
3190 __le64 buffer_address __packed;
3191 __le16 subcommand_length;
3195 uint32_t reserved_3;
3199 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
3200 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
3201 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
3202 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
3203 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
3204 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
3211 const struct firmware *fw;
3214 /* Return data from MBC_GET_ID_LIST call. */
3215 struct gid_list_info {
3219 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
3220 __le16 loop_id; /* ISP23XX -- 6 bytes. */
3221 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
3225 typedef struct vport_info {
3226 uint8_t port_name[WWN_SIZE];
3227 uint8_t node_name[WWN_SIZE];
3230 unsigned long host_no;
3235 typedef struct vport_params {
3236 uint8_t port_name[WWN_SIZE];
3237 uint8_t node_name[WWN_SIZE];
3239 #define VP_OPTS_RETRY_ENABLE BIT_0
3240 #define VP_OPTS_VP_DISABLE BIT_1
3243 /* NPIV - return codes of VP create and modify */
3244 #define VP_RET_CODE_OK 0
3245 #define VP_RET_CODE_FATAL 1
3246 #define VP_RET_CODE_WRONG_ID 2
3247 #define VP_RET_CODE_WWPN 3
3248 #define VP_RET_CODE_RESOURCES 4
3249 #define VP_RET_CODE_NO_MEM 5
3250 #define VP_RET_CODE_NOT_FOUND 6
3257 struct isp_operations {
3259 int (*pci_config) (struct scsi_qla_host *);
3260 int (*reset_chip)(struct scsi_qla_host *);
3261 int (*chip_diag) (struct scsi_qla_host *);
3262 void (*config_rings) (struct scsi_qla_host *);
3263 int (*reset_adapter)(struct scsi_qla_host *);
3264 int (*nvram_config) (struct scsi_qla_host *);
3265 void (*update_fw_options) (struct scsi_qla_host *);
3266 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
3268 char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t);
3269 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
3271 irq_handler_t intr_handler;
3272 void (*enable_intrs) (struct qla_hw_data *);
3273 void (*disable_intrs) (struct qla_hw_data *);
3275 int (*abort_command) (srb_t *);
3276 int (*target_reset) (struct fc_port *, uint64_t, int);
3277 int (*lun_reset) (struct fc_port *, uint64_t, int);
3278 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
3279 uint8_t, uint8_t, uint16_t *, uint8_t);
3280 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
3283 uint16_t (*calc_req_entries) (uint16_t);
3284 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
3285 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *);
3286 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
3289 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *,
3290 uint32_t, uint32_t);
3291 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t,
3294 void (*fw_dump)(struct scsi_qla_host *vha);
3295 void (*mpi_fw_dump)(struct scsi_qla_host *, int);
3297 int (*beacon_on) (struct scsi_qla_host *);
3298 int (*beacon_off) (struct scsi_qla_host *);
3299 void (*beacon_blink) (struct scsi_qla_host *);
3301 void *(*read_optrom)(struct scsi_qla_host *, void *,
3302 uint32_t, uint32_t);
3303 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t,
3306 int (*get_flash_version) (struct scsi_qla_host *, void *);
3307 int (*start_scsi) (srb_t *);
3308 int (*start_scsi_mq) (srb_t *);
3309 int (*abort_isp) (struct scsi_qla_host *);
3310 int (*iospace_config)(struct qla_hw_data *);
3311 int (*initialize_adapter)(struct scsi_qla_host *);
3314 /* MSI-X Support *************************************************************/
3316 #define QLA_MSIX_CHIP_REV_24XX 3
3317 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
3318 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
3320 #define QLA_BASE_VECTORS 2 /* default + RSP */
3321 #define QLA_MSIX_RSP_Q 0x01
3322 #define QLA_ATIO_VECTOR 0x02
3323 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
3324 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q_HS 0x04
3326 #define QLA_MIDX_DEFAULT 0
3327 #define QLA_MIDX_RSP_Q 1
3328 #define QLA_PCI_MSIX_CONTROL 0xa2
3329 #define QLA_83XX_PCI_MSIX_CONTROL 0x92
3331 struct scsi_qla_host;
3334 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */
3336 struct qla_msix_entry {
3346 #define WATCH_INTERVAL 1 /* number of seconds */
3349 enum qla_work_type {
3352 QLA_EVT_ASYNC_LOGIN,
3353 QLA_EVT_ASYNC_LOGOUT,
3354 QLA_EVT_ASYNC_ADISC,
3367 QLA_EVT_ASYNC_PRLO_DONE,
3379 struct qla_work_evt {
3380 struct list_head list;
3381 enum qla_work_type type;
3383 #define QLA_EVT_FLAG_FREE 0x1
3387 enum fc_host_event_code code;
3391 #define QLA_IDC_ACK_REGS 7
3392 uint16_t mb[QLA_IDC_ACK_REGS];
3395 struct fc_port *fcport;
3396 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
3401 #define QLA_UEVENT_CODE_FW_DUMP 0
3421 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */
3437 struct qla_chip_state_84xx {
3438 struct list_head list;
3442 spinlock_t access_lock;
3443 struct mutex fw_update_mutex;
3445 uint32_t op_fw_version;
3446 uint32_t op_fw_size;
3447 uint32_t op_fw_seq_size;
3448 uint32_t diag_fw_version;
3449 uint32_t gold_fw_version;
3452 struct qla_dif_statistics {
3453 uint64_t dif_input_bytes;
3454 uint64_t dif_output_bytes;
3455 uint64_t dif_input_requests;
3456 uint64_t dif_output_requests;
3457 uint32_t dif_guard_err;
3458 uint32_t dif_ref_tag_err;
3459 uint32_t dif_app_tag_err;
3462 struct qla_statistics {
3463 uint32_t total_isp_aborts;
3464 uint64_t input_bytes;
3465 uint64_t output_bytes;
3466 uint64_t input_requests;
3467 uint64_t output_requests;
3468 uint32_t control_requests;
3470 uint64_t jiffies_at_last_reset;
3471 uint32_t stat_max_pend_cmds;
3472 uint32_t stat_max_qfull_cmds_alloc;
3473 uint32_t stat_max_qfull_cmds_dropped;
3475 struct qla_dif_statistics qla_dif_stats;
3478 struct bidi_statistics {
3479 unsigned long long io_count;
3480 unsigned long long transfer_bytes;
3483 struct qla_tc_param {
3484 struct scsi_qla_host *vha;
3487 struct scatterlist *sg;
3488 struct scatterlist *prot_sg;
3489 struct crc_context *ctx;
3490 uint8_t *ctx_dsd_alloced;
3493 /* Multi queue support */
3494 #define MBC_INITIALIZE_MULTIQ 0x1f
3495 #define QLA_QUE_PAGE 0X1000
3496 #define QLA_MQ_SIZE 32
3497 #define QLA_MAX_QUEUES 256
3498 #define ISP_QUE_REG(ha, id) \
3499 ((ha->mqenable || IS_QLA83XX(ha) || \
3500 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \
3501 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
3502 ((void __iomem *)ha->iobase))
3503 #define QLA_REQ_QUE_ID(tag) \
3504 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
3505 #define QLA_DEFAULT_QUE_QOS 5
3506 #define QLA_PRECONFIG_VPORTS 32
3507 #define QLA_MAX_VPORTS_QLA24XX 128
3508 #define QLA_MAX_VPORTS_QLA25XX 256
3510 struct qla_tgt_counters {
3511 uint64_t qla_core_sbt_cmd;
3512 uint64_t core_qla_que_buf;
3513 uint64_t qla_core_ret_ctio;
3514 uint64_t core_qla_snd_status;
3515 uint64_t qla_core_ret_sta_ctio;
3516 uint64_t core_qla_free_cmd;
3517 uint64_t num_q_full_sent;
3518 uint64_t num_alloc_iocb_failed;
3519 uint64_t num_term_xchg_sent;
3522 struct qla_counters {
3523 uint64_t input_bytes;
3524 uint64_t input_requests;
3525 uint64_t output_bytes;
3526 uint64_t output_requests;
3532 /* Response queue data structure */
3536 response_t *ring_ptr;
3537 __le32 __iomem *rsp_q_in; /* FWI2-capable only. */
3538 __le32 __iomem *rsp_q_out;
3539 uint16_t ring_index;
3541 uint16_t *in_ptr; /* queue shadow in index */
3547 struct qla_hw_data *hw;
3548 struct qla_msix_entry *msix;
3549 struct req_que *req;
3550 srb_t *status_srb; /* status continuation entry */
3551 struct qla_qpair *qpair;
3553 dma_addr_t dma_fx00;
3554 response_t *ring_fx00;
3555 uint16_t length_fx00;
3556 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
3559 /* Request queue data structure */
3563 request_t *ring_ptr;
3564 __le32 __iomem *req_q_in; /* FWI2-capable only. */
3565 __le32 __iomem *req_q_out;
3566 uint16_t ring_index;
3568 uint16_t *out_ptr; /* queue shadow out index */
3576 struct rsp_que *rsp;
3577 srb_t **outstanding_cmds;
3578 uint32_t current_outstanding_cmd;
3579 uint16_t num_outstanding_cmds;
3582 dma_addr_t dma_fx00;
3583 request_t *ring_fx00;
3584 uint16_t length_fx00;
3585 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
3588 struct qla_fw_resources {
3595 #define QLA_IOCB_PCT_LIMIT 95
3597 /*Queue pair data structure */
3603 * For qpair 0, qp_lock_ptr will point at hardware_lock due to
3604 * legacy code. For other Qpair(s), it will point at qp_lock.
3606 spinlock_t *qp_lock_ptr;
3607 struct scsi_qla_host *vha;
3610 /* distill these fields down to 'online=0/1'
3611 * ha->flags.eeh_busy
3612 * ha->flags.pci_channel_io_perm_failure
3613 * base_vha->loop_state
3616 /* move vha->flags.difdix_supported here */
3617 uint32_t difdix_supported:1;
3618 uint32_t delete_in_progress:1;
3619 uint32_t fw_started:1;
3620 uint32_t enable_class_2:1;
3621 uint32_t enable_explicit_conf:1;
3622 uint32_t use_shadow_reg:1;
3623 uint32_t rcv_intr:1;
3625 uint16_t id; /* qp number used with FW */
3626 uint16_t vp_idx; /* vport ID */
3627 mempool_t *srb_mempool;
3629 struct pci_dev *pdev;
3630 void (*reqq_start_iocbs)(struct qla_qpair *);
3632 /* to do: New driver: move queues to here instead of pointers */
3633 struct req_que *req;
3634 struct rsp_que *rsp;
3635 struct atio_que *atio;
3636 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */
3637 struct qla_hw_data *hw;
3638 struct work_struct q_work;
3639 struct qla_counters counters;
3641 struct list_head qp_list_elem; /* vha->qp_list */
3642 struct list_head hints_list;
3644 uint16_t retry_term_cnt;
3645 __le32 retry_term_exchg_addr;
3646 uint64_t retry_term_jiff;
3647 struct qla_tgt_counters tgt_counters;
3649 struct qla_fw_resources fwres ____cacheline_aligned;
3652 /* Place holder for FW buffer parameters */
3659 struct rdp_req_payload {
3660 uint32_t els_request;
3661 uint32_t desc_list_len;
3663 /* NPIV descriptor */
3668 uint8_t nport_id[3];
3672 struct rdp_rsp_payload {
3678 /* LS Request Info descriptor */
3682 __be32 req_payload_word_0;
3685 /* LS Request Info descriptor */
3689 __be32 req_payload_word_0;
3690 } ls_req_info_desc2;
3692 /* SFP diagnostic param descriptor */
3704 /* Port Speed Descriptor */
3709 __be16 operating_speed;
3712 /* Link Error Status Descriptor */
3716 __be32 link_fail_cnt;
3717 __be32 loss_sync_cnt;
3718 __be32 loss_sig_cnt;
3719 __be32 prim_seq_err_cnt;
3720 __be32 inval_xmit_word_cnt;
3721 __be32 inval_crc_cnt;
3722 uint8_t pn_port_phy_type;
3723 uint8_t reserved[3];
3726 /* Port name description with diag param */
3730 uint8_t WWNN[WWN_SIZE];
3731 uint8_t WWPN[WWN_SIZE];
3732 } port_name_diag_desc;
3734 /* Port Name desc for Direct attached Fx_Port or Nx_Port */
3738 uint8_t WWNN[WWN_SIZE];
3739 uint8_t WWPN[WWN_SIZE];
3740 } port_name_direct_desc;
3742 /* Buffer Credit descriptor */
3747 __be32 attached_fcport_b2b;
3749 } buffer_credit_desc;
3751 /* Optical Element Data Descriptor */
3759 __be32 element_flags;
3760 } optical_elmt_desc[5];
3762 /* Optical Product Data Descriptor */
3766 uint8_t vendor_name[16];
3767 uint8_t part_number[16];
3768 uint8_t serial_number[16];
3769 uint8_t revision[4];
3771 } optical_prod_desc;
3774 #define RDP_DESC_LEN(obj) \
3775 (sizeof(obj) - sizeof((obj).desc_tag) - sizeof((obj).desc_len))
3777 #define RDP_PORT_SPEED_1GB BIT_15
3778 #define RDP_PORT_SPEED_2GB BIT_14
3779 #define RDP_PORT_SPEED_4GB BIT_13
3780 #define RDP_PORT_SPEED_10GB BIT_12
3781 #define RDP_PORT_SPEED_8GB BIT_11
3782 #define RDP_PORT_SPEED_16GB BIT_10
3783 #define RDP_PORT_SPEED_32GB BIT_9
3784 #define RDP_PORT_SPEED_64GB BIT_8
3785 #define RDP_PORT_SPEED_UNKNOWN BIT_0
3787 struct scsi_qlt_host {
3788 void *target_lport_ptr;
3789 struct mutex tgt_mutex;
3790 struct mutex tgt_host_action_mutex;
3791 struct qla_tgt *qla_tgt;
3794 struct qlt_hw_data {
3795 /* Protected by hw lock */
3796 uint32_t node_name_set:1;
3798 dma_addr_t atio_dma; /* Physical address. */
3799 struct atio *atio_ring; /* Base virtual address */
3800 struct atio *atio_ring_ptr; /* Current address. */
3801 uint16_t atio_ring_index; /* Current index. */
3802 uint16_t atio_q_length;
3803 __le32 __iomem *atio_q_in;
3804 __le32 __iomem *atio_q_out;
3806 struct qla_tgt_func_tmpl *tgt_ops;
3807 struct qla_tgt_vp_map *tgt_vp_map;
3810 __le16 saved_exchange_count;
3811 __le32 saved_firmware_options_1;
3812 __le32 saved_firmware_options_2;
3813 __le32 saved_firmware_options_3;
3814 uint8_t saved_firmware_options[2];
3815 uint8_t saved_add_firmware_options[2];
3817 uint8_t tgt_node_name[WWN_SIZE];
3819 struct dentry *dfs_tgt_sess;
3820 struct dentry *dfs_tgt_port_database;
3821 struct dentry *dfs_naqp;
3823 struct list_head q_full_list;
3824 uint32_t num_pend_cmds;
3825 uint32_t num_qfull_cmds_alloc;
3826 uint32_t num_qfull_cmds_dropped;
3827 spinlock_t q_full_lock;
3828 uint32_t leak_exchg_thresh_hold;
3829 spinlock_t sess_lock;
3831 #define DEFAULT_NAQP 2
3832 spinlock_t atio_lock ____cacheline_aligned;
3833 struct btree_head32 host_map;
3836 #define MAX_QFULL_CMDS_ALLOC 8192
3837 #define Q_FULL_THRESH_HOLD_PERCENT 90
3838 #define Q_FULL_THRESH_HOLD(ha) \
3839 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
3841 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */
3843 struct qla_hw_data_stat {
3849 * Qlogic host adapter specific data structure.
3851 struct qla_hw_data {
3852 struct pci_dev *pdev;
3854 #define SRB_MIN_REQ 128
3855 mempool_t *srb_mempool;
3858 uint32_t mbox_int :1;
3859 uint32_t mbox_busy :1;
3860 uint32_t disable_risc_code_load :1;
3861 uint32_t enable_64bit_addressing :1;
3862 uint32_t enable_lip_reset :1;
3863 uint32_t enable_target_reset :1;
3864 uint32_t enable_lip_full_login :1;
3865 uint32_t enable_led_scheme :1;
3867 uint32_t msi_enabled :1;
3868 uint32_t msix_enabled :1;
3869 uint32_t disable_serdes :1;
3870 uint32_t gpsc_supported :1;
3871 uint32_t npiv_supported :1;
3872 uint32_t pci_channel_io_perm_failure :1;
3873 uint32_t fce_enabled :1;
3874 uint32_t fac_supported :1;
3876 uint32_t chip_reset_done :1;
3877 uint32_t running_gold_fw :1;
3878 uint32_t eeh_busy :1;
3879 uint32_t disable_msix_handshake :1;
3880 uint32_t fcp_prio_enabled :1;
3881 uint32_t isp82xx_fw_hung:1;
3882 uint32_t nic_core_hung:1;
3884 uint32_t quiesce_owner:1;
3885 uint32_t nic_core_reset_hdlr_active:1;
3886 uint32_t nic_core_reset_owner:1;
3887 uint32_t isp82xx_no_md_cap:1;
3888 uint32_t host_shutting_down:1;
3889 uint32_t idc_compl_status:1;
3890 uint32_t mr_reset_hdlr_active:1;
3891 uint32_t mr_intr_valid:1;
3893 uint32_t dport_enabled:1;
3894 uint32_t fawwpn_enabled:1;
3895 uint32_t exlogins_enabled:1;
3896 uint32_t exchoffld_enabled:1;
3900 uint32_t fw_started:1;
3901 uint32_t fw_init_done:1;
3903 uint32_t lr_detected:1;
3905 uint32_t rida_fmt2:1;
3906 uint32_t purge_mbox:1;
3907 uint32_t n2n_bigger:1;
3908 uint32_t secure_adapter:1;
3909 uint32_t secure_fw:1;
3910 /* Supported by Adapter */
3911 uint32_t scm_supported_a:1;
3912 /* Supported by Firmware */
3913 uint32_t scm_supported_f:1;
3914 /* Enabled in Driver */
3915 uint32_t scm_enabled:1;
3916 uint32_t max_req_queue_warned:1;
3917 uint32_t plogi_template_valid:1;
3921 uint16_t lr_distance; /* 32G & above */
3922 #define LR_DISTANCE_5K 1
3923 #define LR_DISTANCE_10K 0
3925 /* This spinlock is used to protect "io transactions", you must
3926 * acquire it before doing any IO to the card, eg with RD_REG*() and
3927 * WRT_REG*() for the duration of your entire commandtransaction.
3929 * This spinlock is of lower priority than the io request lock.
3932 spinlock_t hardware_lock ____cacheline_aligned;
3935 device_reg_t *iobase; /* Base I/O address */
3936 resource_size_t pio_address;
3938 #define MIN_IOBASE_LEN 0x100
3939 dma_addr_t bar0_hdl;
3941 void __iomem *cregbase;
3942 dma_addr_t bar2_hdl;
3943 #define BAR0_LEN_FX00 (1024 * 1024)
3944 #define BAR2_LEN_FX00 (128 * 1024)
3946 uint32_t rqstq_intr_code;
3947 uint32_t mbx_intr_code;
3948 uint32_t req_que_len;
3949 uint32_t rsp_que_len;
3950 uint32_t req_que_off;
3951 uint32_t rsp_que_off;
3953 /* Multi queue data structs */
3954 device_reg_t *mqiobase;
3955 device_reg_t *msixbase;
3956 uint16_t msix_count;
3958 struct req_que **req_q_map;
3959 struct rsp_que **rsp_q_map;
3960 struct qla_qpair **queue_pair_map;
3961 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3962 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3963 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
3964 / sizeof(unsigned long)];
3965 uint8_t max_req_queues;
3966 uint8_t max_rsp_queues;
3969 struct qla_qpair *base_qpair;
3970 struct qla_npiv_entry *npiv_info;
3971 uint16_t nvram_npiv_size;
3973 uint16_t switch_cap;
3974 #define FLOGI_SEQ_DEL BIT_8
3975 #define FLOGI_MID_SUPPORT BIT_10
3976 #define FLOGI_VSAN_SUPPORT BIT_12
3977 #define FLOGI_SP_SUPPORT BIT_13
3979 uint8_t port_no; /* Physical port of adapter */
3980 uint8_t exch_starvation;
3982 /* Timeout timers. */
3983 uint8_t loop_down_abort_time; /* port down timer */
3984 atomic_t loop_down_timer; /* loop down timer */
3985 uint8_t link_down_timeout; /* link down timeout */
3986 uint16_t max_loop_id;
3987 uint16_t max_fibre_devices; /* Maximum number of targets */
3990 uint16_t min_external_loopid; /* First external loop Id */
3992 #define PORT_SPEED_UNKNOWN 0xFFFF
3993 #define PORT_SPEED_1GB 0x00
3994 #define PORT_SPEED_2GB 0x01
3995 #define PORT_SPEED_AUTO 0x02
3996 #define PORT_SPEED_4GB 0x03
3997 #define PORT_SPEED_8GB 0x04
3998 #define PORT_SPEED_16GB 0x05
3999 #define PORT_SPEED_32GB 0x06
4000 #define PORT_SPEED_64GB 0x07
4001 #define PORT_SPEED_10GB 0x13
4002 uint16_t link_data_rate; /* F/W operating speed */
4003 uint16_t set_data_rate; /* Set by user */
4005 uint8_t current_topology;
4006 uint8_t prev_topology;
4007 #define ISP_CFG_NL 1
4009 #define ISP_CFG_FL 4
4012 uint8_t operating_mode; /* F/W operating mode */
4017 uint8_t interrupts_on;
4018 uint32_t isp_abort_cnt;
4019 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
4020 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
4021 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
4022 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
4023 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
4024 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
4025 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
4026 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
4027 #define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061
4028 #define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081
4029 #define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089
4030 #define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281
4031 #define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289
4034 #define DT_ISP2100 BIT_0
4035 #define DT_ISP2200 BIT_1
4036 #define DT_ISP2300 BIT_2
4037 #define DT_ISP2312 BIT_3
4038 #define DT_ISP2322 BIT_4
4039 #define DT_ISP6312 BIT_5
4040 #define DT_ISP6322 BIT_6
4041 #define DT_ISP2422 BIT_7
4042 #define DT_ISP2432 BIT_8
4043 #define DT_ISP5422 BIT_9
4044 #define DT_ISP5432 BIT_10
4045 #define DT_ISP2532 BIT_11
4046 #define DT_ISP8432 BIT_12
4047 #define DT_ISP8001 BIT_13
4048 #define DT_ISP8021 BIT_14
4049 #define DT_ISP2031 BIT_15
4050 #define DT_ISP8031 BIT_16
4051 #define DT_ISPFX00 BIT_17
4052 #define DT_ISP8044 BIT_18
4053 #define DT_ISP2071 BIT_19
4054 #define DT_ISP2271 BIT_20
4055 #define DT_ISP2261 BIT_21
4056 #define DT_ISP2061 BIT_22
4057 #define DT_ISP2081 BIT_23
4058 #define DT_ISP2089 BIT_24
4059 #define DT_ISP2281 BIT_25
4060 #define DT_ISP2289 BIT_26
4061 #define DT_ISP_LAST (DT_ISP2289 << 1)
4063 uint32_t device_type;
4064 #define DT_T10_PI BIT_25
4065 #define DT_IIDMA BIT_26
4066 #define DT_FWI2 BIT_27
4067 #define DT_ZIO_SUPPORTED BIT_28
4068 #define DT_OEM_001 BIT_29
4069 #define DT_ISP2200A BIT_30
4070 #define DT_EXTENDED_IDS BIT_31
4072 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
4073 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
4074 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
4075 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
4076 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
4077 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
4078 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
4079 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
4080 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
4081 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
4082 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
4083 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
4084 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
4085 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
4086 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
4087 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
4088 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
4089 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
4090 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
4091 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
4092 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
4093 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
4094 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
4095 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
4096 #define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081)
4097 #define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281)
4099 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
4100 IS_QLA6312(ha) || IS_QLA6322(ha))
4101 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
4102 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
4103 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
4104 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
4105 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
4106 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
4107 #define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha))
4108 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
4110 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
4111 IS_QLA8031(ha) || IS_QLA8044(ha))
4112 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
4113 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
4114 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
4115 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
4116 IS_QLA8044(ha) || IS_QLA27XX(ha) || \
4118 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4119 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4120 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
4121 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4122 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4123 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4124 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4125 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
4127 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
4128 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
4129 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
4130 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
4131 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
4132 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
4133 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
4134 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
4135 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4136 #define IS_BIDI_CAPABLE(ha) \
4137 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4138 /* Bit 21 of fw_attributes decides the MCTP capabilities */
4139 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
4140 ((ha)->fw_attributes_ext[0] & BIT_0))
4141 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
4142 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
4143 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
4144 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4146 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
4147 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
4148 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4150 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
4151 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha))
4152 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4154 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4156 #define IS_EXCHG_OFFLD_CAPABLE(ha) \
4157 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4158 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
4159 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4160 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4161 #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\
4162 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4164 #define IS_ZIO_THRESHOLD_CAPABLE(ha) \
4165 ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&\
4166 (ha->zio_mode == QLA_ZIO_MODE_6))
4168 /* HBA serial number */
4173 /* NVRAM configuration data */
4174 #define MAX_NVRAM_SIZE 4096
4175 #define VPD_OFFSET (MAX_NVRAM_SIZE / 2)
4176 uint16_t nvram_size;
4177 uint16_t nvram_base;
4183 uint16_t loop_reset_delay;
4184 uint8_t retry_count;
4185 uint8_t login_timeout;
4187 int port_down_retry_count;
4189 uint8_t aen_mbx_count;
4190 atomic_t num_pend_mbx_stage1;
4191 atomic_t num_pend_mbx_stage2;
4192 atomic_t num_pend_mbx_stage3;
4193 uint16_t frame_payload_size;
4195 uint32_t login_retry_count;
4196 /* SNS command interfaces. */
4197 ms_iocb_entry_t *ms_iocb;
4198 dma_addr_t ms_iocb_dma;
4199 struct ct_sns_pkt *ct_sns;
4200 dma_addr_t ct_sns_dma;
4201 /* SNS command interfaces for 2200. */
4202 struct sns_cmd_pkt *sns_cmd;
4203 dma_addr_t sns_cmd_dma;
4205 #define SFP_DEV_SIZE 512
4206 #define SFP_BLOCK_SIZE 64
4207 #define SFP_RTDI_LEN SFP_BLOCK_SIZE
4210 dma_addr_t sfp_data_dma;
4212 struct qla_flt_header *flt;
4215 #define XGMAC_DATA_SIZE 4096
4217 dma_addr_t xgmac_data_dma;
4219 #define DCBX_TLV_DATA_SIZE 4096
4221 dma_addr_t dcbx_tlv_dma;
4223 struct task_struct *dpc_thread;
4224 uint8_t dpc_active; /* DPC routine is active */
4226 dma_addr_t gid_list_dma;
4227 struct gid_list_info *gid_list;
4228 int gid_list_info_size;
4230 /* Small DMA pool allocations -- maximum 256 bytes in length. */
4231 #define DMA_POOL_SIZE 256
4232 struct dma_pool *s_dma_pool;
4234 dma_addr_t init_cb_dma;
4237 dma_addr_t ex_init_cb_dma;
4238 struct ex_init_cb_81xx *ex_init_cb;
4239 dma_addr_t sf_init_cb_dma;
4240 struct init_sf_cb *sf_init_cb;
4242 void *scm_fpin_els_buff;
4243 uint64_t scm_fpin_els_buff_size;
4244 bool scm_fpin_valid;
4245 bool scm_fpin_payload_size;
4248 dma_addr_t async_pd_dma;
4250 #define ENABLE_EXTENDED_LOGIN BIT_7
4252 /* Extended Logins */
4254 dma_addr_t exlogin_buf_dma;
4255 uint32_t exlogin_size;
4257 #define ENABLE_EXCHANGE_OFFLD BIT_2
4259 /* Exchange Offload */
4260 void *exchoffld_buf;
4261 dma_addr_t exchoffld_buf_dma;
4263 int exchoffld_count;
4266 struct fc_els_flogi plogi_els_payld;
4267 #define LOGIN_TEMPLATE_SIZE (sizeof(struct fc_els_flogi) - 4)
4271 /* These are used by mailbox operations. */
4272 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
4273 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
4274 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
4277 struct mbx_cmd_32 *mcp32;
4279 unsigned long mbx_cmd_flags;
4280 #define MBX_INTERRUPT 1
4281 #define MBX_INTR_WAIT 2
4282 #define MBX_UPDATE_FLASH_ACTIVE 3
4284 struct mutex vport_lock; /* Virtual port synchronization */
4285 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
4286 struct mutex mq_lock; /* multi-queue synchronization */
4287 struct completion mbx_cmd_comp; /* Serialize mbx access */
4288 struct completion mbx_intr_comp; /* Used for completion notification */
4289 struct completion dcbx_comp; /* For set port config notification */
4290 struct completion lb_portup_comp; /* Used to wait for link up during
4292 #define DCBX_COMP_TIMEOUT 20
4293 #define LB_PORTUP_COMP_TIMEOUT 10
4295 int notify_dcbx_comp;
4296 int notify_lb_portup_comp;
4297 struct mutex selflogin_lock;
4299 /* Basic firmware related information. */
4300 uint16_t fw_major_version;
4301 uint16_t fw_minor_version;
4302 uint16_t fw_subminor_version;
4303 uint16_t fw_attributes;
4304 uint16_t fw_attributes_h;
4305 #define FW_ATTR_H_NVME_FBURST BIT_1
4306 #define FW_ATTR_H_NVME BIT_10
4307 #define FW_ATTR_H_NVME_UPDATED BIT_14
4309 /* About firmware SCM support */
4310 #define FW_ATTR_EXT0_SCM_SUPPORTED BIT_12
4311 /* Brocade fabric attached */
4312 #define FW_ATTR_EXT0_SCM_BROCADE 0x00001000
4313 /* Cisco fabric attached */
4314 #define FW_ATTR_EXT0_SCM_CISCO 0x00002000
4315 #define FW_ATTR_EXT0_NVME2 BIT_13
4316 uint16_t fw_attributes_ext[2];
4317 uint32_t fw_memory_size;
4318 uint32_t fw_transfer_size;
4319 uint32_t fw_srisc_address;
4320 #define RISC_START_ADDRESS_2100 0x1000
4321 #define RISC_START_ADDRESS_2300 0x800
4322 #define RISC_START_ADDRESS_2400 0x100000
4324 uint16_t orig_fw_tgt_xcb_count;
4325 uint16_t cur_fw_tgt_xcb_count;
4326 uint16_t orig_fw_xcb_count;
4327 uint16_t cur_fw_xcb_count;
4328 uint16_t orig_fw_iocb_count;
4329 uint16_t cur_fw_iocb_count;
4330 uint16_t fw_max_fcf_count;
4332 uint32_t fw_shared_ram_start;
4333 uint32_t fw_shared_ram_end;
4334 uint32_t fw_ddr_ram_start;
4335 uint32_t fw_ddr_ram_end;
4337 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
4338 uint8_t fw_seriallink_options[4];
4339 __le16 fw_seriallink_options24[4];
4341 uint8_t serdes_version[3];
4342 uint8_t mpi_version[3];
4343 uint32_t mpi_capabilities;
4344 uint8_t phy_version[3];
4345 uint8_t pep_version[3];
4347 /* Firmware dump template */
4353 struct qla2xxx_fw_dump *fw_dump;
4354 uint32_t fw_dump_len;
4355 u32 fw_dump_alloc_len;
4357 unsigned long fw_dump_cap_flags;
4358 #define RISC_PAUSE_CMPL 0
4359 #define DMA_SHUTDOWN_CMPL 1
4360 #define ISP_RESET_CMPL 2
4361 #define RISC_RDY_AFT_RESET 3
4362 #define RISC_SRAM_DUMP_CMPL 4
4363 #define RISC_EXT_MEM_DUMP_CMPL 5
4364 #define ISP_MBX_RDY 6
4365 #define ISP_SOFT_RESET_CMPL 7
4366 int fw_dump_reading;
4368 u32 mpi_fw_dump_len;
4369 unsigned int mpi_fw_dump_reading:1;
4370 unsigned int mpi_fw_dumped:1;
4371 int prev_minidump_failed;
4374 /* Current size of mctp dump is 0x086064 bytes */
4375 #define MCTP_DUMP_SIZE 0x086064
4376 dma_addr_t mctp_dump_dma;
4379 int mctp_dump_reading;
4380 uint32_t chain_offset;
4381 struct dentry *dfs_dir;
4382 struct dentry *dfs_fce;
4383 struct dentry *dfs_tgt_counters;
4384 struct dentry *dfs_fw_resource_cnt;
4390 uint64_t fce_wr, fce_rd;
4391 struct mutex fce_mutex;
4394 uint16_t chip_revision;
4396 uint16_t product_id[4];
4398 uint8_t model_number[16+1];
4399 char model_desc[80];
4400 uint8_t adapter_id[16+1];
4402 /* Option ROM information. */
4403 char *optrom_buffer;
4404 uint32_t optrom_size;
4406 #define QLA_SWAITING 0
4407 #define QLA_SREADING 1
4408 #define QLA_SWRITING 2
4409 uint32_t optrom_region_start;
4410 uint32_t optrom_region_size;
4411 struct mutex optrom_mutex;
4413 /* PCI expansion ROM image information. */
4414 #define ROM_CODE_TYPE_BIOS 0
4415 #define ROM_CODE_TYPE_FCODE 1
4416 #define ROM_CODE_TYPE_EFI 3
4417 uint8_t bios_revision[2];
4418 uint8_t efi_revision[2];
4419 uint8_t fcode_revision[16];
4420 uint32_t fw_revision[4];
4422 uint32_t gold_fw_version[4];
4424 /* Offsets for flash/nvram access (set to ~0 if not used). */
4425 uint32_t flash_conf_off;
4426 uint32_t flash_data_off;
4427 uint32_t nvram_conf_off;
4428 uint32_t nvram_data_off;
4430 uint32_t fdt_wrt_disable;
4431 uint32_t fdt_wrt_enable;
4432 uint32_t fdt_erase_cmd;
4433 uint32_t fdt_block_size;
4434 uint32_t fdt_unprotect_sec_cmd;
4435 uint32_t fdt_protect_sec_cmd;
4436 uint32_t fdt_wrt_sts_reg_cmd;
4439 uint32_t flt_region_flt;
4440 uint32_t flt_region_fdt;
4441 uint32_t flt_region_boot;
4442 uint32_t flt_region_boot_sec;
4443 uint32_t flt_region_fw;
4444 uint32_t flt_region_fw_sec;
4445 uint32_t flt_region_vpd_nvram;
4446 uint32_t flt_region_vpd_nvram_sec;
4447 uint32_t flt_region_vpd;
4448 uint32_t flt_region_vpd_sec;
4449 uint32_t flt_region_nvram;
4450 uint32_t flt_region_nvram_sec;
4451 uint32_t flt_region_npiv_conf;
4452 uint32_t flt_region_gold_fw;
4453 uint32_t flt_region_fcp_prio;
4454 uint32_t flt_region_bootload;
4455 uint32_t flt_region_img_status_pri;
4456 uint32_t flt_region_img_status_sec;
4457 uint32_t flt_region_aux_img_status_pri;
4458 uint32_t flt_region_aux_img_status_sec;
4460 uint8_t active_image;
4462 /* Needed for BEACON */
4463 uint16_t beacon_blink_led;
4464 uint8_t beacon_color_state;
4465 #define QLA_LED_GRN_ON 0x01
4466 #define QLA_LED_YLW_ON 0x02
4467 #define QLA_LED_ABR_ON 0x04
4468 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
4469 /* ISP2322: red, green, amber. */
4473 struct qla_msix_entry *msix_entries;
4475 struct list_head vp_list; /* list of VP */
4476 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
4477 sizeof(unsigned long)];
4478 uint16_t num_vhosts; /* number of vports created */
4479 uint16_t num_vsans; /* number of vsan created */
4480 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
4481 int cur_vport_count;
4483 struct qla_chip_state_84xx *cs84xx;
4484 struct isp_operations *isp_ops;
4485 struct workqueue_struct *wq;
4486 struct qlfc_fw fw_buf;
4488 /* FCP_CMND priority support */
4489 struct qla_fcp_prio_cfg *fcp_prio_cfg;
4491 struct dma_pool *dl_dma_pool;
4492 #define DSD_LIST_DMA_POOL_SIZE 512
4494 struct dma_pool *fcp_cmnd_dma_pool;
4495 mempool_t *ctx_mempool;
4496 #define FCP_CMND_DMA_POOL_SIZE 512
4498 void __iomem *nx_pcibase; /* Base I/O address */
4499 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */
4500 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */
4503 uint32_t curr_window;
4504 uint32_t ddr_mn_window;
4505 unsigned long mn_win_crb;
4506 unsigned long ms_win_crb;
4508 uint32_t fcoe_dev_init_timeout;
4509 uint32_t fcoe_reset_timeout;
4511 uint16_t portnum; /* port number */
4513 struct fw_blob *hablob;
4514 struct qla82xx_legacy_intr_set nx_legacy_intr;
4516 uint16_t gbl_dsd_inuse;
4517 uint16_t gbl_dsd_avail;
4518 struct list_head gbl_dsd_list;
4519 #define NUM_DSD_CHAIN 4096
4522 uint32_t file_prd_off; /* File firmware product offset */
4524 uint32_t md_template_size;
4526 dma_addr_t md_tmplt_hdr_dma;
4528 uint32_t md_dump_size;
4532 /* QLA83XX IDC specific fields */
4533 uint32_t idc_audit_ts;
4534 uint32_t idc_extend_tmo;
4536 /* DPC low-priority workqueue */
4537 struct workqueue_struct *dpc_lp_wq;
4538 struct work_struct idc_aen;
4539 /* DPC high-priority workqueue */
4540 struct workqueue_struct *dpc_hp_wq;
4541 struct work_struct nic_core_reset;
4542 struct work_struct idc_state_handler;
4543 struct work_struct nic_core_unrecoverable;
4544 struct work_struct board_disable;
4546 struct mr_data_fx00 mr;
4547 uint32_t chip_reset;
4549 struct qlt_hw_data tgt;
4550 int allow_cna_fw_dump;
4551 uint32_t fw_ability_mask;
4552 uint16_t min_supported_speed;
4553 uint16_t max_supported_speed;
4555 /* DMA pool for the DIF bundling buffers */
4556 struct dma_pool *dif_bundl_pool;
4557 #define DIF_BUNDLING_DMA_POOL_SIZE 1024
4560 struct list_head head;
4564 struct list_head head;
4569 unsigned long long dif_bundle_crossed_pages;
4570 unsigned long long dif_bundle_reads;
4571 unsigned long long dif_bundle_writes;
4572 unsigned long long dif_bundle_kallocs;
4573 unsigned long long dif_bundle_dma_allocs;
4575 atomic_t nvme_active_aen_cnt;
4576 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */
4578 uint8_t fc4_type_priority;
4580 atomic_t zio_threshold;
4581 uint16_t last_zio_threshold;
4583 #define DEFAULT_ZIO_THRESHOLD 5
4585 struct qla_hw_data_stat stat;
4588 struct active_regions {
4591 uint8_t board_config;
4593 uint8_t npiv_config_0_1;
4594 uint8_t npiv_config_2_3;
4598 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL
4599 #define FW_ABILITY_MAX_SPEED_16G 0x0
4600 #define FW_ABILITY_MAX_SPEED_32G 0x1
4601 #define FW_ABILITY_MAX_SPEED(ha) \
4602 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK)
4604 #define QLA_GET_DATA_RATE 0
4605 #define QLA_SET_DATA_RATE_NOLR 1
4606 #define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */
4608 #define QLA_DEFAULT_PAYLOAD_SIZE 64
4610 * This item might be allocated with a size > sizeof(struct purex_item).
4611 * The "size" variable gives the size of the payload (which
4612 * is variable) starting at "iocb".
4615 struct list_head list;
4616 struct scsi_qla_host *vha;
4617 void (*process_item)(struct scsi_qla_host *vha,
4618 struct purex_item *pkt);
4626 #define SCM_FLAG_RDF_REJECT 0x00
4627 #define SCM_FLAG_RDF_COMPLETED 0x01
4629 #define QLA_CON_PRIMITIVE_RECEIVED 0x1
4630 #define QLA_CONGESTION_ARB_WARNING 0x1
4631 #define QLA_CONGESTION_ARB_ALARM 0X2
4634 * Qlogic scsi host structure
4636 typedef struct scsi_qla_host {
4637 struct list_head list;
4638 struct list_head vp_fcports; /* list of fcports */
4639 struct list_head work_list;
4640 spinlock_t work_lock;
4641 struct work_struct iocb_work;
4643 /* Commonly used flags and state information. */
4644 struct Scsi_Host *host;
4645 unsigned long host_no;
4646 uint8_t host_str[16];
4649 uint32_t init_done :1;
4651 uint32_t reset_active :1;
4653 uint32_t management_server_logged_in :1;
4654 uint32_t process_response_queue :1;
4655 uint32_t difdix_supported:1;
4656 uint32_t delete_progress:1;
4658 uint32_t fw_tgt_reported:1;
4659 uint32_t bbcr_enable:1;
4660 uint32_t qpairs_available:1;
4661 uint32_t qpairs_req_created:1;
4662 uint32_t qpairs_rsp_created:1;
4663 uint32_t nvme_enabled:1;
4664 uint32_t nvme_first_burst:1;
4665 uint32_t nvme2_enabled:1;
4668 atomic_t loop_state;
4669 #define LOOP_TIMEOUT 1
4672 #define LOOP_UPDATE 4
4673 #define LOOP_READY 5
4676 unsigned long relogin_jif;
4677 unsigned long dpc_flags;
4678 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
4679 #define RESET_ACTIVE 1
4680 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
4681 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
4682 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
4683 #define LOOP_RESYNC_ACTIVE 5
4684 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
4685 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
4686 #define RELOGIN_NEEDED 8
4687 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
4688 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
4689 #define BEACON_BLINK_NEEDED 11
4690 #define REGISTER_FDMI_NEEDED 12
4691 #define FCPORT_UPDATE_NEEDED 13
4692 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
4693 #define UNLOADING 15
4694 #define NPIV_CONFIG_NEEDED 16
4695 #define ISP_UNRECOVERABLE 17
4696 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
4697 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
4698 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
4699 #define N2N_LINK_RESET 21
4700 #define PORT_UPDATE_NEEDED 22
4701 #define FX00_RESET_RECOVERY 23
4702 #define FX00_TARGET_SCAN 24
4703 #define FX00_CRITEMP_RECOVERY 25
4704 #define FX00_HOST_INFO_RESEND 26
4705 #define QPAIR_ONLINE_CHECK_NEEDED 27
4706 #define SET_NVME_ZIO_THRESHOLD_NEEDED 28
4707 #define DETECT_SFP_CHANGE 29
4708 #define N2N_LOGIN_NEEDED 30
4709 #define IOCB_WORK_ACTIVE 31
4710 #define SET_ZIO_THRESHOLD_NEEDED 32
4711 #define ISP_ABORT_TO_ROM 33
4712 #define VPORT_DELETE 34
4714 #define PROCESS_PUREX_IOCB 63
4716 unsigned long pci_flags;
4717 #define PFLG_DISCONNECTED 0 /* PCI device removed */
4718 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */
4719 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */
4721 uint32_t device_flags;
4722 #define SWITCH_FOUND BIT_0
4723 #define DFLG_NO_CABLE BIT_1
4724 #define DFLG_DEV_FAILED BIT_5
4726 /* ISP configuration data. */
4727 uint16_t loop_id; /* Host adapter loop id */
4728 uint16_t self_login_loop_id; /* host adapter loop id
4729 * get it on self login
4731 fc_port_t bidir_fcport; /* fcport used for bidir cmnds
4732 * no need of allocating it for
4736 port_id_t d_id; /* Host adapter port id */
4737 uint8_t marker_needed;
4738 uint16_t mgmt_svr_loop_id;
4742 /* Timeout timers. */
4743 uint8_t loop_down_abort_time; /* port down timer */
4744 atomic_t loop_down_timer; /* loop down timer */
4745 uint8_t link_down_timeout; /* link down timeout */
4747 uint32_t timer_active;
4748 struct timer_list timer;
4750 uint8_t node_name[WWN_SIZE];
4751 uint8_t port_name[WWN_SIZE];
4752 uint8_t fabric_node_name[WWN_SIZE];
4753 uint8_t fabric_port_name[WWN_SIZE];
4755 struct nvme_fc_local_port *nvme_local_port;
4756 struct completion nvme_del_done;
4758 uint16_t fcoe_vlan_id;
4759 uint16_t fcoe_fcf_idx;
4760 uint8_t fcoe_vn_port_mac[6];
4762 /* list of commands waiting on workqueue */
4763 struct list_head qla_cmd_list;
4764 struct list_head qla_sess_op_cmd_list;
4765 struct list_head unknown_atio_list;
4766 spinlock_t cmd_list_lock;
4767 struct delayed_work unknown_atio_work;
4769 /* Counter to detect races between ELS and RSCN events */
4770 atomic_t generation_tick;
4771 /* Time when global fcport update has been scheduled */
4772 int total_fcport_update_gen;
4773 /* List of pending LOGOs, protected by tgt_mutex */
4774 struct list_head logo_list;
4775 /* List of pending PLOGI acks, protected by hw lock */
4776 struct list_head plogi_ack_list;
4778 struct list_head qp_list;
4780 uint32_t vp_abort_cnt;
4782 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
4783 uint16_t vp_idx; /* vport ID */
4784 struct qla_qpair *qpair; /* base qpair */
4786 unsigned long vp_flags;
4787 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
4788 #define VP_CREATE_NEEDED 1
4789 #define VP_BIND_NEEDED 2
4790 #define VP_DELETE_NEEDED 3
4791 #define VP_SCR_NEEDED 4 /* State Change Request registration */
4792 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */
4794 #define VP_OFFLINE 0
4797 // #define VP_DISABLE 3
4798 uint16_t vp_err_state;
4799 uint16_t vp_prev_err_state;
4800 #define VP_ERR_UNKWN 0
4801 #define VP_ERR_PORTDWN 1
4802 #define VP_ERR_FAB_UNSUPPORTED 2
4803 #define VP_ERR_FAB_NORESOURCES 3
4804 #define VP_ERR_FAB_LOGOUT 4
4805 #define VP_ERR_ADAP_NORESOURCES 5
4806 struct qla_hw_data *hw;
4807 struct scsi_qlt_host vha_tgt;
4808 struct req_que *req;
4809 int fw_heartbeat_counter;
4810 int seconds_since_last_heartbeat;
4811 struct fc_host_statistics fc_host_stat;
4812 struct qla_statistics qla_stats;
4813 struct bidi_statistics bidi_stats;
4814 atomic_t vref_count;
4815 struct qla8044_reset_template reset_tmplt;
4818 uint16_t u_ql2xexchoffld;
4819 uint16_t u_ql2xiniexchg;
4820 uint16_t qlini_mode;
4821 uint16_t ql2xexchoffld;
4822 uint16_t ql2xiniexchg;
4824 struct dentry *dfs_rport_root;
4827 struct list_head head;
4830 struct purex_item default_item;
4832 struct name_list_extended gnl;
4833 /* Count of active session/fcport */
4835 wait_queue_head_t fcport_waitQ;
4836 wait_queue_head_t vref_waitq;
4837 uint8_t min_supported_speed;
4838 uint8_t n2n_node_name[WWN_SIZE];
4839 uint8_t n2n_port_name[WWN_SIZE];
4841 __le16 dport_data[4];
4842 struct list_head gpnid_list;
4843 struct fab_scan scan;
4844 uint8_t scm_fabric_connection_flags;
4846 unsigned int irq_offset;
4849 struct qla27xx_image_status {
4850 uint8_t image_status_mask;
4854 uint8_t bitmap; /* 28xx only */
4855 uint8_t reserved[2];
4860 /* 28xx aux image status bimap values */
4861 #define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0
4862 #define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1
4863 #define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2
4864 #define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3
4866 #define SET_VP_IDX 1
4868 #define RESET_VP_IDX 3
4869 #define RESET_AL_PA 4
4870 struct qla_tgt_vp_map {
4872 scsi_qla_host_t *vha;
4876 dma_addr_t dma_addr; /* OUT */
4877 uint32_t dma_len; /* OUT */
4879 uint32_t tot_bytes; /* IN */
4880 struct scatterlist *cur_sg; /* IN */
4882 /* for book keeping, bzero on initial invocation */
4883 uint32_t bytes_consumed;
4885 uint32_t tot_partial;
4892 #define QLA_FW_STARTED(_ha) { \
4894 _ha->flags.fw_started = 1; \
4895 _ha->base_qpair->fw_started = 1; \
4896 for (i = 0; i < _ha->max_qpairs; i++) { \
4897 if (_ha->queue_pair_map[i]) \
4898 _ha->queue_pair_map[i]->fw_started = 1; \
4902 #define QLA_FW_STOPPED(_ha) { \
4904 _ha->flags.fw_started = 0; \
4905 _ha->base_qpair->fw_started = 0; \
4906 for (i = 0; i < _ha->max_qpairs; i++) { \
4907 if (_ha->queue_pair_map[i]) \
4908 _ha->queue_pair_map[i]->fw_started = 0; \
4913 #define SFUB_CHECKSUM_SIZE 4
4915 struct secure_flash_update_block {
4916 uint32_t block_info;
4917 uint32_t signature_lo;
4918 uint32_t signature_hi;
4919 uint32_t signature_upper[0x3e];
4922 struct secure_flash_update_block_pk {
4923 uint32_t block_info;
4924 uint32_t signature_lo;
4925 uint32_t signature_hi;
4926 uint32_t signature_upper[0x3e];
4927 uint32_t public_key[0x41];
4931 * Macros to help code, maintain, etc.
4933 #define LOOP_TRANSITION(ha) \
4934 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4935 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
4936 atomic_read(&ha->loop_state) == LOOP_DOWN)
4938 #define STATE_TRANSITION(ha) \
4939 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4940 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
4942 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
4943 atomic_inc(&__vha->vref_count); \
4945 if (__vha->flags.delete_progress) { \
4946 atomic_dec(&__vha->vref_count); \
4947 wake_up(&__vha->vref_waitq); \
4954 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
4955 atomic_dec(&__vha->vref_count); \
4956 wake_up(&__vha->vref_waitq); \
4959 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
4960 atomic_inc(&__qpair->ref_count); \
4962 if (__qpair->delete_in_progress) { \
4963 atomic_dec(&__qpair->ref_count); \
4970 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
4971 atomic_dec(&__qpair->ref_count); \
4974 #define QLA_ENA_CONF(_ha) {\
4976 _ha->base_qpair->enable_explicit_conf = 1; \
4977 for (i = 0; i < _ha->max_qpairs; i++) { \
4978 if (_ha->queue_pair_map[i]) \
4979 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \
4983 #define QLA_DIS_CONF(_ha) {\
4985 _ha->base_qpair->enable_explicit_conf = 0; \
4986 for (i = 0; i < _ha->max_qpairs; i++) { \
4987 if (_ha->queue_pair_map[i]) \
4988 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \
4993 * qla2x00 local function return status codes
4995 #define MBS_MASK 0x3fff
4997 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
4998 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
4999 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
5000 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
5001 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
5002 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
5003 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
5004 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
5005 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
5006 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
5008 #define QLA_FUNCTION_TIMEOUT 0x100
5009 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
5010 #define QLA_FUNCTION_FAILED 0x102
5011 #define QLA_MEMORY_ALLOC_FAILED 0x103
5012 #define QLA_LOCK_TIMEOUT 0x104
5013 #define QLA_ABORTED 0x105
5014 #define QLA_SUSPENDED 0x106
5015 #define QLA_BUSY 0x107
5016 #define QLA_ALREADY_REGISTERED 0x109
5017 #define QLA_OS_TIMER_EXPIRED 0x10a
5019 #define NVRAM_DELAY() udelay(10)
5022 * Flash support definitions
5024 #define OPTROM_SIZE_2300 0x20000
5025 #define OPTROM_SIZE_2322 0x100000
5026 #define OPTROM_SIZE_24XX 0x100000
5027 #define OPTROM_SIZE_25XX 0x200000
5028 #define OPTROM_SIZE_81XX 0x400000
5029 #define OPTROM_SIZE_82XX 0x800000
5030 #define OPTROM_SIZE_83XX 0x1000000
5031 #define OPTROM_SIZE_28XX 0x2000000
5033 #define OPTROM_BURST_SIZE 0x1000
5034 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
5036 #define QLA_DSDS_PER_IOCB 37
5038 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
5040 #define QLA_SG_ALL 1024
5042 enum nexus_wait_type {
5048 /* Refer to SNIA SFF 8247 */
5049 struct sff_8247_a0 {
5050 u8 txid; /* transceiver id */
5053 /* compliance code */
5054 u8 eth_infi_cc3; /* ethernet, inifiband */
5058 #define FC_LL_VL BIT_7 /* very long */
5059 #define FC_LL_S BIT_6 /* Short */
5060 #define FC_LL_I BIT_5 /* Intermidiate*/
5061 #define FC_LL_L BIT_4 /* Long */
5062 #define FC_LL_M BIT_3 /* Medium */
5063 #define FC_LL_SA BIT_2 /* ShortWave laser */
5064 #define FC_LL_LC BIT_1 /* LongWave laser */
5065 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */
5068 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */
5069 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */
5070 #define FC_TEC_SL BIT_5 /* short wave with OFC */
5071 #define FC_TEC_LL BIT_4 /* Longwave Laser */
5072 #define FC_TEC_ACT BIT_3 /* Active cable */
5073 #define FC_TEC_PAS BIT_2 /* Passive cable */
5075 /* Transmission Media */
5076 #define FC_MED_TW BIT_7 /* Twin Ax */
5077 #define FC_MED_TP BIT_6 /* Twited Pair */
5078 #define FC_MED_MI BIT_5 /* Min Coax */
5079 #define FC_MED_TV BIT_4 /* Video Coax */
5080 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */
5081 #define FC_MED_M5 BIT_2 /* Multimode, 50um */
5082 #define FC_MED_SM BIT_0 /* Single Mode */
5084 /* speed FC_SP_12: 12*100M = 1200 MB/s */
5085 #define FC_SP_12 BIT_7
5086 #define FC_SP_8 BIT_6
5087 #define FC_SP_16 BIT_5
5088 #define FC_SP_4 BIT_4
5089 #define FC_SP_32 BIT_3
5090 #define FC_SP_2 BIT_2
5091 #define FC_SP_1 BIT_0
5096 u8 length_km; /* offset 14/eh */
5102 #define SFF_VEN_NAME_LEN 16
5103 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */
5106 #define SFF_PART_NAME_LEN 16
5107 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */
5112 u8 options[2]; /* offset 64 */
5121 u8 vendor_specific[32];
5125 /* BPM -- Buffer Plus Management support. */
5126 #define IS_BPM_CAPABLE(ha) \
5127 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
5128 IS_QLA27XX(ha) || IS_QLA28XX(ha))
5129 #define IS_BPM_RANGE_CAPABLE(ha) \
5130 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
5131 #define IS_BPM_ENABLED(vha) \
5132 (ql2xautodetectsfp && !vha->vp_idx && IS_BPM_CAPABLE(vha->hw))
5134 #define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016
5136 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \
5137 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha)))
5139 #define SAVE_TOPO(_ha) { \
5140 if (_ha->current_topology) \
5141 _ha->prev_topology = _ha->current_topology; \
5144 #define N2N_TOPO(ha) \
5145 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \
5146 ha->current_topology == ISP_CFG_N || \
5147 !ha->current_topology)
5149 #define QLA_N2N_WAIT_TIME 5 /* 2 * ra_tov(n2n) + 1 */
5151 #define NVME_TYPE(fcport) \
5152 (fcport->fc4_type & FS_FC4TYPE_NVME) \
5154 #define FCP_TYPE(fcport) \
5155 (fcport->fc4_type & FS_FC4TYPE_FCP) \
5157 #define NVME_ONLY_TARGET(fcport) \
5158 (NVME_TYPE(fcport) && !FCP_TYPE(fcport)) \
5160 #define NVME_FCP_TARGET(fcport) \
5161 (FCP_TYPE(fcport) && NVME_TYPE(fcport)) \
5163 #define NVME_TARGET(ha, fcport) \
5164 ((NVME_FCP_TARGET(fcport) && \
5165 (ha->fc4_type_priority == FC4_PRIORITY_NVME)) || \
5166 NVME_ONLY_TARGET(fcport)) \
5168 #define PRLI_PHASE(_cls) \
5169 ((_cls == DSC_LS_PRLI_PEND) || (_cls == DSC_LS_PRLI_COMP))
5171 #include "qla_target.h"
5172 #include "qla_gbl.h"
5173 #include "qla_dbg.h"
5174 #include "qla_inline.h"