2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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37 * POSSIBILITY OF SUCH DAMAGES.
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm80xx_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45 #include "pm80xx_tracepoints.h"
48 #define SMP_INDIRECT 2
51 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
55 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
56 /* confirm the setting is written */
57 start = jiffies + HZ; /* 1 sec */
59 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
60 } while ((reg_val != shift_value) && time_before(jiffies, start));
61 if (reg_val != shift_value) {
62 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MEMBASE_II_SHIFT_REGISTER = 0x%x\n",
69 static void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset,
70 const void *destination,
71 u32 dw_count, u32 bus_base_number)
73 u32 index, value, offset;
75 destination1 = (u32 *)destination;
77 for (index = 0; index < dw_count; index += 4, destination1++) {
78 offset = (soffset + index);
79 if (offset < (64 * 1024)) {
80 value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
81 *destination1 = cpu_to_le32(value);
87 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
88 struct device_attribute *attr, char *buf)
90 struct Scsi_Host *shost = class_to_shost(cdev);
91 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
92 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
93 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
94 u32 accum_len, reg_val, index, *temp;
98 char *fatal_error_data = buf;
102 pm8001_ha->forensic_info.data_buf.direct_data = buf;
103 if (pm8001_ha->chip_id == chip_8001) {
104 pm8001_ha->forensic_info.data_buf.direct_data +=
105 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
106 "Not supported for SPC controller");
107 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
110 /* initialize variables for very first call from host application */
111 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
112 pm8001_dbg(pm8001_ha, IO,
113 "forensic_info TYPE_NON_FATAL..............\n");
114 direct_data = (u8 *)fatal_error_data;
115 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
116 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
117 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
118 pm8001_ha->forensic_info.data_buf.read_len = 0;
119 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
121 /* Write signature to fatal dump table */
122 pm8001_mw32(fatal_table_address,
123 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd);
125 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
126 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: status1 %d\n", status);
127 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: read_len 0x%x\n",
128 pm8001_ha->forensic_info.data_buf.read_len);
129 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_len 0x%x\n",
130 pm8001_ha->forensic_info.data_buf.direct_len);
131 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_offset 0x%x\n",
132 pm8001_ha->forensic_info.data_buf.direct_offset);
134 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
135 /* start to get data */
136 /* Program the MEMBASE II Shifting Register with 0x00.*/
137 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
138 pm8001_ha->fatal_forensic_shift_offset);
139 pm8001_ha->forensic_last_offset = 0;
140 pm8001_ha->forensic_fatal_step = 0;
141 pm8001_ha->fatal_bar_loc = 0;
144 /* Read until accum_len is retrieved */
145 accum_len = pm8001_mr32(fatal_table_address,
146 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
147 /* Determine length of data between previously stored transfer length
148 * and current accumulated transfer length
151 accum_len - pm8001_ha->forensic_preserved_accumulated_transfer;
152 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: accum_len 0x%x\n",
154 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: length_to_read 0x%x\n",
156 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: last_offset 0x%x\n",
157 pm8001_ha->forensic_last_offset);
158 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: read_len 0x%x\n",
159 pm8001_ha->forensic_info.data_buf.read_len);
160 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_len 0x%x\n",
161 pm8001_ha->forensic_info.data_buf.direct_len);
162 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_offset 0x%x\n",
163 pm8001_ha->forensic_info.data_buf.direct_offset);
165 /* If accumulated length failed to read correctly fail the attempt.*/
166 if (accum_len == 0xFFFFFFFF) {
167 pm8001_dbg(pm8001_ha, IO,
168 "Possible PCI issue 0x%x not expected\n",
172 /* If accumulated length is zero fail the attempt */
173 if (accum_len == 0) {
174 pm8001_ha->forensic_info.data_buf.direct_data +=
175 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
176 "%08x ", 0xFFFFFFFF);
177 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
180 /* Accumulated length is good so start capturing the first data */
181 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
182 if (pm8001_ha->forensic_fatal_step == 0) {
184 /* If data to read is less than SYSFS_OFFSET then reduce the
187 if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET
189 pm8001_ha->forensic_info.data_buf.direct_len =
191 pm8001_ha->forensic_last_offset;
193 pm8001_ha->forensic_info.data_buf.direct_len =
196 if (pm8001_ha->forensic_info.data_buf.direct_data) {
197 /* Data is in bar, copy to host memory */
198 pm80xx_pci_mem_copy(pm8001_ha,
199 pm8001_ha->fatal_bar_loc,
200 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
201 pm8001_ha->forensic_info.data_buf.direct_len, 1);
203 pm8001_ha->fatal_bar_loc +=
204 pm8001_ha->forensic_info.data_buf.direct_len;
205 pm8001_ha->forensic_info.data_buf.direct_offset +=
206 pm8001_ha->forensic_info.data_buf.direct_len;
207 pm8001_ha->forensic_last_offset +=
208 pm8001_ha->forensic_info.data_buf.direct_len;
209 pm8001_ha->forensic_info.data_buf.read_len =
210 pm8001_ha->forensic_info.data_buf.direct_len;
212 if (pm8001_ha->forensic_last_offset >= length_to_read) {
213 pm8001_ha->forensic_info.data_buf.direct_data +=
214 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
216 for (index = 0; index <
217 (pm8001_ha->forensic_info.data_buf.direct_len
219 pm8001_ha->forensic_info.data_buf.direct_data +=
221 pm8001_ha->forensic_info.data_buf.direct_data,
222 "%08x ", *(temp + index));
225 pm8001_ha->fatal_bar_loc = 0;
226 pm8001_ha->forensic_fatal_step = 1;
227 pm8001_ha->fatal_forensic_shift_offset = 0;
228 pm8001_ha->forensic_last_offset = 0;
231 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
233 pm8001_dbg(pm8001_ha, IO,
234 "get_fatal_spcv:return1 0x%x\n", offset);
235 return (char *)pm8001_ha->
236 forensic_info.data_buf.direct_data -
239 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
240 pm8001_ha->forensic_info.data_buf.direct_data +=
242 forensic_info.data_buf.direct_data,
244 for (index = 0; index <
245 (pm8001_ha->forensic_info.data_buf.direct_len
247 pm8001_ha->forensic_info.data_buf.direct_data
248 += sprintf(pm8001_ha->
249 forensic_info.data_buf.direct_data,
250 "%08x ", *(temp + index));
254 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
256 pm8001_dbg(pm8001_ha, IO,
257 "get_fatal_spcv:return2 0x%x\n", offset);
258 return (char *)pm8001_ha->
259 forensic_info.data_buf.direct_data -
263 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
264 pm8001_ha->forensic_info.data_buf.direct_data +=
265 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
267 for (index = 0; index <
268 (pm8001_ha->forensic_info.data_buf.direct_len
270 pm8001_ha->forensic_info.data_buf.direct_data +=
272 forensic_info.data_buf.direct_data,
273 "%08x ", *(temp + index));
275 pm8001_ha->fatal_forensic_shift_offset += 0x100;
276 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
277 pm8001_ha->fatal_forensic_shift_offset);
278 pm8001_ha->fatal_bar_loc = 0;
281 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
283 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return3 0x%x\n",
285 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
288 if (pm8001_ha->forensic_fatal_step == 1) {
289 /* store previous accumulated length before triggering next
290 * accumulated length update
292 pm8001_ha->forensic_preserved_accumulated_transfer =
293 pm8001_mr32(fatal_table_address,
294 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
296 /* continue capturing the fatal log until Dump status is 0x3 */
297 if (pm8001_mr32(fatal_table_address,
298 MPI_FATAL_EDUMP_TABLE_STATUS) <
299 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
301 /* reset fddstat bit by writing to zero*/
302 pm8001_mw32(fatal_table_address,
303 MPI_FATAL_EDUMP_TABLE_STATUS, 0x0);
305 /* set dump control value to '1' so that new data will
306 * be transferred to shared memory
308 pm8001_mw32(fatal_table_address,
309 MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
310 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
312 /*Poll FDDHSHK until clear */
313 start = jiffies + (2 * HZ); /* 2 sec */
316 reg_val = pm8001_mr32(fatal_table_address,
317 MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
318 } while ((reg_val) && time_before(jiffies, start));
321 pm8001_dbg(pm8001_ha, FAIL,
322 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n",
324 /* Fail the dump if a timeout occurs */
325 pm8001_ha->forensic_info.data_buf.direct_data +=
327 pm8001_ha->forensic_info.data_buf.direct_data,
328 "%08x ", 0xFFFFFFFF);
330 pm8001_ha->forensic_info.data_buf.direct_data
333 /* Poll status register until set to 2 or
334 * 3 for up to 2 seconds
336 start = jiffies + (2 * HZ); /* 2 sec */
339 reg_val = pm8001_mr32(fatal_table_address,
340 MPI_FATAL_EDUMP_TABLE_STATUS);
341 } while (((reg_val != 2) && (reg_val != 3)) &&
342 time_before(jiffies, start));
345 pm8001_dbg(pm8001_ha, FAIL,
346 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n",
348 /* Fail the dump if a timeout occurs */
349 pm8001_ha->forensic_info.data_buf.direct_data +=
351 pm8001_ha->forensic_info.data_buf.direct_data,
352 "%08x ", 0xFFFFFFFF);
353 return((char *)pm8001_ha->forensic_info.data_buf.direct_data -
356 /* reset fatal_forensic_shift_offset back to zero and reset MEMBASE 2 register to zero */
357 pm8001_ha->fatal_forensic_shift_offset = 0; /* location in 64k region */
358 pm8001_cw32(pm8001_ha, 0,
359 MEMBASE_II_SHIFT_REGISTER,
360 pm8001_ha->fatal_forensic_shift_offset);
362 /* Read the next block of the debug data.*/
363 length_to_read = pm8001_mr32(fatal_table_address,
364 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) -
365 pm8001_ha->forensic_preserved_accumulated_transfer;
366 if (length_to_read != 0x0) {
367 pm8001_ha->forensic_fatal_step = 0;
370 pm8001_ha->forensic_info.data_buf.direct_data +=
371 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
373 pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;
374 pm8001_ha->forensic_info.data_buf.direct_len = 0;
375 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
376 pm8001_ha->forensic_info.data_buf.read_len = 0;
379 offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data
381 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return4 0x%x\n", offset);
382 return ((char *)pm8001_ha->forensic_info.data_buf.direct_data -
386 /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma
387 * location by the firmware.
389 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev,
390 struct device_attribute *attr, char *buf)
392 struct Scsi_Host *shost = class_to_shost(cdev);
393 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
394 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
395 void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr;
402 unsigned long start = 0;
403 char *buf_copy = buf;
405 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
406 if (++pm8001_ha->non_fatal_count == 1) {
407 if (pm8001_ha->chip_id == chip_8001) {
408 snprintf(pm8001_ha->forensic_info.data_buf.direct_data,
409 PAGE_SIZE, "Not supported for SPC controller");
412 pm8001_dbg(pm8001_ha, IO, "forensic_info TYPE_NON_FATAL...\n");
414 * Step 1: Write the host buffer parameters in the MPI Fatal and
415 * Non-Fatal Error Dump Capture Table.This is the buffer
416 * where debug data will be DMAed to.
418 pm8001_mw32(nonfatal_table_address,
419 MPI_FATAL_EDUMP_TABLE_LO_OFFSET,
420 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo);
422 pm8001_mw32(nonfatal_table_address,
423 MPI_FATAL_EDUMP_TABLE_HI_OFFSET,
424 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi);
426 pm8001_mw32(nonfatal_table_address,
427 MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET);
429 /* Optionally, set the DUMPCTRL bit to 1 if the host
430 * keeps sending active I/Os while capturing the non-fatal
431 * debug data. Otherwise, leave this bit set to zero
433 pm8001_mw32(nonfatal_table_address,
434 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY);
437 * Step 2: Clear Accumulative Length of Debug Data Transferred
438 * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump
439 * Capture Table to zero.
441 pm8001_mw32(nonfatal_table_address,
442 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0);
444 /* initiallize previous accumulated length to 0 */
445 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
446 pm8001_ha->non_fatal_read_length = 0;
449 total_len = pm8001_mr32(nonfatal_table_address,
450 MPI_FATAL_EDUMP_TABLE_TOTAL_LEN);
452 * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT]
453 * field and then request that the SPCv controller transfer the debug
454 * data by setting bit 7 of the Inbound Doorbell Set Register.
456 pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0);
457 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET,
458 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP);
461 * Step 4.1: Read back the Inbound Doorbell Set Register (by polling for
462 * 2 seconds) until register bit 7 is cleared.
463 * This step only indicates the request is accepted by the controller.
465 start = jiffies + (2 * HZ); /* 2 sec */
467 reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) &
468 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP;
469 } while ((reg_val != 0) && time_before(jiffies, start));
471 /* Step 4.2: To check the completion of the transfer, poll the Fatal/Non
472 * Fatal Debug Data Transfer Status [FDDTSTAT] field for 2 seconds in
473 * the MPI Fatal and Non-Fatal Error Dump Capture Table.
475 start = jiffies + (2 * HZ); /* 2 sec */
477 reg_val = pm8001_mr32(nonfatal_table_address,
478 MPI_FATAL_EDUMP_TABLE_STATUS);
479 } while ((!reg_val) && time_before(jiffies, start));
481 if ((reg_val == 0x00) ||
482 (reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) ||
483 (reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) {
484 pm8001_ha->non_fatal_read_length = 0;
485 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF);
486 pm8001_ha->non_fatal_count = 0;
487 return (buf_copy - buf);
488 } else if (reg_val ==
489 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) {
490 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2);
491 } else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) ||
492 (pm8001_ha->non_fatal_read_length >= total_len)) {
493 pm8001_ha->non_fatal_read_length = 0;
494 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4);
495 pm8001_ha->non_fatal_count = 0;
497 accum_len = pm8001_mr32(nonfatal_table_address,
498 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
499 output_length = accum_len -
500 pm8001_ha->forensic_preserved_accumulated_transfer;
502 for (index = 0; index < output_length/4; index++)
503 buf_copy += snprintf(buf_copy, PAGE_SIZE,
504 "%08x ", *(temp+index));
506 pm8001_ha->non_fatal_read_length += output_length;
508 /* store current accumulated length to use in next iteration as
509 * the previous accumulated length
511 pm8001_ha->forensic_preserved_accumulated_transfer = accum_len;
512 return (buf_copy - buf);
516 * read_main_config_table - read the configure table and save it.
517 * @pm8001_ha: our hba card information
519 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
521 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
523 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
524 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
525 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
526 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
527 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
528 pm8001_mr32(address, MAIN_FW_REVISION);
529 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
530 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
531 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
532 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
533 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
534 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
535 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
536 pm8001_mr32(address, MAIN_GST_OFFSET);
537 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
538 pm8001_mr32(address, MAIN_IBQ_OFFSET);
539 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
540 pm8001_mr32(address, MAIN_OBQ_OFFSET);
542 /* read Error Dump Offset and Length */
543 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
544 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
545 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
546 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
547 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
548 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
549 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
550 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
552 /* read GPIO LED settings from the configuration table */
553 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
554 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
556 /* read analog Setting offset from the configuration table */
557 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
558 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
560 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
561 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
562 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
563 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
564 /* read port recover and reset timeout */
565 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
566 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
567 /* read ILA and inactive firmware version */
568 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =
569 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE);
570 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =
571 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION);
573 pm8001_dbg(pm8001_ha, DEV,
574 "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n",
575 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature,
576 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev,
577 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev);
579 pm8001_dbg(pm8001_ha, DEV,
580 "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n",
581 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset,
582 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset,
583 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset,
584 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset,
585 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset);
587 pm8001_dbg(pm8001_ha, DEV,
588 "Main cfg table; ila rev:%x Inactive fw rev:%x\n",
589 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version,
590 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version);
594 * read_general_status_table - read the general status table and save it.
595 * @pm8001_ha: our hba card information
597 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
599 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
600 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
601 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
602 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
603 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
604 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
605 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
606 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
607 pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
608 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
609 pm8001_mr32(address, GST_IOPTCNT_OFFSET);
610 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
611 pm8001_mr32(address, GST_GPIO_INPUT_VAL);
612 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
613 pm8001_mr32(address, GST_RERRINFO_OFFSET0);
614 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
615 pm8001_mr32(address, GST_RERRINFO_OFFSET1);
616 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
617 pm8001_mr32(address, GST_RERRINFO_OFFSET2);
618 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
619 pm8001_mr32(address, GST_RERRINFO_OFFSET3);
620 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
621 pm8001_mr32(address, GST_RERRINFO_OFFSET4);
622 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
623 pm8001_mr32(address, GST_RERRINFO_OFFSET5);
624 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
625 pm8001_mr32(address, GST_RERRINFO_OFFSET6);
626 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
627 pm8001_mr32(address, GST_RERRINFO_OFFSET7);
630 * read_phy_attr_table - read the phy attribute table and save it.
631 * @pm8001_ha: our hba card information
633 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
635 void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
636 pm8001_ha->phy_attr_table.phystart1_16[0] =
637 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
638 pm8001_ha->phy_attr_table.phystart1_16[1] =
639 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
640 pm8001_ha->phy_attr_table.phystart1_16[2] =
641 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
642 pm8001_ha->phy_attr_table.phystart1_16[3] =
643 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
644 pm8001_ha->phy_attr_table.phystart1_16[4] =
645 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
646 pm8001_ha->phy_attr_table.phystart1_16[5] =
647 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
648 pm8001_ha->phy_attr_table.phystart1_16[6] =
649 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
650 pm8001_ha->phy_attr_table.phystart1_16[7] =
651 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
652 pm8001_ha->phy_attr_table.phystart1_16[8] =
653 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
654 pm8001_ha->phy_attr_table.phystart1_16[9] =
655 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
656 pm8001_ha->phy_attr_table.phystart1_16[10] =
657 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
658 pm8001_ha->phy_attr_table.phystart1_16[11] =
659 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
660 pm8001_ha->phy_attr_table.phystart1_16[12] =
661 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
662 pm8001_ha->phy_attr_table.phystart1_16[13] =
663 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
664 pm8001_ha->phy_attr_table.phystart1_16[14] =
665 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
666 pm8001_ha->phy_attr_table.phystart1_16[15] =
667 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
669 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
670 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
671 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
672 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
673 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
674 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
675 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
676 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
677 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
678 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
679 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
680 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
681 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
682 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
683 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
684 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
685 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
686 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
687 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
688 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
689 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
690 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
691 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
692 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
693 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
694 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
695 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
696 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
697 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
698 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
699 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
700 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
705 * read_inbnd_queue_table - read the inbound queue table and save it.
706 * @pm8001_ha: our hba card information
708 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
711 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
712 for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
713 u32 offset = i * 0x20;
714 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
715 get_pci_bar_index(pm8001_mr32(address,
716 (offset + IB_PIPCI_BAR)));
717 pm8001_ha->inbnd_q_tbl[i].pi_offset =
718 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
723 * read_outbnd_queue_table - read the outbound queue table and save it.
724 * @pm8001_ha: our hba card information
726 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
729 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
730 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
731 u32 offset = i * 0x24;
732 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
733 get_pci_bar_index(pm8001_mr32(address,
734 (offset + OB_CIPCI_BAR)));
735 pm8001_ha->outbnd_q_tbl[i].ci_offset =
736 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
741 * init_default_table_values - init the default table.
742 * @pm8001_ha: our hba card information
744 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
747 u32 offsetib, offsetob;
748 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
749 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
750 u32 ib_offset = pm8001_ha->ib_offset;
751 u32 ob_offset = pm8001_ha->ob_offset;
752 u32 ci_offset = pm8001_ha->ci_offset;
753 u32 pi_offset = pm8001_ha->pi_offset;
755 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
756 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
757 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
758 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
759 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
760 PM8001_EVENT_LOG_SIZE;
761 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
762 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
763 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
764 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
765 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
766 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
767 PM8001_EVENT_LOG_SIZE;
768 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01;
769 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
771 /* Disable end to end CRC checking */
772 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
774 for (i = 0; i < pm8001_ha->max_q_num; i++) {
775 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
776 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
777 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
778 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
779 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
780 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
781 pm8001_ha->inbnd_q_tbl[i].base_virt =
782 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
783 pm8001_ha->inbnd_q_tbl[i].total_length =
784 pm8001_ha->memoryMap.region[ib_offset + i].total_len;
785 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
786 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
787 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
788 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
789 pm8001_ha->inbnd_q_tbl[i].ci_virt =
790 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
791 pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0);
793 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
794 get_pci_bar_index(pm8001_mr32(addressib,
796 pm8001_ha->inbnd_q_tbl[i].pi_offset =
797 pm8001_mr32(addressib, (offsetib + 0x18));
798 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
799 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
801 pm8001_dbg(pm8001_ha, DEV,
802 "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i,
803 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar,
804 pm8001_ha->inbnd_q_tbl[i].pi_offset);
806 for (i = 0; i < pm8001_ha->max_q_num; i++) {
807 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
808 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
809 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
810 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
811 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
812 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
813 pm8001_ha->outbnd_q_tbl[i].base_virt =
814 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
815 pm8001_ha->outbnd_q_tbl[i].total_length =
816 pm8001_ha->memoryMap.region[ob_offset + i].total_len;
817 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
818 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
819 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
820 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
821 /* interrupt vector based on oq */
822 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
823 pm8001_ha->outbnd_q_tbl[i].pi_virt =
824 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
825 pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0);
827 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
828 get_pci_bar_index(pm8001_mr32(addressob,
830 pm8001_ha->outbnd_q_tbl[i].ci_offset =
831 pm8001_mr32(addressob, (offsetob + 0x18));
832 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
833 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
835 pm8001_dbg(pm8001_ha, DEV,
836 "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i,
837 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar,
838 pm8001_ha->outbnd_q_tbl[i].ci_offset);
843 * update_main_config_table - update the main default table to the HBA.
844 * @pm8001_ha: our hba card information
846 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
848 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
849 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
850 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
851 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
852 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
853 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
854 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
855 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
856 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
857 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
858 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
859 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
860 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
861 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
862 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
863 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
864 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
865 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
866 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
867 /* Update Fatal error interrupt vector */
868 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
869 ((pm8001_ha->max_q_num - 1) << 8);
870 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
871 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
872 pm8001_dbg(pm8001_ha, DEV,
873 "Updated Fatal error interrupt vector 0x%x\n",
874 pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT));
876 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
877 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
880 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
881 /* Set GPIOLED to 0x2 for LED indicator */
882 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
883 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
884 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
885 pm8001_dbg(pm8001_ha, DEV,
886 "Programming DW 0x21 in main cfg table with 0x%x\n",
887 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET));
889 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
890 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
891 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
892 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
894 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
895 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
896 PORT_RECOVERY_TIMEOUT;
897 if (pm8001_ha->chip_id == chip_8006) {
898 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=
900 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
901 CHIP_8006_PORT_RECOVERY_TIMEOUT;
903 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
904 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
908 * update_inbnd_queue_table - update the inbound queue table to the HBA.
909 * @pm8001_ha: our hba card information
910 * @number: entry in the queue
912 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
915 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
916 u16 offset = number * 0x20;
917 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
918 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
919 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
920 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
921 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
922 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
923 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
924 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
925 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
926 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
928 pm8001_dbg(pm8001_ha, DEV,
929 "IQ %d: Element pri size 0x%x\n",
931 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
933 pm8001_dbg(pm8001_ha, DEV,
934 "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n",
935 pm8001_ha->inbnd_q_tbl[number].upper_base_addr,
936 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
938 pm8001_dbg(pm8001_ha, DEV,
939 "CI upper base addr 0x%x CI lower base addr 0x%x\n",
940 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr,
941 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
945 * update_outbnd_queue_table - update the outbound queue table to the HBA.
946 * @pm8001_ha: our hba card information
947 * @number: entry in the queue
949 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
952 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
953 u16 offset = number * 0x24;
954 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
955 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
956 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
957 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
958 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
959 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
960 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
961 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
962 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
963 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
964 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
965 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
967 pm8001_dbg(pm8001_ha, DEV,
968 "OQ %d: Element pri size 0x%x\n",
970 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
972 pm8001_dbg(pm8001_ha, DEV,
973 "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n",
974 pm8001_ha->outbnd_q_tbl[number].upper_base_addr,
975 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
977 pm8001_dbg(pm8001_ha, DEV,
978 "PI upper base addr 0x%x PI lower base addr 0x%x\n",
979 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr,
980 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
984 * mpi_init_check - check firmware initialization status.
985 * @pm8001_ha: our hba card information
987 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
991 u32 gst_len_mpistate;
993 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
995 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
996 /* wait until Inbound DoorBell Clear Register toggled */
997 if (IS_SPCV_12G(pm8001_ha->pdev)) {
998 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
1000 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
1003 msleep(FW_READY_INTERVAL);
1004 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1005 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
1006 } while ((value != 0) && (--max_wait_count));
1008 if (!max_wait_count) {
1009 /* additional check */
1010 pm8001_dbg(pm8001_ha, FAIL,
1011 "Inb doorbell clear not toggled[value:%x]\n",
1015 /* check the MPI-State for initialization up to 100ms*/
1016 max_wait_count = 5;/* 100 msec */
1018 msleep(FW_READY_INTERVAL);
1020 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1021 GST_GSTLEN_MPIS_OFFSET);
1022 } while ((GST_MPI_STATE_INIT !=
1023 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
1024 if (!max_wait_count)
1027 /* check MPI Initialization error */
1028 gst_len_mpistate = gst_len_mpistate >> 16;
1029 if (0x0000 != gst_len_mpistate)
1036 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
1037 * This function sleeps hence it must not be used in atomic context.
1038 * @pm8001_ha: our hba card information
1040 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
1048 /* reset / PCIe ready */
1049 max_wait_time = max_wait_count = 5; /* 100 milli sec */
1051 msleep(FW_READY_INTERVAL);
1052 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1053 } while ((value == 0xFFFFFFFF) && (--max_wait_count));
1055 /* check ila, RAAE and iops status */
1056 if ((pm8001_ha->chip_id != chip_8008) &&
1057 (pm8001_ha->chip_id != chip_8009)) {
1058 max_wait_time = max_wait_count = 180; /* 3600 milli sec */
1059 expected_mask = SCRATCH_PAD_ILA_READY |
1060 SCRATCH_PAD_RAAE_READY |
1061 SCRATCH_PAD_IOP0_READY |
1062 SCRATCH_PAD_IOP1_READY;
1064 max_wait_time = max_wait_count = 170; /* 3400 milli sec */
1065 expected_mask = SCRATCH_PAD_ILA_READY |
1066 SCRATCH_PAD_RAAE_READY |
1067 SCRATCH_PAD_IOP0_READY;
1070 msleep(FW_READY_INTERVAL);
1071 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1072 } while (((value & expected_mask) !=
1073 expected_mask) && (--max_wait_count));
1074 if (!max_wait_count) {
1075 pm8001_dbg(pm8001_ha, INIT,
1076 "At least one FW component failed to load within %d millisec: Scratchpad1: 0x%x\n",
1077 max_wait_time * FW_READY_INTERVAL, value);
1080 pm8001_dbg(pm8001_ha, MSG,
1081 "All FW components ready by %d ms\n",
1082 (max_wait_time - max_wait_count) * FW_READY_INTERVAL);
1087 static int init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
1089 void __iomem *base_addr;
1095 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1098 * lower 26 bits of SCRATCHPAD0 register describes offset within the
1099 * PCIe BAR where the MPI configuration table is present
1101 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
1103 pm8001_dbg(pm8001_ha, DEV, "Scratchpad 0 Offset: 0x%x value 0x%x\n",
1106 * Upper 6 bits describe the offset within PCI config space where BAR
1109 pcilogic = (value & 0xFC000000) >> 26;
1110 pcibar = get_pci_bar_index(pcilogic);
1111 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar);
1114 * Make sure the offset falls inside the ioremapped PCI BAR
1116 if (offset > pm8001_ha->io_mem[pcibar].memsize) {
1117 pm8001_dbg(pm8001_ha, FAIL,
1118 "Main cfg tbl offset outside %u > %u\n",
1119 offset, pm8001_ha->io_mem[pcibar].memsize);
1122 pm8001_ha->main_cfg_tbl_addr = base_addr =
1123 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
1126 * Validate main configuration table address: first DWord should read
1129 value = pm8001_mr32(pm8001_ha->main_cfg_tbl_addr, 0);
1130 if (memcmp(&value, "PMCS", 4) != 0) {
1131 pm8001_dbg(pm8001_ha, FAIL,
1132 "BAD main config signature 0x%x\n",
1136 pm8001_dbg(pm8001_ha, INIT,
1137 "VALID main config signature 0x%x\n", value);
1138 pm8001_ha->general_stat_tbl_addr =
1139 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
1141 pm8001_ha->inbnd_q_tbl_addr =
1142 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
1144 pm8001_ha->outbnd_q_tbl_addr =
1145 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
1147 pm8001_ha->ivt_tbl_addr =
1148 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
1150 pm8001_ha->pspa_q_tbl_addr =
1151 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
1153 pm8001_ha->fatal_tbl_addr =
1154 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
1157 pm8001_dbg(pm8001_ha, INIT, "GST OFFSET 0x%x\n",
1158 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18));
1159 pm8001_dbg(pm8001_ha, INIT, "INBND OFFSET 0x%x\n",
1160 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C));
1161 pm8001_dbg(pm8001_ha, INIT, "OBND OFFSET 0x%x\n",
1162 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20));
1163 pm8001_dbg(pm8001_ha, INIT, "IVT OFFSET 0x%x\n",
1164 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C));
1165 pm8001_dbg(pm8001_ha, INIT, "PSPA OFFSET 0x%x\n",
1166 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90));
1167 pm8001_dbg(pm8001_ha, INIT, "addr - main cfg %p general status %p\n",
1168 pm8001_ha->main_cfg_tbl_addr,
1169 pm8001_ha->general_stat_tbl_addr);
1170 pm8001_dbg(pm8001_ha, INIT, "addr - inbnd %p obnd %p\n",
1171 pm8001_ha->inbnd_q_tbl_addr,
1172 pm8001_ha->outbnd_q_tbl_addr);
1173 pm8001_dbg(pm8001_ha, INIT, "addr - pspa %p ivt %p\n",
1174 pm8001_ha->pspa_q_tbl_addr,
1175 pm8001_ha->ivt_tbl_addr);
1180 * pm80xx_set_thermal_config - support the thermal configuration
1181 * @pm8001_ha: our hba card information.
1184 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
1186 struct set_ctrl_cfg_req payload;
1187 struct inbound_queue_table *circularQ;
1190 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1193 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1194 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1198 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1199 payload.tag = cpu_to_le32(tag);
1201 if (IS_SPCV_12G(pm8001_ha->pdev))
1202 page_code = THERMAL_PAGE_CODE_7H;
1204 page_code = THERMAL_PAGE_CODE_8H;
1206 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
1207 (THERMAL_ENABLE << 8) | page_code;
1208 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
1210 pm8001_dbg(pm8001_ha, DEV,
1211 "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n",
1212 payload.cfg_pg[0], payload.cfg_pg[1]);
1214 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1215 sizeof(payload), 0);
1217 pm8001_tag_free(pm8001_ha, tag);
1223 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
1224 * Timer configuration page
1225 * @pm8001_ha: our hba card information.
1228 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
1230 struct set_ctrl_cfg_req payload;
1231 struct inbound_queue_table *circularQ;
1232 SASProtocolTimerConfig_t SASConfigPage;
1235 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1237 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1238 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
1240 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1245 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1246 payload.tag = cpu_to_le32(tag);
1248 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE;
1249 SASConfigPage.MST_MSI = 3 << 15;
1250 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO;
1251 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) |
1252 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
1253 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME;
1255 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
1256 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
1259 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) |
1260 SAS_OPNRJT_RTRY_INTVL;
1261 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16)
1262 | SAS_COPNRJT_RTRY_TMO;
1263 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16)
1264 | SAS_COPNRJT_RTRY_THR;
1265 SASConfigPage.MAX_AIP = SAS_MAX_AIP;
1267 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.pageCode 0x%08x\n",
1268 SASConfigPage.pageCode);
1269 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MST_MSI 0x%08x\n",
1270 SASConfigPage.MST_MSI);
1271 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_SSP_MCT_TMO 0x%08x\n",
1272 SASConfigPage.STP_SSP_MCT_TMO);
1273 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_FRM_TMO 0x%08x\n",
1274 SASConfigPage.STP_FRM_TMO);
1275 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_IDLE_TMO 0x%08x\n",
1276 SASConfigPage.STP_IDLE_TMO);
1277 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.OPNRJT_RTRY_INTVL 0x%08x\n",
1278 SASConfigPage.OPNRJT_RTRY_INTVL);
1279 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO 0x%08x\n",
1280 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO);
1281 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR 0x%08x\n",
1282 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR);
1283 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MAX_AIP 0x%08x\n",
1284 SASConfigPage.MAX_AIP);
1286 memcpy(&payload.cfg_pg, &SASConfigPage,
1287 sizeof(SASProtocolTimerConfig_t));
1289 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1290 sizeof(payload), 0);
1292 pm8001_tag_free(pm8001_ha, tag);
1298 * pm80xx_get_encrypt_info - Check for encryption
1299 * @pm8001_ha: our hba card information.
1302 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
1307 /* Read encryption status from SCRATCH PAD 3 */
1308 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1310 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1311 SCRATCH_PAD3_ENC_READY) {
1312 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1313 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1314 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1315 SCRATCH_PAD3_SMF_ENABLED)
1316 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1317 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1318 SCRATCH_PAD3_SMA_ENABLED)
1319 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1320 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1321 SCRATCH_PAD3_SMB_ENABLED)
1322 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1323 pm8001_ha->encrypt_info.status = 0;
1324 pm8001_dbg(pm8001_ha, INIT,
1325 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X.Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
1327 pm8001_ha->encrypt_info.cipher_mode,
1328 pm8001_ha->encrypt_info.sec_mode,
1329 pm8001_ha->encrypt_info.status);
1331 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
1332 SCRATCH_PAD3_ENC_DISABLED) {
1333 pm8001_dbg(pm8001_ha, INIT,
1334 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
1336 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
1337 pm8001_ha->encrypt_info.cipher_mode = 0;
1338 pm8001_ha->encrypt_info.sec_mode = 0;
1340 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1341 SCRATCH_PAD3_ENC_DIS_ERR) {
1342 pm8001_ha->encrypt_info.status =
1343 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1344 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1345 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1346 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1347 SCRATCH_PAD3_SMF_ENABLED)
1348 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1349 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1350 SCRATCH_PAD3_SMA_ENABLED)
1351 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1352 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1353 SCRATCH_PAD3_SMB_ENABLED)
1354 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1355 pm8001_dbg(pm8001_ha, INIT,
1356 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1358 pm8001_ha->encrypt_info.cipher_mode,
1359 pm8001_ha->encrypt_info.sec_mode,
1360 pm8001_ha->encrypt_info.status);
1361 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1362 SCRATCH_PAD3_ENC_ENA_ERR) {
1364 pm8001_ha->encrypt_info.status =
1365 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1366 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1367 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1368 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1369 SCRATCH_PAD3_SMF_ENABLED)
1370 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1371 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1372 SCRATCH_PAD3_SMA_ENABLED)
1373 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1374 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1375 SCRATCH_PAD3_SMB_ENABLED)
1376 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1378 pm8001_dbg(pm8001_ha, INIT,
1379 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1381 pm8001_ha->encrypt_info.cipher_mode,
1382 pm8001_ha->encrypt_info.sec_mode,
1383 pm8001_ha->encrypt_info.status);
1389 * pm80xx_encrypt_update - update flash with encryption information
1390 * @pm8001_ha: our hba card information.
1392 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1394 struct kek_mgmt_req payload;
1395 struct inbound_queue_table *circularQ;
1398 u32 opc = OPC_INB_KEK_MANAGEMENT;
1400 memset(&payload, 0, sizeof(struct kek_mgmt_req));
1401 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1405 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1406 payload.tag = cpu_to_le32(tag);
1407 /* Currently only one key is used. New KEK index is 1.
1408 * Current KEK index is 1. Store KEK to NVRAM is 1.
1410 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
1411 KEK_MGMT_SUBOP_KEYCARDUPDATE);
1413 pm8001_dbg(pm8001_ha, DEV,
1414 "Saving Encryption info to flash. payload 0x%x\n",
1415 payload.new_curidx_ksop);
1417 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1418 sizeof(payload), 0);
1420 pm8001_tag_free(pm8001_ha, tag);
1426 * pm80xx_chip_init - the main init function that initializes whole PM8001 chip.
1427 * @pm8001_ha: our hba card information
1429 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1434 /* check the firmware status */
1435 if (-1 == check_fw_ready(pm8001_ha)) {
1436 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
1440 /* Initialize the controller fatal error flag */
1441 pm8001_ha->controller_fatal_error = false;
1443 /* Initialize pci space address eg: mpi offset */
1444 ret = init_pci_device_addresses(pm8001_ha);
1446 pm8001_dbg(pm8001_ha, FAIL,
1447 "Failed to init pci addresses");
1450 init_default_table_values(pm8001_ha);
1451 read_main_config_table(pm8001_ha);
1452 read_general_status_table(pm8001_ha);
1453 read_inbnd_queue_table(pm8001_ha);
1454 read_outbnd_queue_table(pm8001_ha);
1455 read_phy_attr_table(pm8001_ha);
1457 /* update main config table ,inbound table and outbound table */
1458 update_main_config_table(pm8001_ha);
1459 for (i = 0; i < pm8001_ha->max_q_num; i++) {
1460 update_inbnd_queue_table(pm8001_ha, i);
1461 update_outbnd_queue_table(pm8001_ha, i);
1463 /* notify firmware update finished and check initialization status */
1464 if (0 == mpi_init_check(pm8001_ha)) {
1465 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n");
1469 /* send SAS protocol timer configuration page to FW */
1470 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1472 /* Check for encryption */
1473 if (pm8001_ha->chip->encrypt) {
1474 pm8001_dbg(pm8001_ha, INIT, "Checking for encryption\n");
1475 ret = pm80xx_get_encrypt_info(pm8001_ha);
1477 pm8001_dbg(pm8001_ha, INIT, "Encryption error !!\n");
1478 if (pm8001_ha->encrypt_info.status == 0x81) {
1479 pm8001_dbg(pm8001_ha, INIT,
1480 "Encryption enabled with error.Saving encryption key to flash\n");
1481 pm80xx_encrypt_update(pm8001_ha);
1488 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1492 u32 gst_len_mpistate;
1495 ret = init_pci_device_addresses(pm8001_ha);
1497 pm8001_dbg(pm8001_ha, FAIL,
1498 "Failed to init pci addresses");
1502 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1504 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1506 /* wait until Inbound DoorBell Clear Register toggled */
1507 if (IS_SPCV_12G(pm8001_ha->pdev)) {
1508 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
1510 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
1513 msleep(FW_READY_INTERVAL);
1514 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1515 value &= SPCv_MSGU_CFG_TABLE_RESET;
1516 } while ((value != 0) && (--max_wait_count));
1518 if (!max_wait_count) {
1519 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=%x\n", value);
1523 /* check the MPI-State for termination in progress */
1524 /* wait until Inbound DoorBell Clear Register toggled */
1525 max_wait_count = 100; /* 2 sec for spcv/ve */
1527 msleep(FW_READY_INTERVAL);
1529 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1530 GST_GSTLEN_MPIS_OFFSET);
1531 if (GST_MPI_STATE_UNINIT ==
1532 (gst_len_mpistate & GST_MPI_STATE_MASK))
1534 } while (--max_wait_count);
1535 if (!max_wait_count) {
1536 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n",
1537 gst_len_mpistate & GST_MPI_STATE_MASK);
1545 * pm80xx_fatal_errors - returns non-zero *ONLY* when fatal errors
1546 * @pm8001_ha: our hba card information
1548 * Fatal errors are recoverable only after a host reboot.
1551 pm80xx_fatal_errors(struct pm8001_hba_info *pm8001_ha)
1554 u32 scratch_pad_rsvd0 = pm8001_cr32(pm8001_ha, 0,
1555 MSGU_HOST_SCRATCH_PAD_6);
1556 u32 scratch_pad_rsvd1 = pm8001_cr32(pm8001_ha, 0,
1557 MSGU_HOST_SCRATCH_PAD_7);
1558 u32 scratch_pad1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1559 u32 scratch_pad2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1560 u32 scratch_pad3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1562 if (pm8001_ha->chip_id != chip_8006 &&
1563 pm8001_ha->chip_id != chip_8074 &&
1564 pm8001_ha->chip_id != chip_8076) {
1568 if (MSGU_SCRATCHPAD1_STATE_FATAL_ERROR(scratch_pad1)) {
1569 pm8001_dbg(pm8001_ha, FAIL,
1570 "Fatal error SCRATCHPAD1 = 0x%x SCRATCHPAD2 = 0x%x SCRATCHPAD3 = 0x%x SCRATCHPAD_RSVD0 = 0x%x SCRATCHPAD_RSVD1 = 0x%x\n",
1571 scratch_pad1, scratch_pad2, scratch_pad3,
1572 scratch_pad_rsvd0, scratch_pad_rsvd1);
1580 * pm80xx_chip_soft_rst - soft reset the PM8001 chip, so that all
1581 * FW register status are reset to the originated status.
1582 * @pm8001_ha: our hba card information
1586 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1589 u32 bootloader_state;
1590 u32 ibutton0, ibutton1;
1592 /* Process MPI table uninitialization only if FW is ready */
1593 if (!pm8001_ha->controller_fatal_error) {
1594 /* Check if MPI is in ready state to reset */
1595 if (mpi_uninit_check(pm8001_ha) != 0) {
1596 u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1597 u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1598 u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1599 u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1600 pm8001_dbg(pm8001_ha, FAIL,
1601 "MPI state is not ready scratch: %x:%x:%x:%x\n",
1603 /* if things aren't ready but the bootloader is ok then
1604 * try the reset anyway.
1606 if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK)
1610 /* checked for reset register normal state; 0x0 */
1611 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1612 pm8001_dbg(pm8001_ha, INIT, "reset register before write : 0x%x\n",
1615 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1618 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1619 pm8001_dbg(pm8001_ha, INIT, "reset register after write 0x%x\n",
1622 if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1623 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1624 pm8001_dbg(pm8001_ha, MSG,
1625 " soft reset successful [regval: 0x%x]\n",
1628 pm8001_dbg(pm8001_ha, MSG,
1629 " soft reset failed [regval: 0x%x]\n",
1632 /* check bootloader is successfully executed or in HDA mode */
1634 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1635 SCRATCH_PAD1_BOOTSTATE_MASK;
1637 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1638 pm8001_dbg(pm8001_ha, MSG,
1639 "Bootloader state - HDA mode SEEPROM\n");
1640 } else if (bootloader_state ==
1641 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1642 pm8001_dbg(pm8001_ha, MSG,
1643 "Bootloader state - HDA mode Bootstrap Pin\n");
1644 } else if (bootloader_state ==
1645 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1646 pm8001_dbg(pm8001_ha, MSG,
1647 "Bootloader state - HDA mode soft reset\n");
1648 } else if (bootloader_state ==
1649 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1650 pm8001_dbg(pm8001_ha, MSG,
1651 "Bootloader state-HDA mode critical error\n");
1656 /* check the firmware status after reset */
1657 if (-1 == check_fw_ready(pm8001_ha)) {
1658 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
1659 /* check iButton feature support for motherboard controller */
1660 if (pm8001_ha->pdev->subsystem_vendor !=
1661 PCI_VENDOR_ID_ADAPTEC2 &&
1662 pm8001_ha->pdev->subsystem_vendor !=
1663 PCI_VENDOR_ID_ATTO &&
1664 pm8001_ha->pdev->subsystem_vendor != 0) {
1665 ibutton0 = pm8001_cr32(pm8001_ha, 0,
1666 MSGU_HOST_SCRATCH_PAD_6);
1667 ibutton1 = pm8001_cr32(pm8001_ha, 0,
1668 MSGU_HOST_SCRATCH_PAD_7);
1669 if (!ibutton0 && !ibutton1) {
1670 pm8001_dbg(pm8001_ha, FAIL,
1671 "iButton Feature is not Available!!!\n");
1674 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1675 pm8001_dbg(pm8001_ha, FAIL,
1676 "CRC Check for iButton Feature Failed!!!\n");
1681 pm8001_dbg(pm8001_ha, INIT, "SPCv soft reset Complete\n");
1685 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1689 pm8001_dbg(pm8001_ha, INIT, "chip reset start\n");
1691 /* do SPCv chip reset. */
1692 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1693 pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n");
1695 /* Check this ..whether delay is required or no */
1699 /* wait for 20 msec until the firmware gets reloaded */
1703 } while ((--i) != 0);
1705 pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n");
1709 * pm80xx_chip_intx_interrupt_enable - enable PM8001 chip interrupt
1710 * @pm8001_ha: our hba card information
1713 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1715 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1716 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1720 * pm80xx_chip_intx_interrupt_disable - disable PM8001 chip interrupt
1721 * @pm8001_ha: our hba card information
1724 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1726 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1730 * pm80xx_chip_interrupt_enable - enable PM8001 chip interrupt
1731 * @pm8001_ha: our hba card information
1732 * @vec: interrupt number to enable
1735 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1737 #ifdef PM8001_USE_MSIX
1739 mask = (u32)(1 << vec);
1741 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1744 pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1749 * pm80xx_chip_interrupt_disable - disable PM8001 chip interrupt
1750 * @pm8001_ha: our hba card information
1751 * @vec: interrupt number to disable
1754 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1756 #ifdef PM8001_USE_MSIX
1761 mask = (u32)(1 << vec);
1762 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1765 pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1768 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1769 struct pm8001_device *pm8001_ha_dev)
1773 struct pm8001_ccb_info *ccb;
1774 struct sas_task *task = NULL;
1775 struct task_abort_req task_abort;
1776 struct inbound_queue_table *circularQ;
1777 u32 opc = OPC_INB_SATA_ABORT;
1780 if (!pm8001_ha_dev) {
1781 pm8001_dbg(pm8001_ha, FAIL, "dev is null\n");
1785 task = sas_alloc_slow_task(GFP_ATOMIC);
1788 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n");
1792 task->task_done = pm8001_task_done;
1794 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1796 sas_free_task(task);
1800 ccb = &pm8001_ha->ccb_info[ccb_tag];
1801 ccb->device = pm8001_ha_dev;
1802 ccb->ccb_tag = ccb_tag;
1805 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1807 memset(&task_abort, 0, sizeof(task_abort));
1808 task_abort.abort_all = cpu_to_le32(1);
1809 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1810 task_abort.tag = cpu_to_le32(ccb_tag);
1812 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
1813 sizeof(task_abort), 0);
1814 pm8001_dbg(pm8001_ha, FAIL, "Executing abort task end\n");
1816 sas_free_task(task);
1817 pm8001_tag_free(pm8001_ha, ccb_tag);
1821 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1822 struct pm8001_device *pm8001_ha_dev)
1824 struct sata_start_req sata_cmd;
1827 struct pm8001_ccb_info *ccb;
1828 struct sas_task *task = NULL;
1829 struct host_to_dev_fis fis;
1830 struct domain_device *dev;
1831 struct inbound_queue_table *circularQ;
1832 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1834 task = sas_alloc_slow_task(GFP_ATOMIC);
1837 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n");
1840 task->task_done = pm8001_task_done;
1842 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1844 sas_free_task(task);
1845 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate tag !!!\n");
1849 /* allocate domain device by ourselves as libsas
1850 * is not going to provide any
1852 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1854 sas_free_task(task);
1855 pm8001_tag_free(pm8001_ha, ccb_tag);
1856 pm8001_dbg(pm8001_ha, FAIL,
1857 "Domain device cannot be allocated\n");
1862 task->dev->lldd_dev = pm8001_ha_dev;
1864 ccb = &pm8001_ha->ccb_info[ccb_tag];
1865 ccb->device = pm8001_ha_dev;
1866 ccb->ccb_tag = ccb_tag;
1869 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1870 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1872 memset(&sata_cmd, 0, sizeof(sata_cmd));
1873 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1875 /* construct read log FIS */
1876 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1877 fis.fis_type = 0x27;
1879 fis.command = ATA_CMD_READ_LOG_EXT;
1881 fis.sector_count = 0x1;
1883 sata_cmd.tag = cpu_to_le32(ccb_tag);
1884 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1885 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
1886 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1888 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
1889 sizeof(sata_cmd), 0);
1890 pm8001_dbg(pm8001_ha, FAIL, "Executing read log end\n");
1892 sas_free_task(task);
1893 pm8001_tag_free(pm8001_ha, ccb_tag);
1899 * mpi_ssp_completion - process the event that FW response to the SSP request.
1900 * @pm8001_ha: our hba card information
1901 * @piomb: the message contents of this outbound message.
1903 * When FW has completed a ssp request for example a IO request, after it has
1904 * filled the SG data with the data, it will trigger this event representing
1905 * that he has finished the job; please check the corresponding buffer.
1906 * So we will tell the caller who maybe waiting the result to tell upper layer
1907 * that the task has been finished.
1910 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1913 struct pm8001_ccb_info *ccb;
1914 unsigned long flags;
1918 struct ssp_completion_resp *psspPayload;
1919 struct task_status_struct *ts;
1920 struct ssp_response_iu *iu;
1921 struct pm8001_device *pm8001_dev;
1922 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1923 status = le32_to_cpu(psspPayload->status);
1924 tag = le32_to_cpu(psspPayload->tag);
1925 ccb = &pm8001_ha->ccb_info[tag];
1926 if ((status == IO_ABORTED) && ccb->open_retry) {
1927 /* Being completed by another */
1928 ccb->open_retry = 0;
1931 pm8001_dev = ccb->device;
1932 param = le32_to_cpu(psspPayload->param);
1935 if (status && status != IO_UNDERFLOW)
1936 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status);
1937 if (unlikely(!t || !t->lldd_task || !t->dev))
1939 ts = &t->task_status;
1941 pm8001_dbg(pm8001_ha, DEV,
1942 "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t);
1944 /* Print sas address of IO failed device */
1945 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1946 (status != IO_UNDERFLOW))
1947 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n",
1948 SAS_ADDR(t->dev->sas_addr));
1952 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS ,param = 0x%x\n",
1955 ts->resp = SAS_TASK_COMPLETE;
1956 ts->stat = SAS_SAM_STAT_GOOD;
1958 ts->resp = SAS_TASK_COMPLETE;
1959 ts->stat = SAS_PROTO_RESPONSE;
1960 ts->residual = param;
1961 iu = &psspPayload->ssp_resp_iu;
1962 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1965 atomic_dec(&pm8001_dev->running_req);
1968 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
1969 ts->resp = SAS_TASK_COMPLETE;
1970 ts->stat = SAS_ABORTED_TASK;
1972 atomic_dec(&pm8001_dev->running_req);
1975 /* SSP Completion with error */
1976 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW ,param = 0x%x\n",
1978 ts->resp = SAS_TASK_COMPLETE;
1979 ts->stat = SAS_DATA_UNDERRUN;
1980 ts->residual = param;
1982 atomic_dec(&pm8001_dev->running_req);
1985 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
1986 ts->resp = SAS_TASK_UNDELIVERED;
1987 ts->stat = SAS_PHY_DOWN;
1989 atomic_dec(&pm8001_dev->running_req);
1991 case IO_XFER_ERROR_BREAK:
1992 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
1993 ts->resp = SAS_TASK_COMPLETE;
1994 ts->stat = SAS_OPEN_REJECT;
1995 /* Force the midlayer to retry */
1996 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1998 atomic_dec(&pm8001_dev->running_req);
2000 case IO_XFER_ERROR_PHY_NOT_READY:
2001 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2002 ts->resp = SAS_TASK_COMPLETE;
2003 ts->stat = SAS_OPEN_REJECT;
2004 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2006 atomic_dec(&pm8001_dev->running_req);
2008 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
2009 pm8001_dbg(pm8001_ha, IO,
2010 "IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n");
2011 ts->resp = SAS_TASK_COMPLETE;
2012 ts->stat = SAS_OPEN_REJECT;
2013 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2015 atomic_dec(&pm8001_dev->running_req);
2017 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2018 pm8001_dbg(pm8001_ha, IO,
2019 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2020 ts->resp = SAS_TASK_COMPLETE;
2021 ts->stat = SAS_OPEN_REJECT;
2022 ts->open_rej_reason = SAS_OREJ_EPROTO;
2024 atomic_dec(&pm8001_dev->running_req);
2026 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2027 pm8001_dbg(pm8001_ha, IO,
2028 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2029 ts->resp = SAS_TASK_COMPLETE;
2030 ts->stat = SAS_OPEN_REJECT;
2031 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2033 atomic_dec(&pm8001_dev->running_req);
2035 case IO_OPEN_CNX_ERROR_BREAK:
2036 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2037 ts->resp = SAS_TASK_COMPLETE;
2038 ts->stat = SAS_OPEN_REJECT;
2039 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2041 atomic_dec(&pm8001_dev->running_req);
2043 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2044 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2045 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2046 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2047 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2048 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2049 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2050 ts->resp = SAS_TASK_COMPLETE;
2051 ts->stat = SAS_OPEN_REJECT;
2052 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2054 pm8001_handle_event(pm8001_ha,
2056 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2058 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2059 pm8001_dbg(pm8001_ha, IO,
2060 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2061 ts->resp = SAS_TASK_COMPLETE;
2062 ts->stat = SAS_OPEN_REJECT;
2063 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2065 atomic_dec(&pm8001_dev->running_req);
2067 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2068 pm8001_dbg(pm8001_ha, IO,
2069 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2070 ts->resp = SAS_TASK_COMPLETE;
2071 ts->stat = SAS_OPEN_REJECT;
2072 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2074 atomic_dec(&pm8001_dev->running_req);
2076 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2077 pm8001_dbg(pm8001_ha, IO,
2078 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2079 ts->resp = SAS_TASK_UNDELIVERED;
2080 ts->stat = SAS_OPEN_REJECT;
2081 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2083 atomic_dec(&pm8001_dev->running_req);
2085 case IO_XFER_ERROR_NAK_RECEIVED:
2086 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2087 ts->resp = SAS_TASK_COMPLETE;
2088 ts->stat = SAS_OPEN_REJECT;
2089 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2091 atomic_dec(&pm8001_dev->running_req);
2093 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2094 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2095 ts->resp = SAS_TASK_COMPLETE;
2096 ts->stat = SAS_NAK_R_ERR;
2098 atomic_dec(&pm8001_dev->running_req);
2100 case IO_XFER_ERROR_DMA:
2101 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2102 ts->resp = SAS_TASK_COMPLETE;
2103 ts->stat = SAS_OPEN_REJECT;
2105 atomic_dec(&pm8001_dev->running_req);
2107 case IO_XFER_OPEN_RETRY_TIMEOUT:
2108 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2109 ts->resp = SAS_TASK_COMPLETE;
2110 ts->stat = SAS_OPEN_REJECT;
2111 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2113 atomic_dec(&pm8001_dev->running_req);
2115 case IO_XFER_ERROR_OFFSET_MISMATCH:
2116 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2117 ts->resp = SAS_TASK_COMPLETE;
2118 ts->stat = SAS_OPEN_REJECT;
2120 atomic_dec(&pm8001_dev->running_req);
2122 case IO_PORT_IN_RESET:
2123 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2124 ts->resp = SAS_TASK_COMPLETE;
2125 ts->stat = SAS_OPEN_REJECT;
2127 atomic_dec(&pm8001_dev->running_req);
2129 case IO_DS_NON_OPERATIONAL:
2130 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2131 ts->resp = SAS_TASK_COMPLETE;
2132 ts->stat = SAS_OPEN_REJECT;
2134 pm8001_handle_event(pm8001_ha,
2136 IO_DS_NON_OPERATIONAL);
2138 case IO_DS_IN_RECOVERY:
2139 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2140 ts->resp = SAS_TASK_COMPLETE;
2141 ts->stat = SAS_OPEN_REJECT;
2143 atomic_dec(&pm8001_dev->running_req);
2145 case IO_TM_TAG_NOT_FOUND:
2146 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n");
2147 ts->resp = SAS_TASK_COMPLETE;
2148 ts->stat = SAS_OPEN_REJECT;
2150 atomic_dec(&pm8001_dev->running_req);
2152 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2153 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n");
2154 ts->resp = SAS_TASK_COMPLETE;
2155 ts->stat = SAS_OPEN_REJECT;
2157 atomic_dec(&pm8001_dev->running_req);
2159 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2160 pm8001_dbg(pm8001_ha, IO,
2161 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2162 ts->resp = SAS_TASK_COMPLETE;
2163 ts->stat = SAS_OPEN_REJECT;
2164 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2166 atomic_dec(&pm8001_dev->running_req);
2169 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2170 /* not allowed case. Therefore, return failed status */
2171 ts->resp = SAS_TASK_COMPLETE;
2172 ts->stat = SAS_OPEN_REJECT;
2174 atomic_dec(&pm8001_dev->running_req);
2177 pm8001_dbg(pm8001_ha, IO, "scsi_status = 0x%x\n ",
2178 psspPayload->ssp_resp_iu.status);
2179 spin_lock_irqsave(&t->task_state_lock, flags);
2180 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2181 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2182 t->task_state_flags |= SAS_TASK_STATE_DONE;
2183 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2184 spin_unlock_irqrestore(&t->task_state_lock, flags);
2185 pm8001_dbg(pm8001_ha, FAIL,
2186 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2187 t, status, ts->resp, ts->stat);
2189 complete(&t->slow_task->completion);
2190 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2192 spin_unlock_irqrestore(&t->task_state_lock, flags);
2193 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2194 mb();/* in order to force CPU ordering */
2199 /*See the comments for mpi_ssp_completion */
2200 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2203 unsigned long flags;
2204 struct task_status_struct *ts;
2205 struct pm8001_ccb_info *ccb;
2206 struct pm8001_device *pm8001_dev;
2207 struct ssp_event_resp *psspPayload =
2208 (struct ssp_event_resp *)(piomb + 4);
2209 u32 event = le32_to_cpu(psspPayload->event);
2210 u32 tag = le32_to_cpu(psspPayload->tag);
2211 u32 port_id = le32_to_cpu(psspPayload->port_id);
2213 ccb = &pm8001_ha->ccb_info[tag];
2215 pm8001_dev = ccb->device;
2217 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event);
2218 if (unlikely(!t || !t->lldd_task || !t->dev))
2220 ts = &t->task_status;
2221 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",
2222 port_id, tag, event);
2225 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2226 ts->resp = SAS_TASK_COMPLETE;
2227 ts->stat = SAS_DATA_OVERRUN;
2230 atomic_dec(&pm8001_dev->running_req);
2232 case IO_XFER_ERROR_BREAK:
2233 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2234 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2236 case IO_XFER_ERROR_PHY_NOT_READY:
2237 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2238 ts->resp = SAS_TASK_COMPLETE;
2239 ts->stat = SAS_OPEN_REJECT;
2240 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2242 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2243 pm8001_dbg(pm8001_ha, IO,
2244 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2245 ts->resp = SAS_TASK_COMPLETE;
2246 ts->stat = SAS_OPEN_REJECT;
2247 ts->open_rej_reason = SAS_OREJ_EPROTO;
2249 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2250 pm8001_dbg(pm8001_ha, IO,
2251 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2252 ts->resp = SAS_TASK_COMPLETE;
2253 ts->stat = SAS_OPEN_REJECT;
2254 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2256 case IO_OPEN_CNX_ERROR_BREAK:
2257 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2258 ts->resp = SAS_TASK_COMPLETE;
2259 ts->stat = SAS_OPEN_REJECT;
2260 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2262 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2263 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2264 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2265 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2266 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2267 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2268 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2269 ts->resp = SAS_TASK_COMPLETE;
2270 ts->stat = SAS_OPEN_REJECT;
2271 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2273 pm8001_handle_event(pm8001_ha,
2275 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2277 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2278 pm8001_dbg(pm8001_ha, IO,
2279 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2280 ts->resp = SAS_TASK_COMPLETE;
2281 ts->stat = SAS_OPEN_REJECT;
2282 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2284 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2285 pm8001_dbg(pm8001_ha, IO,
2286 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2287 ts->resp = SAS_TASK_COMPLETE;
2288 ts->stat = SAS_OPEN_REJECT;
2289 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2291 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2292 pm8001_dbg(pm8001_ha, IO,
2293 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2294 ts->resp = SAS_TASK_COMPLETE;
2295 ts->stat = SAS_OPEN_REJECT;
2296 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2298 case IO_XFER_ERROR_NAK_RECEIVED:
2299 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2300 ts->resp = SAS_TASK_COMPLETE;
2301 ts->stat = SAS_OPEN_REJECT;
2302 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2304 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2305 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2306 ts->resp = SAS_TASK_COMPLETE;
2307 ts->stat = SAS_NAK_R_ERR;
2309 case IO_XFER_OPEN_RETRY_TIMEOUT:
2310 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2311 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2313 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2314 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2315 ts->resp = SAS_TASK_COMPLETE;
2316 ts->stat = SAS_DATA_OVERRUN;
2318 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2319 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2320 ts->resp = SAS_TASK_COMPLETE;
2321 ts->stat = SAS_DATA_OVERRUN;
2323 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2324 pm8001_dbg(pm8001_ha, IO,
2325 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2326 ts->resp = SAS_TASK_COMPLETE;
2327 ts->stat = SAS_DATA_OVERRUN;
2329 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2330 pm8001_dbg(pm8001_ha, IO,
2331 "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n");
2332 ts->resp = SAS_TASK_COMPLETE;
2333 ts->stat = SAS_DATA_OVERRUN;
2335 case IO_XFER_ERROR_OFFSET_MISMATCH:
2336 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2337 ts->resp = SAS_TASK_COMPLETE;
2338 ts->stat = SAS_DATA_OVERRUN;
2340 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2341 pm8001_dbg(pm8001_ha, IO,
2342 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2343 ts->resp = SAS_TASK_COMPLETE;
2344 ts->stat = SAS_DATA_OVERRUN;
2346 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2347 pm8001_dbg(pm8001_ha, IOERR,
2348 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n");
2349 /* TBC: used default set values */
2350 ts->resp = SAS_TASK_COMPLETE;
2351 ts->stat = SAS_DATA_OVERRUN;
2353 case IO_XFER_CMD_FRAME_ISSUED:
2354 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2357 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2358 /* not allowed case. Therefore, return failed status */
2359 ts->resp = SAS_TASK_COMPLETE;
2360 ts->stat = SAS_DATA_OVERRUN;
2363 spin_lock_irqsave(&t->task_state_lock, flags);
2364 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2365 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2366 t->task_state_flags |= SAS_TASK_STATE_DONE;
2367 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2368 spin_unlock_irqrestore(&t->task_state_lock, flags);
2369 pm8001_dbg(pm8001_ha, FAIL,
2370 "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2371 t, event, ts->resp, ts->stat);
2372 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2374 spin_unlock_irqrestore(&t->task_state_lock, flags);
2375 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2376 mb();/* in order to force CPU ordering */
2381 /*See the comments for mpi_ssp_completion */
2383 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha,
2384 struct outbound_queue_table *circularQ, void *piomb)
2387 struct pm8001_ccb_info *ccb;
2392 u8 sata_addr_low[4];
2393 u32 temp_sata_addr_low, temp_sata_addr_hi;
2395 struct sata_completion_resp *psataPayload;
2396 struct task_status_struct *ts;
2397 struct ata_task_resp *resp ;
2399 struct pm8001_device *pm8001_dev;
2400 unsigned long flags;
2402 psataPayload = (struct sata_completion_resp *)(piomb + 4);
2403 status = le32_to_cpu(psataPayload->status);
2404 param = le32_to_cpu(psataPayload->param);
2405 tag = le32_to_cpu(psataPayload->tag);
2408 pm8001_dbg(pm8001_ha, FAIL, "tag null\n");
2412 ccb = &pm8001_ha->ccb_info[tag];
2414 pm8001_dev = ccb->device;
2417 if (t->dev && (t->dev->lldd_dev))
2418 pm8001_dev = t->dev->lldd_dev;
2420 pm8001_dbg(pm8001_ha, FAIL, "task null\n");
2424 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2425 && unlikely(!t || !t->lldd_task || !t->dev)) {
2426 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2430 ts = &t->task_status;
2432 if (status != IO_SUCCESS) {
2433 pm8001_dbg(pm8001_ha, FAIL,
2434 "IO failed device_id %u status 0x%x tag %d\n",
2435 pm8001_dev->device_id, status, tag);
2438 /* Print sas address of IO failed device */
2439 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2440 (status != IO_UNDERFLOW)) {
2441 if (!((t->dev->parent) &&
2442 (dev_is_expander(t->dev->parent->dev_type)))) {
2443 for (i = 0, j = 4; i <= 3 && j <= 7; i++, j++)
2444 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2445 for (i = 0, j = 0; i <= 3 && j <= 3; i++, j++)
2446 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2447 memcpy(&temp_sata_addr_low, sata_addr_low,
2448 sizeof(sata_addr_low));
2449 memcpy(&temp_sata_addr_hi, sata_addr_hi,
2450 sizeof(sata_addr_hi));
2451 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2452 |((temp_sata_addr_hi << 8) &
2454 ((temp_sata_addr_hi >> 8)
2456 ((temp_sata_addr_hi << 24) &
2458 temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2460 ((temp_sata_addr_low << 8)
2462 ((temp_sata_addr_low >> 8)
2464 ((temp_sata_addr_low << 24)
2466 pm8001_dev->attached_phy +
2468 pm8001_dbg(pm8001_ha, FAIL,
2469 "SAS Address of IO Failure Drive:%08x%08x\n",
2471 temp_sata_addr_low);
2474 pm8001_dbg(pm8001_ha, FAIL,
2475 "SAS Address of IO Failure Drive:%016llx\n",
2476 SAS_ADDR(t->dev->sas_addr));
2481 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2483 ts->resp = SAS_TASK_COMPLETE;
2484 ts->stat = SAS_SAM_STAT_GOOD;
2485 /* check if response is for SEND READ LOG */
2487 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2488 /* set new bit for abort_all */
2489 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2490 /* clear bit for read log */
2491 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2492 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2494 pm8001_tag_free(pm8001_ha, tag);
2500 ts->resp = SAS_TASK_COMPLETE;
2501 ts->stat = SAS_PROTO_RESPONSE;
2502 ts->residual = param;
2503 pm8001_dbg(pm8001_ha, IO,
2504 "SAS_PROTO_RESPONSE len = %d\n",
2506 sata_resp = &psataPayload->sata_resp[0];
2507 resp = (struct ata_task_resp *)ts->buf;
2508 if (t->ata_task.dma_xfer == 0 &&
2509 t->data_dir == DMA_FROM_DEVICE) {
2510 len = sizeof(struct pio_setup_fis);
2511 pm8001_dbg(pm8001_ha, IO,
2512 "PIO read len = %d\n", len);
2513 } else if (t->ata_task.use_ncq) {
2514 len = sizeof(struct set_dev_bits_fis);
2515 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n",
2518 len = sizeof(struct dev_to_host_fis);
2519 pm8001_dbg(pm8001_ha, IO, "other len = %d\n",
2522 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2523 resp->frame_len = len;
2524 memcpy(&resp->ending_fis[0], sata_resp, len);
2525 ts->buf_valid_size = sizeof(*resp);
2527 pm8001_dbg(pm8001_ha, IO,
2528 "response too large\n");
2531 atomic_dec(&pm8001_dev->running_req);
2534 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
2535 ts->resp = SAS_TASK_COMPLETE;
2536 ts->stat = SAS_ABORTED_TASK;
2538 atomic_dec(&pm8001_dev->running_req);
2540 /* following cases are to do cases */
2542 /* SATA Completion with error */
2543 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param);
2544 ts->resp = SAS_TASK_COMPLETE;
2545 ts->stat = SAS_DATA_UNDERRUN;
2546 ts->residual = param;
2548 atomic_dec(&pm8001_dev->running_req);
2551 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2552 ts->resp = SAS_TASK_UNDELIVERED;
2553 ts->stat = SAS_PHY_DOWN;
2555 atomic_dec(&pm8001_dev->running_req);
2557 case IO_XFER_ERROR_BREAK:
2558 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2559 ts->resp = SAS_TASK_COMPLETE;
2560 ts->stat = SAS_INTERRUPTED;
2562 atomic_dec(&pm8001_dev->running_req);
2564 case IO_XFER_ERROR_PHY_NOT_READY:
2565 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2566 ts->resp = SAS_TASK_COMPLETE;
2567 ts->stat = SAS_OPEN_REJECT;
2568 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2570 atomic_dec(&pm8001_dev->running_req);
2572 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2573 pm8001_dbg(pm8001_ha, IO,
2574 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2575 ts->resp = SAS_TASK_COMPLETE;
2576 ts->stat = SAS_OPEN_REJECT;
2577 ts->open_rej_reason = SAS_OREJ_EPROTO;
2579 atomic_dec(&pm8001_dev->running_req);
2581 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2582 pm8001_dbg(pm8001_ha, IO,
2583 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2584 ts->resp = SAS_TASK_COMPLETE;
2585 ts->stat = SAS_OPEN_REJECT;
2586 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2588 atomic_dec(&pm8001_dev->running_req);
2590 case IO_OPEN_CNX_ERROR_BREAK:
2591 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2592 ts->resp = SAS_TASK_COMPLETE;
2593 ts->stat = SAS_OPEN_REJECT;
2594 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2596 atomic_dec(&pm8001_dev->running_req);
2598 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2599 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2600 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2601 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2602 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2603 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2604 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2605 ts->resp = SAS_TASK_COMPLETE;
2606 ts->stat = SAS_DEV_NO_RESPONSE;
2607 if (!t->uldd_task) {
2608 pm8001_handle_event(pm8001_ha,
2610 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2611 ts->resp = SAS_TASK_UNDELIVERED;
2612 ts->stat = SAS_QUEUE_FULL;
2613 spin_unlock_irqrestore(&circularQ->oq_lock,
2614 circularQ->lock_flags);
2615 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2616 spin_lock_irqsave(&circularQ->oq_lock,
2617 circularQ->lock_flags);
2621 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2622 pm8001_dbg(pm8001_ha, IO,
2623 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2624 ts->resp = SAS_TASK_UNDELIVERED;
2625 ts->stat = SAS_OPEN_REJECT;
2626 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2627 if (!t->uldd_task) {
2628 pm8001_handle_event(pm8001_ha,
2630 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2631 ts->resp = SAS_TASK_UNDELIVERED;
2632 ts->stat = SAS_QUEUE_FULL;
2633 spin_unlock_irqrestore(&circularQ->oq_lock,
2634 circularQ->lock_flags);
2635 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2636 spin_lock_irqsave(&circularQ->oq_lock,
2637 circularQ->lock_flags);
2641 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2642 pm8001_dbg(pm8001_ha, IO,
2643 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2644 ts->resp = SAS_TASK_COMPLETE;
2645 ts->stat = SAS_OPEN_REJECT;
2646 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2648 atomic_dec(&pm8001_dev->running_req);
2650 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2651 pm8001_dbg(pm8001_ha, IO,
2652 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n");
2653 ts->resp = SAS_TASK_COMPLETE;
2654 ts->stat = SAS_DEV_NO_RESPONSE;
2655 if (!t->uldd_task) {
2656 pm8001_handle_event(pm8001_ha,
2658 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2659 ts->resp = SAS_TASK_UNDELIVERED;
2660 ts->stat = SAS_QUEUE_FULL;
2661 spin_unlock_irqrestore(&circularQ->oq_lock,
2662 circularQ->lock_flags);
2663 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2664 spin_lock_irqsave(&circularQ->oq_lock,
2665 circularQ->lock_flags);
2669 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2670 pm8001_dbg(pm8001_ha, IO,
2671 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2672 ts->resp = SAS_TASK_COMPLETE;
2673 ts->stat = SAS_OPEN_REJECT;
2674 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2676 atomic_dec(&pm8001_dev->running_req);
2678 case IO_XFER_ERROR_NAK_RECEIVED:
2679 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2680 ts->resp = SAS_TASK_COMPLETE;
2681 ts->stat = SAS_NAK_R_ERR;
2683 atomic_dec(&pm8001_dev->running_req);
2685 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2686 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2687 ts->resp = SAS_TASK_COMPLETE;
2688 ts->stat = SAS_NAK_R_ERR;
2690 atomic_dec(&pm8001_dev->running_req);
2692 case IO_XFER_ERROR_DMA:
2693 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2694 ts->resp = SAS_TASK_COMPLETE;
2695 ts->stat = SAS_ABORTED_TASK;
2697 atomic_dec(&pm8001_dev->running_req);
2699 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2700 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n");
2701 ts->resp = SAS_TASK_UNDELIVERED;
2702 ts->stat = SAS_DEV_NO_RESPONSE;
2704 atomic_dec(&pm8001_dev->running_req);
2706 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2707 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2708 ts->resp = SAS_TASK_COMPLETE;
2709 ts->stat = SAS_DATA_UNDERRUN;
2711 atomic_dec(&pm8001_dev->running_req);
2713 case IO_XFER_OPEN_RETRY_TIMEOUT:
2714 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2715 ts->resp = SAS_TASK_COMPLETE;
2716 ts->stat = SAS_OPEN_TO;
2718 atomic_dec(&pm8001_dev->running_req);
2720 case IO_PORT_IN_RESET:
2721 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2722 ts->resp = SAS_TASK_COMPLETE;
2723 ts->stat = SAS_DEV_NO_RESPONSE;
2725 atomic_dec(&pm8001_dev->running_req);
2727 case IO_DS_NON_OPERATIONAL:
2728 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2729 ts->resp = SAS_TASK_COMPLETE;
2730 ts->stat = SAS_DEV_NO_RESPONSE;
2731 if (!t->uldd_task) {
2732 pm8001_handle_event(pm8001_ha, pm8001_dev,
2733 IO_DS_NON_OPERATIONAL);
2734 ts->resp = SAS_TASK_UNDELIVERED;
2735 ts->stat = SAS_QUEUE_FULL;
2736 spin_unlock_irqrestore(&circularQ->oq_lock,
2737 circularQ->lock_flags);
2738 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2739 spin_lock_irqsave(&circularQ->oq_lock,
2740 circularQ->lock_flags);
2744 case IO_DS_IN_RECOVERY:
2745 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2746 ts->resp = SAS_TASK_COMPLETE;
2747 ts->stat = SAS_DEV_NO_RESPONSE;
2749 atomic_dec(&pm8001_dev->running_req);
2751 case IO_DS_IN_ERROR:
2752 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n");
2753 ts->resp = SAS_TASK_COMPLETE;
2754 ts->stat = SAS_DEV_NO_RESPONSE;
2755 if (!t->uldd_task) {
2756 pm8001_handle_event(pm8001_ha, pm8001_dev,
2758 ts->resp = SAS_TASK_UNDELIVERED;
2759 ts->stat = SAS_QUEUE_FULL;
2760 spin_unlock_irqrestore(&circularQ->oq_lock,
2761 circularQ->lock_flags);
2762 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2763 spin_lock_irqsave(&circularQ->oq_lock,
2764 circularQ->lock_flags);
2768 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2769 pm8001_dbg(pm8001_ha, IO,
2770 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2771 ts->resp = SAS_TASK_COMPLETE;
2772 ts->stat = SAS_OPEN_REJECT;
2773 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2775 atomic_dec(&pm8001_dev->running_req);
2778 pm8001_dbg(pm8001_ha, DEVIO,
2779 "Unknown status device_id %u status 0x%x tag %d\n",
2780 pm8001_dev->device_id, status, tag);
2781 /* not allowed case. Therefore, return failed status */
2782 ts->resp = SAS_TASK_COMPLETE;
2783 ts->stat = SAS_DEV_NO_RESPONSE;
2785 atomic_dec(&pm8001_dev->running_req);
2788 spin_lock_irqsave(&t->task_state_lock, flags);
2789 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2790 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2791 t->task_state_flags |= SAS_TASK_STATE_DONE;
2792 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2793 spin_unlock_irqrestore(&t->task_state_lock, flags);
2794 pm8001_dbg(pm8001_ha, FAIL,
2795 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2796 t, status, ts->resp, ts->stat);
2798 complete(&t->slow_task->completion);
2799 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2801 spin_unlock_irqrestore(&t->task_state_lock, flags);
2802 spin_unlock_irqrestore(&circularQ->oq_lock,
2803 circularQ->lock_flags);
2804 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2805 spin_lock_irqsave(&circularQ->oq_lock,
2806 circularQ->lock_flags);
2810 /*See the comments for mpi_ssp_completion */
2811 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha,
2812 struct outbound_queue_table *circularQ, void *piomb)
2815 struct task_status_struct *ts;
2816 struct pm8001_ccb_info *ccb;
2817 struct pm8001_device *pm8001_dev;
2818 struct sata_event_resp *psataPayload =
2819 (struct sata_event_resp *)(piomb + 4);
2820 u32 event = le32_to_cpu(psataPayload->event);
2821 u32 tag = le32_to_cpu(psataPayload->tag);
2822 u32 port_id = le32_to_cpu(psataPayload->port_id);
2823 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2824 unsigned long flags;
2827 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);
2829 /* Check if this is NCQ error */
2830 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2831 /* find device using device id */
2832 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2833 /* send read log extension */
2835 pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2839 ccb = &pm8001_ha->ccb_info[tag];
2841 pm8001_dev = ccb->device;
2843 if (unlikely(!t || !t->lldd_task || !t->dev)) {
2844 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2848 ts = &t->task_status;
2849 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",
2850 port_id, tag, event);
2853 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2854 ts->resp = SAS_TASK_COMPLETE;
2855 ts->stat = SAS_DATA_OVERRUN;
2858 atomic_dec(&pm8001_dev->running_req);
2860 case IO_XFER_ERROR_BREAK:
2861 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2862 ts->resp = SAS_TASK_COMPLETE;
2863 ts->stat = SAS_INTERRUPTED;
2865 case IO_XFER_ERROR_PHY_NOT_READY:
2866 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2867 ts->resp = SAS_TASK_COMPLETE;
2868 ts->stat = SAS_OPEN_REJECT;
2869 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2871 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2872 pm8001_dbg(pm8001_ha, IO,
2873 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2874 ts->resp = SAS_TASK_COMPLETE;
2875 ts->stat = SAS_OPEN_REJECT;
2876 ts->open_rej_reason = SAS_OREJ_EPROTO;
2878 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2879 pm8001_dbg(pm8001_ha, IO,
2880 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2881 ts->resp = SAS_TASK_COMPLETE;
2882 ts->stat = SAS_OPEN_REJECT;
2883 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2885 case IO_OPEN_CNX_ERROR_BREAK:
2886 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2887 ts->resp = SAS_TASK_COMPLETE;
2888 ts->stat = SAS_OPEN_REJECT;
2889 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2891 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2892 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2893 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2894 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2895 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2896 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2897 pm8001_dbg(pm8001_ha, FAIL,
2898 "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2899 ts->resp = SAS_TASK_UNDELIVERED;
2900 ts->stat = SAS_DEV_NO_RESPONSE;
2901 if (!t->uldd_task) {
2902 pm8001_handle_event(pm8001_ha,
2904 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2905 ts->resp = SAS_TASK_COMPLETE;
2906 ts->stat = SAS_QUEUE_FULL;
2907 spin_unlock_irqrestore(&circularQ->oq_lock,
2908 circularQ->lock_flags);
2909 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2910 spin_lock_irqsave(&circularQ->oq_lock,
2911 circularQ->lock_flags);
2915 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2916 pm8001_dbg(pm8001_ha, IO,
2917 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2918 ts->resp = SAS_TASK_UNDELIVERED;
2919 ts->stat = SAS_OPEN_REJECT;
2920 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2922 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2923 pm8001_dbg(pm8001_ha, IO,
2924 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2925 ts->resp = SAS_TASK_COMPLETE;
2926 ts->stat = SAS_OPEN_REJECT;
2927 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2929 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2930 pm8001_dbg(pm8001_ha, IO,
2931 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2932 ts->resp = SAS_TASK_COMPLETE;
2933 ts->stat = SAS_OPEN_REJECT;
2934 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2936 case IO_XFER_ERROR_NAK_RECEIVED:
2937 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2938 ts->resp = SAS_TASK_COMPLETE;
2939 ts->stat = SAS_NAK_R_ERR;
2941 case IO_XFER_ERROR_PEER_ABORTED:
2942 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n");
2943 ts->resp = SAS_TASK_COMPLETE;
2944 ts->stat = SAS_NAK_R_ERR;
2946 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2947 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2948 ts->resp = SAS_TASK_COMPLETE;
2949 ts->stat = SAS_DATA_UNDERRUN;
2951 case IO_XFER_OPEN_RETRY_TIMEOUT:
2952 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2953 ts->resp = SAS_TASK_COMPLETE;
2954 ts->stat = SAS_OPEN_TO;
2956 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2957 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2958 ts->resp = SAS_TASK_COMPLETE;
2959 ts->stat = SAS_OPEN_TO;
2961 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2962 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2963 ts->resp = SAS_TASK_COMPLETE;
2964 ts->stat = SAS_OPEN_TO;
2966 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2967 pm8001_dbg(pm8001_ha, IO,
2968 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2969 ts->resp = SAS_TASK_COMPLETE;
2970 ts->stat = SAS_OPEN_TO;
2972 case IO_XFER_ERROR_OFFSET_MISMATCH:
2973 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2974 ts->resp = SAS_TASK_COMPLETE;
2975 ts->stat = SAS_OPEN_TO;
2977 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2978 pm8001_dbg(pm8001_ha, IO,
2979 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2980 ts->resp = SAS_TASK_COMPLETE;
2981 ts->stat = SAS_OPEN_TO;
2983 case IO_XFER_CMD_FRAME_ISSUED:
2984 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2986 case IO_XFER_PIO_SETUP_ERROR:
2987 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n");
2988 ts->resp = SAS_TASK_COMPLETE;
2989 ts->stat = SAS_OPEN_TO;
2991 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2992 pm8001_dbg(pm8001_ha, FAIL,
2993 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n");
2994 /* TBC: used default set values */
2995 ts->resp = SAS_TASK_COMPLETE;
2996 ts->stat = SAS_OPEN_TO;
2998 case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2999 pm8001_dbg(pm8001_ha, FAIL, "IO_XFR_DMA_ACTIVATE_TIMEOUT\n");
3000 /* TBC: used default set values */
3001 ts->resp = SAS_TASK_COMPLETE;
3002 ts->stat = SAS_OPEN_TO;
3005 pm8001_dbg(pm8001_ha, IO, "Unknown status 0x%x\n", event);
3006 /* not allowed case. Therefore, return failed status */
3007 ts->resp = SAS_TASK_COMPLETE;
3008 ts->stat = SAS_OPEN_TO;
3011 spin_lock_irqsave(&t->task_state_lock, flags);
3012 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3013 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3014 t->task_state_flags |= SAS_TASK_STATE_DONE;
3015 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3016 spin_unlock_irqrestore(&t->task_state_lock, flags);
3017 pm8001_dbg(pm8001_ha, FAIL,
3018 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
3019 t, event, ts->resp, ts->stat);
3020 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3022 spin_unlock_irqrestore(&t->task_state_lock, flags);
3023 spin_unlock_irqrestore(&circularQ->oq_lock,
3024 circularQ->lock_flags);
3025 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
3026 spin_lock_irqsave(&circularQ->oq_lock,
3027 circularQ->lock_flags);
3031 /*See the comments for mpi_ssp_completion */
3033 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
3037 struct pm8001_ccb_info *ccb;
3038 unsigned long flags;
3041 struct smp_completion_resp *psmpPayload;
3042 struct task_status_struct *ts;
3043 struct pm8001_device *pm8001_dev;
3045 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
3046 status = le32_to_cpu(psmpPayload->status);
3047 tag = le32_to_cpu(psmpPayload->tag);
3049 ccb = &pm8001_ha->ccb_info[tag];
3050 param = le32_to_cpu(psmpPayload->param);
3052 ts = &t->task_status;
3053 pm8001_dev = ccb->device;
3055 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status);
3056 if (unlikely(!t || !t->lldd_task || !t->dev))
3059 pm8001_dbg(pm8001_ha, DEV, "tag::0x%x status::0x%x\n", tag, status);
3064 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
3065 ts->resp = SAS_TASK_COMPLETE;
3066 ts->stat = SAS_SAM_STAT_GOOD;
3068 atomic_dec(&pm8001_dev->running_req);
3069 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3070 struct scatterlist *sg_resp = &t->smp_task.smp_resp;
3074 pm8001_dbg(pm8001_ha, IO,
3075 "DIRECT RESPONSE Length:%d\n",
3077 to = kmap_atomic(sg_page(sg_resp));
3078 payload = to + sg_resp->offset;
3079 for (i = 0; i < param; i++) {
3080 *(payload + i) = psmpPayload->_r_a[i];
3081 pm8001_dbg(pm8001_ha, IO,
3082 "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
3084 psmpPayload->_r_a[i]);
3090 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n");
3091 ts->resp = SAS_TASK_COMPLETE;
3092 ts->stat = SAS_ABORTED_TASK;
3094 atomic_dec(&pm8001_dev->running_req);
3097 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
3098 ts->resp = SAS_TASK_COMPLETE;
3099 ts->stat = SAS_DATA_OVERRUN;
3102 atomic_dec(&pm8001_dev->running_req);
3105 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
3106 ts->resp = SAS_TASK_COMPLETE;
3107 ts->stat = SAS_PHY_DOWN;
3109 case IO_ERROR_HW_TIMEOUT:
3110 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n");
3111 ts->resp = SAS_TASK_COMPLETE;
3112 ts->stat = SAS_SAM_STAT_BUSY;
3114 case IO_XFER_ERROR_BREAK:
3115 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
3116 ts->resp = SAS_TASK_COMPLETE;
3117 ts->stat = SAS_SAM_STAT_BUSY;
3119 case IO_XFER_ERROR_PHY_NOT_READY:
3120 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
3121 ts->resp = SAS_TASK_COMPLETE;
3122 ts->stat = SAS_SAM_STAT_BUSY;
3124 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
3125 pm8001_dbg(pm8001_ha, IO,
3126 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
3127 ts->resp = SAS_TASK_COMPLETE;
3128 ts->stat = SAS_OPEN_REJECT;
3129 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3131 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
3132 pm8001_dbg(pm8001_ha, IO,
3133 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
3134 ts->resp = SAS_TASK_COMPLETE;
3135 ts->stat = SAS_OPEN_REJECT;
3136 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3138 case IO_OPEN_CNX_ERROR_BREAK:
3139 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
3140 ts->resp = SAS_TASK_COMPLETE;
3141 ts->stat = SAS_OPEN_REJECT;
3142 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
3144 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
3145 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
3146 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
3147 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
3148 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
3149 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
3150 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
3151 ts->resp = SAS_TASK_COMPLETE;
3152 ts->stat = SAS_OPEN_REJECT;
3153 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3154 pm8001_handle_event(pm8001_ha,
3156 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
3158 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
3159 pm8001_dbg(pm8001_ha, IO,
3160 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
3161 ts->resp = SAS_TASK_COMPLETE;
3162 ts->stat = SAS_OPEN_REJECT;
3163 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
3165 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
3166 pm8001_dbg(pm8001_ha, IO,
3167 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
3168 ts->resp = SAS_TASK_COMPLETE;
3169 ts->stat = SAS_OPEN_REJECT;
3170 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
3172 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
3173 pm8001_dbg(pm8001_ha, IO,
3174 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
3175 ts->resp = SAS_TASK_COMPLETE;
3176 ts->stat = SAS_OPEN_REJECT;
3177 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
3179 case IO_XFER_ERROR_RX_FRAME:
3180 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n");
3181 ts->resp = SAS_TASK_COMPLETE;
3182 ts->stat = SAS_DEV_NO_RESPONSE;
3184 case IO_XFER_OPEN_RETRY_TIMEOUT:
3185 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
3186 ts->resp = SAS_TASK_COMPLETE;
3187 ts->stat = SAS_OPEN_REJECT;
3188 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3190 case IO_ERROR_INTERNAL_SMP_RESOURCE:
3191 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n");
3192 ts->resp = SAS_TASK_COMPLETE;
3193 ts->stat = SAS_QUEUE_FULL;
3195 case IO_PORT_IN_RESET:
3196 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
3197 ts->resp = SAS_TASK_COMPLETE;
3198 ts->stat = SAS_OPEN_REJECT;
3199 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3201 case IO_DS_NON_OPERATIONAL:
3202 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
3203 ts->resp = SAS_TASK_COMPLETE;
3204 ts->stat = SAS_DEV_NO_RESPONSE;
3206 case IO_DS_IN_RECOVERY:
3207 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
3208 ts->resp = SAS_TASK_COMPLETE;
3209 ts->stat = SAS_OPEN_REJECT;
3210 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3212 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3213 pm8001_dbg(pm8001_ha, IO,
3214 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
3215 ts->resp = SAS_TASK_COMPLETE;
3216 ts->stat = SAS_OPEN_REJECT;
3217 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3220 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
3221 ts->resp = SAS_TASK_COMPLETE;
3222 ts->stat = SAS_DEV_NO_RESPONSE;
3223 /* not allowed case. Therefore, return failed status */
3226 spin_lock_irqsave(&t->task_state_lock, flags);
3227 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3228 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3229 t->task_state_flags |= SAS_TASK_STATE_DONE;
3230 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3231 spin_unlock_irqrestore(&t->task_state_lock, flags);
3232 pm8001_dbg(pm8001_ha, FAIL,
3233 "task 0x%p done with io_status 0x%x resp 0x%xstat 0x%x but aborted by upper layer!\n",
3234 t, status, ts->resp, ts->stat);
3235 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3237 spin_unlock_irqrestore(&t->task_state_lock, flags);
3238 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3239 mb();/* in order to force CPU ordering */
3245 * pm80xx_hw_event_ack_req- For PM8001, some events need to acknowledge to FW.
3246 * @pm8001_ha: our hba card information
3247 * @Qnum: the outbound queue message number.
3248 * @SEA: source of event to ack
3249 * @port_id: port id.
3251 * @param0: parameter 0.
3252 * @param1: parameter 1.
3254 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3255 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3257 struct hw_event_ack_req payload;
3258 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3260 struct inbound_queue_table *circularQ;
3262 memset((u8 *)&payload, 0, sizeof(payload));
3263 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3264 payload.tag = cpu_to_le32(1);
3265 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3266 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
3267 payload.param0 = cpu_to_le32(param0);
3268 payload.param1 = cpu_to_le32(param1);
3269 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
3270 sizeof(payload), 0);
3273 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3274 u32 phyId, u32 phy_op);
3276 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
3279 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
3280 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3281 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3282 u32 lr_status_evt_portid =
3283 le32_to_cpu(pPayload->lr_status_evt_portid);
3284 u8 deviceType = pPayload->sas_identify.dev_type;
3285 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3286 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3287 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3288 struct pm8001_port *port = &pm8001_ha->port[port_id];
3290 if (deviceType == SAS_END_DEVICE) {
3291 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3292 PHY_NOTIFY_ENABLE_SPINUP);
3295 port->wide_port_phymap |= (1U << phy_id);
3296 pm8001_get_lrate_mode(phy, link_rate);
3297 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3298 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3299 phy->phy_attached = 1;
3303 * hw_event_sas_phy_up - FW tells me a SAS phy up event.
3304 * @pm8001_ha: our hba card information
3305 * @piomb: IO message buffer
3308 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3310 struct hw_event_resp *pPayload =
3311 (struct hw_event_resp *)(piomb + 4);
3312 u32 lr_status_evt_portid =
3313 le32_to_cpu(pPayload->lr_status_evt_portid);
3314 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3317 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3318 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3320 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3321 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3323 struct pm8001_port *port = &pm8001_ha->port[port_id];
3324 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3325 unsigned long flags;
3326 u8 deviceType = pPayload->sas_identify.dev_type;
3328 port->port_id = port_id;
3329 port->port_state = portstate;
3330 port->wide_port_phymap |= (1U << phy_id);
3331 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3332 pm8001_dbg(pm8001_ha, MSG,
3333 "portid:%d; phyid:%d; linkrate:%d; portstate:%x; devicetype:%x\n",
3334 port_id, phy_id, link_rate, portstate, deviceType);
3336 switch (deviceType) {
3337 case SAS_PHY_UNUSED:
3338 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n");
3340 case SAS_END_DEVICE:
3341 pm8001_dbg(pm8001_ha, MSG, "end device.\n");
3342 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3343 PHY_NOTIFY_ENABLE_SPINUP);
3344 port->port_attached = 1;
3345 pm8001_get_lrate_mode(phy, link_rate);
3347 case SAS_EDGE_EXPANDER_DEVICE:
3348 pm8001_dbg(pm8001_ha, MSG, "expander device.\n");
3349 port->port_attached = 1;
3350 pm8001_get_lrate_mode(phy, link_rate);
3352 case SAS_FANOUT_EXPANDER_DEVICE:
3353 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n");
3354 port->port_attached = 1;
3355 pm8001_get_lrate_mode(phy, link_rate);
3358 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n",
3362 phy->phy_type |= PORT_TYPE_SAS;
3363 phy->identify.device_type = deviceType;
3364 phy->phy_attached = 1;
3365 if (phy->identify.device_type == SAS_END_DEVICE)
3366 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3367 else if (phy->identify.device_type != SAS_PHY_UNUSED)
3368 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3369 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3370 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3371 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3372 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3373 sizeof(struct sas_identify_frame)-4);
3374 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3375 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3376 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3377 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3378 mdelay(200); /* delay a moment to wait for disk to spin up */
3379 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3383 * hw_event_sata_phy_up - FW tells me a SATA phy up event.
3384 * @pm8001_ha: our hba card information
3385 * @piomb: IO message buffer
3388 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3390 struct hw_event_resp *pPayload =
3391 (struct hw_event_resp *)(piomb + 4);
3392 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3393 u32 lr_status_evt_portid =
3394 le32_to_cpu(pPayload->lr_status_evt_portid);
3396 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3397 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3399 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3401 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3403 struct pm8001_port *port = &pm8001_ha->port[port_id];
3404 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3405 unsigned long flags;
3406 pm8001_dbg(pm8001_ha, DEVIO,
3407 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
3408 port_id, phy_id, link_rate, portstate);
3411 port->port_id = port_id;
3412 port->port_state = portstate;
3413 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3414 port->port_attached = 1;
3415 pm8001_get_lrate_mode(phy, link_rate);
3416 phy->phy_type |= PORT_TYPE_SATA;
3417 phy->phy_attached = 1;
3418 phy->sas_phy.oob_mode = SATA_OOB_MODE;
3419 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3420 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3421 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3422 sizeof(struct dev_to_host_fis));
3423 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3424 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3425 phy->identify.device_type = SAS_SATA_DEV;
3426 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3427 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3428 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3432 * hw_event_phy_down - we should notify the libsas the phy is down.
3433 * @pm8001_ha: our hba card information
3434 * @piomb: IO message buffer
3437 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3439 struct hw_event_resp *pPayload =
3440 (struct hw_event_resp *)(piomb + 4);
3442 u32 lr_status_evt_portid =
3443 le32_to_cpu(pPayload->lr_status_evt_portid);
3444 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3445 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3447 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3448 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3450 struct pm8001_port *port = &pm8001_ha->port[port_id];
3451 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3452 u32 port_sata = (phy->phy_type & PORT_TYPE_SATA);
3453 port->port_state = portstate;
3454 phy->identify.device_type = 0;
3455 phy->phy_attached = 0;
3456 switch (portstate) {
3460 pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n",
3462 pm8001_dbg(pm8001_ha, MSG,
3463 " Last phy Down and port invalid\n");
3466 port->port_attached = 0;
3467 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3468 port_id, phy_id, 0, 0);
3470 sas_phy_disconnected(&phy->sas_phy);
3473 pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n",
3476 case PORT_NOT_ESTABLISHED:
3477 pm8001_dbg(pm8001_ha, MSG,
3478 " Phy Down and PORT_NOT_ESTABLISHED\n");
3479 port->port_attached = 0;
3482 pm8001_dbg(pm8001_ha, MSG, " Phy Down and PORT_LOSTCOMM\n");
3483 pm8001_dbg(pm8001_ha, MSG,
3484 " Last phy Down and port invalid\n");
3486 port->port_attached = 0;
3488 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3489 port_id, phy_id, 0, 0);
3491 sas_phy_disconnected(&phy->sas_phy);
3494 port->port_attached = 0;
3495 pm8001_dbg(pm8001_ha, DEVIO,
3496 " Phy Down and(default) = 0x%x\n",
3501 if (port_sata && (portstate != PORT_IN_RESET))
3502 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL,
3506 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3508 struct phy_start_resp *pPayload =
3509 (struct phy_start_resp *)(piomb + 4);
3511 le32_to_cpu(pPayload->status);
3513 le32_to_cpu(pPayload->phyid) & 0xFF;
3514 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3516 pm8001_dbg(pm8001_ha, INIT,
3517 "phy start resp status:0x%x, phyid:0x%x\n",
3520 phy->phy_state = PHY_LINK_DOWN;
3522 if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3523 phy->enable_completion != NULL) {
3524 complete(phy->enable_completion);
3525 phy->enable_completion = NULL;
3532 * mpi_thermal_hw_event - a thermal hw event has come.
3533 * @pm8001_ha: our hba card information
3534 * @piomb: IO message buffer
3536 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3538 struct thermal_hw_event *pPayload =
3539 (struct thermal_hw_event *)(piomb + 4);
3541 u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3542 u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3544 if (thermal_event & 0x40) {
3545 pm8001_dbg(pm8001_ha, IO,
3546 "Thermal Event: Local high temperature violated!\n");
3547 pm8001_dbg(pm8001_ha, IO,
3548 "Thermal Event: Measured local high temperature %d\n",
3549 ((rht_lht & 0xFF00) >> 8));
3551 if (thermal_event & 0x10) {
3552 pm8001_dbg(pm8001_ha, IO,
3553 "Thermal Event: Remote high temperature violated!\n");
3554 pm8001_dbg(pm8001_ha, IO,
3555 "Thermal Event: Measured remote high temperature %d\n",
3556 ((rht_lht & 0xFF000000) >> 24));
3562 * mpi_hw_event - The hw event has come.
3563 * @pm8001_ha: our hba card information
3564 * @piomb: IO message buffer
3566 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3568 unsigned long flags, i;
3569 struct hw_event_resp *pPayload =
3570 (struct hw_event_resp *)(piomb + 4);
3571 u32 lr_status_evt_portid =
3572 le32_to_cpu(pPayload->lr_status_evt_portid);
3573 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3574 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3576 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3578 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3580 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3581 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3582 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3583 struct pm8001_port *port = &pm8001_ha->port[port_id];
3584 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3585 pm8001_dbg(pm8001_ha, DEV,
3586 "portid:%d phyid:%d event:0x%x status:0x%x\n",
3587 port_id, phy_id, eventType, status);
3589 switch (eventType) {
3591 case HW_EVENT_SAS_PHY_UP:
3592 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n");
3593 hw_event_sas_phy_up(pm8001_ha, piomb);
3595 case HW_EVENT_SATA_PHY_UP:
3596 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n");
3597 hw_event_sata_phy_up(pm8001_ha, piomb);
3599 case HW_EVENT_SATA_SPINUP_HOLD:
3600 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n");
3601 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD,
3604 case HW_EVENT_PHY_DOWN:
3605 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n");
3606 hw_event_phy_down(pm8001_ha, piomb);
3607 if (pm8001_ha->reset_in_progress) {
3608 pm8001_dbg(pm8001_ha, MSG, "Reset in progress\n");
3611 phy->phy_attached = 0;
3612 phy->phy_state = PHY_LINK_DISABLE;
3614 case HW_EVENT_PORT_INVALID:
3615 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n");
3616 sas_phy_disconnected(sas_phy);
3617 phy->phy_attached = 0;
3618 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3621 /* the broadcast change primitive received, tell the LIBSAS this event
3622 to revalidate the sas domain*/
3623 case HW_EVENT_BROADCAST_CHANGE:
3624 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n");
3625 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3626 port_id, phy_id, 1, 0);
3627 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3628 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3629 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3630 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3633 case HW_EVENT_PHY_ERROR:
3634 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n");
3635 sas_phy_disconnected(&phy->sas_phy);
3636 phy->phy_attached = 0;
3637 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC);
3639 case HW_EVENT_BROADCAST_EXP:
3640 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n");
3641 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3642 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3643 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3644 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3647 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3648 pm8001_dbg(pm8001_ha, MSG,
3649 "HW_EVENT_LINK_ERR_INVALID_DWORD\n");
3650 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3651 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3653 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3654 pm8001_dbg(pm8001_ha, MSG,
3655 "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n");
3656 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3657 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3658 port_id, phy_id, 0, 0);
3660 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3661 pm8001_dbg(pm8001_ha, MSG,
3662 "HW_EVENT_LINK_ERR_CODE_VIOLATION\n");
3663 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3664 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3665 port_id, phy_id, 0, 0);
3667 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3668 pm8001_dbg(pm8001_ha, MSG,
3669 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n");
3670 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3671 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3672 port_id, phy_id, 0, 0);
3674 case HW_EVENT_MALFUNCTION:
3675 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n");
3677 case HW_EVENT_BROADCAST_SES:
3678 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n");
3679 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3680 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3681 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3682 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3685 case HW_EVENT_INBOUND_CRC_ERROR:
3686 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n");
3687 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3688 HW_EVENT_INBOUND_CRC_ERROR,
3689 port_id, phy_id, 0, 0);
3691 case HW_EVENT_HARD_RESET_RECEIVED:
3692 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n");
3693 sas_notify_port_event(sas_phy, PORTE_HARD_RESET, GFP_ATOMIC);
3695 case HW_EVENT_ID_FRAME_TIMEOUT:
3696 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n");
3697 sas_phy_disconnected(sas_phy);
3698 phy->phy_attached = 0;
3699 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3702 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3703 pm8001_dbg(pm8001_ha, MSG,
3704 "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n");
3705 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3706 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3707 port_id, phy_id, 0, 0);
3708 sas_phy_disconnected(sas_phy);
3709 phy->phy_attached = 0;
3710 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3713 case HW_EVENT_PORT_RESET_TIMER_TMO:
3714 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n");
3715 if (!pm8001_ha->phy[phy_id].reset_completion) {
3716 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3717 port_id, phy_id, 0, 0);
3719 sas_phy_disconnected(sas_phy);
3720 phy->phy_attached = 0;
3721 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3723 if (pm8001_ha->phy[phy_id].reset_completion) {
3724 pm8001_ha->phy[phy_id].port_reset_status =
3726 complete(pm8001_ha->phy[phy_id].reset_completion);
3727 pm8001_ha->phy[phy_id].reset_completion = NULL;
3730 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3731 pm8001_dbg(pm8001_ha, MSG,
3732 "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n");
3733 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3734 HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3735 port_id, phy_id, 0, 0);
3736 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
3737 if (port->wide_port_phymap & (1 << i)) {
3738 phy = &pm8001_ha->phy[i];
3739 sas_notify_phy_event(&phy->sas_phy,
3740 PHYE_LOSS_OF_SIGNAL, GFP_ATOMIC);
3741 port->wide_port_phymap &= ~(1 << i);
3745 case HW_EVENT_PORT_RECOVER:
3746 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n");
3747 hw_event_port_recover(pm8001_ha, piomb);
3749 case HW_EVENT_PORT_RESET_COMPLETE:
3750 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n");
3751 if (pm8001_ha->phy[phy_id].reset_completion) {
3752 pm8001_ha->phy[phy_id].port_reset_status =
3754 complete(pm8001_ha->phy[phy_id].reset_completion);
3755 pm8001_ha->phy[phy_id].reset_completion = NULL;
3758 case EVENT_BROADCAST_ASYNCH_EVENT:
3759 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n");
3762 pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type 0x%x\n",
3770 * mpi_phy_stop_resp - SPCv specific
3771 * @pm8001_ha: our hba card information
3772 * @piomb: IO message buffer
3774 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3776 struct phy_stop_resp *pPayload =
3777 (struct phy_stop_resp *)(piomb + 4);
3779 le32_to_cpu(pPayload->status);
3781 le32_to_cpu(pPayload->phyid) & 0xFF;
3782 struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3783 pm8001_dbg(pm8001_ha, MSG, "phy:0x%x status:0x%x\n",
3785 if (status == PHY_STOP_SUCCESS ||
3786 status == PHY_STOP_ERR_DEVICE_ATTACHED)
3787 phy->phy_state = PHY_LINK_DISABLE;
3792 * mpi_set_controller_config_resp - SPCv specific
3793 * @pm8001_ha: our hba card information
3794 * @piomb: IO message buffer
3796 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3799 struct set_ctrl_cfg_resp *pPayload =
3800 (struct set_ctrl_cfg_resp *)(piomb + 4);
3801 u32 status = le32_to_cpu(pPayload->status);
3802 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3804 pm8001_dbg(pm8001_ha, MSG,
3805 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3806 status, err_qlfr_pgcd);
3812 * mpi_get_controller_config_resp - SPCv specific
3813 * @pm8001_ha: our hba card information
3814 * @piomb: IO message buffer
3816 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3819 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3825 * mpi_get_phy_profile_resp - SPCv specific
3826 * @pm8001_ha: our hba card information
3827 * @piomb: IO message buffer
3829 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3832 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3838 * mpi_flash_op_ext_resp - SPCv specific
3839 * @pm8001_ha: our hba card information
3840 * @piomb: IO message buffer
3842 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3844 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3850 * mpi_set_phy_profile_resp - SPCv specific
3851 * @pm8001_ha: our hba card information
3852 * @piomb: IO message buffer
3854 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3860 struct set_phy_profile_resp *pPayload =
3861 (struct set_phy_profile_resp *)(piomb + 4);
3862 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3863 u32 status = le32_to_cpu(pPayload->status);
3865 tag = le32_to_cpu(pPayload->tag);
3866 page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3868 /* status is FAILED */
3869 pm8001_dbg(pm8001_ha, FAIL,
3870 "PhyProfile command failed with status 0x%08X\n",
3874 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3875 pm8001_dbg(pm8001_ha, FAIL, "Invalid page code 0x%X\n",
3880 pm8001_tag_free(pm8001_ha, tag);
3885 * mpi_kek_management_resp - SPCv specific
3886 * @pm8001_ha: our hba card information
3887 * @piomb: IO message buffer
3889 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3892 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3894 u32 status = le32_to_cpu(pPayload->status);
3895 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3896 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3898 pm8001_dbg(pm8001_ha, MSG,
3899 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3900 status, kidx_new_curr_ksop, err_qlfr);
3906 * mpi_dek_management_resp - SPCv specific
3907 * @pm8001_ha: our hba card information
3908 * @piomb: IO message buffer
3910 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3913 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3919 * ssp_coalesced_comp_resp - SPCv specific
3920 * @pm8001_ha: our hba card information
3921 * @piomb: IO message buffer
3923 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3926 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3932 * process_one_iomb - process one outbound Queue memory block
3933 * @pm8001_ha: our hba card information
3934 * @piomb: IO message buffer
3936 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha,
3937 struct outbound_queue_table *circularQ, void *piomb)
3939 __le32 pHeader = *(__le32 *)piomb;
3940 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3944 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n");
3946 case OPC_OUB_HW_EVENT:
3947 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n");
3948 mpi_hw_event(pm8001_ha, piomb);
3950 case OPC_OUB_THERM_HW_EVENT:
3951 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_THERMAL_EVENT\n");
3952 mpi_thermal_hw_event(pm8001_ha, piomb);
3954 case OPC_OUB_SSP_COMP:
3955 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n");
3956 mpi_ssp_completion(pm8001_ha, piomb);
3958 case OPC_OUB_SMP_COMP:
3959 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n");
3960 mpi_smp_completion(pm8001_ha, piomb);
3962 case OPC_OUB_LOCAL_PHY_CNTRL:
3963 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n");
3964 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3966 case OPC_OUB_DEV_REGIST:
3967 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n");
3968 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3970 case OPC_OUB_DEREG_DEV:
3971 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n");
3972 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3974 case OPC_OUB_GET_DEV_HANDLE:
3975 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n");
3977 case OPC_OUB_SATA_COMP:
3978 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n");
3979 mpi_sata_completion(pm8001_ha, circularQ, piomb);
3981 case OPC_OUB_SATA_EVENT:
3982 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n");
3983 mpi_sata_event(pm8001_ha, circularQ, piomb);
3985 case OPC_OUB_SSP_EVENT:
3986 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n");
3987 mpi_ssp_event(pm8001_ha, piomb);
3989 case OPC_OUB_DEV_HANDLE_ARRIV:
3990 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n");
3991 /*This is for target*/
3993 case OPC_OUB_SSP_RECV_EVENT:
3994 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n");
3995 /*This is for target*/
3997 case OPC_OUB_FW_FLASH_UPDATE:
3998 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n");
3999 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
4001 case OPC_OUB_GPIO_RESPONSE:
4002 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n");
4004 case OPC_OUB_GPIO_EVENT:
4005 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n");
4007 case OPC_OUB_GENERAL_EVENT:
4008 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n");
4009 pm8001_mpi_general_event(pm8001_ha, piomb);
4011 case OPC_OUB_SSP_ABORT_RSP:
4012 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n");
4013 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4015 case OPC_OUB_SATA_ABORT_RSP:
4016 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n");
4017 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4019 case OPC_OUB_SAS_DIAG_MODE_START_END:
4020 pm8001_dbg(pm8001_ha, MSG,
4021 "OPC_OUB_SAS_DIAG_MODE_START_END\n");
4023 case OPC_OUB_SAS_DIAG_EXECUTE:
4024 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n");
4026 case OPC_OUB_GET_TIME_STAMP:
4027 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n");
4029 case OPC_OUB_SAS_HW_EVENT_ACK:
4030 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n");
4032 case OPC_OUB_PORT_CONTROL:
4033 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n");
4035 case OPC_OUB_SMP_ABORT_RSP:
4036 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n");
4037 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4039 case OPC_OUB_GET_NVMD_DATA:
4040 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n");
4041 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
4043 case OPC_OUB_SET_NVMD_DATA:
4044 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n");
4045 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
4047 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
4048 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n");
4050 case OPC_OUB_SET_DEVICE_STATE:
4051 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n");
4052 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
4054 case OPC_OUB_GET_DEVICE_STATE:
4055 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n");
4057 case OPC_OUB_SET_DEV_INFO:
4058 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n");
4060 /* spcv specific commands */
4061 case OPC_OUB_PHY_START_RESP:
4062 pm8001_dbg(pm8001_ha, MSG,
4063 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc);
4064 mpi_phy_start_resp(pm8001_ha, piomb);
4066 case OPC_OUB_PHY_STOP_RESP:
4067 pm8001_dbg(pm8001_ha, MSG,
4068 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc);
4069 mpi_phy_stop_resp(pm8001_ha, piomb);
4071 case OPC_OUB_SET_CONTROLLER_CONFIG:
4072 pm8001_dbg(pm8001_ha, MSG,
4073 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc);
4074 mpi_set_controller_config_resp(pm8001_ha, piomb);
4076 case OPC_OUB_GET_CONTROLLER_CONFIG:
4077 pm8001_dbg(pm8001_ha, MSG,
4078 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc);
4079 mpi_get_controller_config_resp(pm8001_ha, piomb);
4081 case OPC_OUB_GET_PHY_PROFILE:
4082 pm8001_dbg(pm8001_ha, MSG,
4083 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc);
4084 mpi_get_phy_profile_resp(pm8001_ha, piomb);
4086 case OPC_OUB_FLASH_OP_EXT:
4087 pm8001_dbg(pm8001_ha, MSG,
4088 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc);
4089 mpi_flash_op_ext_resp(pm8001_ha, piomb);
4091 case OPC_OUB_SET_PHY_PROFILE:
4092 pm8001_dbg(pm8001_ha, MSG,
4093 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc);
4094 mpi_set_phy_profile_resp(pm8001_ha, piomb);
4096 case OPC_OUB_KEK_MANAGEMENT_RESP:
4097 pm8001_dbg(pm8001_ha, MSG,
4098 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc);
4099 mpi_kek_management_resp(pm8001_ha, piomb);
4101 case OPC_OUB_DEK_MANAGEMENT_RESP:
4102 pm8001_dbg(pm8001_ha, MSG,
4103 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc);
4104 mpi_dek_management_resp(pm8001_ha, piomb);
4106 case OPC_OUB_SSP_COALESCED_COMP_RESP:
4107 pm8001_dbg(pm8001_ha, MSG,
4108 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc);
4109 ssp_coalesced_comp_resp(pm8001_ha, piomb);
4112 pm8001_dbg(pm8001_ha, DEVIO,
4113 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc);
4118 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
4120 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_0: 0x%x\n",
4121 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0));
4122 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_1:0x%x\n",
4123 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1));
4124 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_2: 0x%x\n",
4125 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2));
4126 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_3: 0x%x\n",
4127 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3));
4128 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
4129 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0));
4130 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
4131 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1));
4132 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
4133 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2));
4134 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
4135 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3));
4136 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
4137 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4));
4138 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
4139 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5));
4140 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
4141 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6));
4142 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
4143 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7));
4146 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4148 struct outbound_queue_table *circularQ;
4151 u32 ret = MPI_IO_STATUS_FAIL;
4154 if (vec == (pm8001_ha->max_q_num - 1)) {
4155 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
4156 if ((regval & SCRATCH_PAD_MIPSALL_READY) !=
4157 SCRATCH_PAD_MIPSALL_READY) {
4158 pm8001_ha->controller_fatal_error = true;
4159 pm8001_dbg(pm8001_ha, FAIL,
4160 "Firmware Fatal error! Regval:0x%x\n",
4162 pm8001_handle_event(pm8001_ha, NULL, IO_FATAL_ERROR);
4163 print_scratchpad_registers(pm8001_ha);
4167 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4168 spin_lock_irqsave(&circularQ->oq_lock, circularQ->lock_flags);
4170 /* spurious interrupt during setup if kexec-ing and
4171 * driver doing a doorbell access w/ the pre-kexec oq
4174 if (!circularQ->pi_virt)
4176 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4177 if (MPI_IO_STATUS_SUCCESS == ret) {
4178 /* process the outbound message */
4179 process_one_iomb(pm8001_ha, circularQ,
4180 (void *)(pMsg1 - 4));
4181 /* free the message from the outbound circular buffer */
4182 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4185 if (MPI_IO_STATUS_BUSY == ret) {
4186 /* Update the producer index from SPC */
4187 circularQ->producer_index =
4188 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4189 if (le32_to_cpu(circularQ->producer_index) ==
4190 circularQ->consumer_idx)
4195 spin_unlock_irqrestore(&circularQ->oq_lock, circularQ->lock_flags);
4199 /* DMA_... to our direction translation. */
4200 static const u8 data_dir_flags[] = {
4201 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
4202 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */
4203 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */
4204 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */
4207 static void build_smp_cmd(u32 deviceID, __le32 hTag,
4208 struct smp_req *psmp_cmd, int mode, int length)
4210 psmp_cmd->tag = hTag;
4211 psmp_cmd->device_id = cpu_to_le32(deviceID);
4212 if (mode == SMP_DIRECT) {
4213 length = length - 4; /* subtract crc */
4214 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
4216 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4221 * pm80xx_chip_smp_req - send an SMP task to FW
4222 * @pm8001_ha: our hba card information.
4223 * @ccb: the ccb information this request used.
4225 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4226 struct pm8001_ccb_info *ccb)
4229 struct sas_task *task = ccb->task;
4230 struct domain_device *dev = task->dev;
4231 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4232 struct scatterlist *sg_req, *sg_resp, *smp_req;
4233 u32 req_len, resp_len;
4234 struct smp_req smp_cmd;
4236 struct inbound_queue_table *circularQ;
4241 memset(&smp_cmd, 0, sizeof(smp_cmd));
4243 * DMA-map SMP request, response buffers
4245 sg_req = &task->smp_task.smp_req;
4246 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4249 req_len = sg_dma_len(sg_req);
4251 sg_resp = &task->smp_task.smp_resp;
4252 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4257 resp_len = sg_dma_len(sg_resp);
4258 /* must be in dwords */
4259 if ((req_len & 0x3) || (resp_len & 0x3)) {
4264 opc = OPC_INB_SMP_REQUEST;
4265 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4266 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4268 length = sg_req->length;
4269 pm8001_dbg(pm8001_ha, IO, "SMP Frame Length %d\n", sg_req->length);
4271 pm8001_ha->smp_exp_mode = SMP_DIRECT;
4273 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
4276 smp_req = &task->smp_task.smp_req;
4277 to = kmap_atomic(sg_page(smp_req));
4278 payload = to + smp_req->offset;
4280 /* INDIRECT MODE command settings. Use DMA */
4281 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
4282 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST INDIRECT MODE\n");
4283 /* for SPCv indirect mode. Place the top 4 bytes of
4284 * SMP Request header here. */
4285 for (i = 0; i < 4; i++)
4286 smp_cmd.smp_req16[i] = *(payload + i);
4287 /* exclude top 4 bytes for SMP req header */
4288 smp_cmd.long_smp_req.long_req_addr =
4289 cpu_to_le64((u64)sg_dma_address
4290 (&task->smp_task.smp_req) + 4);
4291 /* exclude 4 bytes for SMP req header and CRC */
4292 smp_cmd.long_smp_req.long_req_size =
4293 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
4294 smp_cmd.long_smp_req.long_resp_addr =
4295 cpu_to_le64((u64)sg_dma_address
4296 (&task->smp_task.smp_resp));
4297 smp_cmd.long_smp_req.long_resp_size =
4298 cpu_to_le32((u32)sg_dma_len
4299 (&task->smp_task.smp_resp)-4);
4300 } else { /* DIRECT MODE */
4301 smp_cmd.long_smp_req.long_req_addr =
4302 cpu_to_le64((u64)sg_dma_address
4303 (&task->smp_task.smp_req));
4304 smp_cmd.long_smp_req.long_req_size =
4305 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4306 smp_cmd.long_smp_req.long_resp_addr =
4307 cpu_to_le64((u64)sg_dma_address
4308 (&task->smp_task.smp_resp));
4309 smp_cmd.long_smp_req.long_resp_size =
4311 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4313 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
4314 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST DIRECT MODE\n");
4315 for (i = 0; i < length; i++)
4317 smp_cmd.smp_req16[i] = *(payload + i);
4318 pm8001_dbg(pm8001_ha, IO,
4319 "Byte[%d]:%x (DMA data:%x)\n",
4320 i, smp_cmd.smp_req16[i],
4323 smp_cmd.smp_req[i] = *(payload + i);
4324 pm8001_dbg(pm8001_ha, IO,
4325 "Byte[%d]:%x (DMA data:%x)\n",
4326 i, smp_cmd.smp_req[i],
4331 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
4332 &smp_cmd, pm8001_ha->smp_exp_mode, length);
4333 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &smp_cmd,
4334 sizeof(smp_cmd), 0);
4340 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4343 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4348 static int check_enc_sas_cmd(struct sas_task *task)
4350 u8 cmd = task->ssp_task.cmd->cmnd[0];
4352 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
4358 static int check_enc_sat_cmd(struct sas_task *task)
4361 switch (task->ata_task.fis.command) {
4362 case ATA_CMD_FPDMA_READ:
4363 case ATA_CMD_READ_EXT:
4365 case ATA_CMD_FPDMA_WRITE:
4366 case ATA_CMD_WRITE_EXT:
4368 case ATA_CMD_PIO_READ:
4369 case ATA_CMD_PIO_READ_EXT:
4370 case ATA_CMD_PIO_WRITE:
4371 case ATA_CMD_PIO_WRITE_EXT:
4382 * pm80xx_chip_ssp_io_req - send an SSP task to FW
4383 * @pm8001_ha: our hba card information.
4384 * @ccb: the ccb information this request used.
4386 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4387 struct pm8001_ccb_info *ccb)
4389 struct sas_task *task = ccb->task;
4390 struct domain_device *dev = task->dev;
4391 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4392 struct ssp_ini_io_start_req ssp_cmd;
4393 u32 tag = ccb->ccb_tag;
4395 u64 phys_addr, start_addr, end_addr;
4396 u32 end_addr_high, end_addr_low;
4397 struct inbound_queue_table *circularQ;
4398 u32 q_index, cpu_id;
4399 u32 opc = OPC_INB_SSPINIIOSTART;
4400 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4401 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4402 /* data address domain added for spcv; set to 0 by host,
4403 * used internally by controller
4404 * 0 for SAS 1.1 and SAS 2.0 compatible TLR
4406 ssp_cmd.dad_dir_m_tlr =
4407 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
4408 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4409 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4410 ssp_cmd.tag = cpu_to_le32(tag);
4411 if (task->ssp_task.enable_first_burst)
4412 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4413 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4414 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4415 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4416 task->ssp_task.cmd->cmd_len);
4417 cpu_id = smp_processor_id();
4418 q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num);
4419 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4421 /* Check if encryption is set */
4422 if (pm8001_ha->chip->encrypt &&
4423 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
4424 pm8001_dbg(pm8001_ha, IO,
4425 "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
4426 task->ssp_task.cmd->cmnd[0]);
4427 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
4428 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
4429 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
4430 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
4432 /* fill in PRD (scatter/gather) table, if any */
4433 if (task->num_scatter > 1) {
4434 pm8001_chip_make_sg(task->scatter,
4435 ccb->n_elem, ccb->buf_prd);
4436 phys_addr = ccb->ccb_dma_handle;
4437 ssp_cmd.enc_addr_low =
4438 cpu_to_le32(lower_32_bits(phys_addr));
4439 ssp_cmd.enc_addr_high =
4440 cpu_to_le32(upper_32_bits(phys_addr));
4441 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4442 } else if (task->num_scatter == 1) {
4443 u64 dma_addr = sg_dma_address(task->scatter);
4444 ssp_cmd.enc_addr_low =
4445 cpu_to_le32(lower_32_bits(dma_addr));
4446 ssp_cmd.enc_addr_high =
4447 cpu_to_le32(upper_32_bits(dma_addr));
4448 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4449 ssp_cmd.enc_esgl = 0;
4450 /* Check 4G Boundary */
4451 start_addr = cpu_to_le64(dma_addr);
4452 end_addr = (start_addr + ssp_cmd.enc_len) - 1;
4453 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4454 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4455 if (end_addr_high != ssp_cmd.enc_addr_high) {
4456 pm8001_dbg(pm8001_ha, FAIL,
4457 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4458 start_addr, ssp_cmd.enc_len,
4459 end_addr_high, end_addr_low);
4460 pm8001_chip_make_sg(task->scatter, 1,
4462 phys_addr = ccb->ccb_dma_handle;
4463 ssp_cmd.enc_addr_low =
4464 cpu_to_le32(lower_32_bits(phys_addr));
4465 ssp_cmd.enc_addr_high =
4466 cpu_to_le32(upper_32_bits(phys_addr));
4467 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4469 } else if (task->num_scatter == 0) {
4470 ssp_cmd.enc_addr_low = 0;
4471 ssp_cmd.enc_addr_high = 0;
4472 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4473 ssp_cmd.enc_esgl = 0;
4475 /* XTS mode. All other fields are 0 */
4476 ssp_cmd.key_cmode = 0x6 << 4;
4477 /* set tweak values. Should be the start lba */
4478 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4479 (task->ssp_task.cmd->cmnd[3] << 16) |
4480 (task->ssp_task.cmd->cmnd[4] << 8) |
4481 (task->ssp_task.cmd->cmnd[5]));
4483 pm8001_dbg(pm8001_ha, IO,
4484 "Sending Normal SAS command 0x%x inb q %x\n",
4485 task->ssp_task.cmd->cmnd[0], q_index);
4486 /* fill in PRD (scatter/gather) table, if any */
4487 if (task->num_scatter > 1) {
4488 pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4490 phys_addr = ccb->ccb_dma_handle;
4492 cpu_to_le32(lower_32_bits(phys_addr));
4494 cpu_to_le32(upper_32_bits(phys_addr));
4495 ssp_cmd.esgl = cpu_to_le32(1<<31);
4496 } else if (task->num_scatter == 1) {
4497 u64 dma_addr = sg_dma_address(task->scatter);
4498 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4500 cpu_to_le32(upper_32_bits(dma_addr));
4501 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4503 /* Check 4G Boundary */
4504 start_addr = cpu_to_le64(dma_addr);
4505 end_addr = (start_addr + ssp_cmd.len) - 1;
4506 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4507 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4508 if (end_addr_high != ssp_cmd.addr_high) {
4509 pm8001_dbg(pm8001_ha, FAIL,
4510 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4511 start_addr, ssp_cmd.len,
4512 end_addr_high, end_addr_low);
4513 pm8001_chip_make_sg(task->scatter, 1,
4515 phys_addr = ccb->ccb_dma_handle;
4517 cpu_to_le32(lower_32_bits(phys_addr));
4519 cpu_to_le32(upper_32_bits(phys_addr));
4520 ssp_cmd.esgl = cpu_to_le32(1<<31);
4522 } else if (task->num_scatter == 0) {
4523 ssp_cmd.addr_low = 0;
4524 ssp_cmd.addr_high = 0;
4525 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4529 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4530 &ssp_cmd, sizeof(ssp_cmd), q_index);
4534 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4535 struct pm8001_ccb_info *ccb)
4537 struct sas_task *task = ccb->task;
4538 struct domain_device *dev = task->dev;
4539 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4540 struct ata_queued_cmd *qc = task->uldd_task;
4541 u32 tag = ccb->ccb_tag;
4543 u32 q_index, cpu_id;
4544 struct sata_start_req sata_cmd;
4545 u32 hdr_tag, ncg_tag = 0;
4546 u64 phys_addr, start_addr, end_addr;
4547 u32 end_addr_high, end_addr_low;
4550 struct inbound_queue_table *circularQ;
4551 unsigned long flags;
4552 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4553 memset(&sata_cmd, 0, sizeof(sata_cmd));
4554 cpu_id = smp_processor_id();
4555 q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num);
4556 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4558 if (task->data_dir == DMA_NONE) {
4559 ATAP = 0x04; /* no data*/
4560 pm8001_dbg(pm8001_ha, IO, "no data\n");
4561 } else if (likely(!task->ata_task.device_control_reg_update)) {
4562 if (task->ata_task.dma_xfer) {
4563 ATAP = 0x06; /* DMA */
4564 pm8001_dbg(pm8001_ha, IO, "DMA\n");
4566 ATAP = 0x05; /* PIO*/
4567 pm8001_dbg(pm8001_ha, IO, "PIO\n");
4569 if (task->ata_task.use_ncq &&
4570 dev->sata_dev.class != ATA_DEV_ATAPI) {
4571 ATAP = 0x07; /* FPDMA */
4572 pm8001_dbg(pm8001_ha, IO, "FPDMA\n");
4575 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4576 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4579 dir = data_dir_flags[task->data_dir] << 8;
4580 sata_cmd.tag = cpu_to_le32(tag);
4581 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4582 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4584 sata_cmd.sata_fis = task->ata_task.fis;
4585 if (likely(!task->ata_task.device_control_reg_update))
4586 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4587 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4589 /* Check if encryption is set */
4590 if (pm8001_ha->chip->encrypt &&
4591 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4592 pm8001_dbg(pm8001_ha, IO,
4593 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4594 sata_cmd.sata_fis.command);
4595 opc = OPC_INB_SATA_DIF_ENC_IO;
4597 /* set encryption bit */
4598 sata_cmd.ncqtag_atap_dir_m_dad =
4599 cpu_to_le32(((ncg_tag & 0xff)<<16)|
4600 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4601 /* dad (bit 0-1) is 0 */
4602 /* fill in PRD (scatter/gather) table, if any */
4603 if (task->num_scatter > 1) {
4604 pm8001_chip_make_sg(task->scatter,
4605 ccb->n_elem, ccb->buf_prd);
4606 phys_addr = ccb->ccb_dma_handle;
4607 sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
4608 sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
4609 sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4610 } else if (task->num_scatter == 1) {
4611 u64 dma_addr = sg_dma_address(task->scatter);
4612 sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
4613 sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
4614 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4615 sata_cmd.enc_esgl = 0;
4616 /* Check 4G Boundary */
4617 start_addr = cpu_to_le64(dma_addr);
4618 end_addr = (start_addr + sata_cmd.enc_len) - 1;
4619 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4620 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4621 if (end_addr_high != sata_cmd.enc_addr_high) {
4622 pm8001_dbg(pm8001_ha, FAIL,
4623 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4624 start_addr, sata_cmd.enc_len,
4625 end_addr_high, end_addr_low);
4626 pm8001_chip_make_sg(task->scatter, 1,
4628 phys_addr = ccb->ccb_dma_handle;
4629 sata_cmd.enc_addr_low =
4630 lower_32_bits(phys_addr);
4631 sata_cmd.enc_addr_high =
4632 upper_32_bits(phys_addr);
4634 cpu_to_le32(1 << 31);
4636 } else if (task->num_scatter == 0) {
4637 sata_cmd.enc_addr_low = 0;
4638 sata_cmd.enc_addr_high = 0;
4639 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4640 sata_cmd.enc_esgl = 0;
4642 /* XTS mode. All other fields are 0 */
4643 sata_cmd.key_index_mode = 0x6 << 4;
4644 /* set tweak values. Should be the start lba */
4646 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4647 (sata_cmd.sata_fis.lbah << 16) |
4648 (sata_cmd.sata_fis.lbam << 8) |
4649 (sata_cmd.sata_fis.lbal));
4651 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4652 (sata_cmd.sata_fis.lbam_exp));
4654 pm8001_dbg(pm8001_ha, IO,
4655 "Sending Normal SATA command 0x%x inb %x\n",
4656 sata_cmd.sata_fis.command, q_index);
4657 /* dad (bit 0-1) is 0 */
4658 sata_cmd.ncqtag_atap_dir_m_dad =
4659 cpu_to_le32(((ncg_tag & 0xff)<<16) |
4660 ((ATAP & 0x3f) << 10) | dir);
4662 /* fill in PRD (scatter/gather) table, if any */
4663 if (task->num_scatter > 1) {
4664 pm8001_chip_make_sg(task->scatter,
4665 ccb->n_elem, ccb->buf_prd);
4666 phys_addr = ccb->ccb_dma_handle;
4667 sata_cmd.addr_low = lower_32_bits(phys_addr);
4668 sata_cmd.addr_high = upper_32_bits(phys_addr);
4669 sata_cmd.esgl = cpu_to_le32(1 << 31);
4670 } else if (task->num_scatter == 1) {
4671 u64 dma_addr = sg_dma_address(task->scatter);
4672 sata_cmd.addr_low = lower_32_bits(dma_addr);
4673 sata_cmd.addr_high = upper_32_bits(dma_addr);
4674 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4676 /* Check 4G Boundary */
4677 start_addr = cpu_to_le64(dma_addr);
4678 end_addr = (start_addr + sata_cmd.len) - 1;
4679 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4680 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4681 if (end_addr_high != sata_cmd.addr_high) {
4682 pm8001_dbg(pm8001_ha, FAIL,
4683 "The sg list address start_addr=0x%016llx data_len=0x%xend_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4684 start_addr, sata_cmd.len,
4685 end_addr_high, end_addr_low);
4686 pm8001_chip_make_sg(task->scatter, 1,
4688 phys_addr = ccb->ccb_dma_handle;
4690 lower_32_bits(phys_addr);
4691 sata_cmd.addr_high =
4692 upper_32_bits(phys_addr);
4693 sata_cmd.esgl = cpu_to_le32(1 << 31);
4695 } else if (task->num_scatter == 0) {
4696 sata_cmd.addr_low = 0;
4697 sata_cmd.addr_high = 0;
4698 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4702 sata_cmd.atapi_scsi_cdb[0] =
4703 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4704 (task->ata_task.atapi_packet[1] << 8) |
4705 (task->ata_task.atapi_packet[2] << 16) |
4706 (task->ata_task.atapi_packet[3] << 24)));
4707 sata_cmd.atapi_scsi_cdb[1] =
4708 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4709 (task->ata_task.atapi_packet[5] << 8) |
4710 (task->ata_task.atapi_packet[6] << 16) |
4711 (task->ata_task.atapi_packet[7] << 24)));
4712 sata_cmd.atapi_scsi_cdb[2] =
4713 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4714 (task->ata_task.atapi_packet[9] << 8) |
4715 (task->ata_task.atapi_packet[10] << 16) |
4716 (task->ata_task.atapi_packet[11] << 24)));
4717 sata_cmd.atapi_scsi_cdb[3] =
4718 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4719 (task->ata_task.atapi_packet[13] << 8) |
4720 (task->ata_task.atapi_packet[14] << 16) |
4721 (task->ata_task.atapi_packet[15] << 24)));
4724 /* Check for read log for failed drive and return */
4725 if (sata_cmd.sata_fis.command == 0x2f) {
4726 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4727 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4728 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4729 struct task_status_struct *ts;
4731 pm8001_ha_dev->id &= 0xDFFFFFFF;
4732 ts = &task->task_status;
4734 spin_lock_irqsave(&task->task_state_lock, flags);
4735 ts->resp = SAS_TASK_COMPLETE;
4736 ts->stat = SAS_SAM_STAT_GOOD;
4737 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4738 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4739 task->task_state_flags |= SAS_TASK_STATE_DONE;
4740 if (unlikely((task->task_state_flags &
4741 SAS_TASK_STATE_ABORTED))) {
4742 spin_unlock_irqrestore(&task->task_state_lock,
4744 pm8001_dbg(pm8001_ha, FAIL,
4745 "task 0x%p resp 0x%x stat 0x%x but aborted by upper layer\n",
4748 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4751 spin_unlock_irqrestore(&task->task_state_lock,
4753 pm8001_ccb_task_free_done(pm8001_ha, task,
4755 atomic_dec(&pm8001_ha_dev->running_req);
4760 trace_pm80xx_request_issue(pm8001_ha->id,
4761 ccb->device ? ccb->device->attached_phy : PM8001_MAX_PHYS,
4763 qc ? qc->tf.command : 0, // ata opcode
4764 ccb->device ? atomic_read(&ccb->device->running_req) : 0);
4765 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4766 &sata_cmd, sizeof(sata_cmd), q_index);
4771 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4772 * @pm8001_ha: our hba card information.
4773 * @phy_id: the phy id which we wanted to start up.
4776 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4778 struct phy_start_req payload;
4779 struct inbound_queue_table *circularQ;
4782 u32 opcode = OPC_INB_PHYSTART;
4783 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4784 memset(&payload, 0, sizeof(payload));
4785 payload.tag = cpu_to_le32(tag);
4787 pm8001_dbg(pm8001_ha, INIT, "PHY START REQ for phy_id %d\n", phy_id);
4789 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4790 LINKMODE_AUTO | pm8001_ha->link_rate | phy_id);
4791 /* SSC Disable and SAS Analog ST configuration */
4793 payload.ase_sh_lm_slr_phyid =
4794 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4795 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4797 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4800 payload.sas_identify.dev_type = SAS_END_DEVICE;
4801 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4802 memcpy(payload.sas_identify.sas_addr,
4803 &pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4804 payload.sas_identify.phy_id = phy_id;
4805 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4806 sizeof(payload), 0);
4811 * pm80xx_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4812 * @pm8001_ha: our hba card information.
4813 * @phy_id: the phy id which we wanted to start up.
4815 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4818 struct phy_stop_req payload;
4819 struct inbound_queue_table *circularQ;
4822 u32 opcode = OPC_INB_PHYSTOP;
4823 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4824 memset(&payload, 0, sizeof(payload));
4825 payload.tag = cpu_to_le32(tag);
4826 payload.phy_id = cpu_to_le32(phy_id);
4827 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4828 sizeof(payload), 0);
4833 * see comments on pm8001_mpi_reg_resp.
4835 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4836 struct pm8001_device *pm8001_dev, u32 flag)
4838 struct reg_dev_req payload;
4840 u32 stp_sspsmp_sata = 0x4;
4841 struct inbound_queue_table *circularQ;
4842 u32 linkrate, phy_id;
4843 int rc, tag = 0xdeadbeef;
4844 struct pm8001_ccb_info *ccb;
4846 u16 firstBurstSize = 0;
4848 struct domain_device *dev = pm8001_dev->sas_device;
4849 struct domain_device *parent_dev = dev->parent;
4850 struct pm8001_port *port = dev->port->lldd_port;
4851 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4853 memset(&payload, 0, sizeof(payload));
4854 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4857 ccb = &pm8001_ha->ccb_info[tag];
4858 ccb->device = pm8001_dev;
4860 payload.tag = cpu_to_le32(tag);
4863 stp_sspsmp_sata = 0x02; /*direct attached sata */
4865 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4866 stp_sspsmp_sata = 0x00; /* stp*/
4867 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4868 dev_is_expander(pm8001_dev->dev_type))
4869 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4871 if (parent_dev && dev_is_expander(parent_dev->dev_type))
4872 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4874 phy_id = pm8001_dev->attached_phy;
4876 opc = OPC_INB_REG_DEV;
4878 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4879 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4881 payload.phyid_portid =
4882 cpu_to_le32(((port->port_id) & 0xFF) |
4883 ((phy_id & 0xFF) << 8));
4885 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4886 ((linkrate & 0x0F) << 24) |
4887 ((stp_sspsmp_sata & 0x03) << 28));
4888 payload.firstburstsize_ITNexustimeout =
4889 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4891 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4894 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4895 sizeof(payload), 0);
4897 pm8001_tag_free(pm8001_ha, tag);
4903 * pm80xx_chip_phy_ctl_req - support the local phy operation
4904 * @pm8001_ha: our hba card information.
4905 * @phyId: the phy id which we wanted to operate
4906 * @phy_op: phy operation to request
4908 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4909 u32 phyId, u32 phy_op)
4913 struct local_phy_ctl_req payload;
4914 struct inbound_queue_table *circularQ;
4915 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4916 memset(&payload, 0, sizeof(payload));
4917 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4920 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4921 payload.tag = cpu_to_le32(tag);
4922 payload.phyop_phyid =
4923 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4924 return pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4925 sizeof(payload), 0);
4928 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4930 #ifdef PM8001_USE_MSIX
4935 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4943 * pm80xx_chip_isr - PM8001 isr handler.
4944 * @pm8001_ha: our hba card information.
4948 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4950 pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4951 pm8001_dbg(pm8001_ha, DEVIO,
4952 "irq vec %d, ODMR:0x%x\n",
4953 vec, pm8001_cr32(pm8001_ha, 0, 0x30));
4954 process_oq(pm8001_ha, vec);
4955 pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4959 static void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4960 u32 operation, u32 phyid,
4961 u32 length, u32 *buf)
4965 struct set_phy_profile_req payload;
4966 struct inbound_queue_table *circularQ;
4967 u32 opc = OPC_INB_SET_PHY_PROFILE;
4969 memset(&payload, 0, sizeof(payload));
4970 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4972 pm8001_dbg(pm8001_ha, FAIL, "Invalid tag\n");
4973 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4974 payload.tag = cpu_to_le32(tag);
4975 payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF));
4976 pm8001_dbg(pm8001_ha, INIT,
4977 " phy profile command for phy %x ,length is %d\n",
4978 payload.ppc_phyid, length);
4979 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4980 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i));
4983 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4984 sizeof(payload), 0);
4986 pm8001_tag_free(pm8001_ha, tag);
4989 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4990 u32 length, u8 *buf)
4994 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4995 mpi_set_phy_profile_req(pm8001_ha,
4996 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
4997 length = length + PHY_DWORD_LENGTH;
4999 pm8001_dbg(pm8001_ha, INIT, "phy settings completed\n");
5002 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
5003 u32 phy, u32 length, u32 *buf)
5007 struct set_phy_profile_req payload;
5008 struct inbound_queue_table *circularQ;
5010 memset(&payload, 0, sizeof(payload));
5012 rc = pm8001_tag_alloc(pm8001_ha, &tag);
5014 pm8001_dbg(pm8001_ha, INIT, "Invalid tag\n");
5016 circularQ = &pm8001_ha->inbnd_q_tbl[0];
5017 opc = OPC_INB_SET_PHY_PROFILE;
5019 payload.tag = cpu_to_le32(tag);
5020 payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
5023 for (i = 0; i < length; i++)
5024 payload.reserved[i] = cpu_to_le32(*(buf + i));
5026 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
5027 sizeof(payload), 0);
5029 pm8001_tag_free(pm8001_ha, tag);
5031 pm8001_dbg(pm8001_ha, INIT, "PHY %d settings applied\n", phy);
5033 const struct pm8001_dispatch pm8001_80xx_dispatch = {
5035 .chip_init = pm80xx_chip_init,
5036 .chip_soft_rst = pm80xx_chip_soft_rst,
5037 .chip_rst = pm80xx_hw_chip_rst,
5038 .chip_iounmap = pm8001_chip_iounmap,
5039 .isr = pm80xx_chip_isr,
5040 .is_our_interrupt = pm80xx_chip_is_our_interrupt,
5041 .isr_process_oq = process_oq,
5042 .interrupt_enable = pm80xx_chip_interrupt_enable,
5043 .interrupt_disable = pm80xx_chip_interrupt_disable,
5044 .make_prd = pm8001_chip_make_sg,
5045 .smp_req = pm80xx_chip_smp_req,
5046 .ssp_io_req = pm80xx_chip_ssp_io_req,
5047 .sata_req = pm80xx_chip_sata_req,
5048 .phy_start_req = pm80xx_chip_phy_start_req,
5049 .phy_stop_req = pm80xx_chip_phy_stop_req,
5050 .reg_dev_req = pm80xx_chip_reg_dev_req,
5051 .dereg_dev_req = pm8001_chip_dereg_dev_req,
5052 .phy_ctl_req = pm80xx_chip_phy_ctl_req,
5053 .task_abort = pm8001_chip_abort_task,
5054 .ssp_tm_req = pm8001_chip_ssp_tm_req,
5055 .get_nvmd_req = pm8001_chip_get_nvmd_req,
5056 .set_nvmd_req = pm8001_chip_set_nvmd_req,
5057 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
5058 .set_dev_state_req = pm8001_chip_set_dev_state_req,
5059 .fatal_errors = pm80xx_fatal_errors,
5060 .hw_event_ack_req = pm80xx_hw_event_ack_req,