drivers/scsi/pm8001/pm80xx_hwi.c

   1 /*
   2  * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  * notice, this list of conditions, and the following disclaimer,
  12  * without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  * substantially similar to the "NO WARRANTY" disclaimer below
  15  * ("Disclaimer") and any redistribution must be conditioned upon
  16  * including a substantially similar Disclaimer requirement for further
  17  * binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  * of any contributors may be used to endorse or promote products derived
  20  * from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include <linux/slab.h>
  41  #include "pm8001_sas.h"
  42  #include "pm80xx_hwi.h"
  43  #include "pm8001_chips.h"
  44  #include "pm8001_ctl.h"
  45
  46 #define SMP_DIRECT 1
  47 #define SMP_INDIRECT 2
  48
  49
  50 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
  51 {
  52         u32 reg_val;
  53         unsigned long start;
  54         pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
  55         /* confirm the setting is written */
  56         start = jiffies + HZ; /* 1 sec */
  57         do {
  58                 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
  59         } while ((reg_val != shift_value) && time_before(jiffies, start));
  60         if (reg_val != shift_value) {
  61                 PM8001_FAIL_DBG(pm8001_ha,
  62                         pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
  63                         " = 0x%x\n", reg_val));
  64                 return -1;
  65         }
  66         return 0;
  67 }
  68
  69 static void pm80xx_pci_mem_copy(struct pm8001_hba_info  *pm8001_ha, u32 soffset,
  70                                 const void *destination,
  71                                 u32 dw_count, u32 bus_base_number)
  72 {
  73         u32 index, value, offset;
  74         u32 *destination1;
  75         destination1 = (u32 *)destination;
  76
  77         for (index = 0; index < dw_count; index += 4, destination1++) {
  78                 offset = (soffset + index);
  79                 if (offset < (64 * 1024)) {
  80                         value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
  81                         *destination1 =  cpu_to_le32(value);
  82                 }
  83         }
  84         return;
  85 }
  86
  87 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
  88         struct device_attribute *attr, char *buf)
  89 {
  90         struct Scsi_Host *shost = class_to_shost(cdev);
  91         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  92         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
  93         void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
  94         u32 accum_len , reg_val, index, *temp;
  95         u32 status = 1;
  96         unsigned long start;
  97         u8 *direct_data;
  98         char *fatal_error_data = buf;
  99         u32 length_to_read;
 100         u32 offset;
 101
 102         pm8001_ha->forensic_info.data_buf.direct_data = buf;
 103         if (pm8001_ha->chip_id == chip_8001) {
 104                 pm8001_ha->forensic_info.data_buf.direct_data +=
 105                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 106                         "Not supported for SPC controller");
 107                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 108                         (char *)buf;
 109         }
 110         /* initialize variables for very first call from host application */
 111         if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
 112                 PM8001_IO_DBG(pm8001_ha,
 113                 pm8001_printk("forensic_info TYPE_NON_FATAL..............\n"));
 114                 direct_data = (u8 *)fatal_error_data;
 115                 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
 116                 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
 117                 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
 118                 pm8001_ha->forensic_info.data_buf.read_len = 0;
 119                 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
 120
 121                 /* Write signature to fatal dump table */
 122                 pm8001_mw32(fatal_table_address,
 123                                 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd);
 124
 125                 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
 126                 PM8001_IO_DBG(pm8001_ha,
 127                         pm8001_printk("ossaHwCB: status1 %d\n", status));
 128                 PM8001_IO_DBG(pm8001_ha,
 129                         pm8001_printk("ossaHwCB: read_len 0x%x\n",
 130                         pm8001_ha->forensic_info.data_buf.read_len));
 131                 PM8001_IO_DBG(pm8001_ha,
 132                         pm8001_printk("ossaHwCB: direct_len 0x%x\n",
 133                         pm8001_ha->forensic_info.data_buf.direct_len));
 134                 PM8001_IO_DBG(pm8001_ha,
 135                         pm8001_printk("ossaHwCB: direct_offset 0x%x\n",
 136                         pm8001_ha->forensic_info.data_buf.direct_offset));
 137         }
 138         if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
 139                 /* start to get data */
 140                 /* Program the MEMBASE II Shifting Register with 0x00.*/
 141                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 142                                 pm8001_ha->fatal_forensic_shift_offset);
 143                 pm8001_ha->forensic_last_offset = 0;
 144                 pm8001_ha->forensic_fatal_step = 0;
 145                 pm8001_ha->fatal_bar_loc = 0;
 146         }
 147
 148         /* Read until accum_len is retrived */
 149         accum_len = pm8001_mr32(fatal_table_address,
 150                                 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
 151         /* Determine length of data between previously stored transfer length
 152          * and current accumulated transfer length
 153          */
 154         length_to_read =
 155                 accum_len - pm8001_ha->forensic_preserved_accumulated_transfer;
 156         PM8001_IO_DBG(pm8001_ha,
 157                 pm8001_printk("get_fatal_spcv: accum_len 0x%x\n", accum_len));
 158         PM8001_IO_DBG(pm8001_ha,
 159                 pm8001_printk("get_fatal_spcv: length_to_read 0x%x\n",
 160                 length_to_read));
 161         PM8001_IO_DBG(pm8001_ha,
 162                 pm8001_printk("get_fatal_spcv: last_offset 0x%x\n",
 163                 pm8001_ha->forensic_last_offset));
 164         PM8001_IO_DBG(pm8001_ha,
 165                 pm8001_printk("get_fatal_spcv: read_len 0x%x\n",
 166                 pm8001_ha->forensic_info.data_buf.read_len));
 167         PM8001_IO_DBG(pm8001_ha,
 168                 pm8001_printk("get_fatal_spcv:: direct_len 0x%x\n",
 169                 pm8001_ha->forensic_info.data_buf.direct_len));
 170         PM8001_IO_DBG(pm8001_ha,
 171                 pm8001_printk("get_fatal_spcv:: direct_offset 0x%x\n",
 172                 pm8001_ha->forensic_info.data_buf.direct_offset));
 173
 174         /* If accumulated length failed to read correctly fail the attempt.*/
 175         if (accum_len == 0xFFFFFFFF) {
 176                 PM8001_IO_DBG(pm8001_ha,
 177                         pm8001_printk("Possible PCI issue 0x%x not expected\n",
 178                         accum_len));
 179                 return status;
 180         }
 181         /* If accumulated length is zero fail the attempt */
 182         if (accum_len == 0) {
 183                 pm8001_ha->forensic_info.data_buf.direct_data +=
 184                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 185                         "%08x ", 0xFFFFFFFF);
 186                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 187                         (char *)buf;
 188         }
 189         /* Accumulated length is good so start capturing the first data */
 190         temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
 191         if (pm8001_ha->forensic_fatal_step == 0) {
 192 moreData:
 193                 /* If data to read is less than SYSFS_OFFSET then reduce the
 194                  * length of dataLen
 195                  */
 196                 if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET
 197                                 > length_to_read) {
 198                         pm8001_ha->forensic_info.data_buf.direct_len =
 199                                 length_to_read -
 200                                 pm8001_ha->forensic_last_offset;
 201                 } else {
 202                         pm8001_ha->forensic_info.data_buf.direct_len =
 203                                 SYSFS_OFFSET;
 204                 }
 205                 if (pm8001_ha->forensic_info.data_buf.direct_data) {
 206                         /* Data is in bar, copy to host memory */
 207                         pm80xx_pci_mem_copy(pm8001_ha,
 208                         pm8001_ha->fatal_bar_loc,
 209                         pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
 210                         pm8001_ha->forensic_info.data_buf.direct_len, 1);
 211                 }
 212                 pm8001_ha->fatal_bar_loc +=
 213                         pm8001_ha->forensic_info.data_buf.direct_len;
 214                 pm8001_ha->forensic_info.data_buf.direct_offset +=
 215                         pm8001_ha->forensic_info.data_buf.direct_len;
 216                 pm8001_ha->forensic_last_offset +=
 217                         pm8001_ha->forensic_info.data_buf.direct_len;
 218                 pm8001_ha->forensic_info.data_buf.read_len =
 219                         pm8001_ha->forensic_info.data_buf.direct_len;
 220
 221                 if (pm8001_ha->forensic_last_offset  >= length_to_read) {
 222                         pm8001_ha->forensic_info.data_buf.direct_data +=
 223                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 224                                 "%08x ", 3);
 225                         for (index = 0; index <
 226                                 (pm8001_ha->forensic_info.data_buf.direct_len
 227                                  / 4); index++) {
 228                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 229                                 sprintf(
 230                                 pm8001_ha->forensic_info.data_buf.direct_data,
 231                                 "%08x ", *(temp + index));
 232                         }
 233
 234                         pm8001_ha->fatal_bar_loc = 0;
 235                         pm8001_ha->forensic_fatal_step = 1;
 236                         pm8001_ha->fatal_forensic_shift_offset = 0;
 237                         pm8001_ha->forensic_last_offset = 0;
 238                         status = 0;
 239                         offset = (int)
 240                         ((char *)pm8001_ha->forensic_info.data_buf.direct_data
 241                         - (char *)buf);
 242                         PM8001_IO_DBG(pm8001_ha,
 243                         pm8001_printk("get_fatal_spcv:return1 0x%x\n", offset));
 244                         return (char *)pm8001_ha->
 245                                 forensic_info.data_buf.direct_data -
 246                                 (char *)buf;
 247                 }
 248                 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
 249                         pm8001_ha->forensic_info.data_buf.direct_data +=
 250                                 sprintf(pm8001_ha->
 251                                         forensic_info.data_buf.direct_data,
 252                                         "%08x ", 2);
 253                         for (index = 0; index <
 254                                 (pm8001_ha->forensic_info.data_buf.direct_len
 255                                  / 4); index++) {
 256                                 pm8001_ha->forensic_info.data_buf.direct_data
 257                                         += sprintf(pm8001_ha->
 258                                         forensic_info.data_buf.direct_data,
 259                                         "%08x ", *(temp + index));
 260                         }
 261                         status = 0;
 262                         offset = (int)
 263                         ((char *)pm8001_ha->forensic_info.data_buf.direct_data
 264                         - (char *)buf);
 265                         PM8001_IO_DBG(pm8001_ha,
 266                         pm8001_printk("get_fatal_spcv:return2 0x%x\n", offset));
 267                         return (char *)pm8001_ha->
 268                                 forensic_info.data_buf.direct_data -
 269                                 (char *)buf;
 270                 }
 271
 272                 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
 273                 pm8001_ha->forensic_info.data_buf.direct_data +=
 274                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 275                                 "%08x ", 2);
 276                 for (index = 0; index <
 277                         (pm8001_ha->forensic_info.data_buf.direct_len
 278                          / 4) ; index++) {
 279                         pm8001_ha->forensic_info.data_buf.direct_data +=
 280                                 sprintf(pm8001_ha->
 281                                 forensic_info.data_buf.direct_data,
 282                                 "%08x ", *(temp + index));
 283                 }
 284                 pm8001_ha->fatal_forensic_shift_offset += 0x100;
 285                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 286                         pm8001_ha->fatal_forensic_shift_offset);
 287                 pm8001_ha->fatal_bar_loc = 0;
 288                 status = 0;
 289                 offset = (int)
 290                         ((char *)pm8001_ha->forensic_info.data_buf.direct_data
 291                         - (char *)buf);
 292                 PM8001_IO_DBG(pm8001_ha,
 293                 pm8001_printk("get_fatal_spcv: return3 0x%x\n", offset));
 294                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 295                         (char *)buf;
 296         }
 297         if (pm8001_ha->forensic_fatal_step == 1) {
 298                 /* store previous accumulated length before triggering next
 299                  * accumulated length update
 300                  */
 301                 pm8001_ha->forensic_preserved_accumulated_transfer =
 302                         pm8001_mr32(fatal_table_address,
 303                         MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
 304
 305                 /* continue capturing the fatal log until Dump status is 0x3 */
 306                 if (pm8001_mr32(fatal_table_address,
 307                         MPI_FATAL_EDUMP_TABLE_STATUS) <
 308                         MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
 309
 310                         /* reset fddstat bit by writing to zero*/
 311                         pm8001_mw32(fatal_table_address,
 312                                         MPI_FATAL_EDUMP_TABLE_STATUS, 0x0);
 313
 314                         /* set dump control value to '1' so that new data will
 315                          * be transferred to shared memory
 316                          */
 317                         pm8001_mw32(fatal_table_address,
 318                                 MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
 319                                 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
 320
 321                         /*Poll FDDHSHK  until clear */
 322                         start = jiffies + (2 * HZ); /* 2 sec */
 323
 324                         do {
 325                                 reg_val = pm8001_mr32(fatal_table_address,
 326                                         MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
 327                         } while ((reg_val) && time_before(jiffies, start));
 328
 329                         if (reg_val != 0) {
 330                                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
 331                                 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n",
 332                                 reg_val));
 333                                /* Fail the dump if a timeout occurs */
 334                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 335                                 sprintf(
 336                                 pm8001_ha->forensic_info.data_buf.direct_data,
 337                                 "%08x ", 0xFFFFFFFF);
 338                                 return((char *)
 339                                 pm8001_ha->forensic_info.data_buf.direct_data
 340                                 - (char *)buf);
 341                         }
 342                         /* Poll status register until set to 2 or
 343                          * 3 for up to 2 seconds
 344                          */
 345                         start = jiffies + (2 * HZ); /* 2 sec */
 346
 347                         do {
 348                                 reg_val = pm8001_mr32(fatal_table_address,
 349                                         MPI_FATAL_EDUMP_TABLE_STATUS);
 350                         } while (((reg_val != 2) && (reg_val != 3)) &&
 351                                         time_before(jiffies, start));
 352
 353                         if (reg_val < 2) {
 354                                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
 355                                 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n",
 356                                 reg_val));
 357                                 /* Fail the dump if a timeout occurs */
 358                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 359                                 sprintf(
 360                                 pm8001_ha->forensic_info.data_buf.direct_data,
 361                                 "%08x ", 0xFFFFFFFF);
 362                                 pm8001_cw32(pm8001_ha, 0,
 363                                         MEMBASE_II_SHIFT_REGISTER,
 364                                         pm8001_ha->fatal_forensic_shift_offset);
 365                         }
 366                         /* Read the next block of the debug data.*/
 367                         length_to_read = pm8001_mr32(fatal_table_address,
 368                         MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) -
 369                         pm8001_ha->forensic_preserved_accumulated_transfer;
 370                         if (length_to_read != 0x0) {
 371                                 pm8001_ha->forensic_fatal_step = 0;
 372                                 goto moreData;
 373                         } else {
 374                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 375                                 sprintf(
 376                                 pm8001_ha->forensic_info.data_buf.direct_data,
 377                                 "%08x ", 4);
 378                                 pm8001_ha->forensic_info.data_buf.read_len
 379                                                                 = 0xFFFFFFFF;
 380                                 pm8001_ha->forensic_info.data_buf.direct_len
 381                                                                 =  0;
 382                                 pm8001_ha->forensic_info.data_buf.direct_offset
 383                                                                 = 0;
 384                                 pm8001_ha->forensic_info.data_buf.read_len = 0;
 385                         }
 386                 }
 387         }
 388         offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data
 389                         - (char *)buf);
 390         PM8001_IO_DBG(pm8001_ha,
 391                 pm8001_printk("get_fatal_spcv: return4 0x%x\n", offset));
 392         return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 393                 (char *)buf;
 394 }
 395
 396 /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma
 397  * location by the firmware.
 398  */
 399 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev,
 400         struct device_attribute *attr, char *buf)
 401 {
 402         struct Scsi_Host *shost = class_to_shost(cdev);
 403         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 404         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
 405         void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr;
 406         u32 accum_len = 0;
 407         u32 total_len = 0;
 408         u32 reg_val = 0;
 409         u32 *temp = NULL;
 410         u32 index = 0;
 411         u32 output_length;
 412         unsigned long start = 0;
 413         char *buf_copy = buf;
 414
 415         temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
 416         if (++pm8001_ha->non_fatal_count == 1) {
 417                 if (pm8001_ha->chip_id == chip_8001) {
 418                         snprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 419                                 PAGE_SIZE, "Not supported for SPC controller");
 420                         return 0;
 421                 }
 422                 PM8001_IO_DBG(pm8001_ha,
 423                         pm8001_printk("forensic_info TYPE_NON_FATAL...\n"));
 424                 /*
 425                  * Step 1: Write the host buffer parameters in the MPI Fatal and
 426                  * Non-Fatal Error Dump Capture Table.This is the buffer
 427                  * where debug data will be DMAed to.
 428                  */
 429                 pm8001_mw32(nonfatal_table_address,
 430                 MPI_FATAL_EDUMP_TABLE_LO_OFFSET,
 431                 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo);
 432
 433                 pm8001_mw32(nonfatal_table_address,
 434                 MPI_FATAL_EDUMP_TABLE_HI_OFFSET,
 435                 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi);
 436
 437                 pm8001_mw32(nonfatal_table_address,
 438                 MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET);
 439
 440                 /* Optionally, set the DUMPCTRL bit to 1 if the host
 441                  * keeps sending active I/Os while capturing the non-fatal
 442                  * debug data. Otherwise, leave this bit set to zero
 443                  */
 444                 pm8001_mw32(nonfatal_table_address,
 445                 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY);
 446
 447                 /*
 448                  * Step 2: Clear Accumulative Length of Debug Data Transferred
 449                  * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump
 450                  * Capture Table to zero.
 451                  */
 452                 pm8001_mw32(nonfatal_table_address,
 453                                 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0);
 454
 455                 /* initiallize previous accumulated length to 0 */
 456                 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
 457                 pm8001_ha->non_fatal_read_length = 0;
 458         }
 459
 460         total_len = pm8001_mr32(nonfatal_table_address,
 461                         MPI_FATAL_EDUMP_TABLE_TOTAL_LEN);
 462         /*
 463          * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT]
 464          * field and then request that the SPCv controller transfer the debug
 465          * data by setting bit 7 of the Inbound Doorbell Set Register.
 466          */
 467         pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0);
 468         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET,
 469                         SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP);
 470
 471         /*
 472          * Step 4.1: Read back the Inbound Doorbell Set Register (by polling for
 473          * 2 seconds) until register bit 7 is cleared.
 474          * This step only indicates the request is accepted by the controller.
 475          */
 476         start = jiffies + (2 * HZ); /* 2 sec */
 477         do {
 478                 reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) &
 479                         SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP;
 480         } while ((reg_val != 0) && time_before(jiffies, start));
 481
 482         /* Step 4.2: To check the completion of the transfer, poll the Fatal/Non
 483          * Fatal Debug Data Transfer Status [FDDTSTAT] field for 2 seconds in
 484          * the MPI Fatal and Non-Fatal Error Dump Capture Table.
 485          */
 486         start = jiffies + (2 * HZ); /* 2 sec */
 487         do {
 488                 reg_val = pm8001_mr32(nonfatal_table_address,
 489                                 MPI_FATAL_EDUMP_TABLE_STATUS);
 490         } while ((!reg_val) && time_before(jiffies, start));
 491
 492         if ((reg_val == 0x00) ||
 493                 (reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) ||
 494                 (reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) {
 495                 pm8001_ha->non_fatal_read_length = 0;
 496                 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF);
 497                 pm8001_ha->non_fatal_count = 0;
 498                 return (buf_copy - buf);
 499         } else if (reg_val ==
 500                         MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) {
 501                 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2);
 502         } else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) ||
 503                 (pm8001_ha->non_fatal_read_length >= total_len)) {
 504                 pm8001_ha->non_fatal_read_length = 0;
 505                 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4);
 506                 pm8001_ha->non_fatal_count = 0;
 507         }
 508         accum_len = pm8001_mr32(nonfatal_table_address,
 509                         MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
 510         output_length = accum_len -
 511                 pm8001_ha->forensic_preserved_accumulated_transfer;
 512
 513         for (index = 0; index < output_length/4; index++)
 514                 buf_copy += snprintf(buf_copy, PAGE_SIZE,
 515                                 "%08x ", *(temp+index));
 516
 517         pm8001_ha->non_fatal_read_length += output_length;
 518
 519         /* store current accumulated length to use in next iteration as
 520          * the previous accumulated length
 521          */
 522         pm8001_ha->forensic_preserved_accumulated_transfer = accum_len;
 523         return (buf_copy - buf);
 524 }
 525
 526 /**
 527  * read_main_config_table - read the configure table and save it.
 528  * @pm8001_ha: our hba card information
 529  */
 530 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
 531 {
 532         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 533
 534         pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature    =
 535                 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
 536         pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
 537                 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
 538         pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
 539                 pm8001_mr32(address, MAIN_FW_REVISION);
 540         pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io   =
 541                 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
 542         pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl      =
 543                 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
 544         pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
 545                 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
 546         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset   =
 547                 pm8001_mr32(address, MAIN_GST_OFFSET);
 548         pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
 549                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
 550         pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
 551                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
 552
 553         /* read Error Dump Offset and Length */
 554         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
 555                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
 556         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
 557                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
 558         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
 559                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
 560         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
 561                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
 562
 563         /* read GPIO LED settings from the configuration table */
 564         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
 565                 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
 566
 567         /* read analog Setting offset from the configuration table */
 568         pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
 569                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
 570
 571         pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
 572                 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
 573         pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
 574                 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
 575         /* read port recover and reset timeout */
 576         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
 577                 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
 578         /* read ILA and inactive firmware version */
 579         pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =
 580                 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE);
 581         pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =
 582                 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION);
 583
 584         PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
 585                 "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n",
 586                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature,
 587                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev,
 588                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev));
 589
 590         PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
 591                 "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n",
 592                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset,
 593                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset,
 594                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset,
 595                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset,
 596                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset));
 597
 598         PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
 599                 "Main cfg table; ila rev:%x Inactive fw rev:%x\n",
 600                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version,
 601                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version));
 602 }
 603
 604 /**
 605  * read_general_status_table - read the general status table and save it.
 606  * @pm8001_ha: our hba card information
 607  */
 608 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
 609 {
 610         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
 611         pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate   =
 612                         pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
 613         pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0   =
 614                         pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
 615         pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1   =
 616                         pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
 617         pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt          =
 618                         pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
 619         pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt           =
 620                         pm8001_mr32(address, GST_IOPTCNT_OFFSET);
 621         pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val     =
 622                         pm8001_mr32(address, GST_GPIO_INPUT_VAL);
 623         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
 624                         pm8001_mr32(address, GST_RERRINFO_OFFSET0);
 625         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
 626                         pm8001_mr32(address, GST_RERRINFO_OFFSET1);
 627         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
 628                         pm8001_mr32(address, GST_RERRINFO_OFFSET2);
 629         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
 630                         pm8001_mr32(address, GST_RERRINFO_OFFSET3);
 631         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
 632                         pm8001_mr32(address, GST_RERRINFO_OFFSET4);
 633         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
 634                         pm8001_mr32(address, GST_RERRINFO_OFFSET5);
 635         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
 636                         pm8001_mr32(address, GST_RERRINFO_OFFSET6);
 637         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
 638                          pm8001_mr32(address, GST_RERRINFO_OFFSET7);
 639 }
 640 /**
 641  * read_phy_attr_table - read the phy attribute table and save it.
 642  * @pm8001_ha: our hba card information
 643  */
 644 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
 645 {
 646         void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
 647         pm8001_ha->phy_attr_table.phystart1_16[0] =
 648                         pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
 649         pm8001_ha->phy_attr_table.phystart1_16[1] =
 650                         pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
 651         pm8001_ha->phy_attr_table.phystart1_16[2] =
 652                         pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
 653         pm8001_ha->phy_attr_table.phystart1_16[3] =
 654                         pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
 655         pm8001_ha->phy_attr_table.phystart1_16[4] =
 656                         pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
 657         pm8001_ha->phy_attr_table.phystart1_16[5] =
 658                         pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
 659         pm8001_ha->phy_attr_table.phystart1_16[6] =
 660                         pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
 661         pm8001_ha->phy_attr_table.phystart1_16[7] =
 662                         pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
 663         pm8001_ha->phy_attr_table.phystart1_16[8] =
 664                         pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
 665         pm8001_ha->phy_attr_table.phystart1_16[9] =
 666                         pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
 667         pm8001_ha->phy_attr_table.phystart1_16[10] =
 668                         pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
 669         pm8001_ha->phy_attr_table.phystart1_16[11] =
 670                         pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
 671         pm8001_ha->phy_attr_table.phystart1_16[12] =
 672                         pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
 673         pm8001_ha->phy_attr_table.phystart1_16[13] =
 674                         pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
 675         pm8001_ha->phy_attr_table.phystart1_16[14] =
 676                         pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
 677         pm8001_ha->phy_attr_table.phystart1_16[15] =
 678                         pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
 679
 680         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
 681                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
 682         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
 683                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
 684         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
 685                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
 686         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
 687                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
 688         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
 689                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
 690         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
 691                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
 692         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
 693                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
 694         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
 695                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
 696         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
 697                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
 698         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
 699                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
 700         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
 701                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
 702         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
 703                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
 704         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
 705                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
 706         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
 707                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
 708         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
 709                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
 710         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
 711                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
 712
 713 }
 714
 715 /**
 716  * read_inbnd_queue_table - read the inbound queue table and save it.
 717  * @pm8001_ha: our hba card information
 718  */
 719 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 720 {
 721         int i;
 722         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 723         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
 724                 u32 offset = i * 0x20;
 725                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 726                         get_pci_bar_index(pm8001_mr32(address,
 727                                 (offset + IB_PIPCI_BAR)));
 728                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 729                         pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
 730         }
 731 }
 732
 733 /**
 734  * read_outbnd_queue_table - read the outbound queue table and save it.
 735  * @pm8001_ha: our hba card information
 736  */
 737 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 738 {
 739         int i;
 740         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 741         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
 742                 u32 offset = i * 0x24;
 743                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 744                         get_pci_bar_index(pm8001_mr32(address,
 745                                 (offset + OB_CIPCI_BAR)));
 746                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 747                         pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
 748         }
 749 }
 750
 751 /**
 752  * init_default_table_values - init the default table.
 753  * @pm8001_ha: our hba card information
 754  */
 755 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 756 {
 757         int i;
 758         u32 offsetib, offsetob;
 759         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 760         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 761
 762         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr         =
 763                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 764         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr         =
 765                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 766         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size               =
 767                                                         PM8001_EVENT_LOG_SIZE;
 768         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity           = 0x01;
 769         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr     =
 770                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 771         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr     =
 772                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 773         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size           =
 774                                                         PM8001_EVENT_LOG_SIZE;
 775         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity       = 0x01;
 776         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt          = 0x01;
 777
 778         /* Disable end to end CRC checking */
 779         pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
 780
 781         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
 782                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 783                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
 784                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 785                         pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
 786                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 787                 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
 788                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 789                         (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
 790                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 791                         pm8001_ha->memoryMap.region[IB + i].total_len;
 792                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 793                         pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
 794                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 795                         pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
 796                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 797                         pm8001_ha->memoryMap.region[CI + i].virt_ptr;
 798                 offsetib = i * 0x20;
 799                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 800                         get_pci_bar_index(pm8001_mr32(addressib,
 801                                 (offsetib + 0x14)));
 802                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 803                         pm8001_mr32(addressib, (offsetib + 0x18));
 804                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 805                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 806
 807                 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
 808                         "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i,
 809                         pm8001_ha->inbnd_q_tbl[i].pi_pci_bar,
 810                         pm8001_ha->inbnd_q_tbl[i].pi_offset));
 811         }
 812         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
 813                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 814                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
 815                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 816                         pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
 817                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 818                         pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
 819                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 820                         (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
 821                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 822                         pm8001_ha->memoryMap.region[OB + i].total_len;
 823                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 824                         pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
 825                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 826                         pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
 827                 /* interrupt vector based on oq */
 828                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
 829                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 830                         pm8001_ha->memoryMap.region[PI + i].virt_ptr;
 831                 offsetob = i * 0x24;
 832                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 833                         get_pci_bar_index(pm8001_mr32(addressob,
 834                         offsetob + 0x14));
 835                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 836                         pm8001_mr32(addressob, (offsetob + 0x18));
 837                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 838                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 839
 840                 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
 841                         "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i,
 842                         pm8001_ha->outbnd_q_tbl[i].ci_pci_bar,
 843                         pm8001_ha->outbnd_q_tbl[i].ci_offset));
 844         }
 845 }
 846
 847 /**
 848  * update_main_config_table - update the main default table to the HBA.
 849  * @pm8001_ha: our hba card information
 850  */
 851 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 852 {
 853         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 854         pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
 855                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
 856         pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
 857                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
 858         pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
 859                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
 860         pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
 861                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
 862         pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
 863                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
 864         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
 865                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
 866         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
 867                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
 868         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
 869                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
 870         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
 871                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
 872         /* Update Fatal error interrupt vector */
 873         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
 874                                         ((pm8001_ha->number_of_intr - 1) << 8);
 875         pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
 876                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
 877         PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
 878                 "Updated Fatal error interrupt vector 0x%x\n",
 879                 pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT)));
 880
 881         pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
 882                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
 883
 884         /* SPCv specific */
 885         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
 886         /* Set GPIOLED to 0x2 for LED indicator */
 887         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
 888         pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
 889                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
 890         PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
 891                 "Programming DW 0x21 in main cfg table with 0x%x\n",
 892                 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET)));
 893
 894         pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
 895                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
 896         pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
 897                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
 898
 899         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
 900         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
 901                                                         PORT_RECOVERY_TIMEOUT;
 902         if (pm8001_ha->chip_id == chip_8006) {
 903                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=
 904                                         0x0000ffff;
 905                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
 906                                         CHIP_8006_PORT_RECOVERY_TIMEOUT;
 907         }
 908         pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
 909                         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
 910 }
 911
 912 /**
 913  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 914  * @pm8001_ha: our hba card information
 915  * @number: entry in the queue
 916  */
 917 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 918                                          int number)
 919 {
 920         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 921         u16 offset = number * 0x20;
 922         pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
 923                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 924         pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
 925                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 926         pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
 927                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 928         pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
 929                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 930         pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
 931                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 932
 933         PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
 934                 "IQ %d: Element pri size 0x%x\n",
 935                 number,
 936                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt));
 937
 938         PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
 939                 "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n",
 940                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr,
 941                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr));
 942
 943         PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
 944                 "CI upper base addr 0x%x CI lower base addr 0x%x\n",
 945                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr,
 946                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr));
 947 }
 948
 949 /**
 950  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 951  * @pm8001_ha: our hba card information
 952  * @number: entry in the queue
 953  */
 954 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 955                                                  int number)
 956 {
 957         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 958         u16 offset = number * 0x24;
 959         pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
 960                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 961         pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
 962                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 963         pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
 964                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 965         pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
 966                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 967         pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
 968                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 969         pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
 970                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 971
 972         PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
 973                 "OQ %d: Element pri size 0x%x\n",
 974                 number,
 975                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt));
 976
 977         PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
 978                 "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n",
 979                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr,
 980                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr));
 981
 982         PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
 983                 "PI upper base addr 0x%x PI lower base addr 0x%x\n",
 984                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr,
 985                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr));
 986 }
 987
 988 /**
 989  * mpi_init_check - check firmware initialization status.
 990  * @pm8001_ha: our hba card information
 991  */
 992 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 993 {
 994         u32 max_wait_count;
 995         u32 value;
 996         u32 gst_len_mpistate;
 997
 998         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 999         table is updated */
1000         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
1001         /* wait until Inbound DoorBell Clear Register toggled */
1002         if (IS_SPCV_12G(pm8001_ha->pdev)) {
1003                 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
1004         } else {
1005                 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
1006         }
1007         do {
1008                 udelay(1);
1009                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1010                 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
1011         } while ((value != 0) && (--max_wait_count));
1012
1013         if (!max_wait_count)
1014                 return -1;
1015         /* check the MPI-State for initialization upto 100ms*/
1016         max_wait_count = 100 * 1000;/* 100 msec */
1017         do {
1018                 udelay(1);
1019                 gst_len_mpistate =
1020                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1021                                         GST_GSTLEN_MPIS_OFFSET);
1022         } while ((GST_MPI_STATE_INIT !=
1023                 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
1024         if (!max_wait_count)
1025                 return -1;
1026
1027         /* check MPI Initialization error */
1028         gst_len_mpistate = gst_len_mpistate >> 16;
1029         if (0x0000 != gst_len_mpistate)
1030                 return -1;
1031
1032         return 0;
1033 }
1034
1035 /**
1036  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
1037  * @pm8001_ha: our hba card information
1038  */
1039 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
1040 {
1041         u32 value;
1042         u32 max_wait_count;
1043         u32 max_wait_time;
1044         int ret = 0;
1045
1046         /* reset / PCIe ready */
1047         max_wait_time = max_wait_count = 100 * 1000;    /* 100 milli sec */
1048         do {
1049                 udelay(1);
1050                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1051         } while ((value == 0xFFFFFFFF) && (--max_wait_count));
1052
1053         /* check ila status */
1054         max_wait_time = max_wait_count = 1000 * 1000;   /* 1000 milli sec */
1055         do {
1056                 udelay(1);
1057                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1058         } while (((value & SCRATCH_PAD_ILA_READY) !=
1059                         SCRATCH_PAD_ILA_READY) && (--max_wait_count));
1060         if (!max_wait_count)
1061                 ret = -1;
1062         else {
1063                 PM8001_MSG_DBG(pm8001_ha,
1064                         pm8001_printk(" ila ready status in %d millisec\n",
1065                                 (max_wait_time - max_wait_count)));
1066         }
1067
1068         /* check RAAE status */
1069         max_wait_time = max_wait_count = 1800 * 1000;   /* 1800 milli sec */
1070         do {
1071                 udelay(1);
1072                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1073         } while (((value & SCRATCH_PAD_RAAE_READY) !=
1074                                 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
1075         if (!max_wait_count)
1076                 ret = -1;
1077         else {
1078                 PM8001_MSG_DBG(pm8001_ha,
1079                         pm8001_printk(" raae ready status in %d millisec\n",
1080                                         (max_wait_time - max_wait_count)));
1081         }
1082
1083         /* check iop0 status */
1084         max_wait_time = max_wait_count = 600 * 1000;    /* 600 milli sec */
1085         do {
1086                 udelay(1);
1087                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1088         } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
1089                         (--max_wait_count));
1090         if (!max_wait_count)
1091                 ret = -1;
1092         else {
1093                 PM8001_MSG_DBG(pm8001_ha,
1094                         pm8001_printk(" iop0 ready status in %d millisec\n",
1095                                 (max_wait_time - max_wait_count)));
1096         }
1097
1098         /* check iop1 status only for 16 port controllers */
1099         if ((pm8001_ha->chip_id != chip_8008) &&
1100                         (pm8001_ha->chip_id != chip_8009)) {
1101                 /* 200 milli sec */
1102                 max_wait_time = max_wait_count = 200 * 1000;
1103                 do {
1104                         udelay(1);
1105                         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1106                 } while (((value & SCRATCH_PAD_IOP1_READY) !=
1107                                 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
1108                 if (!max_wait_count)
1109                         ret = -1;
1110                 else {
1111                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1112                                 "iop1 ready status in %d millisec\n",
1113                                 (max_wait_time - max_wait_count)));
1114                 }
1115         }
1116
1117         return ret;
1118 }
1119
1120 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
1121 {
1122         void __iomem *base_addr;
1123         u32     value;
1124         u32     offset;
1125         u32     pcibar;
1126         u32     pcilogic;
1127
1128         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1129         offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
1130
1131         PM8001_DEV_DBG(pm8001_ha,
1132                 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
1133                                 offset, value));
1134         pcilogic = (value & 0xFC000000) >> 26;
1135         pcibar = get_pci_bar_index(pcilogic);
1136         PM8001_INIT_DBG(pm8001_ha,
1137                 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
1138         pm8001_ha->main_cfg_tbl_addr = base_addr =
1139                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
1140         pm8001_ha->general_stat_tbl_addr =
1141                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
1142                                         0xFFFFFF);
1143         pm8001_ha->inbnd_q_tbl_addr =
1144                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
1145                                         0xFFFFFF);
1146         pm8001_ha->outbnd_q_tbl_addr =
1147                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
1148                                         0xFFFFFF);
1149         pm8001_ha->ivt_tbl_addr =
1150                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
1151                                         0xFFFFFF);
1152         pm8001_ha->pspa_q_tbl_addr =
1153                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
1154                                         0xFFFFFF);
1155         pm8001_ha->fatal_tbl_addr =
1156                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
1157                                         0xFFFFFF);
1158
1159         PM8001_INIT_DBG(pm8001_ha,
1160                         pm8001_printk("GST OFFSET 0x%x\n",
1161                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
1162         PM8001_INIT_DBG(pm8001_ha,
1163                         pm8001_printk("INBND OFFSET 0x%x\n",
1164                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
1165         PM8001_INIT_DBG(pm8001_ha,
1166                         pm8001_printk("OBND OFFSET 0x%x\n",
1167                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
1168         PM8001_INIT_DBG(pm8001_ha,
1169                         pm8001_printk("IVT OFFSET 0x%x\n",
1170                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
1171         PM8001_INIT_DBG(pm8001_ha,
1172                         pm8001_printk("PSPA OFFSET 0x%x\n",
1173                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
1174         PM8001_INIT_DBG(pm8001_ha,
1175                         pm8001_printk("addr - main cfg %p general status %p\n",
1176                         pm8001_ha->main_cfg_tbl_addr,
1177                         pm8001_ha->general_stat_tbl_addr));
1178         PM8001_INIT_DBG(pm8001_ha,
1179                         pm8001_printk("addr - inbnd %p obnd %p\n",
1180                         pm8001_ha->inbnd_q_tbl_addr,
1181                         pm8001_ha->outbnd_q_tbl_addr));
1182         PM8001_INIT_DBG(pm8001_ha,
1183                         pm8001_printk("addr - pspa %p ivt %p\n",
1184                         pm8001_ha->pspa_q_tbl_addr,
1185                         pm8001_ha->ivt_tbl_addr));
1186 }
1187
1188 /**
1189  * pm80xx_set_thermal_config - support the thermal configuration
1190  * @pm8001_ha: our hba card information.
1191  */
1192 int
1193 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
1194 {
1195         struct set_ctrl_cfg_req payload;
1196         struct inbound_queue_table *circularQ;
1197         int rc;
1198         u32 tag;
1199         u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1200         u32 page_code;
1201
1202         memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1203         rc = pm8001_tag_alloc(pm8001_ha, &tag);
1204         if (rc)
1205                 return -1;
1206
1207         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1208         payload.tag = cpu_to_le32(tag);
1209
1210         if (IS_SPCV_12G(pm8001_ha->pdev))
1211                 page_code = THERMAL_PAGE_CODE_7H;
1212         else
1213                 page_code = THERMAL_PAGE_CODE_8H;
1214
1215         payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
1216                                 (THERMAL_ENABLE << 8) | page_code;
1217         payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
1218
1219         PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
1220                 "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n",
1221                 payload.cfg_pg[0], payload.cfg_pg[1]));
1222
1223         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1224                         sizeof(payload), 0);
1225         if (rc)
1226                 pm8001_tag_free(pm8001_ha, tag);
1227         return rc;
1228
1229 }
1230
1231 /**
1232 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
1233 * Timer configuration page
1234 * @pm8001_ha: our hba card information.
1235 */
1236 static int
1237 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
1238 {
1239         struct set_ctrl_cfg_req payload;
1240         struct inbound_queue_table *circularQ;
1241         SASProtocolTimerConfig_t SASConfigPage;
1242         int rc;
1243         u32 tag;
1244         u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1245
1246         memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1247         memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
1248
1249         rc = pm8001_tag_alloc(pm8001_ha, &tag);
1250
1251         if (rc)
1252                 return -1;
1253
1254         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1255         payload.tag = cpu_to_le32(tag);
1256
1257         SASConfigPage.pageCode        =  SAS_PROTOCOL_TIMER_CONFIG_PAGE;
1258         SASConfigPage.MST_MSI         =  3 << 15;
1259         SASConfigPage.STP_SSP_MCT_TMO =  (STP_MCT_TMO << 16) | SSP_MCT_TMO;
1260         SASConfigPage.STP_FRM_TMO     = (SAS_MAX_OPEN_TIME << 24) |
1261                                 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
1262         SASConfigPage.STP_IDLE_TMO    =  STP_IDLE_TIME;
1263
1264         if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
1265                 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
1266
1267
1268         SASConfigPage.OPNRJT_RTRY_INTVL =         (SAS_MFD << 16) |
1269                                                 SAS_OPNRJT_RTRY_INTVL;
1270         SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO =  (SAS_DOPNRJT_RTRY_TMO << 16)
1271                                                 | SAS_COPNRJT_RTRY_TMO;
1272         SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR =  (SAS_DOPNRJT_RTRY_THR << 16)
1273                                                 | SAS_COPNRJT_RTRY_THR;
1274         SASConfigPage.MAX_AIP =  SAS_MAX_AIP;
1275
1276         PM8001_INIT_DBG(pm8001_ha,
1277                         pm8001_printk("SASConfigPage.pageCode "
1278                         "0x%08x\n", SASConfigPage.pageCode));
1279         PM8001_INIT_DBG(pm8001_ha,
1280                         pm8001_printk("SASConfigPage.MST_MSI "
1281                         " 0x%08x\n", SASConfigPage.MST_MSI));
1282         PM8001_INIT_DBG(pm8001_ha,
1283                         pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO "
1284                         " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO));
1285         PM8001_INIT_DBG(pm8001_ha,
1286                         pm8001_printk("SASConfigPage.STP_FRM_TMO "
1287                         " 0x%08x\n", SASConfigPage.STP_FRM_TMO));
1288         PM8001_INIT_DBG(pm8001_ha,
1289                         pm8001_printk("SASConfigPage.STP_IDLE_TMO "
1290                         " 0x%08x\n", SASConfigPage.STP_IDLE_TMO));
1291         PM8001_INIT_DBG(pm8001_ha,
1292                         pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL "
1293                         " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL));
1294         PM8001_INIT_DBG(pm8001_ha,
1295                         pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO "
1296                         " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
1297         PM8001_INIT_DBG(pm8001_ha,
1298                         pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR "
1299                         " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
1300         PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP "
1301                         " 0x%08x\n", SASConfigPage.MAX_AIP));
1302
1303         memcpy(&payload.cfg_pg, &SASConfigPage,
1304                          sizeof(SASProtocolTimerConfig_t));
1305
1306         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1307                         sizeof(payload), 0);
1308         if (rc)
1309                 pm8001_tag_free(pm8001_ha, tag);
1310
1311         return rc;
1312 }
1313
1314 /**
1315  * pm80xx_get_encrypt_info - Check for encryption
1316  * @pm8001_ha: our hba card information.
1317  */
1318 static int
1319 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
1320 {
1321         u32 scratch3_value;
1322         int ret = -1;
1323
1324         /* Read encryption status from SCRATCH PAD 3 */
1325         scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1326
1327         if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1328                                         SCRATCH_PAD3_ENC_READY) {
1329                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1330                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1331                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1332                                                 SCRATCH_PAD3_SMF_ENABLED)
1333                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1334                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1335                                                 SCRATCH_PAD3_SMA_ENABLED)
1336                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1337                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1338                                                 SCRATCH_PAD3_SMB_ENABLED)
1339                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1340                 pm8001_ha->encrypt_info.status = 0;
1341                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1342                         "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
1343                         "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
1344                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1345                         pm8001_ha->encrypt_info.sec_mode,
1346                         pm8001_ha->encrypt_info.status));
1347                 ret = 0;
1348         } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
1349                                         SCRATCH_PAD3_ENC_DISABLED) {
1350                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1351                         "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
1352                         scratch3_value));
1353                 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
1354                 pm8001_ha->encrypt_info.cipher_mode = 0;
1355                 pm8001_ha->encrypt_info.sec_mode = 0;
1356                 ret = 0;
1357         } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1358                                 SCRATCH_PAD3_ENC_DIS_ERR) {
1359                 pm8001_ha->encrypt_info.status =
1360                         (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1361                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1362                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1363                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1364                                         SCRATCH_PAD3_SMF_ENABLED)
1365                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1366                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1367                                         SCRATCH_PAD3_SMA_ENABLED)
1368                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1369                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1370                                         SCRATCH_PAD3_SMB_ENABLED)
1371                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1372                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1373                         "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
1374                         "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1375                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1376                         pm8001_ha->encrypt_info.sec_mode,
1377                         pm8001_ha->encrypt_info.status));
1378         } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1379                                  SCRATCH_PAD3_ENC_ENA_ERR) {
1380
1381                 pm8001_ha->encrypt_info.status =
1382                         (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1383                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1384                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1385                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1386                                         SCRATCH_PAD3_SMF_ENABLED)
1387                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1388                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1389                                         SCRATCH_PAD3_SMA_ENABLED)
1390                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1391                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1392                                         SCRATCH_PAD3_SMB_ENABLED)
1393                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1394
1395                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1396                         "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
1397                         "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1398                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1399                         pm8001_ha->encrypt_info.sec_mode,
1400                         pm8001_ha->encrypt_info.status));
1401         }
1402         return ret;
1403 }
1404
1405 /**
1406  * pm80xx_encrypt_update - update flash with encryption informtion
1407  * @pm8001_ha: our hba card information.
1408  */
1409 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1410 {
1411         struct kek_mgmt_req payload;
1412         struct inbound_queue_table *circularQ;
1413         int rc;
1414         u32 tag;
1415         u32 opc = OPC_INB_KEK_MANAGEMENT;
1416
1417         memset(&payload, 0, sizeof(struct kek_mgmt_req));
1418         rc = pm8001_tag_alloc(pm8001_ha, &tag);
1419         if (rc)
1420                 return -1;
1421
1422         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1423         payload.tag = cpu_to_le32(tag);
1424         /* Currently only one key is used. New KEK index is 1.
1425          * Current KEK index is 1. Store KEK to NVRAM is 1.
1426          */
1427         payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
1428                                         KEK_MGMT_SUBOP_KEYCARDUPDATE);
1429
1430         PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
1431                 "Saving Encryption info to flash. payload 0x%x\n",
1432                 payload.new_curidx_ksop));
1433
1434         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1435                         sizeof(payload), 0);
1436         if (rc)
1437                 pm8001_tag_free(pm8001_ha, tag);
1438
1439         return rc;
1440 }
1441
1442 /**
1443  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
1444  * @pm8001_ha: our hba card information
1445  */
1446 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1447 {
1448         int ret;
1449         u8 i = 0;
1450
1451         /* check the firmware status */
1452         if (-1 == check_fw_ready(pm8001_ha)) {
1453                 PM8001_FAIL_DBG(pm8001_ha,
1454                         pm8001_printk("Firmware is not ready!\n"));
1455                 return -EBUSY;
1456         }
1457
1458         /* Initialize the controller fatal error flag */
1459         pm8001_ha->controller_fatal_error = false;
1460
1461         /* Initialize pci space address eg: mpi offset */
1462         init_pci_device_addresses(pm8001_ha);
1463         init_default_table_values(pm8001_ha);
1464         read_main_config_table(pm8001_ha);
1465         read_general_status_table(pm8001_ha);
1466         read_inbnd_queue_table(pm8001_ha);
1467         read_outbnd_queue_table(pm8001_ha);
1468         read_phy_attr_table(pm8001_ha);
1469
1470         /* update main config table ,inbound table and outbound table */
1471         update_main_config_table(pm8001_ha);
1472         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++)
1473                 update_inbnd_queue_table(pm8001_ha, i);
1474         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++)
1475                 update_outbnd_queue_table(pm8001_ha, i);
1476
1477         /* notify firmware update finished and check initialization status */
1478         if (0 == mpi_init_check(pm8001_ha)) {
1479                 PM8001_INIT_DBG(pm8001_ha,
1480                         pm8001_printk("MPI initialize successful!\n"));
1481         } else
1482                 return -EBUSY;
1483
1484         /* send SAS protocol timer configuration page to FW */
1485         ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1486
1487         /* Check for encryption */
1488         if (pm8001_ha->chip->encrypt) {
1489                 PM8001_INIT_DBG(pm8001_ha,
1490                         pm8001_printk("Checking for encryption\n"));
1491                 ret = pm80xx_get_encrypt_info(pm8001_ha);
1492                 if (ret == -1) {
1493                         PM8001_INIT_DBG(pm8001_ha,
1494                                 pm8001_printk("Encryption error !!\n"));
1495                         if (pm8001_ha->encrypt_info.status == 0x81) {
1496                                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1497                                         "Encryption enabled with error."
1498                                         "Saving encryption key to flash\n"));
1499                                 pm80xx_encrypt_update(pm8001_ha);
1500                         }
1501                 }
1502         }
1503         return 0;
1504 }
1505
1506 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1507 {
1508         u32 max_wait_count;
1509         u32 value;
1510         u32 gst_len_mpistate;
1511         init_pci_device_addresses(pm8001_ha);
1512         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1513         table is stop */
1514         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1515
1516         /* wait until Inbound DoorBell Clear Register toggled */
1517         if (IS_SPCV_12G(pm8001_ha->pdev)) {
1518                 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
1519         } else {
1520                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1521         }
1522         do {
1523                 udelay(1);
1524                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1525                 value &= SPCv_MSGU_CFG_TABLE_RESET;
1526         } while ((value != 0) && (--max_wait_count));
1527
1528         if (!max_wait_count) {
1529                 PM8001_FAIL_DBG(pm8001_ha,
1530                         pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
1531                 return -1;
1532         }
1533
1534         /* check the MPI-State for termination in progress */
1535         /* wait until Inbound DoorBell Clear Register toggled */
1536         max_wait_count = 2 * 1000 * 1000;       /* 2 sec for spcv/ve */
1537         do {
1538                 udelay(1);
1539                 gst_len_mpistate =
1540                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1541                         GST_GSTLEN_MPIS_OFFSET);
1542                 if (GST_MPI_STATE_UNINIT ==
1543                         (gst_len_mpistate & GST_MPI_STATE_MASK))
1544                         break;
1545         } while (--max_wait_count);
1546         if (!max_wait_count) {
1547                 PM8001_FAIL_DBG(pm8001_ha,
1548                         pm8001_printk(" TIME OUT MPI State = 0x%x\n",
1549                                 gst_len_mpistate & GST_MPI_STATE_MASK));
1550                 return -1;
1551         }
1552
1553         return 0;
1554 }
1555
1556 /**
1557  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
1558  * the FW register status to the originated status.
1559  * @pm8001_ha: our hba card information
1560  */
1561
1562 static int
1563 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1564 {
1565         u32 regval;
1566         u32 bootloader_state;
1567         u32 ibutton0, ibutton1;
1568
1569         /* Process MPI table uninitialization only if FW is ready */
1570         if (!pm8001_ha->controller_fatal_error) {
1571                 /* Check if MPI is in ready state to reset */
1572                 if (mpi_uninit_check(pm8001_ha) != 0) {
1573                         u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1574                         u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1575                         u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1576                         u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1577                         PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1578                                 "MPI state is not ready scratch: %x:%x:%x:%x\n",
1579                                 r0, r1, r2, r3));
1580                         /* if things aren't ready but the bootloader is ok then
1581                          * try the reset anyway.
1582                          */
1583                         if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK)
1584                                 return -1;
1585                 }
1586         }
1587         /* checked for reset register normal state; 0x0 */
1588         regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1589         PM8001_INIT_DBG(pm8001_ha,
1590                 pm8001_printk("reset register before write : 0x%x\n", regval));
1591
1592         pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1593         msleep(500);
1594
1595         regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1596         PM8001_INIT_DBG(pm8001_ha,
1597         pm8001_printk("reset register after write 0x%x\n", regval));
1598
1599         if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1600                         SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1601                 PM8001_MSG_DBG(pm8001_ha,
1602                         pm8001_printk(" soft reset successful [regval: 0x%x]\n",
1603                                         regval));
1604         } else {
1605                 PM8001_MSG_DBG(pm8001_ha,
1606                         pm8001_printk(" soft reset failed [regval: 0x%x]\n",
1607                                         regval));
1608
1609                 /* check bootloader is successfully executed or in HDA mode */
1610                 bootloader_state =
1611                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1612                         SCRATCH_PAD1_BOOTSTATE_MASK;
1613
1614                 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1615                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1616                                 "Bootloader state - HDA mode SEEPROM\n"));
1617                 } else if (bootloader_state ==
1618                                 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1619                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1620                                 "Bootloader state - HDA mode Bootstrap Pin\n"));
1621                 } else if (bootloader_state ==
1622                                 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1623                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1624                                 "Bootloader state - HDA mode soft reset\n"));
1625                 } else if (bootloader_state ==
1626                                         SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1627                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1628                                 "Bootloader state-HDA mode critical error\n"));
1629                 }
1630                 return -EBUSY;
1631         }
1632
1633         /* check the firmware status after reset */
1634         if (-1 == check_fw_ready(pm8001_ha)) {
1635                 PM8001_FAIL_DBG(pm8001_ha,
1636                         pm8001_printk("Firmware is not ready!\n"));
1637                 /* check iButton feature support for motherboard controller */
1638                 if (pm8001_ha->pdev->subsystem_vendor !=
1639                         PCI_VENDOR_ID_ADAPTEC2 &&
1640                         pm8001_ha->pdev->subsystem_vendor !=
1641                         PCI_VENDOR_ID_ATTO &&
1642                         pm8001_ha->pdev->subsystem_vendor != 0) {
1643                         ibutton0 = pm8001_cr32(pm8001_ha, 0,
1644                                         MSGU_HOST_SCRATCH_PAD_6);
1645                         ibutton1 = pm8001_cr32(pm8001_ha, 0,
1646                                         MSGU_HOST_SCRATCH_PAD_7);
1647                         if (!ibutton0 && !ibutton1) {
1648                                 PM8001_FAIL_DBG(pm8001_ha,
1649                                         pm8001_printk("iButton Feature is"
1650                                         " not Available!!!\n"));
1651                                 return -EBUSY;
1652                         }
1653                         if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1654                                 PM8001_FAIL_DBG(pm8001_ha,
1655                                         pm8001_printk("CRC Check for iButton"
1656                                         " Feature Failed!!!\n"));
1657                                 return -EBUSY;
1658                         }
1659                 }
1660         }
1661         PM8001_INIT_DBG(pm8001_ha,
1662                 pm8001_printk("SPCv soft reset Complete\n"));
1663         return 0;
1664 }
1665
1666 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1667 {
1668         u32 i;
1669
1670         PM8001_INIT_DBG(pm8001_ha,
1671                 pm8001_printk("chip reset start\n"));
1672
1673         /* do SPCv chip reset. */
1674         pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1675         PM8001_INIT_DBG(pm8001_ha,
1676                 pm8001_printk("SPC soft reset Complete\n"));
1677
1678         /* Check this ..whether delay is required or no */
1679         /* delay 10 usec */
1680         udelay(10);
1681
1682         /* wait for 20 msec until the firmware gets reloaded */
1683         i = 20;
1684         do {
1685                 mdelay(1);
1686         } while ((--i) != 0);
1687
1688         PM8001_INIT_DBG(pm8001_ha,
1689                 pm8001_printk("chip reset finished\n"));
1690 }
1691
1692 /**
1693  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1694  * @pm8001_ha: our hba card information
1695  */
1696 static void
1697 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1698 {
1699         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1700         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1701 }
1702
1703 /**
1704  * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1705  * @pm8001_ha: our hba card information
1706  */
1707 static void
1708 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1709 {
1710         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1711 }
1712
1713 /**
1714  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1715  * @pm8001_ha: our hba card information
1716  * @vec: interrupt number to enable
1717  */
1718 static void
1719 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1720 {
1721 #ifdef PM8001_USE_MSIX
1722         u32 mask;
1723         mask = (u32)(1 << vec);
1724
1725         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1726         return;
1727 #endif
1728         pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1729
1730 }
1731
1732 /**
1733  * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1734  * @pm8001_ha: our hba card information
1735  * @vec: interrupt number to disable
1736  */
1737 static void
1738 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1739 {
1740 #ifdef PM8001_USE_MSIX
1741         u32 mask;
1742         if (vec == 0xFF)
1743                 mask = 0xFFFFFFFF;
1744         else
1745                 mask = (u32)(1 << vec);
1746         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1747         return;
1748 #endif
1749         pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1750 }
1751
1752 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1753                 struct pm8001_device *pm8001_ha_dev)
1754 {
1755         int res;
1756         u32 ccb_tag;
1757         struct pm8001_ccb_info *ccb;
1758         struct sas_task *task = NULL;
1759         struct task_abort_req task_abort;
1760         struct inbound_queue_table *circularQ;
1761         u32 opc = OPC_INB_SATA_ABORT;
1762         int ret;
1763
1764         if (!pm8001_ha_dev) {
1765                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1766                 return;
1767         }
1768
1769         task = sas_alloc_slow_task(GFP_ATOMIC);
1770
1771         if (!task) {
1772                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1773                                                 "allocate task\n"));
1774                 return;
1775         }
1776
1777         task->task_done = pm8001_task_done;
1778
1779         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1780         if (res) {
1781                 sas_free_task(task);
1782                 return;
1783         }
1784
1785         ccb = &pm8001_ha->ccb_info[ccb_tag];
1786         ccb->device = pm8001_ha_dev;
1787         ccb->ccb_tag = ccb_tag;
1788         ccb->task = task;
1789
1790         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1791
1792         memset(&task_abort, 0, sizeof(task_abort));
1793         task_abort.abort_all = cpu_to_le32(1);
1794         task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1795         task_abort.tag = cpu_to_le32(ccb_tag);
1796
1797         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
1798                         sizeof(task_abort), 0);
1799         PM8001_FAIL_DBG(pm8001_ha,
1800                 pm8001_printk("Executing abort task end\n"));
1801         if (ret) {
1802                 sas_free_task(task);
1803                 pm8001_tag_free(pm8001_ha, ccb_tag);
1804         }
1805 }
1806
1807 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1808                 struct pm8001_device *pm8001_ha_dev)
1809 {
1810         struct sata_start_req sata_cmd;
1811         int res;
1812         u32 ccb_tag;
1813         struct pm8001_ccb_info *ccb;
1814         struct sas_task *task = NULL;
1815         struct host_to_dev_fis fis;
1816         struct domain_device *dev;
1817         struct inbound_queue_table *circularQ;
1818         u32 opc = OPC_INB_SATA_HOST_OPSTART;
1819
1820         task = sas_alloc_slow_task(GFP_ATOMIC);
1821
1822         if (!task) {
1823                 PM8001_FAIL_DBG(pm8001_ha,
1824                         pm8001_printk("cannot allocate task !!!\n"));
1825                 return;
1826         }
1827         task->task_done = pm8001_task_done;
1828
1829         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1830         if (res) {
1831                 sas_free_task(task);
1832                 PM8001_FAIL_DBG(pm8001_ha,
1833                         pm8001_printk("cannot allocate tag !!!\n"));
1834                 return;
1835         }
1836
1837         /* allocate domain device by ourselves as libsas
1838          * is not going to provide any
1839         */
1840         dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1841         if (!dev) {
1842                 sas_free_task(task);
1843                 pm8001_tag_free(pm8001_ha, ccb_tag);
1844                 PM8001_FAIL_DBG(pm8001_ha,
1845                         pm8001_printk("Domain device cannot be allocated\n"));
1846                 return;
1847         }
1848
1849         task->dev = dev;
1850         task->dev->lldd_dev = pm8001_ha_dev;
1851
1852         ccb = &pm8001_ha->ccb_info[ccb_tag];
1853         ccb->device = pm8001_ha_dev;
1854         ccb->ccb_tag = ccb_tag;
1855         ccb->task = task;
1856         ccb->n_elem = 0;
1857         pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1858         pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1859
1860         memset(&sata_cmd, 0, sizeof(sata_cmd));
1861         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1862
1863         /* construct read log FIS */
1864         memset(&fis, 0, sizeof(struct host_to_dev_fis));
1865         fis.fis_type = 0x27;
1866         fis.flags = 0x80;
1867         fis.command = ATA_CMD_READ_LOG_EXT;
1868         fis.lbal = 0x10;
1869         fis.sector_count = 0x1;
1870
1871         sata_cmd.tag = cpu_to_le32(ccb_tag);
1872         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1873         sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
1874         memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1875
1876         res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
1877                         sizeof(sata_cmd), 0);
1878         PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Executing read log end\n"));
1879         if (res) {
1880                 sas_free_task(task);
1881                 pm8001_tag_free(pm8001_ha, ccb_tag);
1882                 kfree(dev);
1883         }
1884 }
1885
1886 /**
1887  * mpi_ssp_completion- process the event that FW response to the SSP request.
1888  * @pm8001_ha: our hba card information
1889  * @piomb: the message contents of this outbound message.
1890  *
1891  * When FW has completed a ssp request for example a IO request, after it has
1892  * filled the SG data with the data, it will trigger this event represent
1893  * that he has finished the job,please check the coresponding buffer.
1894  * So we will tell the caller who maybe waiting the result to tell upper layer
1895  * that the task has been finished.
1896  */
1897 static void
1898 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1899 {
1900         struct sas_task *t;
1901         struct pm8001_ccb_info *ccb;
1902         unsigned long flags;
1903         u32 status;
1904         u32 param;
1905         u32 tag;
1906         struct ssp_completion_resp *psspPayload;
1907         struct task_status_struct *ts;
1908         struct ssp_response_iu *iu;
1909         struct pm8001_device *pm8001_dev;
1910         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1911         status = le32_to_cpu(psspPayload->status);
1912         tag = le32_to_cpu(psspPayload->tag);
1913         ccb = &pm8001_ha->ccb_info[tag];
1914         if ((status == IO_ABORTED) && ccb->open_retry) {
1915                 /* Being completed by another */
1916                 ccb->open_retry = 0;
1917                 return;
1918         }
1919         pm8001_dev = ccb->device;
1920         param = le32_to_cpu(psspPayload->param);
1921         t = ccb->task;
1922
1923         if (status && status != IO_UNDERFLOW)
1924                 PM8001_FAIL_DBG(pm8001_ha,
1925                         pm8001_printk("sas IO status 0x%x\n", status));
1926         if (unlikely(!t || !t->lldd_task || !t->dev))
1927                 return;
1928         ts = &t->task_status;
1929
1930         PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
1931                 "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t));
1932
1933         /* Print sas address of IO failed device */
1934         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1935                 (status != IO_UNDERFLOW))
1936                 PM8001_FAIL_DBG(pm8001_ha,
1937                         pm8001_printk("SAS Address of IO Failure Drive"
1938                         ":%016llx", SAS_ADDR(t->dev->sas_addr)));
1939
1940         switch (status) {
1941         case IO_SUCCESS:
1942                 PM8001_IO_DBG(pm8001_ha,
1943                         pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1944                                 param));
1945                 if (param == 0) {
1946                         ts->resp = SAS_TASK_COMPLETE;
1947                         ts->stat = SAM_STAT_GOOD;
1948                 } else {
1949                         ts->resp = SAS_TASK_COMPLETE;
1950                         ts->stat = SAS_PROTO_RESPONSE;
1951                         ts->residual = param;
1952                         iu = &psspPayload->ssp_resp_iu;
1953                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1954                 }
1955                 if (pm8001_dev)
1956                         pm8001_dev->running_req--;
1957                 break;
1958         case IO_ABORTED:
1959                 PM8001_IO_DBG(pm8001_ha,
1960                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
1961                 ts->resp = SAS_TASK_COMPLETE;
1962                 ts->stat = SAS_ABORTED_TASK;
1963                 break;
1964         case IO_UNDERFLOW:
1965                 /* SSP Completion with error */
1966                 PM8001_IO_DBG(pm8001_ha,
1967                         pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1968                                 param));
1969                 ts->resp = SAS_TASK_COMPLETE;
1970                 ts->stat = SAS_DATA_UNDERRUN;
1971                 ts->residual = param;
1972                 if (pm8001_dev)
1973                         pm8001_dev->running_req--;
1974                 break;
1975         case IO_NO_DEVICE:
1976                 PM8001_IO_DBG(pm8001_ha,
1977                         pm8001_printk("IO_NO_DEVICE\n"));
1978                 ts->resp = SAS_TASK_UNDELIVERED;
1979                 ts->stat = SAS_PHY_DOWN;
1980                 break;
1981         case IO_XFER_ERROR_BREAK:
1982                 PM8001_IO_DBG(pm8001_ha,
1983                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1984                 ts->resp = SAS_TASK_COMPLETE;
1985                 ts->stat = SAS_OPEN_REJECT;
1986                 /* Force the midlayer to retry */
1987                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1988                 break;
1989         case IO_XFER_ERROR_PHY_NOT_READY:
1990                 PM8001_IO_DBG(pm8001_ha,
1991                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1992                 ts->resp = SAS_TASK_COMPLETE;
1993                 ts->stat = SAS_OPEN_REJECT;
1994                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1995                 break;
1996         case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
1997                 PM8001_IO_DBG(pm8001_ha,
1998                         pm8001_printk("IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n"));
1999                 ts->resp = SAS_TASK_COMPLETE;
2000                 ts->stat = SAS_OPEN_REJECT;
2001                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2002                 break;
2003         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2004                 PM8001_IO_DBG(pm8001_ha,
2005                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2006                 ts->resp = SAS_TASK_COMPLETE;
2007                 ts->stat = SAS_OPEN_REJECT;
2008                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2009                 break;
2010         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2011                 PM8001_IO_DBG(pm8001_ha,
2012                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2013                 ts->resp = SAS_TASK_COMPLETE;
2014                 ts->stat = SAS_OPEN_REJECT;
2015                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2016                 break;
2017         case IO_OPEN_CNX_ERROR_BREAK:
2018                 PM8001_IO_DBG(pm8001_ha,
2019                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2020                 ts->resp = SAS_TASK_COMPLETE;
2021                 ts->stat = SAS_OPEN_REJECT;
2022                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2023                 break;
2024         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2025         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2026         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2027         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2028         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2029         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2030                 PM8001_IO_DBG(pm8001_ha,
2031                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2032                 ts->resp = SAS_TASK_COMPLETE;
2033                 ts->stat = SAS_OPEN_REJECT;
2034                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2035                 if (!t->uldd_task)
2036                         pm8001_handle_event(pm8001_ha,
2037                                 pm8001_dev,
2038                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2039                 break;
2040         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2041                 PM8001_IO_DBG(pm8001_ha,
2042                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2043                 ts->resp = SAS_TASK_COMPLETE;
2044                 ts->stat = SAS_OPEN_REJECT;
2045                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2046                 break;
2047         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2048                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2049                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2050                 ts->resp = SAS_TASK_COMPLETE;
2051                 ts->stat = SAS_OPEN_REJECT;
2052                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2053                 break;
2054         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2055                 PM8001_IO_DBG(pm8001_ha,
2056                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2057                 ts->resp = SAS_TASK_UNDELIVERED;
2058                 ts->stat = SAS_OPEN_REJECT;
2059                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2060                 break;
2061         case IO_XFER_ERROR_NAK_RECEIVED:
2062                 PM8001_IO_DBG(pm8001_ha,
2063                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2064                 ts->resp = SAS_TASK_COMPLETE;
2065                 ts->stat = SAS_OPEN_REJECT;
2066                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2067                 break;
2068         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2069                 PM8001_IO_DBG(pm8001_ha,
2070                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2071                 ts->resp = SAS_TASK_COMPLETE;
2072                 ts->stat = SAS_NAK_R_ERR;
2073                 break;
2074         case IO_XFER_ERROR_DMA:
2075                 PM8001_IO_DBG(pm8001_ha,
2076                 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2077                 ts->resp = SAS_TASK_COMPLETE;
2078                 ts->stat = SAS_OPEN_REJECT;
2079                 break;
2080         case IO_XFER_OPEN_RETRY_TIMEOUT:
2081                 PM8001_IO_DBG(pm8001_ha,
2082                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2083                 ts->resp = SAS_TASK_COMPLETE;
2084                 ts->stat = SAS_OPEN_REJECT;
2085                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2086                 break;
2087         case IO_XFER_ERROR_OFFSET_MISMATCH:
2088                 PM8001_IO_DBG(pm8001_ha,
2089                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2090                 ts->resp = SAS_TASK_COMPLETE;
2091                 ts->stat = SAS_OPEN_REJECT;
2092                 break;
2093         case IO_PORT_IN_RESET:
2094                 PM8001_IO_DBG(pm8001_ha,
2095                         pm8001_printk("IO_PORT_IN_RESET\n"));
2096                 ts->resp = SAS_TASK_COMPLETE;
2097                 ts->stat = SAS_OPEN_REJECT;
2098                 break;
2099         case IO_DS_NON_OPERATIONAL:
2100                 PM8001_IO_DBG(pm8001_ha,
2101                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2102                 ts->resp = SAS_TASK_COMPLETE;
2103                 ts->stat = SAS_OPEN_REJECT;
2104                 if (!t->uldd_task)
2105                         pm8001_handle_event(pm8001_ha,
2106                                 pm8001_dev,
2107                                 IO_DS_NON_OPERATIONAL);
2108                 break;
2109         case IO_DS_IN_RECOVERY:
2110                 PM8001_IO_DBG(pm8001_ha,
2111                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2112                 ts->resp = SAS_TASK_COMPLETE;
2113                 ts->stat = SAS_OPEN_REJECT;
2114                 break;
2115         case IO_TM_TAG_NOT_FOUND:
2116                 PM8001_IO_DBG(pm8001_ha,
2117                         pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
2118                 ts->resp = SAS_TASK_COMPLETE;
2119                 ts->stat = SAS_OPEN_REJECT;
2120                 break;
2121         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2122                 PM8001_IO_DBG(pm8001_ha,
2123                         pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
2124                 ts->resp = SAS_TASK_COMPLETE;
2125                 ts->stat = SAS_OPEN_REJECT;
2126                 break;
2127         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2128                 PM8001_IO_DBG(pm8001_ha,
2129                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2130                 ts->resp = SAS_TASK_COMPLETE;
2131                 ts->stat = SAS_OPEN_REJECT;
2132                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2133                 break;
2134         default:
2135                 PM8001_DEVIO_DBG(pm8001_ha,
2136                         pm8001_printk("Unknown status 0x%x\n", status));
2137                 /* not allowed case. Therefore, return failed status */
2138                 ts->resp = SAS_TASK_COMPLETE;
2139                 ts->stat = SAS_OPEN_REJECT;
2140                 break;
2141         }
2142         PM8001_IO_DBG(pm8001_ha,
2143                 pm8001_printk("scsi_status = 0x%x\n ",
2144                 psspPayload->ssp_resp_iu.status));
2145         spin_lock_irqsave(&t->task_state_lock, flags);
2146         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2147         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2148         t->task_state_flags |= SAS_TASK_STATE_DONE;
2149         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2150                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2151                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2152                         "task 0x%p done with io_status 0x%x resp 0x%x "
2153                         "stat 0x%x but aborted by upper layer!\n",
2154                         t, status, ts->resp, ts->stat));
2155                 if (t->slow_task)
2156                         complete(&t->slow_task->completion);
2157                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2158         } else {
2159                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2160                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2161                 mb();/* in order to force CPU ordering */
2162                 t->task_done(t);
2163         }
2164 }
2165
2166 /*See the comments for mpi_ssp_completion */
2167 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2168 {
2169         struct sas_task *t;
2170         unsigned long flags;
2171         struct task_status_struct *ts;
2172         struct pm8001_ccb_info *ccb;
2173         struct pm8001_device *pm8001_dev;
2174         struct ssp_event_resp *psspPayload =
2175                 (struct ssp_event_resp *)(piomb + 4);
2176         u32 event = le32_to_cpu(psspPayload->event);
2177         u32 tag = le32_to_cpu(psspPayload->tag);
2178         u32 port_id = le32_to_cpu(psspPayload->port_id);
2179
2180         ccb = &pm8001_ha->ccb_info[tag];
2181         t = ccb->task;
2182         pm8001_dev = ccb->device;
2183         if (event)
2184                 PM8001_FAIL_DBG(pm8001_ha,
2185                         pm8001_printk("sas IO status 0x%x\n", event));
2186         if (unlikely(!t || !t->lldd_task || !t->dev))
2187                 return;
2188         ts = &t->task_status;
2189         PM8001_IOERR_DBG(pm8001_ha,
2190                 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2191                                 port_id, tag, event));
2192         switch (event) {
2193         case IO_OVERFLOW:
2194                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
2195                 ts->resp = SAS_TASK_COMPLETE;
2196                 ts->stat = SAS_DATA_OVERRUN;
2197                 ts->residual = 0;
2198                 if (pm8001_dev)
2199                         pm8001_dev->running_req--;
2200                 break;
2201         case IO_XFER_ERROR_BREAK:
2202                 PM8001_IO_DBG(pm8001_ha,
2203                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2204                 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2205                 return;
2206         case IO_XFER_ERROR_PHY_NOT_READY:
2207                 PM8001_IO_DBG(pm8001_ha,
2208                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2209                 ts->resp = SAS_TASK_COMPLETE;
2210                 ts->stat = SAS_OPEN_REJECT;
2211                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2212                 break;
2213         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2214                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2215                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2216                 ts->resp = SAS_TASK_COMPLETE;
2217                 ts->stat = SAS_OPEN_REJECT;
2218                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2219                 break;
2220         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2221                 PM8001_IO_DBG(pm8001_ha,
2222                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2223                 ts->resp = SAS_TASK_COMPLETE;
2224                 ts->stat = SAS_OPEN_REJECT;
2225                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2226                 break;
2227         case IO_OPEN_CNX_ERROR_BREAK:
2228                 PM8001_IO_DBG(pm8001_ha,
2229                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2230                 ts->resp = SAS_TASK_COMPLETE;
2231                 ts->stat = SAS_OPEN_REJECT;
2232                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2233                 break;
2234         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2235         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2236         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2237         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2238         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2239         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2240                 PM8001_IO_DBG(pm8001_ha,
2241                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2242                 ts->resp = SAS_TASK_COMPLETE;
2243                 ts->stat = SAS_OPEN_REJECT;
2244                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2245                 if (!t->uldd_task)
2246                         pm8001_handle_event(pm8001_ha,
2247                                 pm8001_dev,
2248                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2249                 break;
2250         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2251                 PM8001_IO_DBG(pm8001_ha,
2252                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2253                 ts->resp = SAS_TASK_COMPLETE;
2254                 ts->stat = SAS_OPEN_REJECT;
2255                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2256                 break;
2257         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2258                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2259                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2260                 ts->resp = SAS_TASK_COMPLETE;
2261                 ts->stat = SAS_OPEN_REJECT;
2262                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2263                 break;
2264         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2265                 PM8001_IO_DBG(pm8001_ha,
2266                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2267                 ts->resp = SAS_TASK_COMPLETE;
2268                 ts->stat = SAS_OPEN_REJECT;
2269                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2270                 break;
2271         case IO_XFER_ERROR_NAK_RECEIVED:
2272                 PM8001_IO_DBG(pm8001_ha,
2273                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2274                 ts->resp = SAS_TASK_COMPLETE;
2275                 ts->stat = SAS_OPEN_REJECT;
2276                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2277                 break;
2278         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2279                 PM8001_IO_DBG(pm8001_ha,
2280                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2281                 ts->resp = SAS_TASK_COMPLETE;
2282                 ts->stat = SAS_NAK_R_ERR;
2283                 break;
2284         case IO_XFER_OPEN_RETRY_TIMEOUT:
2285                 PM8001_IO_DBG(pm8001_ha,
2286                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2287                 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2288                 return;
2289         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2290                 PM8001_IO_DBG(pm8001_ha,
2291                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2292                 ts->resp = SAS_TASK_COMPLETE;
2293                 ts->stat = SAS_DATA_OVERRUN;
2294                 break;
2295         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2296                 PM8001_IO_DBG(pm8001_ha,
2297                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2298                 ts->resp = SAS_TASK_COMPLETE;
2299                 ts->stat = SAS_DATA_OVERRUN;
2300                 break;
2301         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2302                 PM8001_IO_DBG(pm8001_ha,
2303                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2304                 ts->resp = SAS_TASK_COMPLETE;
2305                 ts->stat = SAS_DATA_OVERRUN;
2306                 break;
2307         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2308                 PM8001_IO_DBG(pm8001_ha,
2309                 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
2310                 ts->resp = SAS_TASK_COMPLETE;
2311                 ts->stat = SAS_DATA_OVERRUN;
2312                 break;
2313         case IO_XFER_ERROR_OFFSET_MISMATCH:
2314                 PM8001_IO_DBG(pm8001_ha,
2315                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2316                 ts->resp = SAS_TASK_COMPLETE;
2317                 ts->stat = SAS_DATA_OVERRUN;
2318                 break;
2319         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2320                 PM8001_IO_DBG(pm8001_ha,
2321                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2322                 ts->resp = SAS_TASK_COMPLETE;
2323                 ts->stat = SAS_DATA_OVERRUN;
2324                 break;
2325         case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2326                 PM8001_IOERR_DBG(pm8001_ha,
2327                         pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2328                 /* TBC: used default set values */
2329                 ts->resp = SAS_TASK_COMPLETE;
2330                 ts->stat = SAS_DATA_OVERRUN;
2331                 break;
2332         case IO_XFER_CMD_FRAME_ISSUED:
2333                 PM8001_IO_DBG(pm8001_ha,
2334                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2335                 return;
2336         default:
2337                 PM8001_DEVIO_DBG(pm8001_ha,
2338                         pm8001_printk("Unknown status 0x%x\n", event));
2339                 /* not allowed case. Therefore, return failed status */
2340                 ts->resp = SAS_TASK_COMPLETE;
2341                 ts->stat = SAS_DATA_OVERRUN;
2342                 break;
2343         }
2344         spin_lock_irqsave(&t->task_state_lock, flags);
2345         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2346         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2347         t->task_state_flags |= SAS_TASK_STATE_DONE;
2348         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2349                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2350                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2351                         "task 0x%p done with event 0x%x resp 0x%x "
2352                         "stat 0x%x but aborted by upper layer!\n",
2353                         t, event, ts->resp, ts->stat));
2354                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2355         } else {
2356                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2357                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2358                 mb();/* in order to force CPU ordering */
2359                 t->task_done(t);
2360         }
2361 }
2362
2363 /*See the comments for mpi_ssp_completion */
2364 static void
2365 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2366 {
2367         struct sas_task *t;
2368         struct pm8001_ccb_info *ccb;
2369         u32 param;
2370         u32 status;
2371         u32 tag;
2372         int i, j;
2373         u8 sata_addr_low[4];
2374         u32 temp_sata_addr_low, temp_sata_addr_hi;
2375         u8 sata_addr_hi[4];
2376         struct sata_completion_resp *psataPayload;
2377         struct task_status_struct *ts;
2378         struct ata_task_resp *resp ;
2379         u32 *sata_resp;
2380         struct pm8001_device *pm8001_dev;
2381         unsigned long flags;
2382
2383         psataPayload = (struct sata_completion_resp *)(piomb + 4);
2384         status = le32_to_cpu(psataPayload->status);
2385         tag = le32_to_cpu(psataPayload->tag);
2386
2387         if (!tag) {
2388                 PM8001_FAIL_DBG(pm8001_ha,
2389                         pm8001_printk("tag null\n"));
2390                 return;
2391         }
2392         ccb = &pm8001_ha->ccb_info[tag];
2393         param = le32_to_cpu(psataPayload->param);
2394         if (ccb) {
2395                 t = ccb->task;
2396                 pm8001_dev = ccb->device;
2397         } else {
2398                 PM8001_FAIL_DBG(pm8001_ha,
2399                         pm8001_printk("ccb null\n"));
2400                 return;
2401         }
2402
2403         if (t) {
2404                 if (t->dev && (t->dev->lldd_dev))
2405                         pm8001_dev = t->dev->lldd_dev;
2406         } else {
2407                 PM8001_FAIL_DBG(pm8001_ha,
2408                         pm8001_printk("task null\n"));
2409                 return;
2410         }
2411
2412         if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2413                 && unlikely(!t || !t->lldd_task || !t->dev)) {
2414                 PM8001_FAIL_DBG(pm8001_ha,
2415                         pm8001_printk("task or dev null\n"));
2416                 return;
2417         }
2418
2419         ts = &t->task_status;
2420         if (!ts) {
2421                 PM8001_FAIL_DBG(pm8001_ha,
2422                         pm8001_printk("ts null\n"));
2423                 return;
2424         }
2425
2426         if (unlikely(status))
2427                 PM8001_IOERR_DBG(pm8001_ha, pm8001_printk(
2428                         "status:0x%x, tag:0x%x, task::0x%p\n",
2429                         status, tag, t));
2430
2431         /* Print sas address of IO failed device */
2432         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2433                 (status != IO_UNDERFLOW)) {
2434                 if (!((t->dev->parent) &&
2435                         (dev_is_expander(t->dev->parent->dev_type)))) {
2436                         for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
2437                                 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2438                         for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
2439                                 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2440                         memcpy(&temp_sata_addr_low, sata_addr_low,
2441                                 sizeof(sata_addr_low));
2442                         memcpy(&temp_sata_addr_hi, sata_addr_hi,
2443                                 sizeof(sata_addr_hi));
2444                         temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2445                                                 |((temp_sata_addr_hi << 8) &
2446                                                 0xff0000) |
2447                                                 ((temp_sata_addr_hi >> 8)
2448                                                 & 0xff00) |
2449                                                 ((temp_sata_addr_hi << 24) &
2450                                                 0xff000000));
2451                         temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2452                                                 & 0xff) |
2453                                                 ((temp_sata_addr_low << 8)
2454                                                 & 0xff0000) |
2455                                                 ((temp_sata_addr_low >> 8)
2456                                                 & 0xff00) |
2457                                                 ((temp_sata_addr_low << 24)
2458                                                 & 0xff000000)) +
2459                                                 pm8001_dev->attached_phy +
2460                                                 0x10);
2461                         PM8001_FAIL_DBG(pm8001_ha,
2462                                 pm8001_printk("SAS Address of IO Failure Drive:"
2463                                 "%08x%08x", temp_sata_addr_hi,
2464                                         temp_sata_addr_low));
2465
2466                 } else {
2467                         PM8001_FAIL_DBG(pm8001_ha,
2468                                 pm8001_printk("SAS Address of IO Failure Drive:"
2469                                 "%016llx", SAS_ADDR(t->dev->sas_addr)));
2470                 }
2471         }
2472         switch (status) {
2473         case IO_SUCCESS:
2474                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2475                 if (param == 0) {
2476                         ts->resp = SAS_TASK_COMPLETE;
2477                         ts->stat = SAM_STAT_GOOD;
2478                         /* check if response is for SEND READ LOG */
2479                         if (pm8001_dev &&
2480                                 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2481                                 /* set new bit for abort_all */
2482                                 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2483                                 /* clear bit for read log */
2484                                 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2485                                 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2486                                 /* Free the tag */
2487                                 pm8001_tag_free(pm8001_ha, tag);
2488                                 sas_free_task(t);
2489                                 return;
2490                         }
2491                 } else {
2492                         u8 len;
2493                         ts->resp = SAS_TASK_COMPLETE;
2494                         ts->stat = SAS_PROTO_RESPONSE;
2495                         ts->residual = param;
2496                         PM8001_IO_DBG(pm8001_ha,
2497                                 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2498                                 param));
2499                         sata_resp = &psataPayload->sata_resp[0];
2500                         resp = (struct ata_task_resp *)ts->buf;
2501                         if (t->ata_task.dma_xfer == 0 &&
2502                             t->data_dir == DMA_FROM_DEVICE) {
2503                                 len = sizeof(struct pio_setup_fis);
2504                                 PM8001_IO_DBG(pm8001_ha,
2505                                 pm8001_printk("PIO read len = %d\n", len));
2506                         } else if (t->ata_task.use_ncq) {
2507                                 len = sizeof(struct set_dev_bits_fis);
2508                                 PM8001_IO_DBG(pm8001_ha,
2509                                         pm8001_printk("FPDMA len = %d\n", len));
2510                         } else {
2511                                 len = sizeof(struct dev_to_host_fis);
2512                                 PM8001_IO_DBG(pm8001_ha,
2513                                 pm8001_printk("other len = %d\n", len));
2514                         }
2515                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2516                                 resp->frame_len = len;
2517                                 memcpy(&resp->ending_fis[0], sata_resp, len);
2518                                 ts->buf_valid_size = sizeof(*resp);
2519                         } else
2520                                 PM8001_IO_DBG(pm8001_ha,
2521                                         pm8001_printk("response too large\n"));
2522                 }
2523                 if (pm8001_dev)
2524                         pm8001_dev->running_req--;
2525                 break;
2526         case IO_ABORTED:
2527                 PM8001_IO_DBG(pm8001_ha,
2528                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
2529                 ts->resp = SAS_TASK_COMPLETE;
2530                 ts->stat = SAS_ABORTED_TASK;
2531                 if (pm8001_dev)
2532                         pm8001_dev->running_req--;
2533                 break;
2534                 /* following cases are to do cases */
2535         case IO_UNDERFLOW:
2536                 /* SATA Completion with error */
2537                 PM8001_IO_DBG(pm8001_ha,
2538                         pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2539                 ts->resp = SAS_TASK_COMPLETE;
2540                 ts->stat = SAS_DATA_UNDERRUN;
2541                 ts->residual = param;
2542                 if (pm8001_dev)
2543                         pm8001_dev->running_req--;
2544                 break;
2545         case IO_NO_DEVICE:
2546                 PM8001_IO_DBG(pm8001_ha,
2547                         pm8001_printk("IO_NO_DEVICE\n"));
2548                 ts->resp = SAS_TASK_UNDELIVERED;
2549                 ts->stat = SAS_PHY_DOWN;
2550                 break;
2551         case IO_XFER_ERROR_BREAK:
2552                 PM8001_IO_DBG(pm8001_ha,
2553                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2554                 ts->resp = SAS_TASK_COMPLETE;
2555                 ts->stat = SAS_INTERRUPTED;
2556                 break;
2557         case IO_XFER_ERROR_PHY_NOT_READY:
2558                 PM8001_IO_DBG(pm8001_ha,
2559                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2560                 ts->resp = SAS_TASK_COMPLETE;
2561                 ts->stat = SAS_OPEN_REJECT;
2562                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2563                 break;
2564         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2565                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2566                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2567                 ts->resp = SAS_TASK_COMPLETE;
2568                 ts->stat = SAS_OPEN_REJECT;
2569                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2570                 break;
2571         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2572                 PM8001_IO_DBG(pm8001_ha,
2573                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2574                 ts->resp = SAS_TASK_COMPLETE;
2575                 ts->stat = SAS_OPEN_REJECT;
2576                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2577                 break;
2578         case IO_OPEN_CNX_ERROR_BREAK:
2579                 PM8001_IO_DBG(pm8001_ha,
2580                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2581                 ts->resp = SAS_TASK_COMPLETE;
2582                 ts->stat = SAS_OPEN_REJECT;
2583                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2584                 break;
2585         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2586         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2587         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2588         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2589         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2590         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2591                 PM8001_IO_DBG(pm8001_ha,
2592                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2593                 ts->resp = SAS_TASK_COMPLETE;
2594                 ts->stat = SAS_DEV_NO_RESPONSE;
2595                 if (!t->uldd_task) {
2596                         pm8001_handle_event(pm8001_ha,
2597                                 pm8001_dev,
2598                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2599                         ts->resp = SAS_TASK_UNDELIVERED;
2600                         ts->stat = SAS_QUEUE_FULL;
2601                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2602                         return;
2603                 }
2604                 break;
2605         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2606                 PM8001_IO_DBG(pm8001_ha,
2607                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2608                 ts->resp = SAS_TASK_UNDELIVERED;
2609                 ts->stat = SAS_OPEN_REJECT;
2610                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2611                 if (!t->uldd_task) {
2612                         pm8001_handle_event(pm8001_ha,
2613                                 pm8001_dev,
2614                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2615                         ts->resp = SAS_TASK_UNDELIVERED;
2616                         ts->stat = SAS_QUEUE_FULL;
2617                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2618                         return;
2619                 }
2620                 break;
2621         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2622                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2623                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2624                 ts->resp = SAS_TASK_COMPLETE;
2625                 ts->stat = SAS_OPEN_REJECT;
2626                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2627                 break;
2628         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2629                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2630                         "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
2631                 ts->resp = SAS_TASK_COMPLETE;
2632                 ts->stat = SAS_DEV_NO_RESPONSE;
2633                 if (!t->uldd_task) {
2634                         pm8001_handle_event(pm8001_ha,
2635                                 pm8001_dev,
2636                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2637                         ts->resp = SAS_TASK_UNDELIVERED;
2638                         ts->stat = SAS_QUEUE_FULL;
2639                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2640                         return;
2641                 }
2642                 break;
2643         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2644                 PM8001_IO_DBG(pm8001_ha,
2645                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2646                 ts->resp = SAS_TASK_COMPLETE;
2647                 ts->stat = SAS_OPEN_REJECT;
2648                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2649                 break;
2650         case IO_XFER_ERROR_NAK_RECEIVED:
2651                 PM8001_IO_DBG(pm8001_ha,
2652                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2653                 ts->resp = SAS_TASK_COMPLETE;
2654                 ts->stat = SAS_NAK_R_ERR;
2655                 break;
2656         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2657                 PM8001_IO_DBG(pm8001_ha,
2658                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2659                 ts->resp = SAS_TASK_COMPLETE;
2660                 ts->stat = SAS_NAK_R_ERR;
2661                 break;
2662         case IO_XFER_ERROR_DMA:
2663                 PM8001_IO_DBG(pm8001_ha,
2664                         pm8001_printk("IO_XFER_ERROR_DMA\n"));
2665                 ts->resp = SAS_TASK_COMPLETE;
2666                 ts->stat = SAS_ABORTED_TASK;
2667                 break;
2668         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2669                 PM8001_IO_DBG(pm8001_ha,
2670                         pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2671                 ts->resp = SAS_TASK_UNDELIVERED;
2672                 ts->stat = SAS_DEV_NO_RESPONSE;
2673                 break;
2674         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2675                 PM8001_IO_DBG(pm8001_ha,
2676                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2677                 ts->resp = SAS_TASK_COMPLETE;
2678                 ts->stat = SAS_DATA_UNDERRUN;
2679                 break;
2680         case IO_XFER_OPEN_RETRY_TIMEOUT:
2681                 PM8001_IO_DBG(pm8001_ha,
2682                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2683                 ts->resp = SAS_TASK_COMPLETE;
2684                 ts->stat = SAS_OPEN_TO;
2685                 break;
2686         case IO_PORT_IN_RESET:
2687                 PM8001_IO_DBG(pm8001_ha,
2688                         pm8001_printk("IO_PORT_IN_RESET\n"));
2689                 ts->resp = SAS_TASK_COMPLETE;
2690                 ts->stat = SAS_DEV_NO_RESPONSE;
2691                 break;
2692         case IO_DS_NON_OPERATIONAL:
2693                 PM8001_IO_DBG(pm8001_ha,
2694                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2695                 ts->resp = SAS_TASK_COMPLETE;
2696                 ts->stat = SAS_DEV_NO_RESPONSE;
2697                 if (!t->uldd_task) {
2698                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2699                                         IO_DS_NON_OPERATIONAL);
2700                         ts->resp = SAS_TASK_UNDELIVERED;
2701                         ts->stat = SAS_QUEUE_FULL;
2702                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2703                         return;
2704                 }
2705                 break;
2706         case IO_DS_IN_RECOVERY:
2707                 PM8001_IO_DBG(pm8001_ha,
2708                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2709                 ts->resp = SAS_TASK_COMPLETE;
2710                 ts->stat = SAS_DEV_NO_RESPONSE;
2711                 break;
2712         case IO_DS_IN_ERROR:
2713                 PM8001_IO_DBG(pm8001_ha,
2714                         pm8001_printk("IO_DS_IN_ERROR\n"));
2715                 ts->resp = SAS_TASK_COMPLETE;
2716                 ts->stat = SAS_DEV_NO_RESPONSE;
2717                 if (!t->uldd_task) {
2718                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2719                                         IO_DS_IN_ERROR);
2720                         ts->resp = SAS_TASK_UNDELIVERED;
2721                         ts->stat = SAS_QUEUE_FULL;
2722                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2723                         return;
2724                 }
2725                 break;
2726         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2727                 PM8001_IO_DBG(pm8001_ha,
2728                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2729                 ts->resp = SAS_TASK_COMPLETE;
2730                 ts->stat = SAS_OPEN_REJECT;
2731                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2732                 break;
2733         default:
2734                 PM8001_DEVIO_DBG(pm8001_ha,
2735                         pm8001_printk("Unknown status 0x%x\n", status));
2736                 /* not allowed case. Therefore, return failed status */
2737                 ts->resp = SAS_TASK_COMPLETE;
2738                 ts->stat = SAS_DEV_NO_RESPONSE;
2739                 break;
2740         }
2741         spin_lock_irqsave(&t->task_state_lock, flags);
2742         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2743         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2744         t->task_state_flags |= SAS_TASK_STATE_DONE;
2745         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2746                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2747                 PM8001_FAIL_DBG(pm8001_ha,
2748                         pm8001_printk("task 0x%p done with io_status 0x%x"
2749                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2750                         t, status, ts->resp, ts->stat));
2751                 if (t->slow_task)
2752                         complete(&t->slow_task->completion);
2753                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2754         } else {
2755                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2756                 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2757         }
2758 }
2759
2760 /*See the comments for mpi_ssp_completion */
2761 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2762 {
2763         struct sas_task *t;
2764         struct task_status_struct *ts;
2765         struct pm8001_ccb_info *ccb;
2766         struct pm8001_device *pm8001_dev;
2767         struct sata_event_resp *psataPayload =
2768                 (struct sata_event_resp *)(piomb + 4);
2769         u32 event = le32_to_cpu(psataPayload->event);
2770         u32 tag = le32_to_cpu(psataPayload->tag);
2771         u32 port_id = le32_to_cpu(psataPayload->port_id);
2772         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2773         unsigned long flags;
2774
2775         ccb = &pm8001_ha->ccb_info[tag];
2776
2777         if (ccb) {
2778                 t = ccb->task;
2779                 pm8001_dev = ccb->device;
2780         } else {
2781                 PM8001_FAIL_DBG(pm8001_ha,
2782                         pm8001_printk("No CCB !!!. returning\n"));
2783                 return;
2784         }
2785         if (event)
2786                 PM8001_FAIL_DBG(pm8001_ha,
2787                         pm8001_printk("SATA EVENT 0x%x\n", event));
2788
2789         /* Check if this is NCQ error */
2790         if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2791                 /* find device using device id */
2792                 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2793                 /* send read log extension */
2794                 if (pm8001_dev)
2795                         pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2796                 return;
2797         }
2798
2799         if (unlikely(!t || !t->lldd_task || !t->dev)) {
2800                 PM8001_FAIL_DBG(pm8001_ha,
2801                         pm8001_printk("task or dev null\n"));
2802                 return;
2803         }
2804
2805         ts = &t->task_status;
2806         PM8001_IOERR_DBG(pm8001_ha,
2807                 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2808                                 port_id, tag, event));
2809         switch (event) {
2810         case IO_OVERFLOW:
2811                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2812                 ts->resp = SAS_TASK_COMPLETE;
2813                 ts->stat = SAS_DATA_OVERRUN;
2814                 ts->residual = 0;
2815                 if (pm8001_dev)
2816                         pm8001_dev->running_req--;
2817                 break;
2818         case IO_XFER_ERROR_BREAK:
2819                 PM8001_IO_DBG(pm8001_ha,
2820                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2821                 ts->resp = SAS_TASK_COMPLETE;
2822                 ts->stat = SAS_INTERRUPTED;
2823                 break;
2824         case IO_XFER_ERROR_PHY_NOT_READY:
2825                 PM8001_IO_DBG(pm8001_ha,
2826                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2827                 ts->resp = SAS_TASK_COMPLETE;
2828                 ts->stat = SAS_OPEN_REJECT;
2829                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2830                 break;
2831         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2832                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2833                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2834                 ts->resp = SAS_TASK_COMPLETE;
2835                 ts->stat = SAS_OPEN_REJECT;
2836                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2837                 break;
2838         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2839                 PM8001_IO_DBG(pm8001_ha,
2840                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2841                 ts->resp = SAS_TASK_COMPLETE;
2842                 ts->stat = SAS_OPEN_REJECT;
2843                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2844                 break;
2845         case IO_OPEN_CNX_ERROR_BREAK:
2846                 PM8001_IO_DBG(pm8001_ha,
2847                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2848                 ts->resp = SAS_TASK_COMPLETE;
2849                 ts->stat = SAS_OPEN_REJECT;
2850                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2851                 break;
2852         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2853         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2854         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2855         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2856         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2857         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2858                 PM8001_FAIL_DBG(pm8001_ha,
2859                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2860                 ts->resp = SAS_TASK_UNDELIVERED;
2861                 ts->stat = SAS_DEV_NO_RESPONSE;
2862                 if (!t->uldd_task) {
2863                         pm8001_handle_event(pm8001_ha,
2864                                 pm8001_dev,
2865                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2866                         ts->resp = SAS_TASK_COMPLETE;
2867                         ts->stat = SAS_QUEUE_FULL;
2868                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2869                         return;
2870                 }
2871                 break;
2872         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2873                 PM8001_IO_DBG(pm8001_ha,
2874                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2875                 ts->resp = SAS_TASK_UNDELIVERED;
2876                 ts->stat = SAS_OPEN_REJECT;
2877                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2878                 break;
2879         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2880                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2881                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2882                 ts->resp = SAS_TASK_COMPLETE;
2883                 ts->stat = SAS_OPEN_REJECT;
2884                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2885                 break;
2886         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2887                 PM8001_IO_DBG(pm8001_ha,
2888                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2889                 ts->resp = SAS_TASK_COMPLETE;
2890                 ts->stat = SAS_OPEN_REJECT;
2891                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2892                 break;
2893         case IO_XFER_ERROR_NAK_RECEIVED:
2894                 PM8001_IO_DBG(pm8001_ha,
2895                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2896                 ts->resp = SAS_TASK_COMPLETE;
2897                 ts->stat = SAS_NAK_R_ERR;
2898                 break;
2899         case IO_XFER_ERROR_PEER_ABORTED:
2900                 PM8001_IO_DBG(pm8001_ha,
2901                         pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2902                 ts->resp = SAS_TASK_COMPLETE;
2903                 ts->stat = SAS_NAK_R_ERR;
2904                 break;
2905         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2906                 PM8001_IO_DBG(pm8001_ha,
2907                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2908                 ts->resp = SAS_TASK_COMPLETE;
2909                 ts->stat = SAS_DATA_UNDERRUN;
2910                 break;
2911         case IO_XFER_OPEN_RETRY_TIMEOUT:
2912                 PM8001_IO_DBG(pm8001_ha,
2913                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2914                 ts->resp = SAS_TASK_COMPLETE;
2915                 ts->stat = SAS_OPEN_TO;
2916                 break;
2917         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2918                 PM8001_IO_DBG(pm8001_ha,
2919                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2920                 ts->resp = SAS_TASK_COMPLETE;
2921                 ts->stat = SAS_OPEN_TO;
2922                 break;
2923         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2924                 PM8001_IO_DBG(pm8001_ha,
2925                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2926                 ts->resp = SAS_TASK_COMPLETE;
2927                 ts->stat = SAS_OPEN_TO;
2928                 break;
2929         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2930                 PM8001_IO_DBG(pm8001_ha,
2931                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2932                 ts->resp = SAS_TASK_COMPLETE;
2933                 ts->stat = SAS_OPEN_TO;
2934                 break;
2935         case IO_XFER_ERROR_OFFSET_MISMATCH:
2936                 PM8001_IO_DBG(pm8001_ha,
2937                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2938                 ts->resp = SAS_TASK_COMPLETE;
2939                 ts->stat = SAS_OPEN_TO;
2940                 break;
2941         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2942                 PM8001_IO_DBG(pm8001_ha,
2943                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2944                 ts->resp = SAS_TASK_COMPLETE;
2945                 ts->stat = SAS_OPEN_TO;
2946                 break;
2947         case IO_XFER_CMD_FRAME_ISSUED:
2948                 PM8001_IO_DBG(pm8001_ha,
2949                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2950                 break;
2951         case IO_XFER_PIO_SETUP_ERROR:
2952                 PM8001_IO_DBG(pm8001_ha,
2953                         pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2954                 ts->resp = SAS_TASK_COMPLETE;
2955                 ts->stat = SAS_OPEN_TO;
2956                 break;
2957         case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2958                 PM8001_FAIL_DBG(pm8001_ha,
2959                         pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2960                 /* TBC: used default set values */
2961                 ts->resp = SAS_TASK_COMPLETE;
2962                 ts->stat = SAS_OPEN_TO;
2963                 break;
2964         case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2965                 PM8001_FAIL_DBG(pm8001_ha,
2966                         pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n"));
2967                 /* TBC: used default set values */
2968                 ts->resp = SAS_TASK_COMPLETE;
2969                 ts->stat = SAS_OPEN_TO;
2970                 break;
2971         default:
2972                 PM8001_IO_DBG(pm8001_ha,
2973                         pm8001_printk("Unknown status 0x%x\n", event));
2974                 /* not allowed case. Therefore, return failed status */
2975                 ts->resp = SAS_TASK_COMPLETE;
2976                 ts->stat = SAS_OPEN_TO;
2977                 break;
2978         }
2979         spin_lock_irqsave(&t->task_state_lock, flags);
2980         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2981         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2982         t->task_state_flags |= SAS_TASK_STATE_DONE;
2983         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2984                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2985                 PM8001_FAIL_DBG(pm8001_ha,
2986                         pm8001_printk("task 0x%p done with io_status 0x%x"
2987                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2988                         t, event, ts->resp, ts->stat));
2989                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2990         } else {
2991                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2992                 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2993         }
2994 }
2995
2996 /*See the comments for mpi_ssp_completion */
2997 static void
2998 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2999 {
3000         u32 param, i;
3001         struct sas_task *t;
3002         struct pm8001_ccb_info *ccb;
3003         unsigned long flags;
3004         u32 status;
3005         u32 tag;
3006         struct smp_completion_resp *psmpPayload;
3007         struct task_status_struct *ts;
3008         struct pm8001_device *pm8001_dev;
3009         char *pdma_respaddr = NULL;
3010
3011         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
3012         status = le32_to_cpu(psmpPayload->status);
3013         tag = le32_to_cpu(psmpPayload->tag);
3014
3015         ccb = &pm8001_ha->ccb_info[tag];
3016         param = le32_to_cpu(psmpPayload->param);
3017         t = ccb->task;
3018         ts = &t->task_status;
3019         pm8001_dev = ccb->device;
3020         if (status)
3021                 PM8001_FAIL_DBG(pm8001_ha,
3022                         pm8001_printk("smp IO status 0x%x\n", status));
3023         if (unlikely(!t || !t->lldd_task || !t->dev))
3024                 return;
3025
3026         PM8001_DEV_DBG(pm8001_ha,
3027                 pm8001_printk("tag::0x%x status::0x%x\n", tag, status));
3028
3029         switch (status) {
3030
3031         case IO_SUCCESS:
3032                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3033                 ts->resp = SAS_TASK_COMPLETE;
3034                 ts->stat = SAM_STAT_GOOD;
3035                 if (pm8001_dev)
3036                         pm8001_dev->running_req--;
3037                 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3038                         PM8001_IO_DBG(pm8001_ha,
3039                                 pm8001_printk("DIRECT RESPONSE Length:%d\n",
3040                                                 param));
3041                         pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
3042                                                 ((u64)sg_dma_address
3043                                                 (&t->smp_task.smp_resp))));
3044                         for (i = 0; i < param; i++) {
3045                                 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
3046                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3047                                         "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
3048                                         i, *(pdma_respaddr+i),
3049                                         psmpPayload->_r_a[i]));
3050                         }
3051                 }
3052                 break;
3053         case IO_ABORTED:
3054                 PM8001_IO_DBG(pm8001_ha,
3055                         pm8001_printk("IO_ABORTED IOMB\n"));
3056                 ts->resp = SAS_TASK_COMPLETE;
3057                 ts->stat = SAS_ABORTED_TASK;
3058                 if (pm8001_dev)
3059                         pm8001_dev->running_req--;
3060                 break;
3061         case IO_OVERFLOW:
3062                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
3063                 ts->resp = SAS_TASK_COMPLETE;
3064                 ts->stat = SAS_DATA_OVERRUN;
3065                 ts->residual = 0;
3066                 if (pm8001_dev)
3067                         pm8001_dev->running_req--;
3068                 break;
3069         case IO_NO_DEVICE:
3070                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
3071                 ts->resp = SAS_TASK_COMPLETE;
3072                 ts->stat = SAS_PHY_DOWN;
3073                 break;
3074         case IO_ERROR_HW_TIMEOUT:
3075                 PM8001_IO_DBG(pm8001_ha,
3076                         pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
3077                 ts->resp = SAS_TASK_COMPLETE;
3078                 ts->stat = SAM_STAT_BUSY;
3079                 break;
3080         case IO_XFER_ERROR_BREAK:
3081                 PM8001_IO_DBG(pm8001_ha,
3082                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
3083                 ts->resp = SAS_TASK_COMPLETE;
3084                 ts->stat = SAM_STAT_BUSY;
3085                 break;
3086         case IO_XFER_ERROR_PHY_NOT_READY:
3087                 PM8001_IO_DBG(pm8001_ha,
3088                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
3089                 ts->resp = SAS_TASK_COMPLETE;
3090                 ts->stat = SAM_STAT_BUSY;
3091                 break;
3092         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
3093                 PM8001_IO_DBG(pm8001_ha,
3094                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
3095                 ts->resp = SAS_TASK_COMPLETE;
3096                 ts->stat = SAS_OPEN_REJECT;
3097                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3098                 break;
3099         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
3100                 PM8001_IO_DBG(pm8001_ha,
3101                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
3102                 ts->resp = SAS_TASK_COMPLETE;
3103                 ts->stat = SAS_OPEN_REJECT;
3104                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3105                 break;
3106         case IO_OPEN_CNX_ERROR_BREAK:
3107                 PM8001_IO_DBG(pm8001_ha,
3108                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
3109                 ts->resp = SAS_TASK_COMPLETE;
3110                 ts->stat = SAS_OPEN_REJECT;
3111                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
3112                 break;
3113         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
3114         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
3115         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
3116         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
3117         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
3118         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
3119                 PM8001_IO_DBG(pm8001_ha,
3120                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
3121                 ts->resp = SAS_TASK_COMPLETE;
3122                 ts->stat = SAS_OPEN_REJECT;
3123                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3124                 pm8001_handle_event(pm8001_ha,
3125                                 pm8001_dev,
3126                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
3127                 break;
3128         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
3129                 PM8001_IO_DBG(pm8001_ha,
3130                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
3131                 ts->resp = SAS_TASK_COMPLETE;
3132                 ts->stat = SAS_OPEN_REJECT;
3133                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
3134                 break;
3135         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
3136                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
3137                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
3138                 ts->resp = SAS_TASK_COMPLETE;
3139                 ts->stat = SAS_OPEN_REJECT;
3140                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
3141                 break;
3142         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
3143                 PM8001_IO_DBG(pm8001_ha,
3144                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
3145                 ts->resp = SAS_TASK_COMPLETE;
3146                 ts->stat = SAS_OPEN_REJECT;
3147                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
3148                 break;
3149         case IO_XFER_ERROR_RX_FRAME:
3150                 PM8001_IO_DBG(pm8001_ha,
3151                         pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
3152                 ts->resp = SAS_TASK_COMPLETE;
3153                 ts->stat = SAS_DEV_NO_RESPONSE;
3154                 break;
3155         case IO_XFER_OPEN_RETRY_TIMEOUT:
3156                 PM8001_IO_DBG(pm8001_ha,
3157                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
3158                 ts->resp = SAS_TASK_COMPLETE;
3159                 ts->stat = SAS_OPEN_REJECT;
3160                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3161                 break;
3162         case IO_ERROR_INTERNAL_SMP_RESOURCE:
3163                 PM8001_IO_DBG(pm8001_ha,
3164                         pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
3165                 ts->resp = SAS_TASK_COMPLETE;
3166                 ts->stat = SAS_QUEUE_FULL;
3167                 break;
3168         case IO_PORT_IN_RESET:
3169                 PM8001_IO_DBG(pm8001_ha,
3170                         pm8001_printk("IO_PORT_IN_RESET\n"));
3171                 ts->resp = SAS_TASK_COMPLETE;
3172                 ts->stat = SAS_OPEN_REJECT;
3173                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3174                 break;
3175         case IO_DS_NON_OPERATIONAL:
3176                 PM8001_IO_DBG(pm8001_ha,
3177                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
3178                 ts->resp = SAS_TASK_COMPLETE;
3179                 ts->stat = SAS_DEV_NO_RESPONSE;
3180                 break;
3181         case IO_DS_IN_RECOVERY:
3182                 PM8001_IO_DBG(pm8001_ha,
3183                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
3184                 ts->resp = SAS_TASK_COMPLETE;
3185                 ts->stat = SAS_OPEN_REJECT;
3186                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3187                 break;
3188         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3189                 PM8001_IO_DBG(pm8001_ha,
3190                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
3191                 ts->resp = SAS_TASK_COMPLETE;
3192                 ts->stat = SAS_OPEN_REJECT;
3193                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3194                 break;
3195         default:
3196                 PM8001_DEVIO_DBG(pm8001_ha,
3197                         pm8001_printk("Unknown status 0x%x\n", status));
3198                 ts->resp = SAS_TASK_COMPLETE;
3199                 ts->stat = SAS_DEV_NO_RESPONSE;
3200                 /* not allowed case. Therefore, return failed status */
3201                 break;
3202         }
3203         spin_lock_irqsave(&t->task_state_lock, flags);
3204         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3205         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3206         t->task_state_flags |= SAS_TASK_STATE_DONE;
3207         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3208                 spin_unlock_irqrestore(&t->task_state_lock, flags);
3209                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
3210                         "task 0x%p done with io_status 0x%x resp 0x%x"
3211                         "stat 0x%x but aborted by upper layer!\n",
3212                         t, status, ts->resp, ts->stat));
3213                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3214         } else {
3215                 spin_unlock_irqrestore(&t->task_state_lock, flags);
3216                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3217                 mb();/* in order to force CPU ordering */
3218                 t->task_done(t);
3219         }
3220 }
3221
3222 /**
3223  * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3224  * @pm8001_ha: our hba card information
3225  * @Qnum: the outbound queue message number.
3226  * @SEA: source of event to ack
3227  * @port_id: port id.
3228  * @phyId: phy id.
3229  * @param0: parameter 0.
3230  * @param1: parameter 1.
3231  */
3232 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3233         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3234 {
3235         struct hw_event_ack_req  payload;
3236         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3237
3238         struct inbound_queue_table *circularQ;
3239
3240         memset((u8 *)&payload, 0, sizeof(payload));
3241         circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3242         payload.tag = cpu_to_le32(1);
3243         payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3244                 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
3245         payload.param0 = cpu_to_le32(param0);
3246         payload.param1 = cpu_to_le32(param1);
3247         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
3248                         sizeof(payload), 0);
3249 }
3250
3251 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3252         u32 phyId, u32 phy_op);
3253
3254 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
3255                                         void *piomb)
3256 {
3257         struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
3258         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3259         u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3260         u32 lr_status_evt_portid =
3261                 le32_to_cpu(pPayload->lr_status_evt_portid);
3262         u8 deviceType = pPayload->sas_identify.dev_type;
3263         u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3264         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3265         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3266         struct pm8001_port *port = &pm8001_ha->port[port_id];
3267
3268         if (deviceType == SAS_END_DEVICE) {
3269                 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3270                                         PHY_NOTIFY_ENABLE_SPINUP);
3271         }
3272
3273         port->wide_port_phymap |= (1U << phy_id);
3274         pm8001_get_lrate_mode(phy, link_rate);
3275         phy->sas_phy.oob_mode = SAS_OOB_MODE;
3276         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3277         phy->phy_attached = 1;
3278 }
3279
3280 /**
3281  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3282  * @pm8001_ha: our hba card information
3283  * @piomb: IO message buffer
3284  */
3285 static void
3286 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3287 {
3288         struct hw_event_resp *pPayload =
3289                 (struct hw_event_resp *)(piomb + 4);
3290         u32 lr_status_evt_portid =
3291                 le32_to_cpu(pPayload->lr_status_evt_portid);
3292         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3293
3294         u8 link_rate =
3295                 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3296         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3297         u8 phy_id =
3298                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3299         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3300
3301         struct pm8001_port *port = &pm8001_ha->port[port_id];
3302         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3303         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3304         unsigned long flags;
3305         u8 deviceType = pPayload->sas_identify.dev_type;
3306         port->port_state = portstate;
3307         port->wide_port_phymap |= (1U << phy_id);
3308         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3309         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3310                 "portid:%d; phyid:%d; linkrate:%d; "
3311                 "portstate:%x; devicetype:%x\n",
3312                 port_id, phy_id, link_rate, portstate, deviceType));
3313
3314         switch (deviceType) {
3315         case SAS_PHY_UNUSED:
3316                 PM8001_MSG_DBG(pm8001_ha,
3317                         pm8001_printk("device type no device.\n"));
3318                 break;
3319         case SAS_END_DEVICE:
3320                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
3321                 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3322                         PHY_NOTIFY_ENABLE_SPINUP);
3323                 port->port_attached = 1;
3324                 pm8001_get_lrate_mode(phy, link_rate);
3325                 break;
3326         case SAS_EDGE_EXPANDER_DEVICE:
3327                 PM8001_MSG_DBG(pm8001_ha,
3328                         pm8001_printk("expander device.\n"));
3329                 port->port_attached = 1;
3330                 pm8001_get_lrate_mode(phy, link_rate);
3331                 break;
3332         case SAS_FANOUT_EXPANDER_DEVICE:
3333                 PM8001_MSG_DBG(pm8001_ha,
3334                         pm8001_printk("fanout expander device.\n"));
3335                 port->port_attached = 1;
3336                 pm8001_get_lrate_mode(phy, link_rate);
3337                 break;
3338         default:
3339                 PM8001_DEVIO_DBG(pm8001_ha,
3340                         pm8001_printk("unknown device type(%x)\n", deviceType));
3341                 break;
3342         }
3343         phy->phy_type |= PORT_TYPE_SAS;
3344         phy->identify.device_type = deviceType;
3345         phy->phy_attached = 1;
3346         if (phy->identify.device_type == SAS_END_DEVICE)
3347                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3348         else if (phy->identify.device_type != SAS_PHY_UNUSED)
3349                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3350         phy->sas_phy.oob_mode = SAS_OOB_MODE;
3351         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3352         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3353         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3354                 sizeof(struct sas_identify_frame)-4);
3355         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3356         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3357         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3358         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3359                 msleep(200);/*delay a moment to wait disk to spinup*/
3360         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3361 }
3362
3363 /**
3364  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3365  * @pm8001_ha: our hba card information
3366  * @piomb: IO message buffer
3367  */
3368 static void
3369 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3370 {
3371         struct hw_event_resp *pPayload =
3372                 (struct hw_event_resp *)(piomb + 4);
3373         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3374         u32 lr_status_evt_portid =
3375                 le32_to_cpu(pPayload->lr_status_evt_portid);
3376         u8 link_rate =
3377                 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3378         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3379         u8 phy_id =
3380                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3381
3382         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3383
3384         struct pm8001_port *port = &pm8001_ha->port[port_id];
3385         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3386         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3387         unsigned long flags;
3388         PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
3389                 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
3390                                 port_id, phy_id, link_rate, portstate));
3391
3392         port->port_state = portstate;
3393         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3394         port->port_attached = 1;
3395         pm8001_get_lrate_mode(phy, link_rate);
3396         phy->phy_type |= PORT_TYPE_SATA;
3397         phy->phy_attached = 1;
3398         phy->sas_phy.oob_mode = SATA_OOB_MODE;
3399         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3400         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3401         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3402                 sizeof(struct dev_to_host_fis));
3403         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3404         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3405         phy->identify.device_type = SAS_SATA_DEV;
3406         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3407         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3408         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3409 }
3410
3411 /**
3412  * hw_event_phy_down -we should notify the libsas the phy is down.
3413  * @pm8001_ha: our hba card information
3414  * @piomb: IO message buffer
3415  */
3416 static void
3417 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3418 {
3419         struct hw_event_resp *pPayload =
3420                 (struct hw_event_resp *)(piomb + 4);
3421
3422         u32 lr_status_evt_portid =
3423                 le32_to_cpu(pPayload->lr_status_evt_portid);
3424         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3425         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3426         u8 phy_id =
3427                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3428         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3429
3430         struct pm8001_port *port = &pm8001_ha->port[port_id];
3431         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3432         u32 port_sata = (phy->phy_type & PORT_TYPE_SATA);
3433         port->port_state = portstate;
3434         phy->identify.device_type = 0;
3435         phy->phy_attached = 0;
3436         switch (portstate) {
3437         case PORT_VALID:
3438                 break;
3439         case PORT_INVALID:
3440                 PM8001_MSG_DBG(pm8001_ha,
3441                         pm8001_printk(" PortInvalid portID %d\n", port_id));
3442                 PM8001_MSG_DBG(pm8001_ha,
3443                         pm8001_printk(" Last phy Down and port invalid\n"));
3444                 if (port_sata) {
3445                         phy->phy_type = 0;
3446                         port->port_attached = 0;
3447                         pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3448                                         port_id, phy_id, 0, 0);
3449                 }
3450                 sas_phy_disconnected(&phy->sas_phy);
3451                 break;
3452         case PORT_IN_RESET:
3453                 PM8001_MSG_DBG(pm8001_ha,
3454                         pm8001_printk(" Port In Reset portID %d\n", port_id));
3455                 break;
3456         case PORT_NOT_ESTABLISHED:
3457                 PM8001_MSG_DBG(pm8001_ha,
3458                         pm8001_printk(" Phy Down and PORT_NOT_ESTABLISHED\n"));
3459                 port->port_attached = 0;
3460                 break;
3461         case PORT_LOSTCOMM:
3462                 PM8001_MSG_DBG(pm8001_ha,
3463                         pm8001_printk(" Phy Down and PORT_LOSTCOMM\n"));
3464                 PM8001_MSG_DBG(pm8001_ha,
3465                         pm8001_printk(" Last phy Down and port invalid\n"));
3466                 if (port_sata) {
3467                         port->port_attached = 0;
3468                         phy->phy_type = 0;
3469                         pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3470                                         port_id, phy_id, 0, 0);
3471                 }
3472                 sas_phy_disconnected(&phy->sas_phy);
3473                 break;
3474         default:
3475                 port->port_attached = 0;
3476                 PM8001_DEVIO_DBG(pm8001_ha,
3477                         pm8001_printk(" Phy Down and(default) = 0x%x\n",
3478                         portstate));
3479                 break;
3480
3481         }
3482         if (port_sata && (portstate != PORT_IN_RESET)) {
3483                 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3484
3485                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3486         }
3487 }
3488
3489 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3490 {
3491         struct phy_start_resp *pPayload =
3492                 (struct phy_start_resp *)(piomb + 4);
3493         u32 status =
3494                 le32_to_cpu(pPayload->status);
3495         u32 phy_id =
3496                 le32_to_cpu(pPayload->phyid);
3497         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3498
3499         PM8001_INIT_DBG(pm8001_ha,
3500                 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
3501                                 status, phy_id));
3502         if (status == 0) {
3503                 phy->phy_state = PHY_LINK_DOWN;
3504                 if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3505                                 phy->enable_completion != NULL) {
3506                         complete(phy->enable_completion);
3507                         phy->enable_completion = NULL;
3508                 }
3509         }
3510         return 0;
3511
3512 }
3513
3514 /**
3515  * mpi_thermal_hw_event -The hw event has come.
3516  * @pm8001_ha: our hba card information
3517  * @piomb: IO message buffer
3518  */
3519 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3520 {
3521         struct thermal_hw_event *pPayload =
3522                 (struct thermal_hw_event *)(piomb + 4);
3523
3524         u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3525         u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3526
3527         if (thermal_event & 0x40) {
3528                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3529                         "Thermal Event: Local high temperature violated!\n"));
3530                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3531                         "Thermal Event: Measured local high temperature %d\n",
3532                                 ((rht_lht & 0xFF00) >> 8)));
3533         }
3534         if (thermal_event & 0x10) {
3535                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3536                         "Thermal Event: Remote high temperature violated!\n"));
3537                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3538                         "Thermal Event: Measured remote high temperature %d\n",
3539                                 ((rht_lht & 0xFF000000) >> 24)));
3540         }
3541         return 0;
3542 }
3543
3544 /**
3545  * mpi_hw_event -The hw event has come.
3546  * @pm8001_ha: our hba card information
3547  * @piomb: IO message buffer
3548  */
3549 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3550 {
3551         unsigned long flags, i;
3552         struct hw_event_resp *pPayload =
3553                 (struct hw_event_resp *)(piomb + 4);
3554         u32 lr_status_evt_portid =
3555                 le32_to_cpu(pPayload->lr_status_evt_portid);
3556         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3557         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3558         u8 phy_id =
3559                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3560         u16 eventType =
3561                 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3562         u8 status =
3563                 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3564         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3565         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3566         struct pm8001_port *port = &pm8001_ha->port[port_id];
3567         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3568         PM8001_DEV_DBG(pm8001_ha,
3569                 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
3570                                 port_id, phy_id, eventType, status));
3571
3572         switch (eventType) {
3573
3574         case HW_EVENT_SAS_PHY_UP:
3575                 PM8001_MSG_DBG(pm8001_ha,
3576                         pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3577                 hw_event_sas_phy_up(pm8001_ha, piomb);
3578                 break;
3579         case HW_EVENT_SATA_PHY_UP:
3580                 PM8001_MSG_DBG(pm8001_ha,
3581                         pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3582                 hw_event_sata_phy_up(pm8001_ha, piomb);
3583                 break;
3584         case HW_EVENT_SATA_SPINUP_HOLD:
3585                 PM8001_MSG_DBG(pm8001_ha,
3586                         pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3587                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3588                 break;
3589         case HW_EVENT_PHY_DOWN:
3590                 PM8001_MSG_DBG(pm8001_ha,
3591                         pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3592                 hw_event_phy_down(pm8001_ha, piomb);
3593                 if (pm8001_ha->reset_in_progress) {
3594                         PM8001_MSG_DBG(pm8001_ha,
3595                                 pm8001_printk("Reset in progress\n"));
3596                         return 0;
3597                 }
3598                 phy->phy_attached = 0;
3599                 phy->phy_state = PHY_LINK_DISABLE;
3600                 break;
3601         case HW_EVENT_PORT_INVALID:
3602                 PM8001_MSG_DBG(pm8001_ha,
3603                         pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3604                 sas_phy_disconnected(sas_phy);
3605                 phy->phy_attached = 0;
3606                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3607                 break;
3608         /* the broadcast change primitive received, tell the LIBSAS this event
3609         to revalidate the sas domain*/
3610         case HW_EVENT_BROADCAST_CHANGE:
3611                 PM8001_MSG_DBG(pm8001_ha,
3612                         pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3613                 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3614                         port_id, phy_id, 1, 0);
3615                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3616                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3617                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3618                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3619                 break;
3620         case HW_EVENT_PHY_ERROR:
3621                 PM8001_MSG_DBG(pm8001_ha,
3622                         pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3623                 sas_phy_disconnected(&phy->sas_phy);
3624                 phy->phy_attached = 0;
3625                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3626                 break;
3627         case HW_EVENT_BROADCAST_EXP:
3628                 PM8001_MSG_DBG(pm8001_ha,
3629                         pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3630                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3631                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3632                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3633                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3634                 break;
3635         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3636                 PM8001_MSG_DBG(pm8001_ha,
3637                         pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3638                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3639                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3640                 break;
3641         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3642                 PM8001_MSG_DBG(pm8001_ha,
3643                         pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3644                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3645                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3646                         port_id, phy_id, 0, 0);
3647                 break;
3648         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3649                 PM8001_MSG_DBG(pm8001_ha,
3650                         pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3651                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3652                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3653                         port_id, phy_id, 0, 0);
3654                 break;
3655         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3656                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3657                                 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3658                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3659                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3660                         port_id, phy_id, 0, 0);
3661                 break;
3662         case HW_EVENT_MALFUNCTION:
3663                 PM8001_MSG_DBG(pm8001_ha,
3664                         pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3665                 break;
3666         case HW_EVENT_BROADCAST_SES:
3667                 PM8001_MSG_DBG(pm8001_ha,
3668                         pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3669                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3670                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3671                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3672                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3673                 break;
3674         case HW_EVENT_INBOUND_CRC_ERROR:
3675                 PM8001_MSG_DBG(pm8001_ha,
3676                         pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3677                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3678                         HW_EVENT_INBOUND_CRC_ERROR,
3679                         port_id, phy_id, 0, 0);
3680                 break;
3681         case HW_EVENT_HARD_RESET_RECEIVED:
3682                 PM8001_MSG_DBG(pm8001_ha,
3683                         pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3684                 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3685                 break;
3686         case HW_EVENT_ID_FRAME_TIMEOUT:
3687                 PM8001_MSG_DBG(pm8001_ha,
3688                         pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3689                 sas_phy_disconnected(sas_phy);
3690                 phy->phy_attached = 0;
3691                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3692                 break;
3693         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3694                 PM8001_MSG_DBG(pm8001_ha,
3695                         pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3696                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3697                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3698                         port_id, phy_id, 0, 0);
3699                 sas_phy_disconnected(sas_phy);
3700                 phy->phy_attached = 0;
3701                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3702                 break;
3703         case HW_EVENT_PORT_RESET_TIMER_TMO:
3704                 PM8001_MSG_DBG(pm8001_ha,
3705                         pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3706                 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3707                         port_id, phy_id, 0, 0);
3708                 sas_phy_disconnected(sas_phy);
3709                 phy->phy_attached = 0;
3710                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3711                 if (pm8001_ha->phy[phy_id].reset_completion) {
3712                         pm8001_ha->phy[phy_id].port_reset_status =
3713                                         PORT_RESET_TMO;
3714                         complete(pm8001_ha->phy[phy_id].reset_completion);
3715                         pm8001_ha->phy[phy_id].reset_completion = NULL;
3716                 }
3717                 break;
3718         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3719                 PM8001_MSG_DBG(pm8001_ha,
3720                         pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3721                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3722                         HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3723                         port_id, phy_id, 0, 0);
3724                 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
3725                         if (port->wide_port_phymap & (1 << i)) {
3726                                 phy = &pm8001_ha->phy[i];
3727                                 sas_ha->notify_phy_event(&phy->sas_phy,
3728                                                 PHYE_LOSS_OF_SIGNAL);
3729                                 port->wide_port_phymap &= ~(1 << i);
3730                         }
3731                 }
3732                 break;
3733         case HW_EVENT_PORT_RECOVER:
3734                 PM8001_MSG_DBG(pm8001_ha,
3735                         pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3736                 hw_event_port_recover(pm8001_ha, piomb);
3737                 break;
3738         case HW_EVENT_PORT_RESET_COMPLETE:
3739                 PM8001_MSG_DBG(pm8001_ha,
3740                         pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3741                 if (pm8001_ha->phy[phy_id].reset_completion) {
3742                         pm8001_ha->phy[phy_id].port_reset_status =
3743                                         PORT_RESET_SUCCESS;
3744                         complete(pm8001_ha->phy[phy_id].reset_completion);
3745                         pm8001_ha->phy[phy_id].reset_completion = NULL;
3746                 }
3747                 break;
3748         case EVENT_BROADCAST_ASYNCH_EVENT:
3749                 PM8001_MSG_DBG(pm8001_ha,
3750                         pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3751                 break;
3752         default:
3753                 PM8001_DEVIO_DBG(pm8001_ha,
3754                         pm8001_printk("Unknown event type 0x%x\n", eventType));
3755                 break;
3756         }
3757         return 0;
3758 }
3759
3760 /**
3761  * mpi_phy_stop_resp - SPCv specific
3762  * @pm8001_ha: our hba card information
3763  * @piomb: IO message buffer
3764  */
3765 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3766 {
3767         struct phy_stop_resp *pPayload =
3768                 (struct phy_stop_resp *)(piomb + 4);
3769         u32 status =
3770                 le32_to_cpu(pPayload->status);
3771         u32 phyid =
3772                 le32_to_cpu(pPayload->phyid) & 0xFF;
3773         struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3774         PM8001_MSG_DBG(pm8001_ha,
3775                         pm8001_printk("phy:0x%x status:0x%x\n",
3776                                         phyid, status));
3777         if (status == PHY_STOP_SUCCESS ||
3778                 status == PHY_STOP_ERR_DEVICE_ATTACHED)
3779                 phy->phy_state = PHY_LINK_DISABLE;
3780         return 0;
3781 }
3782
3783 /**
3784  * mpi_set_controller_config_resp - SPCv specific
3785  * @pm8001_ha: our hba card information
3786  * @piomb: IO message buffer
3787  */
3788 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3789                         void *piomb)
3790 {
3791         struct set_ctrl_cfg_resp *pPayload =
3792                         (struct set_ctrl_cfg_resp *)(piomb + 4);
3793         u32 status = le32_to_cpu(pPayload->status);
3794         u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3795
3796         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3797                         "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3798                         status, err_qlfr_pgcd));
3799
3800         return 0;
3801 }
3802
3803 /**
3804  * mpi_get_controller_config_resp - SPCv specific
3805  * @pm8001_ha: our hba card information
3806  * @piomb: IO message buffer
3807  */
3808 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3809                         void *piomb)
3810 {
3811         PM8001_MSG_DBG(pm8001_ha,
3812                         pm8001_printk(" pm80xx_addition_functionality\n"));
3813
3814         return 0;
3815 }
3816
3817 /**
3818  * mpi_get_phy_profile_resp - SPCv specific
3819  * @pm8001_ha: our hba card information
3820  * @piomb: IO message buffer
3821  */
3822 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3823                         void *piomb)
3824 {
3825         PM8001_MSG_DBG(pm8001_ha,
3826                         pm8001_printk(" pm80xx_addition_functionality\n"));
3827
3828         return 0;
3829 }
3830
3831 /**
3832  * mpi_flash_op_ext_resp - SPCv specific
3833  * @pm8001_ha: our hba card information
3834  * @piomb: IO message buffer
3835  */
3836 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3837 {
3838         PM8001_MSG_DBG(pm8001_ha,
3839                         pm8001_printk(" pm80xx_addition_functionality\n"));
3840
3841         return 0;
3842 }
3843
3844 /**
3845  * mpi_set_phy_profile_resp - SPCv specific
3846  * @pm8001_ha: our hba card information
3847  * @piomb: IO message buffer
3848  */
3849 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3850                         void *piomb)
3851 {
3852         u32 tag;
3853         u8 page_code;
3854         int rc = 0;
3855         struct set_phy_profile_resp *pPayload =
3856                 (struct set_phy_profile_resp *)(piomb + 4);
3857         u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3858         u32 status = le32_to_cpu(pPayload->status);
3859
3860         tag = le32_to_cpu(pPayload->tag);
3861         page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3862         if (status) {
3863                 /* status is FAILED */
3864                 PM8001_FAIL_DBG(pm8001_ha,
3865                         pm8001_printk("PhyProfile command failed  with status "
3866                         "0x%08X \n", status));
3867                 rc = -1;
3868         } else {
3869                 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3870                         PM8001_FAIL_DBG(pm8001_ha,
3871                                 pm8001_printk("Invalid page code 0x%X\n",
3872                                         page_code));
3873                         rc = -1;
3874                 }
3875         }
3876         pm8001_tag_free(pm8001_ha, tag);
3877         return rc;
3878 }
3879
3880 /**
3881  * mpi_kek_management_resp - SPCv specific
3882  * @pm8001_ha: our hba card information
3883  * @piomb: IO message buffer
3884  */
3885 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3886                         void *piomb)
3887 {
3888         struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3889
3890         u32 status = le32_to_cpu(pPayload->status);
3891         u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3892         u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3893
3894         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3895                 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3896                 status, kidx_new_curr_ksop, err_qlfr));
3897
3898         return 0;
3899 }
3900
3901 /**
3902  * mpi_dek_management_resp - SPCv specific
3903  * @pm8001_ha: our hba card information
3904  * @piomb: IO message buffer
3905  */
3906 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3907                         void *piomb)
3908 {
3909         PM8001_MSG_DBG(pm8001_ha,
3910                         pm8001_printk(" pm80xx_addition_functionality\n"));
3911
3912         return 0;
3913 }
3914
3915 /**
3916  * ssp_coalesced_comp_resp - SPCv specific
3917  * @pm8001_ha: our hba card information
3918  * @piomb: IO message buffer
3919  */
3920 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3921                         void *piomb)
3922 {
3923         PM8001_MSG_DBG(pm8001_ha,
3924                         pm8001_printk(" pm80xx_addition_functionality\n"));
3925
3926         return 0;
3927 }
3928
3929 /**
3930  * process_one_iomb - process one outbound Queue memory block
3931  * @pm8001_ha: our hba card information
3932  * @piomb: IO message buffer
3933  */
3934 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3935 {
3936         __le32 pHeader = *(__le32 *)piomb;
3937         u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3938
3939         switch (opc) {
3940         case OPC_OUB_ECHO:
3941                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3942                 break;
3943         case OPC_OUB_HW_EVENT:
3944                 PM8001_MSG_DBG(pm8001_ha,
3945                         pm8001_printk("OPC_OUB_HW_EVENT\n"));
3946                 mpi_hw_event(pm8001_ha, piomb);
3947                 break;
3948         case OPC_OUB_THERM_HW_EVENT:
3949                 PM8001_MSG_DBG(pm8001_ha,
3950                         pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
3951                 mpi_thermal_hw_event(pm8001_ha, piomb);
3952                 break;
3953         case OPC_OUB_SSP_COMP:
3954                 PM8001_MSG_DBG(pm8001_ha,
3955                         pm8001_printk("OPC_OUB_SSP_COMP\n"));
3956                 mpi_ssp_completion(pm8001_ha, piomb);
3957                 break;
3958         case OPC_OUB_SMP_COMP:
3959                 PM8001_MSG_DBG(pm8001_ha,
3960                         pm8001_printk("OPC_OUB_SMP_COMP\n"));
3961                 mpi_smp_completion(pm8001_ha, piomb);
3962                 break;
3963         case OPC_OUB_LOCAL_PHY_CNTRL:
3964                 PM8001_MSG_DBG(pm8001_ha,
3965                         pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3966                 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3967                 break;
3968         case OPC_OUB_DEV_REGIST:
3969                 PM8001_MSG_DBG(pm8001_ha,
3970                 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3971                 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3972                 break;
3973         case OPC_OUB_DEREG_DEV:
3974                 PM8001_MSG_DBG(pm8001_ha,
3975                         pm8001_printk("unregister the device\n"));
3976                 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3977                 break;
3978         case OPC_OUB_GET_DEV_HANDLE:
3979                 PM8001_MSG_DBG(pm8001_ha,
3980                         pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3981                 break;
3982         case OPC_OUB_SATA_COMP:
3983                 PM8001_MSG_DBG(pm8001_ha,
3984                         pm8001_printk("OPC_OUB_SATA_COMP\n"));
3985                 mpi_sata_completion(pm8001_ha, piomb);
3986                 break;
3987         case OPC_OUB_SATA_EVENT:
3988                 PM8001_MSG_DBG(pm8001_ha,
3989                         pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3990                 mpi_sata_event(pm8001_ha, piomb);
3991                 break;
3992         case OPC_OUB_SSP_EVENT:
3993                 PM8001_MSG_DBG(pm8001_ha,
3994                         pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3995                 mpi_ssp_event(pm8001_ha, piomb);
3996                 break;
3997         case OPC_OUB_DEV_HANDLE_ARRIV:
3998                 PM8001_MSG_DBG(pm8001_ha,
3999                         pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
4000                 /*This is for target*/
4001                 break;
4002         case OPC_OUB_SSP_RECV_EVENT:
4003                 PM8001_MSG_DBG(pm8001_ha,
4004                         pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
4005                 /*This is for target*/
4006                 break;
4007         case OPC_OUB_FW_FLASH_UPDATE:
4008                 PM8001_MSG_DBG(pm8001_ha,
4009                         pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
4010                 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
4011                 break;
4012         case OPC_OUB_GPIO_RESPONSE:
4013                 PM8001_MSG_DBG(pm8001_ha,
4014                         pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
4015                 break;
4016         case OPC_OUB_GPIO_EVENT:
4017                 PM8001_MSG_DBG(pm8001_ha,
4018                         pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
4019                 break;
4020         case OPC_OUB_GENERAL_EVENT:
4021                 PM8001_MSG_DBG(pm8001_ha,
4022                         pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
4023                 pm8001_mpi_general_event(pm8001_ha, piomb);
4024                 break;
4025         case OPC_OUB_SSP_ABORT_RSP:
4026                 PM8001_MSG_DBG(pm8001_ha,
4027                         pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
4028                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4029                 break;
4030         case OPC_OUB_SATA_ABORT_RSP:
4031                 PM8001_MSG_DBG(pm8001_ha,
4032                         pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
4033                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4034                 break;
4035         case OPC_OUB_SAS_DIAG_MODE_START_END:
4036                 PM8001_MSG_DBG(pm8001_ha,
4037                         pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
4038                 break;
4039         case OPC_OUB_SAS_DIAG_EXECUTE:
4040                 PM8001_MSG_DBG(pm8001_ha,
4041                         pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
4042                 break;
4043         case OPC_OUB_GET_TIME_STAMP:
4044                 PM8001_MSG_DBG(pm8001_ha,
4045                         pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
4046                 break;
4047         case OPC_OUB_SAS_HW_EVENT_ACK:
4048                 PM8001_MSG_DBG(pm8001_ha,
4049                         pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
4050                 break;
4051         case OPC_OUB_PORT_CONTROL:
4052                 PM8001_MSG_DBG(pm8001_ha,
4053                         pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
4054                 break;
4055         case OPC_OUB_SMP_ABORT_RSP:
4056                 PM8001_MSG_DBG(pm8001_ha,
4057                         pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
4058                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4059                 break;
4060         case OPC_OUB_GET_NVMD_DATA:
4061                 PM8001_MSG_DBG(pm8001_ha,
4062                         pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
4063                 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
4064                 break;
4065         case OPC_OUB_SET_NVMD_DATA:
4066                 PM8001_MSG_DBG(pm8001_ha,
4067                         pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
4068                 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
4069                 break;
4070         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
4071                 PM8001_MSG_DBG(pm8001_ha,
4072                         pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
4073                 break;
4074         case OPC_OUB_SET_DEVICE_STATE:
4075                 PM8001_MSG_DBG(pm8001_ha,
4076                         pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
4077                 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
4078                 break;
4079         case OPC_OUB_GET_DEVICE_STATE:
4080                 PM8001_MSG_DBG(pm8001_ha,
4081                         pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
4082                 break;
4083         case OPC_OUB_SET_DEV_INFO:
4084                 PM8001_MSG_DBG(pm8001_ha,
4085                         pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
4086                 break;
4087         /* spcv specifc commands */
4088         case OPC_OUB_PHY_START_RESP:
4089                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4090                         "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
4091                 mpi_phy_start_resp(pm8001_ha, piomb);
4092                 break;
4093         case OPC_OUB_PHY_STOP_RESP:
4094                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4095                         "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
4096                 mpi_phy_stop_resp(pm8001_ha, piomb);
4097                 break;
4098         case OPC_OUB_SET_CONTROLLER_CONFIG:
4099                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4100                         "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
4101                 mpi_set_controller_config_resp(pm8001_ha, piomb);
4102                 break;
4103         case OPC_OUB_GET_CONTROLLER_CONFIG:
4104                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4105                         "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
4106                 mpi_get_controller_config_resp(pm8001_ha, piomb);
4107                 break;
4108         case OPC_OUB_GET_PHY_PROFILE:
4109                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4110                         "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
4111                 mpi_get_phy_profile_resp(pm8001_ha, piomb);
4112                 break;
4113         case OPC_OUB_FLASH_OP_EXT:
4114                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4115                         "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
4116                 mpi_flash_op_ext_resp(pm8001_ha, piomb);
4117                 break;
4118         case OPC_OUB_SET_PHY_PROFILE:
4119                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4120                         "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
4121                 mpi_set_phy_profile_resp(pm8001_ha, piomb);
4122                 break;
4123         case OPC_OUB_KEK_MANAGEMENT_RESP:
4124                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4125                         "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
4126                 mpi_kek_management_resp(pm8001_ha, piomb);
4127                 break;
4128         case OPC_OUB_DEK_MANAGEMENT_RESP:
4129                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4130                         "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
4131                 mpi_dek_management_resp(pm8001_ha, piomb);
4132                 break;
4133         case OPC_OUB_SSP_COALESCED_COMP_RESP:
4134                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4135                         "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
4136                 ssp_coalesced_comp_resp(pm8001_ha, piomb);
4137                 break;
4138         default:
4139                 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
4140                         "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
4141                 break;
4142         }
4143 }
4144
4145 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
4146 {
4147         PM8001_FAIL_DBG(pm8001_ha,
4148                 pm8001_printk("MSGU_SCRATCH_PAD_0: 0x%x\n",
4149                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
4150         PM8001_FAIL_DBG(pm8001_ha,
4151                 pm8001_printk("MSGU_SCRATCH_PAD_1:0x%x\n",
4152                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)));
4153         PM8001_FAIL_DBG(pm8001_ha,
4154                 pm8001_printk("MSGU_SCRATCH_PAD_2: 0x%x\n",
4155                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)));
4156         PM8001_FAIL_DBG(pm8001_ha,
4157                 pm8001_printk("MSGU_SCRATCH_PAD_3: 0x%x\n",
4158                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
4159         PM8001_FAIL_DBG(pm8001_ha,
4160                 pm8001_printk("MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
4161                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0)));
4162         PM8001_FAIL_DBG(pm8001_ha,
4163                 pm8001_printk("MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
4164                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1)));
4165         PM8001_FAIL_DBG(pm8001_ha,
4166                 pm8001_printk("MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
4167                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2)));
4168         PM8001_FAIL_DBG(pm8001_ha,
4169                 pm8001_printk("MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
4170                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3)));
4171         PM8001_FAIL_DBG(pm8001_ha,
4172                 pm8001_printk("MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
4173                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4)));
4174         PM8001_FAIL_DBG(pm8001_ha,
4175                 pm8001_printk("MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
4176                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5)));
4177         PM8001_FAIL_DBG(pm8001_ha,
4178                 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
4179                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6)));
4180         PM8001_FAIL_DBG(pm8001_ha,
4181                 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
4182                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7)));
4183 }
4184
4185 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4186 {
4187         struct outbound_queue_table *circularQ;
4188         void *pMsg1 = NULL;
4189         u8 bc;
4190         u32 ret = MPI_IO_STATUS_FAIL;
4191         unsigned long flags;
4192         u32 regval;
4193
4194         if (vec == (pm8001_ha->number_of_intr - 1)) {
4195                 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
4196                 if ((regval & SCRATCH_PAD_MIPSALL_READY) !=
4197                                         SCRATCH_PAD_MIPSALL_READY) {
4198                         pm8001_ha->controller_fatal_error = true;
4199                         PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
4200                                 "Firmware Fatal error! Regval:0x%x\n", regval));
4201                         print_scratchpad_registers(pm8001_ha);
4202                         return ret;
4203                 }
4204         }
4205         spin_lock_irqsave(&pm8001_ha->lock, flags);
4206         circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4207         do {
4208                 /* spurious interrupt during setup if kexec-ing and
4209                  * driver doing a doorbell access w/ the pre-kexec oq
4210                  * interrupt setup.
4211                  */
4212                 if (!circularQ->pi_virt)
4213                         break;
4214                 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4215                 if (MPI_IO_STATUS_SUCCESS == ret) {
4216                         /* process the outbound message */
4217                         process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
4218                         /* free the message from the outbound circular buffer */
4219                         pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4220                                                         circularQ, bc);
4221                 }
4222                 if (MPI_IO_STATUS_BUSY == ret) {
4223                         /* Update the producer index from SPC */
4224                         circularQ->producer_index =
4225                                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4226                         if (le32_to_cpu(circularQ->producer_index) ==
4227                                 circularQ->consumer_idx)
4228                                 /* OQ is empty */
4229                                 break;
4230                 }
4231         } while (1);
4232         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4233         return ret;
4234 }
4235
4236 /* DMA_... to our direction translation. */
4237 static const u8 data_dir_flags[] = {
4238         [DMA_BIDIRECTIONAL]     = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
4239         [DMA_TO_DEVICE]         = DATA_DIR_OUT,         /* OUTBOUND */
4240         [DMA_FROM_DEVICE]       = DATA_DIR_IN,          /* INBOUND */
4241         [DMA_NONE]              = DATA_DIR_NONE,        /* NO TRANSFER */
4242 };
4243
4244 static void build_smp_cmd(u32 deviceID, __le32 hTag,
4245                         struct smp_req *psmp_cmd, int mode, int length)
4246 {
4247         psmp_cmd->tag = hTag;
4248         psmp_cmd->device_id = cpu_to_le32(deviceID);
4249         if (mode == SMP_DIRECT) {
4250                 length = length - 4; /* subtract crc */
4251                 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
4252         } else {
4253                 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4254         }
4255 }
4256
4257 /**
4258  * pm8001_chip_smp_req - send a SMP task to FW
4259  * @pm8001_ha: our hba card information.
4260  * @ccb: the ccb information this request used.
4261  */
4262 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4263         struct pm8001_ccb_info *ccb)
4264 {
4265         int elem, rc;
4266         struct sas_task *task = ccb->task;
4267         struct domain_device *dev = task->dev;
4268         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4269         struct scatterlist *sg_req, *sg_resp;
4270         u32 req_len, resp_len;
4271         struct smp_req smp_cmd;
4272         u32 opc;
4273         struct inbound_queue_table *circularQ;
4274         char *preq_dma_addr = NULL;
4275         __le64 tmp_addr;
4276         u32 i, length;
4277
4278         memset(&smp_cmd, 0, sizeof(smp_cmd));
4279         /*
4280          * DMA-map SMP request, response buffers
4281          */
4282         sg_req = &task->smp_task.smp_req;
4283         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4284         if (!elem)
4285                 return -ENOMEM;
4286         req_len = sg_dma_len(sg_req);
4287
4288         sg_resp = &task->smp_task.smp_resp;
4289         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4290         if (!elem) {
4291                 rc = -ENOMEM;
4292                 goto err_out;
4293         }
4294         resp_len = sg_dma_len(sg_resp);
4295         /* must be in dwords */
4296         if ((req_len & 0x3) || (resp_len & 0x3)) {
4297                 rc = -EINVAL;
4298                 goto err_out_2;
4299         }
4300
4301         opc = OPC_INB_SMP_REQUEST;
4302         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4303         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4304
4305         length = sg_req->length;
4306         PM8001_IO_DBG(pm8001_ha,
4307                 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
4308         if (!(length - 8))
4309                 pm8001_ha->smp_exp_mode = SMP_DIRECT;
4310         else
4311                 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
4312
4313
4314         tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4315         preq_dma_addr = (char *)phys_to_virt(tmp_addr);
4316
4317         /* INDIRECT MODE command settings. Use DMA */
4318         if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
4319                 PM8001_IO_DBG(pm8001_ha,
4320                         pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
4321                 /* for SPCv indirect mode. Place the top 4 bytes of
4322                  * SMP Request header here. */
4323                 for (i = 0; i < 4; i++)
4324                         smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
4325                 /* exclude top 4 bytes for SMP req header */
4326                 smp_cmd.long_smp_req.long_req_addr =
4327                         cpu_to_le64((u64)sg_dma_address
4328                                 (&task->smp_task.smp_req) + 4);
4329                 /* exclude 4 bytes for SMP req header and CRC */
4330                 smp_cmd.long_smp_req.long_req_size =
4331                         cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
4332                 smp_cmd.long_smp_req.long_resp_addr =
4333                                 cpu_to_le64((u64)sg_dma_address
4334                                         (&task->smp_task.smp_resp));
4335                 smp_cmd.long_smp_req.long_resp_size =
4336                                 cpu_to_le32((u32)sg_dma_len
4337                                         (&task->smp_task.smp_resp)-4);
4338         } else { /* DIRECT MODE */
4339                 smp_cmd.long_smp_req.long_req_addr =
4340                         cpu_to_le64((u64)sg_dma_address
4341                                         (&task->smp_task.smp_req));
4342                 smp_cmd.long_smp_req.long_req_size =
4343                         cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4344                 smp_cmd.long_smp_req.long_resp_addr =
4345                         cpu_to_le64((u64)sg_dma_address
4346                                 (&task->smp_task.smp_resp));
4347                 smp_cmd.long_smp_req.long_resp_size =
4348                         cpu_to_le32
4349                         ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4350         }
4351         if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
4352                 PM8001_IO_DBG(pm8001_ha,
4353                         pm8001_printk("SMP REQUEST DIRECT MODE\n"));
4354                 for (i = 0; i < length; i++)
4355                         if (i < 16) {
4356                                 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
4357                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4358                                         "Byte[%d]:%x (DMA data:%x)\n",
4359                                         i, smp_cmd.smp_req16[i],
4360                                         *(preq_dma_addr)));
4361                         } else {
4362                                 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
4363                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4364                                         "Byte[%d]:%x (DMA data:%x)\n",
4365                                         i, smp_cmd.smp_req[i],
4366                                         *(preq_dma_addr)));
4367                         }
4368         }
4369
4370         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
4371                                 &smp_cmd, pm8001_ha->smp_exp_mode, length);
4372         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &smp_cmd,
4373                         sizeof(smp_cmd), 0);
4374         if (rc)
4375                 goto err_out_2;
4376         return 0;
4377
4378 err_out_2:
4379         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4380                         DMA_FROM_DEVICE);
4381 err_out:
4382         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4383                         DMA_TO_DEVICE);
4384         return rc;
4385 }
4386
4387 static int check_enc_sas_cmd(struct sas_task *task)
4388 {
4389         u8 cmd = task->ssp_task.cmd->cmnd[0];
4390
4391         if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
4392                 return 1;
4393         else
4394                 return 0;
4395 }
4396
4397 static int check_enc_sat_cmd(struct sas_task *task)
4398 {
4399         int ret = 0;
4400         switch (task->ata_task.fis.command) {
4401         case ATA_CMD_FPDMA_READ:
4402         case ATA_CMD_READ_EXT:
4403         case ATA_CMD_READ:
4404         case ATA_CMD_FPDMA_WRITE:
4405         case ATA_CMD_WRITE_EXT:
4406         case ATA_CMD_WRITE:
4407         case ATA_CMD_PIO_READ:
4408         case ATA_CMD_PIO_READ_EXT:
4409         case ATA_CMD_PIO_WRITE:
4410         case ATA_CMD_PIO_WRITE_EXT:
4411                 ret = 1;
4412                 break;
4413         default:
4414                 ret = 0;
4415                 break;
4416         }
4417         return ret;
4418 }
4419
4420 /**
4421  * pm80xx_chip_ssp_io_req - send a SSP task to FW
4422  * @pm8001_ha: our hba card information.
4423  * @ccb: the ccb information this request used.
4424  */
4425 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4426         struct pm8001_ccb_info *ccb)
4427 {
4428         struct sas_task *task = ccb->task;
4429         struct domain_device *dev = task->dev;
4430         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4431         struct ssp_ini_io_start_req ssp_cmd;
4432         u32 tag = ccb->ccb_tag;
4433         int ret;
4434         u64 phys_addr, start_addr, end_addr;
4435         u32 end_addr_high, end_addr_low;
4436         struct inbound_queue_table *circularQ;
4437         u32 q_index;
4438         u32 opc = OPC_INB_SSPINIIOSTART;
4439         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4440         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4441         /* data address domain added for spcv; set to 0 by host,
4442          * used internally by controller
4443          * 0 for SAS 1.1 and SAS 2.0 compatible TLR
4444          */
4445         ssp_cmd.dad_dir_m_tlr =
4446                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
4447         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4448         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4449         ssp_cmd.tag = cpu_to_le32(tag);
4450         if (task->ssp_task.enable_first_burst)
4451                 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4452         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4453         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4454         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4455                        task->ssp_task.cmd->cmd_len);
4456         q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4457         circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4458
4459         /* Check if encryption is set */
4460         if (pm8001_ha->chip->encrypt &&
4461                 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
4462                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4463                         "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
4464                         task->ssp_task.cmd->cmnd[0]));
4465                 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
4466                 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
4467                 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
4468                         ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
4469
4470                 /* fill in PRD (scatter/gather) table, if any */
4471                 if (task->num_scatter > 1) {
4472                         pm8001_chip_make_sg(task->scatter,
4473                                                 ccb->n_elem, ccb->buf_prd);
4474                         phys_addr = ccb->ccb_dma_handle +
4475                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4476                         ssp_cmd.enc_addr_low =
4477                                 cpu_to_le32(lower_32_bits(phys_addr));
4478                         ssp_cmd.enc_addr_high =
4479                                 cpu_to_le32(upper_32_bits(phys_addr));
4480                         ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4481                 } else if (task->num_scatter == 1) {
4482                         u64 dma_addr = sg_dma_address(task->scatter);
4483                         ssp_cmd.enc_addr_low =
4484                                 cpu_to_le32(lower_32_bits(dma_addr));
4485                         ssp_cmd.enc_addr_high =
4486                                 cpu_to_le32(upper_32_bits(dma_addr));
4487                         ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4488                         ssp_cmd.enc_esgl = 0;
4489                         /* Check 4G Boundary */
4490                         start_addr = cpu_to_le64(dma_addr);
4491                         end_addr = (start_addr + ssp_cmd.enc_len) - 1;
4492                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4493                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4494                         if (end_addr_high != ssp_cmd.enc_addr_high) {
4495                                 PM8001_FAIL_DBG(pm8001_ha,
4496                                         pm8001_printk("The sg list address "
4497                                         "start_addr=0x%016llx data_len=0x%x "
4498                                         "end_addr_high=0x%08x end_addr_low="
4499                                         "0x%08x has crossed 4G boundary\n",
4500                                                 start_addr, ssp_cmd.enc_len,
4501                                                 end_addr_high, end_addr_low));
4502                                 pm8001_chip_make_sg(task->scatter, 1,
4503                                         ccb->buf_prd);
4504                                 phys_addr = ccb->ccb_dma_handle +
4505                                         offsetof(struct pm8001_ccb_info,
4506                                                 buf_prd[0]);
4507                                 ssp_cmd.enc_addr_low =
4508                                         cpu_to_le32(lower_32_bits(phys_addr));
4509                                 ssp_cmd.enc_addr_high =
4510                                         cpu_to_le32(upper_32_bits(phys_addr));
4511                                 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4512                         }
4513                 } else if (task->num_scatter == 0) {
4514                         ssp_cmd.enc_addr_low = 0;
4515                         ssp_cmd.enc_addr_high = 0;
4516                         ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4517                         ssp_cmd.enc_esgl = 0;
4518                 }
4519                 /* XTS mode. All other fields are 0 */
4520                 ssp_cmd.key_cmode = 0x6 << 4;
4521                 /* set tweak values. Should be the start lba */
4522                 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4523                                                 (task->ssp_task.cmd->cmnd[3] << 16) |
4524                                                 (task->ssp_task.cmd->cmnd[4] << 8) |
4525                                                 (task->ssp_task.cmd->cmnd[5]));
4526         } else {
4527                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4528                         "Sending Normal SAS command 0x%x inb q %x\n",
4529                         task->ssp_task.cmd->cmnd[0], q_index));
4530                 /* fill in PRD (scatter/gather) table, if any */
4531                 if (task->num_scatter > 1) {
4532                         pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4533                                         ccb->buf_prd);
4534                         phys_addr = ccb->ccb_dma_handle +
4535                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4536                         ssp_cmd.addr_low =
4537                                 cpu_to_le32(lower_32_bits(phys_addr));
4538                         ssp_cmd.addr_high =
4539                                 cpu_to_le32(upper_32_bits(phys_addr));
4540                         ssp_cmd.esgl = cpu_to_le32(1<<31);
4541                 } else if (task->num_scatter == 1) {
4542                         u64 dma_addr = sg_dma_address(task->scatter);
4543                         ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4544                         ssp_cmd.addr_high =
4545                                 cpu_to_le32(upper_32_bits(dma_addr));
4546                         ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4547                         ssp_cmd.esgl = 0;
4548                         /* Check 4G Boundary */
4549                         start_addr = cpu_to_le64(dma_addr);
4550                         end_addr = (start_addr + ssp_cmd.len) - 1;
4551                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4552                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4553                         if (end_addr_high != ssp_cmd.addr_high) {
4554                                 PM8001_FAIL_DBG(pm8001_ha,
4555                                         pm8001_printk("The sg list address "
4556                                         "start_addr=0x%016llx data_len=0x%x "
4557                                         "end_addr_high=0x%08x end_addr_low="
4558                                         "0x%08x has crossed 4G boundary\n",
4559                                                  start_addr, ssp_cmd.len,
4560                                                  end_addr_high, end_addr_low));
4561                                 pm8001_chip_make_sg(task->scatter, 1,
4562                                         ccb->buf_prd);
4563                                 phys_addr = ccb->ccb_dma_handle +
4564                                         offsetof(struct pm8001_ccb_info,
4565                                                  buf_prd[0]);
4566                                 ssp_cmd.addr_low =
4567                                         cpu_to_le32(lower_32_bits(phys_addr));
4568                                 ssp_cmd.addr_high =
4569                                         cpu_to_le32(upper_32_bits(phys_addr));
4570                                 ssp_cmd.esgl = cpu_to_le32(1<<31);
4571                         }
4572                 } else if (task->num_scatter == 0) {
4573                         ssp_cmd.addr_low = 0;
4574                         ssp_cmd.addr_high = 0;
4575                         ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4576                         ssp_cmd.esgl = 0;
4577                 }
4578         }
4579         q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4580         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4581                         &ssp_cmd, sizeof(ssp_cmd), q_index);
4582         return ret;
4583 }
4584
4585 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4586         struct pm8001_ccb_info *ccb)
4587 {
4588         struct sas_task *task = ccb->task;
4589         struct domain_device *dev = task->dev;
4590         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4591         u32 tag = ccb->ccb_tag;
4592         int ret;
4593         u32 q_index;
4594         struct sata_start_req sata_cmd;
4595         u32 hdr_tag, ncg_tag = 0;
4596         u64 phys_addr, start_addr, end_addr;
4597         u32 end_addr_high, end_addr_low;
4598         u32 ATAP = 0x0;
4599         u32 dir;
4600         struct inbound_queue_table *circularQ;
4601         unsigned long flags;
4602         u32 opc = OPC_INB_SATA_HOST_OPSTART;
4603         memset(&sata_cmd, 0, sizeof(sata_cmd));
4604         q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4605         circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4606
4607         if (task->data_dir == DMA_NONE) {
4608                 ATAP = 0x04; /* no data*/
4609                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4610         } else if (likely(!task->ata_task.device_control_reg_update)) {
4611                 if (task->ata_task.dma_xfer) {
4612                         ATAP = 0x06; /* DMA */
4613                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4614                 } else {
4615                         ATAP = 0x05; /* PIO*/
4616                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4617                 }
4618                 if (task->ata_task.use_ncq &&
4619                     dev->sata_dev.class != ATA_DEV_ATAPI) {
4620                         ATAP = 0x07; /* FPDMA */
4621                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4622                 }
4623         }
4624         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4625                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4626                 ncg_tag = hdr_tag;
4627         }
4628         dir = data_dir_flags[task->data_dir] << 8;
4629         sata_cmd.tag = cpu_to_le32(tag);
4630         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4631         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4632
4633         sata_cmd.sata_fis = task->ata_task.fis;
4634         if (likely(!task->ata_task.device_control_reg_update))
4635                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4636         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4637
4638         /* Check if encryption is set */
4639         if (pm8001_ha->chip->encrypt &&
4640                 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4641                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4642                         "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4643                         sata_cmd.sata_fis.command));
4644                 opc = OPC_INB_SATA_DIF_ENC_IO;
4645
4646                 /* set encryption bit */
4647                 sata_cmd.ncqtag_atap_dir_m_dad =
4648                         cpu_to_le32(((ncg_tag & 0xff)<<16)|
4649                                 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4650                                                         /* dad (bit 0-1) is 0 */
4651                 /* fill in PRD (scatter/gather) table, if any */
4652                 if (task->num_scatter > 1) {
4653                         pm8001_chip_make_sg(task->scatter,
4654                                                 ccb->n_elem, ccb->buf_prd);
4655                         phys_addr = ccb->ccb_dma_handle +
4656                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4657                         sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
4658                         sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
4659                         sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4660                 } else if (task->num_scatter == 1) {
4661                         u64 dma_addr = sg_dma_address(task->scatter);
4662                         sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
4663                         sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
4664                         sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4665                         sata_cmd.enc_esgl = 0;
4666                         /* Check 4G Boundary */
4667                         start_addr = cpu_to_le64(dma_addr);
4668                         end_addr = (start_addr + sata_cmd.enc_len) - 1;
4669                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4670                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4671                         if (end_addr_high != sata_cmd.enc_addr_high) {
4672                                 PM8001_FAIL_DBG(pm8001_ha,
4673                                         pm8001_printk("The sg list address "
4674                                         "start_addr=0x%016llx data_len=0x%x "
4675                                         "end_addr_high=0x%08x end_addr_low"
4676                                         "=0x%08x has crossed 4G boundary\n",
4677                                                 start_addr, sata_cmd.enc_len,
4678                                                 end_addr_high, end_addr_low));
4679                                 pm8001_chip_make_sg(task->scatter, 1,
4680                                         ccb->buf_prd);
4681                                 phys_addr = ccb->ccb_dma_handle +
4682                                                 offsetof(struct pm8001_ccb_info,
4683                                                 buf_prd[0]);
4684                                 sata_cmd.enc_addr_low =
4685                                         lower_32_bits(phys_addr);
4686                                 sata_cmd.enc_addr_high =
4687                                         upper_32_bits(phys_addr);
4688                                 sata_cmd.enc_esgl =
4689                                         cpu_to_le32(1 << 31);
4690                         }
4691                 } else if (task->num_scatter == 0) {
4692                         sata_cmd.enc_addr_low = 0;
4693                         sata_cmd.enc_addr_high = 0;
4694                         sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4695                         sata_cmd.enc_esgl = 0;
4696                 }
4697                 /* XTS mode. All other fields are 0 */
4698                 sata_cmd.key_index_mode = 0x6 << 4;
4699                 /* set tweak values. Should be the start lba */
4700                 sata_cmd.twk_val0 =
4701                         cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4702                                         (sata_cmd.sata_fis.lbah << 16) |
4703                                         (sata_cmd.sata_fis.lbam << 8) |
4704                                         (sata_cmd.sata_fis.lbal));
4705                 sata_cmd.twk_val1 =
4706                         cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4707                                          (sata_cmd.sata_fis.lbam_exp));
4708         } else {
4709                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4710                         "Sending Normal SATA command 0x%x inb %x\n",
4711                         sata_cmd.sata_fis.command, q_index));
4712                 /* dad (bit 0-1) is 0 */
4713                 sata_cmd.ncqtag_atap_dir_m_dad =
4714                         cpu_to_le32(((ncg_tag & 0xff)<<16) |
4715                                         ((ATAP & 0x3f) << 10) | dir);
4716
4717                 /* fill in PRD (scatter/gather) table, if any */
4718                 if (task->num_scatter > 1) {
4719                         pm8001_chip_make_sg(task->scatter,
4720                                         ccb->n_elem, ccb->buf_prd);
4721                         phys_addr = ccb->ccb_dma_handle +
4722                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4723                         sata_cmd.addr_low = lower_32_bits(phys_addr);
4724                         sata_cmd.addr_high = upper_32_bits(phys_addr);
4725                         sata_cmd.esgl = cpu_to_le32(1 << 31);
4726                 } else if (task->num_scatter == 1) {
4727                         u64 dma_addr = sg_dma_address(task->scatter);
4728                         sata_cmd.addr_low = lower_32_bits(dma_addr);
4729                         sata_cmd.addr_high = upper_32_bits(dma_addr);
4730                         sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4731                         sata_cmd.esgl = 0;
4732                         /* Check 4G Boundary */
4733                         start_addr = cpu_to_le64(dma_addr);
4734                         end_addr = (start_addr + sata_cmd.len) - 1;
4735                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4736                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4737                         if (end_addr_high != sata_cmd.addr_high) {
4738                                 PM8001_FAIL_DBG(pm8001_ha,
4739                                         pm8001_printk("The sg list address "
4740                                         "start_addr=0x%016llx data_len=0x%x"
4741                                         "end_addr_high=0x%08x end_addr_low="
4742                                         "0x%08x has crossed 4G boundary\n",
4743                                                 start_addr, sata_cmd.len,
4744                                                 end_addr_high, end_addr_low));
4745                                 pm8001_chip_make_sg(task->scatter, 1,
4746                                         ccb->buf_prd);
4747                                 phys_addr = ccb->ccb_dma_handle +
4748                                         offsetof(struct pm8001_ccb_info,
4749                                         buf_prd[0]);
4750                                 sata_cmd.addr_low =
4751                                         lower_32_bits(phys_addr);
4752                                 sata_cmd.addr_high =
4753                                         upper_32_bits(phys_addr);
4754                                 sata_cmd.esgl = cpu_to_le32(1 << 31);
4755                         }
4756                 } else if (task->num_scatter == 0) {
4757                         sata_cmd.addr_low = 0;
4758                         sata_cmd.addr_high = 0;
4759                         sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4760                         sata_cmd.esgl = 0;
4761                 }
4762                 /* scsi cdb */
4763                 sata_cmd.atapi_scsi_cdb[0] =
4764                         cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4765                         (task->ata_task.atapi_packet[1] << 8) |
4766                         (task->ata_task.atapi_packet[2] << 16) |
4767                         (task->ata_task.atapi_packet[3] << 24)));
4768                 sata_cmd.atapi_scsi_cdb[1] =
4769                         cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4770                         (task->ata_task.atapi_packet[5] << 8) |
4771                         (task->ata_task.atapi_packet[6] << 16) |
4772                         (task->ata_task.atapi_packet[7] << 24)));
4773                 sata_cmd.atapi_scsi_cdb[2] =
4774                         cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4775                         (task->ata_task.atapi_packet[9] << 8) |
4776                         (task->ata_task.atapi_packet[10] << 16) |
4777                         (task->ata_task.atapi_packet[11] << 24)));
4778                 sata_cmd.atapi_scsi_cdb[3] =
4779                         cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4780                         (task->ata_task.atapi_packet[13] << 8) |
4781                         (task->ata_task.atapi_packet[14] << 16) |
4782                         (task->ata_task.atapi_packet[15] << 24)));
4783         }
4784
4785         /* Check for read log for failed drive and return */
4786         if (sata_cmd.sata_fis.command == 0x2f) {
4787                 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4788                         (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4789                         (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4790                         struct task_status_struct *ts;
4791
4792                         pm8001_ha_dev->id &= 0xDFFFFFFF;
4793                         ts = &task->task_status;
4794
4795                         spin_lock_irqsave(&task->task_state_lock, flags);
4796                         ts->resp = SAS_TASK_COMPLETE;
4797                         ts->stat = SAM_STAT_GOOD;
4798                         task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4799                         task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4800                         task->task_state_flags |= SAS_TASK_STATE_DONE;
4801                         if (unlikely((task->task_state_flags &
4802                                         SAS_TASK_STATE_ABORTED))) {
4803                                 spin_unlock_irqrestore(&task->task_state_lock,
4804                                                         flags);
4805                                 PM8001_FAIL_DBG(pm8001_ha,
4806                                         pm8001_printk("task 0x%p resp 0x%x "
4807                                         " stat 0x%x but aborted by upper layer "
4808                                         "\n", task, ts->resp, ts->stat));
4809                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4810                                 return 0;
4811                         } else {
4812                                 spin_unlock_irqrestore(&task->task_state_lock,
4813                                                         flags);
4814                                 pm8001_ccb_task_free_done(pm8001_ha, task,
4815                                                                 ccb, tag);
4816                                 return 0;
4817                         }
4818                 }
4819         }
4820         q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4821         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4822                         &sata_cmd, sizeof(sata_cmd), q_index);
4823         return ret;
4824 }
4825
4826 /**
4827  * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4828  * @pm8001_ha: our hba card information.
4829  * @phy_id: the phy id which we wanted to start up.
4830  */
4831 static int
4832 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4833 {
4834         struct phy_start_req payload;
4835         struct inbound_queue_table *circularQ;
4836         int ret;
4837         u32 tag = 0x01;
4838         u32 opcode = OPC_INB_PHYSTART;
4839         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4840         memset(&payload, 0, sizeof(payload));
4841         payload.tag = cpu_to_le32(tag);
4842
4843         PM8001_INIT_DBG(pm8001_ha,
4844                 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
4845
4846         payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4847                         LINKMODE_AUTO | pm8001_ha->link_rate | phy_id);
4848         /* SSC Disable and SAS Analog ST configuration */
4849         /**
4850         payload.ase_sh_lm_slr_phyid =
4851                 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4852                 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4853                 phy_id);
4854         Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4855         **/
4856
4857         payload.sas_identify.dev_type = SAS_END_DEVICE;
4858         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4859         memcpy(payload.sas_identify.sas_addr,
4860           &pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4861         payload.sas_identify.phy_id = phy_id;
4862         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4863                         sizeof(payload), 0);
4864         return ret;
4865 }
4866
4867 /**
4868  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4869  * @pm8001_ha: our hba card information.
4870  * @phy_id: the phy id which we wanted to start up.
4871  */
4872 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4873         u8 phy_id)
4874 {
4875         struct phy_stop_req payload;
4876         struct inbound_queue_table *circularQ;
4877         int ret;
4878         u32 tag = 0x01;
4879         u32 opcode = OPC_INB_PHYSTOP;
4880         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4881         memset(&payload, 0, sizeof(payload));
4882         payload.tag = cpu_to_le32(tag);
4883         payload.phy_id = cpu_to_le32(phy_id);
4884         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4885                         sizeof(payload), 0);
4886         return ret;
4887 }
4888
4889 /*
4890  * see comments on pm8001_mpi_reg_resp.
4891  */
4892 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4893         struct pm8001_device *pm8001_dev, u32 flag)
4894 {
4895         struct reg_dev_req payload;
4896         u32     opc;
4897         u32 stp_sspsmp_sata = 0x4;
4898         struct inbound_queue_table *circularQ;
4899         u32 linkrate, phy_id;
4900         int rc, tag = 0xdeadbeef;
4901         struct pm8001_ccb_info *ccb;
4902         u8 retryFlag = 0x1;
4903         u16 firstBurstSize = 0;
4904         u16 ITNT = 2000;
4905         struct domain_device *dev = pm8001_dev->sas_device;
4906         struct domain_device *parent_dev = dev->parent;
4907         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4908
4909         memset(&payload, 0, sizeof(payload));
4910         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4911         if (rc)
4912                 return rc;
4913         ccb = &pm8001_ha->ccb_info[tag];
4914         ccb->device = pm8001_dev;
4915         ccb->ccb_tag = tag;
4916         payload.tag = cpu_to_le32(tag);
4917
4918         if (flag == 1) {
4919                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4920         } else {
4921                 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4922                         stp_sspsmp_sata = 0x00; /* stp*/
4923                 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4924                         pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4925                         pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4926                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4927         }
4928         if (parent_dev && dev_is_expander(parent_dev->dev_type))
4929                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4930         else
4931                 phy_id = pm8001_dev->attached_phy;
4932
4933         opc = OPC_INB_REG_DEV;
4934
4935         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4936                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4937
4938         payload.phyid_portid =
4939                 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4940                 ((phy_id & 0xFF) << 8));
4941
4942         payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4943                 ((linkrate & 0x0F) << 24) |
4944                 ((stp_sspsmp_sata & 0x03) << 28));
4945         payload.firstburstsize_ITNexustimeout =
4946                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4947
4948         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4949                 SAS_ADDR_SIZE);
4950
4951         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4952                         sizeof(payload), 0);
4953         if (rc)
4954                 pm8001_tag_free(pm8001_ha, tag);
4955
4956         return rc;
4957 }
4958
4959 /**
4960  * pm80xx_chip_phy_ctl_req - support the local phy operation
4961  * @pm8001_ha: our hba card information.
4962  * @phyId: the phy id which we wanted to operate
4963  * @phy_op: phy operation to request
4964  */
4965 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4966         u32 phyId, u32 phy_op)
4967 {
4968         u32 tag;
4969         int rc;
4970         struct local_phy_ctl_req payload;
4971         struct inbound_queue_table *circularQ;
4972         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4973         memset(&payload, 0, sizeof(payload));
4974         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4975         if (rc)
4976                 return rc;
4977         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4978         payload.tag = cpu_to_le32(tag);
4979         payload.phyop_phyid =
4980                 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4981         return pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4982                         sizeof(payload), 0);
4983 }
4984
4985 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4986 {
4987 #ifdef PM8001_USE_MSIX
4988         return 1;
4989 #else
4990         u32 value;
4991
4992         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4993         if (value)
4994                 return 1;
4995         return 0;
4996 #endif
4997 }
4998
4999 /**
5000  * pm8001_chip_isr - PM8001 isr handler.
5001  * @pm8001_ha: our hba card information.
5002  * @vec: irq number.
5003  */
5004 static irqreturn_t
5005 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
5006 {
5007         pm80xx_chip_interrupt_disable(pm8001_ha, vec);
5008         PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
5009                 "irq vec %d, ODMR:0x%x\n",
5010                 vec, pm8001_cr32(pm8001_ha, 0, 0x30)));
5011         process_oq(pm8001_ha, vec);
5012         pm80xx_chip_interrupt_enable(pm8001_ha, vec);
5013         return IRQ_HANDLED;
5014 }
5015
5016 static void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
5017                                     u32 operation, u32 phyid,
5018                                     u32 length, u32 *buf)
5019 {
5020         u32 tag , i, j = 0;
5021         int rc;
5022         struct set_phy_profile_req payload;
5023         struct inbound_queue_table *circularQ;
5024         u32 opc = OPC_INB_SET_PHY_PROFILE;
5025
5026         memset(&payload, 0, sizeof(payload));
5027         rc = pm8001_tag_alloc(pm8001_ha, &tag);
5028         if (rc)
5029                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n"));
5030         circularQ = &pm8001_ha->inbnd_q_tbl[0];
5031         payload.tag = cpu_to_le32(tag);
5032         payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid  & 0xFF));
5033         PM8001_INIT_DBG(pm8001_ha,
5034                 pm8001_printk(" phy profile command for phy %x ,length is %d\n",
5035                         payload.ppc_phyid, length));
5036         for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
5037                 payload.reserved[j] =  cpu_to_le32(*((u32 *)buf + i));
5038                 j++;
5039         }
5040         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
5041                         sizeof(payload), 0);
5042         if (rc)
5043                 pm8001_tag_free(pm8001_ha, tag);
5044 }
5045
5046 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
5047         u32 length, u8 *buf)
5048 {
5049         u32 i;
5050
5051         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
5052                 mpi_set_phy_profile_req(pm8001_ha,
5053                         SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
5054                 length = length + PHY_DWORD_LENGTH;
5055         }
5056         PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n"));
5057 }
5058
5059 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
5060                 u32 phy, u32 length, u32 *buf)
5061 {
5062         u32 tag, opc;
5063         int rc, i;
5064         struct set_phy_profile_req payload;
5065         struct inbound_queue_table *circularQ;
5066
5067         memset(&payload, 0, sizeof(payload));
5068
5069         rc = pm8001_tag_alloc(pm8001_ha, &tag);
5070         if (rc)
5071                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("Invalid tag"));
5072
5073         circularQ = &pm8001_ha->inbnd_q_tbl[0];
5074         opc = OPC_INB_SET_PHY_PROFILE;
5075
5076         payload.tag = cpu_to_le32(tag);
5077         payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
5078                                 | (phy & 0xFF));
5079
5080         for (i = 0; i < length; i++)
5081                 payload.reserved[i] = cpu_to_le32(*(buf + i));
5082
5083         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
5084                         sizeof(payload), 0);
5085         if (rc)
5086                 pm8001_tag_free(pm8001_ha, tag);
5087
5088         PM8001_INIT_DBG(pm8001_ha,
5089                 pm8001_printk("PHY %d settings applied", phy));
5090 }
5091 const struct pm8001_dispatch pm8001_80xx_dispatch = {
5092         .name                   = "pmc80xx",
5093         .chip_init              = pm80xx_chip_init,
5094         .chip_soft_rst          = pm80xx_chip_soft_rst,
5095         .chip_rst               = pm80xx_hw_chip_rst,
5096         .chip_iounmap           = pm8001_chip_iounmap,
5097         .isr                    = pm80xx_chip_isr,
5098         .is_our_interrupt       = pm80xx_chip_is_our_interrupt,
5099         .isr_process_oq         = process_oq,
5100         .interrupt_enable       = pm80xx_chip_interrupt_enable,
5101         .interrupt_disable      = pm80xx_chip_interrupt_disable,
5102         .make_prd               = pm8001_chip_make_sg,
5103         .smp_req                = pm80xx_chip_smp_req,
5104         .ssp_io_req             = pm80xx_chip_ssp_io_req,
5105         .sata_req               = pm80xx_chip_sata_req,
5106         .phy_start_req          = pm80xx_chip_phy_start_req,
5107         .phy_stop_req           = pm80xx_chip_phy_stop_req,
5108         .reg_dev_req            = pm80xx_chip_reg_dev_req,
5109         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
5110         .phy_ctl_req            = pm80xx_chip_phy_ctl_req,
5111         .task_abort             = pm8001_chip_abort_task,
5112         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
5113         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
5114         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
5115         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
5116         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
5117 };