2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 USI Co., Ltd.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
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12 * without modification.
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14 * substantially similar to the "NO WARRANTY" disclaimer below
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16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
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19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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41 #include <linux/slab.h>
42 #include "pm8001_sas.h"
43 #include "pm8001_chips.h"
44 #include "pm80xx_hwi.h"
46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING;
47 module_param(logging_level, ulong, 0644);
48 MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
50 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
51 module_param(link_rate, ulong, 0644);
52 MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
53 " 1: Link rate 1.5G\n"
54 " 2: Link rate 3.0G\n"
55 " 4: Link rate 6.0G\n"
56 " 8: Link rate 12.0G\n");
58 static struct scsi_transport_template *pm8001_stt;
59 static int pm8001_init_ccb_tag(struct pm8001_hba_info *, struct Scsi_Host *, struct pci_dev *);
62 * chip info structure to identify chip key functionality as
63 * encryption available/not, no of ports, hw specific function ref
65 static const struct pm8001_chip_info pm8001_chips[] = {
66 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
67 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
68 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
69 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
70 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
71 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,},
72 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,},
73 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,},
74 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,},
75 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,},
76 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,},
82 struct workqueue_struct *pm8001_wq;
85 * The main structure which LLDD must register for scsi core.
87 static struct scsi_host_template pm8001_sht = {
88 .module = THIS_MODULE,
90 .queuecommand = sas_queuecommand,
91 .dma_need_drain = ata_scsi_dma_need_drain,
92 .target_alloc = sas_target_alloc,
93 .slave_configure = sas_slave_configure,
94 .scan_finished = pm8001_scan_finished,
95 .scan_start = pm8001_scan_start,
96 .change_queue_depth = sas_change_queue_depth,
97 .bios_param = sas_bios_param,
100 .sg_tablesize = PM8001_MAX_DMA_SG,
101 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
102 .eh_device_reset_handler = sas_eh_device_reset_handler,
103 .eh_target_reset_handler = sas_eh_target_reset_handler,
104 .target_destroy = sas_target_destroy,
107 .compat_ioctl = sas_ioctl,
109 .shost_attrs = pm8001_host_attrs,
110 .track_queue_depth = 1,
114 * Sas layer call this function to execute specific task.
116 static struct sas_domain_function_template pm8001_transport_ops = {
117 .lldd_dev_found = pm8001_dev_found,
118 .lldd_dev_gone = pm8001_dev_gone,
120 .lldd_execute_task = pm8001_queue_command,
121 .lldd_control_phy = pm8001_phy_control,
123 .lldd_abort_task = pm8001_abort_task,
124 .lldd_abort_task_set = pm8001_abort_task_set,
125 .lldd_clear_aca = pm8001_clear_aca,
126 .lldd_clear_task_set = pm8001_clear_task_set,
127 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
128 .lldd_lu_reset = pm8001_lu_reset,
129 .lldd_query_task = pm8001_query_task,
133 * pm8001_phy_init - initiate our adapter phys
134 * @pm8001_ha: our hba structure.
137 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
139 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
140 struct asd_sas_phy *sas_phy = &phy->sas_phy;
141 phy->phy_state = PHY_LINK_DISABLE;
142 phy->pm8001_ha = pm8001_ha;
143 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
144 sas_phy->class = SAS;
145 sas_phy->iproto = SAS_PROTOCOL_ALL;
147 sas_phy->type = PHY_TYPE_PHYSICAL;
148 sas_phy->role = PHY_ROLE_INITIATOR;
149 sas_phy->oob_mode = OOB_NOT_CONNECTED;
150 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
151 sas_phy->id = phy_id;
152 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
153 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
154 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
155 sas_phy->lldd_phy = phy;
159 * pm8001_free - free hba
160 * @pm8001_ha: our hba structure.
162 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
169 for (i = 0; i < USI_MAX_MEMCNT; i++) {
170 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
171 dma_free_coherent(&pm8001_ha->pdev->dev,
172 (pm8001_ha->memoryMap.region[i].total_len +
173 pm8001_ha->memoryMap.region[i].alignment),
174 pm8001_ha->memoryMap.region[i].virt_ptr,
175 pm8001_ha->memoryMap.region[i].phys_addr);
178 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
179 flush_workqueue(pm8001_wq);
180 kfree(pm8001_ha->tags);
184 #ifdef PM8001_USE_TASKLET
187 * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler
188 * @opaque: the passed general host adapter struct
189 * Note: pm8001_tasklet is common for pm8001 & pm80xx
191 static void pm8001_tasklet(unsigned long opaque)
193 struct pm8001_hba_info *pm8001_ha;
194 struct isr_param *irq_vector;
196 irq_vector = (struct isr_param *)opaque;
197 pm8001_ha = irq_vector->drv_inst;
198 if (unlikely(!pm8001_ha))
200 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
205 * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
206 * It obtains the vector number and calls the equivalent bottom
207 * half or services directly.
208 * @irq: interrupt number
209 * @opaque: the passed outbound queue/vector. Host structure is
210 * retrieved from the same.
212 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
214 struct isr_param *irq_vector;
215 struct pm8001_hba_info *pm8001_ha;
216 irqreturn_t ret = IRQ_HANDLED;
217 irq_vector = (struct isr_param *)opaque;
218 pm8001_ha = irq_vector->drv_inst;
220 if (unlikely(!pm8001_ha))
222 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
224 #ifdef PM8001_USE_TASKLET
225 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
227 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
233 * pm8001_interrupt_handler_intx - main INTx interrupt handler.
234 * @irq: interrupt number
235 * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
238 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
240 struct pm8001_hba_info *pm8001_ha;
241 irqreturn_t ret = IRQ_HANDLED;
242 struct sas_ha_struct *sha = dev_id;
243 pm8001_ha = sha->lldd_ha;
244 if (unlikely(!pm8001_ha))
246 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
249 #ifdef PM8001_USE_TASKLET
250 tasklet_schedule(&pm8001_ha->tasklet[0]);
252 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
257 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha);
258 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
261 * pm8001_alloc - initiate our hba structure and 6 DMAs area.
262 * @pm8001_ha: our hba structure.
263 * @ent: PCI device ID structure to match on
265 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
266 const struct pci_device_id *ent)
268 int i, count = 0, rc = 0;
269 u32 ci_offset, ib_offset, ob_offset, pi_offset;
270 struct inbound_queue_table *ibq;
271 struct outbound_queue_table *obq;
273 spin_lock_init(&pm8001_ha->lock);
274 spin_lock_init(&pm8001_ha->bitmap_lock);
275 pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n",
276 pm8001_ha->chip->n_phy);
278 /* Setup Interrupt */
279 rc = pm8001_setup_irq(pm8001_ha);
281 pm8001_dbg(pm8001_ha, FAIL,
282 "pm8001_setup_irq failed [ret: %d]\n", rc);
285 /* Request Interrupt */
286 rc = pm8001_request_irq(pm8001_ha);
290 count = pm8001_ha->max_q_num;
291 /* Queues are chosen based on the number of cores/msix availability */
292 ib_offset = pm8001_ha->ib_offset = USI_MAX_MEMCNT_BASE;
293 ci_offset = pm8001_ha->ci_offset = ib_offset + count;
294 ob_offset = pm8001_ha->ob_offset = ci_offset + count;
295 pi_offset = pm8001_ha->pi_offset = ob_offset + count;
296 pm8001_ha->max_memcnt = pi_offset + count;
298 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
299 pm8001_phy_init(pm8001_ha, i);
300 pm8001_ha->port[i].wide_port_phymap = 0;
301 pm8001_ha->port[i].port_attached = 0;
302 pm8001_ha->port[i].port_state = 0;
303 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
306 /* MPI Memory region 1 for AAP Event Log for fw */
307 pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
308 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
309 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
310 pm8001_ha->memoryMap.region[AAP1].alignment = 32;
312 /* MPI Memory region 2 for IOP Event Log for fw */
313 pm8001_ha->memoryMap.region[IOP].num_elements = 1;
314 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
315 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
316 pm8001_ha->memoryMap.region[IOP].alignment = 32;
318 for (i = 0; i < count; i++) {
319 ibq = &pm8001_ha->inbnd_q_tbl[i];
320 spin_lock_init(&ibq->iq_lock);
321 /* MPI Memory region 3 for consumer Index of inbound queues */
322 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;
323 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;
324 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;
325 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;
327 if ((ent->driver_data) != chip_8001) {
328 /* MPI Memory region 5 inbound queues */
329 pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
331 pm8001_ha->memoryMap.region[ib_offset+i].element_size
333 pm8001_ha->memoryMap.region[ib_offset+i].total_len =
334 PM8001_MPI_QUEUE * 128;
335 pm8001_ha->memoryMap.region[ib_offset+i].alignment
338 pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
340 pm8001_ha->memoryMap.region[ib_offset+i].element_size
342 pm8001_ha->memoryMap.region[ib_offset+i].total_len =
343 PM8001_MPI_QUEUE * 64;
344 pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;
348 for (i = 0; i < count; i++) {
349 obq = &pm8001_ha->outbnd_q_tbl[i];
350 spin_lock_init(&obq->oq_lock);
351 /* MPI Memory region 4 for producer Index of outbound queues */
352 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;
353 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;
354 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;
355 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;
357 if (ent->driver_data != chip_8001) {
358 /* MPI Memory region 6 Outbound queues */
359 pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
361 pm8001_ha->memoryMap.region[ob_offset+i].element_size
363 pm8001_ha->memoryMap.region[ob_offset+i].total_len =
364 PM8001_MPI_QUEUE * 128;
365 pm8001_ha->memoryMap.region[ob_offset+i].alignment
368 /* MPI Memory region 6 Outbound queues */
369 pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
371 pm8001_ha->memoryMap.region[ob_offset+i].element_size
373 pm8001_ha->memoryMap.region[ob_offset+i].total_len =
374 PM8001_MPI_QUEUE * 64;
375 pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;
379 /* Memory region write DMA*/
380 pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
381 pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
382 pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
384 /* Memory region for fw flash */
385 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
387 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
388 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
389 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
390 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
391 for (i = 0; i < pm8001_ha->max_memcnt; i++) {
392 struct mpi_mem *region = &pm8001_ha->memoryMap.region[i];
394 if (pm8001_mem_alloc(pm8001_ha->pdev,
397 ®ion->phys_addr_hi,
398 ®ion->phys_addr_lo,
400 region->alignment) != 0) {
401 pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i);
406 /* Memory region for devices*/
407 pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES
408 * sizeof(struct pm8001_device), GFP_KERNEL);
409 if (!pm8001_ha->devices) {
413 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
414 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
415 pm8001_ha->devices[i].id = i;
416 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
417 atomic_set(&pm8001_ha->devices[i].running_req, 0);
419 pm8001_ha->flags = PM8001F_INIT_TIME;
420 /* Initialize tags */
421 pm8001_tag_init(pm8001_ha);
425 scsi_remove_host(pm8001_ha->shost);
427 for (i = 0; i < pm8001_ha->max_memcnt; i++) {
428 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
429 dma_free_coherent(&pm8001_ha->pdev->dev,
430 (pm8001_ha->memoryMap.region[i].total_len +
431 pm8001_ha->memoryMap.region[i].alignment),
432 pm8001_ha->memoryMap.region[i].virt_ptr,
433 pm8001_ha->memoryMap.region[i].phys_addr);
441 * pm8001_ioremap - remap the pci high physical address to kernal virtual
442 * address so that we can access them.
443 * @pm8001_ha:our hba structure.
445 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
449 struct pci_dev *pdev;
451 pdev = pm8001_ha->pdev;
452 /* map pci mem (PMC pci base 0-3)*/
453 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
455 ** logical BARs for SPC:
456 ** bar 0 and 1 - logical BAR0
457 ** bar 2 and 3 - logical BAR1
458 ** bar4 - logical BAR2
459 ** bar5 - logical BAR3
460 ** Skip the appropriate assignments:
462 if ((bar == 1) || (bar == 3))
464 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
465 pm8001_ha->io_mem[logicalBar].membase =
466 pci_resource_start(pdev, bar);
467 pm8001_ha->io_mem[logicalBar].memsize =
468 pci_resource_len(pdev, bar);
469 pm8001_ha->io_mem[logicalBar].memvirtaddr =
470 ioremap(pm8001_ha->io_mem[logicalBar].membase,
471 pm8001_ha->io_mem[logicalBar].memsize);
472 if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) {
473 pm8001_dbg(pm8001_ha, INIT,
474 "Failed to ioremap bar %d, logicalBar %d",
478 pm8001_dbg(pm8001_ha, INIT,
479 "base addr %llx virt_addr=%llx len=%d\n",
480 (u64)pm8001_ha->io_mem[logicalBar].membase,
482 pm8001_ha->io_mem[logicalBar].memvirtaddr,
483 pm8001_ha->io_mem[logicalBar].memsize);
485 pm8001_ha->io_mem[logicalBar].membase = 0;
486 pm8001_ha->io_mem[logicalBar].memsize = 0;
487 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
495 * pm8001_pci_alloc - initialize our ha card structure
498 * @shost: scsi host struct which has been initialized before.
500 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
501 const struct pci_device_id *ent,
502 struct Scsi_Host *shost)
505 struct pm8001_hba_info *pm8001_ha;
506 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
509 pm8001_ha = sha->lldd_ha;
513 pm8001_ha->pdev = pdev;
514 pm8001_ha->dev = &pdev->dev;
515 pm8001_ha->chip_id = ent->driver_data;
516 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
517 pm8001_ha->irq = pdev->irq;
518 pm8001_ha->sas = sha;
519 pm8001_ha->shost = shost;
520 pm8001_ha->id = pm8001_id++;
521 pm8001_ha->logging_level = logging_level;
522 pm8001_ha->non_fatal_count = 0;
523 if (link_rate >= 1 && link_rate <= 15)
524 pm8001_ha->link_rate = (link_rate << 8);
526 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
527 LINKRATE_60 | LINKRATE_120;
528 pm8001_dbg(pm8001_ha, FAIL,
529 "Setting link rate to default value\n");
531 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
532 /* IOMB size is 128 for 8088/89 controllers */
533 if (pm8001_ha->chip_id != chip_8001)
534 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
536 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
538 #ifdef PM8001_USE_TASKLET
539 /* Tasklet for non msi-x interrupt handler */
540 if ((!pdev->msix_cap || !pci_msi_enabled())
541 || (pm8001_ha->chip_id == chip_8001))
542 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
543 (unsigned long)&(pm8001_ha->irq_vector[0]));
545 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
546 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
547 (unsigned long)&(pm8001_ha->irq_vector[j]));
549 if (pm8001_ioremap(pm8001_ha))
550 goto failed_pci_alloc;
551 if (!pm8001_alloc(pm8001_ha, ent))
554 pm8001_free(pm8001_ha);
559 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
562 static int pci_go_44(struct pci_dev *pdev)
566 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
568 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
570 dev_printk(KERN_ERR, &pdev->dev,
571 "32-bit DMA enable failed\n");
577 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
578 * @shost: scsi host which has been allocated outside.
579 * @chip_info: our ha struct.
581 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
582 const struct pm8001_chip_info *chip_info)
585 struct asd_sas_phy **arr_phy;
586 struct asd_sas_port **arr_port;
587 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
589 phy_nr = chip_info->n_phy;
591 memset(sha, 0x00, sizeof(*sha));
592 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
595 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
599 sha->sas_phy = arr_phy;
600 sha->sas_port = arr_port;
601 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
605 shost->transportt = pm8001_stt;
606 shost->max_id = PM8001_MAX_DEVICES;
608 shost->max_channel = 0;
609 shost->unique_id = pm8001_id;
610 shost->max_cmd_len = 16;
611 shost->can_queue = PM8001_CAN_QUEUE;
612 shost->cmd_per_lun = 32;
623 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
624 * @shost: scsi host which has been allocated outside
625 * @chip_info: our ha struct.
627 static void pm8001_post_sas_ha_init(struct Scsi_Host *shost,
628 const struct pm8001_chip_info *chip_info)
631 struct pm8001_hba_info *pm8001_ha;
632 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
634 pm8001_ha = sha->lldd_ha;
635 for (i = 0; i < chip_info->n_phy; i++) {
636 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
637 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
638 sha->sas_phy[i]->sas_addr =
639 (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
641 sha->sas_ha_name = DRV_NAME;
642 sha->dev = pm8001_ha->dev;
643 sha->strict_wide_ports = 1;
644 sha->lldd_module = THIS_MODULE;
645 sha->sas_addr = &pm8001_ha->sas_addr[0];
646 sha->num_phys = chip_info->n_phy;
647 sha->core.shost = shost;
651 * pm8001_init_sas_add - initialize sas address
652 * @pm8001_ha: our ha struct.
654 * Currently we just set the fixed SAS address to our HBA,for manufacture,
655 * it should read from the EEPROM
657 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
661 #ifdef PM8001_READ_VPD
662 /* For new SPC controllers WWN is stored in flash vpd
663 * For SPC/SPCve controllers WWN is stored in EEPROM
664 * For Older SPC WWN is stored in NVMD
666 DECLARE_COMPLETION_ONSTACK(completion);
667 struct pm8001_ioctl_payload payload;
671 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
672 pm8001_ha->nvmd_completion = &completion;
674 if (pm8001_ha->chip_id == chip_8001) {
675 if (deviceid == 0x8081 || deviceid == 0x0042) {
676 payload.minor_function = 4;
677 payload.rd_length = 4096;
679 payload.minor_function = 0;
680 payload.rd_length = 128;
682 } else if ((pm8001_ha->chip_id == chip_8070 ||
683 pm8001_ha->chip_id == chip_8072) &&
684 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
685 payload.minor_function = 4;
686 payload.rd_length = 4096;
688 payload.minor_function = 1;
689 payload.rd_length = 4096;
692 payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
693 if (!payload.func_specific) {
694 pm8001_dbg(pm8001_ha, INIT, "mem alloc fail\n");
697 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
699 kfree(payload.func_specific);
700 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
703 wait_for_completion(&completion);
705 for (i = 0, j = 0; i <= 7; i++, j++) {
706 if (pm8001_ha->chip_id == chip_8001) {
707 if (deviceid == 0x8081)
708 pm8001_ha->sas_addr[j] =
709 payload.func_specific[0x704 + i];
710 else if (deviceid == 0x0042)
711 pm8001_ha->sas_addr[j] =
712 payload.func_specific[0x010 + i];
713 } else if ((pm8001_ha->chip_id == chip_8070 ||
714 pm8001_ha->chip_id == chip_8072) &&
715 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
716 pm8001_ha->sas_addr[j] =
717 payload.func_specific[0x010 + i];
719 pm8001_ha->sas_addr[j] =
720 payload.func_specific[0x804 + i];
722 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
723 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
724 if (i && ((i % 4) == 0))
725 sas_add[7] = sas_add[7] + 4;
726 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
727 sas_add, SAS_ADDR_SIZE);
728 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i,
729 pm8001_ha->phy[i].dev_sas_addr);
731 kfree(payload.func_specific);
733 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
734 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
735 pm8001_ha->phy[i].dev_sas_addr =
737 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
739 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
745 * pm8001_get_phy_settings_info : Read phy setting values.
746 * @pm8001_ha : our hba.
748 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
751 #ifdef PM8001_READ_VPD
752 /*OPTION ROM FLASH read for the SPC cards */
753 DECLARE_COMPLETION_ONSTACK(completion);
754 struct pm8001_ioctl_payload payload;
757 pm8001_ha->nvmd_completion = &completion;
758 /* SAS ADDRESS read from flash / EEPROM */
759 payload.minor_function = 6;
761 payload.rd_length = 4096;
762 payload.func_specific = kzalloc(4096, GFP_KERNEL);
763 if (!payload.func_specific)
765 /* Read phy setting values from flash */
766 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
768 kfree(payload.func_specific);
769 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
772 wait_for_completion(&completion);
773 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
774 kfree(payload.func_specific);
779 struct pm8001_mpi3_phy_pg_trx_config {
792 * pm8001_get_internal_phy_settings : Retrieves the internal PHY settings
793 * @pm8001_ha : our adapter
794 * @phycfg : PHY config page to populate
797 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
798 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
800 phycfg->LaneLosCfg = 0x00000132;
801 phycfg->LanePgaCfg1 = 0x00203949;
802 phycfg->LanePisoCfg1 = 0x000000FF;
803 phycfg->LanePisoCfg2 = 0xFF000001;
804 phycfg->LanePisoCfg3 = 0xE7011300;
805 phycfg->LanePisoCfg4 = 0x631C40C0;
806 phycfg->LanePisoCfg5 = 0xF8102036;
807 phycfg->LanePisoCfg6 = 0xF74A1000;
808 phycfg->LaneBctCtrl = 0x00FB33F8;
812 * pm8001_get_external_phy_settings : Retrieves the external PHY settings
813 * @pm8001_ha : our adapter
814 * @phycfg : PHY config page to populate
817 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
818 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
820 phycfg->LaneLosCfg = 0x00000132;
821 phycfg->LanePgaCfg1 = 0x00203949;
822 phycfg->LanePisoCfg1 = 0x000000FF;
823 phycfg->LanePisoCfg2 = 0xFF000001;
824 phycfg->LanePisoCfg3 = 0xE7011300;
825 phycfg->LanePisoCfg4 = 0x63349140;
826 phycfg->LanePisoCfg5 = 0xF8102036;
827 phycfg->LanePisoCfg6 = 0xF80D9300;
828 phycfg->LaneBctCtrl = 0x00FB33F8;
832 * pm8001_get_phy_mask : Retrieves the mask that denotes if a PHY is int/ext
833 * @pm8001_ha : our adapter
834 * @phymask : The PHY mask
837 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
839 switch (pm8001_ha->pdev->subsystem_device) {
840 case 0x0070: /* H1280 - 8 external 0 internal */
841 case 0x0072: /* H12F0 - 16 external 0 internal */
845 case 0x0071: /* H1208 - 0 external 8 internal */
846 case 0x0073: /* H120F - 0 external 16 internal */
850 case 0x0080: /* H1244 - 4 external 4 internal */
854 case 0x0081: /* H1248 - 4 external 8 internal */
858 case 0x0082: /* H1288 - 8 external 8 internal */
863 pm8001_dbg(pm8001_ha, INIT,
864 "Unknown subsystem device=0x%.04x\n",
865 pm8001_ha->pdev->subsystem_device);
870 * pm8001_set_phy_settings_ven_117c_12G() : Configure ATTO 12Gb PHY settings
871 * @pm8001_ha : our adapter
874 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
876 struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
877 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
881 memset(&phycfg_int, 0, sizeof(phycfg_int));
882 memset(&phycfg_ext, 0, sizeof(phycfg_ext));
884 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
885 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
886 pm8001_get_phy_mask(pm8001_ha, &phymask);
888 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
889 if (phymask & (1 << i)) {/* Internal PHY */
890 pm8001_set_phy_profile_single(pm8001_ha, i,
891 sizeof(phycfg_int) / sizeof(u32),
894 } else { /* External PHY */
895 pm8001_set_phy_profile_single(pm8001_ha, i,
896 sizeof(phycfg_ext) / sizeof(u32),
905 * pm8001_configure_phy_settings : Configures PHY settings based on vendor ID.
906 * @pm8001_ha : our hba.
908 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
910 switch (pm8001_ha->pdev->subsystem_vendor) {
911 case PCI_VENDOR_ID_ATTO:
912 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
915 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
917 case PCI_VENDOR_ID_ADAPTEC2:
922 return pm8001_get_phy_settings_info(pm8001_ha);
926 #ifdef PM8001_USE_MSIX
928 * pm8001_setup_msix - enable MSI-X interrupt
929 * @pm8001_ha: our ha struct.
931 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
934 int rc, cpu_online_count;
935 unsigned int allocated_irq_vectors;
937 /* SPCv controllers supports 64 msi-x */
938 if (pm8001_ha->chip_id == chip_8001) {
941 number_of_intr = PM8001_MAX_MSIX_VEC;
944 cpu_online_count = num_online_cpus();
945 number_of_intr = min_t(int, cpu_online_count, number_of_intr);
946 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr,
947 number_of_intr, PCI_IRQ_MSIX);
948 allocated_irq_vectors = rc;
952 /* Assigns the number of interrupts */
953 number_of_intr = min_t(int, allocated_irq_vectors, number_of_intr);
954 pm8001_ha->number_of_intr = number_of_intr;
956 /* Maximum queue number updating in HBA structure */
957 pm8001_ha->max_q_num = number_of_intr;
959 pm8001_dbg(pm8001_ha, INIT,
960 "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
961 rc, pm8001_ha->number_of_intr);
965 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
968 int flag = 0, rc = 0;
969 int nr_irqs = pm8001_ha->number_of_intr;
971 if (pm8001_ha->chip_id != chip_8001)
972 flag &= ~IRQF_SHARED;
974 pm8001_dbg(pm8001_ha, INIT,
975 "pci_enable_msix request number of intr %d\n",
976 pm8001_ha->number_of_intr);
978 if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname))
979 nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname);
981 for (i = 0; i < nr_irqs; i++) {
982 snprintf(pm8001_ha->intr_drvname[i],
983 sizeof(pm8001_ha->intr_drvname[0]),
984 "%s-%d", pm8001_ha->name, i);
985 pm8001_ha->irq_vector[i].irq_id = i;
986 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
988 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
989 pm8001_interrupt_handler_msix, flag,
990 pm8001_ha->intr_drvname[i],
991 &(pm8001_ha->irq_vector[i]));
993 for (j = 0; j < i; j++) {
994 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
995 &(pm8001_ha->irq_vector[i]));
997 pci_free_irq_vectors(pm8001_ha->pdev);
1006 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha)
1008 struct pci_dev *pdev;
1010 pdev = pm8001_ha->pdev;
1012 #ifdef PM8001_USE_MSIX
1013 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
1014 return pm8001_setup_msix(pm8001_ha);
1015 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1021 * pm8001_request_irq - register interrupt
1022 * @pm8001_ha: our ha struct.
1024 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
1026 struct pci_dev *pdev;
1029 pdev = pm8001_ha->pdev;
1031 #ifdef PM8001_USE_MSIX
1032 if (pdev->msix_cap && pci_msi_enabled())
1033 return pm8001_request_msix(pm8001_ha);
1035 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1041 /* initialize the INT-X interrupt */
1042 pm8001_ha->irq_vector[0].irq_id = 0;
1043 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1044 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
1045 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost));
1050 * pm8001_pci_probe - probe supported device
1051 * @pdev: pci device which kernel has been prepared for.
1052 * @ent: pci device id
1054 * This function is the main initialization function, when register a new
1055 * pci driver it is invoked, all struct an hardware initilization should be done
1056 * here, also, register interrupt
1058 static int pm8001_pci_probe(struct pci_dev *pdev,
1059 const struct pci_device_id *ent)
1064 struct pm8001_hba_info *pm8001_ha;
1065 struct Scsi_Host *shost = NULL;
1066 const struct pm8001_chip_info *chip;
1067 struct sas_ha_struct *sha;
1069 dev_printk(KERN_INFO, &pdev->dev,
1070 "pm80xx: driver version %s\n", DRV_VERSION);
1071 rc = pci_enable_device(pdev);
1073 goto err_out_enable;
1074 pci_set_master(pdev);
1076 * Enable pci slot busmaster by setting pci command register.
1077 * This is required by FW for Cyclone card.
1080 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1082 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1083 rc = pci_request_regions(pdev, DRV_NAME);
1085 goto err_out_disable;
1086 rc = pci_go_44(pdev);
1088 goto err_out_regions;
1090 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1093 goto err_out_regions;
1095 chip = &pm8001_chips[ent->driver_data];
1096 sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1099 goto err_out_free_host;
1101 SHOST_TO_SAS_HA(shost) = sha;
1103 rc = pm8001_prep_sas_ha_init(shost, chip);
1108 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1109 /* ent->driver variable is used to differentiate between controllers */
1110 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1116 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1117 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1119 pm8001_dbg(pm8001_ha, FAIL,
1120 "chip_init failed [ret: %d]\n", rc);
1121 goto err_out_ha_free;
1124 rc = pm8001_init_ccb_tag(pm8001_ha, shost, pdev);
1126 goto err_out_enable;
1128 rc = scsi_add_host(shost, &pdev->dev);
1130 goto err_out_ha_free;
1132 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1133 if (pm8001_ha->chip_id != chip_8001) {
1134 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1135 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1136 /* setup thermal configuration. */
1137 pm80xx_set_thermal_config(pm8001_ha);
1140 pm8001_init_sas_add(pm8001_ha);
1141 /* phy setting support for motherboard controller */
1142 rc = pm8001_configure_phy_settings(pm8001_ha);
1146 pm8001_post_sas_ha_init(shost, chip);
1147 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1149 pm8001_dbg(pm8001_ha, FAIL,
1150 "sas_register_ha failed [ret: %d]\n", rc);
1153 list_add_tail(&pm8001_ha->list, &hba_list);
1154 pm8001_ha->flags = PM8001F_RUN_TIME;
1155 scsi_scan_host(pm8001_ha->shost);
1159 scsi_remove_host(pm8001_ha->shost);
1161 pm8001_free(pm8001_ha);
1165 scsi_host_put(shost);
1167 pci_release_regions(pdev);
1169 pci_disable_device(pdev);
1175 * pm8001_init_ccb_tag - allocate memory to CCB and tag.
1176 * @pm8001_ha: our hba card information.
1177 * @shost: scsi host which has been allocated outside.
1180 pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha, struct Scsi_Host *shost,
1181 struct pci_dev *pdev)
1184 u32 max_out_io, ccb_count;
1187 max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;
1188 ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);
1190 /* Update to the scsi host*/
1191 can_queue = ccb_count - PM8001_RESERVE_SLOT;
1192 shost->can_queue = can_queue;
1194 pm8001_ha->tags = kzalloc(ccb_count, GFP_KERNEL);
1195 if (!pm8001_ha->tags)
1198 /* Memory region for ccb_info*/
1199 pm8001_ha->ccb_info =
1200 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);
1201 if (!pm8001_ha->ccb_info) {
1202 pm8001_dbg(pm8001_ha, FAIL,
1203 "Unable to allocate memory for ccb\n");
1206 for (i = 0; i < ccb_count; i++) {
1207 pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(&pdev->dev,
1208 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1209 &pm8001_ha->ccb_info[i].ccb_dma_handle,
1211 if (!pm8001_ha->ccb_info[i].buf_prd) {
1212 pm8001_dbg(pm8001_ha, FAIL,
1213 "ccb prd memory allocation error\n");
1216 pm8001_ha->ccb_info[i].task = NULL;
1217 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
1218 pm8001_ha->ccb_info[i].device = NULL;
1219 ++pm8001_ha->tags_num;
1224 kfree(pm8001_ha->devices);
1229 static void pm8001_pci_remove(struct pci_dev *pdev)
1231 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1232 struct pm8001_hba_info *pm8001_ha;
1234 pm8001_ha = sha->lldd_ha;
1235 sas_unregister_ha(sha);
1236 sas_remove_host(pm8001_ha->shost);
1237 list_del(&pm8001_ha->list);
1238 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1239 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1241 #ifdef PM8001_USE_MSIX
1242 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1243 synchronize_irq(pci_irq_vector(pdev, i));
1244 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1245 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1246 pci_free_irq_vectors(pdev);
1248 free_irq(pm8001_ha->irq, sha);
1250 #ifdef PM8001_USE_TASKLET
1251 /* For non-msix and msix interrupts */
1252 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1253 (pm8001_ha->chip_id == chip_8001))
1254 tasklet_kill(&pm8001_ha->tasklet[0]);
1256 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1257 tasklet_kill(&pm8001_ha->tasklet[j]);
1259 scsi_host_put(pm8001_ha->shost);
1260 pm8001_free(pm8001_ha);
1261 kfree(sha->sas_phy);
1262 kfree(sha->sas_port);
1264 pci_release_regions(pdev);
1265 pci_disable_device(pdev);
1269 * pm8001_pci_suspend - power management suspend main entry point
1270 * @dev: Device struct
1272 * Returns 0 success, anything else error.
1274 static int __maybe_unused pm8001_pci_suspend(struct device *dev)
1276 struct pci_dev *pdev = to_pci_dev(dev);
1277 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1278 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
1280 sas_suspend_ha(sha);
1281 flush_workqueue(pm8001_wq);
1282 scsi_block_requests(pm8001_ha->shost);
1283 if (!pdev->pm_cap) {
1284 dev_err(dev, " PCI PM not supported\n");
1287 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1288 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1289 #ifdef PM8001_USE_MSIX
1290 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1291 synchronize_irq(pci_irq_vector(pdev, i));
1292 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1293 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1294 pci_free_irq_vectors(pdev);
1296 free_irq(pm8001_ha->irq, sha);
1298 #ifdef PM8001_USE_TASKLET
1299 /* For non-msix and msix interrupts */
1300 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1301 (pm8001_ha->chip_id == chip_8001))
1302 tasklet_kill(&pm8001_ha->tasklet[0]);
1304 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1305 tasklet_kill(&pm8001_ha->tasklet[j]);
1307 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering "
1308 "suspended state\n", pdev,
1314 * pm8001_pci_resume - power management resume main entry point
1315 * @dev: Device struct
1317 * Returns 0 success, anything else error.
1319 static int __maybe_unused pm8001_pci_resume(struct device *dev)
1321 struct pci_dev *pdev = to_pci_dev(dev);
1322 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1323 struct pm8001_hba_info *pm8001_ha;
1327 DECLARE_COMPLETION_ONSTACK(completion);
1328 pm8001_ha = sha->lldd_ha;
1329 device_state = pdev->current_state;
1331 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n",
1332 pdev, pm8001_ha->name, device_state);
1334 rc = pci_go_44(pdev);
1336 goto err_out_disable;
1337 sas_prep_resume_ha(sha);
1338 /* chip soft rst only for spc */
1339 if (pm8001_ha->chip_id == chip_8001) {
1340 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1341 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n");
1343 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1345 goto err_out_disable;
1347 /* disable all the interrupt bits */
1348 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1350 rc = pm8001_request_irq(pm8001_ha);
1352 goto err_out_disable;
1353 #ifdef PM8001_USE_TASKLET
1354 /* Tasklet for non msi-x interrupt handler */
1355 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1356 (pm8001_ha->chip_id == chip_8001))
1357 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1358 (unsigned long)&(pm8001_ha->irq_vector[0]));
1360 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1361 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1362 (unsigned long)&(pm8001_ha->irq_vector[j]));
1364 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1365 if (pm8001_ha->chip_id != chip_8001) {
1366 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1367 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1370 /* Chip documentation for the 8070 and 8072 SPCv */
1371 /* states that a 500ms minimum delay is required */
1372 /* before issuing commands. Otherwise, the firmware */
1373 /* will enter an unrecoverable state. */
1375 if (pm8001_ha->chip_id == chip_8070 ||
1376 pm8001_ha->chip_id == chip_8072) {
1380 /* Spin up the PHYs */
1382 pm8001_ha->flags = PM8001F_RUN_TIME;
1383 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1384 pm8001_ha->phy[i].enable_completion = &completion;
1385 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1386 wait_for_completion(&completion);
1392 scsi_remove_host(pm8001_ha->shost);
1397 /* update of pci device, vendor id and driver data with
1398 * unique value for each of the controller
1400 static struct pci_device_id pm8001_pci_table[] = {
1401 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1402 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1403 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1404 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1405 /* Support for SPC/SPCv/SPCve controllers */
1406 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1407 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1408 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1409 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1410 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1411 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1412 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1413 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1414 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1415 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1416 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1417 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1418 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1419 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1420 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1421 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1422 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1423 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1424 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1425 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1426 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1427 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1428 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1429 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1430 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1431 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1432 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1433 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1434 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1435 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1436 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1437 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1438 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1439 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1440 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1441 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1442 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1443 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1444 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1445 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1446 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1447 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1448 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1449 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1450 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1451 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1452 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1453 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1454 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1455 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1456 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1457 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1458 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1459 { PCI_VENDOR_ID_ATTO, 0x8070,
1460 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1461 { PCI_VENDOR_ID_ATTO, 0x8070,
1462 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1463 { PCI_VENDOR_ID_ATTO, 0x8072,
1464 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1465 { PCI_VENDOR_ID_ATTO, 0x8072,
1466 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1467 { PCI_VENDOR_ID_ATTO, 0x8070,
1468 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1469 { PCI_VENDOR_ID_ATTO, 0x8072,
1470 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1471 { PCI_VENDOR_ID_ATTO, 0x8072,
1472 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1473 {} /* terminate list */
1476 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops,
1480 static struct pci_driver pm8001_pci_driver = {
1482 .id_table = pm8001_pci_table,
1483 .probe = pm8001_pci_probe,
1484 .remove = pm8001_pci_remove,
1485 .driver.pm = &pm8001_pci_pm_ops,
1489 * pm8001_init - initialize scsi transport template
1491 static int __init pm8001_init(void)
1495 pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1500 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1503 rc = pci_register_driver(&pm8001_pci_driver);
1509 sas_release_transport(pm8001_stt);
1511 destroy_workqueue(pm8001_wq);
1516 static void __exit pm8001_exit(void)
1518 pci_unregister_driver(&pm8001_pci_driver);
1519 sas_release_transport(pm8001_stt);
1520 destroy_workqueue(pm8001_wq);
1523 module_init(pm8001_init);
1524 module_exit(pm8001_exit);
1526 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1527 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1528 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1529 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1531 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1532 "SAS/SATA controller driver");
1533 MODULE_VERSION(DRV_VERSION);
1534 MODULE_LICENSE("GPL");
1535 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);