2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 USI Co., Ltd.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
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14 * substantially similar to the "NO WARRANTY" disclaimer below
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16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
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19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
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37 * POSSIBILITY OF SUCH DAMAGES.
41 #include <linux/slab.h>
42 #include "pm8001_sas.h"
43 #include "pm8001_chips.h"
44 #include "pm80xx_hwi.h"
46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING;
47 module_param(logging_level, ulong, 0644);
48 MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
50 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
51 module_param(link_rate, ulong, 0644);
52 MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
53 " 1: Link rate 1.5G\n"
54 " 2: Link rate 3.0G\n"
55 " 4: Link rate 6.0G\n"
56 " 8: Link rate 12.0G\n");
58 static struct scsi_transport_template *pm8001_stt;
59 static int pm8001_init_ccb_tag(struct pm8001_hba_info *, struct Scsi_Host *, struct pci_dev *);
62 * chip info structure to identify chip key functionality as
63 * encryption available/not, no of ports, hw specific function ref
65 static const struct pm8001_chip_info pm8001_chips[] = {
66 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
67 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
68 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
69 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
70 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
71 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,},
72 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,},
73 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,},
74 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,},
75 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,},
76 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,},
82 struct workqueue_struct *pm8001_wq;
85 * The main structure which LLDD must register for scsi core.
87 static struct scsi_host_template pm8001_sht = {
88 .module = THIS_MODULE,
90 .queuecommand = sas_queuecommand,
91 .dma_need_drain = ata_scsi_dma_need_drain,
92 .target_alloc = sas_target_alloc,
93 .slave_configure = sas_slave_configure,
94 .scan_finished = pm8001_scan_finished,
95 .scan_start = pm8001_scan_start,
96 .change_queue_depth = sas_change_queue_depth,
97 .bios_param = sas_bios_param,
100 .sg_tablesize = PM8001_MAX_DMA_SG,
101 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
102 .eh_device_reset_handler = sas_eh_device_reset_handler,
103 .eh_target_reset_handler = sas_eh_target_reset_handler,
104 .target_destroy = sas_target_destroy,
107 .compat_ioctl = sas_ioctl,
109 .shost_attrs = pm8001_host_attrs,
110 .track_queue_depth = 1,
114 * Sas layer call this function to execute specific task.
116 static struct sas_domain_function_template pm8001_transport_ops = {
117 .lldd_dev_found = pm8001_dev_found,
118 .lldd_dev_gone = pm8001_dev_gone,
120 .lldd_execute_task = pm8001_queue_command,
121 .lldd_control_phy = pm8001_phy_control,
123 .lldd_abort_task = pm8001_abort_task,
124 .lldd_abort_task_set = pm8001_abort_task_set,
125 .lldd_clear_aca = pm8001_clear_aca,
126 .lldd_clear_task_set = pm8001_clear_task_set,
127 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
128 .lldd_lu_reset = pm8001_lu_reset,
129 .lldd_query_task = pm8001_query_task,
133 * pm8001_phy_init - initiate our adapter phys
134 * @pm8001_ha: our hba structure.
137 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
139 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
140 struct asd_sas_phy *sas_phy = &phy->sas_phy;
141 phy->phy_state = PHY_LINK_DISABLE;
142 phy->pm8001_ha = pm8001_ha;
143 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
144 sas_phy->class = SAS;
145 sas_phy->iproto = SAS_PROTOCOL_ALL;
147 sas_phy->type = PHY_TYPE_PHYSICAL;
148 sas_phy->role = PHY_ROLE_INITIATOR;
149 sas_phy->oob_mode = OOB_NOT_CONNECTED;
150 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
151 sas_phy->id = phy_id;
152 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
153 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
154 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
155 sas_phy->lldd_phy = phy;
159 * pm8001_free - free hba
160 * @pm8001_ha: our hba structure.
162 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
169 for (i = 0; i < USI_MAX_MEMCNT; i++) {
170 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
171 dma_free_coherent(&pm8001_ha->pdev->dev,
172 (pm8001_ha->memoryMap.region[i].total_len +
173 pm8001_ha->memoryMap.region[i].alignment),
174 pm8001_ha->memoryMap.region[i].virt_ptr,
175 pm8001_ha->memoryMap.region[i].phys_addr);
178 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
179 flush_workqueue(pm8001_wq);
180 kfree(pm8001_ha->tags);
184 #ifdef PM8001_USE_TASKLET
187 * tasklet for 64 msi-x interrupt handler
188 * @opaque: the passed general host adapter struct
189 * Note: pm8001_tasklet is common for pm8001 & pm80xx
191 static void pm8001_tasklet(unsigned long opaque)
193 struct pm8001_hba_info *pm8001_ha;
194 struct isr_param *irq_vector;
196 irq_vector = (struct isr_param *)opaque;
197 pm8001_ha = irq_vector->drv_inst;
198 if (unlikely(!pm8001_ha))
200 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
205 * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
206 * It obtains the vector number and calls the equivalent bottom
207 * half or services directly.
208 * @irq: interrupt number
209 * @opaque: the passed outbound queue/vector. Host structure is
210 * retrieved from the same.
212 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
214 struct isr_param *irq_vector;
215 struct pm8001_hba_info *pm8001_ha;
216 irqreturn_t ret = IRQ_HANDLED;
217 irq_vector = (struct isr_param *)opaque;
218 pm8001_ha = irq_vector->drv_inst;
220 if (unlikely(!pm8001_ha))
222 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
224 #ifdef PM8001_USE_TASKLET
225 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
227 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
233 * pm8001_interrupt_handler_intx - main INTx interrupt handler.
234 * @irq: interrupt number
235 * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
238 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
240 struct pm8001_hba_info *pm8001_ha;
241 irqreturn_t ret = IRQ_HANDLED;
242 struct sas_ha_struct *sha = dev_id;
243 pm8001_ha = sha->lldd_ha;
244 if (unlikely(!pm8001_ha))
246 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
249 #ifdef PM8001_USE_TASKLET
250 tasklet_schedule(&pm8001_ha->tasklet[0]);
252 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
257 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha);
258 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
261 * pm8001_alloc - initiate our hba structure and 6 DMAs area.
262 * @pm8001_ha: our hba structure.
263 * @ent: PCI device ID structure to match on
265 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
266 const struct pci_device_id *ent)
268 int i, count = 0, rc = 0;
269 u32 ci_offset, ib_offset, ob_offset, pi_offset;
270 struct inbound_queue_table *circularQ;
272 spin_lock_init(&pm8001_ha->lock);
273 spin_lock_init(&pm8001_ha->bitmap_lock);
274 pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n",
275 pm8001_ha->chip->n_phy);
277 /* Setup Interrupt */
278 rc = pm8001_setup_irq(pm8001_ha);
280 pm8001_dbg(pm8001_ha, FAIL,
281 "pm8001_setup_irq failed [ret: %d]\n", rc);
284 /* Request Interrupt */
285 rc = pm8001_request_irq(pm8001_ha);
289 count = pm8001_ha->max_q_num;
290 /* Queues are chosen based on the number of cores/msix availability */
291 ib_offset = pm8001_ha->ib_offset = USI_MAX_MEMCNT_BASE;
292 ci_offset = pm8001_ha->ci_offset = ib_offset + count;
293 ob_offset = pm8001_ha->ob_offset = ci_offset + count;
294 pi_offset = pm8001_ha->pi_offset = ob_offset + count;
295 pm8001_ha->max_memcnt = pi_offset + count;
297 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
298 pm8001_phy_init(pm8001_ha, i);
299 pm8001_ha->port[i].wide_port_phymap = 0;
300 pm8001_ha->port[i].port_attached = 0;
301 pm8001_ha->port[i].port_state = 0;
302 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
305 /* MPI Memory region 1 for AAP Event Log for fw */
306 pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
307 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
308 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
309 pm8001_ha->memoryMap.region[AAP1].alignment = 32;
311 /* MPI Memory region 2 for IOP Event Log for fw */
312 pm8001_ha->memoryMap.region[IOP].num_elements = 1;
313 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
314 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
315 pm8001_ha->memoryMap.region[IOP].alignment = 32;
317 for (i = 0; i < count; i++) {
318 circularQ = &pm8001_ha->inbnd_q_tbl[i];
319 spin_lock_init(&circularQ->iq_lock);
320 /* MPI Memory region 3 for consumer Index of inbound queues */
321 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;
322 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;
323 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;
324 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;
326 if ((ent->driver_data) != chip_8001) {
327 /* MPI Memory region 5 inbound queues */
328 pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
330 pm8001_ha->memoryMap.region[ib_offset+i].element_size
332 pm8001_ha->memoryMap.region[ib_offset+i].total_len =
333 PM8001_MPI_QUEUE * 128;
334 pm8001_ha->memoryMap.region[ib_offset+i].alignment
337 pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
339 pm8001_ha->memoryMap.region[ib_offset+i].element_size
341 pm8001_ha->memoryMap.region[ib_offset+i].total_len =
342 PM8001_MPI_QUEUE * 64;
343 pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;
347 for (i = 0; i < count; i++) {
348 /* MPI Memory region 4 for producer Index of outbound queues */
349 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;
350 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;
351 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;
352 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;
354 if (ent->driver_data != chip_8001) {
355 /* MPI Memory region 6 Outbound queues */
356 pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
358 pm8001_ha->memoryMap.region[ob_offset+i].element_size
360 pm8001_ha->memoryMap.region[ob_offset+i].total_len =
361 PM8001_MPI_QUEUE * 128;
362 pm8001_ha->memoryMap.region[ob_offset+i].alignment
365 /* MPI Memory region 6 Outbound queues */
366 pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
368 pm8001_ha->memoryMap.region[ob_offset+i].element_size
370 pm8001_ha->memoryMap.region[ob_offset+i].total_len =
371 PM8001_MPI_QUEUE * 64;
372 pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;
376 /* Memory region write DMA*/
377 pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
378 pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
379 pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
381 /* Memory region for fw flash */
382 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
384 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
385 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
386 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
387 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
388 for (i = 0; i < pm8001_ha->max_memcnt; i++) {
389 struct mpi_mem *region = &pm8001_ha->memoryMap.region[i];
391 if (pm8001_mem_alloc(pm8001_ha->pdev,
394 ®ion->phys_addr_hi,
395 ®ion->phys_addr_lo,
397 region->alignment) != 0) {
398 pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i);
403 /* Memory region for devices*/
404 pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES
405 * sizeof(struct pm8001_device), GFP_KERNEL);
406 if (!pm8001_ha->devices) {
410 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
411 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
412 pm8001_ha->devices[i].id = i;
413 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
414 atomic_set(&pm8001_ha->devices[i].running_req, 0);
416 pm8001_ha->flags = PM8001F_INIT_TIME;
417 /* Initialize tags */
418 pm8001_tag_init(pm8001_ha);
422 scsi_remove_host(pm8001_ha->shost);
424 for (i = 0; i < pm8001_ha->max_memcnt; i++) {
425 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
426 dma_free_coherent(&pm8001_ha->pdev->dev,
427 (pm8001_ha->memoryMap.region[i].total_len +
428 pm8001_ha->memoryMap.region[i].alignment),
429 pm8001_ha->memoryMap.region[i].virt_ptr,
430 pm8001_ha->memoryMap.region[i].phys_addr);
438 * pm8001_ioremap - remap the pci high physical address to kernal virtual
439 * address so that we can access them.
440 * @pm8001_ha:our hba structure.
442 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
446 struct pci_dev *pdev;
448 pdev = pm8001_ha->pdev;
449 /* map pci mem (PMC pci base 0-3)*/
450 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
452 ** logical BARs for SPC:
453 ** bar 0 and 1 - logical BAR0
454 ** bar 2 and 3 - logical BAR1
455 ** bar4 - logical BAR2
456 ** bar5 - logical BAR3
457 ** Skip the appropriate assignments:
459 if ((bar == 1) || (bar == 3))
461 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
462 pm8001_ha->io_mem[logicalBar].membase =
463 pci_resource_start(pdev, bar);
464 pm8001_ha->io_mem[logicalBar].memsize =
465 pci_resource_len(pdev, bar);
466 pm8001_ha->io_mem[logicalBar].memvirtaddr =
467 ioremap(pm8001_ha->io_mem[logicalBar].membase,
468 pm8001_ha->io_mem[logicalBar].memsize);
469 if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) {
470 pm8001_dbg(pm8001_ha, INIT,
471 "Failed to ioremap bar %d, logicalBar %d",
475 pm8001_dbg(pm8001_ha, INIT,
476 "base addr %llx virt_addr=%llx len=%d\n",
477 (u64)pm8001_ha->io_mem[logicalBar].membase,
479 pm8001_ha->io_mem[logicalBar].memvirtaddr,
480 pm8001_ha->io_mem[logicalBar].memsize);
482 pm8001_ha->io_mem[logicalBar].membase = 0;
483 pm8001_ha->io_mem[logicalBar].memsize = 0;
484 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
492 * pm8001_pci_alloc - initialize our ha card structure
495 * @shost: scsi host struct which has been initialized before.
497 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
498 const struct pci_device_id *ent,
499 struct Scsi_Host *shost)
502 struct pm8001_hba_info *pm8001_ha;
503 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
506 pm8001_ha = sha->lldd_ha;
510 pm8001_ha->pdev = pdev;
511 pm8001_ha->dev = &pdev->dev;
512 pm8001_ha->chip_id = ent->driver_data;
513 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
514 pm8001_ha->irq = pdev->irq;
515 pm8001_ha->sas = sha;
516 pm8001_ha->shost = shost;
517 pm8001_ha->id = pm8001_id++;
518 pm8001_ha->logging_level = logging_level;
519 pm8001_ha->non_fatal_count = 0;
520 if (link_rate >= 1 && link_rate <= 15)
521 pm8001_ha->link_rate = (link_rate << 8);
523 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
524 LINKRATE_60 | LINKRATE_120;
525 pm8001_dbg(pm8001_ha, FAIL,
526 "Setting link rate to default value\n");
528 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
529 /* IOMB size is 128 for 8088/89 controllers */
530 if (pm8001_ha->chip_id != chip_8001)
531 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
533 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
535 #ifdef PM8001_USE_TASKLET
536 /* Tasklet for non msi-x interrupt handler */
537 if ((!pdev->msix_cap || !pci_msi_enabled())
538 || (pm8001_ha->chip_id == chip_8001))
539 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
540 (unsigned long)&(pm8001_ha->irq_vector[0]));
542 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
543 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
544 (unsigned long)&(pm8001_ha->irq_vector[j]));
546 if (pm8001_ioremap(pm8001_ha))
547 goto failed_pci_alloc;
548 if (!pm8001_alloc(pm8001_ha, ent))
551 pm8001_free(pm8001_ha);
556 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
559 static int pci_go_44(struct pci_dev *pdev)
563 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
565 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
567 dev_printk(KERN_ERR, &pdev->dev,
568 "32-bit DMA enable failed\n");
574 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
575 * @shost: scsi host which has been allocated outside.
576 * @chip_info: our ha struct.
578 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
579 const struct pm8001_chip_info *chip_info)
582 struct asd_sas_phy **arr_phy;
583 struct asd_sas_port **arr_port;
584 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
586 phy_nr = chip_info->n_phy;
588 memset(sha, 0x00, sizeof(*sha));
589 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
592 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
596 sha->sas_phy = arr_phy;
597 sha->sas_port = arr_port;
598 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
602 shost->transportt = pm8001_stt;
603 shost->max_id = PM8001_MAX_DEVICES;
605 shost->max_channel = 0;
606 shost->unique_id = pm8001_id;
607 shost->max_cmd_len = 16;
608 shost->can_queue = PM8001_CAN_QUEUE;
609 shost->cmd_per_lun = 32;
620 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
621 * @shost: scsi host which has been allocated outside
622 * @chip_info: our ha struct.
624 static void pm8001_post_sas_ha_init(struct Scsi_Host *shost,
625 const struct pm8001_chip_info *chip_info)
628 struct pm8001_hba_info *pm8001_ha;
629 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
631 pm8001_ha = sha->lldd_ha;
632 for (i = 0; i < chip_info->n_phy; i++) {
633 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
634 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
635 sha->sas_phy[i]->sas_addr =
636 (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
638 sha->sas_ha_name = DRV_NAME;
639 sha->dev = pm8001_ha->dev;
640 sha->strict_wide_ports = 1;
641 sha->lldd_module = THIS_MODULE;
642 sha->sas_addr = &pm8001_ha->sas_addr[0];
643 sha->num_phys = chip_info->n_phy;
644 sha->core.shost = shost;
648 * pm8001_init_sas_add - initialize sas address
649 * @pm8001_ha: our ha struct.
651 * Currently we just set the fixed SAS address to our HBA,for manufacture,
652 * it should read from the EEPROM
654 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
658 #ifdef PM8001_READ_VPD
659 /* For new SPC controllers WWN is stored in flash vpd
660 * For SPC/SPCve controllers WWN is stored in EEPROM
661 * For Older SPC WWN is stored in NVMD
663 DECLARE_COMPLETION_ONSTACK(completion);
664 struct pm8001_ioctl_payload payload;
668 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
669 pm8001_ha->nvmd_completion = &completion;
671 if (pm8001_ha->chip_id == chip_8001) {
672 if (deviceid == 0x8081 || deviceid == 0x0042) {
673 payload.minor_function = 4;
674 payload.rd_length = 4096;
676 payload.minor_function = 0;
677 payload.rd_length = 128;
679 } else if ((pm8001_ha->chip_id == chip_8070 ||
680 pm8001_ha->chip_id == chip_8072) &&
681 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
682 payload.minor_function = 4;
683 payload.rd_length = 4096;
685 payload.minor_function = 1;
686 payload.rd_length = 4096;
689 payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
690 if (!payload.func_specific) {
691 pm8001_dbg(pm8001_ha, INIT, "mem alloc fail\n");
694 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
696 kfree(payload.func_specific);
697 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
700 wait_for_completion(&completion);
702 for (i = 0, j = 0; i <= 7; i++, j++) {
703 if (pm8001_ha->chip_id == chip_8001) {
704 if (deviceid == 0x8081)
705 pm8001_ha->sas_addr[j] =
706 payload.func_specific[0x704 + i];
707 else if (deviceid == 0x0042)
708 pm8001_ha->sas_addr[j] =
709 payload.func_specific[0x010 + i];
710 } else if ((pm8001_ha->chip_id == chip_8070 ||
711 pm8001_ha->chip_id == chip_8072) &&
712 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
713 pm8001_ha->sas_addr[j] =
714 payload.func_specific[0x010 + i];
716 pm8001_ha->sas_addr[j] =
717 payload.func_specific[0x804 + i];
719 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
720 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
721 if (i && ((i % 4) == 0))
722 sas_add[7] = sas_add[7] + 4;
723 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
724 sas_add, SAS_ADDR_SIZE);
725 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i,
726 pm8001_ha->phy[i].dev_sas_addr);
728 kfree(payload.func_specific);
730 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
731 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
732 pm8001_ha->phy[i].dev_sas_addr =
734 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
736 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
742 * pm8001_get_phy_settings_info : Read phy setting values.
743 * @pm8001_ha : our hba.
745 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
748 #ifdef PM8001_READ_VPD
749 /*OPTION ROM FLASH read for the SPC cards */
750 DECLARE_COMPLETION_ONSTACK(completion);
751 struct pm8001_ioctl_payload payload;
754 pm8001_ha->nvmd_completion = &completion;
755 /* SAS ADDRESS read from flash / EEPROM */
756 payload.minor_function = 6;
758 payload.rd_length = 4096;
759 payload.func_specific = kzalloc(4096, GFP_KERNEL);
760 if (!payload.func_specific)
762 /* Read phy setting values from flash */
763 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
765 kfree(payload.func_specific);
766 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
769 wait_for_completion(&completion);
770 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
771 kfree(payload.func_specific);
776 struct pm8001_mpi3_phy_pg_trx_config {
789 * pm8001_get_internal_phy_settings : Retrieves the internal PHY settings
790 * @pm8001_ha : our adapter
791 * @phycfg : PHY config page to populate
794 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
795 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
797 phycfg->LaneLosCfg = 0x00000132;
798 phycfg->LanePgaCfg1 = 0x00203949;
799 phycfg->LanePisoCfg1 = 0x000000FF;
800 phycfg->LanePisoCfg2 = 0xFF000001;
801 phycfg->LanePisoCfg3 = 0xE7011300;
802 phycfg->LanePisoCfg4 = 0x631C40C0;
803 phycfg->LanePisoCfg5 = 0xF8102036;
804 phycfg->LanePisoCfg6 = 0xF74A1000;
805 phycfg->LaneBctCtrl = 0x00FB33F8;
809 * pm8001_get_external_phy_settings : Retrieves the external PHY settings
810 * @pm8001_ha : our adapter
811 * @phycfg : PHY config page to populate
814 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
815 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
817 phycfg->LaneLosCfg = 0x00000132;
818 phycfg->LanePgaCfg1 = 0x00203949;
819 phycfg->LanePisoCfg1 = 0x000000FF;
820 phycfg->LanePisoCfg2 = 0xFF000001;
821 phycfg->LanePisoCfg3 = 0xE7011300;
822 phycfg->LanePisoCfg4 = 0x63349140;
823 phycfg->LanePisoCfg5 = 0xF8102036;
824 phycfg->LanePisoCfg6 = 0xF80D9300;
825 phycfg->LaneBctCtrl = 0x00FB33F8;
829 * pm8001_get_phy_mask : Retrieves the mask that denotes if a PHY is int/ext
830 * @pm8001_ha : our adapter
831 * @phymask : The PHY mask
834 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
836 switch (pm8001_ha->pdev->subsystem_device) {
837 case 0x0070: /* H1280 - 8 external 0 internal */
838 case 0x0072: /* H12F0 - 16 external 0 internal */
842 case 0x0071: /* H1208 - 0 external 8 internal */
843 case 0x0073: /* H120F - 0 external 16 internal */
847 case 0x0080: /* H1244 - 4 external 4 internal */
851 case 0x0081: /* H1248 - 4 external 8 internal */
855 case 0x0082: /* H1288 - 8 external 8 internal */
860 pm8001_dbg(pm8001_ha, INIT,
861 "Unknown subsystem device=0x%.04x\n",
862 pm8001_ha->pdev->subsystem_device);
867 * pm8001_set_phy_settings_ven_117c_12Gb : Configure ATTO 12Gb PHY settings
868 * @pm8001_ha : our adapter
871 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
873 struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
874 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
878 memset(&phycfg_int, 0, sizeof(phycfg_int));
879 memset(&phycfg_ext, 0, sizeof(phycfg_ext));
881 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
882 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
883 pm8001_get_phy_mask(pm8001_ha, &phymask);
885 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
886 if (phymask & (1 << i)) {/* Internal PHY */
887 pm8001_set_phy_profile_single(pm8001_ha, i,
888 sizeof(phycfg_int) / sizeof(u32),
891 } else { /* External PHY */
892 pm8001_set_phy_profile_single(pm8001_ha, i,
893 sizeof(phycfg_ext) / sizeof(u32),
902 * pm8001_configure_phy_settings : Configures PHY settings based on vendor ID.
903 * @pm8001_ha : our hba.
905 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
907 switch (pm8001_ha->pdev->subsystem_vendor) {
908 case PCI_VENDOR_ID_ATTO:
909 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
912 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
914 case PCI_VENDOR_ID_ADAPTEC2:
919 return pm8001_get_phy_settings_info(pm8001_ha);
923 #ifdef PM8001_USE_MSIX
925 * pm8001_setup_msix - enable MSI-X interrupt
926 * @pm8001_ha: our ha struct.
928 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
931 int rc, cpu_online_count;
932 unsigned int allocated_irq_vectors;
934 /* SPCv controllers supports 64 msi-x */
935 if (pm8001_ha->chip_id == chip_8001) {
938 number_of_intr = PM8001_MAX_MSIX_VEC;
941 cpu_online_count = num_online_cpus();
942 number_of_intr = min_t(int, cpu_online_count, number_of_intr);
943 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr,
944 number_of_intr, PCI_IRQ_MSIX);
945 allocated_irq_vectors = rc;
949 /* Assigns the number of interrupts */
950 number_of_intr = min_t(int, allocated_irq_vectors, number_of_intr);
951 pm8001_ha->number_of_intr = number_of_intr;
953 /* Maximum queue number updating in HBA structure */
954 pm8001_ha->max_q_num = number_of_intr;
956 pm8001_dbg(pm8001_ha, INIT,
957 "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
958 rc, pm8001_ha->number_of_intr);
962 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
965 int flag = 0, rc = 0;
967 if (pm8001_ha->chip_id != chip_8001)
968 flag &= ~IRQF_SHARED;
970 pm8001_dbg(pm8001_ha, INIT,
971 "pci_enable_msix request number of intr %d\n",
972 pm8001_ha->number_of_intr);
974 for (i = 0; i < pm8001_ha->number_of_intr; i++) {
975 snprintf(pm8001_ha->intr_drvname[i],
976 sizeof(pm8001_ha->intr_drvname[0]),
977 "%s-%d", pm8001_ha->name, i);
978 pm8001_ha->irq_vector[i].irq_id = i;
979 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
981 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
982 pm8001_interrupt_handler_msix, flag,
983 pm8001_ha->intr_drvname[i],
984 &(pm8001_ha->irq_vector[i]));
986 for (j = 0; j < i; j++) {
987 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
988 &(pm8001_ha->irq_vector[i]));
990 pci_free_irq_vectors(pm8001_ha->pdev);
999 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha)
1001 struct pci_dev *pdev;
1003 pdev = pm8001_ha->pdev;
1005 #ifdef PM8001_USE_MSIX
1006 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
1007 return pm8001_setup_msix(pm8001_ha);
1008 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1014 * pm8001_request_irq - register interrupt
1015 * @pm8001_ha: our ha struct.
1017 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
1019 struct pci_dev *pdev;
1022 pdev = pm8001_ha->pdev;
1024 #ifdef PM8001_USE_MSIX
1025 if (pdev->msix_cap && pci_msi_enabled())
1026 return pm8001_request_msix(pm8001_ha);
1028 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1034 /* initialize the INT-X interrupt */
1035 pm8001_ha->irq_vector[0].irq_id = 0;
1036 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1037 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
1038 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost));
1043 * pm8001_pci_probe - probe supported device
1044 * @pdev: pci device which kernel has been prepared for.
1045 * @ent: pci device id
1047 * This function is the main initialization function, when register a new
1048 * pci driver it is invoked, all struct an hardware initilization should be done
1049 * here, also, register interrupt
1051 static int pm8001_pci_probe(struct pci_dev *pdev,
1052 const struct pci_device_id *ent)
1057 struct pm8001_hba_info *pm8001_ha;
1058 struct Scsi_Host *shost = NULL;
1059 const struct pm8001_chip_info *chip;
1060 struct sas_ha_struct *sha;
1062 dev_printk(KERN_INFO, &pdev->dev,
1063 "pm80xx: driver version %s\n", DRV_VERSION);
1064 rc = pci_enable_device(pdev);
1066 goto err_out_enable;
1067 pci_set_master(pdev);
1069 * Enable pci slot busmaster by setting pci command register.
1070 * This is required by FW for Cyclone card.
1073 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1075 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1076 rc = pci_request_regions(pdev, DRV_NAME);
1078 goto err_out_disable;
1079 rc = pci_go_44(pdev);
1081 goto err_out_regions;
1083 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1086 goto err_out_regions;
1088 chip = &pm8001_chips[ent->driver_data];
1089 sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1092 goto err_out_free_host;
1094 SHOST_TO_SAS_HA(shost) = sha;
1096 rc = pm8001_prep_sas_ha_init(shost, chip);
1101 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1102 /* ent->driver variable is used to differentiate between controllers */
1103 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1109 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1110 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1112 pm8001_dbg(pm8001_ha, FAIL,
1113 "chip_init failed [ret: %d]\n", rc);
1114 goto err_out_ha_free;
1117 rc = pm8001_init_ccb_tag(pm8001_ha, shost, pdev);
1119 goto err_out_enable;
1121 rc = scsi_add_host(shost, &pdev->dev);
1123 goto err_out_ha_free;
1125 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1126 if (pm8001_ha->chip_id != chip_8001) {
1127 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1128 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1129 /* setup thermal configuration. */
1130 pm80xx_set_thermal_config(pm8001_ha);
1133 pm8001_init_sas_add(pm8001_ha);
1134 /* phy setting support for motherboard controller */
1135 rc = pm8001_configure_phy_settings(pm8001_ha);
1139 pm8001_post_sas_ha_init(shost, chip);
1140 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1142 pm8001_dbg(pm8001_ha, FAIL,
1143 "sas_register_ha failed [ret: %d]\n", rc);
1146 list_add_tail(&pm8001_ha->list, &hba_list);
1147 scsi_scan_host(pm8001_ha->shost);
1148 pm8001_ha->flags = PM8001F_RUN_TIME;
1152 scsi_remove_host(pm8001_ha->shost);
1154 pm8001_free(pm8001_ha);
1158 scsi_host_put(shost);
1160 pci_release_regions(pdev);
1162 pci_disable_device(pdev);
1168 * pm8001_init_ccb_tag - allocate memory to CCB and tag.
1169 * @pm8001_ha: our hba card information.
1170 * @shost: scsi host which has been allocated outside.
1173 pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha, struct Scsi_Host *shost,
1174 struct pci_dev *pdev)
1177 u32 max_out_io, ccb_count;
1180 max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;
1181 ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);
1183 /* Update to the scsi host*/
1184 can_queue = ccb_count - PM8001_RESERVE_SLOT;
1185 shost->can_queue = can_queue;
1187 pm8001_ha->tags = kzalloc(ccb_count, GFP_KERNEL);
1188 if (!pm8001_ha->tags)
1191 /* Memory region for ccb_info*/
1192 pm8001_ha->ccb_info =
1193 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);
1194 if (!pm8001_ha->ccb_info) {
1195 pm8001_dbg(pm8001_ha, FAIL,
1196 "Unable to allocate memory for ccb\n");
1199 for (i = 0; i < ccb_count; i++) {
1200 pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(&pdev->dev,
1201 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1202 &pm8001_ha->ccb_info[i].ccb_dma_handle,
1204 if (!pm8001_ha->ccb_info[i].buf_prd) {
1205 pm8001_dbg(pm8001_ha, FAIL,
1206 "ccb prd memory allocation error\n");
1209 pm8001_ha->ccb_info[i].task = NULL;
1210 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
1211 pm8001_ha->ccb_info[i].device = NULL;
1212 ++pm8001_ha->tags_num;
1217 kfree(pm8001_ha->devices);
1222 static void pm8001_pci_remove(struct pci_dev *pdev)
1224 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1225 struct pm8001_hba_info *pm8001_ha;
1227 pm8001_ha = sha->lldd_ha;
1228 sas_unregister_ha(sha);
1229 sas_remove_host(pm8001_ha->shost);
1230 list_del(&pm8001_ha->list);
1231 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1232 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1234 #ifdef PM8001_USE_MSIX
1235 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1236 synchronize_irq(pci_irq_vector(pdev, i));
1237 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1238 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1239 pci_free_irq_vectors(pdev);
1241 free_irq(pm8001_ha->irq, sha);
1243 #ifdef PM8001_USE_TASKLET
1244 /* For non-msix and msix interrupts */
1245 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1246 (pm8001_ha->chip_id == chip_8001))
1247 tasklet_kill(&pm8001_ha->tasklet[0]);
1249 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1250 tasklet_kill(&pm8001_ha->tasklet[j]);
1252 scsi_host_put(pm8001_ha->shost);
1253 pm8001_free(pm8001_ha);
1254 kfree(sha->sas_phy);
1255 kfree(sha->sas_port);
1257 pci_release_regions(pdev);
1258 pci_disable_device(pdev);
1262 * pm8001_pci_suspend - power management suspend main entry point
1263 * @dev: Device struct
1265 * Returns 0 success, anything else error.
1267 static int __maybe_unused pm8001_pci_suspend(struct device *dev)
1269 struct pci_dev *pdev = to_pci_dev(dev);
1270 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1271 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
1273 sas_suspend_ha(sha);
1274 flush_workqueue(pm8001_wq);
1275 scsi_block_requests(pm8001_ha->shost);
1276 if (!pdev->pm_cap) {
1277 dev_err(dev, " PCI PM not supported\n");
1280 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1281 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1282 #ifdef PM8001_USE_MSIX
1283 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1284 synchronize_irq(pci_irq_vector(pdev, i));
1285 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1286 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1287 pci_free_irq_vectors(pdev);
1289 free_irq(pm8001_ha->irq, sha);
1291 #ifdef PM8001_USE_TASKLET
1292 /* For non-msix and msix interrupts */
1293 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1294 (pm8001_ha->chip_id == chip_8001))
1295 tasklet_kill(&pm8001_ha->tasklet[0]);
1297 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1298 tasklet_kill(&pm8001_ha->tasklet[j]);
1300 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering "
1301 "suspended state\n", pdev,
1307 * pm8001_pci_resume - power management resume main entry point
1308 * @dev: Device struct
1310 * Returns 0 success, anything else error.
1312 static int __maybe_unused pm8001_pci_resume(struct device *dev)
1314 struct pci_dev *pdev = to_pci_dev(dev);
1315 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1316 struct pm8001_hba_info *pm8001_ha;
1320 DECLARE_COMPLETION_ONSTACK(completion);
1321 pm8001_ha = sha->lldd_ha;
1322 device_state = pdev->current_state;
1324 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n",
1325 pdev, pm8001_ha->name, device_state);
1327 rc = pci_go_44(pdev);
1329 goto err_out_disable;
1330 sas_prep_resume_ha(sha);
1331 /* chip soft rst only for spc */
1332 if (pm8001_ha->chip_id == chip_8001) {
1333 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1334 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n");
1336 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1338 goto err_out_disable;
1340 /* disable all the interrupt bits */
1341 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1343 rc = pm8001_request_irq(pm8001_ha);
1345 goto err_out_disable;
1346 #ifdef PM8001_USE_TASKLET
1347 /* Tasklet for non msi-x interrupt handler */
1348 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1349 (pm8001_ha->chip_id == chip_8001))
1350 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1351 (unsigned long)&(pm8001_ha->irq_vector[0]));
1353 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1354 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1355 (unsigned long)&(pm8001_ha->irq_vector[j]));
1357 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1358 if (pm8001_ha->chip_id != chip_8001) {
1359 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1360 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1363 /* Chip documentation for the 8070 and 8072 SPCv */
1364 /* states that a 500ms minimum delay is required */
1365 /* before issuing commands. Otherwise, the firmware */
1366 /* will enter an unrecoverable state. */
1368 if (pm8001_ha->chip_id == chip_8070 ||
1369 pm8001_ha->chip_id == chip_8072) {
1373 /* Spin up the PHYs */
1375 pm8001_ha->flags = PM8001F_RUN_TIME;
1376 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1377 pm8001_ha->phy[i].enable_completion = &completion;
1378 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1379 wait_for_completion(&completion);
1385 scsi_remove_host(pm8001_ha->shost);
1390 /* update of pci device, vendor id and driver data with
1391 * unique value for each of the controller
1393 static struct pci_device_id pm8001_pci_table[] = {
1394 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1395 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1396 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1397 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1398 /* Support for SPC/SPCv/SPCve controllers */
1399 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1400 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1401 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1402 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1403 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1404 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1405 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1406 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1407 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1408 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1409 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1410 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1411 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1412 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1413 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1414 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1415 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1416 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1417 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1418 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1419 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1420 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1421 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1422 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1423 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1424 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1425 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1426 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1427 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1428 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1429 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1430 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1431 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1432 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1433 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1434 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1435 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1436 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1437 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1438 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1439 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1440 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1441 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1442 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1443 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1444 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1445 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1446 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1447 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1448 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1449 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1450 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1451 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1452 { PCI_VENDOR_ID_ATTO, 0x8070,
1453 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1454 { PCI_VENDOR_ID_ATTO, 0x8070,
1455 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1456 { PCI_VENDOR_ID_ATTO, 0x8072,
1457 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1458 { PCI_VENDOR_ID_ATTO, 0x8072,
1459 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1460 { PCI_VENDOR_ID_ATTO, 0x8070,
1461 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1462 { PCI_VENDOR_ID_ATTO, 0x8072,
1463 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1464 { PCI_VENDOR_ID_ATTO, 0x8072,
1465 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1466 {} /* terminate list */
1469 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops,
1473 static struct pci_driver pm8001_pci_driver = {
1475 .id_table = pm8001_pci_table,
1476 .probe = pm8001_pci_probe,
1477 .remove = pm8001_pci_remove,
1478 .driver.pm = &pm8001_pci_pm_ops,
1482 * pm8001_init - initialize scsi transport template
1484 static int __init pm8001_init(void)
1488 pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1493 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1496 rc = pci_register_driver(&pm8001_pci_driver);
1502 sas_release_transport(pm8001_stt);
1504 destroy_workqueue(pm8001_wq);
1509 static void __exit pm8001_exit(void)
1511 pci_unregister_driver(&pm8001_pci_driver);
1512 sas_release_transport(pm8001_stt);
1513 destroy_workqueue(pm8001_wq);
1516 module_init(pm8001_init);
1517 module_exit(pm8001_exit);
1519 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1520 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1521 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1522 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1524 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1525 "SAS/SATA controller driver");
1526 MODULE_VERSION(DRV_VERSION);
1527 MODULE_LICENSE("GPL");
1528 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);