drivers/scsi/pm8001/pm8001_init.c

   1 /*
   2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40
  41 #include <linux/slab.h>
  42 #include "pm8001_sas.h"
  43 #include "pm8001_chips.h"
  44 #include "pm80xx_hwi.h"
  45
  46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING;
  47 module_param(logging_level, ulong, 0644);
  48 MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
  49
  50 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
  51 module_param(link_rate, ulong, 0644);
  52 MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
  53                 " 1: Link rate 1.5G\n"
  54                 " 2: Link rate 3.0G\n"
  55                 " 4: Link rate 6.0G\n"
  56                 " 8: Link rate 12.0G\n");
  57
  58 static struct scsi_transport_template *pm8001_stt;
  59 static int pm8001_init_ccb_tag(struct pm8001_hba_info *, struct Scsi_Host *, struct pci_dev *);
  60
  61 /*
  62  * chip info structure to identify chip key functionality as
  63  * encryption available/not, no of ports, hw specific function ref
  64  */
  65 static const struct pm8001_chip_info pm8001_chips[] = {
  66         [chip_8001] = {0,  8, &pm8001_8001_dispatch,},
  67         [chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
  68         [chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
  69         [chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
  70         [chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
  71         [chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
  72         [chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
  73         [chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
  74         [chip_8006] = {0,  16, &pm8001_80xx_dispatch,},
  75         [chip_8070] = {0,  8, &pm8001_80xx_dispatch,},
  76         [chip_8072] = {0,  16, &pm8001_80xx_dispatch,},
  77 };
  78 static int pm8001_id;
  79
  80 LIST_HEAD(hba_list);
  81
  82 struct workqueue_struct *pm8001_wq;
  83
  84 /*
  85  * The main structure which LLDD must register for scsi core.
  86  */
  87 static struct scsi_host_template pm8001_sht = {
  88         .module                 = THIS_MODULE,
  89         .name                   = DRV_NAME,
  90         .queuecommand           = sas_queuecommand,
  91         .dma_need_drain         = ata_scsi_dma_need_drain,
  92         .target_alloc           = sas_target_alloc,
  93         .slave_configure        = sas_slave_configure,
  94         .scan_finished          = pm8001_scan_finished,
  95         .scan_start             = pm8001_scan_start,
  96         .change_queue_depth     = sas_change_queue_depth,
  97         .bios_param             = sas_bios_param,
  98         .can_queue              = 1,
  99         .this_id                = -1,
 100         .sg_tablesize           = PM8001_MAX_DMA_SG,
 101         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
 102         .eh_device_reset_handler = sas_eh_device_reset_handler,
 103         .eh_target_reset_handler = sas_eh_target_reset_handler,
 104         .target_destroy         = sas_target_destroy,
 105         .ioctl                  = sas_ioctl,
 106 #ifdef CONFIG_COMPAT
 107         .compat_ioctl           = sas_ioctl,
 108 #endif
 109         .shost_attrs            = pm8001_host_attrs,
 110         .track_queue_depth      = 1,
 111 };
 112
 113 /*
 114  * Sas layer call this function to execute specific task.
 115  */
 116 static struct sas_domain_function_template pm8001_transport_ops = {
 117         .lldd_dev_found         = pm8001_dev_found,
 118         .lldd_dev_gone          = pm8001_dev_gone,
 119
 120         .lldd_execute_task      = pm8001_queue_command,
 121         .lldd_control_phy       = pm8001_phy_control,
 122
 123         .lldd_abort_task        = pm8001_abort_task,
 124         .lldd_abort_task_set    = pm8001_abort_task_set,
 125         .lldd_clear_aca         = pm8001_clear_aca,
 126         .lldd_clear_task_set    = pm8001_clear_task_set,
 127         .lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
 128         .lldd_lu_reset          = pm8001_lu_reset,
 129         .lldd_query_task        = pm8001_query_task,
 130 };
 131
 132 /**
 133  * pm8001_phy_init - initiate our adapter phys
 134  * @pm8001_ha: our hba structure.
 135  * @phy_id: phy id.
 136  */
 137 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
 138 {
 139         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
 140         struct asd_sas_phy *sas_phy = &phy->sas_phy;
 141         phy->phy_state = PHY_LINK_DISABLE;
 142         phy->pm8001_ha = pm8001_ha;
 143         sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
 144         sas_phy->class = SAS;
 145         sas_phy->iproto = SAS_PROTOCOL_ALL;
 146         sas_phy->tproto = 0;
 147         sas_phy->type = PHY_TYPE_PHYSICAL;
 148         sas_phy->role = PHY_ROLE_INITIATOR;
 149         sas_phy->oob_mode = OOB_NOT_CONNECTED;
 150         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
 151         sas_phy->id = phy_id;
 152         sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
 153         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
 154         sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
 155         sas_phy->lldd_phy = phy;
 156 }
 157
 158 /**
 159  * pm8001_free - free hba
 160  * @pm8001_ha:  our hba structure.
 161  */
 162 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
 163 {
 164         int i;
 165
 166         if (!pm8001_ha)
 167                 return;
 168
 169         for (i = 0; i < USI_MAX_MEMCNT; i++) {
 170                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
 171                         dma_free_coherent(&pm8001_ha->pdev->dev,
 172                                 (pm8001_ha->memoryMap.region[i].total_len +
 173                                 pm8001_ha->memoryMap.region[i].alignment),
 174                                 pm8001_ha->memoryMap.region[i].virt_ptr,
 175                                 pm8001_ha->memoryMap.region[i].phys_addr);
 176                         }
 177         }
 178         PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
 179         flush_workqueue(pm8001_wq);
 180         kfree(pm8001_ha->tags);
 181         kfree(pm8001_ha);
 182 }
 183
 184 #ifdef PM8001_USE_TASKLET
 185
 186 /**
 187  * tasklet for 64 msi-x interrupt handler
 188  * @opaque: the passed general host adapter struct
 189  * Note: pm8001_tasklet is common for pm8001 & pm80xx
 190  */
 191 static void pm8001_tasklet(unsigned long opaque)
 192 {
 193         struct pm8001_hba_info *pm8001_ha;
 194         struct isr_param *irq_vector;
 195
 196         irq_vector = (struct isr_param *)opaque;
 197         pm8001_ha = irq_vector->drv_inst;
 198         if (unlikely(!pm8001_ha))
 199                 BUG_ON(1);
 200         PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 201 }
 202 #endif
 203
 204 /**
 205  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
 206  * It obtains the vector number and calls the equivalent bottom
 207  * half or services directly.
 208  * @irq: interrupt number
 209  * @opaque: the passed outbound queue/vector. Host structure is
 210  * retrieved from the same.
 211  */
 212 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
 213 {
 214         struct isr_param *irq_vector;
 215         struct pm8001_hba_info *pm8001_ha;
 216         irqreturn_t ret = IRQ_HANDLED;
 217         irq_vector = (struct isr_param *)opaque;
 218         pm8001_ha = irq_vector->drv_inst;
 219
 220         if (unlikely(!pm8001_ha))
 221                 return IRQ_NONE;
 222         if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
 223                 return IRQ_NONE;
 224 #ifdef PM8001_USE_TASKLET
 225         tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
 226 #else
 227         ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 228 #endif
 229         return ret;
 230 }
 231
 232 /**
 233  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
 234  * @irq: interrupt number
 235  * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
 236  */
 237
 238 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
 239 {
 240         struct pm8001_hba_info *pm8001_ha;
 241         irqreturn_t ret = IRQ_HANDLED;
 242         struct sas_ha_struct *sha = dev_id;
 243         pm8001_ha = sha->lldd_ha;
 244         if (unlikely(!pm8001_ha))
 245                 return IRQ_NONE;
 246         if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
 247                 return IRQ_NONE;
 248
 249 #ifdef PM8001_USE_TASKLET
 250         tasklet_schedule(&pm8001_ha->tasklet[0]);
 251 #else
 252         ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
 253 #endif
 254         return ret;
 255 }
 256
 257 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha);
 258 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
 259
 260 /**
 261  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
 262  * @pm8001_ha: our hba structure.
 263  * @ent: PCI device ID structure to match on
 264  */
 265 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
 266                         const struct pci_device_id *ent)
 267 {
 268         int i, count = 0, rc = 0;
 269         u32 ci_offset, ib_offset, ob_offset, pi_offset;
 270         struct inbound_queue_table *circularQ;
 271
 272         spin_lock_init(&pm8001_ha->lock);
 273         spin_lock_init(&pm8001_ha->bitmap_lock);
 274         pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n",
 275                    pm8001_ha->chip->n_phy);
 276
 277         /* Setup Interrupt */
 278         rc = pm8001_setup_irq(pm8001_ha);
 279         if (rc) {
 280                 pm8001_dbg(pm8001_ha, FAIL,
 281                            "pm8001_setup_irq failed [ret: %d]\n", rc);
 282                 goto err_out_shost;
 283         }
 284         /* Request Interrupt */
 285         rc = pm8001_request_irq(pm8001_ha);
 286         if (rc)
 287                 goto err_out_shost;
 288
 289         count = pm8001_ha->max_q_num;
 290         /* Queues are chosen based on the number of cores/msix availability */
 291         ib_offset = pm8001_ha->ib_offset  = USI_MAX_MEMCNT_BASE;
 292         ci_offset = pm8001_ha->ci_offset  = ib_offset + count;
 293         ob_offset = pm8001_ha->ob_offset  = ci_offset + count;
 294         pi_offset = pm8001_ha->pi_offset  = ob_offset + count;
 295         pm8001_ha->max_memcnt = pi_offset + count;
 296
 297         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 298                 pm8001_phy_init(pm8001_ha, i);
 299                 pm8001_ha->port[i].wide_port_phymap = 0;
 300                 pm8001_ha->port[i].port_attached = 0;
 301                 pm8001_ha->port[i].port_state = 0;
 302                 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
 303         }
 304
 305         /* MPI Memory region 1 for AAP Event Log for fw */
 306         pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
 307         pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
 308         pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
 309         pm8001_ha->memoryMap.region[AAP1].alignment = 32;
 310
 311         /* MPI Memory region 2 for IOP Event Log for fw */
 312         pm8001_ha->memoryMap.region[IOP].num_elements = 1;
 313         pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
 314         pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
 315         pm8001_ha->memoryMap.region[IOP].alignment = 32;
 316
 317         for (i = 0; i < count; i++) {
 318                 circularQ = &pm8001_ha->inbnd_q_tbl[i];
 319                 spin_lock_init(&circularQ->iq_lock);
 320                 /* MPI Memory region 3 for consumer Index of inbound queues */
 321                 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;
 322                 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;
 323                 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;
 324                 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;
 325
 326                 if ((ent->driver_data) != chip_8001) {
 327                         /* MPI Memory region 5 inbound queues */
 328                         pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
 329                                                 PM8001_MPI_QUEUE;
 330                         pm8001_ha->memoryMap.region[ib_offset+i].element_size
 331                                                                 = 128;
 332                         pm8001_ha->memoryMap.region[ib_offset+i].total_len =
 333                                                 PM8001_MPI_QUEUE * 128;
 334                         pm8001_ha->memoryMap.region[ib_offset+i].alignment
 335                                                                 = 128;
 336                 } else {
 337                         pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
 338                                                 PM8001_MPI_QUEUE;
 339                         pm8001_ha->memoryMap.region[ib_offset+i].element_size
 340                                                                 = 64;
 341                         pm8001_ha->memoryMap.region[ib_offset+i].total_len =
 342                                                 PM8001_MPI_QUEUE * 64;
 343                         pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;
 344                 }
 345         }
 346
 347         for (i = 0; i < count; i++) {
 348                 /* MPI Memory region 4 for producer Index of outbound queues */
 349                 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;
 350                 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;
 351                 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;
 352                 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;
 353
 354                 if (ent->driver_data != chip_8001) {
 355                         /* MPI Memory region 6 Outbound queues */
 356                         pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
 357                                                 PM8001_MPI_QUEUE;
 358                         pm8001_ha->memoryMap.region[ob_offset+i].element_size
 359                                                                 = 128;
 360                         pm8001_ha->memoryMap.region[ob_offset+i].total_len =
 361                                                 PM8001_MPI_QUEUE * 128;
 362                         pm8001_ha->memoryMap.region[ob_offset+i].alignment
 363                                                                 = 128;
 364                 } else {
 365                         /* MPI Memory region 6 Outbound queues */
 366                         pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
 367                                                 PM8001_MPI_QUEUE;
 368                         pm8001_ha->memoryMap.region[ob_offset+i].element_size
 369                                                                 = 64;
 370                         pm8001_ha->memoryMap.region[ob_offset+i].total_len =
 371                                                 PM8001_MPI_QUEUE * 64;
 372                         pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;
 373                 }
 374
 375         }
 376         /* Memory region write DMA*/
 377         pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
 378         pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
 379         pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
 380
 381         /* Memory region for fw flash */
 382         pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
 383
 384         pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
 385         pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
 386         pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
 387         pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
 388         for (i = 0; i < pm8001_ha->max_memcnt; i++) {
 389                 struct mpi_mem *region = &pm8001_ha->memoryMap.region[i];
 390
 391                 if (pm8001_mem_alloc(pm8001_ha->pdev,
 392                                      &region->virt_ptr,
 393                                      &region->phys_addr,
 394                                      &region->phys_addr_hi,
 395                                      &region->phys_addr_lo,
 396                                      region->total_len,
 397                                      region->alignment) != 0) {
 398                         pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i);
 399                         goto err_out;
 400                 }
 401         }
 402
 403         /* Memory region for devices*/
 404         pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES
 405                                 * sizeof(struct pm8001_device), GFP_KERNEL);
 406         if (!pm8001_ha->devices) {
 407                 rc = -ENOMEM;
 408                 goto err_out_nodev;
 409         }
 410         for (i = 0; i < PM8001_MAX_DEVICES; i++) {
 411                 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
 412                 pm8001_ha->devices[i].id = i;
 413                 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
 414                 atomic_set(&pm8001_ha->devices[i].running_req, 0);
 415         }
 416         pm8001_ha->flags = PM8001F_INIT_TIME;
 417         /* Initialize tags */
 418         pm8001_tag_init(pm8001_ha);
 419         return 0;
 420
 421 err_out_shost:
 422         scsi_remove_host(pm8001_ha->shost);
 423 err_out_nodev:
 424         for (i = 0; i < pm8001_ha->max_memcnt; i++) {
 425                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
 426                         pci_free_consistent(pm8001_ha->pdev,
 427                                 (pm8001_ha->memoryMap.region[i].total_len +
 428                                 pm8001_ha->memoryMap.region[i].alignment),
 429                                 pm8001_ha->memoryMap.region[i].virt_ptr,
 430                                 pm8001_ha->memoryMap.region[i].phys_addr);
 431                 }
 432         }
 433 err_out:
 434         return 1;
 435 }
 436
 437 /**
 438  * pm8001_ioremap - remap the pci high physical address to kernal virtual
 439  * address so that we can access them.
 440  * @pm8001_ha:our hba structure.
 441  */
 442 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
 443 {
 444         u32 bar;
 445         u32 logicalBar = 0;
 446         struct pci_dev *pdev;
 447
 448         pdev = pm8001_ha->pdev;
 449         /* map pci mem (PMC pci base 0-3)*/
 450         for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
 451                 /*
 452                 ** logical BARs for SPC:
 453                 ** bar 0 and 1 - logical BAR0
 454                 ** bar 2 and 3 - logical BAR1
 455                 ** bar4 - logical BAR2
 456                 ** bar5 - logical BAR3
 457                 ** Skip the appropriate assignments:
 458                 */
 459                 if ((bar == 1) || (bar == 3))
 460                         continue;
 461                 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
 462                         pm8001_ha->io_mem[logicalBar].membase =
 463                                 pci_resource_start(pdev, bar);
 464                         pm8001_ha->io_mem[logicalBar].memsize =
 465                                 pci_resource_len(pdev, bar);
 466                         pm8001_ha->io_mem[logicalBar].memvirtaddr =
 467                                 ioremap(pm8001_ha->io_mem[logicalBar].membase,
 468                                 pm8001_ha->io_mem[logicalBar].memsize);
 469                         pm8001_dbg(pm8001_ha, INIT,
 470                                    "PCI: bar %d, logicalBar %d\n",
 471                                    bar, logicalBar);
 472                         pm8001_dbg(pm8001_ha, INIT,
 473                                    "base addr %llx virt_addr=%llx len=%d\n",
 474                                    (u64)pm8001_ha->io_mem[logicalBar].membase,
 475                                    (u64)(unsigned long)
 476                                    pm8001_ha->io_mem[logicalBar].memvirtaddr,
 477                                    pm8001_ha->io_mem[logicalBar].memsize);
 478                 } else {
 479                         pm8001_ha->io_mem[logicalBar].membase   = 0;
 480                         pm8001_ha->io_mem[logicalBar].memsize   = 0;
 481                         pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
 482                 }
 483                 logicalBar++;
 484         }
 485         return 0;
 486 }
 487
 488 /**
 489  * pm8001_pci_alloc - initialize our ha card structure
 490  * @pdev: pci device.
 491  * @ent: ent
 492  * @shost: scsi host struct which has been initialized before.
 493  */
 494 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
 495                                  const struct pci_device_id *ent,
 496                                 struct Scsi_Host *shost)
 497
 498 {
 499         struct pm8001_hba_info *pm8001_ha;
 500         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 501         int j;
 502
 503         pm8001_ha = sha->lldd_ha;
 504         if (!pm8001_ha)
 505                 return NULL;
 506
 507         pm8001_ha->pdev = pdev;
 508         pm8001_ha->dev = &pdev->dev;
 509         pm8001_ha->chip_id = ent->driver_data;
 510         pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
 511         pm8001_ha->irq = pdev->irq;
 512         pm8001_ha->sas = sha;
 513         pm8001_ha->shost = shost;
 514         pm8001_ha->id = pm8001_id++;
 515         pm8001_ha->logging_level = logging_level;
 516         pm8001_ha->non_fatal_count = 0;
 517         if (link_rate >= 1 && link_rate <= 15)
 518                 pm8001_ha->link_rate = (link_rate << 8);
 519         else {
 520                 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
 521                         LINKRATE_60 | LINKRATE_120;
 522                 pm8001_dbg(pm8001_ha, FAIL,
 523                            "Setting link rate to default value\n");
 524         }
 525         sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
 526         /* IOMB size is 128 for 8088/89 controllers */
 527         if (pm8001_ha->chip_id != chip_8001)
 528                 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
 529         else
 530                 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
 531
 532 #ifdef PM8001_USE_TASKLET
 533         /* Tasklet for non msi-x interrupt handler */
 534         if ((!pdev->msix_cap || !pci_msi_enabled())
 535             || (pm8001_ha->chip_id == chip_8001))
 536                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
 537                         (unsigned long)&(pm8001_ha->irq_vector[0]));
 538         else
 539                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
 540                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
 541                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
 542 #endif
 543         pm8001_ioremap(pm8001_ha);
 544         if (!pm8001_alloc(pm8001_ha, ent))
 545                 return pm8001_ha;
 546         pm8001_free(pm8001_ha);
 547         return NULL;
 548 }
 549
 550 /**
 551  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
 552  * @pdev: pci device.
 553  */
 554 static int pci_go_44(struct pci_dev *pdev)
 555 {
 556         int rc;
 557
 558         rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
 559         if (rc) {
 560                 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 561                 if (rc)
 562                         dev_printk(KERN_ERR, &pdev->dev,
 563                                 "32-bit DMA enable failed\n");
 564         }
 565         return rc;
 566 }
 567
 568 /**
 569  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
 570  * @shost: scsi host which has been allocated outside.
 571  * @chip_info: our ha struct.
 572  */
 573 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
 574                                    const struct pm8001_chip_info *chip_info)
 575 {
 576         int phy_nr, port_nr;
 577         struct asd_sas_phy **arr_phy;
 578         struct asd_sas_port **arr_port;
 579         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 580
 581         phy_nr = chip_info->n_phy;
 582         port_nr = phy_nr;
 583         memset(sha, 0x00, sizeof(*sha));
 584         arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
 585         if (!arr_phy)
 586                 goto exit;
 587         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
 588         if (!arr_port)
 589                 goto exit_free2;
 590
 591         sha->sas_phy = arr_phy;
 592         sha->sas_port = arr_port;
 593         sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
 594         if (!sha->lldd_ha)
 595                 goto exit_free1;
 596
 597         shost->transportt = pm8001_stt;
 598         shost->max_id = PM8001_MAX_DEVICES;
 599         shost->max_lun = 8;
 600         shost->max_channel = 0;
 601         shost->unique_id = pm8001_id;
 602         shost->max_cmd_len = 16;
 603         shost->can_queue = PM8001_CAN_QUEUE;
 604         shost->cmd_per_lun = 32;
 605         return 0;
 606 exit_free1:
 607         kfree(arr_port);
 608 exit_free2:
 609         kfree(arr_phy);
 610 exit:
 611         return -1;
 612 }
 613
 614 /**
 615  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
 616  * @shost: scsi host which has been allocated outside
 617  * @chip_info: our ha struct.
 618  */
 619 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
 620                                      const struct pm8001_chip_info *chip_info)
 621 {
 622         int i = 0;
 623         struct pm8001_hba_info *pm8001_ha;
 624         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 625
 626         pm8001_ha = sha->lldd_ha;
 627         for (i = 0; i < chip_info->n_phy; i++) {
 628                 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
 629                 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
 630                 sha->sas_phy[i]->sas_addr =
 631                         (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
 632         }
 633         sha->sas_ha_name = DRV_NAME;
 634         sha->dev = pm8001_ha->dev;
 635         sha->strict_wide_ports = 1;
 636         sha->lldd_module = THIS_MODULE;
 637         sha->sas_addr = &pm8001_ha->sas_addr[0];
 638         sha->num_phys = chip_info->n_phy;
 639         sha->core.shost = shost;
 640 }
 641
 642 /**
 643  * pm8001_init_sas_add - initialize sas address
 644  * @pm8001_ha: our ha struct.
 645  *
 646  * Currently we just set the fixed SAS address to our HBA,for manufacture,
 647  * it should read from the EEPROM
 648  */
 649 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
 650 {
 651         u8 i, j;
 652         u8 sas_add[8];
 653 #ifdef PM8001_READ_VPD
 654         /* For new SPC controllers WWN is stored in flash vpd
 655         *  For SPC/SPCve controllers WWN is stored in EEPROM
 656         *  For Older SPC WWN is stored in NVMD
 657         */
 658         DECLARE_COMPLETION_ONSTACK(completion);
 659         struct pm8001_ioctl_payload payload;
 660         u16 deviceid;
 661         int rc;
 662
 663         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 664         pm8001_ha->nvmd_completion = &completion;
 665
 666         if (pm8001_ha->chip_id == chip_8001) {
 667                 if (deviceid == 0x8081 || deviceid == 0x0042) {
 668                         payload.minor_function = 4;
 669                         payload.rd_length = 4096;
 670                 } else {
 671                         payload.minor_function = 0;
 672                         payload.rd_length = 128;
 673                 }
 674         } else if ((pm8001_ha->chip_id == chip_8070 ||
 675                         pm8001_ha->chip_id == chip_8072) &&
 676                         pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
 677                 payload.minor_function = 4;
 678                 payload.rd_length = 4096;
 679         } else {
 680                 payload.minor_function = 1;
 681                 payload.rd_length = 4096;
 682         }
 683         payload.offset = 0;
 684         payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
 685         if (!payload.func_specific) {
 686                 pm8001_dbg(pm8001_ha, INIT, "mem alloc fail\n");
 687                 return;
 688         }
 689         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 690         if (rc) {
 691                 kfree(payload.func_specific);
 692                 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
 693                 return;
 694         }
 695         wait_for_completion(&completion);
 696
 697         for (i = 0, j = 0; i <= 7; i++, j++) {
 698                 if (pm8001_ha->chip_id == chip_8001) {
 699                         if (deviceid == 0x8081)
 700                                 pm8001_ha->sas_addr[j] =
 701                                         payload.func_specific[0x704 + i];
 702                         else if (deviceid == 0x0042)
 703                                 pm8001_ha->sas_addr[j] =
 704                                         payload.func_specific[0x010 + i];
 705                 } else if ((pm8001_ha->chip_id == chip_8070 ||
 706                                 pm8001_ha->chip_id == chip_8072) &&
 707                                 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
 708                         pm8001_ha->sas_addr[j] =
 709                                         payload.func_specific[0x010 + i];
 710                 } else
 711                         pm8001_ha->sas_addr[j] =
 712                                         payload.func_specific[0x804 + i];
 713         }
 714         memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
 715         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 716                 if (i && ((i % 4) == 0))
 717                         sas_add[7] = sas_add[7] + 4;
 718                 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
 719                         sas_add, SAS_ADDR_SIZE);
 720                 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i,
 721                            pm8001_ha->phy[i].dev_sas_addr);
 722         }
 723         kfree(payload.func_specific);
 724 #else
 725         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 726                 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
 727                 pm8001_ha->phy[i].dev_sas_addr =
 728                         cpu_to_be64((u64)
 729                                 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
 730         }
 731         memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
 732                 SAS_ADDR_SIZE);
 733 #endif
 734 }
 735
 736 /*
 737  * pm8001_get_phy_settings_info : Read phy setting values.
 738  * @pm8001_ha : our hba.
 739  */
 740 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
 741 {
 742
 743 #ifdef PM8001_READ_VPD
 744         /*OPTION ROM FLASH read for the SPC cards */
 745         DECLARE_COMPLETION_ONSTACK(completion);
 746         struct pm8001_ioctl_payload payload;
 747         int rc;
 748
 749         pm8001_ha->nvmd_completion = &completion;
 750         /* SAS ADDRESS read from flash / EEPROM */
 751         payload.minor_function = 6;
 752         payload.offset = 0;
 753         payload.rd_length = 4096;
 754         payload.func_specific = kzalloc(4096, GFP_KERNEL);
 755         if (!payload.func_specific)
 756                 return -ENOMEM;
 757         /* Read phy setting values from flash */
 758         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 759         if (rc) {
 760                 kfree(payload.func_specific);
 761                 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
 762                 return -ENOMEM;
 763         }
 764         wait_for_completion(&completion);
 765         pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
 766         kfree(payload.func_specific);
 767 #endif
 768         return 0;
 769 }
 770
 771 struct pm8001_mpi3_phy_pg_trx_config {
 772         u32 LaneLosCfg;
 773         u32 LanePgaCfg1;
 774         u32 LanePisoCfg1;
 775         u32 LanePisoCfg2;
 776         u32 LanePisoCfg3;
 777         u32 LanePisoCfg4;
 778         u32 LanePisoCfg5;
 779         u32 LanePisoCfg6;
 780         u32 LaneBctCtrl;
 781 };
 782
 783 /**
 784  * pm8001_get_internal_phy_settings : Retrieves the internal PHY settings
 785  * @pm8001_ha : our adapter
 786  * @phycfg : PHY config page to populate
 787  */
 788 static
 789 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
 790                 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
 791 {
 792         phycfg->LaneLosCfg   = 0x00000132;
 793         phycfg->LanePgaCfg1  = 0x00203949;
 794         phycfg->LanePisoCfg1 = 0x000000FF;
 795         phycfg->LanePisoCfg2 = 0xFF000001;
 796         phycfg->LanePisoCfg3 = 0xE7011300;
 797         phycfg->LanePisoCfg4 = 0x631C40C0;
 798         phycfg->LanePisoCfg5 = 0xF8102036;
 799         phycfg->LanePisoCfg6 = 0xF74A1000;
 800         phycfg->LaneBctCtrl  = 0x00FB33F8;
 801 }
 802
 803 /**
 804  * pm8001_get_external_phy_settings : Retrieves the external PHY settings
 805  * @pm8001_ha : our adapter
 806  * @phycfg : PHY config page to populate
 807  */
 808 static
 809 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
 810                 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
 811 {
 812         phycfg->LaneLosCfg   = 0x00000132;
 813         phycfg->LanePgaCfg1  = 0x00203949;
 814         phycfg->LanePisoCfg1 = 0x000000FF;
 815         phycfg->LanePisoCfg2 = 0xFF000001;
 816         phycfg->LanePisoCfg3 = 0xE7011300;
 817         phycfg->LanePisoCfg4 = 0x63349140;
 818         phycfg->LanePisoCfg5 = 0xF8102036;
 819         phycfg->LanePisoCfg6 = 0xF80D9300;
 820         phycfg->LaneBctCtrl  = 0x00FB33F8;
 821 }
 822
 823 /**
 824  * pm8001_get_phy_mask : Retrieves the mask that denotes if a PHY is int/ext
 825  * @pm8001_ha : our adapter
 826  * @phymask : The PHY mask
 827  */
 828 static
 829 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
 830 {
 831         switch (pm8001_ha->pdev->subsystem_device) {
 832         case 0x0070: /* H1280 - 8 external 0 internal */
 833         case 0x0072: /* H12F0 - 16 external 0 internal */
 834                 *phymask = 0x0000;
 835                 break;
 836
 837         case 0x0071: /* H1208 - 0 external 8 internal */
 838         case 0x0073: /* H120F - 0 external 16 internal */
 839                 *phymask = 0xFFFF;
 840                 break;
 841
 842         case 0x0080: /* H1244 - 4 external 4 internal */
 843                 *phymask = 0x00F0;
 844                 break;
 845
 846         case 0x0081: /* H1248 - 4 external 8 internal */
 847                 *phymask = 0x0FF0;
 848                 break;
 849
 850         case 0x0082: /* H1288 - 8 external 8 internal */
 851                 *phymask = 0xFF00;
 852                 break;
 853
 854         default:
 855                 pm8001_dbg(pm8001_ha, INIT,
 856                            "Unknown subsystem device=0x%.04x\n",
 857                            pm8001_ha->pdev->subsystem_device);
 858         }
 859 }
 860
 861 /**
 862  * pm8001_set_phy_settings_ven_117c_12Gb : Configure ATTO 12Gb PHY settings
 863  * @pm8001_ha : our adapter
 864  */
 865 static
 866 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
 867 {
 868         struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
 869         struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
 870         int phymask = 0;
 871         int i = 0;
 872
 873         memset(&phycfg_int, 0, sizeof(phycfg_int));
 874         memset(&phycfg_ext, 0, sizeof(phycfg_ext));
 875
 876         pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
 877         pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
 878         pm8001_get_phy_mask(pm8001_ha, &phymask);
 879
 880         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 881                 if (phymask & (1 << i)) {/* Internal PHY */
 882                         pm8001_set_phy_profile_single(pm8001_ha, i,
 883                                         sizeof(phycfg_int) / sizeof(u32),
 884                                         (u32 *)&phycfg_int);
 885
 886                 } else { /* External PHY */
 887                         pm8001_set_phy_profile_single(pm8001_ha, i,
 888                                         sizeof(phycfg_ext) / sizeof(u32),
 889                                         (u32 *)&phycfg_ext);
 890                 }
 891         }
 892
 893         return 0;
 894 }
 895
 896 /**
 897  * pm8001_configure_phy_settings : Configures PHY settings based on vendor ID.
 898  * @pm8001_ha : our hba.
 899  */
 900 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
 901 {
 902         switch (pm8001_ha->pdev->subsystem_vendor) {
 903         case PCI_VENDOR_ID_ATTO:
 904                 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
 905                         return 0;
 906                 else
 907                         return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
 908
 909         case PCI_VENDOR_ID_ADAPTEC2:
 910         case 0:
 911                 return 0;
 912
 913         default:
 914                 return pm8001_get_phy_settings_info(pm8001_ha);
 915         }
 916 }
 917
 918 #ifdef PM8001_USE_MSIX
 919 /**
 920  * pm8001_setup_msix - enable MSI-X interrupt
 921  * @pm8001_ha: our ha struct.
 922  */
 923 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
 924 {
 925         u32 number_of_intr;
 926         int rc, cpu_online_count;
 927         unsigned int allocated_irq_vectors;
 928
 929         /* SPCv controllers supports 64 msi-x */
 930         if (pm8001_ha->chip_id == chip_8001) {
 931                 number_of_intr = 1;
 932         } else {
 933                 number_of_intr = PM8001_MAX_MSIX_VEC;
 934         }
 935
 936         cpu_online_count = num_online_cpus();
 937         number_of_intr = min_t(int, cpu_online_count, number_of_intr);
 938         rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr,
 939                         number_of_intr, PCI_IRQ_MSIX);
 940         allocated_irq_vectors = rc;
 941         if (rc < 0)
 942                 return rc;
 943
 944         /* Assigns the number of interrupts */
 945         number_of_intr = min_t(int, allocated_irq_vectors, number_of_intr);
 946         pm8001_ha->number_of_intr = number_of_intr;
 947
 948         /* Maximum queue number updating in HBA structure */
 949         pm8001_ha->max_q_num = number_of_intr;
 950
 951         pm8001_dbg(pm8001_ha, INIT,
 952                    "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
 953                    rc, pm8001_ha->number_of_intr);
 954         return 0;
 955 }
 956
 957 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
 958 {
 959         u32 i = 0, j = 0;
 960         int flag = 0, rc = 0;
 961
 962         if (pm8001_ha->chip_id != chip_8001)
 963                 flag &= ~IRQF_SHARED;
 964
 965         pm8001_dbg(pm8001_ha, INIT,
 966                    "pci_enable_msix request number of intr %d\n",
 967                    pm8001_ha->number_of_intr);
 968
 969         for (i = 0; i < pm8001_ha->number_of_intr; i++) {
 970                 snprintf(pm8001_ha->intr_drvname[i],
 971                         sizeof(pm8001_ha->intr_drvname[0]),
 972                         "%s-%d", pm8001_ha->name, i);
 973                 pm8001_ha->irq_vector[i].irq_id = i;
 974                 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
 975
 976                 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
 977                         pm8001_interrupt_handler_msix, flag,
 978                         pm8001_ha->intr_drvname[i],
 979                         &(pm8001_ha->irq_vector[i]));
 980                 if (rc) {
 981                         for (j = 0; j < i; j++) {
 982                                 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
 983                                         &(pm8001_ha->irq_vector[i]));
 984                         }
 985                         pci_free_irq_vectors(pm8001_ha->pdev);
 986                         break;
 987                 }
 988         }
 989
 990         return rc;
 991 }
 992 #endif
 993
 994 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha)
 995 {
 996         struct pci_dev *pdev;
 997
 998         pdev = pm8001_ha->pdev;
 999
1000 #ifdef PM8001_USE_MSIX
1001         if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
1002                 return pm8001_setup_msix(pm8001_ha);
1003         pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1004 #endif
1005         return 0;
1006 }
1007
1008 /**
1009  * pm8001_request_irq - register interrupt
1010  * @pm8001_ha: our ha struct.
1011  */
1012 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
1013 {
1014         struct pci_dev *pdev;
1015         int rc;
1016
1017         pdev = pm8001_ha->pdev;
1018
1019 #ifdef PM8001_USE_MSIX
1020         if (pdev->msix_cap && pci_msi_enabled())
1021                 return pm8001_request_msix(pm8001_ha);
1022         else {
1023                 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1024                 goto intx;
1025         }
1026 #endif
1027
1028 intx:
1029         /* initialize the INT-X interrupt */
1030         pm8001_ha->irq_vector[0].irq_id = 0;
1031         pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1032         rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
1033                 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost));
1034         return rc;
1035 }
1036
1037 /**
1038  * pm8001_pci_probe - probe supported device
1039  * @pdev: pci device which kernel has been prepared for.
1040  * @ent: pci device id
1041  *
1042  * This function is the main initialization function, when register a new
1043  * pci driver it is invoked, all struct an hardware initilization should be done
1044  * here, also, register interrupt
1045  */
1046 static int pm8001_pci_probe(struct pci_dev *pdev,
1047                             const struct pci_device_id *ent)
1048 {
1049         unsigned int rc;
1050         u32     pci_reg;
1051         u8      i = 0;
1052         struct pm8001_hba_info *pm8001_ha;
1053         struct Scsi_Host *shost = NULL;
1054         const struct pm8001_chip_info *chip;
1055         struct sas_ha_struct *sha;
1056
1057         dev_printk(KERN_INFO, &pdev->dev,
1058                 "pm80xx: driver version %s\n", DRV_VERSION);
1059         rc = pci_enable_device(pdev);
1060         if (rc)
1061                 goto err_out_enable;
1062         pci_set_master(pdev);
1063         /*
1064          * Enable pci slot busmaster by setting pci command register.
1065          * This is required by FW for Cyclone card.
1066          */
1067
1068         pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1069         pci_reg |= 0x157;
1070         pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1071         rc = pci_request_regions(pdev, DRV_NAME);
1072         if (rc)
1073                 goto err_out_disable;
1074         rc = pci_go_44(pdev);
1075         if (rc)
1076                 goto err_out_regions;
1077
1078         shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1079         if (!shost) {
1080                 rc = -ENOMEM;
1081                 goto err_out_regions;
1082         }
1083         chip = &pm8001_chips[ent->driver_data];
1084         sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1085         if (!sha) {
1086                 rc = -ENOMEM;
1087                 goto err_out_free_host;
1088         }
1089         SHOST_TO_SAS_HA(shost) = sha;
1090
1091         rc = pm8001_prep_sas_ha_init(shost, chip);
1092         if (rc) {
1093                 rc = -ENOMEM;
1094                 goto err_out_free;
1095         }
1096         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1097         /* ent->driver variable is used to differentiate between controllers */
1098         pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1099         if (!pm8001_ha) {
1100                 rc = -ENOMEM;
1101                 goto err_out_free;
1102         }
1103
1104         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1105         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1106         if (rc) {
1107                 pm8001_dbg(pm8001_ha, FAIL,
1108                            "chip_init failed [ret: %d]\n", rc);
1109                 goto err_out_ha_free;
1110         }
1111
1112         rc = pm8001_init_ccb_tag(pm8001_ha, shost, pdev);
1113         if (rc)
1114                 goto err_out_enable;
1115
1116         rc = scsi_add_host(shost, &pdev->dev);
1117         if (rc)
1118                 goto err_out_ha_free;
1119
1120         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1121         if (pm8001_ha->chip_id != chip_8001) {
1122                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1123                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1124                 /* setup thermal configuration. */
1125                 pm80xx_set_thermal_config(pm8001_ha);
1126         }
1127
1128         pm8001_init_sas_add(pm8001_ha);
1129         /* phy setting support for motherboard controller */
1130         rc = pm8001_configure_phy_settings(pm8001_ha);
1131         if (rc)
1132                 goto err_out_shost;
1133
1134         pm8001_post_sas_ha_init(shost, chip);
1135         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1136         if (rc) {
1137                 pm8001_dbg(pm8001_ha, FAIL,
1138                            "sas_register_ha failed [ret: %d]\n", rc);
1139                 goto err_out_shost;
1140         }
1141         list_add_tail(&pm8001_ha->list, &hba_list);
1142         scsi_scan_host(pm8001_ha->shost);
1143         pm8001_ha->flags = PM8001F_RUN_TIME;
1144         return 0;
1145
1146 err_out_shost:
1147         scsi_remove_host(pm8001_ha->shost);
1148 err_out_ha_free:
1149         pm8001_free(pm8001_ha);
1150 err_out_free:
1151         kfree(sha);
1152 err_out_free_host:
1153         scsi_host_put(shost);
1154 err_out_regions:
1155         pci_release_regions(pdev);
1156 err_out_disable:
1157         pci_disable_device(pdev);
1158 err_out_enable:
1159         return rc;
1160 }
1161
1162 /*
1163  * pm8001_init_ccb_tag - allocate memory to CCB and tag.
1164  * @pm8001_ha: our hba card information.
1165  * @shost: scsi host which has been allocated outside.
1166  */
1167 static int
1168 pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha, struct Scsi_Host *shost,
1169                         struct pci_dev *pdev)
1170 {
1171         int i = 0;
1172         u32 max_out_io, ccb_count;
1173         u32 can_queue;
1174
1175         max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;
1176         ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);
1177
1178         /* Update to the scsi host*/
1179         can_queue = ccb_count - PM8001_RESERVE_SLOT;
1180         shost->can_queue = can_queue;
1181
1182         pm8001_ha->tags = kzalloc(ccb_count, GFP_KERNEL);
1183         if (!pm8001_ha->tags)
1184                 goto err_out;
1185
1186         /* Memory region for ccb_info*/
1187         pm8001_ha->ccb_info =
1188                 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);
1189         if (!pm8001_ha->ccb_info) {
1190                 pm8001_dbg(pm8001_ha, FAIL,
1191                            "Unable to allocate memory for ccb\n");
1192                 goto err_out_noccb;
1193         }
1194         for (i = 0; i < ccb_count; i++) {
1195                 pm8001_ha->ccb_info[i].buf_prd = pci_alloc_consistent(pdev,
1196                                 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1197                                 &pm8001_ha->ccb_info[i].ccb_dma_handle);
1198                 if (!pm8001_ha->ccb_info[i].buf_prd) {
1199                         pm8001_dbg(pm8001_ha, FAIL,
1200                                    "pm80xx: ccb prd memory allocation error\n");
1201                         goto err_out;
1202                 }
1203                 pm8001_ha->ccb_info[i].task = NULL;
1204                 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
1205                 pm8001_ha->ccb_info[i].device = NULL;
1206                 ++pm8001_ha->tags_num;
1207         }
1208         return 0;
1209
1210 err_out_noccb:
1211         kfree(pm8001_ha->devices);
1212 err_out:
1213         return -ENOMEM;
1214 }
1215
1216 static void pm8001_pci_remove(struct pci_dev *pdev)
1217 {
1218         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1219         struct pm8001_hba_info *pm8001_ha;
1220         int i, j;
1221         pm8001_ha = sha->lldd_ha;
1222         sas_unregister_ha(sha);
1223         sas_remove_host(pm8001_ha->shost);
1224         list_del(&pm8001_ha->list);
1225         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1226         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1227
1228 #ifdef PM8001_USE_MSIX
1229         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1230                 synchronize_irq(pci_irq_vector(pdev, i));
1231         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1232                 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1233         pci_free_irq_vectors(pdev);
1234 #else
1235         free_irq(pm8001_ha->irq, sha);
1236 #endif
1237 #ifdef PM8001_USE_TASKLET
1238         /* For non-msix and msix interrupts */
1239         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1240             (pm8001_ha->chip_id == chip_8001))
1241                 tasklet_kill(&pm8001_ha->tasklet[0]);
1242         else
1243                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1244                         tasklet_kill(&pm8001_ha->tasklet[j]);
1245 #endif
1246         scsi_host_put(pm8001_ha->shost);
1247         pm8001_free(pm8001_ha);
1248         kfree(sha->sas_phy);
1249         kfree(sha->sas_port);
1250         kfree(sha);
1251         pci_release_regions(pdev);
1252         pci_disable_device(pdev);
1253 }
1254
1255 /**
1256  * pm8001_pci_suspend - power management suspend main entry point
1257  * @dev: Device struct
1258  *
1259  * Returns 0 success, anything else error.
1260  */
1261 static int __maybe_unused pm8001_pci_suspend(struct device *dev)
1262 {
1263         struct pci_dev *pdev = to_pci_dev(dev);
1264         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1265         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
1266         int  i, j;
1267         sas_suspend_ha(sha);
1268         flush_workqueue(pm8001_wq);
1269         scsi_block_requests(pm8001_ha->shost);
1270         if (!pdev->pm_cap) {
1271                 dev_err(dev, " PCI PM not supported\n");
1272                 return -ENODEV;
1273         }
1274         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1275         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1276 #ifdef PM8001_USE_MSIX
1277         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1278                 synchronize_irq(pci_irq_vector(pdev, i));
1279         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1280                 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1281         pci_free_irq_vectors(pdev);
1282 #else
1283         free_irq(pm8001_ha->irq, sha);
1284 #endif
1285 #ifdef PM8001_USE_TASKLET
1286         /* For non-msix and msix interrupts */
1287         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1288             (pm8001_ha->chip_id == chip_8001))
1289                 tasklet_kill(&pm8001_ha->tasklet[0]);
1290         else
1291                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1292                         tasklet_kill(&pm8001_ha->tasklet[j]);
1293 #endif
1294         pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering "
1295                       "suspended state\n", pdev,
1296                       pm8001_ha->name);
1297         return 0;
1298 }
1299
1300 /**
1301  * pm8001_pci_resume - power management resume main entry point
1302  * @dev: Device struct
1303  *
1304  * Returns 0 success, anything else error.
1305  */
1306 static int __maybe_unused pm8001_pci_resume(struct device *dev)
1307 {
1308         struct pci_dev *pdev = to_pci_dev(dev);
1309         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1310         struct pm8001_hba_info *pm8001_ha;
1311         int rc;
1312         u8 i = 0, j;
1313         u32 device_state;
1314         DECLARE_COMPLETION_ONSTACK(completion);
1315         pm8001_ha = sha->lldd_ha;
1316         device_state = pdev->current_state;
1317
1318         pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n",
1319                       pdev, pm8001_ha->name, device_state);
1320
1321         rc = pci_go_44(pdev);
1322         if (rc)
1323                 goto err_out_disable;
1324         sas_prep_resume_ha(sha);
1325         /* chip soft rst only for spc */
1326         if (pm8001_ha->chip_id == chip_8001) {
1327                 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1328                 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n");
1329         }
1330         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1331         if (rc)
1332                 goto err_out_disable;
1333
1334         /* disable all the interrupt bits */
1335         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1336
1337         rc = pm8001_request_irq(pm8001_ha);
1338         if (rc)
1339                 goto err_out_disable;
1340 #ifdef PM8001_USE_TASKLET
1341         /*  Tasklet for non msi-x interrupt handler */
1342         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1343             (pm8001_ha->chip_id == chip_8001))
1344                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1345                         (unsigned long)&(pm8001_ha->irq_vector[0]));
1346         else
1347                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1348                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1349                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
1350 #endif
1351         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1352         if (pm8001_ha->chip_id != chip_8001) {
1353                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1354                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1355         }
1356
1357         /* Chip documentation for the 8070 and 8072 SPCv    */
1358         /* states that a 500ms minimum delay is required    */
1359         /* before issuing commands. Otherwise, the firmware */
1360         /* will enter an unrecoverable state.               */
1361
1362         if (pm8001_ha->chip_id == chip_8070 ||
1363                 pm8001_ha->chip_id == chip_8072) {
1364                 mdelay(500);
1365         }
1366
1367         /* Spin up the PHYs */
1368
1369         pm8001_ha->flags = PM8001F_RUN_TIME;
1370         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1371                 pm8001_ha->phy[i].enable_completion = &completion;
1372                 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1373                 wait_for_completion(&completion);
1374         }
1375         sas_resume_ha(sha);
1376         return 0;
1377
1378 err_out_disable:
1379         scsi_remove_host(pm8001_ha->shost);
1380
1381         return rc;
1382 }
1383
1384 /* update of pci device, vendor id and driver data with
1385  * unique value for each of the controller
1386  */
1387 static struct pci_device_id pm8001_pci_table[] = {
1388         { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1389         { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1390         { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1391         { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1392         /* Support for SPC/SPCv/SPCve controllers */
1393         { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1394         { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1395         { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1396         { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1397         { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1398         { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1399         { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1400         { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1401         { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1402         { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1403         { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1404         { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1405         { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1406         { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1407         { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1408         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1409                 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1410         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1411                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1412         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1413                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1414         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1415                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1416         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1417                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1418         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1419                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1420         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1421                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1422         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1423                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1424         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1425                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1426         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1427                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1428         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1429                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1430         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1431                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1432         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1433                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1434         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1435                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1436         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1437                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1438         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1439                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1440         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1441                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1442         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1443                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1444         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1445                 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1446         { PCI_VENDOR_ID_ATTO, 0x8070,
1447                 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1448         { PCI_VENDOR_ID_ATTO, 0x8070,
1449                 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1450         { PCI_VENDOR_ID_ATTO, 0x8072,
1451                 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1452         { PCI_VENDOR_ID_ATTO, 0x8072,
1453                 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1454         { PCI_VENDOR_ID_ATTO, 0x8070,
1455                 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1456         { PCI_VENDOR_ID_ATTO, 0x8072,
1457                 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1458         { PCI_VENDOR_ID_ATTO, 0x8072,
1459                 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1460         {} /* terminate list */
1461 };
1462
1463 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops,
1464                          pm8001_pci_suspend,
1465                          pm8001_pci_resume);
1466
1467 static struct pci_driver pm8001_pci_driver = {
1468         .name           = DRV_NAME,
1469         .id_table       = pm8001_pci_table,
1470         .probe          = pm8001_pci_probe,
1471         .remove         = pm8001_pci_remove,
1472         .driver.pm      = &pm8001_pci_pm_ops,
1473 };
1474
1475 /**
1476  *      pm8001_init - initialize scsi transport template
1477  */
1478 static int __init pm8001_init(void)
1479 {
1480         int rc = -ENOMEM;
1481
1482         pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1483         if (!pm8001_wq)
1484                 goto err;
1485
1486         pm8001_id = 0;
1487         pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1488         if (!pm8001_stt)
1489                 goto err_wq;
1490         rc = pci_register_driver(&pm8001_pci_driver);
1491         if (rc)
1492                 goto err_tp;
1493         return 0;
1494
1495 err_tp:
1496         sas_release_transport(pm8001_stt);
1497 err_wq:
1498         destroy_workqueue(pm8001_wq);
1499 err:
1500         return rc;
1501 }
1502
1503 static void __exit pm8001_exit(void)
1504 {
1505         pci_unregister_driver(&pm8001_pci_driver);
1506         sas_release_transport(pm8001_stt);
1507         destroy_workqueue(pm8001_wq);
1508 }
1509
1510 module_init(pm8001_init);
1511 module_exit(pm8001_exit);
1512
1513 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1514 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1515 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1516 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1517 MODULE_DESCRIPTION(
1518                 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1519                 "SAS/SATA controller driver");
1520 MODULE_VERSION(DRV_VERSION);
1521 MODULE_LICENSE("GPL");
1522 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1523