drivers/scsi/pm8001/pm8001_init.c

   1 /*
   2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40
  41 #include <linux/slab.h>
  42 #include "pm8001_sas.h"
  43 #include "pm8001_chips.h"
  44
  45 static struct scsi_transport_template *pm8001_stt;
  46
  47 /**
  48  * chip info structure to identify chip key functionality as
  49  * encryption available/not, no of ports, hw specific function ref
  50  */
  51 static const struct pm8001_chip_info pm8001_chips[] = {
  52         [chip_8001] = {0,  8, &pm8001_8001_dispatch,},
  53         [chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
  54         [chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
  55         [chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
  56         [chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
  57         [chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
  58         [chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
  59         [chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
  60         [chip_8006] = {0,  16, &pm8001_80xx_dispatch,},
  61         [chip_8070] = {0,  8, &pm8001_80xx_dispatch,},
  62         [chip_8072] = {0,  16, &pm8001_80xx_dispatch,},
  63 };
  64 static int pm8001_id;
  65
  66 LIST_HEAD(hba_list);
  67
  68 struct workqueue_struct *pm8001_wq;
  69
  70 /**
  71  * The main structure which LLDD must register for scsi core.
  72  */
  73 static struct scsi_host_template pm8001_sht = {
  74         .module                 = THIS_MODULE,
  75         .name                   = DRV_NAME,
  76         .queuecommand           = sas_queuecommand,
  77         .target_alloc           = sas_target_alloc,
  78         .slave_configure        = sas_slave_configure,
  79         .scan_finished          = pm8001_scan_finished,
  80         .scan_start             = pm8001_scan_start,
  81         .change_queue_depth     = sas_change_queue_depth,
  82         .bios_param             = sas_bios_param,
  83         .can_queue              = 1,
  84         .this_id                = -1,
  85         .sg_tablesize           = SG_ALL,
  86         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
  87         .use_clustering         = ENABLE_CLUSTERING,
  88         .eh_device_reset_handler = sas_eh_device_reset_handler,
  89         .eh_bus_reset_handler   = sas_eh_bus_reset_handler,
  90         .target_destroy         = sas_target_destroy,
  91         .ioctl                  = sas_ioctl,
  92         .shost_attrs            = pm8001_host_attrs,
  93         .use_blk_tags           = 1,
  94         .track_queue_depth      = 1,
  95 };
  96
  97 /**
  98  * Sas layer call this function to execute specific task.
  99  */
 100 static struct sas_domain_function_template pm8001_transport_ops = {
 101         .lldd_dev_found         = pm8001_dev_found,
 102         .lldd_dev_gone          = pm8001_dev_gone,
 103
 104         .lldd_execute_task      = pm8001_queue_command,
 105         .lldd_control_phy       = pm8001_phy_control,
 106
 107         .lldd_abort_task        = pm8001_abort_task,
 108         .lldd_abort_task_set    = pm8001_abort_task_set,
 109         .lldd_clear_aca         = pm8001_clear_aca,
 110         .lldd_clear_task_set    = pm8001_clear_task_set,
 111         .lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
 112         .lldd_lu_reset          = pm8001_lu_reset,
 113         .lldd_query_task        = pm8001_query_task,
 114 };
 115
 116 /**
 117  *pm8001_phy_init - initiate our adapter phys
 118  *@pm8001_ha: our hba structure.
 119  *@phy_id: phy id.
 120  */
 121 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
 122 {
 123         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
 124         struct asd_sas_phy *sas_phy = &phy->sas_phy;
 125         phy->phy_state = 0;
 126         phy->pm8001_ha = pm8001_ha;
 127         sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
 128         sas_phy->class = SAS;
 129         sas_phy->iproto = SAS_PROTOCOL_ALL;
 130         sas_phy->tproto = 0;
 131         sas_phy->type = PHY_TYPE_PHYSICAL;
 132         sas_phy->role = PHY_ROLE_INITIATOR;
 133         sas_phy->oob_mode = OOB_NOT_CONNECTED;
 134         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
 135         sas_phy->id = phy_id;
 136         sas_phy->sas_addr = &pm8001_ha->sas_addr[0];
 137         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
 138         sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
 139         sas_phy->lldd_phy = phy;
 140 }
 141
 142 /**
 143  *pm8001_free - free hba
 144  *@pm8001_ha:   our hba structure.
 145  *
 146  */
 147 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
 148 {
 149         int i;
 150
 151         if (!pm8001_ha)
 152                 return;
 153
 154         for (i = 0; i < USI_MAX_MEMCNT; i++) {
 155                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
 156                         pci_free_consistent(pm8001_ha->pdev,
 157                                 (pm8001_ha->memoryMap.region[i].total_len +
 158                                 pm8001_ha->memoryMap.region[i].alignment),
 159                                 pm8001_ha->memoryMap.region[i].virt_ptr,
 160                                 pm8001_ha->memoryMap.region[i].phys_addr);
 161                         }
 162         }
 163         PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
 164         if (pm8001_ha->shost)
 165                 scsi_host_put(pm8001_ha->shost);
 166         flush_workqueue(pm8001_wq);
 167         kfree(pm8001_ha->tags);
 168         kfree(pm8001_ha);
 169 }
 170
 171 #ifdef PM8001_USE_TASKLET
 172
 173 /**
 174  * tasklet for 64 msi-x interrupt handler
 175  * @opaque: the passed general host adapter struct
 176  * Note: pm8001_tasklet is common for pm8001 & pm80xx
 177  */
 178 static void pm8001_tasklet(unsigned long opaque)
 179 {
 180         struct pm8001_hba_info *pm8001_ha;
 181         struct isr_param *irq_vector;
 182
 183         irq_vector = (struct isr_param *)opaque;
 184         pm8001_ha = irq_vector->drv_inst;
 185         if (unlikely(!pm8001_ha))
 186                 BUG_ON(1);
 187         PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 188 }
 189 #endif
 190
 191 /**
 192  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
 193  * It obtains the vector number and calls the equivalent bottom
 194  * half or services directly.
 195  * @opaque: the passed outbound queue/vector. Host structure is
 196  * retrieved from the same.
 197  */
 198 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
 199 {
 200         struct isr_param *irq_vector;
 201         struct pm8001_hba_info *pm8001_ha;
 202         irqreturn_t ret = IRQ_HANDLED;
 203         irq_vector = (struct isr_param *)opaque;
 204         pm8001_ha = irq_vector->drv_inst;
 205
 206         if (unlikely(!pm8001_ha))
 207                 return IRQ_NONE;
 208         if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
 209                 return IRQ_NONE;
 210 #ifdef PM8001_USE_TASKLET
 211         tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
 212 #else
 213         ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 214 #endif
 215         return ret;
 216 }
 217
 218 /**
 219  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
 220  * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
 221  */
 222
 223 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
 224 {
 225         struct pm8001_hba_info *pm8001_ha;
 226         irqreturn_t ret = IRQ_HANDLED;
 227         struct sas_ha_struct *sha = dev_id;
 228         pm8001_ha = sha->lldd_ha;
 229         if (unlikely(!pm8001_ha))
 230                 return IRQ_NONE;
 231         if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
 232                 return IRQ_NONE;
 233
 234 #ifdef PM8001_USE_TASKLET
 235         tasklet_schedule(&pm8001_ha->tasklet[0]);
 236 #else
 237         ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
 238 #endif
 239         return ret;
 240 }
 241
 242 /**
 243  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
 244  * @pm8001_ha:our hba structure.
 245  *
 246  */
 247 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
 248                         const struct pci_device_id *ent)
 249 {
 250         int i;
 251         spin_lock_init(&pm8001_ha->lock);
 252         spin_lock_init(&pm8001_ha->bitmap_lock);
 253         PM8001_INIT_DBG(pm8001_ha,
 254                 pm8001_printk("pm8001_alloc: PHY:%x\n",
 255                                 pm8001_ha->chip->n_phy));
 256         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 257                 pm8001_phy_init(pm8001_ha, i);
 258                 pm8001_ha->port[i].wide_port_phymap = 0;
 259                 pm8001_ha->port[i].port_attached = 0;
 260                 pm8001_ha->port[i].port_state = 0;
 261                 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
 262         }
 263
 264         pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
 265         if (!pm8001_ha->tags)
 266                 goto err_out;
 267         /* MPI Memory region 1 for AAP Event Log for fw */
 268         pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
 269         pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
 270         pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
 271         pm8001_ha->memoryMap.region[AAP1].alignment = 32;
 272
 273         /* MPI Memory region 2 for IOP Event Log for fw */
 274         pm8001_ha->memoryMap.region[IOP].num_elements = 1;
 275         pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
 276         pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
 277         pm8001_ha->memoryMap.region[IOP].alignment = 32;
 278
 279         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
 280                 /* MPI Memory region 3 for consumer Index of inbound queues */
 281                 pm8001_ha->memoryMap.region[CI+i].num_elements = 1;
 282                 pm8001_ha->memoryMap.region[CI+i].element_size = 4;
 283                 pm8001_ha->memoryMap.region[CI+i].total_len = 4;
 284                 pm8001_ha->memoryMap.region[CI+i].alignment = 4;
 285
 286                 if ((ent->driver_data) != chip_8001) {
 287                         /* MPI Memory region 5 inbound queues */
 288                         pm8001_ha->memoryMap.region[IB+i].num_elements =
 289                                                 PM8001_MPI_QUEUE;
 290                         pm8001_ha->memoryMap.region[IB+i].element_size = 128;
 291                         pm8001_ha->memoryMap.region[IB+i].total_len =
 292                                                 PM8001_MPI_QUEUE * 128;
 293                         pm8001_ha->memoryMap.region[IB+i].alignment = 128;
 294                 } else {
 295                         pm8001_ha->memoryMap.region[IB+i].num_elements =
 296                                                 PM8001_MPI_QUEUE;
 297                         pm8001_ha->memoryMap.region[IB+i].element_size = 64;
 298                         pm8001_ha->memoryMap.region[IB+i].total_len =
 299                                                 PM8001_MPI_QUEUE * 64;
 300                         pm8001_ha->memoryMap.region[IB+i].alignment = 64;
 301                 }
 302         }
 303
 304         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
 305                 /* MPI Memory region 4 for producer Index of outbound queues */
 306                 pm8001_ha->memoryMap.region[PI+i].num_elements = 1;
 307                 pm8001_ha->memoryMap.region[PI+i].element_size = 4;
 308                 pm8001_ha->memoryMap.region[PI+i].total_len = 4;
 309                 pm8001_ha->memoryMap.region[PI+i].alignment = 4;
 310
 311                 if (ent->driver_data != chip_8001) {
 312                         /* MPI Memory region 6 Outbound queues */
 313                         pm8001_ha->memoryMap.region[OB+i].num_elements =
 314                                                 PM8001_MPI_QUEUE;
 315                         pm8001_ha->memoryMap.region[OB+i].element_size = 128;
 316                         pm8001_ha->memoryMap.region[OB+i].total_len =
 317                                                 PM8001_MPI_QUEUE * 128;
 318                         pm8001_ha->memoryMap.region[OB+i].alignment = 128;
 319                 } else {
 320                         /* MPI Memory region 6 Outbound queues */
 321                         pm8001_ha->memoryMap.region[OB+i].num_elements =
 322                                                 PM8001_MPI_QUEUE;
 323                         pm8001_ha->memoryMap.region[OB+i].element_size = 64;
 324                         pm8001_ha->memoryMap.region[OB+i].total_len =
 325                                                 PM8001_MPI_QUEUE * 64;
 326                         pm8001_ha->memoryMap.region[OB+i].alignment = 64;
 327                 }
 328
 329         }
 330         /* Memory region write DMA*/
 331         pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
 332         pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
 333         pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
 334         /* Memory region for devices*/
 335         pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
 336         pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
 337                 sizeof(struct pm8001_device);
 338         pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
 339                 sizeof(struct pm8001_device);
 340
 341         /* Memory region for ccb_info*/
 342         pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
 343         pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
 344                 sizeof(struct pm8001_ccb_info);
 345         pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
 346                 sizeof(struct pm8001_ccb_info);
 347
 348         /* Memory region for fw flash */
 349         pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
 350
 351         pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
 352         pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
 353         pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
 354         pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
 355         for (i = 0; i < USI_MAX_MEMCNT; i++) {
 356                 if (pm8001_mem_alloc(pm8001_ha->pdev,
 357                         &pm8001_ha->memoryMap.region[i].virt_ptr,
 358                         &pm8001_ha->memoryMap.region[i].phys_addr,
 359                         &pm8001_ha->memoryMap.region[i].phys_addr_hi,
 360                         &pm8001_ha->memoryMap.region[i].phys_addr_lo,
 361                         pm8001_ha->memoryMap.region[i].total_len,
 362                         pm8001_ha->memoryMap.region[i].alignment) != 0) {
 363                                 PM8001_FAIL_DBG(pm8001_ha,
 364                                         pm8001_printk("Mem%d alloc failed\n",
 365                                         i));
 366                                 goto err_out;
 367                 }
 368         }
 369
 370         pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
 371         for (i = 0; i < PM8001_MAX_DEVICES; i++) {
 372                 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
 373                 pm8001_ha->devices[i].id = i;
 374                 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
 375                 pm8001_ha->devices[i].running_req = 0;
 376         }
 377         pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
 378         for (i = 0; i < PM8001_MAX_CCB; i++) {
 379                 pm8001_ha->ccb_info[i].ccb_dma_handle =
 380                         pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
 381                         i * sizeof(struct pm8001_ccb_info);
 382                 pm8001_ha->ccb_info[i].task = NULL;
 383                 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
 384                 pm8001_ha->ccb_info[i].device = NULL;
 385                 ++pm8001_ha->tags_num;
 386         }
 387         pm8001_ha->flags = PM8001F_INIT_TIME;
 388         /* Initialize tags */
 389         pm8001_tag_init(pm8001_ha);
 390         return 0;
 391 err_out:
 392         return 1;
 393 }
 394
 395 /**
 396  * pm8001_ioremap - remap the pci high physical address to kernal virtual
 397  * address so that we can access them.
 398  * @pm8001_ha:our hba structure.
 399  */
 400 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
 401 {
 402         u32 bar;
 403         u32 logicalBar = 0;
 404         struct pci_dev *pdev;
 405
 406         pdev = pm8001_ha->pdev;
 407         /* map pci mem (PMC pci base 0-3)*/
 408         for (bar = 0; bar < 6; bar++) {
 409                 /*
 410                 ** logical BARs for SPC:
 411                 ** bar 0 and 1 - logical BAR0
 412                 ** bar 2 and 3 - logical BAR1
 413                 ** bar4 - logical BAR2
 414                 ** bar5 - logical BAR3
 415                 ** Skip the appropriate assignments:
 416                 */
 417                 if ((bar == 1) || (bar == 3))
 418                         continue;
 419                 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
 420                         pm8001_ha->io_mem[logicalBar].membase =
 421                                 pci_resource_start(pdev, bar);
 422                         pm8001_ha->io_mem[logicalBar].membase &=
 423                                 (u32)PCI_BASE_ADDRESS_MEM_MASK;
 424                         pm8001_ha->io_mem[logicalBar].memsize =
 425                                 pci_resource_len(pdev, bar);
 426                         pm8001_ha->io_mem[logicalBar].memvirtaddr =
 427                                 ioremap(pm8001_ha->io_mem[logicalBar].membase,
 428                                 pm8001_ha->io_mem[logicalBar].memsize);
 429                         PM8001_INIT_DBG(pm8001_ha,
 430                                 pm8001_printk("PCI: bar %d, logicalBar %d ",
 431                                 bar, logicalBar));
 432                         PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 433                                 "base addr %llx virt_addr=%llx len=%d\n",
 434                                 (u64)pm8001_ha->io_mem[logicalBar].membase,
 435                                 (u64)(unsigned long)
 436                                 pm8001_ha->io_mem[logicalBar].memvirtaddr,
 437                                 pm8001_ha->io_mem[logicalBar].memsize));
 438                 } else {
 439                         pm8001_ha->io_mem[logicalBar].membase   = 0;
 440                         pm8001_ha->io_mem[logicalBar].memsize   = 0;
 441                         pm8001_ha->io_mem[logicalBar].memvirtaddr = 0;
 442                 }
 443                 logicalBar++;
 444         }
 445         return 0;
 446 }
 447
 448 /**
 449  * pm8001_pci_alloc - initialize our ha card structure
 450  * @pdev: pci device.
 451  * @ent: ent
 452  * @shost: scsi host struct which has been initialized before.
 453  */
 454 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
 455                                  const struct pci_device_id *ent,
 456                                 struct Scsi_Host *shost)
 457
 458 {
 459         struct pm8001_hba_info *pm8001_ha;
 460         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 461         int j;
 462
 463         pm8001_ha = sha->lldd_ha;
 464         if (!pm8001_ha)
 465                 return NULL;
 466
 467         pm8001_ha->pdev = pdev;
 468         pm8001_ha->dev = &pdev->dev;
 469         pm8001_ha->chip_id = ent->driver_data;
 470         pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
 471         pm8001_ha->irq = pdev->irq;
 472         pm8001_ha->sas = sha;
 473         pm8001_ha->shost = shost;
 474         pm8001_ha->id = pm8001_id++;
 475         pm8001_ha->logging_level = 0x01;
 476         sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
 477         /* IOMB size is 128 for 8088/89 controllers */
 478         if (pm8001_ha->chip_id != chip_8001)
 479                 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
 480         else
 481                 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
 482
 483 #ifdef PM8001_USE_TASKLET
 484         /* Tasklet for non msi-x interrupt handler */
 485         if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
 486                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
 487                         (unsigned long)&(pm8001_ha->irq_vector[0]));
 488         else
 489                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
 490                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
 491                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
 492 #endif
 493         pm8001_ioremap(pm8001_ha);
 494         if (!pm8001_alloc(pm8001_ha, ent))
 495                 return pm8001_ha;
 496         pm8001_free(pm8001_ha);
 497         return NULL;
 498 }
 499
 500 /**
 501  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
 502  * @pdev: pci device.
 503  */
 504 static int pci_go_44(struct pci_dev *pdev)
 505 {
 506         int rc;
 507
 508         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) {
 509                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44));
 510                 if (rc) {
 511                         rc = pci_set_consistent_dma_mask(pdev,
 512                                 DMA_BIT_MASK(32));
 513                         if (rc) {
 514                                 dev_printk(KERN_ERR, &pdev->dev,
 515                                         "44-bit DMA enable failed\n");
 516                                 return rc;
 517                         }
 518                 }
 519         } else {
 520                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 521                 if (rc) {
 522                         dev_printk(KERN_ERR, &pdev->dev,
 523                                 "32-bit DMA enable failed\n");
 524                         return rc;
 525                 }
 526                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 527                 if (rc) {
 528                         dev_printk(KERN_ERR, &pdev->dev,
 529                                 "32-bit consistent DMA enable failed\n");
 530                         return rc;
 531                 }
 532         }
 533         return rc;
 534 }
 535
 536 /**
 537  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
 538  * @shost: scsi host which has been allocated outside.
 539  * @chip_info: our ha struct.
 540  */
 541 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
 542                                    const struct pm8001_chip_info *chip_info)
 543 {
 544         int phy_nr, port_nr;
 545         struct asd_sas_phy **arr_phy;
 546         struct asd_sas_port **arr_port;
 547         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 548
 549         phy_nr = chip_info->n_phy;
 550         port_nr = phy_nr;
 551         memset(sha, 0x00, sizeof(*sha));
 552         arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
 553         if (!arr_phy)
 554                 goto exit;
 555         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
 556         if (!arr_port)
 557                 goto exit_free2;
 558
 559         sha->sas_phy = arr_phy;
 560         sha->sas_port = arr_port;
 561         sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
 562         if (!sha->lldd_ha)
 563                 goto exit_free1;
 564
 565         shost->transportt = pm8001_stt;
 566         shost->max_id = PM8001_MAX_DEVICES;
 567         shost->max_lun = 8;
 568         shost->max_channel = 0;
 569         shost->unique_id = pm8001_id;
 570         shost->max_cmd_len = 16;
 571         shost->can_queue = PM8001_CAN_QUEUE;
 572         shost->cmd_per_lun = 32;
 573         return 0;
 574 exit_free1:
 575         kfree(arr_port);
 576 exit_free2:
 577         kfree(arr_phy);
 578 exit:
 579         return -1;
 580 }
 581
 582 /**
 583  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
 584  * @shost: scsi host which has been allocated outside
 585  * @chip_info: our ha struct.
 586  */
 587 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
 588                                      const struct pm8001_chip_info *chip_info)
 589 {
 590         int i = 0;
 591         struct pm8001_hba_info *pm8001_ha;
 592         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 593
 594         pm8001_ha = sha->lldd_ha;
 595         for (i = 0; i < chip_info->n_phy; i++) {
 596                 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
 597                 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
 598         }
 599         sha->sas_ha_name = DRV_NAME;
 600         sha->dev = pm8001_ha->dev;
 601
 602         sha->lldd_module = THIS_MODULE;
 603         sha->sas_addr = &pm8001_ha->sas_addr[0];
 604         sha->num_phys = chip_info->n_phy;
 605         sha->core.shost = shost;
 606 }
 607
 608 /**
 609  * pm8001_init_sas_add - initialize sas address
 610  * @chip_info: our ha struct.
 611  *
 612  * Currently we just set the fixed SAS address to our HBA,for manufacture,
 613  * it should read from the EEPROM
 614  */
 615 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
 616 {
 617         u8 i, j;
 618 #ifdef PM8001_READ_VPD
 619         /* For new SPC controllers WWN is stored in flash vpd
 620         *  For SPC/SPCve controllers WWN is stored in EEPROM
 621         *  For Older SPC WWN is stored in NVMD
 622         */
 623         DECLARE_COMPLETION_ONSTACK(completion);
 624         struct pm8001_ioctl_payload payload;
 625         u16 deviceid;
 626         int rc;
 627
 628         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 629         pm8001_ha->nvmd_completion = &completion;
 630
 631         if (pm8001_ha->chip_id == chip_8001) {
 632                 if (deviceid == 0x8081 || deviceid == 0x0042) {
 633                         payload.minor_function = 4;
 634                         payload.length = 4096;
 635                 } else {
 636                         payload.minor_function = 0;
 637                         payload.length = 128;
 638                 }
 639         } else if ((pm8001_ha->chip_id == chip_8070 ||
 640                         pm8001_ha->chip_id == chip_8072) &&
 641                         pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
 642                 payload.minor_function = 4;
 643                 payload.length = 4096;
 644         } else {
 645                 payload.minor_function = 1;
 646                 payload.length = 4096;
 647         }
 648         payload.offset = 0;
 649         payload.func_specific = kzalloc(payload.length, GFP_KERNEL);
 650         if (!payload.func_specific) {
 651                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n"));
 652                 return;
 653         }
 654         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 655         if (rc) {
 656                 kfree(payload.func_specific);
 657                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
 658                 return;
 659         }
 660         wait_for_completion(&completion);
 661
 662         for (i = 0, j = 0; i <= 7; i++, j++) {
 663                 if (pm8001_ha->chip_id == chip_8001) {
 664                         if (deviceid == 0x8081)
 665                                 pm8001_ha->sas_addr[j] =
 666                                         payload.func_specific[0x704 + i];
 667                         else if (deviceid == 0x0042)
 668                                 pm8001_ha->sas_addr[j] =
 669                                         payload.func_specific[0x010 + i];
 670                 } else if ((pm8001_ha->chip_id == chip_8070 ||
 671                                 pm8001_ha->chip_id == chip_8072) &&
 672                                 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
 673                         pm8001_ha->sas_addr[j] =
 674                                         payload.func_specific[0x010 + i];
 675                 } else
 676                         pm8001_ha->sas_addr[j] =
 677                                         payload.func_specific[0x804 + i];
 678         }
 679
 680         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 681                 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
 682                         pm8001_ha->sas_addr, SAS_ADDR_SIZE);
 683                 PM8001_INIT_DBG(pm8001_ha,
 684                         pm8001_printk("phy %d sas_addr = %016llx\n", i,
 685                         pm8001_ha->phy[i].dev_sas_addr));
 686         }
 687         kfree(payload.func_specific);
 688 #else
 689         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 690                 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
 691                 pm8001_ha->phy[i].dev_sas_addr =
 692                         cpu_to_be64((u64)
 693                                 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
 694         }
 695         memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
 696                 SAS_ADDR_SIZE);
 697 #endif
 698 }
 699
 700 /*
 701  * pm8001_get_phy_settings_info : Read phy setting values.
 702  * @pm8001_ha : our hba.
 703  */
 704 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
 705 {
 706
 707 #ifdef PM8001_READ_VPD
 708         /*OPTION ROM FLASH read for the SPC cards */
 709         DECLARE_COMPLETION_ONSTACK(completion);
 710         struct pm8001_ioctl_payload payload;
 711         int rc;
 712
 713         pm8001_ha->nvmd_completion = &completion;
 714         /* SAS ADDRESS read from flash / EEPROM */
 715         payload.minor_function = 6;
 716         payload.offset = 0;
 717         payload.length = 4096;
 718         payload.func_specific = kzalloc(4096, GFP_KERNEL);
 719         if (!payload.func_specific)
 720                 return -ENOMEM;
 721         /* Read phy setting values from flash */
 722         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 723         if (rc) {
 724                 kfree(payload.func_specific);
 725                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
 726                 return -ENOMEM;
 727         }
 728         wait_for_completion(&completion);
 729         pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
 730         kfree(payload.func_specific);
 731 #endif
 732         return 0;
 733 }
 734
 735 /**
 736  * pm8001_configure_phy_settings : Configures PHY settings based on vendor ID.
 737  * @pm8001_ha : our hba.
 738  */
 739 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
 740 {
 741         switch (pm8001_ha->pdev->subsystem_vendor) {
 742         case PCI_VENDOR_ID_ATTO:
 743         case PCI_VENDOR_ID_ADAPTEC2:
 744         case 0:
 745                 return 0;
 746
 747         default:
 748                 return pm8001_get_phy_settings_info(pm8001_ha);
 749         }
 750 }
 751
 752 #ifdef PM8001_USE_MSIX
 753 /**
 754  * pm8001_setup_msix - enable MSI-X interrupt
 755  * @chip_info: our ha struct.
 756  * @irq_handler: irq_handler
 757  */
 758 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
 759 {
 760         u32 i = 0, j = 0;
 761         u32 number_of_intr;
 762         int flag = 0;
 763         u32 max_entry;
 764         int rc;
 765         static char intr_drvname[PM8001_MAX_MSIX_VEC][sizeof(DRV_NAME)+3];
 766
 767         /* SPCv controllers supports 64 msi-x */
 768         if (pm8001_ha->chip_id == chip_8001) {
 769                 number_of_intr = 1;
 770         } else {
 771                 number_of_intr = PM8001_MAX_MSIX_VEC;
 772                 flag &= ~IRQF_SHARED;
 773         }
 774
 775         max_entry = sizeof(pm8001_ha->msix_entries) /
 776                 sizeof(pm8001_ha->msix_entries[0]);
 777         for (i = 0; i < max_entry ; i++)
 778                 pm8001_ha->msix_entries[i].entry = i;
 779         rc = pci_enable_msix_exact(pm8001_ha->pdev, pm8001_ha->msix_entries,
 780                 number_of_intr);
 781         pm8001_ha->number_of_intr = number_of_intr;
 782         if (rc)
 783                 return rc;
 784
 785         PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 786                 "pci_enable_msix_exact request ret:%d no of intr %d\n",
 787                                 rc, pm8001_ha->number_of_intr));
 788
 789         for (i = 0; i < number_of_intr; i++) {
 790                 snprintf(intr_drvname[i], sizeof(intr_drvname[0]),
 791                                 DRV_NAME"%d", i);
 792                 pm8001_ha->irq_vector[i].irq_id = i;
 793                 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
 794
 795                 rc = request_irq(pm8001_ha->msix_entries[i].vector,
 796                         pm8001_interrupt_handler_msix, flag,
 797                         intr_drvname[i], &(pm8001_ha->irq_vector[i]));
 798                 if (rc) {
 799                         for (j = 0; j < i; j++) {
 800                                 free_irq(pm8001_ha->msix_entries[j].vector,
 801                                         &(pm8001_ha->irq_vector[i]));
 802                         }
 803                         pci_disable_msix(pm8001_ha->pdev);
 804                         break;
 805                 }
 806         }
 807
 808         return rc;
 809 }
 810 #endif
 811
 812 /**
 813  * pm8001_request_irq - register interrupt
 814  * @chip_info: our ha struct.
 815  */
 816 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
 817 {
 818         struct pci_dev *pdev;
 819         int rc;
 820
 821         pdev = pm8001_ha->pdev;
 822
 823 #ifdef PM8001_USE_MSIX
 824         if (pdev->msix_cap)
 825                 return pm8001_setup_msix(pm8001_ha);
 826         else {
 827                 PM8001_INIT_DBG(pm8001_ha,
 828                         pm8001_printk("MSIX not supported!!!\n"));
 829                 goto intx;
 830         }
 831 #endif
 832
 833 intx:
 834         /* initialize the INT-X interrupt */
 835         rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
 836                 DRV_NAME, SHOST_TO_SAS_HA(pm8001_ha->shost));
 837         return rc;
 838 }
 839
 840 /**
 841  * pm8001_pci_probe - probe supported device
 842  * @pdev: pci device which kernel has been prepared for.
 843  * @ent: pci device id
 844  *
 845  * This function is the main initialization function, when register a new
 846  * pci driver it is invoked, all struct an hardware initilization should be done
 847  * here, also, register interrupt
 848  */
 849 static int pm8001_pci_probe(struct pci_dev *pdev,
 850                             const struct pci_device_id *ent)
 851 {
 852         unsigned int rc;
 853         u32     pci_reg;
 854         u8      i = 0;
 855         struct pm8001_hba_info *pm8001_ha;
 856         struct Scsi_Host *shost = NULL;
 857         const struct pm8001_chip_info *chip;
 858
 859         dev_printk(KERN_INFO, &pdev->dev,
 860                 "pm80xx: driver version %s\n", DRV_VERSION);
 861         rc = pci_enable_device(pdev);
 862         if (rc)
 863                 goto err_out_enable;
 864         pci_set_master(pdev);
 865         /*
 866          * Enable pci slot busmaster by setting pci command register.
 867          * This is required by FW for Cyclone card.
 868          */
 869
 870         pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
 871         pci_reg |= 0x157;
 872         pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
 873         rc = pci_request_regions(pdev, DRV_NAME);
 874         if (rc)
 875                 goto err_out_disable;
 876         rc = pci_go_44(pdev);
 877         if (rc)
 878                 goto err_out_regions;
 879
 880         shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
 881         if (!shost) {
 882                 rc = -ENOMEM;
 883                 goto err_out_regions;
 884         }
 885         chip = &pm8001_chips[ent->driver_data];
 886         SHOST_TO_SAS_HA(shost) =
 887                 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
 888         if (!SHOST_TO_SAS_HA(shost)) {
 889                 rc = -ENOMEM;
 890                 goto err_out_free_host;
 891         }
 892
 893         rc = pm8001_prep_sas_ha_init(shost, chip);
 894         if (rc) {
 895                 rc = -ENOMEM;
 896                 goto err_out_free;
 897         }
 898         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
 899         /* ent->driver variable is used to differentiate between controllers */
 900         pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
 901         if (!pm8001_ha) {
 902                 rc = -ENOMEM;
 903                 goto err_out_free;
 904         }
 905         list_add_tail(&pm8001_ha->list, &hba_list);
 906         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
 907         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
 908         if (rc) {
 909                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
 910                         "chip_init failed [ret: %d]\n", rc));
 911                 goto err_out_ha_free;
 912         }
 913
 914         rc = scsi_add_host(shost, &pdev->dev);
 915         if (rc)
 916                 goto err_out_ha_free;
 917         rc = pm8001_request_irq(pm8001_ha);
 918         if (rc) {
 919                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
 920                         "pm8001_request_irq failed [ret: %d]\n", rc));
 921                 goto err_out_shost;
 922         }
 923
 924         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
 925         if (pm8001_ha->chip_id != chip_8001) {
 926                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
 927                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
 928                 /* setup thermal configuration. */
 929                 pm80xx_set_thermal_config(pm8001_ha);
 930         }
 931
 932         pm8001_init_sas_add(pm8001_ha);
 933         /* phy setting support for motherboard controller */
 934         if (pm8001_configure_phy_settings(pm8001_ha))
 935                 goto err_out_shost;
 936
 937         pm8001_post_sas_ha_init(shost, chip);
 938         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
 939         if (rc)
 940                 goto err_out_shost;
 941         scsi_scan_host(pm8001_ha->shost);
 942         return 0;
 943
 944 err_out_shost:
 945         scsi_remove_host(pm8001_ha->shost);
 946 err_out_ha_free:
 947         pm8001_free(pm8001_ha);
 948 err_out_free:
 949         kfree(SHOST_TO_SAS_HA(shost));
 950 err_out_free_host:
 951         kfree(shost);
 952 err_out_regions:
 953         pci_release_regions(pdev);
 954 err_out_disable:
 955         pci_disable_device(pdev);
 956 err_out_enable:
 957         return rc;
 958 }
 959
 960 static void pm8001_pci_remove(struct pci_dev *pdev)
 961 {
 962         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
 963         struct pm8001_hba_info *pm8001_ha;
 964         int i, j;
 965         pm8001_ha = sha->lldd_ha;
 966         sas_unregister_ha(sha);
 967         sas_remove_host(pm8001_ha->shost);
 968         list_del(&pm8001_ha->list);
 969         scsi_remove_host(pm8001_ha->shost);
 970         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
 971         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
 972
 973 #ifdef PM8001_USE_MSIX
 974         for (i = 0; i < pm8001_ha->number_of_intr; i++)
 975                 synchronize_irq(pm8001_ha->msix_entries[i].vector);
 976         for (i = 0; i < pm8001_ha->number_of_intr; i++)
 977                 free_irq(pm8001_ha->msix_entries[i].vector,
 978                                 &(pm8001_ha->irq_vector[i]));
 979         pci_disable_msix(pdev);
 980 #else
 981         free_irq(pm8001_ha->irq, sha);
 982 #endif
 983 #ifdef PM8001_USE_TASKLET
 984         /* For non-msix and msix interrupts */
 985         if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
 986                 tasklet_kill(&pm8001_ha->tasklet[0]);
 987         else
 988                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
 989                         tasklet_kill(&pm8001_ha->tasklet[j]);
 990 #endif
 991         pm8001_free(pm8001_ha);
 992         kfree(sha->sas_phy);
 993         kfree(sha->sas_port);
 994         kfree(sha);
 995         pci_release_regions(pdev);
 996         pci_disable_device(pdev);
 997 }
 998
 999 /**
1000  * pm8001_pci_suspend - power management suspend main entry point
1001  * @pdev: PCI device struct
1002  * @state: PM state change to (usually PCI_D3)
1003  *
1004  * Returns 0 success, anything else error.
1005  */
1006 static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1007 {
1008         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1009         struct pm8001_hba_info *pm8001_ha;
1010         int  i, j;
1011         u32 device_state;
1012         pm8001_ha = sha->lldd_ha;
1013         sas_suspend_ha(sha);
1014         flush_workqueue(pm8001_wq);
1015         scsi_block_requests(pm8001_ha->shost);
1016         if (!pdev->pm_cap) {
1017                 dev_err(&pdev->dev, " PCI PM not supported\n");
1018                 return -ENODEV;
1019         }
1020         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1021         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1022 #ifdef PM8001_USE_MSIX
1023         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1024                 synchronize_irq(pm8001_ha->msix_entries[i].vector);
1025         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1026                 free_irq(pm8001_ha->msix_entries[i].vector,
1027                                 &(pm8001_ha->irq_vector[i]));
1028         pci_disable_msix(pdev);
1029 #else
1030         free_irq(pm8001_ha->irq, sha);
1031 #endif
1032 #ifdef PM8001_USE_TASKLET
1033         /* For non-msix and msix interrupts */
1034         if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
1035                 tasklet_kill(&pm8001_ha->tasklet[0]);
1036         else
1037                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1038                         tasklet_kill(&pm8001_ha->tasklet[j]);
1039 #endif
1040         device_state = pci_choose_state(pdev, state);
1041         pm8001_printk("pdev=0x%p, slot=%s, entering "
1042                       "operating state [D%d]\n", pdev,
1043                       pm8001_ha->name, device_state);
1044         pci_save_state(pdev);
1045         pci_disable_device(pdev);
1046         pci_set_power_state(pdev, device_state);
1047         return 0;
1048 }
1049
1050 /**
1051  * pm8001_pci_resume - power management resume main entry point
1052  * @pdev: PCI device struct
1053  *
1054  * Returns 0 success, anything else error.
1055  */
1056 static int pm8001_pci_resume(struct pci_dev *pdev)
1057 {
1058         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1059         struct pm8001_hba_info *pm8001_ha;
1060         int rc;
1061         u8 i = 0, j;
1062         u32 device_state;
1063         DECLARE_COMPLETION_ONSTACK(completion);
1064         pm8001_ha = sha->lldd_ha;
1065         device_state = pdev->current_state;
1066
1067         pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
1068                 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1069
1070         pci_set_power_state(pdev, PCI_D0);
1071         pci_enable_wake(pdev, PCI_D0, 0);
1072         pci_restore_state(pdev);
1073         rc = pci_enable_device(pdev);
1074         if (rc) {
1075                 pm8001_printk("slot=%s Enable device failed during resume\n",
1076                               pm8001_ha->name);
1077                 goto err_out_enable;
1078         }
1079
1080         pci_set_master(pdev);
1081         rc = pci_go_44(pdev);
1082         if (rc)
1083                 goto err_out_disable;
1084         sas_prep_resume_ha(sha);
1085         /* chip soft rst only for spc */
1086         if (pm8001_ha->chip_id == chip_8001) {
1087                 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1088                 PM8001_INIT_DBG(pm8001_ha,
1089                         pm8001_printk("chip soft reset successful\n"));
1090         }
1091         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1092         if (rc)
1093                 goto err_out_disable;
1094
1095         /* disable all the interrupt bits */
1096         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1097
1098         rc = pm8001_request_irq(pm8001_ha);
1099         if (rc)
1100                 goto err_out_disable;
1101 #ifdef PM8001_USE_TASKLET
1102         /*  Tasklet for non msi-x interrupt handler */
1103         if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
1104                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1105                         (unsigned long)&(pm8001_ha->irq_vector[0]));
1106         else
1107                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1108                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1109                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
1110 #endif
1111         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1112         if (pm8001_ha->chip_id != chip_8001) {
1113                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1114                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1115         }
1116         pm8001_ha->flags = PM8001F_RUN_TIME;
1117         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1118                 pm8001_ha->phy[i].enable_completion = &completion;
1119                 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1120                 wait_for_completion(&completion);
1121         }
1122         sas_resume_ha(sha);
1123         return 0;
1124
1125 err_out_disable:
1126         scsi_remove_host(pm8001_ha->shost);
1127         pci_disable_device(pdev);
1128 err_out_enable:
1129         return rc;
1130 }
1131
1132 /* update of pci device, vendor id and driver data with
1133  * unique value for each of the controller
1134  */
1135 static struct pci_device_id pm8001_pci_table[] = {
1136         { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1137         { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1138         { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1139         { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1140         /* Support for SPC/SPCv/SPCve controllers */
1141         { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1142         { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1143         { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1144         { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1145         { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1146         { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1147         { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1148         { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1149         { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1150         { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1151         { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1152         { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1153         { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1154         { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1155         { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1156         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1157                 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1158         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1159                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1160         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1161                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1162         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1163                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1164         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1165                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1166         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1167                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1168         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1169                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1170         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1171                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1172         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1173                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1174         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1175                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1176         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1177                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1178         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1179                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1180         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1181                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1182         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1183                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1184         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1185                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1186         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1187                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1188         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1189                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1190         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1191                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1192         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1193                 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1194         { PCI_VENDOR_ID_ATTO, 0x8070,
1195                 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1196         { PCI_VENDOR_ID_ATTO, 0x8070,
1197                 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1198         { PCI_VENDOR_ID_ATTO, 0x8072,
1199                 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1200         { PCI_VENDOR_ID_ATTO, 0x8072,
1201                 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1202         { PCI_VENDOR_ID_ATTO, 0x8070,
1203                 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1204         { PCI_VENDOR_ID_ATTO, 0x8072,
1205                 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1206         { PCI_VENDOR_ID_ATTO, 0x8072,
1207                 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1208         {} /* terminate list */
1209 };
1210
1211 static struct pci_driver pm8001_pci_driver = {
1212         .name           = DRV_NAME,
1213         .id_table       = pm8001_pci_table,
1214         .probe          = pm8001_pci_probe,
1215         .remove         = pm8001_pci_remove,
1216         .suspend        = pm8001_pci_suspend,
1217         .resume         = pm8001_pci_resume,
1218 };
1219
1220 /**
1221  *      pm8001_init - initialize scsi transport template
1222  */
1223 static int __init pm8001_init(void)
1224 {
1225         int rc = -ENOMEM;
1226
1227         pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1228         if (!pm8001_wq)
1229                 goto err;
1230
1231         pm8001_id = 0;
1232         pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1233         if (!pm8001_stt)
1234                 goto err_wq;
1235         rc = pci_register_driver(&pm8001_pci_driver);
1236         if (rc)
1237                 goto err_tp;
1238         return 0;
1239
1240 err_tp:
1241         sas_release_transport(pm8001_stt);
1242 err_wq:
1243         destroy_workqueue(pm8001_wq);
1244 err:
1245         return rc;
1246 }
1247
1248 static void __exit pm8001_exit(void)
1249 {
1250         pci_unregister_driver(&pm8001_pci_driver);
1251         sas_release_transport(pm8001_stt);
1252         destroy_workqueue(pm8001_wq);
1253 }
1254
1255 module_init(pm8001_init);
1256 module_exit(pm8001_exit);
1257
1258 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1259 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1260 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1261 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1262 MODULE_DESCRIPTION(
1263                 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1264                 "SAS/SATA controller driver");
1265 MODULE_VERSION(DRV_VERSION);
1266 MODULE_LICENSE("GPL");
1267 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1268