2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 USI Co., Ltd.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
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33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm8001_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45 #include "pm80xx_tracepoints.h"
48 * read_main_config_table - read the configure table and save it.
49 * @pm8001_ha: our hba card information
51 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
53 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
54 pm8001_ha->main_cfg_tbl.pm8001_tbl.signature =
55 pm8001_mr32(address, 0x00);
56 pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
57 pm8001_mr32(address, 0x04);
58 pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev =
59 pm8001_mr32(address, 0x08);
60 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io =
61 pm8001_mr32(address, 0x0C);
62 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl =
63 pm8001_mr32(address, 0x10);
64 pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
65 pm8001_mr32(address, 0x14);
66 pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset =
67 pm8001_mr32(address, 0x18);
68 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
69 pm8001_mr32(address, MAIN_IBQ_OFFSET);
70 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
71 pm8001_mr32(address, MAIN_OBQ_OFFSET);
72 pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag =
73 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
75 /* read analog Setting offset from the configuration table */
76 pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
77 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
79 /* read Error Dump Offset and Length */
80 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
81 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
82 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
83 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
84 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
85 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
86 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
87 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
91 * read_general_status_table - read the general status table and save it.
92 * @pm8001_ha: our hba card information
94 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
96 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
97 pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate =
98 pm8001_mr32(address, 0x00);
99 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0 =
100 pm8001_mr32(address, 0x04);
101 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1 =
102 pm8001_mr32(address, 0x08);
103 pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt =
104 pm8001_mr32(address, 0x0C);
105 pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt =
106 pm8001_mr32(address, 0x10);
107 pm8001_ha->gs_tbl.pm8001_tbl.rsvd =
108 pm8001_mr32(address, 0x14);
109 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0] =
110 pm8001_mr32(address, 0x18);
111 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1] =
112 pm8001_mr32(address, 0x1C);
113 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2] =
114 pm8001_mr32(address, 0x20);
115 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3] =
116 pm8001_mr32(address, 0x24);
117 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4] =
118 pm8001_mr32(address, 0x28);
119 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5] =
120 pm8001_mr32(address, 0x2C);
121 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6] =
122 pm8001_mr32(address, 0x30);
123 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7] =
124 pm8001_mr32(address, 0x34);
125 pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val =
126 pm8001_mr32(address, 0x38);
127 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0] =
128 pm8001_mr32(address, 0x3C);
129 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1] =
130 pm8001_mr32(address, 0x40);
131 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0] =
132 pm8001_mr32(address, 0x44);
133 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1] =
134 pm8001_mr32(address, 0x48);
135 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2] =
136 pm8001_mr32(address, 0x4C);
137 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3] =
138 pm8001_mr32(address, 0x50);
139 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4] =
140 pm8001_mr32(address, 0x54);
141 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5] =
142 pm8001_mr32(address, 0x58);
143 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6] =
144 pm8001_mr32(address, 0x5C);
145 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7] =
146 pm8001_mr32(address, 0x60);
150 * read_inbnd_queue_table - read the inbound queue table and save it.
151 * @pm8001_ha: our hba card information
153 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
156 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
157 for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
158 u32 offset = i * 0x20;
159 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
160 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
161 pm8001_ha->inbnd_q_tbl[i].pi_offset =
162 pm8001_mr32(address, (offset + 0x18));
167 * read_outbnd_queue_table - read the outbound queue table and save it.
168 * @pm8001_ha: our hba card information
170 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
173 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
174 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
175 u32 offset = i * 0x24;
176 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
177 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
178 pm8001_ha->outbnd_q_tbl[i].ci_offset =
179 pm8001_mr32(address, (offset + 0x18));
184 * init_default_table_values - init the default table.
185 * @pm8001_ha: our hba card information
187 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
190 u32 offsetib, offsetob;
191 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
192 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
193 u32 ib_offset = pm8001_ha->ib_offset;
194 u32 ob_offset = pm8001_ha->ob_offset;
195 u32 ci_offset = pm8001_ha->ci_offset;
196 u32 pi_offset = pm8001_ha->pi_offset;
198 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd = 0;
199 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3 = 0;
200 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7 = 0;
201 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3 = 0;
202 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7 = 0;
203 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
205 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
207 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
208 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
209 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
210 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
212 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr =
213 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
214 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr =
215 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
216 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size =
217 PM8001_EVENT_LOG_SIZE;
218 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option = 0x01;
219 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr =
220 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
221 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr =
222 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
223 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size =
224 PM8001_EVENT_LOG_SIZE;
225 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option = 0x01;
226 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt = 0x01;
227 for (i = 0; i < pm8001_ha->max_q_num; i++) {
228 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
229 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
230 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
231 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
232 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
233 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
234 pm8001_ha->inbnd_q_tbl[i].base_virt =
235 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
236 pm8001_ha->inbnd_q_tbl[i].total_length =
237 pm8001_ha->memoryMap.region[ib_offset + i].total_len;
238 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
239 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
240 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
241 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
242 pm8001_ha->inbnd_q_tbl[i].ci_virt =
243 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
244 pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0);
246 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
247 get_pci_bar_index(pm8001_mr32(addressib,
249 pm8001_ha->inbnd_q_tbl[i].pi_offset =
250 pm8001_mr32(addressib, (offsetib + 0x18));
251 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
252 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
254 for (i = 0; i < pm8001_ha->max_q_num; i++) {
255 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
256 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
257 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
258 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
259 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
260 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
261 pm8001_ha->outbnd_q_tbl[i].base_virt =
262 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
263 pm8001_ha->outbnd_q_tbl[i].total_length =
264 pm8001_ha->memoryMap.region[ob_offset + i].total_len;
265 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
266 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
267 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
268 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
269 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay =
270 0 | (10 << 16) | (i << 24);
271 pm8001_ha->outbnd_q_tbl[i].pi_virt =
272 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
273 pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0);
275 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
276 get_pci_bar_index(pm8001_mr32(addressob,
278 pm8001_ha->outbnd_q_tbl[i].ci_offset =
279 pm8001_mr32(addressob, (offsetob + 0x18));
280 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
281 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
286 * update_main_config_table - update the main default table to the HBA.
287 * @pm8001_ha: our hba card information
289 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
291 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
292 pm8001_mw32(address, 0x24,
293 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
294 pm8001_mw32(address, 0x28,
295 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
296 pm8001_mw32(address, 0x2C,
297 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
298 pm8001_mw32(address, 0x30,
299 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
300 pm8001_mw32(address, 0x34,
301 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
302 pm8001_mw32(address, 0x38,
303 pm8001_ha->main_cfg_tbl.pm8001_tbl.
304 outbound_tgt_ITNexus_event_pid0_3);
305 pm8001_mw32(address, 0x3C,
306 pm8001_ha->main_cfg_tbl.pm8001_tbl.
307 outbound_tgt_ITNexus_event_pid4_7);
308 pm8001_mw32(address, 0x40,
309 pm8001_ha->main_cfg_tbl.pm8001_tbl.
310 outbound_tgt_ssp_event_pid0_3);
311 pm8001_mw32(address, 0x44,
312 pm8001_ha->main_cfg_tbl.pm8001_tbl.
313 outbound_tgt_ssp_event_pid4_7);
314 pm8001_mw32(address, 0x48,
315 pm8001_ha->main_cfg_tbl.pm8001_tbl.
316 outbound_tgt_smp_event_pid0_3);
317 pm8001_mw32(address, 0x4C,
318 pm8001_ha->main_cfg_tbl.pm8001_tbl.
319 outbound_tgt_smp_event_pid4_7);
320 pm8001_mw32(address, 0x50,
321 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
322 pm8001_mw32(address, 0x54,
323 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
324 pm8001_mw32(address, 0x58,
325 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
326 pm8001_mw32(address, 0x5C,
327 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
328 pm8001_mw32(address, 0x60,
329 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
330 pm8001_mw32(address, 0x64,
331 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
332 pm8001_mw32(address, 0x68,
333 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
334 pm8001_mw32(address, 0x6C,
335 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
336 pm8001_mw32(address, 0x70,
337 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
341 * update_inbnd_queue_table - update the inbound queue table to the HBA.
342 * @pm8001_ha: our hba card information
343 * @number: entry in the queue
345 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
348 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
349 u16 offset = number * 0x20;
350 pm8001_mw32(address, offset + 0x00,
351 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
352 pm8001_mw32(address, offset + 0x04,
353 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
354 pm8001_mw32(address, offset + 0x08,
355 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
356 pm8001_mw32(address, offset + 0x0C,
357 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
358 pm8001_mw32(address, offset + 0x10,
359 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
363 * update_outbnd_queue_table - update the outbound queue table to the HBA.
364 * @pm8001_ha: our hba card information
365 * @number: entry in the queue
367 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
370 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
371 u16 offset = number * 0x24;
372 pm8001_mw32(address, offset + 0x00,
373 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
374 pm8001_mw32(address, offset + 0x04,
375 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
376 pm8001_mw32(address, offset + 0x08,
377 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
378 pm8001_mw32(address, offset + 0x0C,
379 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
380 pm8001_mw32(address, offset + 0x10,
381 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
382 pm8001_mw32(address, offset + 0x1C,
383 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
387 * pm8001_bar4_shift - function is called to shift BAR base address
388 * @pm8001_ha : our hba card information
389 * @shiftValue : shifting value in memory bar.
391 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
396 /* program the inbound AXI translation Lower Address */
397 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
399 /* confirm the setting is written */
400 start = jiffies + HZ; /* 1 sec */
402 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
403 } while ((regVal != shiftValue) && time_before(jiffies, start));
405 if (regVal != shiftValue) {
406 pm8001_dbg(pm8001_ha, INIT,
407 "TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n",
415 * mpi_set_phys_g3_with_ssc
416 * @pm8001_ha: our hba card information
417 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
419 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
425 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
426 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
427 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
428 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
429 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
430 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
431 #define SNW3_PHY_CAPABILITIES_PARITY 31
434 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
435 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
437 spin_lock_irqsave(&pm8001_ha->lock, flags);
438 if (-1 == pm8001_bar4_shift(pm8001_ha,
439 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
440 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
444 for (i = 0; i < 4; i++) {
445 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
446 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
448 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
449 if (-1 == pm8001_bar4_shift(pm8001_ha,
450 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
451 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
454 for (i = 4; i < 8; i++) {
455 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
456 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
458 /*************************************************************
459 Change the SSC upspreading value to 0x0 so that upspreading is disabled.
460 Device MABC SMOD0 Controls
461 Address: (via MEMBASE-III):
462 Using shifted destination address 0x0_0000: with Offset 0xD8
464 31:28 R/W Reserved Do not change
465 27:24 R/W SAS_SMOD_SPRDUP 0000
466 23:20 R/W SAS_SMOD_SPRDDN 0000
467 19:0 R/W Reserved Do not change
468 Upon power-up this register will read as 0x8990c016,
469 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
470 so that the written value will be 0x8090c016.
471 This will ensure only down-spreading SSC is enabled on the SPC.
472 *************************************************************/
473 pm8001_cr32(pm8001_ha, 2, 0xd8);
474 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
476 /*set the shifted destination address to 0x0 to avoid error operation */
477 pm8001_bar4_shift(pm8001_ha, 0x0);
478 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
483 * mpi_set_open_retry_interval_reg
484 * @pm8001_ha: our hba card information
485 * @interval: interval time for each OPEN_REJECT (RETRY). The units are in 1us.
487 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
495 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
496 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
497 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
498 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
499 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
501 value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
502 spin_lock_irqsave(&pm8001_ha->lock, flags);
503 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
504 if (-1 == pm8001_bar4_shift(pm8001_ha,
505 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
506 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
509 for (i = 0; i < 4; i++) {
510 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
511 pm8001_cw32(pm8001_ha, 2, offset, value);
514 if (-1 == pm8001_bar4_shift(pm8001_ha,
515 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
516 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
519 for (i = 4; i < 8; i++) {
520 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
521 pm8001_cw32(pm8001_ha, 2, offset, value);
523 /*set the shifted destination address to 0x0 to avoid error operation */
524 pm8001_bar4_shift(pm8001_ha, 0x0);
525 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
530 * mpi_init_check - check firmware initialization status.
531 * @pm8001_ha: our hba card information
533 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
537 u32 gst_len_mpistate;
538 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
540 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
541 /* wait until Inbound DoorBell Clear Register toggled */
542 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
545 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
546 value &= SPC_MSGU_CFG_TABLE_UPDATE;
547 } while ((value != 0) && (--max_wait_count));
551 /* check the MPI-State for initialization */
553 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
554 GST_GSTLEN_MPIS_OFFSET);
555 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
557 /* check MPI Initialization error */
558 gst_len_mpistate = gst_len_mpistate >> 16;
559 if (0x0000 != gst_len_mpistate)
565 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
566 * @pm8001_ha: our hba card information
568 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
572 /* check error state */
573 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
574 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
575 /* check AAP error */
576 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
578 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
582 /* check IOP error */
583 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
585 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
589 /* bit 4-31 of scratch pad1 should be zeros if it is not
591 if (value & SCRATCH_PAD1_STATE_MASK) {
593 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
597 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
599 if (value1 & SCRATCH_PAD2_STATE_MASK) {
604 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
606 /* wait until scratch pad 1 and 2 registers in ready state */
609 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
611 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
613 if ((--max_wait_count) == 0)
615 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
619 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
621 void __iomem *base_addr;
627 value = pm8001_cr32(pm8001_ha, 0, 0x44);
628 offset = value & 0x03FFFFFF;
629 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 Offset: %x\n", offset);
630 pcilogic = (value & 0xFC000000) >> 26;
631 pcibar = get_pci_bar_index(pcilogic);
632 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar);
633 pm8001_ha->main_cfg_tbl_addr = base_addr =
634 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
635 pm8001_ha->general_stat_tbl_addr =
636 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
637 pm8001_ha->inbnd_q_tbl_addr =
638 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
639 pm8001_ha->outbnd_q_tbl_addr =
640 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
644 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
645 * @pm8001_ha: our hba card information
647 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
651 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
652 /* 8081 controllers need BAR shift to access MPI space
653 * as this is shared with BIOS data */
654 if (deviceid == 0x8081 || deviceid == 0x0042) {
655 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
656 pm8001_dbg(pm8001_ha, FAIL,
657 "Shift Bar4 to 0x%x failed\n",
662 /* check the firmware status */
663 if (-1 == check_fw_ready(pm8001_ha)) {
664 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
668 /* Initialize pci space address eg: mpi offset */
669 init_pci_device_addresses(pm8001_ha);
670 init_default_table_values(pm8001_ha);
671 read_main_config_table(pm8001_ha);
672 read_general_status_table(pm8001_ha);
673 read_inbnd_queue_table(pm8001_ha);
674 read_outbnd_queue_table(pm8001_ha);
675 /* update main config table ,inbound table and outbound table */
676 update_main_config_table(pm8001_ha);
677 for (i = 0; i < pm8001_ha->max_q_num; i++)
678 update_inbnd_queue_table(pm8001_ha, i);
679 for (i = 0; i < pm8001_ha->max_q_num; i++)
680 update_outbnd_queue_table(pm8001_ha, i);
681 /* 8081 controller donot require these operations */
682 if (deviceid != 0x8081 && deviceid != 0x0042) {
683 mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
684 /* 7->130ms, 34->500ms, 119->1.5s */
685 mpi_set_open_retry_interval_reg(pm8001_ha, 119);
687 /* notify firmware update finished and check initialization status */
688 if (0 == mpi_init_check(pm8001_ha)) {
689 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n");
692 /*This register is a 16-bit timer with a resolution of 1us. This is the
693 timer used for interrupt delay/coalescing in the PCIe Application Layer.
694 Zero is not a valid value. A value of 1 in the register will cause the
695 interrupts to be normal. A value greater than 1 will cause coalescing
697 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
698 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
702 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
706 u32 gst_len_mpistate;
708 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
709 if (deviceid == 0x8081 || deviceid == 0x0042) {
710 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
711 pm8001_dbg(pm8001_ha, FAIL,
712 "Shift Bar4 to 0x%x failed\n",
717 init_pci_device_addresses(pm8001_ha);
718 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
720 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
722 /* wait until Inbound DoorBell Clear Register toggled */
723 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
726 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
727 value &= SPC_MSGU_CFG_TABLE_RESET;
728 } while ((value != 0) && (--max_wait_count));
730 if (!max_wait_count) {
731 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=0x%x\n",
736 /* check the MPI-State for termination in progress */
737 /* wait until Inbound DoorBell Clear Register toggled */
738 max_wait_count = 1 * 1000 * 1000; /* 1 sec */
742 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
743 GST_GSTLEN_MPIS_OFFSET);
744 if (GST_MPI_STATE_UNINIT ==
745 (gst_len_mpistate & GST_MPI_STATE_MASK))
747 } while (--max_wait_count);
748 if (!max_wait_count) {
749 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n",
750 gst_len_mpistate & GST_MPI_STATE_MASK);
757 * soft_reset_ready_check - Function to check FW is ready for soft reset.
758 * @pm8001_ha: our hba card information
760 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
762 u32 regVal, regVal1, regVal2;
763 if (mpi_uninit_check(pm8001_ha) != 0) {
764 pm8001_dbg(pm8001_ha, FAIL, "MPI state is not ready\n");
767 /* read the scratch pad 2 register bit 2 */
768 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
769 & SCRATCH_PAD2_FWRDY_RST;
770 if (regVal == SCRATCH_PAD2_FWRDY_RST) {
771 pm8001_dbg(pm8001_ha, INIT, "Firmware is ready for reset.\n");
774 /* Trigger NMI twice via RB6 */
775 spin_lock_irqsave(&pm8001_ha->lock, flags);
776 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
777 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
778 pm8001_dbg(pm8001_ha, FAIL,
779 "Shift Bar4 to 0x%x failed\n",
783 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
784 RB6_MAGIC_NUMBER_RST);
785 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
786 /* wait for 100 ms */
788 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
789 SCRATCH_PAD2_FWRDY_RST;
790 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
791 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
792 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
793 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MSGU_SCRATCH_PAD1=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
795 pm8001_dbg(pm8001_ha, FAIL,
796 "SCRATCH_PAD0 value = 0x%x\n",
797 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0));
798 pm8001_dbg(pm8001_ha, FAIL,
799 "SCRATCH_PAD3 value = 0x%x\n",
800 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3));
801 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
804 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
810 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
811 * the FW register status to the originated status.
812 * @pm8001_ha: our hba card information
815 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
817 u32 regVal, toggleVal;
819 u32 regVal1, regVal2, regVal3;
820 u32 signature = 0x252acbcd; /* for host scratch pad0 */
823 /* step1: Check FW is ready for soft reset */
824 if (soft_reset_ready_check(pm8001_ha) != 0) {
825 pm8001_dbg(pm8001_ha, FAIL, "FW is not ready\n");
829 /* step 2: clear NMI status register on AAP1 and IOP, write the same
831 /* map 0x60000 to BAR4(0x20), BAR2(win) */
832 spin_lock_irqsave(&pm8001_ha->lock, flags);
833 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
834 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
835 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
836 MBIC_AAP1_ADDR_BASE);
839 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
840 pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (IOP)= 0x%x\n",
842 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
843 /* map 0x70000 to BAR4(0x20), BAR2(win) */
844 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
845 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
846 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
850 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
851 pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n",
853 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
855 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
856 pm8001_dbg(pm8001_ha, INIT, "PCIE -Event Interrupt Enable = 0x%x\n",
858 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
860 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
861 pm8001_dbg(pm8001_ha, INIT, "PCIE - Event Interrupt = 0x%x\n",
863 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
865 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
866 pm8001_dbg(pm8001_ha, INIT, "PCIE -Error Interrupt Enable = 0x%x\n",
868 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
870 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
871 pm8001_dbg(pm8001_ha, INIT, "PCIE - Error Interrupt = 0x%x\n", regVal);
872 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
874 /* read the scratch pad 1 register bit 2 */
875 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
877 toggleVal = regVal ^ SCRATCH_PAD1_RST;
879 /* set signature in host scratch pad0 register to tell SPC that the
880 host performs the soft reset */
881 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
883 /* read required registers for confirmming */
884 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
885 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
886 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
887 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
891 pm8001_dbg(pm8001_ha, INIT,
892 "GSM 0x0(0x00007b88)-GSM Configuration and Reset = 0x%x\n",
893 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
895 /* step 3: host read GSM Configuration and Reset register */
896 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
897 /* Put those bits to low */
898 /* GSM XCBI offset = 0x70 0000
899 0x00 Bit 13 COM_SLV_SW_RSTB 1
900 0x00 Bit 12 QSSP_SW_RSTB 1
901 0x00 Bit 11 RAAE_SW_RSTB 1
902 0x00 Bit 9 RB_1_SW_RSTB 1
903 0x00 Bit 8 SM_SW_RSTB 1
905 regVal &= ~(0x00003b00);
906 /* host write GSM Configuration and Reset register */
907 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
908 pm8001_dbg(pm8001_ha, INIT,
909 "GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM Configuration and Reset is set to = 0x%x\n",
910 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
913 /* disable GSM - Read Address Parity Check */
914 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
915 pm8001_dbg(pm8001_ha, INIT,
916 "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n",
918 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
919 pm8001_dbg(pm8001_ha, INIT,
920 "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n",
921 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK));
923 /* disable GSM - Write Address Parity Check */
924 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
925 pm8001_dbg(pm8001_ha, INIT,
926 "GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n",
928 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
929 pm8001_dbg(pm8001_ha, INIT,
930 "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n",
931 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK));
933 /* disable GSM - Write Data Parity Check */
934 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
935 pm8001_dbg(pm8001_ha, INIT, "GSM 0x300048 - Write Data Parity Check Enable = 0x%x\n",
937 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
938 pm8001_dbg(pm8001_ha, INIT,
939 "GSM 0x300048 - Write Data Parity Check Enable is set to = 0x%x\n",
940 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK));
942 /* step 5: delay 10 usec */
944 /* step 5-b: set GPIO-0 output control to tristate anyway */
945 if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
946 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
947 pm8001_dbg(pm8001_ha, INIT, "Shift Bar4 to 0x%x failed\n",
951 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
952 pm8001_dbg(pm8001_ha, INIT, "GPIO Output Control Register: = 0x%x\n",
954 /* set GPIO-0 output control to tri-state */
955 regVal &= 0xFFFFFFFC;
956 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
958 /* Step 6: Reset the IOP and AAP1 */
959 /* map 0x00000 to BAR4(0x20), BAR2(win) */
960 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
961 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
962 pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n",
963 SPC_TOP_LEVEL_ADDR_BASE);
966 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
967 pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting IOP/AAP1:= 0x%x\n",
969 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
970 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
972 /* step 7: Reset the BDMA/OSSP */
973 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
974 pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting BDMA/OSSP: = 0x%x\n",
976 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
977 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
979 /* step 8: delay 10 usec */
982 /* step 9: bring the BDMA and OSSP out of reset */
983 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
984 pm8001_dbg(pm8001_ha, INIT,
985 "Top Register before bringing up BDMA/OSSP:= 0x%x\n",
987 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
988 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
990 /* step 10: delay 10 usec */
993 /* step 11: reads and sets the GSM Configuration and Reset Register */
994 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
995 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
996 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
997 pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n",
1001 pm8001_dbg(pm8001_ha, INIT,
1002 "GSM 0x0 (0x00007b88)-GSM Configuration and Reset = 0x%x\n",
1003 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
1004 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
1005 /* Put those bits to high */
1006 /* GSM XCBI offset = 0x70 0000
1007 0x00 Bit 13 COM_SLV_SW_RSTB 1
1008 0x00 Bit 12 QSSP_SW_RSTB 1
1009 0x00 Bit 11 RAAE_SW_RSTB 1
1010 0x00 Bit 9 RB_1_SW_RSTB 1
1011 0x00 Bit 8 SM_SW_RSTB 1
1013 regVal |= (GSM_CONFIG_RESET_VALUE);
1014 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
1015 pm8001_dbg(pm8001_ha, INIT, "GSM (0x00004088 ==> 0x00007b88) - GSM Configuration and Reset is set to = 0x%x\n",
1016 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
1018 /* step 12: Restore GSM - Read Address Parity Check */
1019 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
1020 /* just for debugging */
1021 pm8001_dbg(pm8001_ha, INIT,
1022 "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n",
1024 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
1025 pm8001_dbg(pm8001_ha, INIT, "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n",
1026 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK));
1027 /* Restore GSM - Write Address Parity Check */
1028 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
1029 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
1030 pm8001_dbg(pm8001_ha, INIT,
1031 "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n",
1032 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK));
1033 /* Restore GSM - Write Data Parity Check */
1034 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
1035 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
1036 pm8001_dbg(pm8001_ha, INIT,
1037 "GSM 0x700048 - Write Data Parity Check Enable is set to = 0x%x\n",
1038 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK));
1040 /* step 13: bring the IOP and AAP1 out of reset */
1041 /* map 0x00000 to BAR4(0x20), BAR2(win) */
1042 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
1043 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1044 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
1045 SPC_TOP_LEVEL_ADDR_BASE);
1048 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1049 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1050 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1052 /* step 14: delay 10 usec - Normal Mode */
1054 /* check Soft Reset Normal mode or Soft Reset HDA mode */
1055 if (signature == SPC_SOFT_RESET_SIGNATURE) {
1056 /* step 15 (Normal Mode): wait until scratch pad1 register
1058 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1061 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1063 } while ((regVal != toggleVal) && (--max_wait_count));
1065 if (!max_wait_count) {
1066 regVal = pm8001_cr32(pm8001_ha, 0,
1067 MSGU_SCRATCH_PAD_1);
1068 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT : ToggleVal 0x%x,MSGU_SCRATCH_PAD1 = 0x%x\n",
1070 pm8001_dbg(pm8001_ha, FAIL,
1071 "SCRATCH_PAD0 value = 0x%x\n",
1072 pm8001_cr32(pm8001_ha, 0,
1073 MSGU_SCRATCH_PAD_0));
1074 pm8001_dbg(pm8001_ha, FAIL,
1075 "SCRATCH_PAD2 value = 0x%x\n",
1076 pm8001_cr32(pm8001_ha, 0,
1077 MSGU_SCRATCH_PAD_2));
1078 pm8001_dbg(pm8001_ha, FAIL,
1079 "SCRATCH_PAD3 value = 0x%x\n",
1080 pm8001_cr32(pm8001_ha, 0,
1081 MSGU_SCRATCH_PAD_3));
1082 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1086 /* step 16 (Normal) - Clear ODMR and ODCR */
1087 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1088 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1090 /* step 17 (Normal Mode): wait for the FW and IOP to get
1091 ready - 1 sec timeout */
1092 /* Wait for the SPC Configuration Table to be ready */
1093 if (check_fw_ready(pm8001_ha) == -1) {
1094 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1095 /* return error if MPI Configuration Table not ready */
1096 pm8001_dbg(pm8001_ha, INIT,
1097 "FW not ready SCRATCH_PAD1 = 0x%x\n",
1099 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1100 /* return error if MPI Configuration Table not ready */
1101 pm8001_dbg(pm8001_ha, INIT,
1102 "FW not ready SCRATCH_PAD2 = 0x%x\n",
1104 pm8001_dbg(pm8001_ha, INIT,
1105 "SCRATCH_PAD0 value = 0x%x\n",
1106 pm8001_cr32(pm8001_ha, 0,
1107 MSGU_SCRATCH_PAD_0));
1108 pm8001_dbg(pm8001_ha, INIT,
1109 "SCRATCH_PAD3 value = 0x%x\n",
1110 pm8001_cr32(pm8001_ha, 0,
1111 MSGU_SCRATCH_PAD_3));
1112 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1116 pm8001_bar4_shift(pm8001_ha, 0);
1117 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1119 pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n");
1123 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1127 pm8001_dbg(pm8001_ha, INIT, "chip reset start\n");
1129 /* do SPC chip reset. */
1130 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1131 regVal &= ~(SPC_REG_RESET_DEVICE);
1132 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1137 /* bring chip reset out of reset */
1138 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1139 regVal |= SPC_REG_RESET_DEVICE;
1140 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1145 /* wait for 20 msec until the firmware gets reloaded */
1149 } while ((--i) != 0);
1151 pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n");
1155 * pm8001_chip_iounmap - which mapped when initialized.
1156 * @pm8001_ha: our hba card information
1158 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1160 s8 bar, logical = 0;
1161 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
1163 ** logical BARs for SPC:
1164 ** bar 0 and 1 - logical BAR0
1165 ** bar 2 and 3 - logical BAR1
1166 ** bar4 - logical BAR2
1167 ** bar5 - logical BAR3
1168 ** Skip the appropriate assignments:
1170 if ((bar == 1) || (bar == 3))
1172 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1173 iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1179 #ifndef PM8001_USE_MSIX
1181 * pm8001_chip_intx_interrupt_enable - enable PM8001 chip interrupt
1182 * @pm8001_ha: our hba card information
1185 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1187 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1188 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1192 * pm8001_chip_intx_interrupt_disable - disable PM8001 chip interrupt
1193 * @pm8001_ha: our hba card information
1196 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1198 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1204 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1205 * @pm8001_ha: our hba card information
1206 * @int_vec_idx: interrupt number to enable
1209 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1214 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1215 msi_index += MSIX_TABLE_BASE;
1216 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1217 value = (1 << int_vec_idx);
1218 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value);
1223 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1224 * @pm8001_ha: our hba card information
1225 * @int_vec_idx: interrupt number to disable
1228 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1232 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1233 msi_index += MSIX_TABLE_BASE;
1234 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE);
1239 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1240 * @pm8001_ha: our hba card information
1244 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1246 #ifdef PM8001_USE_MSIX
1247 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1249 pm8001_chip_intx_interrupt_enable(pm8001_ha);
1254 * pm8001_chip_interrupt_disable - disable PM8001 chip interrupt
1255 * @pm8001_ha: our hba card information
1259 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1261 #ifdef PM8001_USE_MSIX
1262 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1264 pm8001_chip_intx_interrupt_disable(pm8001_ha);
1269 * pm8001_mpi_msg_free_get - get the free message buffer for transfer
1271 * @circularQ: the inbound queue we want to transfer to HBA.
1272 * @messageSize: the message size of this transfer, normally it is 64 bytes
1273 * @messagePtr: the pointer to message.
1275 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
1276 u16 messageSize, void **messagePtr)
1278 u32 offset, consumer_index;
1279 struct mpi_msg_hdr *msgHeader;
1280 u8 bcCount = 1; /* only support single buffer */
1282 /* Checks is the requested message size can be allocated in this queue*/
1283 if (messageSize > IOMB_SIZE_SPCV) {
1288 /* Stores the new consumer index */
1289 consumer_index = pm8001_read_32(circularQ->ci_virt);
1290 circularQ->consumer_index = cpu_to_le32(consumer_index);
1291 if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
1292 le32_to_cpu(circularQ->consumer_index)) {
1296 /* get memory IOMB buffer address */
1297 offset = circularQ->producer_idx * messageSize;
1298 /* increment to next bcCount element */
1299 circularQ->producer_idx = (circularQ->producer_idx + bcCount)
1301 /* Adds that distance to the base of the region virtual address plus
1302 the message header size*/
1303 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1304 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1309 * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to
1310 * FW to tell the fw to get this message from IOMB.
1311 * @pm8001_ha: our hba card information
1312 * @q_index: the index in the inbound queue we want to transfer to HBA.
1313 * @opCode: the operation code represents commands which LLDD and fw recognized.
1314 * @payload: the command payload of each operation command.
1315 * @nb: size in bytes of the command payload
1316 * @responseQueue: queue to interrupt on w/ command response (if any)
1318 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1319 u32 q_index, u32 opCode, void *payload, size_t nb,
1322 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1324 unsigned long flags;
1325 struct inbound_queue_table *circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
1327 u32 htag = le32_to_cpu(*(__le32 *)payload);
1329 trace_pm80xx_mpi_build_cmd(pm8001_ha->id, opCode, htag, q_index,
1330 circularQ->producer_idx, le32_to_cpu(circularQ->consumer_index));
1332 if (WARN_ON(q_index >= pm8001_ha->max_q_num))
1335 spin_lock_irqsave(&circularQ->iq_lock, flags);
1336 rv = pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size,
1339 pm8001_dbg(pm8001_ha, IO, "No free mpi buffer\n");
1344 if (nb > (pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr)))
1345 nb = pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr);
1346 memcpy(pMessage, payload, nb);
1347 if (nb + sizeof(struct mpi_msg_hdr) < pm8001_ha->iomb_size)
1348 memset(pMessage + nb, 0, pm8001_ha->iomb_size -
1349 (nb + sizeof(struct mpi_msg_hdr)));
1351 /*Build the header*/
1352 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1353 | ((responseQueue & 0x3F) << 16)
1354 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1356 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1357 /*Update the PI to the firmware*/
1358 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1359 circularQ->pi_offset, circularQ->producer_idx);
1360 pm8001_dbg(pm8001_ha, DEVIO,
1361 "INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n",
1362 responseQueue, opCode, circularQ->producer_idx,
1363 circularQ->consumer_index);
1365 spin_unlock_irqrestore(&circularQ->iq_lock, flags);
1369 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1370 struct outbound_queue_table *circularQ, u8 bc)
1373 struct mpi_msg_hdr *msgHeader;
1374 struct mpi_msg_hdr *pOutBoundMsgHeader;
1376 msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1377 pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1378 circularQ->consumer_idx * pm8001_ha->iomb_size);
1379 if (pOutBoundMsgHeader != msgHeader) {
1380 pm8001_dbg(pm8001_ha, FAIL,
1381 "consumer_idx = %d msgHeader = %p\n",
1382 circularQ->consumer_idx, msgHeader);
1384 /* Update the producer index from SPC */
1385 producer_index = pm8001_read_32(circularQ->pi_virt);
1386 circularQ->producer_index = cpu_to_le32(producer_index);
1387 pm8001_dbg(pm8001_ha, FAIL,
1388 "consumer_idx = %d producer_index = %dmsgHeader = %p\n",
1389 circularQ->consumer_idx,
1390 circularQ->producer_index, msgHeader);
1393 /* free the circular queue buffer elements associated with the message*/
1394 circularQ->consumer_idx = (circularQ->consumer_idx + bc)
1396 /* update the CI of outbound queue */
1397 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1398 circularQ->consumer_idx);
1399 /* Update the producer index from SPC*/
1400 producer_index = pm8001_read_32(circularQ->pi_virt);
1401 circularQ->producer_index = cpu_to_le32(producer_index);
1402 pm8001_dbg(pm8001_ha, IO, " CI=%d PI=%d\n",
1403 circularQ->consumer_idx, circularQ->producer_index);
1408 * pm8001_mpi_msg_consume- get the MPI message from outbound queue
1410 * @pm8001_ha: our hba card information
1411 * @circularQ: the outbound queue table.
1412 * @messagePtr1: the message contents of this outbound message.
1413 * @pBC: the message size.
1415 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1416 struct outbound_queue_table *circularQ,
1417 void **messagePtr1, u8 *pBC)
1419 struct mpi_msg_hdr *msgHeader;
1420 __le32 msgHeader_tmp;
1423 /* If there are not-yet-delivered messages ... */
1424 if (le32_to_cpu(circularQ->producer_index)
1425 != circularQ->consumer_idx) {
1426 /*Get the pointer to the circular queue buffer element*/
1427 msgHeader = (struct mpi_msg_hdr *)
1428 (circularQ->base_virt +
1429 circularQ->consumer_idx * pm8001_ha->iomb_size);
1431 header_tmp = pm8001_read_32(msgHeader);
1432 msgHeader_tmp = cpu_to_le32(header_tmp);
1433 pm8001_dbg(pm8001_ha, DEVIO,
1434 "outbound opcode msgheader:%x ci=%d pi=%d\n",
1435 msgHeader_tmp, circularQ->consumer_idx,
1436 circularQ->producer_index);
1437 if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
1438 if (OPC_OUB_SKIP_ENTRY !=
1439 (le32_to_cpu(msgHeader_tmp) & 0xfff)) {
1442 sizeof(struct mpi_msg_hdr);
1443 *pBC = (u8)((le32_to_cpu(msgHeader_tmp)
1445 pm8001_dbg(pm8001_ha, IO,
1446 ": CI=%d PI=%d msgHeader=%x\n",
1447 circularQ->consumer_idx,
1448 circularQ->producer_index,
1450 return MPI_IO_STATUS_SUCCESS;
1452 circularQ->consumer_idx =
1453 (circularQ->consumer_idx +
1454 ((le32_to_cpu(msgHeader_tmp)
1458 pm8001_write_32(msgHeader, 0, 0);
1459 /* update the CI of outbound queue */
1460 pm8001_cw32(pm8001_ha,
1461 circularQ->ci_pci_bar,
1462 circularQ->ci_offset,
1463 circularQ->consumer_idx);
1466 circularQ->consumer_idx =
1467 (circularQ->consumer_idx +
1468 ((le32_to_cpu(msgHeader_tmp) >> 24) &
1469 0x1f)) % PM8001_MPI_QUEUE;
1471 pm8001_write_32(msgHeader, 0, 0);
1472 /* update the CI of outbound queue */
1473 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1474 circularQ->ci_offset,
1475 circularQ->consumer_idx);
1476 return MPI_IO_STATUS_FAIL;
1480 void *pi_virt = circularQ->pi_virt;
1481 /* spurious interrupt during setup if
1482 * kexec-ing and driver doing a doorbell access
1483 * with the pre-kexec oq interrupt setup
1487 /* Update the producer index from SPC */
1488 producer_index = pm8001_read_32(pi_virt);
1489 circularQ->producer_index = cpu_to_le32(producer_index);
1491 } while (le32_to_cpu(circularQ->producer_index) !=
1492 circularQ->consumer_idx);
1493 /* while we don't have any more not-yet-delivered message */
1495 return MPI_IO_STATUS_BUSY;
1498 void pm8001_work_fn(struct work_struct *work)
1500 struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1501 struct pm8001_device *pm8001_dev;
1502 struct domain_device *dev;
1505 * So far, all users of this stash an associated structure here.
1506 * If we get here, and this pointer is null, then the action
1507 * was cancelled. This nullification happens when the device
1510 if (pw->handler != IO_FATAL_ERROR) {
1511 pm8001_dev = pw->data; /* Most stash device structure */
1512 if ((pm8001_dev == NULL)
1513 || ((pw->handler != IO_XFER_ERROR_BREAK)
1514 && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) {
1520 switch (pw->handler) {
1521 case IO_XFER_ERROR_BREAK:
1522 { /* This one stashes the sas_task instead */
1523 struct sas_task *t = (struct sas_task *)pm8001_dev;
1524 struct pm8001_ccb_info *ccb;
1525 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1526 unsigned long flags, flags1;
1527 struct task_status_struct *ts;
1530 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1531 break; /* Task still on lu */
1532 spin_lock_irqsave(&pm8001_ha->lock, flags);
1534 spin_lock_irqsave(&t->task_state_lock, flags1);
1535 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1536 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1537 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1538 break; /* Task got completed by another */
1540 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1542 /* Search for a possible ccb that matches the task */
1543 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1544 ccb = &pm8001_ha->ccb_info[i];
1545 if ((ccb->ccb_tag != PM8001_INVALID_TAG) &&
1550 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1551 break; /* Task got freed by another */
1553 ts = &t->task_status;
1554 ts->resp = SAS_TASK_COMPLETE;
1555 /* Force the midlayer to retry */
1556 ts->stat = SAS_QUEUE_FULL;
1557 pm8001_dev = ccb->device;
1559 atomic_dec(&pm8001_dev->running_req);
1560 spin_lock_irqsave(&t->task_state_lock, flags1);
1561 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1562 t->task_state_flags |= SAS_TASK_STATE_DONE;
1563 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1564 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1565 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
1566 t, pw->handler, ts->resp, ts->stat);
1567 pm8001_ccb_task_free(pm8001_ha, ccb);
1568 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1570 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1571 pm8001_ccb_task_free(pm8001_ha, ccb);
1572 mb();/* in order to force CPU ordering */
1573 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1577 case IO_XFER_OPEN_RETRY_TIMEOUT:
1578 { /* This one stashes the sas_task instead */
1579 struct sas_task *t = (struct sas_task *)pm8001_dev;
1580 struct pm8001_ccb_info *ccb;
1581 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1582 unsigned long flags, flags1;
1585 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
1587 ret = pm8001_query_task(t);
1589 if (ret == TMF_RESP_FUNC_SUCC)
1590 pm8001_dbg(pm8001_ha, IO, "...Task on lu\n");
1591 else if (ret == TMF_RESP_FUNC_COMPLETE)
1592 pm8001_dbg(pm8001_ha, IO, "...Task NOT on lu\n");
1594 pm8001_dbg(pm8001_ha, DEVIO, "...query task failed!!!\n");
1596 spin_lock_irqsave(&pm8001_ha->lock, flags);
1598 spin_lock_irqsave(&t->task_state_lock, flags1);
1600 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1601 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1602 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1603 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1604 (void)pm8001_abort_task(t);
1605 break; /* Task got completed by another */
1608 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1610 /* Search for a possible ccb that matches the task */
1611 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1612 ccb = &pm8001_ha->ccb_info[i];
1613 if ((ccb->ccb_tag != PM8001_INVALID_TAG) &&
1618 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1619 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1620 (void)pm8001_abort_task(t);
1621 break; /* Task got freed by another */
1624 pm8001_dev = ccb->device;
1625 dev = pm8001_dev->sas_device;
1628 case TMF_RESP_FUNC_SUCC: /* task on lu */
1629 ccb->open_retry = 1; /* Snub completion */
1630 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1631 ret = pm8001_abort_task(t);
1632 ccb->open_retry = 0;
1634 case TMF_RESP_FUNC_SUCC:
1635 case TMF_RESP_FUNC_COMPLETE:
1637 default: /* device misbehavior */
1638 ret = TMF_RESP_FUNC_FAILED;
1639 pm8001_dbg(pm8001_ha, IO, "...Reset phy\n");
1640 pm8001_I_T_nexus_reset(dev);
1645 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1646 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1647 /* Do we need to abort the task locally? */
1650 default: /* device misbehavior */
1651 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1652 ret = TMF_RESP_FUNC_FAILED;
1653 pm8001_dbg(pm8001_ha, IO, "...Reset phy\n");
1654 pm8001_I_T_nexus_reset(dev);
1657 if (ret == TMF_RESP_FUNC_FAILED)
1659 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1660 pm8001_dbg(pm8001_ha, IO, "...Complete\n");
1662 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1663 dev = pm8001_dev->sas_device;
1664 pm8001_I_T_nexus_event_handler(dev);
1666 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1667 dev = pm8001_dev->sas_device;
1668 pm8001_I_T_nexus_reset(dev);
1670 case IO_DS_IN_ERROR:
1671 dev = pm8001_dev->sas_device;
1672 pm8001_I_T_nexus_reset(dev);
1674 case IO_DS_NON_OPERATIONAL:
1675 dev = pm8001_dev->sas_device;
1676 pm8001_I_T_nexus_reset(dev);
1678 case IO_FATAL_ERROR:
1680 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1681 struct pm8001_ccb_info *ccb;
1682 struct task_status_struct *ts;
1683 struct sas_task *task;
1687 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1688 ccb = &pm8001_ha->ccb_info[i];
1690 ts = &task->task_status;
1695 pm8001_dbg(pm8001_ha, FAIL,
1699 /*complete sas task and update to top layer */
1700 pm8001_ccb_task_free(pm8001_ha, ccb);
1701 ts->resp = SAS_TASK_COMPLETE;
1702 task->task_done(task);
1703 } else if (ccb->ccb_tag != PM8001_INVALID_TAG) {
1704 /* complete the internal commands/non-sas task */
1705 pm8001_dev = ccb->device;
1706 if (pm8001_dev->dcompletion) {
1707 complete(pm8001_dev->dcompletion);
1708 pm8001_dev->dcompletion = NULL;
1710 complete(pm8001_ha->nvmd_completion);
1711 pm8001_ccb_free(pm8001_ha, ccb);
1714 /* Deregister all the device ids */
1715 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
1716 pm8001_dev = &pm8001_ha->devices[i];
1717 device_id = pm8001_dev->device_id;
1719 PM8001_CHIP_DISP->dereg_dev_req(pm8001_ha, device_id);
1720 pm8001_free_dev(pm8001_dev);
1728 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1731 struct pm8001_work *pw;
1734 pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1736 pw->pm8001_ha = pm8001_ha;
1738 pw->handler = handler;
1739 INIT_WORK(&pw->work, pm8001_work_fn);
1740 queue_work(pm8001_wq, &pw->work);
1747 static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1748 struct pm8001_device *pm8001_ha_dev)
1750 struct pm8001_ccb_info *ccb;
1751 struct sas_task *task;
1752 struct task_abort_req task_abort;
1753 u32 opc = OPC_INB_SATA_ABORT;
1756 pm8001_ha_dev->id |= NCQ_ABORT_ALL_FLAG;
1757 pm8001_ha_dev->id &= ~NCQ_READ_LOG_FLAG;
1759 task = sas_alloc_slow_task(GFP_ATOMIC);
1761 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n");
1765 task->task_done = pm8001_task_done;
1767 ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_ha_dev, task);
1769 sas_free_task(task);
1773 memset(&task_abort, 0, sizeof(task_abort));
1774 task_abort.abort_all = cpu_to_le32(1);
1775 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1776 task_abort.tag = cpu_to_le32(ccb->ccb_tag);
1778 ret = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &task_abort,
1779 sizeof(task_abort), 0);
1781 sas_free_task(task);
1782 pm8001_ccb_free(pm8001_ha, ccb);
1786 static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha,
1787 struct pm8001_device *pm8001_ha_dev)
1789 struct sata_start_req sata_cmd;
1791 struct pm8001_ccb_info *ccb;
1792 struct sas_task *task = NULL;
1793 struct host_to_dev_fis fis;
1794 struct domain_device *dev;
1795 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1797 task = sas_alloc_slow_task(GFP_ATOMIC);
1799 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n");
1802 task->task_done = pm8001_task_done;
1805 * Allocate domain device by ourselves as libsas is not going to
1808 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1810 sas_free_task(task);
1811 pm8001_dbg(pm8001_ha, FAIL,
1812 "Domain device cannot be allocated\n");
1816 task->dev->lldd_dev = pm8001_ha_dev;
1818 ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_ha_dev, task);
1820 sas_free_task(task);
1825 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1826 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1828 /* construct read log FIS */
1829 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1830 fis.fis_type = 0x27;
1832 fis.command = ATA_CMD_READ_LOG_EXT;
1834 fis.sector_count = 0x1;
1836 memset(&sata_cmd, 0, sizeof(sata_cmd));
1837 sata_cmd.tag = cpu_to_le32(ccb->ccb_tag);
1838 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1839 sata_cmd.ncqtag_atap_dir_m = cpu_to_le32((0x1 << 7) | (0x5 << 9));
1840 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1842 res = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &sata_cmd,
1843 sizeof(sata_cmd), 0);
1845 sas_free_task(task);
1846 pm8001_ccb_free(pm8001_ha, ccb);
1852 * mpi_ssp_completion- process the event that FW response to the SSP request.
1853 * @pm8001_ha: our hba card information
1854 * @piomb: the message contents of this outbound message.
1856 * When FW has completed a ssp request for example a IO request, after it has
1857 * filled the SG data with the data, it will trigger this event representing
1858 * that he has finished the job; please check the corresponding buffer.
1859 * So we will tell the caller who maybe waiting the result to tell upper layer
1860 * that the task has been finished.
1863 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1866 struct pm8001_ccb_info *ccb;
1867 unsigned long flags;
1871 struct ssp_completion_resp *psspPayload;
1872 struct task_status_struct *ts;
1873 struct ssp_response_iu *iu;
1874 struct pm8001_device *pm8001_dev;
1875 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1876 status = le32_to_cpu(psspPayload->status);
1877 tag = le32_to_cpu(psspPayload->tag);
1878 ccb = &pm8001_ha->ccb_info[tag];
1879 if ((status == IO_ABORTED) && ccb->open_retry) {
1880 /* Being completed by another */
1881 ccb->open_retry = 0;
1884 pm8001_dev = ccb->device;
1885 param = le32_to_cpu(psspPayload->param);
1889 if (status && status != IO_UNDERFLOW)
1890 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status);
1891 if (unlikely(!t || !t->lldd_task || !t->dev))
1893 ts = &t->task_status;
1894 /* Print sas address of IO failed device */
1895 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1896 (status != IO_UNDERFLOW))
1897 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n",
1898 SAS_ADDR(t->dev->sas_addr));
1901 pm8001_dbg(pm8001_ha, IOERR,
1902 "status:0x%x, tag:0x%x, task:0x%p\n",
1907 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS,param = %d\n",
1910 ts->resp = SAS_TASK_COMPLETE;
1911 ts->stat = SAS_SAM_STAT_GOOD;
1913 ts->resp = SAS_TASK_COMPLETE;
1914 ts->stat = SAS_PROTO_RESPONSE;
1915 ts->residual = param;
1916 iu = &psspPayload->ssp_resp_iu;
1917 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1920 atomic_dec(&pm8001_dev->running_req);
1923 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
1924 ts->resp = SAS_TASK_COMPLETE;
1925 ts->stat = SAS_ABORTED_TASK;
1928 /* SSP Completion with error */
1929 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW,param = %d\n",
1931 ts->resp = SAS_TASK_COMPLETE;
1932 ts->stat = SAS_DATA_UNDERRUN;
1933 ts->residual = param;
1935 atomic_dec(&pm8001_dev->running_req);
1938 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
1939 ts->resp = SAS_TASK_UNDELIVERED;
1940 ts->stat = SAS_PHY_DOWN;
1942 case IO_XFER_ERROR_BREAK:
1943 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
1944 ts->resp = SAS_TASK_COMPLETE;
1945 ts->stat = SAS_OPEN_REJECT;
1946 /* Force the midlayer to retry */
1947 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1949 case IO_XFER_ERROR_PHY_NOT_READY:
1950 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
1951 ts->resp = SAS_TASK_COMPLETE;
1952 ts->stat = SAS_OPEN_REJECT;
1953 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1955 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1956 pm8001_dbg(pm8001_ha, IO,
1957 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
1958 ts->resp = SAS_TASK_COMPLETE;
1959 ts->stat = SAS_OPEN_REJECT;
1960 ts->open_rej_reason = SAS_OREJ_EPROTO;
1962 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1963 pm8001_dbg(pm8001_ha, IO,
1964 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
1965 ts->resp = SAS_TASK_COMPLETE;
1966 ts->stat = SAS_OPEN_REJECT;
1967 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1969 case IO_OPEN_CNX_ERROR_BREAK:
1970 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
1971 ts->resp = SAS_TASK_COMPLETE;
1972 ts->stat = SAS_OPEN_REJECT;
1973 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1975 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1976 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
1977 ts->resp = SAS_TASK_COMPLETE;
1978 ts->stat = SAS_OPEN_REJECT;
1979 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1981 pm8001_handle_event(pm8001_ha,
1983 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1985 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1986 pm8001_dbg(pm8001_ha, IO,
1987 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
1988 ts->resp = SAS_TASK_COMPLETE;
1989 ts->stat = SAS_OPEN_REJECT;
1990 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1992 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1993 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
1994 ts->resp = SAS_TASK_COMPLETE;
1995 ts->stat = SAS_OPEN_REJECT;
1996 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1998 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1999 pm8001_dbg(pm8001_ha, IO,
2000 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2001 ts->resp = SAS_TASK_UNDELIVERED;
2002 ts->stat = SAS_OPEN_REJECT;
2003 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2005 case IO_XFER_ERROR_NAK_RECEIVED:
2006 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2007 ts->resp = SAS_TASK_COMPLETE;
2008 ts->stat = SAS_OPEN_REJECT;
2009 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2011 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2012 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2013 ts->resp = SAS_TASK_COMPLETE;
2014 ts->stat = SAS_NAK_R_ERR;
2016 case IO_XFER_ERROR_DMA:
2017 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2018 ts->resp = SAS_TASK_COMPLETE;
2019 ts->stat = SAS_OPEN_REJECT;
2021 case IO_XFER_OPEN_RETRY_TIMEOUT:
2022 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2023 ts->resp = SAS_TASK_COMPLETE;
2024 ts->stat = SAS_OPEN_REJECT;
2025 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2027 case IO_XFER_ERROR_OFFSET_MISMATCH:
2028 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2029 ts->resp = SAS_TASK_COMPLETE;
2030 ts->stat = SAS_OPEN_REJECT;
2032 case IO_PORT_IN_RESET:
2033 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2034 ts->resp = SAS_TASK_COMPLETE;
2035 ts->stat = SAS_OPEN_REJECT;
2037 case IO_DS_NON_OPERATIONAL:
2038 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2039 ts->resp = SAS_TASK_COMPLETE;
2040 ts->stat = SAS_OPEN_REJECT;
2042 pm8001_handle_event(pm8001_ha,
2044 IO_DS_NON_OPERATIONAL);
2046 case IO_DS_IN_RECOVERY:
2047 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2048 ts->resp = SAS_TASK_COMPLETE;
2049 ts->stat = SAS_OPEN_REJECT;
2051 case IO_TM_TAG_NOT_FOUND:
2052 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n");
2053 ts->resp = SAS_TASK_COMPLETE;
2054 ts->stat = SAS_OPEN_REJECT;
2056 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2057 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n");
2058 ts->resp = SAS_TASK_COMPLETE;
2059 ts->stat = SAS_OPEN_REJECT;
2061 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2062 pm8001_dbg(pm8001_ha, IO,
2063 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2064 ts->resp = SAS_TASK_COMPLETE;
2065 ts->stat = SAS_OPEN_REJECT;
2066 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2069 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2070 /* not allowed case. Therefore, return failed status */
2071 ts->resp = SAS_TASK_COMPLETE;
2072 ts->stat = SAS_OPEN_REJECT;
2075 pm8001_dbg(pm8001_ha, IO, "scsi_status = %x\n",
2076 psspPayload->ssp_resp_iu.status);
2077 spin_lock_irqsave(&t->task_state_lock, flags);
2078 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2079 t->task_state_flags |= SAS_TASK_STATE_DONE;
2080 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2081 spin_unlock_irqrestore(&t->task_state_lock, flags);
2082 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2083 t, status, ts->resp, ts->stat);
2084 pm8001_ccb_task_free(pm8001_ha, ccb);
2086 spin_unlock_irqrestore(&t->task_state_lock, flags);
2087 pm8001_ccb_task_free(pm8001_ha, ccb);
2088 mb();/* in order to force CPU ordering */
2093 /*See the comments for mpi_ssp_completion */
2094 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2097 unsigned long flags;
2098 struct task_status_struct *ts;
2099 struct pm8001_ccb_info *ccb;
2100 struct pm8001_device *pm8001_dev;
2101 struct ssp_event_resp *psspPayload =
2102 (struct ssp_event_resp *)(piomb + 4);
2103 u32 event = le32_to_cpu(psspPayload->event);
2104 u32 tag = le32_to_cpu(psspPayload->tag);
2105 u32 port_id = le32_to_cpu(psspPayload->port_id);
2106 u32 dev_id = le32_to_cpu(psspPayload->device_id);
2108 ccb = &pm8001_ha->ccb_info[tag];
2110 pm8001_dev = ccb->device;
2112 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event);
2113 if (unlikely(!t || !t->lldd_task || !t->dev))
2115 ts = &t->task_status;
2116 pm8001_dbg(pm8001_ha, DEVIO, "port_id = %x,device_id = %x\n",
2120 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2121 ts->resp = SAS_TASK_COMPLETE;
2122 ts->stat = SAS_DATA_OVERRUN;
2125 atomic_dec(&pm8001_dev->running_req);
2127 case IO_XFER_ERROR_BREAK:
2128 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2129 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2131 case IO_XFER_ERROR_PHY_NOT_READY:
2132 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2133 ts->resp = SAS_TASK_COMPLETE;
2134 ts->stat = SAS_OPEN_REJECT;
2135 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2137 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2138 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2139 ts->resp = SAS_TASK_COMPLETE;
2140 ts->stat = SAS_OPEN_REJECT;
2141 ts->open_rej_reason = SAS_OREJ_EPROTO;
2143 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2144 pm8001_dbg(pm8001_ha, IO,
2145 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2146 ts->resp = SAS_TASK_COMPLETE;
2147 ts->stat = SAS_OPEN_REJECT;
2148 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2150 case IO_OPEN_CNX_ERROR_BREAK:
2151 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2152 ts->resp = SAS_TASK_COMPLETE;
2153 ts->stat = SAS_OPEN_REJECT;
2154 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2156 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2157 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2158 ts->resp = SAS_TASK_COMPLETE;
2159 ts->stat = SAS_OPEN_REJECT;
2160 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2162 pm8001_handle_event(pm8001_ha,
2164 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2166 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2167 pm8001_dbg(pm8001_ha, IO,
2168 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2169 ts->resp = SAS_TASK_COMPLETE;
2170 ts->stat = SAS_OPEN_REJECT;
2171 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2173 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2174 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2175 ts->resp = SAS_TASK_COMPLETE;
2176 ts->stat = SAS_OPEN_REJECT;
2177 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2179 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2180 pm8001_dbg(pm8001_ha, IO,
2181 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2182 ts->resp = SAS_TASK_COMPLETE;
2183 ts->stat = SAS_OPEN_REJECT;
2184 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2186 case IO_XFER_ERROR_NAK_RECEIVED:
2187 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2188 ts->resp = SAS_TASK_COMPLETE;
2189 ts->stat = SAS_OPEN_REJECT;
2190 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2192 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2193 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2194 ts->resp = SAS_TASK_COMPLETE;
2195 ts->stat = SAS_NAK_R_ERR;
2197 case IO_XFER_OPEN_RETRY_TIMEOUT:
2198 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2199 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2201 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2202 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2203 ts->resp = SAS_TASK_COMPLETE;
2204 ts->stat = SAS_DATA_OVERRUN;
2206 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2207 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2208 ts->resp = SAS_TASK_COMPLETE;
2209 ts->stat = SAS_DATA_OVERRUN;
2211 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2212 pm8001_dbg(pm8001_ha, IO,
2213 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2214 ts->resp = SAS_TASK_COMPLETE;
2215 ts->stat = SAS_DATA_OVERRUN;
2217 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2218 pm8001_dbg(pm8001_ha, IO,
2219 "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n");
2220 ts->resp = SAS_TASK_COMPLETE;
2221 ts->stat = SAS_DATA_OVERRUN;
2223 case IO_XFER_ERROR_OFFSET_MISMATCH:
2224 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2225 ts->resp = SAS_TASK_COMPLETE;
2226 ts->stat = SAS_DATA_OVERRUN;
2228 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2229 pm8001_dbg(pm8001_ha, IO,
2230 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2231 ts->resp = SAS_TASK_COMPLETE;
2232 ts->stat = SAS_DATA_OVERRUN;
2234 case IO_XFER_CMD_FRAME_ISSUED:
2235 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2238 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2239 /* not allowed case. Therefore, return failed status */
2240 ts->resp = SAS_TASK_COMPLETE;
2241 ts->stat = SAS_DATA_OVERRUN;
2244 spin_lock_irqsave(&t->task_state_lock, flags);
2245 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2246 t->task_state_flags |= SAS_TASK_STATE_DONE;
2247 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2248 spin_unlock_irqrestore(&t->task_state_lock, flags);
2249 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2250 t, event, ts->resp, ts->stat);
2251 pm8001_ccb_task_free(pm8001_ha, ccb);
2253 spin_unlock_irqrestore(&t->task_state_lock, flags);
2254 pm8001_ccb_task_free(pm8001_ha, ccb);
2255 mb();/* in order to force CPU ordering */
2260 /*See the comments for mpi_ssp_completion */
2262 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2265 struct pm8001_ccb_info *ccb;
2270 u8 sata_addr_low[4];
2271 u32 temp_sata_addr_low;
2273 u32 temp_sata_addr_hi;
2274 struct sata_completion_resp *psataPayload;
2275 struct task_status_struct *ts;
2276 struct ata_task_resp *resp ;
2278 struct pm8001_device *pm8001_dev;
2279 unsigned long flags;
2281 psataPayload = (struct sata_completion_resp *)(piomb + 4);
2282 status = le32_to_cpu(psataPayload->status);
2283 param = le32_to_cpu(psataPayload->param);
2284 tag = le32_to_cpu(psataPayload->tag);
2286 ccb = &pm8001_ha->ccb_info[tag];
2288 pm8001_dev = ccb->device;
2291 if (t->dev && (t->dev->lldd_dev))
2292 pm8001_dev = t->dev->lldd_dev;
2294 pm8001_dbg(pm8001_ha, FAIL, "task null\n");
2298 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2299 && unlikely(!t || !t->lldd_task || !t->dev)) {
2300 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2304 ts = &t->task_status;
2307 pm8001_dbg(pm8001_ha, IOERR,
2308 "status:0x%x, tag:0x%x, task::0x%p\n",
2311 /* Print sas address of IO failed device */
2312 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2313 (status != IO_UNDERFLOW)) {
2314 if (!((t->dev->parent) &&
2315 (dev_is_expander(t->dev->parent->dev_type)))) {
2316 for (i = 0, j = 4; j <= 7 && i <= 3; i++, j++)
2317 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2318 for (i = 0, j = 0; j <= 3 && i <= 3; i++, j++)
2319 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2320 memcpy(&temp_sata_addr_low, sata_addr_low,
2321 sizeof(sata_addr_low));
2322 memcpy(&temp_sata_addr_hi, sata_addr_hi,
2323 sizeof(sata_addr_hi));
2324 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2325 |((temp_sata_addr_hi << 8) &
2327 ((temp_sata_addr_hi >> 8)
2329 ((temp_sata_addr_hi << 24) &
2331 temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2333 ((temp_sata_addr_low << 8)
2335 ((temp_sata_addr_low >> 8)
2337 ((temp_sata_addr_low << 24)
2339 pm8001_dev->attached_phy +
2341 pm8001_dbg(pm8001_ha, FAIL,
2342 "SAS Address of IO Failure Drive:%08x%08x\n",
2344 temp_sata_addr_low);
2346 pm8001_dbg(pm8001_ha, FAIL,
2347 "SAS Address of IO Failure Drive:%016llx\n",
2348 SAS_ADDR(t->dev->sas_addr));
2353 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2355 ts->resp = SAS_TASK_COMPLETE;
2356 ts->stat = SAS_SAM_STAT_GOOD;
2357 /* check if response is for SEND READ LOG */
2359 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2360 pm8001_send_abort_all(pm8001_ha, pm8001_dev);
2362 pm8001_tag_free(pm8001_ha, tag);
2368 ts->resp = SAS_TASK_COMPLETE;
2369 ts->stat = SAS_PROTO_RESPONSE;
2370 ts->residual = param;
2371 pm8001_dbg(pm8001_ha, IO,
2372 "SAS_PROTO_RESPONSE len = %d\n",
2374 sata_resp = &psataPayload->sata_resp[0];
2375 resp = (struct ata_task_resp *)ts->buf;
2376 if (t->ata_task.dma_xfer == 0 &&
2377 t->data_dir == DMA_FROM_DEVICE) {
2378 len = sizeof(struct pio_setup_fis);
2379 pm8001_dbg(pm8001_ha, IO,
2380 "PIO read len = %d\n", len);
2381 } else if (t->ata_task.use_ncq &&
2382 t->data_dir != DMA_NONE) {
2383 len = sizeof(struct set_dev_bits_fis);
2384 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n",
2387 len = sizeof(struct dev_to_host_fis);
2388 pm8001_dbg(pm8001_ha, IO, "other len = %d\n",
2391 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2392 resp->frame_len = len;
2393 memcpy(&resp->ending_fis[0], sata_resp, len);
2394 ts->buf_valid_size = sizeof(*resp);
2396 pm8001_dbg(pm8001_ha, IO,
2397 "response too large\n");
2400 atomic_dec(&pm8001_dev->running_req);
2403 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
2404 ts->resp = SAS_TASK_COMPLETE;
2405 ts->stat = SAS_ABORTED_TASK;
2407 atomic_dec(&pm8001_dev->running_req);
2409 /* following cases are to do cases */
2411 /* SATA Completion with error */
2412 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param);
2413 ts->resp = SAS_TASK_COMPLETE;
2414 ts->stat = SAS_DATA_UNDERRUN;
2415 ts->residual = param;
2417 atomic_dec(&pm8001_dev->running_req);
2420 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2421 ts->resp = SAS_TASK_UNDELIVERED;
2422 ts->stat = SAS_PHY_DOWN;
2424 atomic_dec(&pm8001_dev->running_req);
2426 case IO_XFER_ERROR_BREAK:
2427 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2428 ts->resp = SAS_TASK_COMPLETE;
2429 ts->stat = SAS_INTERRUPTED;
2431 atomic_dec(&pm8001_dev->running_req);
2433 case IO_XFER_ERROR_PHY_NOT_READY:
2434 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2435 ts->resp = SAS_TASK_COMPLETE;
2436 ts->stat = SAS_OPEN_REJECT;
2437 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2439 atomic_dec(&pm8001_dev->running_req);
2441 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2442 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2443 ts->resp = SAS_TASK_COMPLETE;
2444 ts->stat = SAS_OPEN_REJECT;
2445 ts->open_rej_reason = SAS_OREJ_EPROTO;
2447 atomic_dec(&pm8001_dev->running_req);
2449 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2450 pm8001_dbg(pm8001_ha, IO,
2451 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2452 ts->resp = SAS_TASK_COMPLETE;
2453 ts->stat = SAS_OPEN_REJECT;
2454 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2456 atomic_dec(&pm8001_dev->running_req);
2458 case IO_OPEN_CNX_ERROR_BREAK:
2459 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2460 ts->resp = SAS_TASK_COMPLETE;
2461 ts->stat = SAS_OPEN_REJECT;
2462 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2464 atomic_dec(&pm8001_dev->running_req);
2466 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2467 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2468 ts->resp = SAS_TASK_COMPLETE;
2469 ts->stat = SAS_DEV_NO_RESPONSE;
2470 if (!t->uldd_task) {
2471 pm8001_handle_event(pm8001_ha,
2473 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2474 ts->resp = SAS_TASK_UNDELIVERED;
2475 ts->stat = SAS_QUEUE_FULL;
2476 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2480 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2481 pm8001_dbg(pm8001_ha, IO,
2482 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2483 ts->resp = SAS_TASK_UNDELIVERED;
2484 ts->stat = SAS_OPEN_REJECT;
2485 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2486 if (!t->uldd_task) {
2487 pm8001_handle_event(pm8001_ha,
2489 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2490 ts->resp = SAS_TASK_UNDELIVERED;
2491 ts->stat = SAS_QUEUE_FULL;
2492 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2496 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2497 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2498 ts->resp = SAS_TASK_COMPLETE;
2499 ts->stat = SAS_OPEN_REJECT;
2500 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2502 atomic_dec(&pm8001_dev->running_req);
2504 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2505 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n");
2506 ts->resp = SAS_TASK_COMPLETE;
2507 ts->stat = SAS_DEV_NO_RESPONSE;
2508 if (!t->uldd_task) {
2509 pm8001_handle_event(pm8001_ha,
2511 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2512 ts->resp = SAS_TASK_UNDELIVERED;
2513 ts->stat = SAS_QUEUE_FULL;
2514 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2518 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2519 pm8001_dbg(pm8001_ha, IO,
2520 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2521 ts->resp = SAS_TASK_COMPLETE;
2522 ts->stat = SAS_OPEN_REJECT;
2523 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2525 atomic_dec(&pm8001_dev->running_req);
2527 case IO_XFER_ERROR_NAK_RECEIVED:
2528 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2529 ts->resp = SAS_TASK_COMPLETE;
2530 ts->stat = SAS_NAK_R_ERR;
2532 atomic_dec(&pm8001_dev->running_req);
2534 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2535 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2536 ts->resp = SAS_TASK_COMPLETE;
2537 ts->stat = SAS_NAK_R_ERR;
2539 atomic_dec(&pm8001_dev->running_req);
2541 case IO_XFER_ERROR_DMA:
2542 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2543 ts->resp = SAS_TASK_COMPLETE;
2544 ts->stat = SAS_ABORTED_TASK;
2546 atomic_dec(&pm8001_dev->running_req);
2548 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2549 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n");
2550 ts->resp = SAS_TASK_UNDELIVERED;
2551 ts->stat = SAS_DEV_NO_RESPONSE;
2553 atomic_dec(&pm8001_dev->running_req);
2555 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2556 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2557 ts->resp = SAS_TASK_COMPLETE;
2558 ts->stat = SAS_DATA_UNDERRUN;
2560 atomic_dec(&pm8001_dev->running_req);
2562 case IO_XFER_OPEN_RETRY_TIMEOUT:
2563 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2564 ts->resp = SAS_TASK_COMPLETE;
2565 ts->stat = SAS_OPEN_TO;
2567 atomic_dec(&pm8001_dev->running_req);
2569 case IO_PORT_IN_RESET:
2570 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2571 ts->resp = SAS_TASK_COMPLETE;
2572 ts->stat = SAS_DEV_NO_RESPONSE;
2574 atomic_dec(&pm8001_dev->running_req);
2576 case IO_DS_NON_OPERATIONAL:
2577 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2578 ts->resp = SAS_TASK_COMPLETE;
2579 ts->stat = SAS_DEV_NO_RESPONSE;
2580 if (!t->uldd_task) {
2581 pm8001_handle_event(pm8001_ha, pm8001_dev,
2582 IO_DS_NON_OPERATIONAL);
2583 ts->resp = SAS_TASK_UNDELIVERED;
2584 ts->stat = SAS_QUEUE_FULL;
2585 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2589 case IO_DS_IN_RECOVERY:
2590 pm8001_dbg(pm8001_ha, IO, " IO_DS_IN_RECOVERY\n");
2591 ts->resp = SAS_TASK_COMPLETE;
2592 ts->stat = SAS_DEV_NO_RESPONSE;
2594 atomic_dec(&pm8001_dev->running_req);
2596 case IO_DS_IN_ERROR:
2597 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n");
2598 ts->resp = SAS_TASK_COMPLETE;
2599 ts->stat = SAS_DEV_NO_RESPONSE;
2600 if (!t->uldd_task) {
2601 pm8001_handle_event(pm8001_ha, pm8001_dev,
2603 ts->resp = SAS_TASK_UNDELIVERED;
2604 ts->stat = SAS_QUEUE_FULL;
2605 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2609 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2610 pm8001_dbg(pm8001_ha, IO,
2611 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2612 ts->resp = SAS_TASK_COMPLETE;
2613 ts->stat = SAS_OPEN_REJECT;
2614 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2616 atomic_dec(&pm8001_dev->running_req);
2619 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2620 /* not allowed case. Therefore, return failed status */
2621 ts->resp = SAS_TASK_COMPLETE;
2622 ts->stat = SAS_DEV_NO_RESPONSE;
2624 atomic_dec(&pm8001_dev->running_req);
2627 spin_lock_irqsave(&t->task_state_lock, flags);
2628 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2629 t->task_state_flags |= SAS_TASK_STATE_DONE;
2630 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2631 spin_unlock_irqrestore(&t->task_state_lock, flags);
2632 pm8001_dbg(pm8001_ha, FAIL,
2633 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2634 t, status, ts->resp, ts->stat);
2635 pm8001_ccb_task_free(pm8001_ha, ccb);
2637 spin_unlock_irqrestore(&t->task_state_lock, flags);
2638 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2642 /*See the comments for mpi_ssp_completion */
2643 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2646 struct task_status_struct *ts;
2647 struct pm8001_ccb_info *ccb;
2648 struct pm8001_device *pm8001_dev;
2649 struct sata_event_resp *psataPayload =
2650 (struct sata_event_resp *)(piomb + 4);
2651 u32 event = le32_to_cpu(psataPayload->event);
2652 u32 tag = le32_to_cpu(psataPayload->tag);
2653 u32 port_id = le32_to_cpu(psataPayload->port_id);
2654 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2657 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);
2659 /* Check if this is NCQ error */
2660 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2661 /* find device using device id */
2662 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2663 /* send read log extension */
2665 pm8001_send_read_log(pm8001_ha, pm8001_dev);
2669 ccb = &pm8001_ha->ccb_info[tag];
2671 pm8001_dev = ccb->device;
2673 pm8001_dbg(pm8001_ha, FAIL, "sata IO status 0x%x\n", event);
2674 if (unlikely(!t || !t->lldd_task || !t->dev))
2676 ts = &t->task_status;
2677 pm8001_dbg(pm8001_ha, DEVIO,
2678 "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n",
2679 port_id, dev_id, tag, event);
2682 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2683 ts->resp = SAS_TASK_COMPLETE;
2684 ts->stat = SAS_DATA_OVERRUN;
2687 case IO_XFER_ERROR_BREAK:
2688 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2689 ts->resp = SAS_TASK_COMPLETE;
2690 ts->stat = SAS_INTERRUPTED;
2692 case IO_XFER_ERROR_PHY_NOT_READY:
2693 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2694 ts->resp = SAS_TASK_COMPLETE;
2695 ts->stat = SAS_OPEN_REJECT;
2696 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2698 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2699 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2700 ts->resp = SAS_TASK_COMPLETE;
2701 ts->stat = SAS_OPEN_REJECT;
2702 ts->open_rej_reason = SAS_OREJ_EPROTO;
2704 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2705 pm8001_dbg(pm8001_ha, IO,
2706 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2707 ts->resp = SAS_TASK_COMPLETE;
2708 ts->stat = SAS_OPEN_REJECT;
2709 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2711 case IO_OPEN_CNX_ERROR_BREAK:
2712 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2713 ts->resp = SAS_TASK_COMPLETE;
2714 ts->stat = SAS_OPEN_REJECT;
2715 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2717 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2718 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2719 ts->resp = SAS_TASK_UNDELIVERED;
2720 ts->stat = SAS_DEV_NO_RESPONSE;
2721 if (!t->uldd_task) {
2722 pm8001_handle_event(pm8001_ha,
2724 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2725 ts->resp = SAS_TASK_COMPLETE;
2726 ts->stat = SAS_QUEUE_FULL;
2730 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2731 pm8001_dbg(pm8001_ha, IO,
2732 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2733 ts->resp = SAS_TASK_UNDELIVERED;
2734 ts->stat = SAS_OPEN_REJECT;
2735 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2737 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2738 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2739 ts->resp = SAS_TASK_COMPLETE;
2740 ts->stat = SAS_OPEN_REJECT;
2741 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2743 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2744 pm8001_dbg(pm8001_ha, IO,
2745 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2746 ts->resp = SAS_TASK_COMPLETE;
2747 ts->stat = SAS_OPEN_REJECT;
2748 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2750 case IO_XFER_ERROR_NAK_RECEIVED:
2751 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2752 ts->resp = SAS_TASK_COMPLETE;
2753 ts->stat = SAS_NAK_R_ERR;
2755 case IO_XFER_ERROR_PEER_ABORTED:
2756 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n");
2757 ts->resp = SAS_TASK_COMPLETE;
2758 ts->stat = SAS_NAK_R_ERR;
2760 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2761 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2762 ts->resp = SAS_TASK_COMPLETE;
2763 ts->stat = SAS_DATA_UNDERRUN;
2765 case IO_XFER_OPEN_RETRY_TIMEOUT:
2766 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2767 ts->resp = SAS_TASK_COMPLETE;
2768 ts->stat = SAS_OPEN_TO;
2770 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2771 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2772 ts->resp = SAS_TASK_COMPLETE;
2773 ts->stat = SAS_OPEN_TO;
2775 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2776 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2777 ts->resp = SAS_TASK_COMPLETE;
2778 ts->stat = SAS_OPEN_TO;
2780 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2781 pm8001_dbg(pm8001_ha, IO,
2782 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2783 ts->resp = SAS_TASK_COMPLETE;
2784 ts->stat = SAS_OPEN_TO;
2786 case IO_XFER_ERROR_OFFSET_MISMATCH:
2787 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2788 ts->resp = SAS_TASK_COMPLETE;
2789 ts->stat = SAS_OPEN_TO;
2791 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2792 pm8001_dbg(pm8001_ha, IO,
2793 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2794 ts->resp = SAS_TASK_COMPLETE;
2795 ts->stat = SAS_OPEN_TO;
2797 case IO_XFER_CMD_FRAME_ISSUED:
2798 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2800 case IO_XFER_PIO_SETUP_ERROR:
2801 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n");
2802 ts->resp = SAS_TASK_COMPLETE;
2803 ts->stat = SAS_OPEN_TO;
2806 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2807 /* not allowed case. Therefore, return failed status */
2808 ts->resp = SAS_TASK_COMPLETE;
2809 ts->stat = SAS_OPEN_TO;
2814 /*See the comments for mpi_ssp_completion */
2816 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2819 struct pm8001_ccb_info *ccb;
2820 unsigned long flags;
2823 struct smp_completion_resp *psmpPayload;
2824 struct task_status_struct *ts;
2825 struct pm8001_device *pm8001_dev;
2827 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2828 status = le32_to_cpu(psmpPayload->status);
2829 tag = le32_to_cpu(psmpPayload->tag);
2831 ccb = &pm8001_ha->ccb_info[tag];
2833 ts = &t->task_status;
2834 pm8001_dev = ccb->device;
2836 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status);
2837 pm8001_dbg(pm8001_ha, IOERR,
2838 "status:0x%x, tag:0x%x, task:0x%p\n",
2841 if (unlikely(!t || !t->lldd_task || !t->dev))
2846 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2847 ts->resp = SAS_TASK_COMPLETE;
2848 ts->stat = SAS_SAM_STAT_GOOD;
2850 atomic_dec(&pm8001_dev->running_req);
2853 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n");
2854 ts->resp = SAS_TASK_COMPLETE;
2855 ts->stat = SAS_ABORTED_TASK;
2857 atomic_dec(&pm8001_dev->running_req);
2860 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2861 ts->resp = SAS_TASK_COMPLETE;
2862 ts->stat = SAS_DATA_OVERRUN;
2865 atomic_dec(&pm8001_dev->running_req);
2868 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2869 ts->resp = SAS_TASK_COMPLETE;
2870 ts->stat = SAS_PHY_DOWN;
2872 case IO_ERROR_HW_TIMEOUT:
2873 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n");
2874 ts->resp = SAS_TASK_COMPLETE;
2875 ts->stat = SAS_SAM_STAT_BUSY;
2877 case IO_XFER_ERROR_BREAK:
2878 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2879 ts->resp = SAS_TASK_COMPLETE;
2880 ts->stat = SAS_SAM_STAT_BUSY;
2882 case IO_XFER_ERROR_PHY_NOT_READY:
2883 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2884 ts->resp = SAS_TASK_COMPLETE;
2885 ts->stat = SAS_SAM_STAT_BUSY;
2887 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2888 pm8001_dbg(pm8001_ha, IO,
2889 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2890 ts->resp = SAS_TASK_COMPLETE;
2891 ts->stat = SAS_OPEN_REJECT;
2892 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2894 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2895 pm8001_dbg(pm8001_ha, IO,
2896 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2897 ts->resp = SAS_TASK_COMPLETE;
2898 ts->stat = SAS_OPEN_REJECT;
2899 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2901 case IO_OPEN_CNX_ERROR_BREAK:
2902 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2903 ts->resp = SAS_TASK_COMPLETE;
2904 ts->stat = SAS_OPEN_REJECT;
2905 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2907 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2908 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2909 ts->resp = SAS_TASK_COMPLETE;
2910 ts->stat = SAS_OPEN_REJECT;
2911 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2912 pm8001_handle_event(pm8001_ha,
2914 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2916 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2917 pm8001_dbg(pm8001_ha, IO,
2918 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2919 ts->resp = SAS_TASK_COMPLETE;
2920 ts->stat = SAS_OPEN_REJECT;
2921 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2923 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2924 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2925 ts->resp = SAS_TASK_COMPLETE;
2926 ts->stat = SAS_OPEN_REJECT;
2927 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2929 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2930 pm8001_dbg(pm8001_ha, IO,
2931 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2932 ts->resp = SAS_TASK_COMPLETE;
2933 ts->stat = SAS_OPEN_REJECT;
2934 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2936 case IO_XFER_ERROR_RX_FRAME:
2937 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n");
2938 ts->resp = SAS_TASK_COMPLETE;
2939 ts->stat = SAS_DEV_NO_RESPONSE;
2941 case IO_XFER_OPEN_RETRY_TIMEOUT:
2942 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2943 ts->resp = SAS_TASK_COMPLETE;
2944 ts->stat = SAS_OPEN_REJECT;
2945 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2947 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2948 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n");
2949 ts->resp = SAS_TASK_COMPLETE;
2950 ts->stat = SAS_QUEUE_FULL;
2952 case IO_PORT_IN_RESET:
2953 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2954 ts->resp = SAS_TASK_COMPLETE;
2955 ts->stat = SAS_OPEN_REJECT;
2956 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2958 case IO_DS_NON_OPERATIONAL:
2959 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2960 ts->resp = SAS_TASK_COMPLETE;
2961 ts->stat = SAS_DEV_NO_RESPONSE;
2963 case IO_DS_IN_RECOVERY:
2964 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2965 ts->resp = SAS_TASK_COMPLETE;
2966 ts->stat = SAS_OPEN_REJECT;
2967 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2969 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2970 pm8001_dbg(pm8001_ha, IO,
2971 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2972 ts->resp = SAS_TASK_COMPLETE;
2973 ts->stat = SAS_OPEN_REJECT;
2974 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2977 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2978 ts->resp = SAS_TASK_COMPLETE;
2979 ts->stat = SAS_DEV_NO_RESPONSE;
2980 /* not allowed case. Therefore, return failed status */
2983 spin_lock_irqsave(&t->task_state_lock, flags);
2984 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2985 t->task_state_flags |= SAS_TASK_STATE_DONE;
2986 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2987 spin_unlock_irqrestore(&t->task_state_lock, flags);
2988 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2989 t, status, ts->resp, ts->stat);
2990 pm8001_ccb_task_free(pm8001_ha, ccb);
2992 spin_unlock_irqrestore(&t->task_state_lock, flags);
2993 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2997 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
3000 struct set_dev_state_resp *pPayload =
3001 (struct set_dev_state_resp *)(piomb + 4);
3002 u32 tag = le32_to_cpu(pPayload->tag);
3003 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3004 struct pm8001_device *pm8001_dev = ccb->device;
3005 u32 status = le32_to_cpu(pPayload->status);
3006 u32 device_id = le32_to_cpu(pPayload->device_id);
3007 u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS;
3008 u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS;
3010 pm8001_dbg(pm8001_ha, MSG,
3011 "Set device id = 0x%x state from 0x%x to 0x%x status = 0x%x!\n",
3012 device_id, pds, nds, status);
3013 complete(pm8001_dev->setds_completion);
3014 pm8001_ccb_free(pm8001_ha, ccb);
3017 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3019 struct get_nvm_data_resp *pPayload =
3020 (struct get_nvm_data_resp *)(piomb + 4);
3021 u32 tag = le32_to_cpu(pPayload->tag);
3022 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3023 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3025 complete(pm8001_ha->nvmd_completion);
3026 pm8001_dbg(pm8001_ha, MSG, "Set nvm data complete!\n");
3027 if ((dlen_status & NVMD_STAT) != 0) {
3028 pm8001_dbg(pm8001_ha, FAIL, "Set nvm data error %x\n",
3031 pm8001_ccb_free(pm8001_ha, ccb);
3035 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3037 struct fw_control_ex *fw_control_context;
3038 struct get_nvm_data_resp *pPayload =
3039 (struct get_nvm_data_resp *)(piomb + 4);
3040 u32 tag = le32_to_cpu(pPayload->tag);
3041 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3042 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3043 u32 ir_tds_bn_dps_das_nvm =
3044 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
3045 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
3046 fw_control_context = ccb->fw_control_context;
3048 pm8001_dbg(pm8001_ha, MSG, "Get nvm data complete!\n");
3049 if ((dlen_status & NVMD_STAT) != 0) {
3050 pm8001_dbg(pm8001_ha, FAIL, "Get nvm data error %x\n",
3052 complete(pm8001_ha->nvmd_completion);
3053 /* We should free tag during failure also, the tag is not being
3054 * freed by requesting path anywhere.
3056 pm8001_ccb_free(pm8001_ha, ccb);
3059 if (ir_tds_bn_dps_das_nvm & IPMode) {
3060 /* indirect mode - IR bit set */
3061 pm8001_dbg(pm8001_ha, MSG, "Get NVMD success, IR=1\n");
3062 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
3063 if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
3064 memcpy(pm8001_ha->sas_addr,
3065 ((u8 *)virt_addr + 4),
3067 pm8001_dbg(pm8001_ha, MSG, "Get SAS address from VPD successfully!\n");
3069 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
3070 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
3071 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
3073 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
3074 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
3077 /* Should not be happened*/
3078 pm8001_dbg(pm8001_ha, MSG,
3079 "(IR=1)Wrong Device type 0x%x\n",
3080 ir_tds_bn_dps_das_nvm);
3082 } else /* direct mode */{
3083 pm8001_dbg(pm8001_ha, MSG,
3084 "Get NVMD success, IR=0, dataLen=%d\n",
3085 (dlen_status & NVMD_LEN) >> 24);
3087 /* Though fw_control_context is freed below, usrAddr still needs
3088 * to be updated as this holds the response to the request function
3090 memcpy(fw_control_context->usrAddr,
3091 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
3092 fw_control_context->len);
3093 kfree(ccb->fw_control_context);
3094 /* To avoid race condition, complete should be
3095 * called after the message is copied to
3096 * fw_control_context->usrAddr
3098 complete(pm8001_ha->nvmd_completion);
3099 pm8001_dbg(pm8001_ha, MSG, "Get nvmd data complete!\n");
3100 pm8001_ccb_free(pm8001_ha, ccb);
3103 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
3106 struct local_phy_ctl_resp *pPayload =
3107 (struct local_phy_ctl_resp *)(piomb + 4);
3108 u32 status = le32_to_cpu(pPayload->status);
3109 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
3110 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
3111 tag = le32_to_cpu(pPayload->tag);
3113 pm8001_dbg(pm8001_ha, MSG,
3114 "%x phy execute %x phy op failed!\n",
3117 pm8001_dbg(pm8001_ha, MSG,
3118 "%x phy execute %x phy op success!\n",
3120 pm8001_ha->phy[phy_id].reset_success = true;
3122 if (pm8001_ha->phy[phy_id].enable_completion) {
3123 complete(pm8001_ha->phy[phy_id].enable_completion);
3124 pm8001_ha->phy[phy_id].enable_completion = NULL;
3126 pm8001_tag_free(pm8001_ha, tag);
3131 * pm8001_bytes_dmaed - one of the interface function communication with libsas
3132 * @pm8001_ha: our hba card information
3133 * @i: which phy that received the event.
3135 * when HBA driver received the identify done event or initiate FIS received
3136 * event(for SATA), it will invoke this function to notify the sas layer that
3137 * the sas toplogy has formed, please discover the the whole sas domain,
3138 * while receive a broadcast(change) primitive just tell the sas
3139 * layer to discover the changed domain rather than the whole domain.
3141 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
3143 struct pm8001_phy *phy = &pm8001_ha->phy[i];
3144 struct asd_sas_phy *sas_phy = &phy->sas_phy;
3145 if (!phy->phy_attached)
3149 struct sas_phy *sphy = sas_phy->phy;
3150 sphy->negotiated_linkrate = sas_phy->linkrate;
3151 sphy->minimum_linkrate = phy->minimum_linkrate;
3152 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3153 sphy->maximum_linkrate = phy->maximum_linkrate;
3154 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
3157 if (phy->phy_type & PORT_TYPE_SAS) {
3158 struct sas_identify_frame *id;
3159 id = (struct sas_identify_frame *)phy->frame_rcvd;
3160 id->dev_type = phy->identify.device_type;
3161 id->initiator_bits = SAS_PROTOCOL_ALL;
3162 id->target_bits = phy->identify.target_port_protocols;
3163 } else if (phy->phy_type & PORT_TYPE_SATA) {
3166 pm8001_dbg(pm8001_ha, MSG, "phy %d byte dmaded.\n", i);
3168 sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
3169 sas_notify_port_event(sas_phy, PORTE_BYTES_DMAED, GFP_ATOMIC);
3172 /* Get the link rate speed */
3173 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
3175 struct sas_phy *sas_phy = phy->sas_phy.phy;
3177 switch (link_rate) {
3179 phy->sas_phy.linkrate = SAS_LINK_RATE_12_0_GBPS;
3180 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_12_0_GBPS;
3183 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
3184 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
3187 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3188 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
3191 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3192 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
3195 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3196 sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
3197 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3198 sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
3199 sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
3203 * pm8001_get_attached_sas_addr - extract/generate attached SAS address
3204 * @phy: pointer to asd_phy
3205 * @sas_addr: pointer to buffer where the SAS address is to be written
3207 * This function extracts the SAS address from an IDENTIFY frame
3208 * received. If OOB is SATA, then a SAS address is generated from the
3211 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3214 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
3217 if (phy->sas_phy.frame_rcvd[0] == 0x34
3218 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3219 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3220 /* FIS device-to-host */
3221 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3222 addr += phy->sas_phy.id;
3223 *(__be64 *)sas_addr = cpu_to_be64(addr);
3225 struct sas_identify_frame *idframe =
3226 (void *) phy->sas_phy.frame_rcvd;
3227 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3232 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3233 * @pm8001_ha: our hba card information
3234 * @Qnum: the outbound queue message number.
3235 * @SEA: source of event to ack
3236 * @port_id: port id.
3238 * @param0: parameter 0.
3239 * @param1: parameter 1.
3241 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3242 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3244 struct hw_event_ack_req payload;
3245 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3247 memset((u8 *)&payload, 0, sizeof(payload));
3248 payload.tag = cpu_to_le32(1);
3249 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3250 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
3251 payload.param0 = cpu_to_le32(param0);
3252 payload.param1 = cpu_to_le32(param1);
3254 pm8001_mpi_build_cmd(pm8001_ha, Qnum, opc, &payload, sizeof(payload), 0);
3257 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3258 u32 phyId, u32 phy_op);
3261 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3262 * @pm8001_ha: our hba card information
3263 * @piomb: IO message buffer
3266 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3268 struct hw_event_resp *pPayload =
3269 (struct hw_event_resp *)(piomb + 4);
3270 u32 lr_evt_status_phyid_portid =
3271 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3273 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3274 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3276 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3277 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3278 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3279 struct pm8001_port *port = &pm8001_ha->port[port_id];
3280 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3281 unsigned long flags;
3282 u8 deviceType = pPayload->sas_identify.dev_type;
3284 port->port_id = port_id;
3285 port->port_state = portstate;
3286 phy->phy_state = PHY_STATE_LINK_UP_SPC;
3287 pm8001_dbg(pm8001_ha, MSG,
3288 "HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3291 switch (deviceType) {
3292 case SAS_PHY_UNUSED:
3293 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n");
3295 case SAS_END_DEVICE:
3296 pm8001_dbg(pm8001_ha, MSG, "end device.\n");
3297 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3298 PHY_NOTIFY_ENABLE_SPINUP);
3299 port->port_attached = 1;
3300 pm8001_get_lrate_mode(phy, link_rate);
3302 case SAS_EDGE_EXPANDER_DEVICE:
3303 pm8001_dbg(pm8001_ha, MSG, "expander device.\n");
3304 port->port_attached = 1;
3305 pm8001_get_lrate_mode(phy, link_rate);
3307 case SAS_FANOUT_EXPANDER_DEVICE:
3308 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n");
3309 port->port_attached = 1;
3310 pm8001_get_lrate_mode(phy, link_rate);
3313 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n",
3317 phy->phy_type |= PORT_TYPE_SAS;
3318 phy->identify.device_type = deviceType;
3319 phy->phy_attached = 1;
3320 if (phy->identify.device_type == SAS_END_DEVICE)
3321 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3322 else if (phy->identify.device_type != SAS_PHY_UNUSED)
3323 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3324 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3325 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3326 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3327 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3328 sizeof(struct sas_identify_frame)-4);
3329 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3330 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3331 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3332 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3333 mdelay(200);/*delay a moment to wait disk to spinup*/
3334 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3338 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3339 * @pm8001_ha: our hba card information
3340 * @piomb: IO message buffer
3343 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3345 struct hw_event_resp *pPayload =
3346 (struct hw_event_resp *)(piomb + 4);
3347 u32 lr_evt_status_phyid_portid =
3348 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3350 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3351 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3353 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3354 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3355 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3356 struct pm8001_port *port = &pm8001_ha->port[port_id];
3357 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3358 unsigned long flags;
3359 pm8001_dbg(pm8001_ha, DEVIO, "HW_EVENT_SATA_PHY_UP port id = %d, phy id = %d\n",
3362 port->port_id = port_id;
3363 port->port_state = portstate;
3364 phy->phy_state = PHY_STATE_LINK_UP_SPC;
3365 port->port_attached = 1;
3366 pm8001_get_lrate_mode(phy, link_rate);
3367 phy->phy_type |= PORT_TYPE_SATA;
3368 phy->phy_attached = 1;
3369 phy->sas_phy.oob_mode = SATA_OOB_MODE;
3370 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3371 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3372 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3373 sizeof(struct dev_to_host_fis));
3374 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3375 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3376 phy->identify.device_type = SAS_SATA_DEV;
3377 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3378 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3379 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3383 * hw_event_phy_down -we should notify the libsas the phy is down.
3384 * @pm8001_ha: our hba card information
3385 * @piomb: IO message buffer
3388 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3390 struct hw_event_resp *pPayload =
3391 (struct hw_event_resp *)(piomb + 4);
3392 u32 lr_evt_status_phyid_portid =
3393 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3394 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3396 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3397 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3398 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3399 struct pm8001_port *port = &pm8001_ha->port[port_id];
3400 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3401 port->port_state = portstate;
3403 phy->identify.device_type = 0;
3404 phy->phy_attached = 0;
3405 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3406 switch (portstate) {
3410 pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n",
3412 pm8001_dbg(pm8001_ha, MSG,
3413 " Last phy Down and port invalid\n");
3414 port->port_attached = 0;
3415 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3416 port_id, phy_id, 0, 0);
3419 pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n",
3422 case PORT_NOT_ESTABLISHED:
3423 pm8001_dbg(pm8001_ha, MSG,
3424 " phy Down and PORT_NOT_ESTABLISHED\n");
3425 port->port_attached = 0;
3428 pm8001_dbg(pm8001_ha, MSG, " phy Down and PORT_LOSTCOMM\n");
3429 pm8001_dbg(pm8001_ha, MSG,
3430 " Last phy Down and port invalid\n");
3431 port->port_attached = 0;
3432 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3433 port_id, phy_id, 0, 0);
3436 port->port_attached = 0;
3437 pm8001_dbg(pm8001_ha, DEVIO, " phy Down and(default) = %x\n",
3445 * pm8001_mpi_reg_resp -process register device ID response.
3446 * @pm8001_ha: our hba card information
3447 * @piomb: IO message buffer
3449 * when sas layer find a device it will notify LLDD, then the driver register
3450 * the domain device to FW, this event is the return device ID which the FW
3451 * has assigned, from now, inter-communication with FW is no longer using the
3452 * SAS address, use device ID which FW assigned.
3454 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3459 struct pm8001_ccb_info *ccb;
3460 struct pm8001_device *pm8001_dev;
3461 struct dev_reg_resp *registerRespPayload =
3462 (struct dev_reg_resp *)(piomb + 4);
3464 htag = le32_to_cpu(registerRespPayload->tag);
3465 ccb = &pm8001_ha->ccb_info[htag];
3466 pm8001_dev = ccb->device;
3467 status = le32_to_cpu(registerRespPayload->status);
3468 device_id = le32_to_cpu(registerRespPayload->device_id);
3469 pm8001_dbg(pm8001_ha, MSG, " register device is status = %d\n",
3472 case DEVREG_SUCCESS:
3473 pm8001_dbg(pm8001_ha, MSG, "DEVREG_SUCCESS\n");
3474 pm8001_dev->device_id = device_id;
3476 case DEVREG_FAILURE_OUT_OF_RESOURCE:
3477 pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_OUT_OF_RESOURCE\n");
3479 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3480 pm8001_dbg(pm8001_ha, MSG,
3481 "DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n");
3483 case DEVREG_FAILURE_INVALID_PHY_ID:
3484 pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_INVALID_PHY_ID\n");
3486 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3487 pm8001_dbg(pm8001_ha, MSG,
3488 "DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n");
3490 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3491 pm8001_dbg(pm8001_ha, MSG,
3492 "DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n");
3494 case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3495 pm8001_dbg(pm8001_ha, MSG,
3496 "DEVREG_FAILURE_PORT_NOT_VALID_STATE\n");
3498 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3499 pm8001_dbg(pm8001_ha, MSG,
3500 "DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n");
3503 pm8001_dbg(pm8001_ha, MSG,
3504 "DEVREG_FAILURE_DEVICE_TYPE_NOT_SUPPORTED\n");
3507 complete(pm8001_dev->dcompletion);
3508 pm8001_ccb_free(pm8001_ha, ccb);
3512 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3516 struct dev_reg_resp *registerRespPayload =
3517 (struct dev_reg_resp *)(piomb + 4);
3519 status = le32_to_cpu(registerRespPayload->status);
3520 device_id = le32_to_cpu(registerRespPayload->device_id);
3522 pm8001_dbg(pm8001_ha, MSG,
3523 " deregister device failed ,status = %x, device_id = %x\n",
3529 * pm8001_mpi_fw_flash_update_resp - Response from FW for flash update command.
3530 * @pm8001_ha: our hba card information
3531 * @piomb: IO message buffer
3533 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
3537 struct fw_flash_Update_resp *ppayload =
3538 (struct fw_flash_Update_resp *)(piomb + 4);
3539 u32 tag = le32_to_cpu(ppayload->tag);
3540 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3542 status = le32_to_cpu(ppayload->status);
3544 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3545 pm8001_dbg(pm8001_ha, MSG,
3546 ": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n");
3548 case FLASH_UPDATE_IN_PROGRESS:
3549 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_IN_PROGRESS\n");
3551 case FLASH_UPDATE_HDR_ERR:
3552 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HDR_ERR\n");
3554 case FLASH_UPDATE_OFFSET_ERR:
3555 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_OFFSET_ERR\n");
3557 case FLASH_UPDATE_CRC_ERR:
3558 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_CRC_ERR\n");
3560 case FLASH_UPDATE_LENGTH_ERR:
3561 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_LENGTH_ERR\n");
3563 case FLASH_UPDATE_HW_ERR:
3564 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HW_ERR\n");
3566 case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3567 pm8001_dbg(pm8001_ha, MSG,
3568 ": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n");
3570 case FLASH_UPDATE_DISABLED:
3571 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_DISABLED\n");
3574 pm8001_dbg(pm8001_ha, DEVIO, "No matched status = %d\n",
3578 kfree(ccb->fw_control_context);
3579 pm8001_ccb_free(pm8001_ha, ccb);
3580 complete(pm8001_ha->nvmd_completion);
3584 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3588 struct general_event_resp *pPayload =
3589 (struct general_event_resp *)(piomb + 4);
3590 status = le32_to_cpu(pPayload->status);
3591 pm8001_dbg(pm8001_ha, MSG, " status = 0x%x\n", status);
3592 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3593 pm8001_dbg(pm8001_ha, MSG, "inb_IOMB_payload[0x%x] 0x%x,\n",
3595 pPayload->inb_IOMB_payload[i]);
3599 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3602 struct pm8001_ccb_info *ccb;
3603 unsigned long flags;
3606 struct task_status_struct *ts;
3607 struct pm8001_device *pm8001_dev;
3609 struct task_abort_resp *pPayload =
3610 (struct task_abort_resp *)(piomb + 4);
3612 status = le32_to_cpu(pPayload->status);
3613 tag = le32_to_cpu(pPayload->tag);
3615 scp = le32_to_cpu(pPayload->scp);
3616 ccb = &pm8001_ha->ccb_info[tag];
3618 pm8001_dev = ccb->device; /* retrieve device */
3621 pm8001_dbg(pm8001_ha, FAIL, " TASK NULL. RETURNING !!!\n");
3624 ts = &t->task_status;
3626 pm8001_dbg(pm8001_ha, FAIL, "task abort failed status 0x%x ,tag = 0x%x, scp= 0x%x\n",
3630 pm8001_dbg(pm8001_ha, EH, "IO_SUCCESS\n");
3631 ts->resp = SAS_TASK_COMPLETE;
3632 ts->stat = SAS_SAM_STAT_GOOD;
3635 pm8001_dbg(pm8001_ha, EH, "IO_NOT_VALID\n");
3636 ts->resp = TMF_RESP_FUNC_FAILED;
3639 spin_lock_irqsave(&t->task_state_lock, flags);
3640 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3641 t->task_state_flags |= SAS_TASK_STATE_DONE;
3642 spin_unlock_irqrestore(&t->task_state_lock, flags);
3643 pm8001_ccb_task_free(pm8001_ha, ccb);
3646 if (pm8001_dev->id & NCQ_ABORT_ALL_FLAG) {
3648 pm8001_dev->id &= ~NCQ_ABORT_ALL_FLAG;
3657 * mpi_hw_event -The hw event has come.
3658 * @pm8001_ha: our hba card information
3659 * @piomb: IO message buffer
3661 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3663 unsigned long flags;
3664 struct hw_event_resp *pPayload =
3665 (struct hw_event_resp *)(piomb + 4);
3666 u32 lr_evt_status_phyid_portid =
3667 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3668 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3670 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3672 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3674 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3675 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3676 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3677 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3678 pm8001_dbg(pm8001_ha, DEVIO,
3679 "SPC HW event for portid:%d, phyid:%d, event:%x, status:%x\n",
3680 port_id, phy_id, eventType, status);
3681 switch (eventType) {
3682 case HW_EVENT_PHY_START_STATUS:
3683 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS status = %x\n",
3688 if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3689 phy->enable_completion != NULL) {
3690 complete(phy->enable_completion);
3691 phy->enable_completion = NULL;
3694 case HW_EVENT_SAS_PHY_UP:
3695 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n");
3696 hw_event_sas_phy_up(pm8001_ha, piomb);
3698 case HW_EVENT_SATA_PHY_UP:
3699 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n");
3700 hw_event_sata_phy_up(pm8001_ha, piomb);
3702 case HW_EVENT_PHY_STOP_STATUS:
3703 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_STOP_STATUS status = %x\n",
3708 case HW_EVENT_SATA_SPINUP_HOLD:
3709 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n");
3710 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD,
3713 case HW_EVENT_PHY_DOWN:
3714 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n");
3715 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL,
3717 phy->phy_attached = 0;
3719 hw_event_phy_down(pm8001_ha, piomb);
3721 case HW_EVENT_PORT_INVALID:
3722 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n");
3723 sas_phy_disconnected(sas_phy);
3724 phy->phy_attached = 0;
3725 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3728 /* the broadcast change primitive received, tell the LIBSAS this event
3729 to revalidate the sas domain*/
3730 case HW_EVENT_BROADCAST_CHANGE:
3731 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n");
3732 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3733 port_id, phy_id, 1, 0);
3734 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3735 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3736 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3737 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3740 case HW_EVENT_PHY_ERROR:
3741 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n");
3742 sas_phy_disconnected(&phy->sas_phy);
3743 phy->phy_attached = 0;
3744 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC);
3746 case HW_EVENT_BROADCAST_EXP:
3747 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n");
3748 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3749 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3750 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3751 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3754 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3755 pm8001_dbg(pm8001_ha, MSG,
3756 "HW_EVENT_LINK_ERR_INVALID_DWORD\n");
3757 pm8001_hw_event_ack_req(pm8001_ha, 0,
3758 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3759 sas_phy_disconnected(sas_phy);
3760 phy->phy_attached = 0;
3761 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3764 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3765 pm8001_dbg(pm8001_ha, MSG,
3766 "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n");
3767 pm8001_hw_event_ack_req(pm8001_ha, 0,
3768 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3769 port_id, phy_id, 0, 0);
3770 sas_phy_disconnected(sas_phy);
3771 phy->phy_attached = 0;
3772 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3775 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3776 pm8001_dbg(pm8001_ha, MSG,
3777 "HW_EVENT_LINK_ERR_CODE_VIOLATION\n");
3778 pm8001_hw_event_ack_req(pm8001_ha, 0,
3779 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3780 port_id, phy_id, 0, 0);
3781 sas_phy_disconnected(sas_phy);
3782 phy->phy_attached = 0;
3783 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3786 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3787 pm8001_dbg(pm8001_ha, MSG,
3788 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n");
3789 pm8001_hw_event_ack_req(pm8001_ha, 0,
3790 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3791 port_id, phy_id, 0, 0);
3792 sas_phy_disconnected(sas_phy);
3793 phy->phy_attached = 0;
3794 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3797 case HW_EVENT_MALFUNCTION:
3798 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n");
3800 case HW_EVENT_BROADCAST_SES:
3801 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n");
3802 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3803 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3804 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3805 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3808 case HW_EVENT_INBOUND_CRC_ERROR:
3809 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n");
3810 pm8001_hw_event_ack_req(pm8001_ha, 0,
3811 HW_EVENT_INBOUND_CRC_ERROR,
3812 port_id, phy_id, 0, 0);
3814 case HW_EVENT_HARD_RESET_RECEIVED:
3815 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n");
3816 sas_notify_port_event(sas_phy, PORTE_HARD_RESET, GFP_ATOMIC);
3818 case HW_EVENT_ID_FRAME_TIMEOUT:
3819 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n");
3820 sas_phy_disconnected(sas_phy);
3821 phy->phy_attached = 0;
3822 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3825 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3826 pm8001_dbg(pm8001_ha, MSG,
3827 "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n");
3828 pm8001_hw_event_ack_req(pm8001_ha, 0,
3829 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3830 port_id, phy_id, 0, 0);
3831 sas_phy_disconnected(sas_phy);
3832 phy->phy_attached = 0;
3833 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3836 case HW_EVENT_PORT_RESET_TIMER_TMO:
3837 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n");
3838 sas_phy_disconnected(sas_phy);
3839 phy->phy_attached = 0;
3840 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3843 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3844 pm8001_dbg(pm8001_ha, MSG,
3845 "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n");
3846 sas_phy_disconnected(sas_phy);
3847 phy->phy_attached = 0;
3848 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3851 case HW_EVENT_PORT_RECOVER:
3852 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n");
3854 case HW_EVENT_PORT_RESET_COMPLETE:
3855 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n");
3857 case EVENT_BROADCAST_ASYNCH_EVENT:
3858 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n");
3861 pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type = %x\n",
3869 * process_one_iomb - process one outbound Queue memory block
3870 * @pm8001_ha: our hba card information
3871 * @piomb: IO message buffer
3873 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3875 __le32 pHeader = *(__le32 *)piomb;
3876 u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
3878 pm8001_dbg(pm8001_ha, MSG, "process_one_iomb:\n");
3882 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n");
3884 case OPC_OUB_HW_EVENT:
3885 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n");
3886 mpi_hw_event(pm8001_ha, piomb);
3888 case OPC_OUB_SSP_COMP:
3889 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n");
3890 mpi_ssp_completion(pm8001_ha, piomb);
3892 case OPC_OUB_SMP_COMP:
3893 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n");
3894 mpi_smp_completion(pm8001_ha, piomb);
3896 case OPC_OUB_LOCAL_PHY_CNTRL:
3897 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n");
3898 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3900 case OPC_OUB_DEV_REGIST:
3901 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n");
3902 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3904 case OPC_OUB_DEREG_DEV:
3905 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n");
3906 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3908 case OPC_OUB_GET_DEV_HANDLE:
3909 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n");
3911 case OPC_OUB_SATA_COMP:
3912 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n");
3913 mpi_sata_completion(pm8001_ha, piomb);
3915 case OPC_OUB_SATA_EVENT:
3916 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n");
3917 mpi_sata_event(pm8001_ha, piomb);
3919 case OPC_OUB_SSP_EVENT:
3920 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n");
3921 mpi_ssp_event(pm8001_ha, piomb);
3923 case OPC_OUB_DEV_HANDLE_ARRIV:
3924 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n");
3925 /*This is for target*/
3927 case OPC_OUB_SSP_RECV_EVENT:
3928 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n");
3929 /*This is for target*/
3931 case OPC_OUB_DEV_INFO:
3932 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_INFO\n");
3934 case OPC_OUB_FW_FLASH_UPDATE:
3935 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n");
3936 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3938 case OPC_OUB_GPIO_RESPONSE:
3939 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n");
3941 case OPC_OUB_GPIO_EVENT:
3942 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n");
3944 case OPC_OUB_GENERAL_EVENT:
3945 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n");
3946 pm8001_mpi_general_event(pm8001_ha, piomb);
3948 case OPC_OUB_SSP_ABORT_RSP:
3949 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n");
3950 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3952 case OPC_OUB_SATA_ABORT_RSP:
3953 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n");
3954 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3956 case OPC_OUB_SAS_DIAG_MODE_START_END:
3957 pm8001_dbg(pm8001_ha, MSG,
3958 "OPC_OUB_SAS_DIAG_MODE_START_END\n");
3960 case OPC_OUB_SAS_DIAG_EXECUTE:
3961 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n");
3963 case OPC_OUB_GET_TIME_STAMP:
3964 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n");
3966 case OPC_OUB_SAS_HW_EVENT_ACK:
3967 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n");
3969 case OPC_OUB_PORT_CONTROL:
3970 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n");
3972 case OPC_OUB_SMP_ABORT_RSP:
3973 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n");
3974 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3976 case OPC_OUB_GET_NVMD_DATA:
3977 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n");
3978 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3980 case OPC_OUB_SET_NVMD_DATA:
3981 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n");
3982 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3984 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3985 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n");
3987 case OPC_OUB_SET_DEVICE_STATE:
3988 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n");
3989 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3991 case OPC_OUB_GET_DEVICE_STATE:
3992 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n");
3994 case OPC_OUB_SET_DEV_INFO:
3995 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n");
3997 case OPC_OUB_SAS_RE_INITIALIZE:
3998 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_RE_INITIALIZE\n");
4001 pm8001_dbg(pm8001_ha, DEVIO,
4002 "Unknown outbound Queue IOMB OPC = %x\n",
4008 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4010 struct outbound_queue_table *circularQ;
4013 u32 ret = MPI_IO_STATUS_FAIL;
4014 unsigned long flags;
4016 spin_lock_irqsave(&pm8001_ha->lock, flags);
4017 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4019 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4020 if (MPI_IO_STATUS_SUCCESS == ret) {
4021 /* process the outbound message */
4022 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
4023 /* free the message from the outbound circular buffer */
4024 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4027 if (MPI_IO_STATUS_BUSY == ret) {
4028 /* Update the producer index from SPC */
4029 circularQ->producer_index =
4030 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4031 if (le32_to_cpu(circularQ->producer_index) ==
4032 circularQ->consumer_idx)
4037 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4041 /* DMA_... to our direction translation. */
4042 static const u8 data_dir_flags[] = {
4043 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
4044 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */
4045 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */
4046 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */
4049 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
4052 struct scatterlist *sg;
4053 struct pm8001_prd *buf_prd = prd;
4055 for_each_sg(scatter, sg, nr, i) {
4056 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
4057 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
4058 buf_prd->im_len.e = 0;
4063 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
4065 psmp_cmd->tag = hTag;
4066 psmp_cmd->device_id = cpu_to_le32(deviceID);
4067 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4071 * pm8001_chip_smp_req - send a SMP task to FW
4072 * @pm8001_ha: our hba card information.
4073 * @ccb: the ccb information this request used.
4075 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4076 struct pm8001_ccb_info *ccb)
4079 struct sas_task *task = ccb->task;
4080 struct domain_device *dev = task->dev;
4081 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4082 struct scatterlist *sg_req, *sg_resp;
4083 u32 req_len, resp_len;
4084 struct smp_req smp_cmd;
4087 memset(&smp_cmd, 0, sizeof(smp_cmd));
4089 * DMA-map SMP request, response buffers
4091 sg_req = &task->smp_task.smp_req;
4092 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4095 req_len = sg_dma_len(sg_req);
4097 sg_resp = &task->smp_task.smp_resp;
4098 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4103 resp_len = sg_dma_len(sg_resp);
4104 /* must be in dwords */
4105 if ((req_len & 0x3) || (resp_len & 0x3)) {
4110 opc = OPC_INB_SMP_REQUEST;
4111 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4112 smp_cmd.long_smp_req.long_req_addr =
4113 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4114 smp_cmd.long_smp_req.long_req_size =
4115 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4116 smp_cmd.long_smp_req.long_resp_addr =
4117 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
4118 smp_cmd.long_smp_req.long_resp_size =
4119 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4120 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
4121 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc,
4122 &smp_cmd, sizeof(smp_cmd), 0);
4129 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4132 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4138 * pm8001_chip_ssp_io_req - send a SSP task to FW
4139 * @pm8001_ha: our hba card information.
4140 * @ccb: the ccb information this request used.
4142 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4143 struct pm8001_ccb_info *ccb)
4145 struct sas_task *task = ccb->task;
4146 struct domain_device *dev = task->dev;
4147 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4148 struct ssp_ini_io_start_req ssp_cmd;
4149 u32 tag = ccb->ccb_tag;
4151 u32 opc = OPC_INB_SSPINIIOSTART;
4152 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4153 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4155 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
4156 SAS 1.1 compatible TLR*/
4157 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4158 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4159 ssp_cmd.tag = cpu_to_le32(tag);
4160 if (task->ssp_task.enable_first_burst)
4161 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4162 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4163 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4164 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4165 task->ssp_task.cmd->cmd_len);
4167 /* fill in PRD (scatter/gather) table, if any */
4168 if (task->num_scatter > 1) {
4169 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4170 phys_addr = ccb->ccb_dma_handle;
4171 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
4172 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
4173 ssp_cmd.esgl = cpu_to_le32(1<<31);
4174 } else if (task->num_scatter == 1) {
4175 u64 dma_addr = sg_dma_address(task->scatter);
4176 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4177 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
4178 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4180 } else if (task->num_scatter == 0) {
4181 ssp_cmd.addr_low = 0;
4182 ssp_cmd.addr_high = 0;
4183 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4187 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &ssp_cmd,
4188 sizeof(ssp_cmd), 0);
4191 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4192 struct pm8001_ccb_info *ccb)
4194 struct sas_task *task = ccb->task;
4195 struct domain_device *dev = task->dev;
4196 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4197 u32 tag = ccb->ccb_tag;
4198 struct sata_start_req sata_cmd;
4199 u32 hdr_tag, ncg_tag = 0;
4203 unsigned long flags;
4204 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4206 memset(&sata_cmd, 0, sizeof(sata_cmd));
4208 if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) {
4209 ATAP = 0x04; /* no data*/
4210 pm8001_dbg(pm8001_ha, IO, "no data\n");
4211 } else if (likely(!task->ata_task.device_control_reg_update)) {
4212 if (task->ata_task.use_ncq &&
4213 dev->sata_dev.class != ATA_DEV_ATAPI) {
4214 ATAP = 0x07; /* FPDMA */
4215 pm8001_dbg(pm8001_ha, IO, "FPDMA\n");
4216 } else if (task->ata_task.dma_xfer) {
4217 ATAP = 0x06; /* DMA */
4218 pm8001_dbg(pm8001_ha, IO, "DMA\n");
4220 ATAP = 0x05; /* PIO*/
4221 pm8001_dbg(pm8001_ha, IO, "PIO\n");
4224 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4225 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4228 dir = data_dir_flags[task->data_dir] << 8;
4229 sata_cmd.tag = cpu_to_le32(tag);
4230 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4231 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4232 sata_cmd.ncqtag_atap_dir_m =
4233 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
4234 sata_cmd.sata_fis = task->ata_task.fis;
4235 if (likely(!task->ata_task.device_control_reg_update))
4236 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4237 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4238 /* fill in PRD (scatter/gather) table, if any */
4239 if (task->num_scatter > 1) {
4240 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4241 phys_addr = ccb->ccb_dma_handle;
4242 sata_cmd.addr_low = lower_32_bits(phys_addr);
4243 sata_cmd.addr_high = upper_32_bits(phys_addr);
4244 sata_cmd.esgl = cpu_to_le32(1 << 31);
4245 } else if (task->num_scatter == 1) {
4246 u64 dma_addr = sg_dma_address(task->scatter);
4247 sata_cmd.addr_low = lower_32_bits(dma_addr);
4248 sata_cmd.addr_high = upper_32_bits(dma_addr);
4249 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4251 } else if (task->num_scatter == 0) {
4252 sata_cmd.addr_low = 0;
4253 sata_cmd.addr_high = 0;
4254 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4258 /* Check for read log for failed drive and return */
4259 if (sata_cmd.sata_fis.command == 0x2f) {
4260 if (((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4261 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4262 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4263 struct task_status_struct *ts;
4265 pm8001_ha_dev->id &= 0xDFFFFFFF;
4266 ts = &task->task_status;
4268 spin_lock_irqsave(&task->task_state_lock, flags);
4269 ts->resp = SAS_TASK_COMPLETE;
4270 ts->stat = SAS_SAM_STAT_GOOD;
4271 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4272 task->task_state_flags |= SAS_TASK_STATE_DONE;
4273 if (unlikely((task->task_state_flags &
4274 SAS_TASK_STATE_ABORTED))) {
4275 spin_unlock_irqrestore(&task->task_state_lock,
4277 pm8001_dbg(pm8001_ha, FAIL,
4278 "task 0x%p resp 0x%x stat 0x%x but aborted by upper layer\n",
4281 pm8001_ccb_task_free(pm8001_ha, ccb);
4283 spin_unlock_irqrestore(&task->task_state_lock,
4285 pm8001_ccb_task_free_done(pm8001_ha, ccb);
4291 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &sata_cmd,
4292 sizeof(sata_cmd), 0);
4296 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4297 * @pm8001_ha: our hba card information.
4298 * @phy_id: the phy id which we wanted to start up.
4301 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4303 struct phy_start_req payload;
4305 u32 opcode = OPC_INB_PHYSTART;
4307 memset(&payload, 0, sizeof(payload));
4308 payload.tag = cpu_to_le32(tag);
4310 ** [0:7] PHY Identifier
4311 ** [8:11] link rate 1.5G, 3G, 6G
4312 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4313 ** [14] 0b disable spin up hold; 1b enable spin up hold
4315 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4316 LINKMODE_AUTO | LINKRATE_15 |
4317 LINKRATE_30 | LINKRATE_60 | phy_id);
4318 payload.sas_identify.dev_type = SAS_END_DEVICE;
4319 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4320 memcpy(payload.sas_identify.sas_addr,
4321 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4322 payload.sas_identify.phy_id = phy_id;
4324 return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload,
4325 sizeof(payload), 0);
4329 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4330 * @pm8001_ha: our hba card information.
4331 * @phy_id: the phy id which we wanted to start up.
4333 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4336 struct phy_stop_req payload;
4338 u32 opcode = OPC_INB_PHYSTOP;
4340 memset(&payload, 0, sizeof(payload));
4341 payload.tag = cpu_to_le32(tag);
4342 payload.phy_id = cpu_to_le32(phy_id);
4344 return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload,
4345 sizeof(payload), 0);
4349 * see comments on pm8001_mpi_reg_resp.
4351 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4352 struct pm8001_device *pm8001_dev, u32 flag)
4354 struct reg_dev_req payload;
4356 u32 stp_sspsmp_sata = 0x4;
4357 u32 linkrate, phy_id;
4359 struct pm8001_ccb_info *ccb;
4361 u16 firstBurstSize = 0;
4363 struct domain_device *dev = pm8001_dev->sas_device;
4364 struct domain_device *parent_dev = dev->parent;
4365 struct pm8001_port *port = dev->port->lldd_port;
4367 memset(&payload, 0, sizeof(payload));
4368 ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_dev, NULL);
4370 return -SAS_QUEUE_FULL;
4372 payload.tag = cpu_to_le32(ccb->ccb_tag);
4374 stp_sspsmp_sata = 0x02; /*direct attached sata */
4376 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4377 stp_sspsmp_sata = 0x00; /* stp*/
4378 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4379 dev_is_expander(pm8001_dev->dev_type))
4380 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4382 if (parent_dev && dev_is_expander(parent_dev->dev_type))
4383 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4385 phy_id = pm8001_dev->attached_phy;
4386 opc = OPC_INB_REG_DEV;
4387 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4388 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4389 payload.phyid_portid =
4390 cpu_to_le32(((port->port_id) & 0x0F) |
4391 ((phy_id & 0x0F) << 4));
4392 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4393 ((linkrate & 0x0F) * 0x1000000) |
4394 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4395 payload.firstburstsize_ITNexustimeout =
4396 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4397 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4400 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4401 sizeof(payload), 0);
4403 pm8001_ccb_free(pm8001_ha, ccb);
4409 * see comments on pm8001_mpi_reg_resp.
4411 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4414 struct dereg_dev_req payload;
4415 u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4417 memset(&payload, 0, sizeof(payload));
4418 payload.tag = cpu_to_le32(1);
4419 payload.device_id = cpu_to_le32(device_id);
4420 pm8001_dbg(pm8001_ha, MSG, "unregister device device_id = %d\n",
4423 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4424 sizeof(payload), 0);
4428 * pm8001_chip_phy_ctl_req - support the local phy operation
4429 * @pm8001_ha: our hba card information.
4430 * @phyId: the phy id which we wanted to operate
4431 * @phy_op: the phy operation to request
4433 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4434 u32 phyId, u32 phy_op)
4436 struct local_phy_ctl_req payload;
4437 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4439 memset(&payload, 0, sizeof(payload));
4440 payload.tag = cpu_to_le32(1);
4441 payload.phyop_phyid =
4442 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4444 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4445 sizeof(payload), 0);
4448 static u32 pm8001_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4450 #ifdef PM8001_USE_MSIX
4455 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4463 * pm8001_chip_isr - PM8001 isr handler.
4464 * @pm8001_ha: our hba card information.
4468 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4470 pm8001_chip_interrupt_disable(pm8001_ha, vec);
4471 pm8001_dbg(pm8001_ha, DEVIO,
4472 "irq vec %d, ODMR:0x%x\n",
4473 vec, pm8001_cr32(pm8001_ha, 0, 0x30));
4474 process_oq(pm8001_ha, vec);
4475 pm8001_chip_interrupt_enable(pm8001_ha, vec);
4479 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4480 u32 dev_id, enum sas_internal_abort type, u32 task_tag, u32 cmd_tag)
4482 struct task_abort_req task_abort;
4484 memset(&task_abort, 0, sizeof(task_abort));
4485 if (type == SAS_INTERNAL_ABORT_SINGLE) {
4486 task_abort.abort_all = 0;
4487 task_abort.device_id = cpu_to_le32(dev_id);
4488 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4489 } else if (type == SAS_INTERNAL_ABORT_DEV) {
4490 task_abort.abort_all = cpu_to_le32(1);
4491 task_abort.device_id = cpu_to_le32(dev_id);
4493 pm8001_dbg(pm8001_ha, EH, "unknown type (%d)\n", type);
4497 task_abort.tag = cpu_to_le32(cmd_tag);
4499 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &task_abort,
4500 sizeof(task_abort), 0);
4504 * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4506 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4507 struct pm8001_ccb_info *ccb)
4509 struct sas_task *task = ccb->task;
4510 struct sas_internal_abort_task *abort = &task->abort_task;
4511 struct pm8001_device *pm8001_dev = ccb->device;
4512 int rc = TMF_RESP_FUNC_FAILED;
4515 pm8001_dbg(pm8001_ha, EH, "cmd_tag = %x, abort task tag = 0x%x\n",
4516 ccb->ccb_tag, abort->tag);
4517 if (pm8001_dev->dev_type == SAS_END_DEVICE)
4518 opc = OPC_INB_SSP_ABORT;
4519 else if (pm8001_dev->dev_type == SAS_SATA_DEV)
4520 opc = OPC_INB_SATA_ABORT;
4522 opc = OPC_INB_SMP_ABORT;/* SMP */
4523 device_id = pm8001_dev->device_id;
4524 rc = send_task_abort(pm8001_ha, opc, device_id, abort->type,
4525 abort->tag, ccb->ccb_tag);
4526 if (rc != TMF_RESP_FUNC_COMPLETE)
4527 pm8001_dbg(pm8001_ha, EH, "rc= %d\n", rc);
4532 * pm8001_chip_ssp_tm_req - built the task management command.
4533 * @pm8001_ha: our hba card information.
4534 * @ccb: the ccb information.
4535 * @tmf: task management function.
4537 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4538 struct pm8001_ccb_info *ccb, struct sas_tmf_task *tmf)
4540 struct sas_task *task = ccb->task;
4541 struct domain_device *dev = task->dev;
4542 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4543 u32 opc = OPC_INB_SSPINITMSTART;
4544 struct ssp_ini_tm_start_req sspTMCmd;
4546 memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4547 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4548 sspTMCmd.relate_tag = cpu_to_le32((u32)tmf->tag_of_task_to_be_managed);
4549 sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4550 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4551 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4552 if (pm8001_ha->chip_id != chip_8001)
4553 sspTMCmd.ds_ads_m = cpu_to_le32(0x08);
4555 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &sspTMCmd,
4556 sizeof(sspTMCmd), 0);
4559 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4562 u32 opc = OPC_INB_GET_NVMD_DATA;
4565 struct pm8001_ccb_info *ccb;
4566 struct get_nvm_data_req nvmd_req;
4567 struct fw_control_ex *fw_control_context;
4568 struct pm8001_ioctl_payload *ioctl_payload = payload;
4570 nvmd_type = ioctl_payload->minor_function;
4571 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4572 if (!fw_control_context)
4574 fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific;
4575 fw_control_context->len = ioctl_payload->rd_length;
4576 memset(&nvmd_req, 0, sizeof(nvmd_req));
4578 ccb = pm8001_ccb_alloc(pm8001_ha, NULL, NULL);
4580 kfree(fw_control_context);
4581 return -SAS_QUEUE_FULL;
4583 ccb->fw_control_context = fw_control_context;
4585 nvmd_req.tag = cpu_to_le32(ccb->ccb_tag);
4587 switch (nvmd_type) {
4589 u32 twi_addr, twi_page_size;
4593 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4594 twi_page_size << 8 | TWI_DEVICE);
4595 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4596 nvmd_req.resp_addr_hi =
4597 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4598 nvmd_req.resp_addr_lo =
4599 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4603 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4604 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4605 nvmd_req.resp_addr_hi =
4606 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4607 nvmd_req.resp_addr_lo =
4608 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4612 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4613 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4614 nvmd_req.resp_addr_hi =
4615 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4616 nvmd_req.resp_addr_lo =
4617 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4621 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4622 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4623 nvmd_req.resp_addr_hi =
4624 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4625 nvmd_req.resp_addr_lo =
4626 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4630 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP);
4631 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4632 nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset);
4633 nvmd_req.resp_addr_hi =
4634 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4635 nvmd_req.resp_addr_lo =
4636 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4643 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &nvmd_req,
4644 sizeof(nvmd_req), 0);
4646 kfree(fw_control_context);
4647 pm8001_ccb_free(pm8001_ha, ccb);
4652 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4655 u32 opc = OPC_INB_SET_NVMD_DATA;
4658 struct pm8001_ccb_info *ccb;
4659 struct set_nvm_data_req nvmd_req;
4660 struct fw_control_ex *fw_control_context;
4661 struct pm8001_ioctl_payload *ioctl_payload = payload;
4663 nvmd_type = ioctl_payload->minor_function;
4664 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4665 if (!fw_control_context)
4668 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4669 &ioctl_payload->func_specific,
4670 ioctl_payload->wr_length);
4671 memset(&nvmd_req, 0, sizeof(nvmd_req));
4673 ccb = pm8001_ccb_alloc(pm8001_ha, NULL, NULL);
4675 kfree(fw_control_context);
4676 return -SAS_QUEUE_FULL;
4678 ccb->fw_control_context = fw_control_context;
4680 nvmd_req.tag = cpu_to_le32(ccb->ccb_tag);
4681 switch (nvmd_type) {
4683 u32 twi_addr, twi_page_size;
4686 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4687 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4688 twi_page_size << 8 | TWI_DEVICE);
4689 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4690 nvmd_req.resp_addr_hi =
4691 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4692 nvmd_req.resp_addr_lo =
4693 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4697 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4698 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4699 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4700 nvmd_req.resp_addr_hi =
4701 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4702 nvmd_req.resp_addr_lo =
4703 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4706 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4707 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4708 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4709 nvmd_req.resp_addr_hi =
4710 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4711 nvmd_req.resp_addr_lo =
4712 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4715 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4716 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4717 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4718 nvmd_req.resp_addr_hi =
4719 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4720 nvmd_req.resp_addr_lo =
4721 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4727 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &nvmd_req,
4728 sizeof(nvmd_req), 0);
4730 kfree(fw_control_context);
4731 pm8001_ccb_free(pm8001_ha, ccb);
4737 * pm8001_chip_fw_flash_update_build - support the firmware update operation
4738 * @pm8001_ha: our hba card information.
4739 * @fw_flash_updata_info: firmware flash update param
4740 * @tag: Tag to apply to the payload
4743 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4744 void *fw_flash_updata_info, u32 tag)
4746 struct fw_flash_Update_req payload;
4747 struct fw_flash_updata_info *info;
4748 u32 opc = OPC_INB_FW_FLASH_UPDATE;
4750 memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4751 info = fw_flash_updata_info;
4752 payload.tag = cpu_to_le32(tag);
4753 payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4754 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4755 payload.total_image_len = cpu_to_le32(info->total_image_len);
4756 payload.len = info->sgl.im_len.len ;
4757 payload.sgl_addr_lo =
4758 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
4759 payload.sgl_addr_hi =
4760 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
4762 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4763 sizeof(payload), 0);
4767 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4770 struct fw_flash_updata_info flash_update_info;
4771 struct fw_control_info *fw_control;
4772 struct fw_control_ex *fw_control_context;
4774 struct pm8001_ccb_info *ccb;
4775 void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr;
4776 dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr;
4777 struct pm8001_ioctl_payload *ioctl_payload = payload;
4779 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4780 if (!fw_control_context)
4782 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific;
4783 pm8001_dbg(pm8001_ha, DEVIO,
4784 "dma fw_control context input length :%x\n",
4786 memcpy(buffer, fw_control->buffer, fw_control->len);
4787 flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4788 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4789 flash_update_info.sgl.im_len.e = 0;
4790 flash_update_info.cur_image_offset = fw_control->offset;
4791 flash_update_info.cur_image_len = fw_control->len;
4792 flash_update_info.total_image_len = fw_control->size;
4793 fw_control_context->fw_control = fw_control;
4794 fw_control_context->virtAddr = buffer;
4795 fw_control_context->phys_addr = phys_addr;
4796 fw_control_context->len = fw_control->len;
4798 ccb = pm8001_ccb_alloc(pm8001_ha, NULL, NULL);
4800 kfree(fw_control_context);
4801 return -SAS_QUEUE_FULL;
4803 ccb->fw_control_context = fw_control_context;
4805 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4808 kfree(fw_control_context);
4809 pm8001_ccb_free(pm8001_ha, ccb);
4816 pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf)
4818 u32 value, rem, offset = 0, bar = 0;
4819 u32 index, work_offset, dw_length;
4820 u32 shift_value, gsm_base, gsm_dump_offset;
4822 struct Scsi_Host *shost = class_to_shost(cdev);
4823 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
4824 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
4827 gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset;
4829 /* check max is 1 Mbytes */
4830 if ((length > 0x100000) || (gsm_dump_offset & 3) ||
4831 ((gsm_dump_offset + length) > 0x1000000))
4834 if (pm8001_ha->chip_id == chip_8001)
4839 work_offset = gsm_dump_offset & 0xFFFF0000;
4840 offset = gsm_dump_offset & 0x0000FFFF;
4841 gsm_dump_offset = work_offset;
4842 /* adjust length to dword boundary */
4844 dw_length = length >> 2;
4846 for (index = 0; index < dw_length; index++) {
4847 if ((work_offset + offset) & 0xFFFF0000) {
4848 if (pm8001_ha->chip_id == chip_8001)
4849 shift_value = ((gsm_dump_offset + offset) &
4850 SHIFT_REG_64K_MASK);
4852 shift_value = (((gsm_dump_offset + offset) &
4853 SHIFT_REG_64K_MASK) >>
4854 SHIFT_REG_BIT_SHIFT);
4856 if (pm8001_ha->chip_id == chip_8001) {
4857 gsm_base = GSM_BASE;
4858 if (-1 == pm8001_bar4_shift(pm8001_ha,
4859 (gsm_base + shift_value)))
4863 if (-1 == pm80xx_bar4_shift(pm8001_ha,
4864 (gsm_base + shift_value)))
4867 gsm_dump_offset = (gsm_dump_offset + offset) &
4870 offset = offset & 0x0000FFFF;
4872 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
4874 direct_data += sprintf(direct_data, "%08x ", value);
4878 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
4880 /* xfr for non_dw */
4881 direct_data += sprintf(direct_data, "%08x ", value);
4883 /* Shift back to BAR4 original address */
4884 if (-1 == pm8001_bar4_shift(pm8001_ha, 0))
4886 pm8001_ha->fatal_forensic_shift_offset += 1024;
4888 if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000)
4889 pm8001_ha->fatal_forensic_shift_offset = 0;
4890 return direct_data - buf;
4894 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4895 struct pm8001_device *pm8001_dev, u32 state)
4897 struct set_dev_state_req payload;
4898 struct pm8001_ccb_info *ccb;
4900 u32 opc = OPC_INB_SET_DEVICE_STATE;
4902 memset(&payload, 0, sizeof(payload));
4904 ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_dev, NULL);
4906 return -SAS_QUEUE_FULL;
4908 payload.tag = cpu_to_le32(ccb->ccb_tag);
4909 payload.device_id = cpu_to_le32(pm8001_dev->device_id);
4910 payload.nds = cpu_to_le32(state);
4912 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4913 sizeof(payload), 0);
4915 pm8001_ccb_free(pm8001_ha, ccb);
4921 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
4923 struct sas_re_initialization_req payload;
4924 struct pm8001_ccb_info *ccb;
4926 u32 opc = OPC_INB_SAS_RE_INITIALIZE;
4928 memset(&payload, 0, sizeof(payload));
4930 ccb = pm8001_ccb_alloc(pm8001_ha, NULL, NULL);
4932 return -SAS_QUEUE_FULL;
4934 payload.tag = cpu_to_le32(ccb->ccb_tag);
4935 payload.SSAHOLT = cpu_to_le32(0xd << 25);
4936 payload.sata_hol_tmo = cpu_to_le32(80);
4937 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
4939 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4940 sizeof(payload), 0);
4942 pm8001_ccb_free(pm8001_ha, ccb);
4947 const struct pm8001_dispatch pm8001_8001_dispatch = {
4949 .chip_init = pm8001_chip_init,
4950 .chip_soft_rst = pm8001_chip_soft_rst,
4951 .chip_rst = pm8001_hw_chip_rst,
4952 .chip_iounmap = pm8001_chip_iounmap,
4953 .isr = pm8001_chip_isr,
4954 .is_our_interrupt = pm8001_chip_is_our_interrupt,
4955 .isr_process_oq = process_oq,
4956 .interrupt_enable = pm8001_chip_interrupt_enable,
4957 .interrupt_disable = pm8001_chip_interrupt_disable,
4958 .make_prd = pm8001_chip_make_sg,
4959 .smp_req = pm8001_chip_smp_req,
4960 .ssp_io_req = pm8001_chip_ssp_io_req,
4961 .sata_req = pm8001_chip_sata_req,
4962 .phy_start_req = pm8001_chip_phy_start_req,
4963 .phy_stop_req = pm8001_chip_phy_stop_req,
4964 .reg_dev_req = pm8001_chip_reg_dev_req,
4965 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4966 .phy_ctl_req = pm8001_chip_phy_ctl_req,
4967 .task_abort = pm8001_chip_abort_task,
4968 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4969 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4970 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4971 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4972 .set_dev_state_req = pm8001_chip_set_dev_state_req,
4973 .sas_re_init_req = pm8001_chip_sas_re_initialization,
4974 .fatal_errors = pm80xx_fatal_errors,