2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 USI Co., Ltd.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
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33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm8001_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45 #include "pm80xx_tracepoints.h"
48 * read_main_config_table - read the configure table and save it.
49 * @pm8001_ha: our hba card information
51 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
53 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
54 pm8001_ha->main_cfg_tbl.pm8001_tbl.signature =
55 pm8001_mr32(address, 0x00);
56 pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
57 pm8001_mr32(address, 0x04);
58 pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev =
59 pm8001_mr32(address, 0x08);
60 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io =
61 pm8001_mr32(address, 0x0C);
62 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl =
63 pm8001_mr32(address, 0x10);
64 pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
65 pm8001_mr32(address, 0x14);
66 pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset =
67 pm8001_mr32(address, 0x18);
68 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
69 pm8001_mr32(address, MAIN_IBQ_OFFSET);
70 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
71 pm8001_mr32(address, MAIN_OBQ_OFFSET);
72 pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag =
73 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
75 /* read analog Setting offset from the configuration table */
76 pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
77 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
79 /* read Error Dump Offset and Length */
80 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
81 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
82 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
83 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
84 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
85 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
86 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
87 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
91 * read_general_status_table - read the general status table and save it.
92 * @pm8001_ha: our hba card information
94 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
96 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
97 pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate =
98 pm8001_mr32(address, 0x00);
99 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0 =
100 pm8001_mr32(address, 0x04);
101 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1 =
102 pm8001_mr32(address, 0x08);
103 pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt =
104 pm8001_mr32(address, 0x0C);
105 pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt =
106 pm8001_mr32(address, 0x10);
107 pm8001_ha->gs_tbl.pm8001_tbl.rsvd =
108 pm8001_mr32(address, 0x14);
109 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0] =
110 pm8001_mr32(address, 0x18);
111 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1] =
112 pm8001_mr32(address, 0x1C);
113 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2] =
114 pm8001_mr32(address, 0x20);
115 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3] =
116 pm8001_mr32(address, 0x24);
117 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4] =
118 pm8001_mr32(address, 0x28);
119 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5] =
120 pm8001_mr32(address, 0x2C);
121 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6] =
122 pm8001_mr32(address, 0x30);
123 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7] =
124 pm8001_mr32(address, 0x34);
125 pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val =
126 pm8001_mr32(address, 0x38);
127 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0] =
128 pm8001_mr32(address, 0x3C);
129 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1] =
130 pm8001_mr32(address, 0x40);
131 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0] =
132 pm8001_mr32(address, 0x44);
133 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1] =
134 pm8001_mr32(address, 0x48);
135 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2] =
136 pm8001_mr32(address, 0x4C);
137 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3] =
138 pm8001_mr32(address, 0x50);
139 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4] =
140 pm8001_mr32(address, 0x54);
141 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5] =
142 pm8001_mr32(address, 0x58);
143 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6] =
144 pm8001_mr32(address, 0x5C);
145 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7] =
146 pm8001_mr32(address, 0x60);
150 * read_inbnd_queue_table - read the inbound queue table and save it.
151 * @pm8001_ha: our hba card information
153 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
156 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
157 for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
158 u32 offset = i * 0x20;
159 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
160 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
161 pm8001_ha->inbnd_q_tbl[i].pi_offset =
162 pm8001_mr32(address, (offset + 0x18));
167 * read_outbnd_queue_table - read the outbound queue table and save it.
168 * @pm8001_ha: our hba card information
170 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
173 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
174 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
175 u32 offset = i * 0x24;
176 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
177 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
178 pm8001_ha->outbnd_q_tbl[i].ci_offset =
179 pm8001_mr32(address, (offset + 0x18));
184 * init_default_table_values - init the default table.
185 * @pm8001_ha: our hba card information
187 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
190 u32 offsetib, offsetob;
191 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
192 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
193 u32 ib_offset = pm8001_ha->ib_offset;
194 u32 ob_offset = pm8001_ha->ob_offset;
195 u32 ci_offset = pm8001_ha->ci_offset;
196 u32 pi_offset = pm8001_ha->pi_offset;
198 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd = 0;
199 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3 = 0;
200 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7 = 0;
201 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3 = 0;
202 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7 = 0;
203 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
205 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
207 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
208 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
209 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
210 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
212 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr =
213 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
214 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr =
215 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
216 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size =
217 PM8001_EVENT_LOG_SIZE;
218 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option = 0x01;
219 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr =
220 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
221 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr =
222 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
223 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size =
224 PM8001_EVENT_LOG_SIZE;
225 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option = 0x01;
226 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt = 0x01;
227 for (i = 0; i < pm8001_ha->max_q_num; i++) {
228 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
229 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
230 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
231 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
232 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
233 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
234 pm8001_ha->inbnd_q_tbl[i].base_virt =
235 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
236 pm8001_ha->inbnd_q_tbl[i].total_length =
237 pm8001_ha->memoryMap.region[ib_offset + i].total_len;
238 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
239 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
240 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
241 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
242 pm8001_ha->inbnd_q_tbl[i].ci_virt =
243 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
244 pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0);
246 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
247 get_pci_bar_index(pm8001_mr32(addressib,
249 pm8001_ha->inbnd_q_tbl[i].pi_offset =
250 pm8001_mr32(addressib, (offsetib + 0x18));
251 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
252 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
254 for (i = 0; i < pm8001_ha->max_q_num; i++) {
255 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
256 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
257 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
258 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
259 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
260 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
261 pm8001_ha->outbnd_q_tbl[i].base_virt =
262 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
263 pm8001_ha->outbnd_q_tbl[i].total_length =
264 pm8001_ha->memoryMap.region[ob_offset + i].total_len;
265 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
266 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
267 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
268 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
269 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay =
270 0 | (10 << 16) | (i << 24);
271 pm8001_ha->outbnd_q_tbl[i].pi_virt =
272 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
273 pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0);
275 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
276 get_pci_bar_index(pm8001_mr32(addressob,
278 pm8001_ha->outbnd_q_tbl[i].ci_offset =
279 pm8001_mr32(addressob, (offsetob + 0x18));
280 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
281 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
286 * update_main_config_table - update the main default table to the HBA.
287 * @pm8001_ha: our hba card information
289 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
291 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
292 pm8001_mw32(address, 0x24,
293 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
294 pm8001_mw32(address, 0x28,
295 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
296 pm8001_mw32(address, 0x2C,
297 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
298 pm8001_mw32(address, 0x30,
299 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
300 pm8001_mw32(address, 0x34,
301 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
302 pm8001_mw32(address, 0x38,
303 pm8001_ha->main_cfg_tbl.pm8001_tbl.
304 outbound_tgt_ITNexus_event_pid0_3);
305 pm8001_mw32(address, 0x3C,
306 pm8001_ha->main_cfg_tbl.pm8001_tbl.
307 outbound_tgt_ITNexus_event_pid4_7);
308 pm8001_mw32(address, 0x40,
309 pm8001_ha->main_cfg_tbl.pm8001_tbl.
310 outbound_tgt_ssp_event_pid0_3);
311 pm8001_mw32(address, 0x44,
312 pm8001_ha->main_cfg_tbl.pm8001_tbl.
313 outbound_tgt_ssp_event_pid4_7);
314 pm8001_mw32(address, 0x48,
315 pm8001_ha->main_cfg_tbl.pm8001_tbl.
316 outbound_tgt_smp_event_pid0_3);
317 pm8001_mw32(address, 0x4C,
318 pm8001_ha->main_cfg_tbl.pm8001_tbl.
319 outbound_tgt_smp_event_pid4_7);
320 pm8001_mw32(address, 0x50,
321 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
322 pm8001_mw32(address, 0x54,
323 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
324 pm8001_mw32(address, 0x58,
325 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
326 pm8001_mw32(address, 0x5C,
327 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
328 pm8001_mw32(address, 0x60,
329 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
330 pm8001_mw32(address, 0x64,
331 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
332 pm8001_mw32(address, 0x68,
333 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
334 pm8001_mw32(address, 0x6C,
335 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
336 pm8001_mw32(address, 0x70,
337 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
341 * update_inbnd_queue_table - update the inbound queue table to the HBA.
342 * @pm8001_ha: our hba card information
343 * @number: entry in the queue
345 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
348 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
349 u16 offset = number * 0x20;
350 pm8001_mw32(address, offset + 0x00,
351 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
352 pm8001_mw32(address, offset + 0x04,
353 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
354 pm8001_mw32(address, offset + 0x08,
355 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
356 pm8001_mw32(address, offset + 0x0C,
357 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
358 pm8001_mw32(address, offset + 0x10,
359 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
363 * update_outbnd_queue_table - update the outbound queue table to the HBA.
364 * @pm8001_ha: our hba card information
365 * @number: entry in the queue
367 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
370 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
371 u16 offset = number * 0x24;
372 pm8001_mw32(address, offset + 0x00,
373 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
374 pm8001_mw32(address, offset + 0x04,
375 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
376 pm8001_mw32(address, offset + 0x08,
377 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
378 pm8001_mw32(address, offset + 0x0C,
379 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
380 pm8001_mw32(address, offset + 0x10,
381 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
382 pm8001_mw32(address, offset + 0x1C,
383 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
387 * pm8001_bar4_shift - function is called to shift BAR base address
388 * @pm8001_ha : our hba card information
389 * @shiftValue : shifting value in memory bar.
391 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
396 /* program the inbound AXI translation Lower Address */
397 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
399 /* confirm the setting is written */
400 start = jiffies + HZ; /* 1 sec */
402 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
403 } while ((regVal != shiftValue) && time_before(jiffies, start));
405 if (regVal != shiftValue) {
406 pm8001_dbg(pm8001_ha, INIT,
407 "TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n",
415 * mpi_set_phys_g3_with_ssc
416 * @pm8001_ha: our hba card information
417 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
419 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
425 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
426 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
427 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
428 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
429 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
430 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
431 #define SNW3_PHY_CAPABILITIES_PARITY 31
434 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
435 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
437 spin_lock_irqsave(&pm8001_ha->lock, flags);
438 if (-1 == pm8001_bar4_shift(pm8001_ha,
439 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
440 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
444 for (i = 0; i < 4; i++) {
445 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
446 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
448 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
449 if (-1 == pm8001_bar4_shift(pm8001_ha,
450 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
451 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
454 for (i = 4; i < 8; i++) {
455 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
456 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
458 /*************************************************************
459 Change the SSC upspreading value to 0x0 so that upspreading is disabled.
460 Device MABC SMOD0 Controls
461 Address: (via MEMBASE-III):
462 Using shifted destination address 0x0_0000: with Offset 0xD8
464 31:28 R/W Reserved Do not change
465 27:24 R/W SAS_SMOD_SPRDUP 0000
466 23:20 R/W SAS_SMOD_SPRDDN 0000
467 19:0 R/W Reserved Do not change
468 Upon power-up this register will read as 0x8990c016,
469 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
470 so that the written value will be 0x8090c016.
471 This will ensure only down-spreading SSC is enabled on the SPC.
472 *************************************************************/
473 pm8001_cr32(pm8001_ha, 2, 0xd8);
474 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
476 /*set the shifted destination address to 0x0 to avoid error operation */
477 pm8001_bar4_shift(pm8001_ha, 0x0);
478 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
483 * mpi_set_open_retry_interval_reg
484 * @pm8001_ha: our hba card information
485 * @interval: interval time for each OPEN_REJECT (RETRY). The units are in 1us.
487 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
495 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
496 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
497 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
498 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
499 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
501 value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
502 spin_lock_irqsave(&pm8001_ha->lock, flags);
503 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
504 if (-1 == pm8001_bar4_shift(pm8001_ha,
505 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
506 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
509 for (i = 0; i < 4; i++) {
510 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
511 pm8001_cw32(pm8001_ha, 2, offset, value);
514 if (-1 == pm8001_bar4_shift(pm8001_ha,
515 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
516 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
519 for (i = 4; i < 8; i++) {
520 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
521 pm8001_cw32(pm8001_ha, 2, offset, value);
523 /*set the shifted destination address to 0x0 to avoid error operation */
524 pm8001_bar4_shift(pm8001_ha, 0x0);
525 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
530 * mpi_init_check - check firmware initialization status.
531 * @pm8001_ha: our hba card information
533 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
537 u32 gst_len_mpistate;
538 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
540 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
541 /* wait until Inbound DoorBell Clear Register toggled */
542 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
545 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
546 value &= SPC_MSGU_CFG_TABLE_UPDATE;
547 } while ((value != 0) && (--max_wait_count));
551 /* check the MPI-State for initialization */
553 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
554 GST_GSTLEN_MPIS_OFFSET);
555 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
557 /* check MPI Initialization error */
558 gst_len_mpistate = gst_len_mpistate >> 16;
559 if (0x0000 != gst_len_mpistate)
565 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
566 * @pm8001_ha: our hba card information
568 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
572 /* check error state */
573 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
574 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
575 /* check AAP error */
576 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
578 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
582 /* check IOP error */
583 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
585 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
589 /* bit 4-31 of scratch pad1 should be zeros if it is not
591 if (value & SCRATCH_PAD1_STATE_MASK) {
593 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
597 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
599 if (value1 & SCRATCH_PAD2_STATE_MASK) {
604 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
606 /* wait until scratch pad 1 and 2 registers in ready state */
609 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
611 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
613 if ((--max_wait_count) == 0)
615 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
619 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
621 void __iomem *base_addr;
627 value = pm8001_cr32(pm8001_ha, 0, 0x44);
628 offset = value & 0x03FFFFFF;
629 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 Offset: %x\n", offset);
630 pcilogic = (value & 0xFC000000) >> 26;
631 pcibar = get_pci_bar_index(pcilogic);
632 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar);
633 pm8001_ha->main_cfg_tbl_addr = base_addr =
634 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
635 pm8001_ha->general_stat_tbl_addr =
636 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
637 pm8001_ha->inbnd_q_tbl_addr =
638 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
639 pm8001_ha->outbnd_q_tbl_addr =
640 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
644 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
645 * @pm8001_ha: our hba card information
647 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
651 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
652 /* 8081 controllers need BAR shift to access MPI space
653 * as this is shared with BIOS data */
654 if (deviceid == 0x8081 || deviceid == 0x0042) {
655 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
656 pm8001_dbg(pm8001_ha, FAIL,
657 "Shift Bar4 to 0x%x failed\n",
662 /* check the firmware status */
663 if (-1 == check_fw_ready(pm8001_ha)) {
664 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
668 /* Initialize pci space address eg: mpi offset */
669 init_pci_device_addresses(pm8001_ha);
670 init_default_table_values(pm8001_ha);
671 read_main_config_table(pm8001_ha);
672 read_general_status_table(pm8001_ha);
673 read_inbnd_queue_table(pm8001_ha);
674 read_outbnd_queue_table(pm8001_ha);
675 /* update main config table ,inbound table and outbound table */
676 update_main_config_table(pm8001_ha);
677 for (i = 0; i < pm8001_ha->max_q_num; i++)
678 update_inbnd_queue_table(pm8001_ha, i);
679 for (i = 0; i < pm8001_ha->max_q_num; i++)
680 update_outbnd_queue_table(pm8001_ha, i);
681 /* 8081 controller donot require these operations */
682 if (deviceid != 0x8081 && deviceid != 0x0042) {
683 mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
684 /* 7->130ms, 34->500ms, 119->1.5s */
685 mpi_set_open_retry_interval_reg(pm8001_ha, 119);
687 /* notify firmware update finished and check initialization status */
688 if (0 == mpi_init_check(pm8001_ha)) {
689 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n");
692 /*This register is a 16-bit timer with a resolution of 1us. This is the
693 timer used for interrupt delay/coalescing in the PCIe Application Layer.
694 Zero is not a valid value. A value of 1 in the register will cause the
695 interrupts to be normal. A value greater than 1 will cause coalescing
697 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
698 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
702 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
706 u32 gst_len_mpistate;
708 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
709 if (deviceid == 0x8081 || deviceid == 0x0042) {
710 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
711 pm8001_dbg(pm8001_ha, FAIL,
712 "Shift Bar4 to 0x%x failed\n",
717 init_pci_device_addresses(pm8001_ha);
718 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
720 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
722 /* wait until Inbound DoorBell Clear Register toggled */
723 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
726 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
727 value &= SPC_MSGU_CFG_TABLE_RESET;
728 } while ((value != 0) && (--max_wait_count));
730 if (!max_wait_count) {
731 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=0x%x\n",
736 /* check the MPI-State for termination in progress */
737 /* wait until Inbound DoorBell Clear Register toggled */
738 max_wait_count = 1 * 1000 * 1000; /* 1 sec */
742 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
743 GST_GSTLEN_MPIS_OFFSET);
744 if (GST_MPI_STATE_UNINIT ==
745 (gst_len_mpistate & GST_MPI_STATE_MASK))
747 } while (--max_wait_count);
748 if (!max_wait_count) {
749 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n",
750 gst_len_mpistate & GST_MPI_STATE_MASK);
757 * soft_reset_ready_check - Function to check FW is ready for soft reset.
758 * @pm8001_ha: our hba card information
760 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
762 u32 regVal, regVal1, regVal2;
763 if (mpi_uninit_check(pm8001_ha) != 0) {
764 pm8001_dbg(pm8001_ha, FAIL, "MPI state is not ready\n");
767 /* read the scratch pad 2 register bit 2 */
768 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
769 & SCRATCH_PAD2_FWRDY_RST;
770 if (regVal == SCRATCH_PAD2_FWRDY_RST) {
771 pm8001_dbg(pm8001_ha, INIT, "Firmware is ready for reset.\n");
774 /* Trigger NMI twice via RB6 */
775 spin_lock_irqsave(&pm8001_ha->lock, flags);
776 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
777 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
778 pm8001_dbg(pm8001_ha, FAIL,
779 "Shift Bar4 to 0x%x failed\n",
783 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
784 RB6_MAGIC_NUMBER_RST);
785 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
786 /* wait for 100 ms */
788 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
789 SCRATCH_PAD2_FWRDY_RST;
790 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
791 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
792 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
793 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MSGU_SCRATCH_PAD1=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
795 pm8001_dbg(pm8001_ha, FAIL,
796 "SCRATCH_PAD0 value = 0x%x\n",
797 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0));
798 pm8001_dbg(pm8001_ha, FAIL,
799 "SCRATCH_PAD3 value = 0x%x\n",
800 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3));
801 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
804 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
810 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
811 * the FW register status to the originated status.
812 * @pm8001_ha: our hba card information
815 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
817 u32 regVal, toggleVal;
819 u32 regVal1, regVal2, regVal3;
820 u32 signature = 0x252acbcd; /* for host scratch pad0 */
823 /* step1: Check FW is ready for soft reset */
824 if (soft_reset_ready_check(pm8001_ha) != 0) {
825 pm8001_dbg(pm8001_ha, FAIL, "FW is not ready\n");
829 /* step 2: clear NMI status register on AAP1 and IOP, write the same
831 /* map 0x60000 to BAR4(0x20), BAR2(win) */
832 spin_lock_irqsave(&pm8001_ha->lock, flags);
833 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
834 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
835 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
836 MBIC_AAP1_ADDR_BASE);
839 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
840 pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (IOP)= 0x%x\n",
842 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
843 /* map 0x70000 to BAR4(0x20), BAR2(win) */
844 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
845 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
846 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
850 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
851 pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n",
853 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
855 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
856 pm8001_dbg(pm8001_ha, INIT, "PCIE -Event Interrupt Enable = 0x%x\n",
858 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
860 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
861 pm8001_dbg(pm8001_ha, INIT, "PCIE - Event Interrupt = 0x%x\n",
863 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
865 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
866 pm8001_dbg(pm8001_ha, INIT, "PCIE -Error Interrupt Enable = 0x%x\n",
868 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
870 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
871 pm8001_dbg(pm8001_ha, INIT, "PCIE - Error Interrupt = 0x%x\n", regVal);
872 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
874 /* read the scratch pad 1 register bit 2 */
875 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
877 toggleVal = regVal ^ SCRATCH_PAD1_RST;
879 /* set signature in host scratch pad0 register to tell SPC that the
880 host performs the soft reset */
881 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
883 /* read required registers for confirmming */
884 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
885 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
886 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
887 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
891 pm8001_dbg(pm8001_ha, INIT,
892 "GSM 0x0(0x00007b88)-GSM Configuration and Reset = 0x%x\n",
893 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
895 /* step 3: host read GSM Configuration and Reset register */
896 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
897 /* Put those bits to low */
898 /* GSM XCBI offset = 0x70 0000
899 0x00 Bit 13 COM_SLV_SW_RSTB 1
900 0x00 Bit 12 QSSP_SW_RSTB 1
901 0x00 Bit 11 RAAE_SW_RSTB 1
902 0x00 Bit 9 RB_1_SW_RSTB 1
903 0x00 Bit 8 SM_SW_RSTB 1
905 regVal &= ~(0x00003b00);
906 /* host write GSM Configuration and Reset register */
907 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
908 pm8001_dbg(pm8001_ha, INIT,
909 "GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM Configuration and Reset is set to = 0x%x\n",
910 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
913 /* disable GSM - Read Address Parity Check */
914 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
915 pm8001_dbg(pm8001_ha, INIT,
916 "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n",
918 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
919 pm8001_dbg(pm8001_ha, INIT,
920 "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n",
921 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK));
923 /* disable GSM - Write Address Parity Check */
924 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
925 pm8001_dbg(pm8001_ha, INIT,
926 "GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n",
928 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
929 pm8001_dbg(pm8001_ha, INIT,
930 "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n",
931 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK));
933 /* disable GSM - Write Data Parity Check */
934 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
935 pm8001_dbg(pm8001_ha, INIT, "GSM 0x300048 - Write Data Parity Check Enable = 0x%x\n",
937 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
938 pm8001_dbg(pm8001_ha, INIT,
939 "GSM 0x300048 - Write Data Parity Check Enable is set to = 0x%x\n",
940 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK));
942 /* step 5: delay 10 usec */
944 /* step 5-b: set GPIO-0 output control to tristate anyway */
945 if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
946 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
947 pm8001_dbg(pm8001_ha, INIT, "Shift Bar4 to 0x%x failed\n",
951 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
952 pm8001_dbg(pm8001_ha, INIT, "GPIO Output Control Register: = 0x%x\n",
954 /* set GPIO-0 output control to tri-state */
955 regVal &= 0xFFFFFFFC;
956 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
958 /* Step 6: Reset the IOP and AAP1 */
959 /* map 0x00000 to BAR4(0x20), BAR2(win) */
960 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
961 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
962 pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n",
963 SPC_TOP_LEVEL_ADDR_BASE);
966 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
967 pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting IOP/AAP1:= 0x%x\n",
969 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
970 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
972 /* step 7: Reset the BDMA/OSSP */
973 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
974 pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting BDMA/OSSP: = 0x%x\n",
976 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
977 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
979 /* step 8: delay 10 usec */
982 /* step 9: bring the BDMA and OSSP out of reset */
983 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
984 pm8001_dbg(pm8001_ha, INIT,
985 "Top Register before bringing up BDMA/OSSP:= 0x%x\n",
987 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
988 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
990 /* step 10: delay 10 usec */
993 /* step 11: reads and sets the GSM Configuration and Reset Register */
994 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
995 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
996 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
997 pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n",
1001 pm8001_dbg(pm8001_ha, INIT,
1002 "GSM 0x0 (0x00007b88)-GSM Configuration and Reset = 0x%x\n",
1003 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
1004 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
1005 /* Put those bits to high */
1006 /* GSM XCBI offset = 0x70 0000
1007 0x00 Bit 13 COM_SLV_SW_RSTB 1
1008 0x00 Bit 12 QSSP_SW_RSTB 1
1009 0x00 Bit 11 RAAE_SW_RSTB 1
1010 0x00 Bit 9 RB_1_SW_RSTB 1
1011 0x00 Bit 8 SM_SW_RSTB 1
1013 regVal |= (GSM_CONFIG_RESET_VALUE);
1014 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
1015 pm8001_dbg(pm8001_ha, INIT, "GSM (0x00004088 ==> 0x00007b88) - GSM Configuration and Reset is set to = 0x%x\n",
1016 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
1018 /* step 12: Restore GSM - Read Address Parity Check */
1019 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
1020 /* just for debugging */
1021 pm8001_dbg(pm8001_ha, INIT,
1022 "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n",
1024 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
1025 pm8001_dbg(pm8001_ha, INIT, "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n",
1026 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK));
1027 /* Restore GSM - Write Address Parity Check */
1028 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
1029 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
1030 pm8001_dbg(pm8001_ha, INIT,
1031 "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n",
1032 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK));
1033 /* Restore GSM - Write Data Parity Check */
1034 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
1035 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
1036 pm8001_dbg(pm8001_ha, INIT,
1037 "GSM 0x700048 - Write Data Parity Check Enable is set to = 0x%x\n",
1038 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK));
1040 /* step 13: bring the IOP and AAP1 out of reset */
1041 /* map 0x00000 to BAR4(0x20), BAR2(win) */
1042 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
1043 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1044 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
1045 SPC_TOP_LEVEL_ADDR_BASE);
1048 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1049 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1050 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1052 /* step 14: delay 10 usec - Normal Mode */
1054 /* check Soft Reset Normal mode or Soft Reset HDA mode */
1055 if (signature == SPC_SOFT_RESET_SIGNATURE) {
1056 /* step 15 (Normal Mode): wait until scratch pad1 register
1058 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1061 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1063 } while ((regVal != toggleVal) && (--max_wait_count));
1065 if (!max_wait_count) {
1066 regVal = pm8001_cr32(pm8001_ha, 0,
1067 MSGU_SCRATCH_PAD_1);
1068 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT : ToggleVal 0x%x,MSGU_SCRATCH_PAD1 = 0x%x\n",
1070 pm8001_dbg(pm8001_ha, FAIL,
1071 "SCRATCH_PAD0 value = 0x%x\n",
1072 pm8001_cr32(pm8001_ha, 0,
1073 MSGU_SCRATCH_PAD_0));
1074 pm8001_dbg(pm8001_ha, FAIL,
1075 "SCRATCH_PAD2 value = 0x%x\n",
1076 pm8001_cr32(pm8001_ha, 0,
1077 MSGU_SCRATCH_PAD_2));
1078 pm8001_dbg(pm8001_ha, FAIL,
1079 "SCRATCH_PAD3 value = 0x%x\n",
1080 pm8001_cr32(pm8001_ha, 0,
1081 MSGU_SCRATCH_PAD_3));
1082 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1086 /* step 16 (Normal) - Clear ODMR and ODCR */
1087 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1088 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1090 /* step 17 (Normal Mode): wait for the FW and IOP to get
1091 ready - 1 sec timeout */
1092 /* Wait for the SPC Configuration Table to be ready */
1093 if (check_fw_ready(pm8001_ha) == -1) {
1094 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1095 /* return error if MPI Configuration Table not ready */
1096 pm8001_dbg(pm8001_ha, INIT,
1097 "FW not ready SCRATCH_PAD1 = 0x%x\n",
1099 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1100 /* return error if MPI Configuration Table not ready */
1101 pm8001_dbg(pm8001_ha, INIT,
1102 "FW not ready SCRATCH_PAD2 = 0x%x\n",
1104 pm8001_dbg(pm8001_ha, INIT,
1105 "SCRATCH_PAD0 value = 0x%x\n",
1106 pm8001_cr32(pm8001_ha, 0,
1107 MSGU_SCRATCH_PAD_0));
1108 pm8001_dbg(pm8001_ha, INIT,
1109 "SCRATCH_PAD3 value = 0x%x\n",
1110 pm8001_cr32(pm8001_ha, 0,
1111 MSGU_SCRATCH_PAD_3));
1112 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1116 pm8001_bar4_shift(pm8001_ha, 0);
1117 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1119 pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n");
1123 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1127 pm8001_dbg(pm8001_ha, INIT, "chip reset start\n");
1129 /* do SPC chip reset. */
1130 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1131 regVal &= ~(SPC_REG_RESET_DEVICE);
1132 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1137 /* bring chip reset out of reset */
1138 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1139 regVal |= SPC_REG_RESET_DEVICE;
1140 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1145 /* wait for 20 msec until the firmware gets reloaded */
1149 } while ((--i) != 0);
1151 pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n");
1155 * pm8001_chip_iounmap - which mapped when initialized.
1156 * @pm8001_ha: our hba card information
1158 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1160 s8 bar, logical = 0;
1161 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
1163 ** logical BARs for SPC:
1164 ** bar 0 and 1 - logical BAR0
1165 ** bar 2 and 3 - logical BAR1
1166 ** bar4 - logical BAR2
1167 ** bar5 - logical BAR3
1168 ** Skip the appropriate assignments:
1170 if ((bar == 1) || (bar == 3))
1172 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1173 iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1179 #ifndef PM8001_USE_MSIX
1181 * pm8001_chip_intx_interrupt_enable - enable PM8001 chip interrupt
1182 * @pm8001_ha: our hba card information
1185 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1187 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1188 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1192 * pm8001_chip_intx_interrupt_disable - disable PM8001 chip interrupt
1193 * @pm8001_ha: our hba card information
1196 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1198 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1204 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1205 * @pm8001_ha: our hba card information
1206 * @int_vec_idx: interrupt number to enable
1209 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1214 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1215 msi_index += MSIX_TABLE_BASE;
1216 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1217 value = (1 << int_vec_idx);
1218 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value);
1223 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1224 * @pm8001_ha: our hba card information
1225 * @int_vec_idx: interrupt number to disable
1228 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1232 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1233 msi_index += MSIX_TABLE_BASE;
1234 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE);
1239 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1240 * @pm8001_ha: our hba card information
1244 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1246 #ifdef PM8001_USE_MSIX
1247 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1249 pm8001_chip_intx_interrupt_enable(pm8001_ha);
1254 * pm8001_chip_interrupt_disable - disable PM8001 chip interrupt
1255 * @pm8001_ha: our hba card information
1259 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1261 #ifdef PM8001_USE_MSIX
1262 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1264 pm8001_chip_intx_interrupt_disable(pm8001_ha);
1269 * pm8001_mpi_msg_free_get - get the free message buffer for transfer
1271 * @circularQ: the inbound queue we want to transfer to HBA.
1272 * @messageSize: the message size of this transfer, normally it is 64 bytes
1273 * @messagePtr: the pointer to message.
1275 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
1276 u16 messageSize, void **messagePtr)
1278 u32 offset, consumer_index;
1279 struct mpi_msg_hdr *msgHeader;
1280 u8 bcCount = 1; /* only support single buffer */
1282 /* Checks is the requested message size can be allocated in this queue*/
1283 if (messageSize > IOMB_SIZE_SPCV) {
1288 /* Stores the new consumer index */
1289 consumer_index = pm8001_read_32(circularQ->ci_virt);
1290 circularQ->consumer_index = cpu_to_le32(consumer_index);
1291 if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
1292 le32_to_cpu(circularQ->consumer_index)) {
1296 /* get memory IOMB buffer address */
1297 offset = circularQ->producer_idx * messageSize;
1298 /* increment to next bcCount element */
1299 circularQ->producer_idx = (circularQ->producer_idx + bcCount)
1301 /* Adds that distance to the base of the region virtual address plus
1302 the message header size*/
1303 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1304 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1309 * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to
1310 * FW to tell the fw to get this message from IOMB.
1311 * @pm8001_ha: our hba card information
1312 * @circularQ: the inbound queue we want to transfer to HBA.
1313 * @opCode: the operation code represents commands which LLDD and fw recognized.
1314 * @payload: the command payload of each operation command.
1315 * @nb: size in bytes of the command payload
1316 * @responseQueue: queue to interrupt on w/ command response (if any)
1318 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1319 struct inbound_queue_table *circularQ,
1320 u32 opCode, void *payload, size_t nb,
1323 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1325 unsigned long flags;
1326 int q_index = circularQ - pm8001_ha->inbnd_q_tbl;
1328 u32 htag = le32_to_cpu(*(__le32 *)payload);
1330 trace_pm80xx_mpi_build_cmd(pm8001_ha->id, opCode, htag, q_index,
1331 circularQ->producer_idx, le32_to_cpu(circularQ->consumer_index));
1333 if (WARN_ON(q_index >= pm8001_ha->max_q_num))
1336 spin_lock_irqsave(&circularQ->iq_lock, flags);
1337 rv = pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size,
1340 pm8001_dbg(pm8001_ha, IO, "No free mpi buffer\n");
1345 if (nb > (pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr)))
1346 nb = pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr);
1347 memcpy(pMessage, payload, nb);
1348 if (nb + sizeof(struct mpi_msg_hdr) < pm8001_ha->iomb_size)
1349 memset(pMessage + nb, 0, pm8001_ha->iomb_size -
1350 (nb + sizeof(struct mpi_msg_hdr)));
1352 /*Build the header*/
1353 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1354 | ((responseQueue & 0x3F) << 16)
1355 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1357 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1358 /*Update the PI to the firmware*/
1359 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1360 circularQ->pi_offset, circularQ->producer_idx);
1361 pm8001_dbg(pm8001_ha, DEVIO,
1362 "INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n",
1363 responseQueue, opCode, circularQ->producer_idx,
1364 circularQ->consumer_index);
1366 spin_unlock_irqrestore(&circularQ->iq_lock, flags);
1370 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1371 struct outbound_queue_table *circularQ, u8 bc)
1374 struct mpi_msg_hdr *msgHeader;
1375 struct mpi_msg_hdr *pOutBoundMsgHeader;
1377 msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1378 pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1379 circularQ->consumer_idx * pm8001_ha->iomb_size);
1380 if (pOutBoundMsgHeader != msgHeader) {
1381 pm8001_dbg(pm8001_ha, FAIL,
1382 "consumer_idx = %d msgHeader = %p\n",
1383 circularQ->consumer_idx, msgHeader);
1385 /* Update the producer index from SPC */
1386 producer_index = pm8001_read_32(circularQ->pi_virt);
1387 circularQ->producer_index = cpu_to_le32(producer_index);
1388 pm8001_dbg(pm8001_ha, FAIL,
1389 "consumer_idx = %d producer_index = %dmsgHeader = %p\n",
1390 circularQ->consumer_idx,
1391 circularQ->producer_index, msgHeader);
1394 /* free the circular queue buffer elements associated with the message*/
1395 circularQ->consumer_idx = (circularQ->consumer_idx + bc)
1397 /* update the CI of outbound queue */
1398 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1399 circularQ->consumer_idx);
1400 /* Update the producer index from SPC*/
1401 producer_index = pm8001_read_32(circularQ->pi_virt);
1402 circularQ->producer_index = cpu_to_le32(producer_index);
1403 pm8001_dbg(pm8001_ha, IO, " CI=%d PI=%d\n",
1404 circularQ->consumer_idx, circularQ->producer_index);
1409 * pm8001_mpi_msg_consume- get the MPI message from outbound queue
1411 * @pm8001_ha: our hba card information
1412 * @circularQ: the outbound queue table.
1413 * @messagePtr1: the message contents of this outbound message.
1414 * @pBC: the message size.
1416 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1417 struct outbound_queue_table *circularQ,
1418 void **messagePtr1, u8 *pBC)
1420 struct mpi_msg_hdr *msgHeader;
1421 __le32 msgHeader_tmp;
1424 /* If there are not-yet-delivered messages ... */
1425 if (le32_to_cpu(circularQ->producer_index)
1426 != circularQ->consumer_idx) {
1427 /*Get the pointer to the circular queue buffer element*/
1428 msgHeader = (struct mpi_msg_hdr *)
1429 (circularQ->base_virt +
1430 circularQ->consumer_idx * pm8001_ha->iomb_size);
1432 header_tmp = pm8001_read_32(msgHeader);
1433 msgHeader_tmp = cpu_to_le32(header_tmp);
1434 pm8001_dbg(pm8001_ha, DEVIO,
1435 "outbound opcode msgheader:%x ci=%d pi=%d\n",
1436 msgHeader_tmp, circularQ->consumer_idx,
1437 circularQ->producer_index);
1438 if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
1439 if (OPC_OUB_SKIP_ENTRY !=
1440 (le32_to_cpu(msgHeader_tmp) & 0xfff)) {
1443 sizeof(struct mpi_msg_hdr);
1444 *pBC = (u8)((le32_to_cpu(msgHeader_tmp)
1446 pm8001_dbg(pm8001_ha, IO,
1447 ": CI=%d PI=%d msgHeader=%x\n",
1448 circularQ->consumer_idx,
1449 circularQ->producer_index,
1451 return MPI_IO_STATUS_SUCCESS;
1453 circularQ->consumer_idx =
1454 (circularQ->consumer_idx +
1455 ((le32_to_cpu(msgHeader_tmp)
1459 pm8001_write_32(msgHeader, 0, 0);
1460 /* update the CI of outbound queue */
1461 pm8001_cw32(pm8001_ha,
1462 circularQ->ci_pci_bar,
1463 circularQ->ci_offset,
1464 circularQ->consumer_idx);
1467 circularQ->consumer_idx =
1468 (circularQ->consumer_idx +
1469 ((le32_to_cpu(msgHeader_tmp) >> 24) &
1470 0x1f)) % PM8001_MPI_QUEUE;
1472 pm8001_write_32(msgHeader, 0, 0);
1473 /* update the CI of outbound queue */
1474 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1475 circularQ->ci_offset,
1476 circularQ->consumer_idx);
1477 return MPI_IO_STATUS_FAIL;
1481 void *pi_virt = circularQ->pi_virt;
1482 /* spurious interrupt during setup if
1483 * kexec-ing and driver doing a doorbell access
1484 * with the pre-kexec oq interrupt setup
1488 /* Update the producer index from SPC */
1489 producer_index = pm8001_read_32(pi_virt);
1490 circularQ->producer_index = cpu_to_le32(producer_index);
1492 } while (le32_to_cpu(circularQ->producer_index) !=
1493 circularQ->consumer_idx);
1494 /* while we don't have any more not-yet-delivered message */
1496 return MPI_IO_STATUS_BUSY;
1499 void pm8001_work_fn(struct work_struct *work)
1501 struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1502 struct pm8001_device *pm8001_dev;
1503 struct domain_device *dev;
1506 * So far, all users of this stash an associated structure here.
1507 * If we get here, and this pointer is null, then the action
1508 * was cancelled. This nullification happens when the device
1511 if (pw->handler != IO_FATAL_ERROR) {
1512 pm8001_dev = pw->data; /* Most stash device structure */
1513 if ((pm8001_dev == NULL)
1514 || ((pw->handler != IO_XFER_ERROR_BREAK)
1515 && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) {
1521 switch (pw->handler) {
1522 case IO_XFER_ERROR_BREAK:
1523 { /* This one stashes the sas_task instead */
1524 struct sas_task *t = (struct sas_task *)pm8001_dev;
1526 struct pm8001_ccb_info *ccb;
1527 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1528 unsigned long flags, flags1;
1529 struct task_status_struct *ts;
1532 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1533 break; /* Task still on lu */
1534 spin_lock_irqsave(&pm8001_ha->lock, flags);
1536 spin_lock_irqsave(&t->task_state_lock, flags1);
1537 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1538 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1539 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1540 break; /* Task got completed by another */
1542 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1544 /* Search for a possible ccb that matches the task */
1545 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1546 ccb = &pm8001_ha->ccb_info[i];
1548 if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1552 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1553 break; /* Task got freed by another */
1555 ts = &t->task_status;
1556 ts->resp = SAS_TASK_COMPLETE;
1557 /* Force the midlayer to retry */
1558 ts->stat = SAS_QUEUE_FULL;
1559 pm8001_dev = ccb->device;
1561 atomic_dec(&pm8001_dev->running_req);
1562 spin_lock_irqsave(&t->task_state_lock, flags1);
1563 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1564 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1565 t->task_state_flags |= SAS_TASK_STATE_DONE;
1566 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1567 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1568 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
1569 t, pw->handler, ts->resp, ts->stat);
1570 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1571 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1573 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1574 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1575 mb();/* in order to force CPU ordering */
1576 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1580 case IO_XFER_OPEN_RETRY_TIMEOUT:
1581 { /* This one stashes the sas_task instead */
1582 struct sas_task *t = (struct sas_task *)pm8001_dev;
1584 struct pm8001_ccb_info *ccb;
1585 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1586 unsigned long flags, flags1;
1589 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
1591 ret = pm8001_query_task(t);
1593 if (ret == TMF_RESP_FUNC_SUCC)
1594 pm8001_dbg(pm8001_ha, IO, "...Task on lu\n");
1595 else if (ret == TMF_RESP_FUNC_COMPLETE)
1596 pm8001_dbg(pm8001_ha, IO, "...Task NOT on lu\n");
1598 pm8001_dbg(pm8001_ha, DEVIO, "...query task failed!!!\n");
1600 spin_lock_irqsave(&pm8001_ha->lock, flags);
1602 spin_lock_irqsave(&t->task_state_lock, flags1);
1604 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1605 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1606 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1607 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1608 (void)pm8001_abort_task(t);
1609 break; /* Task got completed by another */
1612 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1614 /* Search for a possible ccb that matches the task */
1615 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1616 ccb = &pm8001_ha->ccb_info[i];
1618 if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1622 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1623 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1624 (void)pm8001_abort_task(t);
1625 break; /* Task got freed by another */
1628 pm8001_dev = ccb->device;
1629 dev = pm8001_dev->sas_device;
1632 case TMF_RESP_FUNC_SUCC: /* task on lu */
1633 ccb->open_retry = 1; /* Snub completion */
1634 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1635 ret = pm8001_abort_task(t);
1636 ccb->open_retry = 0;
1638 case TMF_RESP_FUNC_SUCC:
1639 case TMF_RESP_FUNC_COMPLETE:
1641 default: /* device misbehavior */
1642 ret = TMF_RESP_FUNC_FAILED;
1643 pm8001_dbg(pm8001_ha, IO, "...Reset phy\n");
1644 pm8001_I_T_nexus_reset(dev);
1649 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1650 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1651 /* Do we need to abort the task locally? */
1654 default: /* device misbehavior */
1655 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1656 ret = TMF_RESP_FUNC_FAILED;
1657 pm8001_dbg(pm8001_ha, IO, "...Reset phy\n");
1658 pm8001_I_T_nexus_reset(dev);
1661 if (ret == TMF_RESP_FUNC_FAILED)
1663 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1664 pm8001_dbg(pm8001_ha, IO, "...Complete\n");
1666 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1667 dev = pm8001_dev->sas_device;
1668 pm8001_I_T_nexus_event_handler(dev);
1670 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1671 dev = pm8001_dev->sas_device;
1672 pm8001_I_T_nexus_reset(dev);
1674 case IO_DS_IN_ERROR:
1675 dev = pm8001_dev->sas_device;
1676 pm8001_I_T_nexus_reset(dev);
1678 case IO_DS_NON_OPERATIONAL:
1679 dev = pm8001_dev->sas_device;
1680 pm8001_I_T_nexus_reset(dev);
1682 case IO_FATAL_ERROR:
1684 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1685 struct pm8001_ccb_info *ccb;
1686 struct task_status_struct *ts;
1687 struct sas_task *task;
1691 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1692 ccb = &pm8001_ha->ccb_info[i];
1694 ts = &task->task_status;
1696 /* check if tag is NULL */
1698 pm8001_dbg(pm8001_ha, FAIL,
1705 pm8001_dbg(pm8001_ha, FAIL,
1709 /*complete sas task and update to top layer */
1710 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
1711 ts->resp = SAS_TASK_COMPLETE;
1712 task->task_done(task);
1713 } else if (tag != 0xFFFFFFFF) {
1714 /* complete the internal commands/non-sas task */
1715 pm8001_dev = ccb->device;
1716 if (pm8001_dev->dcompletion) {
1717 complete(pm8001_dev->dcompletion);
1718 pm8001_dev->dcompletion = NULL;
1720 complete(pm8001_ha->nvmd_completion);
1721 pm8001_tag_free(pm8001_ha, tag);
1724 /* Deregister all the device ids */
1725 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
1726 pm8001_dev = &pm8001_ha->devices[i];
1727 device_id = pm8001_dev->device_id;
1729 PM8001_CHIP_DISP->dereg_dev_req(pm8001_ha, device_id);
1730 pm8001_free_dev(pm8001_dev);
1738 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1741 struct pm8001_work *pw;
1744 pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1746 pw->pm8001_ha = pm8001_ha;
1748 pw->handler = handler;
1749 INIT_WORK(&pw->work, pm8001_work_fn);
1750 queue_work(pm8001_wq, &pw->work);
1757 static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1758 struct pm8001_device *pm8001_ha_dev)
1762 struct pm8001_ccb_info *ccb;
1763 struct sas_task *task = NULL;
1764 struct task_abort_req task_abort;
1765 struct inbound_queue_table *circularQ;
1766 u32 opc = OPC_INB_SATA_ABORT;
1769 if (!pm8001_ha_dev) {
1770 pm8001_dbg(pm8001_ha, FAIL, "dev is null\n");
1774 task = sas_alloc_slow_task(GFP_ATOMIC);
1777 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n");
1781 task->task_done = pm8001_task_done;
1783 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1787 ccb = &pm8001_ha->ccb_info[ccb_tag];
1788 ccb->device = pm8001_ha_dev;
1789 ccb->ccb_tag = ccb_tag;
1792 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1794 memset(&task_abort, 0, sizeof(task_abort));
1795 task_abort.abort_all = cpu_to_le32(1);
1796 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1797 task_abort.tag = cpu_to_le32(ccb_tag);
1799 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
1800 sizeof(task_abort), 0);
1802 pm8001_tag_free(pm8001_ha, ccb_tag);
1806 static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha,
1807 struct pm8001_device *pm8001_ha_dev)
1809 struct sata_start_req sata_cmd;
1812 struct pm8001_ccb_info *ccb;
1813 struct sas_task *task = NULL;
1814 struct host_to_dev_fis fis;
1815 struct domain_device *dev;
1816 struct inbound_queue_table *circularQ;
1817 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1819 task = sas_alloc_slow_task(GFP_ATOMIC);
1822 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n");
1825 task->task_done = pm8001_task_done;
1827 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1829 sas_free_task(task);
1830 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate tag !!!\n");
1834 /* allocate domain device by ourselves as libsas
1835 * is not going to provide any
1837 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1839 sas_free_task(task);
1840 pm8001_tag_free(pm8001_ha, ccb_tag);
1841 pm8001_dbg(pm8001_ha, FAIL,
1842 "Domain device cannot be allocated\n");
1846 task->dev->lldd_dev = pm8001_ha_dev;
1848 ccb = &pm8001_ha->ccb_info[ccb_tag];
1849 ccb->device = pm8001_ha_dev;
1850 ccb->ccb_tag = ccb_tag;
1852 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1853 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1855 memset(&sata_cmd, 0, sizeof(sata_cmd));
1856 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1858 /* construct read log FIS */
1859 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1860 fis.fis_type = 0x27;
1862 fis.command = ATA_CMD_READ_LOG_EXT;
1864 fis.sector_count = 0x1;
1866 sata_cmd.tag = cpu_to_le32(ccb_tag);
1867 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1868 sata_cmd.ncqtag_atap_dir_m |= ((0x1 << 7) | (0x5 << 9));
1869 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1871 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
1872 sizeof(sata_cmd), 0);
1874 sas_free_task(task);
1875 pm8001_tag_free(pm8001_ha, ccb_tag);
1881 * mpi_ssp_completion- process the event that FW response to the SSP request.
1882 * @pm8001_ha: our hba card information
1883 * @piomb: the message contents of this outbound message.
1885 * When FW has completed a ssp request for example a IO request, after it has
1886 * filled the SG data with the data, it will trigger this event representing
1887 * that he has finished the job; please check the corresponding buffer.
1888 * So we will tell the caller who maybe waiting the result to tell upper layer
1889 * that the task has been finished.
1892 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1895 struct pm8001_ccb_info *ccb;
1896 unsigned long flags;
1900 struct ssp_completion_resp *psspPayload;
1901 struct task_status_struct *ts;
1902 struct ssp_response_iu *iu;
1903 struct pm8001_device *pm8001_dev;
1904 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1905 status = le32_to_cpu(psspPayload->status);
1906 tag = le32_to_cpu(psspPayload->tag);
1907 ccb = &pm8001_ha->ccb_info[tag];
1908 if ((status == IO_ABORTED) && ccb->open_retry) {
1909 /* Being completed by another */
1910 ccb->open_retry = 0;
1913 pm8001_dev = ccb->device;
1914 param = le32_to_cpu(psspPayload->param);
1918 if (status && status != IO_UNDERFLOW)
1919 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status);
1920 if (unlikely(!t || !t->lldd_task || !t->dev))
1922 ts = &t->task_status;
1923 /* Print sas address of IO failed device */
1924 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1925 (status != IO_UNDERFLOW))
1926 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n",
1927 SAS_ADDR(t->dev->sas_addr));
1930 pm8001_dbg(pm8001_ha, IOERR,
1931 "status:0x%x, tag:0x%x, task:0x%p\n",
1936 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS,param = %d\n",
1939 ts->resp = SAS_TASK_COMPLETE;
1940 ts->stat = SAS_SAM_STAT_GOOD;
1942 ts->resp = SAS_TASK_COMPLETE;
1943 ts->stat = SAS_PROTO_RESPONSE;
1944 ts->residual = param;
1945 iu = &psspPayload->ssp_resp_iu;
1946 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1949 atomic_dec(&pm8001_dev->running_req);
1952 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
1953 ts->resp = SAS_TASK_COMPLETE;
1954 ts->stat = SAS_ABORTED_TASK;
1957 /* SSP Completion with error */
1958 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW,param = %d\n",
1960 ts->resp = SAS_TASK_COMPLETE;
1961 ts->stat = SAS_DATA_UNDERRUN;
1962 ts->residual = param;
1964 atomic_dec(&pm8001_dev->running_req);
1967 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
1968 ts->resp = SAS_TASK_UNDELIVERED;
1969 ts->stat = SAS_PHY_DOWN;
1971 case IO_XFER_ERROR_BREAK:
1972 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
1973 ts->resp = SAS_TASK_COMPLETE;
1974 ts->stat = SAS_OPEN_REJECT;
1975 /* Force the midlayer to retry */
1976 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1978 case IO_XFER_ERROR_PHY_NOT_READY:
1979 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
1980 ts->resp = SAS_TASK_COMPLETE;
1981 ts->stat = SAS_OPEN_REJECT;
1982 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1984 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1985 pm8001_dbg(pm8001_ha, IO,
1986 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
1987 ts->resp = SAS_TASK_COMPLETE;
1988 ts->stat = SAS_OPEN_REJECT;
1989 ts->open_rej_reason = SAS_OREJ_EPROTO;
1991 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1992 pm8001_dbg(pm8001_ha, IO,
1993 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
1994 ts->resp = SAS_TASK_COMPLETE;
1995 ts->stat = SAS_OPEN_REJECT;
1996 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1998 case IO_OPEN_CNX_ERROR_BREAK:
1999 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2000 ts->resp = SAS_TASK_COMPLETE;
2001 ts->stat = SAS_OPEN_REJECT;
2002 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2004 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2005 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2006 ts->resp = SAS_TASK_COMPLETE;
2007 ts->stat = SAS_OPEN_REJECT;
2008 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2010 pm8001_handle_event(pm8001_ha,
2012 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2014 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2015 pm8001_dbg(pm8001_ha, IO,
2016 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2017 ts->resp = SAS_TASK_COMPLETE;
2018 ts->stat = SAS_OPEN_REJECT;
2019 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2021 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2022 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2023 ts->resp = SAS_TASK_COMPLETE;
2024 ts->stat = SAS_OPEN_REJECT;
2025 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2027 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2028 pm8001_dbg(pm8001_ha, IO,
2029 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2030 ts->resp = SAS_TASK_UNDELIVERED;
2031 ts->stat = SAS_OPEN_REJECT;
2032 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2034 case IO_XFER_ERROR_NAK_RECEIVED:
2035 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2036 ts->resp = SAS_TASK_COMPLETE;
2037 ts->stat = SAS_OPEN_REJECT;
2038 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2040 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2041 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2042 ts->resp = SAS_TASK_COMPLETE;
2043 ts->stat = SAS_NAK_R_ERR;
2045 case IO_XFER_ERROR_DMA:
2046 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2047 ts->resp = SAS_TASK_COMPLETE;
2048 ts->stat = SAS_OPEN_REJECT;
2050 case IO_XFER_OPEN_RETRY_TIMEOUT:
2051 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2052 ts->resp = SAS_TASK_COMPLETE;
2053 ts->stat = SAS_OPEN_REJECT;
2054 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2056 case IO_XFER_ERROR_OFFSET_MISMATCH:
2057 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2058 ts->resp = SAS_TASK_COMPLETE;
2059 ts->stat = SAS_OPEN_REJECT;
2061 case IO_PORT_IN_RESET:
2062 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2063 ts->resp = SAS_TASK_COMPLETE;
2064 ts->stat = SAS_OPEN_REJECT;
2066 case IO_DS_NON_OPERATIONAL:
2067 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2068 ts->resp = SAS_TASK_COMPLETE;
2069 ts->stat = SAS_OPEN_REJECT;
2071 pm8001_handle_event(pm8001_ha,
2073 IO_DS_NON_OPERATIONAL);
2075 case IO_DS_IN_RECOVERY:
2076 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2077 ts->resp = SAS_TASK_COMPLETE;
2078 ts->stat = SAS_OPEN_REJECT;
2080 case IO_TM_TAG_NOT_FOUND:
2081 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n");
2082 ts->resp = SAS_TASK_COMPLETE;
2083 ts->stat = SAS_OPEN_REJECT;
2085 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2086 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n");
2087 ts->resp = SAS_TASK_COMPLETE;
2088 ts->stat = SAS_OPEN_REJECT;
2090 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2091 pm8001_dbg(pm8001_ha, IO,
2092 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2093 ts->resp = SAS_TASK_COMPLETE;
2094 ts->stat = SAS_OPEN_REJECT;
2095 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2098 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2099 /* not allowed case. Therefore, return failed status */
2100 ts->resp = SAS_TASK_COMPLETE;
2101 ts->stat = SAS_OPEN_REJECT;
2104 pm8001_dbg(pm8001_ha, IO, "scsi_status = %x\n",
2105 psspPayload->ssp_resp_iu.status);
2106 spin_lock_irqsave(&t->task_state_lock, flags);
2107 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2108 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2109 t->task_state_flags |= SAS_TASK_STATE_DONE;
2110 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2111 spin_unlock_irqrestore(&t->task_state_lock, flags);
2112 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2113 t, status, ts->resp, ts->stat);
2114 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2116 spin_unlock_irqrestore(&t->task_state_lock, flags);
2117 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2118 mb();/* in order to force CPU ordering */
2123 /*See the comments for mpi_ssp_completion */
2124 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2127 unsigned long flags;
2128 struct task_status_struct *ts;
2129 struct pm8001_ccb_info *ccb;
2130 struct pm8001_device *pm8001_dev;
2131 struct ssp_event_resp *psspPayload =
2132 (struct ssp_event_resp *)(piomb + 4);
2133 u32 event = le32_to_cpu(psspPayload->event);
2134 u32 tag = le32_to_cpu(psspPayload->tag);
2135 u32 port_id = le32_to_cpu(psspPayload->port_id);
2136 u32 dev_id = le32_to_cpu(psspPayload->device_id);
2138 ccb = &pm8001_ha->ccb_info[tag];
2140 pm8001_dev = ccb->device;
2142 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event);
2143 if (unlikely(!t || !t->lldd_task || !t->dev))
2145 ts = &t->task_status;
2146 pm8001_dbg(pm8001_ha, DEVIO, "port_id = %x,device_id = %x\n",
2150 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2151 ts->resp = SAS_TASK_COMPLETE;
2152 ts->stat = SAS_DATA_OVERRUN;
2155 atomic_dec(&pm8001_dev->running_req);
2157 case IO_XFER_ERROR_BREAK:
2158 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2159 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2161 case IO_XFER_ERROR_PHY_NOT_READY:
2162 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2163 ts->resp = SAS_TASK_COMPLETE;
2164 ts->stat = SAS_OPEN_REJECT;
2165 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2167 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2168 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2169 ts->resp = SAS_TASK_COMPLETE;
2170 ts->stat = SAS_OPEN_REJECT;
2171 ts->open_rej_reason = SAS_OREJ_EPROTO;
2173 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2174 pm8001_dbg(pm8001_ha, IO,
2175 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2176 ts->resp = SAS_TASK_COMPLETE;
2177 ts->stat = SAS_OPEN_REJECT;
2178 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2180 case IO_OPEN_CNX_ERROR_BREAK:
2181 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2182 ts->resp = SAS_TASK_COMPLETE;
2183 ts->stat = SAS_OPEN_REJECT;
2184 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2186 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2187 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2188 ts->resp = SAS_TASK_COMPLETE;
2189 ts->stat = SAS_OPEN_REJECT;
2190 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2192 pm8001_handle_event(pm8001_ha,
2194 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2196 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2197 pm8001_dbg(pm8001_ha, IO,
2198 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2199 ts->resp = SAS_TASK_COMPLETE;
2200 ts->stat = SAS_OPEN_REJECT;
2201 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2203 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2204 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2205 ts->resp = SAS_TASK_COMPLETE;
2206 ts->stat = SAS_OPEN_REJECT;
2207 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2209 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2210 pm8001_dbg(pm8001_ha, IO,
2211 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2212 ts->resp = SAS_TASK_COMPLETE;
2213 ts->stat = SAS_OPEN_REJECT;
2214 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2216 case IO_XFER_ERROR_NAK_RECEIVED:
2217 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2218 ts->resp = SAS_TASK_COMPLETE;
2219 ts->stat = SAS_OPEN_REJECT;
2220 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2222 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2223 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2224 ts->resp = SAS_TASK_COMPLETE;
2225 ts->stat = SAS_NAK_R_ERR;
2227 case IO_XFER_OPEN_RETRY_TIMEOUT:
2228 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2229 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2231 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2232 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2233 ts->resp = SAS_TASK_COMPLETE;
2234 ts->stat = SAS_DATA_OVERRUN;
2236 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2237 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2238 ts->resp = SAS_TASK_COMPLETE;
2239 ts->stat = SAS_DATA_OVERRUN;
2241 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2242 pm8001_dbg(pm8001_ha, IO,
2243 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2244 ts->resp = SAS_TASK_COMPLETE;
2245 ts->stat = SAS_DATA_OVERRUN;
2247 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2248 pm8001_dbg(pm8001_ha, IO,
2249 "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n");
2250 ts->resp = SAS_TASK_COMPLETE;
2251 ts->stat = SAS_DATA_OVERRUN;
2253 case IO_XFER_ERROR_OFFSET_MISMATCH:
2254 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2255 ts->resp = SAS_TASK_COMPLETE;
2256 ts->stat = SAS_DATA_OVERRUN;
2258 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2259 pm8001_dbg(pm8001_ha, IO,
2260 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2261 ts->resp = SAS_TASK_COMPLETE;
2262 ts->stat = SAS_DATA_OVERRUN;
2264 case IO_XFER_CMD_FRAME_ISSUED:
2265 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2268 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2269 /* not allowed case. Therefore, return failed status */
2270 ts->resp = SAS_TASK_COMPLETE;
2271 ts->stat = SAS_DATA_OVERRUN;
2274 spin_lock_irqsave(&t->task_state_lock, flags);
2275 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2276 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2277 t->task_state_flags |= SAS_TASK_STATE_DONE;
2278 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2279 spin_unlock_irqrestore(&t->task_state_lock, flags);
2280 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2281 t, event, ts->resp, ts->stat);
2282 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2284 spin_unlock_irqrestore(&t->task_state_lock, flags);
2285 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2286 mb();/* in order to force CPU ordering */
2291 /*See the comments for mpi_ssp_completion */
2293 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2296 struct pm8001_ccb_info *ccb;
2301 u8 sata_addr_low[4];
2302 u32 temp_sata_addr_low;
2304 u32 temp_sata_addr_hi;
2305 struct sata_completion_resp *psataPayload;
2306 struct task_status_struct *ts;
2307 struct ata_task_resp *resp ;
2309 struct pm8001_device *pm8001_dev;
2310 unsigned long flags;
2312 psataPayload = (struct sata_completion_resp *)(piomb + 4);
2313 status = le32_to_cpu(psataPayload->status);
2314 param = le32_to_cpu(psataPayload->param);
2315 tag = le32_to_cpu(psataPayload->tag);
2318 pm8001_dbg(pm8001_ha, FAIL, "tag null\n");
2322 ccb = &pm8001_ha->ccb_info[tag];
2324 pm8001_dev = ccb->device;
2327 if (t->dev && (t->dev->lldd_dev))
2328 pm8001_dev = t->dev->lldd_dev;
2330 pm8001_dbg(pm8001_ha, FAIL, "task null\n");
2334 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2335 && unlikely(!t || !t->lldd_task || !t->dev)) {
2336 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2340 ts = &t->task_status;
2343 pm8001_dbg(pm8001_ha, IOERR,
2344 "status:0x%x, tag:0x%x, task::0x%p\n",
2347 /* Print sas address of IO failed device */
2348 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2349 (status != IO_UNDERFLOW)) {
2350 if (!((t->dev->parent) &&
2351 (dev_is_expander(t->dev->parent->dev_type)))) {
2352 for (i = 0, j = 4; j <= 7 && i <= 3; i++, j++)
2353 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2354 for (i = 0, j = 0; j <= 3 && i <= 3; i++, j++)
2355 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2356 memcpy(&temp_sata_addr_low, sata_addr_low,
2357 sizeof(sata_addr_low));
2358 memcpy(&temp_sata_addr_hi, sata_addr_hi,
2359 sizeof(sata_addr_hi));
2360 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2361 |((temp_sata_addr_hi << 8) &
2363 ((temp_sata_addr_hi >> 8)
2365 ((temp_sata_addr_hi << 24) &
2367 temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2369 ((temp_sata_addr_low << 8)
2371 ((temp_sata_addr_low >> 8)
2373 ((temp_sata_addr_low << 24)
2375 pm8001_dev->attached_phy +
2377 pm8001_dbg(pm8001_ha, FAIL,
2378 "SAS Address of IO Failure Drive:%08x%08x\n",
2380 temp_sata_addr_low);
2382 pm8001_dbg(pm8001_ha, FAIL,
2383 "SAS Address of IO Failure Drive:%016llx\n",
2384 SAS_ADDR(t->dev->sas_addr));
2389 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2391 ts->resp = SAS_TASK_COMPLETE;
2392 ts->stat = SAS_SAM_STAT_GOOD;
2393 /* check if response is for SEND READ LOG */
2395 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2396 /* set new bit for abort_all */
2397 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2398 /* clear bit for read log */
2399 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2400 pm8001_send_abort_all(pm8001_ha, pm8001_dev);
2402 pm8001_tag_free(pm8001_ha, tag);
2408 ts->resp = SAS_TASK_COMPLETE;
2409 ts->stat = SAS_PROTO_RESPONSE;
2410 ts->residual = param;
2411 pm8001_dbg(pm8001_ha, IO,
2412 "SAS_PROTO_RESPONSE len = %d\n",
2414 sata_resp = &psataPayload->sata_resp[0];
2415 resp = (struct ata_task_resp *)ts->buf;
2416 if (t->ata_task.dma_xfer == 0 &&
2417 t->data_dir == DMA_FROM_DEVICE) {
2418 len = sizeof(struct pio_setup_fis);
2419 pm8001_dbg(pm8001_ha, IO,
2420 "PIO read len = %d\n", len);
2421 } else if (t->ata_task.use_ncq) {
2422 len = sizeof(struct set_dev_bits_fis);
2423 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n",
2426 len = sizeof(struct dev_to_host_fis);
2427 pm8001_dbg(pm8001_ha, IO, "other len = %d\n",
2430 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2431 resp->frame_len = len;
2432 memcpy(&resp->ending_fis[0], sata_resp, len);
2433 ts->buf_valid_size = sizeof(*resp);
2435 pm8001_dbg(pm8001_ha, IO,
2436 "response too large\n");
2439 atomic_dec(&pm8001_dev->running_req);
2442 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
2443 ts->resp = SAS_TASK_COMPLETE;
2444 ts->stat = SAS_ABORTED_TASK;
2446 atomic_dec(&pm8001_dev->running_req);
2448 /* following cases are to do cases */
2450 /* SATA Completion with error */
2451 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param);
2452 ts->resp = SAS_TASK_COMPLETE;
2453 ts->stat = SAS_DATA_UNDERRUN;
2454 ts->residual = param;
2456 atomic_dec(&pm8001_dev->running_req);
2459 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2460 ts->resp = SAS_TASK_UNDELIVERED;
2461 ts->stat = SAS_PHY_DOWN;
2463 atomic_dec(&pm8001_dev->running_req);
2465 case IO_XFER_ERROR_BREAK:
2466 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2467 ts->resp = SAS_TASK_COMPLETE;
2468 ts->stat = SAS_INTERRUPTED;
2470 atomic_dec(&pm8001_dev->running_req);
2472 case IO_XFER_ERROR_PHY_NOT_READY:
2473 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2474 ts->resp = SAS_TASK_COMPLETE;
2475 ts->stat = SAS_OPEN_REJECT;
2476 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2478 atomic_dec(&pm8001_dev->running_req);
2480 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2481 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2482 ts->resp = SAS_TASK_COMPLETE;
2483 ts->stat = SAS_OPEN_REJECT;
2484 ts->open_rej_reason = SAS_OREJ_EPROTO;
2486 atomic_dec(&pm8001_dev->running_req);
2488 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2489 pm8001_dbg(pm8001_ha, IO,
2490 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2491 ts->resp = SAS_TASK_COMPLETE;
2492 ts->stat = SAS_OPEN_REJECT;
2493 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2495 atomic_dec(&pm8001_dev->running_req);
2497 case IO_OPEN_CNX_ERROR_BREAK:
2498 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2499 ts->resp = SAS_TASK_COMPLETE;
2500 ts->stat = SAS_OPEN_REJECT;
2501 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2503 atomic_dec(&pm8001_dev->running_req);
2505 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2506 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2507 ts->resp = SAS_TASK_COMPLETE;
2508 ts->stat = SAS_DEV_NO_RESPONSE;
2509 if (!t->uldd_task) {
2510 pm8001_handle_event(pm8001_ha,
2512 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2513 ts->resp = SAS_TASK_UNDELIVERED;
2514 ts->stat = SAS_QUEUE_FULL;
2515 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2519 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2520 pm8001_dbg(pm8001_ha, IO,
2521 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2522 ts->resp = SAS_TASK_UNDELIVERED;
2523 ts->stat = SAS_OPEN_REJECT;
2524 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2525 if (!t->uldd_task) {
2526 pm8001_handle_event(pm8001_ha,
2528 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2529 ts->resp = SAS_TASK_UNDELIVERED;
2530 ts->stat = SAS_QUEUE_FULL;
2531 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2535 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2536 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2537 ts->resp = SAS_TASK_COMPLETE;
2538 ts->stat = SAS_OPEN_REJECT;
2539 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2541 atomic_dec(&pm8001_dev->running_req);
2543 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2544 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n");
2545 ts->resp = SAS_TASK_COMPLETE;
2546 ts->stat = SAS_DEV_NO_RESPONSE;
2547 if (!t->uldd_task) {
2548 pm8001_handle_event(pm8001_ha,
2550 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2551 ts->resp = SAS_TASK_UNDELIVERED;
2552 ts->stat = SAS_QUEUE_FULL;
2553 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2557 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2558 pm8001_dbg(pm8001_ha, IO,
2559 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2560 ts->resp = SAS_TASK_COMPLETE;
2561 ts->stat = SAS_OPEN_REJECT;
2562 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2564 atomic_dec(&pm8001_dev->running_req);
2566 case IO_XFER_ERROR_NAK_RECEIVED:
2567 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2568 ts->resp = SAS_TASK_COMPLETE;
2569 ts->stat = SAS_NAK_R_ERR;
2571 atomic_dec(&pm8001_dev->running_req);
2573 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2574 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2575 ts->resp = SAS_TASK_COMPLETE;
2576 ts->stat = SAS_NAK_R_ERR;
2578 atomic_dec(&pm8001_dev->running_req);
2580 case IO_XFER_ERROR_DMA:
2581 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2582 ts->resp = SAS_TASK_COMPLETE;
2583 ts->stat = SAS_ABORTED_TASK;
2585 atomic_dec(&pm8001_dev->running_req);
2587 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2588 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n");
2589 ts->resp = SAS_TASK_UNDELIVERED;
2590 ts->stat = SAS_DEV_NO_RESPONSE;
2592 atomic_dec(&pm8001_dev->running_req);
2594 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2595 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2596 ts->resp = SAS_TASK_COMPLETE;
2597 ts->stat = SAS_DATA_UNDERRUN;
2599 atomic_dec(&pm8001_dev->running_req);
2601 case IO_XFER_OPEN_RETRY_TIMEOUT:
2602 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2603 ts->resp = SAS_TASK_COMPLETE;
2604 ts->stat = SAS_OPEN_TO;
2606 atomic_dec(&pm8001_dev->running_req);
2608 case IO_PORT_IN_RESET:
2609 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2610 ts->resp = SAS_TASK_COMPLETE;
2611 ts->stat = SAS_DEV_NO_RESPONSE;
2613 atomic_dec(&pm8001_dev->running_req);
2615 case IO_DS_NON_OPERATIONAL:
2616 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2617 ts->resp = SAS_TASK_COMPLETE;
2618 ts->stat = SAS_DEV_NO_RESPONSE;
2619 if (!t->uldd_task) {
2620 pm8001_handle_event(pm8001_ha, pm8001_dev,
2621 IO_DS_NON_OPERATIONAL);
2622 ts->resp = SAS_TASK_UNDELIVERED;
2623 ts->stat = SAS_QUEUE_FULL;
2624 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2628 case IO_DS_IN_RECOVERY:
2629 pm8001_dbg(pm8001_ha, IO, " IO_DS_IN_RECOVERY\n");
2630 ts->resp = SAS_TASK_COMPLETE;
2631 ts->stat = SAS_DEV_NO_RESPONSE;
2633 atomic_dec(&pm8001_dev->running_req);
2635 case IO_DS_IN_ERROR:
2636 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n");
2637 ts->resp = SAS_TASK_COMPLETE;
2638 ts->stat = SAS_DEV_NO_RESPONSE;
2639 if (!t->uldd_task) {
2640 pm8001_handle_event(pm8001_ha, pm8001_dev,
2642 ts->resp = SAS_TASK_UNDELIVERED;
2643 ts->stat = SAS_QUEUE_FULL;
2644 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2648 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2649 pm8001_dbg(pm8001_ha, IO,
2650 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2651 ts->resp = SAS_TASK_COMPLETE;
2652 ts->stat = SAS_OPEN_REJECT;
2653 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2655 atomic_dec(&pm8001_dev->running_req);
2658 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2659 /* not allowed case. Therefore, return failed status */
2660 ts->resp = SAS_TASK_COMPLETE;
2661 ts->stat = SAS_DEV_NO_RESPONSE;
2663 atomic_dec(&pm8001_dev->running_req);
2666 spin_lock_irqsave(&t->task_state_lock, flags);
2667 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2668 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2669 t->task_state_flags |= SAS_TASK_STATE_DONE;
2670 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2671 spin_unlock_irqrestore(&t->task_state_lock, flags);
2672 pm8001_dbg(pm8001_ha, FAIL,
2673 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2674 t, status, ts->resp, ts->stat);
2675 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2677 spin_unlock_irqrestore(&t->task_state_lock, flags);
2678 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2682 /*See the comments for mpi_ssp_completion */
2683 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2686 struct task_status_struct *ts;
2687 struct pm8001_ccb_info *ccb;
2688 struct pm8001_device *pm8001_dev;
2689 struct sata_event_resp *psataPayload =
2690 (struct sata_event_resp *)(piomb + 4);
2691 u32 event = le32_to_cpu(psataPayload->event);
2692 u32 tag = le32_to_cpu(psataPayload->tag);
2693 u32 port_id = le32_to_cpu(psataPayload->port_id);
2694 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2697 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);
2699 /* Check if this is NCQ error */
2700 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2701 /* find device using device id */
2702 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2703 /* send read log extension */
2705 pm8001_send_read_log(pm8001_ha, pm8001_dev);
2709 ccb = &pm8001_ha->ccb_info[tag];
2711 pm8001_dev = ccb->device;
2713 pm8001_dbg(pm8001_ha, FAIL, "sata IO status 0x%x\n", event);
2714 if (unlikely(!t || !t->lldd_task || !t->dev))
2716 ts = &t->task_status;
2717 pm8001_dbg(pm8001_ha, DEVIO,
2718 "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n",
2719 port_id, dev_id, tag, event);
2722 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2723 ts->resp = SAS_TASK_COMPLETE;
2724 ts->stat = SAS_DATA_OVERRUN;
2727 case IO_XFER_ERROR_BREAK:
2728 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2729 ts->resp = SAS_TASK_COMPLETE;
2730 ts->stat = SAS_INTERRUPTED;
2732 case IO_XFER_ERROR_PHY_NOT_READY:
2733 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2734 ts->resp = SAS_TASK_COMPLETE;
2735 ts->stat = SAS_OPEN_REJECT;
2736 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2738 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2739 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2740 ts->resp = SAS_TASK_COMPLETE;
2741 ts->stat = SAS_OPEN_REJECT;
2742 ts->open_rej_reason = SAS_OREJ_EPROTO;
2744 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2745 pm8001_dbg(pm8001_ha, IO,
2746 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2747 ts->resp = SAS_TASK_COMPLETE;
2748 ts->stat = SAS_OPEN_REJECT;
2749 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2751 case IO_OPEN_CNX_ERROR_BREAK:
2752 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2753 ts->resp = SAS_TASK_COMPLETE;
2754 ts->stat = SAS_OPEN_REJECT;
2755 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2757 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2758 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2759 ts->resp = SAS_TASK_UNDELIVERED;
2760 ts->stat = SAS_DEV_NO_RESPONSE;
2761 if (!t->uldd_task) {
2762 pm8001_handle_event(pm8001_ha,
2764 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2765 ts->resp = SAS_TASK_COMPLETE;
2766 ts->stat = SAS_QUEUE_FULL;
2770 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2771 pm8001_dbg(pm8001_ha, IO,
2772 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2773 ts->resp = SAS_TASK_UNDELIVERED;
2774 ts->stat = SAS_OPEN_REJECT;
2775 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2777 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2778 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2779 ts->resp = SAS_TASK_COMPLETE;
2780 ts->stat = SAS_OPEN_REJECT;
2781 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2783 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2784 pm8001_dbg(pm8001_ha, IO,
2785 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2786 ts->resp = SAS_TASK_COMPLETE;
2787 ts->stat = SAS_OPEN_REJECT;
2788 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2790 case IO_XFER_ERROR_NAK_RECEIVED:
2791 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2792 ts->resp = SAS_TASK_COMPLETE;
2793 ts->stat = SAS_NAK_R_ERR;
2795 case IO_XFER_ERROR_PEER_ABORTED:
2796 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n");
2797 ts->resp = SAS_TASK_COMPLETE;
2798 ts->stat = SAS_NAK_R_ERR;
2800 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2801 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2802 ts->resp = SAS_TASK_COMPLETE;
2803 ts->stat = SAS_DATA_UNDERRUN;
2805 case IO_XFER_OPEN_RETRY_TIMEOUT:
2806 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2807 ts->resp = SAS_TASK_COMPLETE;
2808 ts->stat = SAS_OPEN_TO;
2810 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2811 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2812 ts->resp = SAS_TASK_COMPLETE;
2813 ts->stat = SAS_OPEN_TO;
2815 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2816 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2817 ts->resp = SAS_TASK_COMPLETE;
2818 ts->stat = SAS_OPEN_TO;
2820 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2821 pm8001_dbg(pm8001_ha, IO,
2822 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2823 ts->resp = SAS_TASK_COMPLETE;
2824 ts->stat = SAS_OPEN_TO;
2826 case IO_XFER_ERROR_OFFSET_MISMATCH:
2827 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2828 ts->resp = SAS_TASK_COMPLETE;
2829 ts->stat = SAS_OPEN_TO;
2831 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2832 pm8001_dbg(pm8001_ha, IO,
2833 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2834 ts->resp = SAS_TASK_COMPLETE;
2835 ts->stat = SAS_OPEN_TO;
2837 case IO_XFER_CMD_FRAME_ISSUED:
2838 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2840 case IO_XFER_PIO_SETUP_ERROR:
2841 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n");
2842 ts->resp = SAS_TASK_COMPLETE;
2843 ts->stat = SAS_OPEN_TO;
2846 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2847 /* not allowed case. Therefore, return failed status */
2848 ts->resp = SAS_TASK_COMPLETE;
2849 ts->stat = SAS_OPEN_TO;
2854 /*See the comments for mpi_ssp_completion */
2856 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2859 struct pm8001_ccb_info *ccb;
2860 unsigned long flags;
2863 struct smp_completion_resp *psmpPayload;
2864 struct task_status_struct *ts;
2865 struct pm8001_device *pm8001_dev;
2867 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2868 status = le32_to_cpu(psmpPayload->status);
2869 tag = le32_to_cpu(psmpPayload->tag);
2871 ccb = &pm8001_ha->ccb_info[tag];
2873 ts = &t->task_status;
2874 pm8001_dev = ccb->device;
2876 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status);
2877 pm8001_dbg(pm8001_ha, IOERR,
2878 "status:0x%x, tag:0x%x, task:0x%p\n",
2881 if (unlikely(!t || !t->lldd_task || !t->dev))
2886 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2887 ts->resp = SAS_TASK_COMPLETE;
2888 ts->stat = SAS_SAM_STAT_GOOD;
2890 atomic_dec(&pm8001_dev->running_req);
2893 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n");
2894 ts->resp = SAS_TASK_COMPLETE;
2895 ts->stat = SAS_ABORTED_TASK;
2897 atomic_dec(&pm8001_dev->running_req);
2900 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2901 ts->resp = SAS_TASK_COMPLETE;
2902 ts->stat = SAS_DATA_OVERRUN;
2905 atomic_dec(&pm8001_dev->running_req);
2908 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2909 ts->resp = SAS_TASK_COMPLETE;
2910 ts->stat = SAS_PHY_DOWN;
2912 case IO_ERROR_HW_TIMEOUT:
2913 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n");
2914 ts->resp = SAS_TASK_COMPLETE;
2915 ts->stat = SAS_SAM_STAT_BUSY;
2917 case IO_XFER_ERROR_BREAK:
2918 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2919 ts->resp = SAS_TASK_COMPLETE;
2920 ts->stat = SAS_SAM_STAT_BUSY;
2922 case IO_XFER_ERROR_PHY_NOT_READY:
2923 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2924 ts->resp = SAS_TASK_COMPLETE;
2925 ts->stat = SAS_SAM_STAT_BUSY;
2927 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2928 pm8001_dbg(pm8001_ha, IO,
2929 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2930 ts->resp = SAS_TASK_COMPLETE;
2931 ts->stat = SAS_OPEN_REJECT;
2932 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2934 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2935 pm8001_dbg(pm8001_ha, IO,
2936 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2937 ts->resp = SAS_TASK_COMPLETE;
2938 ts->stat = SAS_OPEN_REJECT;
2939 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2941 case IO_OPEN_CNX_ERROR_BREAK:
2942 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2943 ts->resp = SAS_TASK_COMPLETE;
2944 ts->stat = SAS_OPEN_REJECT;
2945 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2947 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2948 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2949 ts->resp = SAS_TASK_COMPLETE;
2950 ts->stat = SAS_OPEN_REJECT;
2951 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2952 pm8001_handle_event(pm8001_ha,
2954 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2956 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2957 pm8001_dbg(pm8001_ha, IO,
2958 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2959 ts->resp = SAS_TASK_COMPLETE;
2960 ts->stat = SAS_OPEN_REJECT;
2961 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2963 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2964 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2965 ts->resp = SAS_TASK_COMPLETE;
2966 ts->stat = SAS_OPEN_REJECT;
2967 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2969 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2970 pm8001_dbg(pm8001_ha, IO,
2971 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2972 ts->resp = SAS_TASK_COMPLETE;
2973 ts->stat = SAS_OPEN_REJECT;
2974 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2976 case IO_XFER_ERROR_RX_FRAME:
2977 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n");
2978 ts->resp = SAS_TASK_COMPLETE;
2979 ts->stat = SAS_DEV_NO_RESPONSE;
2981 case IO_XFER_OPEN_RETRY_TIMEOUT:
2982 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2983 ts->resp = SAS_TASK_COMPLETE;
2984 ts->stat = SAS_OPEN_REJECT;
2985 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2987 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2988 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n");
2989 ts->resp = SAS_TASK_COMPLETE;
2990 ts->stat = SAS_QUEUE_FULL;
2992 case IO_PORT_IN_RESET:
2993 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2994 ts->resp = SAS_TASK_COMPLETE;
2995 ts->stat = SAS_OPEN_REJECT;
2996 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2998 case IO_DS_NON_OPERATIONAL:
2999 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
3000 ts->resp = SAS_TASK_COMPLETE;
3001 ts->stat = SAS_DEV_NO_RESPONSE;
3003 case IO_DS_IN_RECOVERY:
3004 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
3005 ts->resp = SAS_TASK_COMPLETE;
3006 ts->stat = SAS_OPEN_REJECT;
3007 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3009 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3010 pm8001_dbg(pm8001_ha, IO,
3011 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
3012 ts->resp = SAS_TASK_COMPLETE;
3013 ts->stat = SAS_OPEN_REJECT;
3014 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3017 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
3018 ts->resp = SAS_TASK_COMPLETE;
3019 ts->stat = SAS_DEV_NO_RESPONSE;
3020 /* not allowed case. Therefore, return failed status */
3023 spin_lock_irqsave(&t->task_state_lock, flags);
3024 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3025 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3026 t->task_state_flags |= SAS_TASK_STATE_DONE;
3027 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3028 spin_unlock_irqrestore(&t->task_state_lock, flags);
3029 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
3030 t, status, ts->resp, ts->stat);
3031 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3033 spin_unlock_irqrestore(&t->task_state_lock, flags);
3034 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3035 mb();/* in order to force CPU ordering */
3040 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
3043 struct set_dev_state_resp *pPayload =
3044 (struct set_dev_state_resp *)(piomb + 4);
3045 u32 tag = le32_to_cpu(pPayload->tag);
3046 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3047 struct pm8001_device *pm8001_dev = ccb->device;
3048 u32 status = le32_to_cpu(pPayload->status);
3049 u32 device_id = le32_to_cpu(pPayload->device_id);
3050 u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS;
3051 u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS;
3052 pm8001_dbg(pm8001_ha, MSG, "Set device id = 0x%x state from 0x%x to 0x%x status = 0x%x!\n",
3053 device_id, pds, nds, status);
3054 complete(pm8001_dev->setds_completion);
3056 ccb->ccb_tag = 0xFFFFFFFF;
3057 pm8001_tag_free(pm8001_ha, tag);
3060 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3062 struct get_nvm_data_resp *pPayload =
3063 (struct get_nvm_data_resp *)(piomb + 4);
3064 u32 tag = le32_to_cpu(pPayload->tag);
3065 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3066 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3067 complete(pm8001_ha->nvmd_completion);
3068 pm8001_dbg(pm8001_ha, MSG, "Set nvm data complete!\n");
3069 if ((dlen_status & NVMD_STAT) != 0) {
3070 pm8001_dbg(pm8001_ha, FAIL, "Set nvm data error %x\n",
3074 ccb->ccb_tag = 0xFFFFFFFF;
3075 pm8001_tag_free(pm8001_ha, tag);
3079 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3081 struct fw_control_ex *fw_control_context;
3082 struct get_nvm_data_resp *pPayload =
3083 (struct get_nvm_data_resp *)(piomb + 4);
3084 u32 tag = le32_to_cpu(pPayload->tag);
3085 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3086 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3087 u32 ir_tds_bn_dps_das_nvm =
3088 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
3089 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
3090 fw_control_context = ccb->fw_control_context;
3092 pm8001_dbg(pm8001_ha, MSG, "Get nvm data complete!\n");
3093 if ((dlen_status & NVMD_STAT) != 0) {
3094 pm8001_dbg(pm8001_ha, FAIL, "Get nvm data error %x\n",
3096 complete(pm8001_ha->nvmd_completion);
3097 /* We should free tag during failure also, the tag is not being
3098 * freed by requesting path anywhere.
3101 ccb->ccb_tag = 0xFFFFFFFF;
3102 pm8001_tag_free(pm8001_ha, tag);
3105 if (ir_tds_bn_dps_das_nvm & IPMode) {
3106 /* indirect mode - IR bit set */
3107 pm8001_dbg(pm8001_ha, MSG, "Get NVMD success, IR=1\n");
3108 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
3109 if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
3110 memcpy(pm8001_ha->sas_addr,
3111 ((u8 *)virt_addr + 4),
3113 pm8001_dbg(pm8001_ha, MSG, "Get SAS address from VPD successfully!\n");
3115 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
3116 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
3117 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
3119 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
3120 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
3123 /* Should not be happened*/
3124 pm8001_dbg(pm8001_ha, MSG,
3125 "(IR=1)Wrong Device type 0x%x\n",
3126 ir_tds_bn_dps_das_nvm);
3128 } else /* direct mode */{
3129 pm8001_dbg(pm8001_ha, MSG,
3130 "Get NVMD success, IR=0, dataLen=%d\n",
3131 (dlen_status & NVMD_LEN) >> 24);
3133 /* Though fw_control_context is freed below, usrAddr still needs
3134 * to be updated as this holds the response to the request function
3136 memcpy(fw_control_context->usrAddr,
3137 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
3138 fw_control_context->len);
3139 kfree(ccb->fw_control_context);
3140 /* To avoid race condition, complete should be
3141 * called after the message is copied to
3142 * fw_control_context->usrAddr
3144 complete(pm8001_ha->nvmd_completion);
3145 pm8001_dbg(pm8001_ha, MSG, "Get nvmd data complete!\n");
3147 ccb->ccb_tag = 0xFFFFFFFF;
3148 pm8001_tag_free(pm8001_ha, tag);
3151 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
3154 struct local_phy_ctl_resp *pPayload =
3155 (struct local_phy_ctl_resp *)(piomb + 4);
3156 u32 status = le32_to_cpu(pPayload->status);
3157 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
3158 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
3159 tag = le32_to_cpu(pPayload->tag);
3161 pm8001_dbg(pm8001_ha, MSG,
3162 "%x phy execute %x phy op failed!\n",
3165 pm8001_dbg(pm8001_ha, MSG,
3166 "%x phy execute %x phy op success!\n",
3168 pm8001_ha->phy[phy_id].reset_success = true;
3170 if (pm8001_ha->phy[phy_id].enable_completion) {
3171 complete(pm8001_ha->phy[phy_id].enable_completion);
3172 pm8001_ha->phy[phy_id].enable_completion = NULL;
3174 pm8001_tag_free(pm8001_ha, tag);
3179 * pm8001_bytes_dmaed - one of the interface function communication with libsas
3180 * @pm8001_ha: our hba card information
3181 * @i: which phy that received the event.
3183 * when HBA driver received the identify done event or initiate FIS received
3184 * event(for SATA), it will invoke this function to notify the sas layer that
3185 * the sas toplogy has formed, please discover the the whole sas domain,
3186 * while receive a broadcast(change) primitive just tell the sas
3187 * layer to discover the changed domain rather than the whole domain.
3189 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
3191 struct pm8001_phy *phy = &pm8001_ha->phy[i];
3192 struct asd_sas_phy *sas_phy = &phy->sas_phy;
3193 if (!phy->phy_attached)
3197 struct sas_phy *sphy = sas_phy->phy;
3198 sphy->negotiated_linkrate = sas_phy->linkrate;
3199 sphy->minimum_linkrate = phy->minimum_linkrate;
3200 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3201 sphy->maximum_linkrate = phy->maximum_linkrate;
3202 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
3205 if (phy->phy_type & PORT_TYPE_SAS) {
3206 struct sas_identify_frame *id;
3207 id = (struct sas_identify_frame *)phy->frame_rcvd;
3208 id->dev_type = phy->identify.device_type;
3209 id->initiator_bits = SAS_PROTOCOL_ALL;
3210 id->target_bits = phy->identify.target_port_protocols;
3211 } else if (phy->phy_type & PORT_TYPE_SATA) {
3214 pm8001_dbg(pm8001_ha, MSG, "phy %d byte dmaded.\n", i);
3216 sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
3217 sas_notify_port_event(sas_phy, PORTE_BYTES_DMAED, GFP_ATOMIC);
3220 /* Get the link rate speed */
3221 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
3223 struct sas_phy *sas_phy = phy->sas_phy.phy;
3225 switch (link_rate) {
3227 phy->sas_phy.linkrate = SAS_LINK_RATE_12_0_GBPS;
3228 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_12_0_GBPS;
3231 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
3232 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
3235 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3236 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
3239 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3240 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
3243 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3244 sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
3245 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3246 sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
3247 sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
3251 * pm8001_get_attached_sas_addr - extract/generate attached SAS address
3252 * @phy: pointer to asd_phy
3253 * @sas_addr: pointer to buffer where the SAS address is to be written
3255 * This function extracts the SAS address from an IDENTIFY frame
3256 * received. If OOB is SATA, then a SAS address is generated from the
3259 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3262 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
3265 if (phy->sas_phy.frame_rcvd[0] == 0x34
3266 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3267 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3268 /* FIS device-to-host */
3269 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3270 addr += phy->sas_phy.id;
3271 *(__be64 *)sas_addr = cpu_to_be64(addr);
3273 struct sas_identify_frame *idframe =
3274 (void *) phy->sas_phy.frame_rcvd;
3275 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3280 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3281 * @pm8001_ha: our hba card information
3282 * @Qnum: the outbound queue message number.
3283 * @SEA: source of event to ack
3284 * @port_id: port id.
3286 * @param0: parameter 0.
3287 * @param1: parameter 1.
3289 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3290 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3292 struct hw_event_ack_req payload;
3293 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3295 struct inbound_queue_table *circularQ;
3297 memset((u8 *)&payload, 0, sizeof(payload));
3298 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3299 payload.tag = cpu_to_le32(1);
3300 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3301 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
3302 payload.param0 = cpu_to_le32(param0);
3303 payload.param1 = cpu_to_le32(param1);
3304 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
3305 sizeof(payload), 0);
3308 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3309 u32 phyId, u32 phy_op);
3312 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3313 * @pm8001_ha: our hba card information
3314 * @piomb: IO message buffer
3317 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3319 struct hw_event_resp *pPayload =
3320 (struct hw_event_resp *)(piomb + 4);
3321 u32 lr_evt_status_phyid_portid =
3322 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3324 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3325 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3327 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3328 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3329 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3330 struct pm8001_port *port = &pm8001_ha->port[port_id];
3331 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3332 unsigned long flags;
3333 u8 deviceType = pPayload->sas_identify.dev_type;
3335 port->port_id = port_id;
3336 port->port_state = portstate;
3337 phy->phy_state = PHY_STATE_LINK_UP_SPC;
3338 pm8001_dbg(pm8001_ha, MSG,
3339 "HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3342 switch (deviceType) {
3343 case SAS_PHY_UNUSED:
3344 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n");
3346 case SAS_END_DEVICE:
3347 pm8001_dbg(pm8001_ha, MSG, "end device.\n");
3348 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3349 PHY_NOTIFY_ENABLE_SPINUP);
3350 port->port_attached = 1;
3351 pm8001_get_lrate_mode(phy, link_rate);
3353 case SAS_EDGE_EXPANDER_DEVICE:
3354 pm8001_dbg(pm8001_ha, MSG, "expander device.\n");
3355 port->port_attached = 1;
3356 pm8001_get_lrate_mode(phy, link_rate);
3358 case SAS_FANOUT_EXPANDER_DEVICE:
3359 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n");
3360 port->port_attached = 1;
3361 pm8001_get_lrate_mode(phy, link_rate);
3364 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n",
3368 phy->phy_type |= PORT_TYPE_SAS;
3369 phy->identify.device_type = deviceType;
3370 phy->phy_attached = 1;
3371 if (phy->identify.device_type == SAS_END_DEVICE)
3372 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3373 else if (phy->identify.device_type != SAS_PHY_UNUSED)
3374 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3375 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3376 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3377 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3378 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3379 sizeof(struct sas_identify_frame)-4);
3380 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3381 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3382 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3383 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3384 mdelay(200);/*delay a moment to wait disk to spinup*/
3385 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3389 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3390 * @pm8001_ha: our hba card information
3391 * @piomb: IO message buffer
3394 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3396 struct hw_event_resp *pPayload =
3397 (struct hw_event_resp *)(piomb + 4);
3398 u32 lr_evt_status_phyid_portid =
3399 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3401 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3402 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3404 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3405 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3406 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3407 struct pm8001_port *port = &pm8001_ha->port[port_id];
3408 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3409 unsigned long flags;
3410 pm8001_dbg(pm8001_ha, DEVIO, "HW_EVENT_SATA_PHY_UP port id = %d, phy id = %d\n",
3413 port->port_id = port_id;
3414 port->port_state = portstate;
3415 phy->phy_state = PHY_STATE_LINK_UP_SPC;
3416 port->port_attached = 1;
3417 pm8001_get_lrate_mode(phy, link_rate);
3418 phy->phy_type |= PORT_TYPE_SATA;
3419 phy->phy_attached = 1;
3420 phy->sas_phy.oob_mode = SATA_OOB_MODE;
3421 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3422 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3423 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3424 sizeof(struct dev_to_host_fis));
3425 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3426 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3427 phy->identify.device_type = SAS_SATA_DEV;
3428 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3429 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3430 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3434 * hw_event_phy_down -we should notify the libsas the phy is down.
3435 * @pm8001_ha: our hba card information
3436 * @piomb: IO message buffer
3439 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3441 struct hw_event_resp *pPayload =
3442 (struct hw_event_resp *)(piomb + 4);
3443 u32 lr_evt_status_phyid_portid =
3444 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3445 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3447 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3448 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3449 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3450 struct pm8001_port *port = &pm8001_ha->port[port_id];
3451 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3452 port->port_state = portstate;
3454 phy->identify.device_type = 0;
3455 phy->phy_attached = 0;
3456 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3457 switch (portstate) {
3461 pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n",
3463 pm8001_dbg(pm8001_ha, MSG,
3464 " Last phy Down and port invalid\n");
3465 port->port_attached = 0;
3466 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3467 port_id, phy_id, 0, 0);
3470 pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n",
3473 case PORT_NOT_ESTABLISHED:
3474 pm8001_dbg(pm8001_ha, MSG,
3475 " phy Down and PORT_NOT_ESTABLISHED\n");
3476 port->port_attached = 0;
3479 pm8001_dbg(pm8001_ha, MSG, " phy Down and PORT_LOSTCOMM\n");
3480 pm8001_dbg(pm8001_ha, MSG,
3481 " Last phy Down and port invalid\n");
3482 port->port_attached = 0;
3483 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3484 port_id, phy_id, 0, 0);
3487 port->port_attached = 0;
3488 pm8001_dbg(pm8001_ha, DEVIO, " phy Down and(default) = %x\n",
3496 * pm8001_mpi_reg_resp -process register device ID response.
3497 * @pm8001_ha: our hba card information
3498 * @piomb: IO message buffer
3500 * when sas layer find a device it will notify LLDD, then the driver register
3501 * the domain device to FW, this event is the return device ID which the FW
3502 * has assigned, from now, inter-communication with FW is no longer using the
3503 * SAS address, use device ID which FW assigned.
3505 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3510 struct pm8001_ccb_info *ccb;
3511 struct pm8001_device *pm8001_dev;
3512 struct dev_reg_resp *registerRespPayload =
3513 (struct dev_reg_resp *)(piomb + 4);
3515 htag = le32_to_cpu(registerRespPayload->tag);
3516 ccb = &pm8001_ha->ccb_info[htag];
3517 pm8001_dev = ccb->device;
3518 status = le32_to_cpu(registerRespPayload->status);
3519 device_id = le32_to_cpu(registerRespPayload->device_id);
3520 pm8001_dbg(pm8001_ha, MSG, " register device is status = %d\n",
3523 case DEVREG_SUCCESS:
3524 pm8001_dbg(pm8001_ha, MSG, "DEVREG_SUCCESS\n");
3525 pm8001_dev->device_id = device_id;
3527 case DEVREG_FAILURE_OUT_OF_RESOURCE:
3528 pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_OUT_OF_RESOURCE\n");
3530 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3531 pm8001_dbg(pm8001_ha, MSG,
3532 "DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n");
3534 case DEVREG_FAILURE_INVALID_PHY_ID:
3535 pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_INVALID_PHY_ID\n");
3537 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3538 pm8001_dbg(pm8001_ha, MSG,
3539 "DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n");
3541 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3542 pm8001_dbg(pm8001_ha, MSG,
3543 "DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n");
3545 case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3546 pm8001_dbg(pm8001_ha, MSG,
3547 "DEVREG_FAILURE_PORT_NOT_VALID_STATE\n");
3549 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3550 pm8001_dbg(pm8001_ha, MSG,
3551 "DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n");
3554 pm8001_dbg(pm8001_ha, MSG,
3555 "DEVREG_FAILURE_DEVICE_TYPE_NOT_SUPPORTED\n");
3558 complete(pm8001_dev->dcompletion);
3560 ccb->ccb_tag = 0xFFFFFFFF;
3561 pm8001_tag_free(pm8001_ha, htag);
3565 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3569 struct dev_reg_resp *registerRespPayload =
3570 (struct dev_reg_resp *)(piomb + 4);
3572 status = le32_to_cpu(registerRespPayload->status);
3573 device_id = le32_to_cpu(registerRespPayload->device_id);
3575 pm8001_dbg(pm8001_ha, MSG,
3576 " deregister device failed ,status = %x, device_id = %x\n",
3582 * pm8001_mpi_fw_flash_update_resp - Response from FW for flash update command.
3583 * @pm8001_ha: our hba card information
3584 * @piomb: IO message buffer
3586 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
3590 struct fw_flash_Update_resp *ppayload =
3591 (struct fw_flash_Update_resp *)(piomb + 4);
3592 u32 tag = le32_to_cpu(ppayload->tag);
3593 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3594 status = le32_to_cpu(ppayload->status);
3596 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3597 pm8001_dbg(pm8001_ha, MSG,
3598 ": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n");
3600 case FLASH_UPDATE_IN_PROGRESS:
3601 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_IN_PROGRESS\n");
3603 case FLASH_UPDATE_HDR_ERR:
3604 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HDR_ERR\n");
3606 case FLASH_UPDATE_OFFSET_ERR:
3607 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_OFFSET_ERR\n");
3609 case FLASH_UPDATE_CRC_ERR:
3610 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_CRC_ERR\n");
3612 case FLASH_UPDATE_LENGTH_ERR:
3613 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_LENGTH_ERR\n");
3615 case FLASH_UPDATE_HW_ERR:
3616 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HW_ERR\n");
3618 case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3619 pm8001_dbg(pm8001_ha, MSG,
3620 ": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n");
3622 case FLASH_UPDATE_DISABLED:
3623 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_DISABLED\n");
3626 pm8001_dbg(pm8001_ha, DEVIO, "No matched status = %d\n",
3630 kfree(ccb->fw_control_context);
3632 ccb->ccb_tag = 0xFFFFFFFF;
3633 pm8001_tag_free(pm8001_ha, tag);
3634 complete(pm8001_ha->nvmd_completion);
3638 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3642 struct general_event_resp *pPayload =
3643 (struct general_event_resp *)(piomb + 4);
3644 status = le32_to_cpu(pPayload->status);
3645 pm8001_dbg(pm8001_ha, MSG, " status = 0x%x\n", status);
3646 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3647 pm8001_dbg(pm8001_ha, MSG, "inb_IOMB_payload[0x%x] 0x%x,\n",
3649 pPayload->inb_IOMB_payload[i]);
3653 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3656 struct pm8001_ccb_info *ccb;
3657 unsigned long flags;
3660 struct task_status_struct *ts;
3661 struct pm8001_device *pm8001_dev;
3663 struct task_abort_resp *pPayload =
3664 (struct task_abort_resp *)(piomb + 4);
3666 status = le32_to_cpu(pPayload->status);
3667 tag = le32_to_cpu(pPayload->tag);
3669 pm8001_dbg(pm8001_ha, FAIL, " TAG NULL. RETURNING !!!\n");
3673 scp = le32_to_cpu(pPayload->scp);
3674 ccb = &pm8001_ha->ccb_info[tag];
3676 pm8001_dev = ccb->device; /* retrieve device */
3679 pm8001_dbg(pm8001_ha, FAIL, " TASK NULL. RETURNING !!!\n");
3682 ts = &t->task_status;
3684 pm8001_dbg(pm8001_ha, FAIL, "task abort failed status 0x%x ,tag = 0x%x, scp= 0x%x\n",
3688 pm8001_dbg(pm8001_ha, EH, "IO_SUCCESS\n");
3689 ts->resp = SAS_TASK_COMPLETE;
3690 ts->stat = SAS_SAM_STAT_GOOD;
3693 pm8001_dbg(pm8001_ha, EH, "IO_NOT_VALID\n");
3694 ts->resp = TMF_RESP_FUNC_FAILED;
3697 spin_lock_irqsave(&t->task_state_lock, flags);
3698 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3699 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3700 t->task_state_flags |= SAS_TASK_STATE_DONE;
3701 spin_unlock_irqrestore(&t->task_state_lock, flags);
3702 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3705 if (pm8001_dev->id & NCQ_ABORT_ALL_FLAG) {
3706 pm8001_tag_free(pm8001_ha, tag);
3708 /* clear the flag */
3709 pm8001_dev->id &= 0xBFFFFFFF;
3717 * mpi_hw_event -The hw event has come.
3718 * @pm8001_ha: our hba card information
3719 * @piomb: IO message buffer
3721 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3723 unsigned long flags;
3724 struct hw_event_resp *pPayload =
3725 (struct hw_event_resp *)(piomb + 4);
3726 u32 lr_evt_status_phyid_portid =
3727 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3728 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3730 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3732 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3734 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3735 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3736 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3737 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3738 pm8001_dbg(pm8001_ha, DEVIO,
3739 "SPC HW event for portid:%d, phyid:%d, event:%x, status:%x\n",
3740 port_id, phy_id, eventType, status);
3741 switch (eventType) {
3742 case HW_EVENT_PHY_START_STATUS:
3743 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS status = %x\n",
3748 if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3749 phy->enable_completion != NULL) {
3750 complete(phy->enable_completion);
3751 phy->enable_completion = NULL;
3754 case HW_EVENT_SAS_PHY_UP:
3755 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n");
3756 hw_event_sas_phy_up(pm8001_ha, piomb);
3758 case HW_EVENT_SATA_PHY_UP:
3759 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n");
3760 hw_event_sata_phy_up(pm8001_ha, piomb);
3762 case HW_EVENT_PHY_STOP_STATUS:
3763 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_STOP_STATUS status = %x\n",
3768 case HW_EVENT_SATA_SPINUP_HOLD:
3769 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n");
3770 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD,
3773 case HW_EVENT_PHY_DOWN:
3774 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n");
3775 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL,
3777 phy->phy_attached = 0;
3779 hw_event_phy_down(pm8001_ha, piomb);
3781 case HW_EVENT_PORT_INVALID:
3782 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n");
3783 sas_phy_disconnected(sas_phy);
3784 phy->phy_attached = 0;
3785 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3788 /* the broadcast change primitive received, tell the LIBSAS this event
3789 to revalidate the sas domain*/
3790 case HW_EVENT_BROADCAST_CHANGE:
3791 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n");
3792 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3793 port_id, phy_id, 1, 0);
3794 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3795 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3796 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3797 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3800 case HW_EVENT_PHY_ERROR:
3801 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n");
3802 sas_phy_disconnected(&phy->sas_phy);
3803 phy->phy_attached = 0;
3804 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC);
3806 case HW_EVENT_BROADCAST_EXP:
3807 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n");
3808 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3809 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3810 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3811 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3814 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3815 pm8001_dbg(pm8001_ha, MSG,
3816 "HW_EVENT_LINK_ERR_INVALID_DWORD\n");
3817 pm8001_hw_event_ack_req(pm8001_ha, 0,
3818 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3819 sas_phy_disconnected(sas_phy);
3820 phy->phy_attached = 0;
3821 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3824 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3825 pm8001_dbg(pm8001_ha, MSG,
3826 "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n");
3827 pm8001_hw_event_ack_req(pm8001_ha, 0,
3828 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3829 port_id, phy_id, 0, 0);
3830 sas_phy_disconnected(sas_phy);
3831 phy->phy_attached = 0;
3832 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3835 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3836 pm8001_dbg(pm8001_ha, MSG,
3837 "HW_EVENT_LINK_ERR_CODE_VIOLATION\n");
3838 pm8001_hw_event_ack_req(pm8001_ha, 0,
3839 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3840 port_id, phy_id, 0, 0);
3841 sas_phy_disconnected(sas_phy);
3842 phy->phy_attached = 0;
3843 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3846 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3847 pm8001_dbg(pm8001_ha, MSG,
3848 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n");
3849 pm8001_hw_event_ack_req(pm8001_ha, 0,
3850 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3851 port_id, phy_id, 0, 0);
3852 sas_phy_disconnected(sas_phy);
3853 phy->phy_attached = 0;
3854 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3857 case HW_EVENT_MALFUNCTION:
3858 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n");
3860 case HW_EVENT_BROADCAST_SES:
3861 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n");
3862 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3863 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3864 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3865 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3868 case HW_EVENT_INBOUND_CRC_ERROR:
3869 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n");
3870 pm8001_hw_event_ack_req(pm8001_ha, 0,
3871 HW_EVENT_INBOUND_CRC_ERROR,
3872 port_id, phy_id, 0, 0);
3874 case HW_EVENT_HARD_RESET_RECEIVED:
3875 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n");
3876 sas_notify_port_event(sas_phy, PORTE_HARD_RESET, GFP_ATOMIC);
3878 case HW_EVENT_ID_FRAME_TIMEOUT:
3879 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n");
3880 sas_phy_disconnected(sas_phy);
3881 phy->phy_attached = 0;
3882 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3885 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3886 pm8001_dbg(pm8001_ha, MSG,
3887 "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n");
3888 pm8001_hw_event_ack_req(pm8001_ha, 0,
3889 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3890 port_id, phy_id, 0, 0);
3891 sas_phy_disconnected(sas_phy);
3892 phy->phy_attached = 0;
3893 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3896 case HW_EVENT_PORT_RESET_TIMER_TMO:
3897 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n");
3898 sas_phy_disconnected(sas_phy);
3899 phy->phy_attached = 0;
3900 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3903 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3904 pm8001_dbg(pm8001_ha, MSG,
3905 "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n");
3906 sas_phy_disconnected(sas_phy);
3907 phy->phy_attached = 0;
3908 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3911 case HW_EVENT_PORT_RECOVER:
3912 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n");
3914 case HW_EVENT_PORT_RESET_COMPLETE:
3915 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n");
3917 case EVENT_BROADCAST_ASYNCH_EVENT:
3918 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n");
3921 pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type = %x\n",
3929 * process_one_iomb - process one outbound Queue memory block
3930 * @pm8001_ha: our hba card information
3931 * @piomb: IO message buffer
3933 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3935 __le32 pHeader = *(__le32 *)piomb;
3936 u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
3938 pm8001_dbg(pm8001_ha, MSG, "process_one_iomb:\n");
3942 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n");
3944 case OPC_OUB_HW_EVENT:
3945 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n");
3946 mpi_hw_event(pm8001_ha, piomb);
3948 case OPC_OUB_SSP_COMP:
3949 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n");
3950 mpi_ssp_completion(pm8001_ha, piomb);
3952 case OPC_OUB_SMP_COMP:
3953 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n");
3954 mpi_smp_completion(pm8001_ha, piomb);
3956 case OPC_OUB_LOCAL_PHY_CNTRL:
3957 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n");
3958 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3960 case OPC_OUB_DEV_REGIST:
3961 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n");
3962 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3964 case OPC_OUB_DEREG_DEV:
3965 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n");
3966 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3968 case OPC_OUB_GET_DEV_HANDLE:
3969 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n");
3971 case OPC_OUB_SATA_COMP:
3972 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n");
3973 mpi_sata_completion(pm8001_ha, piomb);
3975 case OPC_OUB_SATA_EVENT:
3976 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n");
3977 mpi_sata_event(pm8001_ha, piomb);
3979 case OPC_OUB_SSP_EVENT:
3980 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n");
3981 mpi_ssp_event(pm8001_ha, piomb);
3983 case OPC_OUB_DEV_HANDLE_ARRIV:
3984 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n");
3985 /*This is for target*/
3987 case OPC_OUB_SSP_RECV_EVENT:
3988 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n");
3989 /*This is for target*/
3991 case OPC_OUB_DEV_INFO:
3992 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_INFO\n");
3994 case OPC_OUB_FW_FLASH_UPDATE:
3995 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n");
3996 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3998 case OPC_OUB_GPIO_RESPONSE:
3999 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n");
4001 case OPC_OUB_GPIO_EVENT:
4002 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n");
4004 case OPC_OUB_GENERAL_EVENT:
4005 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n");
4006 pm8001_mpi_general_event(pm8001_ha, piomb);
4008 case OPC_OUB_SSP_ABORT_RSP:
4009 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n");
4010 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4012 case OPC_OUB_SATA_ABORT_RSP:
4013 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n");
4014 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4016 case OPC_OUB_SAS_DIAG_MODE_START_END:
4017 pm8001_dbg(pm8001_ha, MSG,
4018 "OPC_OUB_SAS_DIAG_MODE_START_END\n");
4020 case OPC_OUB_SAS_DIAG_EXECUTE:
4021 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n");
4023 case OPC_OUB_GET_TIME_STAMP:
4024 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n");
4026 case OPC_OUB_SAS_HW_EVENT_ACK:
4027 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n");
4029 case OPC_OUB_PORT_CONTROL:
4030 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n");
4032 case OPC_OUB_SMP_ABORT_RSP:
4033 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n");
4034 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4036 case OPC_OUB_GET_NVMD_DATA:
4037 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n");
4038 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
4040 case OPC_OUB_SET_NVMD_DATA:
4041 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n");
4042 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
4044 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
4045 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n");
4047 case OPC_OUB_SET_DEVICE_STATE:
4048 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n");
4049 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
4051 case OPC_OUB_GET_DEVICE_STATE:
4052 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n");
4054 case OPC_OUB_SET_DEV_INFO:
4055 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n");
4057 case OPC_OUB_SAS_RE_INITIALIZE:
4058 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_RE_INITIALIZE\n");
4061 pm8001_dbg(pm8001_ha, DEVIO,
4062 "Unknown outbound Queue IOMB OPC = %x\n",
4068 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4070 struct outbound_queue_table *circularQ;
4073 u32 ret = MPI_IO_STATUS_FAIL;
4074 unsigned long flags;
4076 spin_lock_irqsave(&pm8001_ha->lock, flags);
4077 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4079 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4080 if (MPI_IO_STATUS_SUCCESS == ret) {
4081 /* process the outbound message */
4082 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
4083 /* free the message from the outbound circular buffer */
4084 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4087 if (MPI_IO_STATUS_BUSY == ret) {
4088 /* Update the producer index from SPC */
4089 circularQ->producer_index =
4090 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4091 if (le32_to_cpu(circularQ->producer_index) ==
4092 circularQ->consumer_idx)
4097 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4101 /* DMA_... to our direction translation. */
4102 static const u8 data_dir_flags[] = {
4103 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
4104 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */
4105 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */
4106 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */
4109 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
4112 struct scatterlist *sg;
4113 struct pm8001_prd *buf_prd = prd;
4115 for_each_sg(scatter, sg, nr, i) {
4116 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
4117 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
4118 buf_prd->im_len.e = 0;
4123 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
4125 psmp_cmd->tag = hTag;
4126 psmp_cmd->device_id = cpu_to_le32(deviceID);
4127 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4131 * pm8001_chip_smp_req - send a SMP task to FW
4132 * @pm8001_ha: our hba card information.
4133 * @ccb: the ccb information this request used.
4135 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4136 struct pm8001_ccb_info *ccb)
4139 struct sas_task *task = ccb->task;
4140 struct domain_device *dev = task->dev;
4141 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4142 struct scatterlist *sg_req, *sg_resp;
4143 u32 req_len, resp_len;
4144 struct smp_req smp_cmd;
4146 struct inbound_queue_table *circularQ;
4148 memset(&smp_cmd, 0, sizeof(smp_cmd));
4150 * DMA-map SMP request, response buffers
4152 sg_req = &task->smp_task.smp_req;
4153 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4156 req_len = sg_dma_len(sg_req);
4158 sg_resp = &task->smp_task.smp_resp;
4159 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4164 resp_len = sg_dma_len(sg_resp);
4165 /* must be in dwords */
4166 if ((req_len & 0x3) || (resp_len & 0x3)) {
4171 opc = OPC_INB_SMP_REQUEST;
4172 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4173 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4174 smp_cmd.long_smp_req.long_req_addr =
4175 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4176 smp_cmd.long_smp_req.long_req_size =
4177 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4178 smp_cmd.long_smp_req.long_resp_addr =
4179 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
4180 smp_cmd.long_smp_req.long_resp_size =
4181 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4182 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
4183 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4184 &smp_cmd, sizeof(smp_cmd), 0);
4191 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4194 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4200 * pm8001_chip_ssp_io_req - send a SSP task to FW
4201 * @pm8001_ha: our hba card information.
4202 * @ccb: the ccb information this request used.
4204 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4205 struct pm8001_ccb_info *ccb)
4207 struct sas_task *task = ccb->task;
4208 struct domain_device *dev = task->dev;
4209 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4210 struct ssp_ini_io_start_req ssp_cmd;
4211 u32 tag = ccb->ccb_tag;
4214 struct inbound_queue_table *circularQ;
4215 u32 opc = OPC_INB_SSPINIIOSTART;
4216 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4217 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4219 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
4220 SAS 1.1 compatible TLR*/
4221 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4222 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4223 ssp_cmd.tag = cpu_to_le32(tag);
4224 if (task->ssp_task.enable_first_burst)
4225 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4226 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4227 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4228 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4229 task->ssp_task.cmd->cmd_len);
4230 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4232 /* fill in PRD (scatter/gather) table, if any */
4233 if (task->num_scatter > 1) {
4234 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4235 phys_addr = ccb->ccb_dma_handle;
4236 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
4237 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
4238 ssp_cmd.esgl = cpu_to_le32(1<<31);
4239 } else if (task->num_scatter == 1) {
4240 u64 dma_addr = sg_dma_address(task->scatter);
4241 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4242 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
4243 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4245 } else if (task->num_scatter == 0) {
4246 ssp_cmd.addr_low = 0;
4247 ssp_cmd.addr_high = 0;
4248 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4251 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd,
4252 sizeof(ssp_cmd), 0);
4256 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4257 struct pm8001_ccb_info *ccb)
4259 struct sas_task *task = ccb->task;
4260 struct domain_device *dev = task->dev;
4261 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4262 u32 tag = ccb->ccb_tag;
4264 struct sata_start_req sata_cmd;
4265 u32 hdr_tag, ncg_tag = 0;
4269 struct inbound_queue_table *circularQ;
4270 unsigned long flags;
4271 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4272 memset(&sata_cmd, 0, sizeof(sata_cmd));
4273 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4274 if (task->data_dir == DMA_NONE) {
4275 ATAP = 0x04; /* no data*/
4276 pm8001_dbg(pm8001_ha, IO, "no data\n");
4277 } else if (likely(!task->ata_task.device_control_reg_update)) {
4278 if (task->ata_task.dma_xfer) {
4279 ATAP = 0x06; /* DMA */
4280 pm8001_dbg(pm8001_ha, IO, "DMA\n");
4282 ATAP = 0x05; /* PIO*/
4283 pm8001_dbg(pm8001_ha, IO, "PIO\n");
4285 if (task->ata_task.use_ncq &&
4286 dev->sata_dev.class != ATA_DEV_ATAPI) {
4287 ATAP = 0x07; /* FPDMA */
4288 pm8001_dbg(pm8001_ha, IO, "FPDMA\n");
4291 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4292 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4295 dir = data_dir_flags[task->data_dir] << 8;
4296 sata_cmd.tag = cpu_to_le32(tag);
4297 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4298 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4299 sata_cmd.ncqtag_atap_dir_m =
4300 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
4301 sata_cmd.sata_fis = task->ata_task.fis;
4302 if (likely(!task->ata_task.device_control_reg_update))
4303 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4304 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4305 /* fill in PRD (scatter/gather) table, if any */
4306 if (task->num_scatter > 1) {
4307 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4308 phys_addr = ccb->ccb_dma_handle;
4309 sata_cmd.addr_low = lower_32_bits(phys_addr);
4310 sata_cmd.addr_high = upper_32_bits(phys_addr);
4311 sata_cmd.esgl = cpu_to_le32(1 << 31);
4312 } else if (task->num_scatter == 1) {
4313 u64 dma_addr = sg_dma_address(task->scatter);
4314 sata_cmd.addr_low = lower_32_bits(dma_addr);
4315 sata_cmd.addr_high = upper_32_bits(dma_addr);
4316 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4318 } else if (task->num_scatter == 0) {
4319 sata_cmd.addr_low = 0;
4320 sata_cmd.addr_high = 0;
4321 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4325 /* Check for read log for failed drive and return */
4326 if (sata_cmd.sata_fis.command == 0x2f) {
4327 if (((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4328 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4329 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4330 struct task_status_struct *ts;
4332 pm8001_ha_dev->id &= 0xDFFFFFFF;
4333 ts = &task->task_status;
4335 spin_lock_irqsave(&task->task_state_lock, flags);
4336 ts->resp = SAS_TASK_COMPLETE;
4337 ts->stat = SAS_SAM_STAT_GOOD;
4338 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4339 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4340 task->task_state_flags |= SAS_TASK_STATE_DONE;
4341 if (unlikely((task->task_state_flags &
4342 SAS_TASK_STATE_ABORTED))) {
4343 spin_unlock_irqrestore(&task->task_state_lock,
4345 pm8001_dbg(pm8001_ha, FAIL,
4346 "task 0x%p resp 0x%x stat 0x%x but aborted by upper layer\n",
4349 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4351 spin_unlock_irqrestore(&task->task_state_lock,
4353 pm8001_ccb_task_free_done(pm8001_ha, task,
4360 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
4361 sizeof(sata_cmd), 0);
4366 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4367 * @pm8001_ha: our hba card information.
4368 * @phy_id: the phy id which we wanted to start up.
4371 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4373 struct phy_start_req payload;
4374 struct inbound_queue_table *circularQ;
4377 u32 opcode = OPC_INB_PHYSTART;
4378 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4379 memset(&payload, 0, sizeof(payload));
4380 payload.tag = cpu_to_le32(tag);
4382 ** [0:7] PHY Identifier
4383 ** [8:11] link rate 1.5G, 3G, 6G
4384 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4385 ** [14] 0b disable spin up hold; 1b enable spin up hold
4387 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4388 LINKMODE_AUTO | LINKRATE_15 |
4389 LINKRATE_30 | LINKRATE_60 | phy_id);
4390 payload.sas_identify.dev_type = SAS_END_DEVICE;
4391 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4392 memcpy(payload.sas_identify.sas_addr,
4393 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4394 payload.sas_identify.phy_id = phy_id;
4395 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4396 sizeof(payload), 0);
4401 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4402 * @pm8001_ha: our hba card information.
4403 * @phy_id: the phy id which we wanted to start up.
4405 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4408 struct phy_stop_req payload;
4409 struct inbound_queue_table *circularQ;
4412 u32 opcode = OPC_INB_PHYSTOP;
4413 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4414 memset(&payload, 0, sizeof(payload));
4415 payload.tag = cpu_to_le32(tag);
4416 payload.phy_id = cpu_to_le32(phy_id);
4417 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4418 sizeof(payload), 0);
4423 * see comments on pm8001_mpi_reg_resp.
4425 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4426 struct pm8001_device *pm8001_dev, u32 flag)
4428 struct reg_dev_req payload;
4430 u32 stp_sspsmp_sata = 0x4;
4431 struct inbound_queue_table *circularQ;
4432 u32 linkrate, phy_id;
4433 int rc, tag = 0xdeadbeef;
4434 struct pm8001_ccb_info *ccb;
4436 u16 firstBurstSize = 0;
4438 struct domain_device *dev = pm8001_dev->sas_device;
4439 struct domain_device *parent_dev = dev->parent;
4440 struct pm8001_port *port = dev->port->lldd_port;
4441 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4443 memset(&payload, 0, sizeof(payload));
4444 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4447 ccb = &pm8001_ha->ccb_info[tag];
4448 ccb->device = pm8001_dev;
4450 payload.tag = cpu_to_le32(tag);
4452 stp_sspsmp_sata = 0x02; /*direct attached sata */
4454 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4455 stp_sspsmp_sata = 0x00; /* stp*/
4456 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4457 dev_is_expander(pm8001_dev->dev_type))
4458 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4460 if (parent_dev && dev_is_expander(parent_dev->dev_type))
4461 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4463 phy_id = pm8001_dev->attached_phy;
4464 opc = OPC_INB_REG_DEV;
4465 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4466 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4467 payload.phyid_portid =
4468 cpu_to_le32(((port->port_id) & 0x0F) |
4469 ((phy_id & 0x0F) << 4));
4470 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4471 ((linkrate & 0x0F) * 0x1000000) |
4472 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4473 payload.firstburstsize_ITNexustimeout =
4474 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4475 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4477 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4478 sizeof(payload), 0);
4483 * see comments on pm8001_mpi_reg_resp.
4485 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4488 struct dereg_dev_req payload;
4489 u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4491 struct inbound_queue_table *circularQ;
4493 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4494 memset(&payload, 0, sizeof(payload));
4495 payload.tag = cpu_to_le32(1);
4496 payload.device_id = cpu_to_le32(device_id);
4497 pm8001_dbg(pm8001_ha, MSG, "unregister device device_id = %d\n",
4499 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4500 sizeof(payload), 0);
4505 * pm8001_chip_phy_ctl_req - support the local phy operation
4506 * @pm8001_ha: our hba card information.
4507 * @phyId: the phy id which we wanted to operate
4508 * @phy_op: the phy operation to request
4510 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4511 u32 phyId, u32 phy_op)
4513 struct local_phy_ctl_req payload;
4514 struct inbound_queue_table *circularQ;
4516 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4517 memset(&payload, 0, sizeof(payload));
4518 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4519 payload.tag = cpu_to_le32(1);
4520 payload.phyop_phyid =
4521 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4522 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4523 sizeof(payload), 0);
4527 static u32 pm8001_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4529 #ifdef PM8001_USE_MSIX
4534 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4542 * pm8001_chip_isr - PM8001 isr handler.
4543 * @pm8001_ha: our hba card information.
4547 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4549 pm8001_chip_interrupt_disable(pm8001_ha, vec);
4550 pm8001_dbg(pm8001_ha, DEVIO,
4551 "irq vec %d, ODMR:0x%x\n",
4552 vec, pm8001_cr32(pm8001_ha, 0, 0x30));
4553 process_oq(pm8001_ha, vec);
4554 pm8001_chip_interrupt_enable(pm8001_ha, vec);
4558 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4559 u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4561 struct task_abort_req task_abort;
4562 struct inbound_queue_table *circularQ;
4564 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4565 memset(&task_abort, 0, sizeof(task_abort));
4566 if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4567 task_abort.abort_all = 0;
4568 task_abort.device_id = cpu_to_le32(dev_id);
4569 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4570 task_abort.tag = cpu_to_le32(cmd_tag);
4571 } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4572 task_abort.abort_all = cpu_to_le32(1);
4573 task_abort.device_id = cpu_to_le32(dev_id);
4574 task_abort.tag = cpu_to_le32(cmd_tag);
4576 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
4577 sizeof(task_abort), 0);
4582 * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4584 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4585 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4588 int rc = TMF_RESP_FUNC_FAILED;
4589 pm8001_dbg(pm8001_ha, EH, "cmd_tag = %x, abort task tag = 0x%x\n",
4591 if (pm8001_dev->dev_type == SAS_END_DEVICE)
4592 opc = OPC_INB_SSP_ABORT;
4593 else if (pm8001_dev->dev_type == SAS_SATA_DEV)
4594 opc = OPC_INB_SATA_ABORT;
4596 opc = OPC_INB_SMP_ABORT;/* SMP */
4597 device_id = pm8001_dev->device_id;
4598 rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4600 if (rc != TMF_RESP_FUNC_COMPLETE)
4601 pm8001_dbg(pm8001_ha, EH, "rc= %d\n", rc);
4606 * pm8001_chip_ssp_tm_req - built the task management command.
4607 * @pm8001_ha: our hba card information.
4608 * @ccb: the ccb information.
4609 * @tmf: task management function.
4611 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4612 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4614 struct sas_task *task = ccb->task;
4615 struct domain_device *dev = task->dev;
4616 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4617 u32 opc = OPC_INB_SSPINITMSTART;
4618 struct inbound_queue_table *circularQ;
4619 struct ssp_ini_tm_start_req sspTMCmd;
4622 memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4623 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4624 sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4625 sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4626 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4627 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4628 if (pm8001_ha->chip_id != chip_8001)
4629 sspTMCmd.ds_ads_m = 0x08;
4630 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4631 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd,
4632 sizeof(sspTMCmd), 0);
4636 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4639 u32 opc = OPC_INB_GET_NVMD_DATA;
4643 struct pm8001_ccb_info *ccb;
4644 struct inbound_queue_table *circularQ;
4645 struct get_nvm_data_req nvmd_req;
4646 struct fw_control_ex *fw_control_context;
4647 struct pm8001_ioctl_payload *ioctl_payload = payload;
4649 nvmd_type = ioctl_payload->minor_function;
4650 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4651 if (!fw_control_context)
4653 fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific;
4654 fw_control_context->len = ioctl_payload->rd_length;
4655 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4656 memset(&nvmd_req, 0, sizeof(nvmd_req));
4657 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4659 kfree(fw_control_context);
4662 ccb = &pm8001_ha->ccb_info[tag];
4664 ccb->fw_control_context = fw_control_context;
4665 nvmd_req.tag = cpu_to_le32(tag);
4667 switch (nvmd_type) {
4669 u32 twi_addr, twi_page_size;
4673 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4674 twi_page_size << 8 | TWI_DEVICE);
4675 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4676 nvmd_req.resp_addr_hi =
4677 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4678 nvmd_req.resp_addr_lo =
4679 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4683 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4684 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4685 nvmd_req.resp_addr_hi =
4686 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4687 nvmd_req.resp_addr_lo =
4688 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4692 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4693 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4694 nvmd_req.resp_addr_hi =
4695 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4696 nvmd_req.resp_addr_lo =
4697 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4701 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4702 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4703 nvmd_req.resp_addr_hi =
4704 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4705 nvmd_req.resp_addr_lo =
4706 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4710 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP);
4711 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4712 nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset);
4713 nvmd_req.resp_addr_hi =
4714 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4715 nvmd_req.resp_addr_lo =
4716 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4722 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req,
4723 sizeof(nvmd_req), 0);
4725 kfree(fw_control_context);
4726 pm8001_tag_free(pm8001_ha, tag);
4731 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4734 u32 opc = OPC_INB_SET_NVMD_DATA;
4738 struct pm8001_ccb_info *ccb;
4739 struct inbound_queue_table *circularQ;
4740 struct set_nvm_data_req nvmd_req;
4741 struct fw_control_ex *fw_control_context;
4742 struct pm8001_ioctl_payload *ioctl_payload = payload;
4744 nvmd_type = ioctl_payload->minor_function;
4745 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4746 if (!fw_control_context)
4748 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4749 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4750 &ioctl_payload->func_specific,
4751 ioctl_payload->wr_length);
4752 memset(&nvmd_req, 0, sizeof(nvmd_req));
4753 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4755 kfree(fw_control_context);
4758 ccb = &pm8001_ha->ccb_info[tag];
4759 ccb->fw_control_context = fw_control_context;
4761 nvmd_req.tag = cpu_to_le32(tag);
4762 switch (nvmd_type) {
4764 u32 twi_addr, twi_page_size;
4767 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4768 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4769 twi_page_size << 8 | TWI_DEVICE);
4770 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4771 nvmd_req.resp_addr_hi =
4772 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4773 nvmd_req.resp_addr_lo =
4774 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4778 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4779 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4780 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4781 nvmd_req.resp_addr_hi =
4782 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4783 nvmd_req.resp_addr_lo =
4784 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4787 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4788 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4789 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4790 nvmd_req.resp_addr_hi =
4791 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4792 nvmd_req.resp_addr_lo =
4793 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4796 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4797 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4798 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4799 nvmd_req.resp_addr_hi =
4800 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4801 nvmd_req.resp_addr_lo =
4802 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4807 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req,
4808 sizeof(nvmd_req), 0);
4810 kfree(fw_control_context);
4811 pm8001_tag_free(pm8001_ha, tag);
4817 * pm8001_chip_fw_flash_update_build - support the firmware update operation
4818 * @pm8001_ha: our hba card information.
4819 * @fw_flash_updata_info: firmware flash update param
4820 * @tag: Tag to apply to the payload
4823 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4824 void *fw_flash_updata_info, u32 tag)
4826 struct fw_flash_Update_req payload;
4827 struct fw_flash_updata_info *info;
4828 struct inbound_queue_table *circularQ;
4830 u32 opc = OPC_INB_FW_FLASH_UPDATE;
4832 memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4833 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4834 info = fw_flash_updata_info;
4835 payload.tag = cpu_to_le32(tag);
4836 payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4837 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4838 payload.total_image_len = cpu_to_le32(info->total_image_len);
4839 payload.len = info->sgl.im_len.len ;
4840 payload.sgl_addr_lo =
4841 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
4842 payload.sgl_addr_hi =
4843 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
4844 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4845 sizeof(payload), 0);
4850 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4853 struct fw_flash_updata_info flash_update_info;
4854 struct fw_control_info *fw_control;
4855 struct fw_control_ex *fw_control_context;
4858 struct pm8001_ccb_info *ccb;
4859 void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr;
4860 dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr;
4861 struct pm8001_ioctl_payload *ioctl_payload = payload;
4863 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4864 if (!fw_control_context)
4866 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific;
4867 pm8001_dbg(pm8001_ha, DEVIO,
4868 "dma fw_control context input length :%x\n",
4870 memcpy(buffer, fw_control->buffer, fw_control->len);
4871 flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4872 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4873 flash_update_info.sgl.im_len.e = 0;
4874 flash_update_info.cur_image_offset = fw_control->offset;
4875 flash_update_info.cur_image_len = fw_control->len;
4876 flash_update_info.total_image_len = fw_control->size;
4877 fw_control_context->fw_control = fw_control;
4878 fw_control_context->virtAddr = buffer;
4879 fw_control_context->phys_addr = phys_addr;
4880 fw_control_context->len = fw_control->len;
4881 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4883 kfree(fw_control_context);
4886 ccb = &pm8001_ha->ccb_info[tag];
4887 ccb->fw_control_context = fw_control_context;
4889 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4895 pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf)
4897 u32 value, rem, offset = 0, bar = 0;
4898 u32 index, work_offset, dw_length;
4899 u32 shift_value, gsm_base, gsm_dump_offset;
4901 struct Scsi_Host *shost = class_to_shost(cdev);
4902 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
4903 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
4906 gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset;
4908 /* check max is 1 Mbytes */
4909 if ((length > 0x100000) || (gsm_dump_offset & 3) ||
4910 ((gsm_dump_offset + length) > 0x1000000))
4913 if (pm8001_ha->chip_id == chip_8001)
4918 work_offset = gsm_dump_offset & 0xFFFF0000;
4919 offset = gsm_dump_offset & 0x0000FFFF;
4920 gsm_dump_offset = work_offset;
4921 /* adjust length to dword boundary */
4923 dw_length = length >> 2;
4925 for (index = 0; index < dw_length; index++) {
4926 if ((work_offset + offset) & 0xFFFF0000) {
4927 if (pm8001_ha->chip_id == chip_8001)
4928 shift_value = ((gsm_dump_offset + offset) &
4929 SHIFT_REG_64K_MASK);
4931 shift_value = (((gsm_dump_offset + offset) &
4932 SHIFT_REG_64K_MASK) >>
4933 SHIFT_REG_BIT_SHIFT);
4935 if (pm8001_ha->chip_id == chip_8001) {
4936 gsm_base = GSM_BASE;
4937 if (-1 == pm8001_bar4_shift(pm8001_ha,
4938 (gsm_base + shift_value)))
4942 if (-1 == pm80xx_bar4_shift(pm8001_ha,
4943 (gsm_base + shift_value)))
4946 gsm_dump_offset = (gsm_dump_offset + offset) &
4949 offset = offset & 0x0000FFFF;
4951 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
4953 direct_data += sprintf(direct_data, "%08x ", value);
4957 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
4959 /* xfr for non_dw */
4960 direct_data += sprintf(direct_data, "%08x ", value);
4962 /* Shift back to BAR4 original address */
4963 if (-1 == pm8001_bar4_shift(pm8001_ha, 0))
4965 pm8001_ha->fatal_forensic_shift_offset += 1024;
4967 if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000)
4968 pm8001_ha->fatal_forensic_shift_offset = 0;
4969 return direct_data - buf;
4973 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4974 struct pm8001_device *pm8001_dev, u32 state)
4976 struct set_dev_state_req payload;
4977 struct inbound_queue_table *circularQ;
4978 struct pm8001_ccb_info *ccb;
4981 u32 opc = OPC_INB_SET_DEVICE_STATE;
4982 memset(&payload, 0, sizeof(payload));
4983 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4986 ccb = &pm8001_ha->ccb_info[tag];
4988 ccb->device = pm8001_dev;
4989 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4990 payload.tag = cpu_to_le32(tag);
4991 payload.device_id = cpu_to_le32(pm8001_dev->device_id);
4992 payload.nds = cpu_to_le32(state);
4993 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4994 sizeof(payload), 0);
5000 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
5002 struct sas_re_initialization_req payload;
5003 struct inbound_queue_table *circularQ;
5004 struct pm8001_ccb_info *ccb;
5007 u32 opc = OPC_INB_SAS_RE_INITIALIZE;
5008 memset(&payload, 0, sizeof(payload));
5009 rc = pm8001_tag_alloc(pm8001_ha, &tag);
5012 ccb = &pm8001_ha->ccb_info[tag];
5014 circularQ = &pm8001_ha->inbnd_q_tbl[0];
5015 payload.tag = cpu_to_le32(tag);
5016 payload.SSAHOLT = cpu_to_le32(0xd << 25);
5017 payload.sata_hol_tmo = cpu_to_le32(80);
5018 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
5019 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
5020 sizeof(payload), 0);
5022 pm8001_tag_free(pm8001_ha, tag);
5027 const struct pm8001_dispatch pm8001_8001_dispatch = {
5029 .chip_init = pm8001_chip_init,
5030 .chip_soft_rst = pm8001_chip_soft_rst,
5031 .chip_rst = pm8001_hw_chip_rst,
5032 .chip_iounmap = pm8001_chip_iounmap,
5033 .isr = pm8001_chip_isr,
5034 .is_our_interrupt = pm8001_chip_is_our_interrupt,
5035 .isr_process_oq = process_oq,
5036 .interrupt_enable = pm8001_chip_interrupt_enable,
5037 .interrupt_disable = pm8001_chip_interrupt_disable,
5038 .make_prd = pm8001_chip_make_sg,
5039 .smp_req = pm8001_chip_smp_req,
5040 .ssp_io_req = pm8001_chip_ssp_io_req,
5041 .sata_req = pm8001_chip_sata_req,
5042 .phy_start_req = pm8001_chip_phy_start_req,
5043 .phy_stop_req = pm8001_chip_phy_stop_req,
5044 .reg_dev_req = pm8001_chip_reg_dev_req,
5045 .dereg_dev_req = pm8001_chip_dereg_dev_req,
5046 .phy_ctl_req = pm8001_chip_phy_ctl_req,
5047 .task_abort = pm8001_chip_abort_task,
5048 .ssp_tm_req = pm8001_chip_ssp_tm_req,
5049 .get_nvmd_req = pm8001_chip_get_nvmd_req,
5050 .set_nvmd_req = pm8001_chip_set_nvmd_req,
5051 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
5052 .set_dev_state_req = pm8001_chip_set_dev_state_req,
5053 .sas_re_init_req = pm8001_chip_sas_re_initialization,
5054 .fatal_errors = pm80xx_fatal_errors,