drivers/scsi/mvsas/mv_init.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Marvell 88SE64xx/88SE94xx pci init
   4  *
   5  * Copyright 2007 Red Hat, Inc.
   6  * Copyright 2008 Marvell. <kewei@marvell.com>
   7  * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
   8 */
   9
  10
  11 #include "mv_sas.h"
  12
  13 int interrupt_coalescing = 0x80;
  14
  15 static struct scsi_transport_template *mvs_stt;
  16 static const struct mvs_chip_info mvs_chips[] = {
  17         [chip_6320] =   { 1, 2, 0x400, 17, 16, 6,  9, &mvs_64xx_dispatch, },
  18         [chip_6440] =   { 1, 4, 0x400, 17, 16, 6,  9, &mvs_64xx_dispatch, },
  19         [chip_6485] =   { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, },
  20         [chip_9180] =   { 2, 4, 0x800, 17, 64, 8,  9, &mvs_94xx_dispatch, },
  21         [chip_9480] =   { 2, 4, 0x800, 17, 64, 8,  9, &mvs_94xx_dispatch, },
  22         [chip_9445] =   { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
  23         [chip_9485] =   { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
  24         [chip_1300] =   { 1, 4, 0x400, 17, 16, 6,  9, &mvs_64xx_dispatch, },
  25         [chip_1320] =   { 2, 4, 0x800, 17, 64, 8,  9, &mvs_94xx_dispatch, },
  26 };
  27
  28 static struct device_attribute *mvst_host_attrs[];
  29
  30 #define SOC_SAS_NUM 2
  31
  32 static struct scsi_host_template mvs_sht = {
  33         .module                 = THIS_MODULE,
  34         .name                   = DRV_NAME,
  35         .queuecommand           = sas_queuecommand,
  36         .dma_need_drain         = ata_scsi_dma_need_drain,
  37         .target_alloc           = sas_target_alloc,
  38         .slave_configure        = sas_slave_configure,
  39         .scan_finished          = mvs_scan_finished,
  40         .scan_start             = mvs_scan_start,
  41         .change_queue_depth     = sas_change_queue_depth,
  42         .bios_param             = sas_bios_param,
  43         .can_queue              = 1,
  44         .this_id                = -1,
  45         .sg_tablesize           = SG_ALL,
  46         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
  47         .eh_device_reset_handler = sas_eh_device_reset_handler,
  48         .eh_target_reset_handler = sas_eh_target_reset_handler,
  49         .slave_alloc            = sas_slave_alloc,
  50         .target_destroy         = sas_target_destroy,
  51         .ioctl                  = sas_ioctl,
  52 #ifdef CONFIG_COMPAT
  53         .compat_ioctl           = sas_ioctl,
  54 #endif
  55         .shost_attrs            = mvst_host_attrs,
  56         .track_queue_depth      = 1,
  57 };
  58
  59 static struct sas_domain_function_template mvs_transport_ops = {
  60         .lldd_dev_found         = mvs_dev_found,
  61         .lldd_dev_gone          = mvs_dev_gone,
  62         .lldd_execute_task      = mvs_queue_command,
  63         .lldd_control_phy       = mvs_phy_control,
  64
  65         .lldd_abort_task        = mvs_abort_task,
  66         .lldd_abort_task_set    = mvs_abort_task_set,
  67         .lldd_clear_aca         = mvs_clear_aca,
  68         .lldd_clear_task_set    = mvs_clear_task_set,
  69         .lldd_I_T_nexus_reset   = mvs_I_T_nexus_reset,
  70         .lldd_lu_reset          = mvs_lu_reset,
  71         .lldd_query_task        = mvs_query_task,
  72         .lldd_port_formed       = mvs_port_formed,
  73         .lldd_port_deformed     = mvs_port_deformed,
  74
  75         .lldd_write_gpio        = mvs_gpio_write,
  76
  77 };
  78
  79 static void mvs_phy_init(struct mvs_info *mvi, int phy_id)
  80 {
  81         struct mvs_phy *phy = &mvi->phy[phy_id];
  82         struct asd_sas_phy *sas_phy = &phy->sas_phy;
  83
  84         phy->mvi = mvi;
  85         phy->port = NULL;
  86         timer_setup(&phy->timer, NULL, 0);
  87         sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
  88         sas_phy->class = SAS;
  89         sas_phy->iproto = SAS_PROTOCOL_ALL;
  90         sas_phy->tproto = 0;
  91         sas_phy->type = PHY_TYPE_PHYSICAL;
  92         sas_phy->role = PHY_ROLE_INITIATOR;
  93         sas_phy->oob_mode = OOB_NOT_CONNECTED;
  94         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
  95
  96         sas_phy->id = phy_id;
  97         sas_phy->sas_addr = &mvi->sas_addr[0];
  98         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
  99         sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata;
 100         sas_phy->lldd_phy = phy;
 101 }
 102
 103 static void mvs_free(struct mvs_info *mvi)
 104 {
 105         struct mvs_wq *mwq;
 106         int slot_nr;
 107
 108         if (!mvi)
 109                 return;
 110
 111         if (mvi->flags & MVF_FLAG_SOC)
 112                 slot_nr = MVS_SOC_SLOTS;
 113         else
 114                 slot_nr = MVS_CHIP_SLOT_SZ;
 115
 116         dma_pool_destroy(mvi->dma_pool);
 117
 118         if (mvi->tx)
 119                 dma_free_coherent(mvi->dev,
 120                                   sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
 121                                   mvi->tx, mvi->tx_dma);
 122         if (mvi->rx_fis)
 123                 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ,
 124                                   mvi->rx_fis, mvi->rx_fis_dma);
 125         if (mvi->rx)
 126                 dma_free_coherent(mvi->dev,
 127                                   sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
 128                                   mvi->rx, mvi->rx_dma);
 129         if (mvi->slot)
 130                 dma_free_coherent(mvi->dev,
 131                                   sizeof(*mvi->slot) * slot_nr,
 132                                   mvi->slot, mvi->slot_dma);
 133
 134         if (mvi->bulk_buffer)
 135                 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
 136                                   mvi->bulk_buffer, mvi->bulk_buffer_dma);
 137         if (mvi->bulk_buffer1)
 138                 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
 139                                   mvi->bulk_buffer1, mvi->bulk_buffer_dma1);
 140
 141         MVS_CHIP_DISP->chip_iounmap(mvi);
 142         if (mvi->shost)
 143                 scsi_host_put(mvi->shost);
 144         list_for_each_entry(mwq, &mvi->wq_list, entry)
 145                 cancel_delayed_work(&mwq->work_q);
 146         kfree(mvi->tags);
 147         kfree(mvi);
 148 }
 149
 150 #ifdef CONFIG_SCSI_MVSAS_TASKLET
 151 static void mvs_tasklet(unsigned long opaque)
 152 {
 153         u32 stat;
 154         u16 core_nr, i = 0;
 155
 156         struct mvs_info *mvi;
 157         struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque;
 158
 159         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 160         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
 161
 162         if (unlikely(!mvi))
 163                 BUG_ON(1);
 164
 165         stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq);
 166         if (!stat)
 167                 goto out;
 168
 169         for (i = 0; i < core_nr; i++) {
 170                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
 171                 MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat);
 172         }
 173 out:
 174         MVS_CHIP_DISP->interrupt_enable(mvi);
 175
 176 }
 177 #endif
 178
 179 static irqreturn_t mvs_interrupt(int irq, void *opaque)
 180 {
 181         u32 stat;
 182         struct mvs_info *mvi;
 183         struct sas_ha_struct *sha = opaque;
 184 #ifndef CONFIG_SCSI_MVSAS_TASKLET
 185         u32 i;
 186         u32 core_nr;
 187
 188         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 189 #endif
 190
 191         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
 192
 193         if (unlikely(!mvi))
 194                 return IRQ_NONE;
 195 #ifdef CONFIG_SCSI_MVSAS_TASKLET
 196         MVS_CHIP_DISP->interrupt_disable(mvi);
 197 #endif
 198
 199         stat = MVS_CHIP_DISP->isr_status(mvi, irq);
 200         if (!stat) {
 201         #ifdef CONFIG_SCSI_MVSAS_TASKLET
 202                 MVS_CHIP_DISP->interrupt_enable(mvi);
 203         #endif
 204                 return IRQ_NONE;
 205         }
 206
 207 #ifdef CONFIG_SCSI_MVSAS_TASKLET
 208         tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
 209 #else
 210         for (i = 0; i < core_nr; i++) {
 211                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
 212                 MVS_CHIP_DISP->isr(mvi, irq, stat);
 213         }
 214 #endif
 215         return IRQ_HANDLED;
 216 }
 217
 218 static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost)
 219 {
 220         int i = 0, slot_nr;
 221         char pool_name[32];
 222
 223         if (mvi->flags & MVF_FLAG_SOC)
 224                 slot_nr = MVS_SOC_SLOTS;
 225         else
 226                 slot_nr = MVS_CHIP_SLOT_SZ;
 227
 228         spin_lock_init(&mvi->lock);
 229         for (i = 0; i < mvi->chip->n_phy; i++) {
 230                 mvs_phy_init(mvi, i);
 231                 mvi->port[i].wide_port_phymap = 0;
 232                 mvi->port[i].port_attached = 0;
 233                 INIT_LIST_HEAD(&mvi->port[i].list);
 234         }
 235         for (i = 0; i < MVS_MAX_DEVICES; i++) {
 236                 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED;
 237                 mvi->devices[i].dev_type = SAS_PHY_UNUSED;
 238                 mvi->devices[i].device_id = i;
 239                 mvi->devices[i].dev_status = MVS_DEV_NORMAL;
 240         }
 241
 242         /*
 243          * alloc and init our DMA areas
 244          */
 245         mvi->tx = dma_alloc_coherent(mvi->dev,
 246                                      sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
 247                                      &mvi->tx_dma, GFP_KERNEL);
 248         if (!mvi->tx)
 249                 goto err_out;
 250         mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ,
 251                                          &mvi->rx_fis_dma, GFP_KERNEL);
 252         if (!mvi->rx_fis)
 253                 goto err_out;
 254
 255         mvi->rx = dma_alloc_coherent(mvi->dev,
 256                                      sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
 257                                      &mvi->rx_dma, GFP_KERNEL);
 258         if (!mvi->rx)
 259                 goto err_out;
 260         mvi->rx[0] = cpu_to_le32(0xfff);
 261         mvi->rx_cons = 0xfff;
 262
 263         mvi->slot = dma_alloc_coherent(mvi->dev,
 264                                        sizeof(*mvi->slot) * slot_nr,
 265                                        &mvi->slot_dma, GFP_KERNEL);
 266         if (!mvi->slot)
 267                 goto err_out;
 268
 269         mvi->bulk_buffer = dma_alloc_coherent(mvi->dev,
 270                                        TRASH_BUCKET_SIZE,
 271                                        &mvi->bulk_buffer_dma, GFP_KERNEL);
 272         if (!mvi->bulk_buffer)
 273                 goto err_out;
 274
 275         mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev,
 276                                        TRASH_BUCKET_SIZE,
 277                                        &mvi->bulk_buffer_dma1, GFP_KERNEL);
 278         if (!mvi->bulk_buffer1)
 279                 goto err_out;
 280
 281         sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id);
 282         mvi->dma_pool = dma_pool_create(pool_name, &mvi->pdev->dev,
 283                                         MVS_SLOT_BUF_SZ, 16, 0);
 284         if (!mvi->dma_pool) {
 285                         printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name);
 286                         goto err_out;
 287         }
 288         mvi->tags_num = slot_nr;
 289
 290         /* Initialize tags */
 291         mvs_tag_init(mvi);
 292         return 0;
 293 err_out:
 294         return 1;
 295 }
 296
 297
 298 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex)
 299 {
 300         unsigned long res_start, res_len, res_flag_ex = 0;
 301         struct pci_dev *pdev = mvi->pdev;
 302         if (bar_ex != -1) {
 303                 /*
 304                  * ioremap main and peripheral registers
 305                  */
 306                 res_start = pci_resource_start(pdev, bar_ex);
 307                 res_len = pci_resource_len(pdev, bar_ex);
 308                 if (!res_start || !res_len)
 309                         goto err_out;
 310
 311                 res_flag_ex = pci_resource_flags(pdev, bar_ex);
 312                 if (res_flag_ex & IORESOURCE_MEM)
 313                         mvi->regs_ex = ioremap(res_start, res_len);
 314                 else
 315                         mvi->regs_ex = (void *)res_start;
 316                 if (!mvi->regs_ex)
 317                         goto err_out;
 318         }
 319
 320         res_start = pci_resource_start(pdev, bar);
 321         res_len = pci_resource_len(pdev, bar);
 322         if (!res_start || !res_len) {
 323                 iounmap(mvi->regs_ex);
 324                 mvi->regs_ex = NULL;
 325                 goto err_out;
 326         }
 327
 328         mvi->regs = ioremap(res_start, res_len);
 329
 330         if (!mvi->regs) {
 331                 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM))
 332                         iounmap(mvi->regs_ex);
 333                 mvi->regs_ex = NULL;
 334                 goto err_out;
 335         }
 336
 337         return 0;
 338 err_out:
 339         return -1;
 340 }
 341
 342 void mvs_iounmap(void __iomem *regs)
 343 {
 344         iounmap(regs);
 345 }
 346
 347 static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev,
 348                                 const struct pci_device_id *ent,
 349                                 struct Scsi_Host *shost, unsigned int id)
 350 {
 351         struct mvs_info *mvi = NULL;
 352         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 353
 354         mvi = kzalloc(sizeof(*mvi) +
 355                 (1L << mvs_chips[ent->driver_data].slot_width) *
 356                 sizeof(struct mvs_slot_info), GFP_KERNEL);
 357         if (!mvi)
 358                 return NULL;
 359
 360         mvi->pdev = pdev;
 361         mvi->dev = &pdev->dev;
 362         mvi->chip_id = ent->driver_data;
 363         mvi->chip = &mvs_chips[mvi->chip_id];
 364         INIT_LIST_HEAD(&mvi->wq_list);
 365
 366         ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi;
 367         ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy;
 368
 369         mvi->id = id;
 370         mvi->sas = sha;
 371         mvi->shost = shost;
 372
 373         mvi->tags = kzalloc(MVS_CHIP_SLOT_SZ>>3, GFP_KERNEL);
 374         if (!mvi->tags)
 375                 goto err_out;
 376
 377         if (MVS_CHIP_DISP->chip_ioremap(mvi))
 378                 goto err_out;
 379         if (!mvs_alloc(mvi, shost))
 380                 return mvi;
 381 err_out:
 382         mvs_free(mvi);
 383         return NULL;
 384 }
 385
 386 static int pci_go_64(struct pci_dev *pdev)
 387 {
 388         int rc;
 389
 390         rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
 391         if (rc) {
 392                 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 393                 if (rc) {
 394                         dev_printk(KERN_ERR, &pdev->dev,
 395                                    "32-bit DMA enable failed\n");
 396                         return rc;
 397                 }
 398         }
 399
 400         return rc;
 401 }
 402
 403 static int mvs_prep_sas_ha_init(struct Scsi_Host *shost,
 404                                 const struct mvs_chip_info *chip_info)
 405 {
 406         int phy_nr, port_nr; unsigned short core_nr;
 407         struct asd_sas_phy **arr_phy;
 408         struct asd_sas_port **arr_port;
 409         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 410
 411         core_nr = chip_info->n_host;
 412         phy_nr  = core_nr * chip_info->n_phy;
 413         port_nr = phy_nr;
 414
 415         memset(sha, 0x00, sizeof(struct sas_ha_struct));
 416         arr_phy  = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
 417         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
 418         if (!arr_phy || !arr_port)
 419                 goto exit_free;
 420
 421         sha->sas_phy = arr_phy;
 422         sha->sas_port = arr_port;
 423         sha->core.shost = shost;
 424
 425         sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL);
 426         if (!sha->lldd_ha)
 427                 goto exit_free;
 428
 429         ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr;
 430
 431         shost->transportt = mvs_stt;
 432         shost->max_id = MVS_MAX_DEVICES;
 433         shost->max_lun = ~0;
 434         shost->max_channel = 1;
 435         shost->max_cmd_len = 16;
 436
 437         return 0;
 438 exit_free:
 439         kfree(arr_phy);
 440         kfree(arr_port);
 441         return -1;
 442
 443 }
 444
 445 static void  mvs_post_sas_ha_init(struct Scsi_Host *shost,
 446                         const struct mvs_chip_info *chip_info)
 447 {
 448         int can_queue, i = 0, j = 0;
 449         struct mvs_info *mvi = NULL;
 450         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 451         unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 452
 453         for (j = 0; j < nr_core; j++) {
 454                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
 455                 for (i = 0; i < chip_info->n_phy; i++) {
 456                         sha->sas_phy[j * chip_info->n_phy  + i] =
 457                                 &mvi->phy[i].sas_phy;
 458                         sha->sas_port[j * chip_info->n_phy + i] =
 459                                 &mvi->port[i].sas_port;
 460                 }
 461         }
 462
 463         sha->sas_ha_name = DRV_NAME;
 464         sha->dev = mvi->dev;
 465         sha->lldd_module = THIS_MODULE;
 466         sha->sas_addr = &mvi->sas_addr[0];
 467
 468         sha->num_phys = nr_core * chip_info->n_phy;
 469
 470         if (mvi->flags & MVF_FLAG_SOC)
 471                 can_queue = MVS_SOC_CAN_QUEUE;
 472         else
 473                 can_queue = MVS_CHIP_SLOT_SZ;
 474
 475         shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG);
 476         shost->can_queue = can_queue;
 477         mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE;
 478         sha->core.shost = mvi->shost;
 479 }
 480
 481 static void mvs_init_sas_add(struct mvs_info *mvi)
 482 {
 483         u8 i;
 484         for (i = 0; i < mvi->chip->n_phy; i++) {
 485                 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL;
 486                 mvi->phy[i].dev_sas_addr =
 487                         cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr));
 488         }
 489
 490         memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE);
 491 }
 492
 493 static int mvs_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent)
 494 {
 495         unsigned int rc, nhost = 0;
 496         struct mvs_info *mvi;
 497         struct mvs_prv_info *mpi;
 498         irq_handler_t irq_handler = mvs_interrupt;
 499         struct Scsi_Host *shost = NULL;
 500         const struct mvs_chip_info *chip;
 501
 502         dev_printk(KERN_INFO, &pdev->dev,
 503                 "mvsas: driver version %s\n", DRV_VERSION);
 504         rc = pci_enable_device(pdev);
 505         if (rc)
 506                 goto err_out_enable;
 507
 508         pci_set_master(pdev);
 509
 510         rc = pci_request_regions(pdev, DRV_NAME);
 511         if (rc)
 512                 goto err_out_disable;
 513
 514         rc = pci_go_64(pdev);
 515         if (rc)
 516                 goto err_out_regions;
 517
 518         shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
 519         if (!shost) {
 520                 rc = -ENOMEM;
 521                 goto err_out_regions;
 522         }
 523
 524         chip = &mvs_chips[ent->driver_data];
 525         SHOST_TO_SAS_HA(shost) =
 526                 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL);
 527         if (!SHOST_TO_SAS_HA(shost)) {
 528                 scsi_host_put(shost);
 529                 rc = -ENOMEM;
 530                 goto err_out_regions;
 531         }
 532
 533         rc = mvs_prep_sas_ha_init(shost, chip);
 534         if (rc) {
 535                 scsi_host_put(shost);
 536                 rc = -ENOMEM;
 537                 goto err_out_regions;
 538         }
 539
 540         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
 541
 542         do {
 543                 mvi = mvs_pci_alloc(pdev, ent, shost, nhost);
 544                 if (!mvi) {
 545                         rc = -ENOMEM;
 546                         goto err_out_regions;
 547                 }
 548
 549                 memset(&mvi->hba_info_param, 0xFF,
 550                         sizeof(struct hba_info_page));
 551
 552                 mvs_init_sas_add(mvi);
 553
 554                 mvi->instance = nhost;
 555                 rc = MVS_CHIP_DISP->chip_init(mvi);
 556                 if (rc) {
 557                         mvs_free(mvi);
 558                         goto err_out_regions;
 559                 }
 560                 nhost++;
 561         } while (nhost < chip->n_host);
 562         mpi = (struct mvs_prv_info *)(SHOST_TO_SAS_HA(shost)->lldd_ha);
 563 #ifdef CONFIG_SCSI_MVSAS_TASKLET
 564         tasklet_init(&(mpi->mv_tasklet), mvs_tasklet,
 565                      (unsigned long)SHOST_TO_SAS_HA(shost));
 566 #endif
 567
 568         mvs_post_sas_ha_init(shost, chip);
 569
 570         rc = scsi_add_host(shost, &pdev->dev);
 571         if (rc)
 572                 goto err_out_shost;
 573
 574         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
 575         if (rc)
 576                 goto err_out_shost;
 577         rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED,
 578                 DRV_NAME, SHOST_TO_SAS_HA(shost));
 579         if (rc)
 580                 goto err_not_sas;
 581
 582         MVS_CHIP_DISP->interrupt_enable(mvi);
 583
 584         scsi_scan_host(mvi->shost);
 585
 586         return 0;
 587
 588 err_not_sas:
 589         sas_unregister_ha(SHOST_TO_SAS_HA(shost));
 590 err_out_shost:
 591         scsi_remove_host(mvi->shost);
 592 err_out_regions:
 593         pci_release_regions(pdev);
 594 err_out_disable:
 595         pci_disable_device(pdev);
 596 err_out_enable:
 597         return rc;
 598 }
 599
 600 static void mvs_pci_remove(struct pci_dev *pdev)
 601 {
 602         unsigned short core_nr, i = 0;
 603         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
 604         struct mvs_info *mvi = NULL;
 605
 606         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 607         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
 608
 609 #ifdef CONFIG_SCSI_MVSAS_TASKLET
 610         tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
 611 #endif
 612
 613         sas_unregister_ha(sha);
 614         sas_remove_host(mvi->shost);
 615
 616         MVS_CHIP_DISP->interrupt_disable(mvi);
 617         free_irq(mvi->pdev->irq, sha);
 618         for (i = 0; i < core_nr; i++) {
 619                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
 620                 mvs_free(mvi);
 621         }
 622         kfree(sha->sas_phy);
 623         kfree(sha->sas_port);
 624         kfree(sha);
 625         pci_release_regions(pdev);
 626         pci_disable_device(pdev);
 627         return;
 628 }
 629
 630 static struct pci_device_id mvs_pci_table[] = {
 631         { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },
 632         { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },
 633         {
 634                 .vendor         = PCI_VENDOR_ID_MARVELL,
 635                 .device         = 0x6440,
 636                 .subvendor      = PCI_ANY_ID,
 637                 .subdevice      = 0x6480,
 638                 .class          = 0,
 639                 .class_mask     = 0,
 640                 .driver_data    = chip_6485,
 641         },
 642         { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },
 643         { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 },
 644         { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 },
 645         { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 },
 646         { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 },
 647         { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 },
 648         { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 },
 649         { PCI_VDEVICE(TTI, 0x2710), chip_9480 },
 650         { PCI_VDEVICE(TTI, 0x2720), chip_9480 },
 651         { PCI_VDEVICE(TTI, 0x2721), chip_9480 },
 652         { PCI_VDEVICE(TTI, 0x2722), chip_9480 },
 653         { PCI_VDEVICE(TTI, 0x2740), chip_9480 },
 654         { PCI_VDEVICE(TTI, 0x2744), chip_9480 },
 655         { PCI_VDEVICE(TTI, 0x2760), chip_9480 },
 656         {
 657                 .vendor         = PCI_VENDOR_ID_MARVELL_EXT,
 658                 .device         = 0x9480,
 659                 .subvendor      = PCI_ANY_ID,
 660                 .subdevice      = 0x9480,
 661                 .class          = 0,
 662                 .class_mask     = 0,
 663                 .driver_data    = chip_9480,
 664         },
 665         {
 666                 .vendor         = PCI_VENDOR_ID_MARVELL_EXT,
 667                 .device         = 0x9445,
 668                 .subvendor      = PCI_ANY_ID,
 669                 .subdevice      = 0x9480,
 670                 .class          = 0,
 671                 .class_mask     = 0,
 672                 .driver_data    = chip_9445,
 673         },
 674         { PCI_VDEVICE(MARVELL_EXT, 0x9485), chip_9485 }, /* Marvell 9480/9485 (any vendor/model) */
 675         { PCI_VDEVICE(OCZ, 0x1021), chip_9485}, /* OCZ RevoDrive3 */
 676         { PCI_VDEVICE(OCZ, 0x1022), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 677         { PCI_VDEVICE(OCZ, 0x1040), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 678         { PCI_VDEVICE(OCZ, 0x1041), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 679         { PCI_VDEVICE(OCZ, 0x1042), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 680         { PCI_VDEVICE(OCZ, 0x1043), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 681         { PCI_VDEVICE(OCZ, 0x1044), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 682         { PCI_VDEVICE(OCZ, 0x1080), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 683         { PCI_VDEVICE(OCZ, 0x1083), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 684         { PCI_VDEVICE(OCZ, 0x1084), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
 685
 686         { }     /* terminate list */
 687 };
 688
 689 static struct pci_driver mvs_pci_driver = {
 690         .name           = DRV_NAME,
 691         .id_table       = mvs_pci_table,
 692         .probe          = mvs_pci_init,
 693         .remove         = mvs_pci_remove,
 694 };
 695
 696 static ssize_t driver_version_show(struct device *cdev,
 697                                    struct device_attribute *attr, char *buffer)
 698 {
 699         return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION);
 700 }
 701
 702 static DEVICE_ATTR_RO(driver_version);
 703
 704 static ssize_t interrupt_coalescing_store(struct device *cdev,
 705                                           struct device_attribute *attr,
 706                                           const char *buffer, size_t size)
 707 {
 708         unsigned int val = 0;
 709         struct mvs_info *mvi = NULL;
 710         struct Scsi_Host *shost = class_to_shost(cdev);
 711         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 712         u8 i, core_nr;
 713         if (buffer == NULL)
 714                 return size;
 715
 716         if (sscanf(buffer, "%u", &val) != 1)
 717                 return -EINVAL;
 718
 719         if (val >= 0x10000) {
 720                 mv_dprintk("interrupt coalescing timer %d us is"
 721                         "too long\n", val);
 722                 return strlen(buffer);
 723         }
 724
 725         interrupt_coalescing = val;
 726
 727         core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
 728         mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
 729
 730         if (unlikely(!mvi))
 731                 return -EINVAL;
 732
 733         for (i = 0; i < core_nr; i++) {
 734                 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
 735                 if (MVS_CHIP_DISP->tune_interrupt)
 736                         MVS_CHIP_DISP->tune_interrupt(mvi,
 737                                 interrupt_coalescing);
 738         }
 739         mv_dprintk("set interrupt coalescing time to %d us\n",
 740                 interrupt_coalescing);
 741         return strlen(buffer);
 742 }
 743
 744 static ssize_t interrupt_coalescing_show(struct device *cdev,
 745                                          struct device_attribute *attr, char *buffer)
 746 {
 747         return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing);
 748 }
 749
 750 static DEVICE_ATTR_RW(interrupt_coalescing);
 751
 752 static int __init mvs_init(void)
 753 {
 754         int rc;
 755         mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);
 756         if (!mvs_stt)
 757                 return -ENOMEM;
 758
 759         rc = pci_register_driver(&mvs_pci_driver);
 760         if (rc)
 761                 goto err_out;
 762
 763         return 0;
 764
 765 err_out:
 766         sas_release_transport(mvs_stt);
 767         return rc;
 768 }
 769
 770 static void __exit mvs_exit(void)
 771 {
 772         pci_unregister_driver(&mvs_pci_driver);
 773         sas_release_transport(mvs_stt);
 774 }
 775
 776 static struct device_attribute *mvst_host_attrs[] = {
 777         &dev_attr_driver_version,
 778         &dev_attr_interrupt_coalescing,
 779         NULL,
 780 };
 781
 782 module_init(mvs_init);
 783 module_exit(mvs_exit);
 784
 785 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
 786 MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");
 787 MODULE_VERSION(DRV_VERSION);
 788 MODULE_LICENSE("GPL");
 789 #ifdef CONFIG_PCI
 790 MODULE_DEVICE_TABLE(pci, mvs_pci_table);
 791 #endif