2 * This is the Fusion MPT base driver providing common API layer interface
3 * for access to MPT (Message Passing Technology) firmware.
5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
6 * Copyright (C) 2012-2014 LSI Corporation
7 * Copyright (C) 2013-2014 Avago Technologies
8 * (mailto: MPT-FusionLinux.pdl@avagotech.com)
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25 * solely responsible for determining the appropriateness of using and
26 * distributing the Program and assumes all risks associated with its
27 * exercise of rights under this Agreement, including but not limited to
28 * the risks and costs of program errors, damage to or loss of data,
29 * programs or equipment, and unavailability or interruption of operations.
31 * DISCLAIMER OF LIABILITY
32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/errno.h>
49 #include <linux/init.h>
50 #include <linux/slab.h>
51 #include <linux/types.h>
52 #include <linux/pci.h>
53 #include <linux/kdev_t.h>
54 #include <linux/blkdev.h>
55 #include <linux/delay.h>
56 #include <linux/interrupt.h>
57 #include <linux/dma-mapping.h>
59 #include <linux/time.h>
60 #include <linux/ktime.h>
61 #include <linux/kthread.h>
62 #include <asm/page.h> /* To get host page size per arch */
63 #include <linux/aer.h>
66 #include "mpt3sas_base.h"
68 static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
71 #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
73 /* maximum controller queue depth */
74 #define MAX_HBA_QUEUE_DEPTH 30000
75 #define MAX_CHAIN_DEPTH 100000
76 static int max_queue_depth = -1;
77 module_param(max_queue_depth, int, 0);
78 MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
80 static int max_sgl_entries = -1;
81 module_param(max_sgl_entries, int, 0);
82 MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
84 static int msix_disable = -1;
85 module_param(msix_disable, int, 0);
86 MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
88 static int smp_affinity_enable = 1;
89 module_param(smp_affinity_enable, int, S_IRUGO);
90 MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disbale Default: enable(1)");
92 static int max_msix_vectors = -1;
93 module_param(max_msix_vectors, int, 0);
94 MODULE_PARM_DESC(max_msix_vectors,
97 static int mpt3sas_fwfault_debug;
98 MODULE_PARM_DESC(mpt3sas_fwfault_debug,
99 " enable detection of firmware fault and halt firmware - (default=0)");
102 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc);
105 * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
109 _scsih_set_fwfault_debug(const char *val, const struct kernel_param *kp)
111 int ret = param_set_int(val, kp);
112 struct MPT3SAS_ADAPTER *ioc;
117 /* global ioc spinlock to protect controller list on list operations */
118 pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
119 spin_lock(&gioc_lock);
120 list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
121 ioc->fwfault_debug = mpt3sas_fwfault_debug;
122 spin_unlock(&gioc_lock);
125 module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
126 param_get_int, &mpt3sas_fwfault_debug, 0644);
129 * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
130 * @arg: input argument, used to derive ioc
132 * Return 0 if controller is removed from pci subsystem.
133 * Return -1 for other case.
135 static int mpt3sas_remove_dead_ioc_func(void *arg)
137 struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
138 struct pci_dev *pdev;
146 pci_stop_and_remove_bus_device_locked(pdev);
151 * _base_fault_reset_work - workq handling ioc fault conditions
152 * @work: input argument, used to derive ioc
158 _base_fault_reset_work(struct work_struct *work)
160 struct MPT3SAS_ADAPTER *ioc =
161 container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
165 struct task_struct *p;
168 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
169 if (ioc->shost_recovery || ioc->pci_error_recovery)
171 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
173 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
174 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
175 pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n",
178 /* It may be possible that EEH recovery can resolve some of
179 * pci bus failure issues rather removing the dead ioc function
180 * by considering controller is in a non-operational state. So
181 * here priority is given to the EEH recovery. If it doesn't
182 * not resolve this issue, mpt3sas driver will consider this
183 * controller to non-operational state and remove the dead ioc
186 if (ioc->non_operational_loop++ < 5) {
187 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock,
193 * Call _scsih_flush_pending_cmds callback so that we flush all
194 * pending commands back to OS. This call is required to aovid
195 * deadlock at block layer. Dead IOC will fail to do diag reset,
196 * and this call is safe since dead ioc will never return any
197 * command back from HW.
199 ioc->schedule_dead_ioc_flush_running_cmds(ioc);
201 * Set remove_host flag early since kernel thread will
202 * take some time to execute.
204 ioc->remove_host = 1;
205 /*Remove the Dead Host */
206 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
207 "%s_dead_ioc_%d", ioc->driver_name, ioc->id);
210 "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
211 ioc->name, __func__);
214 "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
215 ioc->name, __func__);
216 return; /* don't rearm timer */
219 ioc->non_operational_loop = 0;
221 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
222 rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
223 pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name,
224 __func__, (rc == 0) ? "success" : "failed");
225 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
226 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
227 mpt3sas_base_fault_info(ioc, doorbell &
228 MPI2_DOORBELL_DATA_MASK);
229 if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
230 MPI2_IOC_STATE_OPERATIONAL)
231 return; /* don't rearm timer */
234 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
236 if (ioc->fault_reset_work_q)
237 queue_delayed_work(ioc->fault_reset_work_q,
238 &ioc->fault_reset_work,
239 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
240 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
244 * mpt3sas_base_start_watchdog - start the fault_reset_work_q
245 * @ioc: per adapter object
251 mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
255 if (ioc->fault_reset_work_q)
258 /* initialize fault polling */
260 INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
261 snprintf(ioc->fault_reset_work_q_name,
262 sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status",
263 ioc->driver_name, ioc->id);
264 ioc->fault_reset_work_q =
265 create_singlethread_workqueue(ioc->fault_reset_work_q_name);
266 if (!ioc->fault_reset_work_q) {
267 pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n",
268 ioc->name, __func__, __LINE__);
271 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
272 if (ioc->fault_reset_work_q)
273 queue_delayed_work(ioc->fault_reset_work_q,
274 &ioc->fault_reset_work,
275 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
276 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
280 * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
281 * @ioc: per adapter object
287 mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
290 struct workqueue_struct *wq;
292 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
293 wq = ioc->fault_reset_work_q;
294 ioc->fault_reset_work_q = NULL;
295 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
297 if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
299 destroy_workqueue(wq);
304 * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
305 * @ioc: per adapter object
306 * @fault_code: fault code
311 mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
313 pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n",
314 ioc->name, fault_code);
318 * mpt3sas_halt_firmware - halt's mpt controller firmware
319 * @ioc: per adapter object
321 * For debugging timeout related issues. Writing 0xCOFFEE00
322 * to the doorbell register will halt controller firmware. With
323 * the purpose to stop both driver and firmware, the enduser can
324 * obtain a ring buffer from controller UART.
327 mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
331 if (!ioc->fwfault_debug)
336 doorbell = readl(&ioc->chip->Doorbell);
337 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
338 mpt3sas_base_fault_info(ioc , doorbell);
340 writel(0xC0FFEE00, &ioc->chip->Doorbell);
341 pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n",
345 if (ioc->fwfault_debug == 2)
349 panic("panic in %s\n", __func__);
353 * _base_sas_ioc_info - verbose translation of the ioc status
354 * @ioc: per adapter object
355 * @mpi_reply: reply mf payload returned from firmware
356 * @request_hdr: request mf
361 _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
362 MPI2RequestHeader_t *request_hdr)
364 u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
368 char *func_str = NULL;
370 /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
371 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
372 request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
373 request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
376 if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
379 switch (ioc_status) {
381 /****************************************************************************
382 * Common IOCStatus values for all replies
383 ****************************************************************************/
385 case MPI2_IOCSTATUS_INVALID_FUNCTION:
386 desc = "invalid function";
388 case MPI2_IOCSTATUS_BUSY:
391 case MPI2_IOCSTATUS_INVALID_SGL:
392 desc = "invalid sgl";
394 case MPI2_IOCSTATUS_INTERNAL_ERROR:
395 desc = "internal error";
397 case MPI2_IOCSTATUS_INVALID_VPID:
398 desc = "invalid vpid";
400 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
401 desc = "insufficient resources";
403 case MPI2_IOCSTATUS_INSUFFICIENT_POWER:
404 desc = "insufficient power";
406 case MPI2_IOCSTATUS_INVALID_FIELD:
407 desc = "invalid field";
409 case MPI2_IOCSTATUS_INVALID_STATE:
410 desc = "invalid state";
412 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
413 desc = "op state not supported";
416 /****************************************************************************
417 * Config IOCStatus values
418 ****************************************************************************/
420 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
421 desc = "config invalid action";
423 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
424 desc = "config invalid type";
426 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
427 desc = "config invalid page";
429 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
430 desc = "config invalid data";
432 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
433 desc = "config no defaults";
435 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
436 desc = "config cant commit";
439 /****************************************************************************
441 ****************************************************************************/
443 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
444 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
445 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
446 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
447 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
448 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
449 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
450 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
451 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
452 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
453 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
454 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
457 /****************************************************************************
458 * For use by SCSI Initiator and SCSI Target end-to-end data protection
459 ****************************************************************************/
461 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
462 desc = "eedp guard error";
464 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
465 desc = "eedp ref tag error";
467 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
468 desc = "eedp app tag error";
471 /****************************************************************************
473 ****************************************************************************/
475 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
476 desc = "target invalid io index";
478 case MPI2_IOCSTATUS_TARGET_ABORTED:
479 desc = "target aborted";
481 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
482 desc = "target no conn retryable";
484 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
485 desc = "target no connection";
487 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
488 desc = "target xfer count mismatch";
490 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
491 desc = "target data offset error";
493 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
494 desc = "target too much write data";
496 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
497 desc = "target iu too short";
499 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
500 desc = "target ack nak timeout";
502 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
503 desc = "target nak received";
506 /****************************************************************************
507 * Serial Attached SCSI values
508 ****************************************************************************/
510 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
511 desc = "smp request failed";
513 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
514 desc = "smp data overrun";
517 /****************************************************************************
518 * Diagnostic Buffer Post / Diagnostic Release values
519 ****************************************************************************/
521 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
522 desc = "diagnostic released";
531 switch (request_hdr->Function) {
532 case MPI2_FUNCTION_CONFIG:
533 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
534 func_str = "config_page";
536 case MPI2_FUNCTION_SCSI_TASK_MGMT:
537 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
538 func_str = "task_mgmt";
540 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
541 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
542 func_str = "sas_iounit_ctl";
544 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
545 frame_sz = sizeof(Mpi2SepRequest_t);
546 func_str = "enclosure";
548 case MPI2_FUNCTION_IOC_INIT:
549 frame_sz = sizeof(Mpi2IOCInitRequest_t);
550 func_str = "ioc_init";
552 case MPI2_FUNCTION_PORT_ENABLE:
553 frame_sz = sizeof(Mpi2PortEnableRequest_t);
554 func_str = "port_enable";
556 case MPI2_FUNCTION_SMP_PASSTHROUGH:
557 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
558 func_str = "smp_passthru";
560 case MPI2_FUNCTION_NVME_ENCAPSULATED:
561 frame_sz = sizeof(Mpi26NVMeEncapsulatedRequest_t) +
563 func_str = "nvme_encapsulated";
567 func_str = "unknown";
571 pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
572 ioc->name, desc, ioc_status, request_hdr, func_str);
574 _debug_dump_mf(request_hdr, frame_sz/4);
578 * _base_display_event_data - verbose translation of firmware asyn events
579 * @ioc: per adapter object
580 * @mpi_reply: reply mf payload returned from firmware
585 _base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
586 Mpi2EventNotificationReply_t *mpi_reply)
591 if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
594 event = le16_to_cpu(mpi_reply->Event);
597 case MPI2_EVENT_LOG_DATA:
600 case MPI2_EVENT_STATE_CHANGE:
601 desc = "Status Change";
603 case MPI2_EVENT_HARD_RESET_RECEIVED:
604 desc = "Hard Reset Received";
606 case MPI2_EVENT_EVENT_CHANGE:
607 desc = "Event Change";
609 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
610 desc = "Device Status Change";
612 case MPI2_EVENT_IR_OPERATION_STATUS:
613 if (!ioc->hide_ir_msg)
614 desc = "IR Operation Status";
616 case MPI2_EVENT_SAS_DISCOVERY:
618 Mpi2EventDataSasDiscovery_t *event_data =
619 (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
620 pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name,
621 (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
623 if (event_data->DiscoveryStatus)
624 pr_cont(" discovery_status(0x%08x)",
625 le32_to_cpu(event_data->DiscoveryStatus));
629 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
630 desc = "SAS Broadcast Primitive";
632 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
633 desc = "SAS Init Device Status Change";
635 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
636 desc = "SAS Init Table Overflow";
638 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
639 desc = "SAS Topology Change List";
641 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
642 desc = "SAS Enclosure Device Status Change";
644 case MPI2_EVENT_IR_VOLUME:
645 if (!ioc->hide_ir_msg)
648 case MPI2_EVENT_IR_PHYSICAL_DISK:
649 if (!ioc->hide_ir_msg)
650 desc = "IR Physical Disk";
652 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
653 if (!ioc->hide_ir_msg)
654 desc = "IR Configuration Change List";
656 case MPI2_EVENT_LOG_ENTRY_ADDED:
657 if (!ioc->hide_ir_msg)
658 desc = "Log Entry Added";
660 case MPI2_EVENT_TEMP_THRESHOLD:
661 desc = "Temperature Threshold";
663 case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION:
664 desc = "Cable Event";
666 case MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE:
667 desc = "PCIE Device Status Change";
669 case MPI2_EVENT_PCIE_ENUMERATION:
671 Mpi26EventDataPCIeEnumeration_t *event_data =
672 (Mpi26EventDataPCIeEnumeration_t *)mpi_reply->EventData;
673 pr_info(MPT3SAS_FMT "PCIE Enumeration: (%s)", ioc->name,
674 (event_data->ReasonCode ==
675 MPI26_EVENT_PCIE_ENUM_RC_STARTED) ?
677 if (event_data->EnumerationStatus)
678 pr_info("enumeration_status(0x%08x)",
679 le32_to_cpu(event_data->EnumerationStatus));
683 case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
684 desc = "PCIE Topology Change List";
691 pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc);
695 * _base_sas_log_info - verbose translation of firmware log info
696 * @ioc: per adapter object
697 * @log_info: log info
702 _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
713 union loginfo_type sas_loginfo;
714 char *originator_str = NULL;
716 sas_loginfo.loginfo = log_info;
717 if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
720 /* each nexus loss loginfo */
721 if (log_info == 0x31170000)
724 /* eat the loginfos associated with task aborts */
725 if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
726 0x31140000 || log_info == 0x31130000))
729 switch (sas_loginfo.dw.originator) {
731 originator_str = "IOP";
734 originator_str = "PL";
737 if (!ioc->hide_ir_msg)
738 originator_str = "IR";
740 originator_str = "WarpDrive";
745 "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
747 originator_str, sas_loginfo.dw.code,
748 sas_loginfo.dw.subcode);
752 * _base_display_reply_info -
753 * @ioc: per adapter object
754 * @smid: system request message index
755 * @msix_index: MSIX table index supplied by the OS
756 * @reply: reply message frame(lower 32bit addr)
761 _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
764 MPI2DefaultReply_t *mpi_reply;
768 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
769 if (unlikely(!mpi_reply)) {
770 pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n",
771 ioc->name, __FILE__, __LINE__, __func__);
774 ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
776 if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
777 (ioc->logging_level & MPT_DEBUG_REPLY)) {
778 _base_sas_ioc_info(ioc , mpi_reply,
779 mpt3sas_base_get_msg_frame(ioc, smid));
782 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
783 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
784 _base_sas_log_info(ioc, loginfo);
787 if (ioc_status || loginfo) {
788 ioc_status &= MPI2_IOCSTATUS_MASK;
789 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
794 * mpt3sas_base_done - base internal command completion routine
795 * @ioc: per adapter object
796 * @smid: system request message index
797 * @msix_index: MSIX table index supplied by the OS
798 * @reply: reply message frame(lower 32bit addr)
800 * Return 1 meaning mf should be freed from _base_interrupt
801 * 0 means the mf is freed from this function.
804 mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
807 MPI2DefaultReply_t *mpi_reply;
809 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
810 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
811 return mpt3sas_check_for_pending_internal_cmds(ioc, smid);
813 if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
816 ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
818 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
819 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
821 ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
823 complete(&ioc->base_cmds.done);
828 * _base_async_event - main callback handler for firmware asyn events
829 * @ioc: per adapter object
830 * @msix_index: MSIX table index supplied by the OS
831 * @reply: reply message frame(lower 32bit addr)
833 * Return 1 meaning mf should be freed from _base_interrupt
834 * 0 means the mf is freed from this function.
837 _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
839 Mpi2EventNotificationReply_t *mpi_reply;
840 Mpi2EventAckRequest_t *ack_request;
842 struct _event_ack_list *delayed_event_ack;
844 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
847 if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
850 _base_display_event_data(ioc, mpi_reply);
852 if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
854 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
856 delayed_event_ack = kzalloc(sizeof(*delayed_event_ack),
858 if (!delayed_event_ack)
860 INIT_LIST_HEAD(&delayed_event_ack->list);
861 delayed_event_ack->Event = mpi_reply->Event;
862 delayed_event_ack->EventContext = mpi_reply->EventContext;
863 list_add_tail(&delayed_event_ack->list,
864 &ioc->delayed_event_ack_list);
865 dewtprintk(ioc, pr_info(MPT3SAS_FMT
866 "DELAYED: EVENT ACK: event (0x%04x)\n",
867 ioc->name, le16_to_cpu(mpi_reply->Event)));
871 ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
872 memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
873 ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
874 ack_request->Event = mpi_reply->Event;
875 ack_request->EventContext = mpi_reply->EventContext;
876 ack_request->VF_ID = 0; /* TODO */
877 ack_request->VP_ID = 0;
878 ioc->put_smid_default(ioc, smid);
882 /* scsih callback handler */
883 mpt3sas_scsih_event_callback(ioc, msix_index, reply);
885 /* ctl callback handler */
886 mpt3sas_ctl_event_callback(ioc, msix_index, reply);
891 static struct scsiio_tracker *
892 _get_st_from_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
894 struct scsi_cmnd *cmd;
896 if (WARN_ON(!smid) ||
897 WARN_ON(smid >= ioc->hi_priority_smid))
900 cmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid);
902 return scsi_cmd_priv(cmd);
908 * _base_get_cb_idx - obtain the callback index
909 * @ioc: per adapter object
910 * @smid: system request message index
912 * Return callback index.
915 _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
918 u16 ctl_smid = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT + 1;
921 if (smid < ioc->hi_priority_smid) {
922 struct scsiio_tracker *st;
924 if (smid < ctl_smid) {
925 st = _get_st_from_smid(ioc, smid);
928 } else if (smid == ctl_smid)
929 cb_idx = ioc->ctl_cb_idx;
930 } else if (smid < ioc->internal_smid) {
931 i = smid - ioc->hi_priority_smid;
932 cb_idx = ioc->hpr_lookup[i].cb_idx;
933 } else if (smid <= ioc->hba_queue_depth) {
934 i = smid - ioc->internal_smid;
935 cb_idx = ioc->internal_lookup[i].cb_idx;
941 * _base_mask_interrupts - disable interrupts
942 * @ioc: per adapter object
944 * Disabling ResetIRQ, Reply and Doorbell Interrupts
949 _base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
953 ioc->mask_interrupts = 1;
954 him_register = readl(&ioc->chip->HostInterruptMask);
955 him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
956 writel(him_register, &ioc->chip->HostInterruptMask);
957 readl(&ioc->chip->HostInterruptMask);
961 * _base_unmask_interrupts - enable interrupts
962 * @ioc: per adapter object
964 * Enabling only Reply Interrupts
969 _base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
973 him_register = readl(&ioc->chip->HostInterruptMask);
974 him_register &= ~MPI2_HIM_RIM;
975 writel(him_register, &ioc->chip->HostInterruptMask);
976 ioc->mask_interrupts = 0;
979 union reply_descriptor {
988 * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
989 * @irq: irq number (not used)
990 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
991 * @r: pt_regs pointer (not used)
993 * Return IRQ_HANDLE if processed, else IRQ_NONE.
996 _base_interrupt(int irq, void *bus_id)
998 struct adapter_reply_queue *reply_q = bus_id;
999 union reply_descriptor rd;
1001 u8 request_desript_type;
1005 u8 msix_index = reply_q->msix_index;
1006 struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
1007 Mpi2ReplyDescriptorsUnion_t *rpf;
1010 if (ioc->mask_interrupts)
1013 if (!atomic_add_unless(&reply_q->busy, 1, 1))
1016 rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
1017 request_desript_type = rpf->Default.ReplyFlags
1018 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1019 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
1020 atomic_dec(&reply_q->busy);
1027 rd.word = le64_to_cpu(rpf->Words);
1028 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
1031 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
1032 if (request_desript_type ==
1033 MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
1034 request_desript_type ==
1035 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS ||
1036 request_desript_type ==
1037 MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS) {
1038 cb_idx = _base_get_cb_idx(ioc, smid);
1039 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
1040 (likely(mpt_callbacks[cb_idx] != NULL))) {
1041 rc = mpt_callbacks[cb_idx](ioc, smid,
1044 mpt3sas_base_free_smid(ioc, smid);
1046 } else if (request_desript_type ==
1047 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
1048 reply = le32_to_cpu(
1049 rpf->AddressReply.ReplyFrameAddress);
1050 if (reply > ioc->reply_dma_max_address ||
1051 reply < ioc->reply_dma_min_address)
1054 cb_idx = _base_get_cb_idx(ioc, smid);
1055 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
1056 (likely(mpt_callbacks[cb_idx] != NULL))) {
1057 rc = mpt_callbacks[cb_idx](ioc, smid,
1060 _base_display_reply_info(ioc,
1061 smid, msix_index, reply);
1063 mpt3sas_base_free_smid(ioc,
1067 _base_async_event(ioc, msix_index, reply);
1070 /* reply free queue handling */
1072 ioc->reply_free_host_index =
1073 (ioc->reply_free_host_index ==
1074 (ioc->reply_free_queue_depth - 1)) ?
1075 0 : ioc->reply_free_host_index + 1;
1076 ioc->reply_free[ioc->reply_free_host_index] =
1078 writel(ioc->reply_free_host_index,
1079 &ioc->chip->ReplyFreeHostIndex);
1083 rpf->Words = cpu_to_le64(ULLONG_MAX);
1084 reply_q->reply_post_host_index =
1085 (reply_q->reply_post_host_index ==
1086 (ioc->reply_post_queue_depth - 1)) ? 0 :
1087 reply_q->reply_post_host_index + 1;
1088 request_desript_type =
1089 reply_q->reply_post_free[reply_q->reply_post_host_index].
1090 Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1092 /* Update the reply post host index after continuously
1093 * processing the threshold number of Reply Descriptors.
1094 * So that FW can find enough entries to post the Reply
1095 * Descriptors in the reply descriptor post queue.
1097 if (completed_cmds > ioc->hba_queue_depth/3) {
1098 if (ioc->combined_reply_queue) {
1099 writel(reply_q->reply_post_host_index |
1100 ((msix_index & 7) <<
1101 MPI2_RPHI_MSIX_INDEX_SHIFT),
1102 ioc->replyPostRegisterIndex[msix_index/8]);
1104 writel(reply_q->reply_post_host_index |
1106 MPI2_RPHI_MSIX_INDEX_SHIFT),
1107 &ioc->chip->ReplyPostHostIndex);
1111 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
1113 if (!reply_q->reply_post_host_index)
1114 rpf = reply_q->reply_post_free;
1121 if (!completed_cmds) {
1122 atomic_dec(&reply_q->busy);
1126 if (ioc->is_warpdrive) {
1127 writel(reply_q->reply_post_host_index,
1128 ioc->reply_post_host_index[msix_index]);
1129 atomic_dec(&reply_q->busy);
1133 /* Update Reply Post Host Index.
1134 * For those HBA's which support combined reply queue feature
1135 * 1. Get the correct Supplemental Reply Post Host Index Register.
1136 * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
1137 * Index Register address bank i.e replyPostRegisterIndex[],
1138 * 2. Then update this register with new reply host index value
1139 * in ReplyPostIndex field and the MSIxIndex field with
1140 * msix_index value reduced to a value between 0 and 7,
1141 * using a modulo 8 operation. Since each Supplemental Reply Post
1142 * Host Index Register supports 8 MSI-X vectors.
1144 * For other HBA's just update the Reply Post Host Index register with
1145 * new reply host index value in ReplyPostIndex Field and msix_index
1146 * value in MSIxIndex field.
1148 if (ioc->combined_reply_queue)
1149 writel(reply_q->reply_post_host_index | ((msix_index & 7) <<
1150 MPI2_RPHI_MSIX_INDEX_SHIFT),
1151 ioc->replyPostRegisterIndex[msix_index/8]);
1153 writel(reply_q->reply_post_host_index | (msix_index <<
1154 MPI2_RPHI_MSIX_INDEX_SHIFT),
1155 &ioc->chip->ReplyPostHostIndex);
1156 atomic_dec(&reply_q->busy);
1161 * _base_is_controller_msix_enabled - is controller support muli-reply queues
1162 * @ioc: per adapter object
1166 _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
1168 return (ioc->facts.IOCCapabilities &
1169 MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
1173 * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts
1174 * @ioc: per adapter object
1175 * Context: non ISR conext
1177 * Called when a Task Management request has completed.
1182 mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc)
1184 struct adapter_reply_queue *reply_q;
1186 /* If MSIX capability is turned off
1187 * then multi-queues are not enabled
1189 if (!_base_is_controller_msix_enabled(ioc))
1192 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1193 if (ioc->shost_recovery || ioc->remove_host ||
1194 ioc->pci_error_recovery)
1196 /* TMs are on msix_index == 0 */
1197 if (reply_q->msix_index == 0)
1199 synchronize_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index));
1204 * mpt3sas_base_release_callback_handler - clear interrupt callback handler
1205 * @cb_idx: callback index
1210 mpt3sas_base_release_callback_handler(u8 cb_idx)
1212 mpt_callbacks[cb_idx] = NULL;
1216 * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
1217 * @cb_func: callback function
1222 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
1226 for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
1227 if (mpt_callbacks[cb_idx] == NULL)
1230 mpt_callbacks[cb_idx] = cb_func;
1235 * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
1240 mpt3sas_base_initialize_callback_handler(void)
1244 for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
1245 mpt3sas_base_release_callback_handler(cb_idx);
1250 * _base_build_zero_len_sge - build zero length sg entry
1251 * @ioc: per adapter object
1252 * @paddr: virtual address for SGE
1254 * Create a zero length scatter gather entry to insure the IOCs hardware has
1255 * something to use if the target device goes brain dead and tries
1256 * to send data even when none is asked for.
1261 _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1263 u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
1264 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
1265 MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
1266 MPI2_SGE_FLAGS_SHIFT);
1267 ioc->base_add_sg_single(paddr, flags_length, -1);
1271 * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
1272 * @paddr: virtual address for SGE
1273 * @flags_length: SGE flags and data transfer length
1274 * @dma_addr: Physical address
1279 _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1281 Mpi2SGESimple32_t *sgel = paddr;
1283 flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
1284 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1285 sgel->FlagsLength = cpu_to_le32(flags_length);
1286 sgel->Address = cpu_to_le32(dma_addr);
1291 * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
1292 * @paddr: virtual address for SGE
1293 * @flags_length: SGE flags and data transfer length
1294 * @dma_addr: Physical address
1299 _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1301 Mpi2SGESimple64_t *sgel = paddr;
1303 flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
1304 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1305 sgel->FlagsLength = cpu_to_le32(flags_length);
1306 sgel->Address = cpu_to_le64(dma_addr);
1310 * _base_get_chain_buffer_tracker - obtain chain tracker
1311 * @ioc: per adapter object
1312 * @scmd: SCSI commands of the IO request
1314 * Returns chain tracker(from ioc->free_chain_list)
1316 static struct chain_tracker *
1317 _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc,
1318 struct scsi_cmnd *scmd)
1320 struct chain_tracker *chain_req;
1321 struct scsiio_tracker *st = scsi_cmd_priv(scmd);
1322 unsigned long flags;
1324 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1325 if (list_empty(&ioc->free_chain_list)) {
1326 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1327 dfailprintk(ioc, pr_warn(MPT3SAS_FMT
1328 "chain buffers not available\n", ioc->name));
1331 chain_req = list_entry(ioc->free_chain_list.next,
1332 struct chain_tracker, tracker_list);
1333 list_del_init(&chain_req->tracker_list);
1334 list_add_tail(&chain_req->tracker_list, &st->chain_list);
1335 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1341 * _base_build_sg - build generic sg
1342 * @ioc: per adapter object
1343 * @psge: virtual address for SGE
1344 * @data_out_dma: physical address for WRITES
1345 * @data_out_sz: data xfer size for WRITES
1346 * @data_in_dma: physical address for READS
1347 * @data_in_sz: data xfer size for READS
1352 _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
1353 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1358 if (!data_out_sz && !data_in_sz) {
1359 _base_build_zero_len_sge(ioc, psge);
1363 if (data_out_sz && data_in_sz) {
1364 /* WRITE sgel first */
1365 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1366 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
1367 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1368 ioc->base_add_sg_single(psge, sgl_flags |
1369 data_out_sz, data_out_dma);
1372 psge += ioc->sge_size;
1374 /* READ sgel last */
1375 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1376 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1377 MPI2_SGE_FLAGS_END_OF_LIST);
1378 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1379 ioc->base_add_sg_single(psge, sgl_flags |
1380 data_in_sz, data_in_dma);
1381 } else if (data_out_sz) /* WRITE */ {
1382 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1383 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1384 MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
1385 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1386 ioc->base_add_sg_single(psge, sgl_flags |
1387 data_out_sz, data_out_dma);
1388 } else if (data_in_sz) /* READ */ {
1389 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1390 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1391 MPI2_SGE_FLAGS_END_OF_LIST);
1392 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1393 ioc->base_add_sg_single(psge, sgl_flags |
1394 data_in_sz, data_in_dma);
1398 /* IEEE format sgls */
1401 * _base_build_nvme_prp - This function is called for NVMe end devices to build
1402 * a native SGL (NVMe PRP). The native SGL is built starting in the first PRP
1403 * entry of the NVMe message (PRP1). If the data buffer is small enough to be
1404 * described entirely using PRP1, then PRP2 is not used. If needed, PRP2 is
1405 * used to describe a larger data buffer. If the data buffer is too large to
1406 * describe using the two PRP entriess inside the NVMe message, then PRP1
1407 * describes the first data memory segment, and PRP2 contains a pointer to a PRP
1408 * list located elsewhere in memory to describe the remaining data memory
1409 * segments. The PRP list will be contiguous.
1411 * The native SGL for NVMe devices is a Physical Region Page (PRP). A PRP
1412 * consists of a list of PRP entries to describe a number of noncontigous
1413 * physical memory segments as a single memory buffer, just as a SGL does. Note
1414 * however, that this function is only used by the IOCTL call, so the memory
1415 * given will be guaranteed to be contiguous. There is no need to translate
1416 * non-contiguous SGL into a PRP in this case. All PRPs will describe
1417 * contiguous space that is one page size each.
1419 * Each NVMe message contains two PRP entries. The first (PRP1) either contains
1420 * a PRP list pointer or a PRP element, depending upon the command. PRP2
1421 * contains the second PRP element if the memory being described fits within 2
1422 * PRP entries, or a PRP list pointer if the PRP spans more than two entries.
1424 * A PRP list pointer contains the address of a PRP list, structured as a linear
1425 * array of PRP entries. Each PRP entry in this list describes a segment of
1428 * Each 64-bit PRP entry comprises an address and an offset field. The address
1429 * always points at the beginning of a 4KB physical memory page, and the offset
1430 * describes where within that 4KB page the memory segment begins. Only the
1431 * first element in a PRP list may contain a non-zero offest, implying that all
1432 * memory segments following the first begin at the start of a 4KB page.
1434 * Each PRP element normally describes 4KB of physical memory, with exceptions
1435 * for the first and last elements in the list. If the memory being described
1436 * by the list begins at a non-zero offset within the first 4KB page, then the
1437 * first PRP element will contain a non-zero offset indicating where the region
1438 * begins within the 4KB page. The last memory segment may end before the end
1439 * of the 4KB segment, depending upon the overall size of the memory being
1440 * described by the PRP list.
1442 * Since PRP entries lack any indication of size, the overall data buffer length
1443 * is used to determine where the end of the data memory buffer is located, and
1444 * how many PRP entries are required to describe it.
1446 * @ioc: per adapter object
1447 * @smid: system request message index for getting asscociated SGL
1448 * @nvme_encap_request: the NVMe request msg frame pointer
1449 * @data_out_dma: physical address for WRITES
1450 * @data_out_sz: data xfer size for WRITES
1451 * @data_in_dma: physical address for READS
1452 * @data_in_sz: data xfer size for READS
1457 _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid,
1458 Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request,
1459 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1462 int prp_size = NVME_PRP_SIZE;
1463 __le64 *prp_entry, *prp1_entry, *prp2_entry;
1465 dma_addr_t prp_entry_dma, prp_page_dma, dma_addr;
1466 u32 offset, entry_len;
1467 u32 page_mask_result, page_mask;
1471 * Not all commands require a data transfer. If no data, just return
1472 * without constructing any PRP.
1474 if (!data_in_sz && !data_out_sz)
1477 * Set pointers to PRP1 and PRP2, which are in the NVMe command.
1478 * PRP1 is located at a 24 byte offset from the start of the NVMe
1479 * command. Then set the current PRP entry pointer to PRP1.
1481 prp1_entry = (__le64 *)(nvme_encap_request->NVMe_Command +
1482 NVME_CMD_PRP1_OFFSET);
1483 prp2_entry = (__le64 *)(nvme_encap_request->NVMe_Command +
1484 NVME_CMD_PRP2_OFFSET);
1485 prp_entry = prp1_entry;
1487 * For the PRP entries, use the specially allocated buffer of
1488 * contiguous memory.
1490 prp_page = (__le64 *)mpt3sas_base_get_pcie_sgl(ioc, smid);
1491 prp_page_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid);
1494 * Check if we are within 1 entry of a page boundary we don't
1495 * want our first entry to be a PRP List entry.
1497 page_mask = ioc->page_size - 1;
1498 page_mask_result = (uintptr_t)((u8 *)prp_page + prp_size) & page_mask;
1499 if (!page_mask_result) {
1500 /* Bump up to next page boundary. */
1501 prp_page = (__le64 *)((u8 *)prp_page + prp_size);
1502 prp_page_dma = prp_page_dma + prp_size;
1506 * Set PRP physical pointer, which initially points to the current PRP
1509 prp_entry_dma = prp_page_dma;
1511 /* Get physical address and length of the data buffer. */
1513 dma_addr = data_in_dma;
1514 length = data_in_sz;
1516 dma_addr = data_out_dma;
1517 length = data_out_sz;
1520 /* Loop while the length is not zero. */
1523 * Check if we need to put a list pointer here if we are at
1524 * page boundary - prp_size (8 bytes).
1526 page_mask_result = (prp_entry_dma + prp_size) & page_mask;
1527 if (!page_mask_result) {
1529 * This is the last entry in a PRP List, so we need to
1530 * put a PRP list pointer here. What this does is:
1531 * - bump the current memory pointer to the next
1532 * address, which will be the next full page.
1533 * - set the PRP Entry to point to that page. This
1534 * is now the PRP List pointer.
1535 * - bump the PRP Entry pointer the start of the
1536 * next page. Since all of this PRP memory is
1537 * contiguous, no need to get a new page - it's
1538 * just the next address.
1541 *prp_entry = cpu_to_le64(prp_entry_dma);
1545 /* Need to handle if entry will be part of a page. */
1546 offset = dma_addr & page_mask;
1547 entry_len = ioc->page_size - offset;
1549 if (prp_entry == prp1_entry) {
1551 * Must fill in the first PRP pointer (PRP1) before
1554 *prp1_entry = cpu_to_le64(dma_addr);
1557 * Now point to the second PRP entry within the
1560 prp_entry = prp2_entry;
1561 } else if (prp_entry == prp2_entry) {
1563 * Should the PRP2 entry be a PRP List pointer or just
1564 * a regular PRP pointer? If there is more than one
1565 * more page of data, must use a PRP List pointer.
1567 if (length > ioc->page_size) {
1569 * PRP2 will contain a PRP List pointer because
1570 * more PRP's are needed with this command. The
1571 * list will start at the beginning of the
1572 * contiguous buffer.
1574 *prp2_entry = cpu_to_le64(prp_entry_dma);
1577 * The next PRP Entry will be the start of the
1580 prp_entry = prp_page;
1583 * After this, the PRP Entries are complete.
1584 * This command uses 2 PRP's and no PRP list.
1586 *prp2_entry = cpu_to_le64(dma_addr);
1590 * Put entry in list and bump the addresses.
1592 * After PRP1 and PRP2 are filled in, this will fill in
1593 * all remaining PRP entries in a PRP List, one per
1594 * each time through the loop.
1596 *prp_entry = cpu_to_le64(dma_addr);
1602 * Bump the phys address of the command's data buffer by the
1605 dma_addr += entry_len;
1607 /* Decrement length accounting for last partial page. */
1608 if (entry_len > length)
1611 length -= entry_len;
1616 * base_make_prp_nvme -
1617 * Prepare PRPs(Physical Region Page)- SGLs specific to NVMe drives only
1619 * @ioc: per adapter object
1620 * @scmd: SCSI command from the mid-layer
1621 * @mpi_request: mpi request
1623 * @sge_count: scatter gather element count.
1625 * Returns: true: PRPs are built
1626 * false: IEEE SGLs needs to be built
1629 base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc,
1630 struct scsi_cmnd *scmd,
1631 Mpi25SCSIIORequest_t *mpi_request,
1632 u16 smid, int sge_count)
1634 int sge_len, num_prp_in_chain = 0;
1635 Mpi25IeeeSgeChain64_t *main_chain_element, *ptr_first_sgl;
1637 dma_addr_t msg_dma, sge_addr, offset;
1638 u32 page_mask, page_mask_result;
1639 struct scatterlist *sg_scmd;
1641 int data_len = scsi_bufflen(scmd);
1644 nvme_pg_size = max_t(u32, ioc->page_size, NVME_PRP_PAGE_SIZE);
1646 * Nvme has a very convoluted prp format. One prp is required
1647 * for each page or partial page. Driver need to split up OS sg_list
1648 * entries if it is longer than one page or cross a page
1649 * boundary. Driver also have to insert a PRP list pointer entry as
1650 * the last entry in each physical page of the PRP list.
1652 * NOTE: The first PRP "entry" is actually placed in the first
1653 * SGL entry in the main message as IEEE 64 format. The 2nd
1654 * entry in the main message is the chain element, and the rest
1655 * of the PRP entries are built in the contiguous pcie buffer.
1657 page_mask = nvme_pg_size - 1;
1660 * Native SGL is needed.
1661 * Put a chain element in main message frame that points to the first
1664 * NOTE: The ChainOffset field must be 0 when using a chain pointer to
1668 /* Set main message chain element pointer */
1669 main_chain_element = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL;
1671 * For NVMe the chain element needs to be the 2nd SG entry in the main
1674 main_chain_element = (Mpi25IeeeSgeChain64_t *)
1675 ((u8 *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64));
1678 * For the PRP entries, use the specially allocated buffer of
1679 * contiguous memory. Normal chain buffers can't be used
1680 * because each chain buffer would need to be the size of an OS
1683 curr_buff = mpt3sas_base_get_pcie_sgl(ioc, smid);
1684 msg_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid);
1686 main_chain_element->Address = cpu_to_le64(msg_dma);
1687 main_chain_element->NextChainOffset = 0;
1688 main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
1689 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
1690 MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP;
1692 /* Build first prp, sge need not to be page aligned*/
1693 ptr_first_sgl = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL;
1694 sg_scmd = scsi_sglist(scmd);
1695 sge_addr = sg_dma_address(sg_scmd);
1696 sge_len = sg_dma_len(sg_scmd);
1698 offset = sge_addr & page_mask;
1699 first_prp_len = nvme_pg_size - offset;
1701 ptr_first_sgl->Address = cpu_to_le64(sge_addr);
1702 ptr_first_sgl->Length = cpu_to_le32(first_prp_len);
1704 data_len -= first_prp_len;
1706 if (sge_len > first_prp_len) {
1707 sge_addr += first_prp_len;
1708 sge_len -= first_prp_len;
1709 } else if (data_len && (sge_len == first_prp_len)) {
1710 sg_scmd = sg_next(sg_scmd);
1711 sge_addr = sg_dma_address(sg_scmd);
1712 sge_len = sg_dma_len(sg_scmd);
1716 offset = sge_addr & page_mask;
1718 /* Put PRP pointer due to page boundary*/
1719 page_mask_result = (uintptr_t)(curr_buff + 1) & page_mask;
1720 if (unlikely(!page_mask_result)) {
1721 scmd_printk(KERN_NOTICE,
1722 scmd, "page boundary curr_buff: 0x%p\n",
1725 *curr_buff = cpu_to_le64(msg_dma);
1730 *curr_buff = cpu_to_le64(sge_addr);
1735 sge_addr += nvme_pg_size;
1736 sge_len -= nvme_pg_size;
1737 data_len -= nvme_pg_size;
1745 sg_scmd = sg_next(sg_scmd);
1746 sge_addr = sg_dma_address(sg_scmd);
1747 sge_len = sg_dma_len(sg_scmd);
1750 main_chain_element->Length =
1751 cpu_to_le32(num_prp_in_chain * sizeof(u64));
1756 base_is_prp_possible(struct MPT3SAS_ADAPTER *ioc,
1757 struct _pcie_device *pcie_device, struct scsi_cmnd *scmd, int sge_count)
1759 u32 data_length = 0;
1760 struct scatterlist *sg_scmd;
1761 bool build_prp = true;
1763 data_length = scsi_bufflen(scmd);
1764 sg_scmd = scsi_sglist(scmd);
1766 /* If Datalenth is <= 16K and number of SGE’s entries are <= 2
1769 if ((data_length <= NVME_PRP_PAGE_SIZE*4) && (sge_count <= 2))
1776 * _base_check_pcie_native_sgl - This function is called for PCIe end devices to
1777 * determine if the driver needs to build a native SGL. If so, that native
1778 * SGL is built in the special contiguous buffers allocated especially for
1779 * PCIe SGL creation. If the driver will not build a native SGL, return
1780 * TRUE and a normal IEEE SGL will be built. Currently this routine
1782 * @ioc: per adapter object
1783 * @mpi_request: mf request pointer
1784 * @smid: system request message index
1785 * @scmd: scsi command
1786 * @pcie_device: points to the PCIe device's info
1788 * Returns 0 if native SGL was built, 1 if no SGL was built
1791 _base_check_pcie_native_sgl(struct MPT3SAS_ADAPTER *ioc,
1792 Mpi25SCSIIORequest_t *mpi_request, u16 smid, struct scsi_cmnd *scmd,
1793 struct _pcie_device *pcie_device)
1795 struct scatterlist *sg_scmd;
1798 /* Get the SG list pointer and info. */
1799 sg_scmd = scsi_sglist(scmd);
1800 sges_left = scsi_dma_map(scmd);
1801 if (sges_left < 0) {
1802 sdev_printk(KERN_ERR, scmd->device,
1803 "scsi_dma_map failed: request for %d bytes!\n",
1804 scsi_bufflen(scmd));
1808 /* Check if we need to build a native SG list. */
1809 if (base_is_prp_possible(ioc, pcie_device,
1810 scmd, sges_left) == 0) {
1811 /* We built a native SG list, just return. */
1816 * Build native NVMe PRP.
1818 base_make_prp_nvme(ioc, scmd, mpi_request,
1823 scsi_dma_unmap(scmd);
1828 * _base_add_sg_single_ieee - add sg element for IEEE format
1829 * @paddr: virtual address for SGE
1831 * @chain_offset: number of 128 byte elements from start of segment
1832 * @length: data transfer length
1833 * @dma_addr: Physical address
1838 _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
1839 dma_addr_t dma_addr)
1841 Mpi25IeeeSgeChain64_t *sgel = paddr;
1843 sgel->Flags = flags;
1844 sgel->NextChainOffset = chain_offset;
1845 sgel->Length = cpu_to_le32(length);
1846 sgel->Address = cpu_to_le64(dma_addr);
1850 * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
1851 * @ioc: per adapter object
1852 * @paddr: virtual address for SGE
1854 * Create a zero length scatter gather entry to insure the IOCs hardware has
1855 * something to use if the target device goes brain dead and tries
1856 * to send data even when none is asked for.
1861 _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1863 u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1864 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
1865 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
1867 _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
1871 * _base_build_sg_scmd - main sg creation routine
1872 * pcie_device is unused here!
1873 * @ioc: per adapter object
1874 * @scmd: scsi command
1875 * @smid: system request message index
1876 * @unused: unused pcie_device pointer
1879 * The main routine that builds scatter gather table from a given
1880 * scsi request sent via the .queuecommand main handler.
1882 * Returns 0 success, anything else error
1885 _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc,
1886 struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *unused)
1888 Mpi2SCSIIORequest_t *mpi_request;
1889 dma_addr_t chain_dma;
1890 struct scatterlist *sg_scmd;
1891 void *sg_local, *chain;
1896 u32 sges_in_segment;
1898 u32 sgl_flags_last_element;
1899 u32 sgl_flags_end_buffer;
1900 struct chain_tracker *chain_req;
1902 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1904 /* init scatter gather flags */
1905 sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT;
1906 if (scmd->sc_data_direction == DMA_TO_DEVICE)
1907 sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
1908 sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT)
1909 << MPI2_SGE_FLAGS_SHIFT;
1910 sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT |
1911 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST)
1912 << MPI2_SGE_FLAGS_SHIFT;
1913 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1915 sg_scmd = scsi_sglist(scmd);
1916 sges_left = scsi_dma_map(scmd);
1917 if (sges_left < 0) {
1918 sdev_printk(KERN_ERR, scmd->device,
1919 "pci_map_sg failed: request for %d bytes!\n",
1920 scsi_bufflen(scmd));
1924 sg_local = &mpi_request->SGL;
1925 sges_in_segment = ioc->max_sges_in_main_message;
1926 if (sges_left <= sges_in_segment)
1927 goto fill_in_last_segment;
1929 mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) +
1930 (sges_in_segment * ioc->sge_size))/4;
1932 /* fill in main message segment when there is a chain following */
1933 while (sges_in_segment) {
1934 if (sges_in_segment == 1)
1935 ioc->base_add_sg_single(sg_local,
1936 sgl_flags_last_element | sg_dma_len(sg_scmd),
1937 sg_dma_address(sg_scmd));
1939 ioc->base_add_sg_single(sg_local, sgl_flags |
1940 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1941 sg_scmd = sg_next(sg_scmd);
1942 sg_local += ioc->sge_size;
1947 /* initializing the chain flags and pointers */
1948 chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT;
1949 chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
1952 chain = chain_req->chain_buffer;
1953 chain_dma = chain_req->chain_buffer_dma;
1955 sges_in_segment = (sges_left <=
1956 ioc->max_sges_in_chain_message) ? sges_left :
1957 ioc->max_sges_in_chain_message;
1958 chain_offset = (sges_left == sges_in_segment) ?
1959 0 : (sges_in_segment * ioc->sge_size)/4;
1960 chain_length = sges_in_segment * ioc->sge_size;
1962 chain_offset = chain_offset <<
1963 MPI2_SGE_CHAIN_OFFSET_SHIFT;
1964 chain_length += ioc->sge_size;
1966 ioc->base_add_sg_single(sg_local, chain_flags | chain_offset |
1967 chain_length, chain_dma);
1970 goto fill_in_last_segment;
1972 /* fill in chain segments */
1973 while (sges_in_segment) {
1974 if (sges_in_segment == 1)
1975 ioc->base_add_sg_single(sg_local,
1976 sgl_flags_last_element |
1977 sg_dma_len(sg_scmd),
1978 sg_dma_address(sg_scmd));
1980 ioc->base_add_sg_single(sg_local, sgl_flags |
1981 sg_dma_len(sg_scmd),
1982 sg_dma_address(sg_scmd));
1983 sg_scmd = sg_next(sg_scmd);
1984 sg_local += ioc->sge_size;
1989 chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
1992 chain = chain_req->chain_buffer;
1993 chain_dma = chain_req->chain_buffer_dma;
1997 fill_in_last_segment:
1999 /* fill the last segment */
2002 ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer |
2003 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2005 ioc->base_add_sg_single(sg_local, sgl_flags |
2006 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2007 sg_scmd = sg_next(sg_scmd);
2008 sg_local += ioc->sge_size;
2016 * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
2017 * @ioc: per adapter object
2018 * @scmd: scsi command
2019 * @smid: system request message index
2020 * @pcie_device: Pointer to pcie_device. If set, the pcie native sgl will be
2021 * constructed on need.
2024 * The main routine that builds scatter gather table from a given
2025 * scsi request sent via the .queuecommand main handler.
2027 * Returns 0 success, anything else error
2030 _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
2031 struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *pcie_device)
2033 Mpi25SCSIIORequest_t *mpi_request;
2034 dma_addr_t chain_dma;
2035 struct scatterlist *sg_scmd;
2036 void *sg_local, *chain;
2040 u32 sges_in_segment;
2041 u8 simple_sgl_flags;
2042 u8 simple_sgl_flags_last;
2044 struct chain_tracker *chain_req;
2046 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
2048 /* init scatter gather flags */
2049 simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2050 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2051 simple_sgl_flags_last = simple_sgl_flags |
2052 MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
2053 chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
2054 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2056 /* Check if we need to build a native SG list. */
2057 if ((pcie_device) && (_base_check_pcie_native_sgl(ioc, mpi_request,
2058 smid, scmd, pcie_device) == 0)) {
2059 /* We built a native SG list, just return. */
2063 sg_scmd = scsi_sglist(scmd);
2064 sges_left = scsi_dma_map(scmd);
2065 if (sges_left < 0) {
2066 sdev_printk(KERN_ERR, scmd->device,
2067 "pci_map_sg failed: request for %d bytes!\n",
2068 scsi_bufflen(scmd));
2072 sg_local = &mpi_request->SGL;
2073 sges_in_segment = (ioc->request_sz -
2074 offsetof(Mpi25SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
2075 if (sges_left <= sges_in_segment)
2076 goto fill_in_last_segment;
2078 mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
2079 (offsetof(Mpi25SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
2081 /* fill in main message segment when there is a chain following */
2082 while (sges_in_segment > 1) {
2083 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2084 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2085 sg_scmd = sg_next(sg_scmd);
2086 sg_local += ioc->sge_size_ieee;
2091 /* initializing the pointers */
2092 chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2095 chain = chain_req->chain_buffer;
2096 chain_dma = chain_req->chain_buffer_dma;
2098 sges_in_segment = (sges_left <=
2099 ioc->max_sges_in_chain_message) ? sges_left :
2100 ioc->max_sges_in_chain_message;
2101 chain_offset = (sges_left == sges_in_segment) ?
2102 0 : sges_in_segment;
2103 chain_length = sges_in_segment * ioc->sge_size_ieee;
2105 chain_length += ioc->sge_size_ieee;
2106 _base_add_sg_single_ieee(sg_local, chain_sgl_flags,
2107 chain_offset, chain_length, chain_dma);
2111 goto fill_in_last_segment;
2113 /* fill in chain segments */
2114 while (sges_in_segment) {
2115 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2116 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2117 sg_scmd = sg_next(sg_scmd);
2118 sg_local += ioc->sge_size_ieee;
2123 chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2126 chain = chain_req->chain_buffer;
2127 chain_dma = chain_req->chain_buffer_dma;
2131 fill_in_last_segment:
2133 /* fill the last segment */
2134 while (sges_left > 0) {
2136 _base_add_sg_single_ieee(sg_local,
2137 simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
2138 sg_dma_address(sg_scmd));
2140 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2141 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2142 sg_scmd = sg_next(sg_scmd);
2143 sg_local += ioc->sge_size_ieee;
2151 * _base_build_sg_ieee - build generic sg for IEEE format
2152 * @ioc: per adapter object
2153 * @psge: virtual address for SGE
2154 * @data_out_dma: physical address for WRITES
2155 * @data_out_sz: data xfer size for WRITES
2156 * @data_in_dma: physical address for READS
2157 * @data_in_sz: data xfer size for READS
2162 _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
2163 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
2168 if (!data_out_sz && !data_in_sz) {
2169 _base_build_zero_len_sge_ieee(ioc, psge);
2173 if (data_out_sz && data_in_sz) {
2174 /* WRITE sgel first */
2175 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2176 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2177 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
2181 psge += ioc->sge_size_ieee;
2183 /* READ sgel last */
2184 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
2185 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
2187 } else if (data_out_sz) /* WRITE */ {
2188 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2189 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
2190 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2191 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
2193 } else if (data_in_sz) /* READ */ {
2194 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2195 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
2196 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2197 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
2202 #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
2205 * _base_config_dma_addressing - set dma addressing
2206 * @ioc: per adapter object
2207 * @pdev: PCI device struct
2209 * Returns 0 for success, non-zero for failure.
2212 _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
2215 u64 consistent_dma_mask;
2218 consistent_dma_mask = DMA_BIT_MASK(64);
2220 consistent_dma_mask = DMA_BIT_MASK(32);
2222 if (sizeof(dma_addr_t) > 4) {
2223 const uint64_t required_mask =
2224 dma_get_required_mask(&pdev->dev);
2225 if ((required_mask > DMA_BIT_MASK(32)) &&
2226 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
2227 !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) {
2228 ioc->base_add_sg_single = &_base_add_sg_single_64;
2229 ioc->sge_size = sizeof(Mpi2SGESimple64_t);
2235 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
2236 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
2237 ioc->base_add_sg_single = &_base_add_sg_single_32;
2238 ioc->sge_size = sizeof(Mpi2SGESimple32_t);
2246 "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
2247 ioc->name, ioc->dma_mask, convert_to_kb(s.totalram));
2253 _base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc,
2254 struct pci_dev *pdev)
2256 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2257 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2264 * _base_check_enable_msix - checks MSIX capabable.
2265 * @ioc: per adapter object
2267 * Check to see if card is capable of MSIX, and set number
2268 * of available msix vectors
2271 _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
2274 u16 message_control;
2276 /* Check whether controller SAS2008 B0 controller,
2277 * if it is SAS2008 B0 controller use IO-APIC instead of MSIX
2279 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 &&
2280 ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) {
2284 base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
2286 dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n",
2291 /* get msix vector count */
2292 /* NUMA_IO not supported for older controllers */
2293 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
2294 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
2295 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
2296 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
2297 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
2298 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
2299 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
2300 ioc->msix_vector_count = 1;
2302 pci_read_config_word(ioc->pdev, base + 2, &message_control);
2303 ioc->msix_vector_count = (message_control & 0x3FF) + 1;
2305 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2306 "msix is supported, vector_count(%d)\n",
2307 ioc->name, ioc->msix_vector_count));
2312 * _base_free_irq - free irq
2313 * @ioc: per adapter object
2315 * Freeing respective reply_queue from the list.
2318 _base_free_irq(struct MPT3SAS_ADAPTER *ioc)
2320 struct adapter_reply_queue *reply_q, *next;
2322 if (list_empty(&ioc->reply_queue_list))
2325 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
2326 list_del(&reply_q->list);
2327 free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index),
2334 * _base_request_irq - request irq
2335 * @ioc: per adapter object
2336 * @index: msix index into vector table
2338 * Inserting respective reply_queue into the list.
2341 _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index)
2343 struct pci_dev *pdev = ioc->pdev;
2344 struct adapter_reply_queue *reply_q;
2347 reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
2349 pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n",
2350 ioc->name, (int)sizeof(struct adapter_reply_queue));
2354 reply_q->msix_index = index;
2356 atomic_set(&reply_q->busy, 0);
2357 if (ioc->msix_enable)
2358 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
2359 ioc->driver_name, ioc->id, index);
2361 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
2362 ioc->driver_name, ioc->id);
2363 r = request_irq(pci_irq_vector(pdev, index), _base_interrupt,
2364 IRQF_SHARED, reply_q->name, reply_q);
2366 pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n",
2367 reply_q->name, pci_irq_vector(pdev, index));
2372 INIT_LIST_HEAD(&reply_q->list);
2373 list_add_tail(&reply_q->list, &ioc->reply_queue_list);
2378 * _base_assign_reply_queues - assigning msix index for each cpu
2379 * @ioc: per adapter object
2381 * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
2383 * It would nice if we could call irq_set_affinity, however it is not
2384 * an exported symbol
2387 _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
2389 unsigned int cpu, nr_cpus, nr_msix, index = 0;
2390 struct adapter_reply_queue *reply_q;
2392 if (!_base_is_controller_msix_enabled(ioc))
2395 memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
2397 nr_cpus = num_online_cpus();
2398 nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
2399 ioc->facts.MaxMSIxVectors);
2403 if (smp_affinity_enable) {
2404 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
2405 const cpumask_t *mask = pci_irq_get_affinity(ioc->pdev,
2406 reply_q->msix_index);
2408 pr_warn(MPT3SAS_FMT "no affinity for msi %x\n",
2409 ioc->name, reply_q->msix_index);
2413 for_each_cpu(cpu, mask)
2414 ioc->cpu_msix_table[cpu] = reply_q->msix_index;
2418 cpu = cpumask_first(cpu_online_mask);
2420 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
2422 unsigned int i, group = nr_cpus / nr_msix;
2427 if (index < nr_cpus % nr_msix)
2430 for (i = 0 ; i < group ; i++) {
2431 ioc->cpu_msix_table[cpu] = reply_q->msix_index;
2432 cpu = cpumask_next(cpu, cpu_online_mask);
2439 * _base_disable_msix - disables msix
2440 * @ioc: per adapter object
2444 _base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
2446 if (!ioc->msix_enable)
2448 pci_disable_msix(ioc->pdev);
2449 ioc->msix_enable = 0;
2453 * _base_enable_msix - enables msix, failback to io_apic
2454 * @ioc: per adapter object
2458 _base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
2461 int i, local_max_msix_vectors;
2463 unsigned int irq_flags = PCI_IRQ_MSIX;
2465 if (msix_disable == -1 || msix_disable == 0)
2471 if (_base_check_enable_msix(ioc) != 0)
2474 ioc->reply_queue_count = min_t(int, ioc->cpu_count,
2475 ioc->msix_vector_count);
2477 printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores"
2478 ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count,
2479 ioc->cpu_count, max_msix_vectors);
2481 if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
2482 local_max_msix_vectors = (reset_devices) ? 1 : 8;
2484 local_max_msix_vectors = max_msix_vectors;
2486 if (local_max_msix_vectors > 0)
2487 ioc->reply_queue_count = min_t(int, local_max_msix_vectors,
2488 ioc->reply_queue_count);
2489 else if (local_max_msix_vectors == 0)
2492 if (ioc->msix_vector_count < ioc->cpu_count)
2493 smp_affinity_enable = 0;
2495 if (smp_affinity_enable)
2496 irq_flags |= PCI_IRQ_AFFINITY;
2498 r = pci_alloc_irq_vectors(ioc->pdev, 1, ioc->reply_queue_count,
2501 dfailprintk(ioc, pr_info(MPT3SAS_FMT
2502 "pci_alloc_irq_vectors failed (r=%d) !!!\n",
2507 ioc->msix_enable = 1;
2508 ioc->reply_queue_count = r;
2509 for (i = 0; i < ioc->reply_queue_count; i++) {
2510 r = _base_request_irq(ioc, i);
2512 _base_free_irq(ioc);
2513 _base_disable_msix(ioc);
2520 /* failback to io_apic interrupt routing */
2523 ioc->reply_queue_count = 1;
2524 r = pci_alloc_irq_vectors(ioc->pdev, 1, 1, PCI_IRQ_LEGACY);
2526 dfailprintk(ioc, pr_info(MPT3SAS_FMT
2527 "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n",
2530 r = _base_request_irq(ioc, 0);
2536 * mpt3sas_base_unmap_resources - free controller resources
2537 * @ioc: per adapter object
2540 mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
2542 struct pci_dev *pdev = ioc->pdev;
2544 dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n",
2545 ioc->name, __func__));
2547 _base_free_irq(ioc);
2548 _base_disable_msix(ioc);
2550 if (ioc->combined_reply_queue) {
2551 kfree(ioc->replyPostRegisterIndex);
2552 ioc->replyPostRegisterIndex = NULL;
2555 if (ioc->chip_phys) {
2560 if (pci_is_enabled(pdev)) {
2561 pci_release_selected_regions(ioc->pdev, ioc->bars);
2562 pci_disable_pcie_error_reporting(pdev);
2563 pci_disable_device(pdev);
2568 * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
2569 * @ioc: per adapter object
2571 * Returns 0 for success, non-zero for failure.
2574 mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
2576 struct pci_dev *pdev = ioc->pdev;
2582 struct adapter_reply_queue *reply_q;
2584 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n",
2585 ioc->name, __func__));
2587 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
2588 if (pci_enable_device_mem(pdev)) {
2589 pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n",
2596 if (pci_request_selected_regions(pdev, ioc->bars,
2597 ioc->driver_name)) {
2598 pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n",
2605 /* AER (Advanced Error Reporting) hooks */
2606 pci_enable_pcie_error_reporting(pdev);
2608 pci_set_master(pdev);
2611 if (_base_config_dma_addressing(ioc, pdev) != 0) {
2612 pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n",
2613 ioc->name, pci_name(pdev));
2618 for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
2619 (!memap_sz || !pio_sz); i++) {
2620 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
2623 pio_chip = (u64)pci_resource_start(pdev, i);
2624 pio_sz = pci_resource_len(pdev, i);
2625 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
2628 ioc->chip_phys = pci_resource_start(pdev, i);
2629 chip_phys = (u64)ioc->chip_phys;
2630 memap_sz = pci_resource_len(pdev, i);
2631 ioc->chip = ioremap(ioc->chip_phys, memap_sz);
2635 if (ioc->chip == NULL) {
2636 pr_err(MPT3SAS_FMT "unable to map adapter memory! "
2637 " or resource not found\n", ioc->name);
2642 _base_mask_interrupts(ioc);
2644 r = _base_get_ioc_facts(ioc);
2648 if (!ioc->rdpq_array_enable_assigned) {
2649 ioc->rdpq_array_enable = ioc->rdpq_array_capable;
2650 ioc->rdpq_array_enable_assigned = 1;
2653 r = _base_enable_msix(ioc);
2657 /* Use the Combined reply queue feature only for SAS3 C0 & higher
2658 * revision HBAs and also only when reply queue count is greater than 8
2660 if (ioc->combined_reply_queue && ioc->reply_queue_count > 8) {
2661 /* Determine the Supplemental Reply Post Host Index Registers
2662 * Addresse. Supplemental Reply Post Host Index Registers
2663 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
2664 * each register is at offset bytes of
2665 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
2667 ioc->replyPostRegisterIndex = kcalloc(
2668 ioc->combined_reply_index_count,
2669 sizeof(resource_size_t *), GFP_KERNEL);
2670 if (!ioc->replyPostRegisterIndex) {
2671 dfailprintk(ioc, printk(MPT3SAS_FMT
2672 "allocation for reply Post Register Index failed!!!\n",
2678 for (i = 0; i < ioc->combined_reply_index_count; i++) {
2679 ioc->replyPostRegisterIndex[i] = (resource_size_t *)
2680 ((u8 *)&ioc->chip->Doorbell +
2681 MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
2682 (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
2685 ioc->combined_reply_queue = 0;
2687 if (ioc->is_warpdrive) {
2688 ioc->reply_post_host_index[0] = (resource_size_t __iomem *)
2689 &ioc->chip->ReplyPostHostIndex;
2691 for (i = 1; i < ioc->cpu_msix_table_sz; i++)
2692 ioc->reply_post_host_index[i] =
2693 (resource_size_t __iomem *)
2694 ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1)
2698 list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
2699 pr_info(MPT3SAS_FMT "%s: IRQ %d\n",
2700 reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
2702 pci_irq_vector(ioc->pdev, reply_q->msix_index));
2704 pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
2705 ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
2706 pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n",
2707 ioc->name, (unsigned long long)pio_chip, pio_sz);
2709 /* Save PCI configuration state for recovery from PCI AER/EEH errors */
2710 pci_save_state(pdev);
2714 mpt3sas_base_unmap_resources(ioc);
2719 * mpt3sas_base_get_msg_frame - obtain request mf pointer
2720 * @ioc: per adapter object
2721 * @smid: system request message index(smid zero is invalid)
2723 * Returns virt pointer to message frame.
2726 mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2728 return (void *)(ioc->request + (smid * ioc->request_sz));
2732 * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
2733 * @ioc: per adapter object
2734 * @smid: system request message index
2736 * Returns virt pointer to sense buffer.
2739 mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2741 return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
2745 * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
2746 * @ioc: per adapter object
2747 * @smid: system request message index
2749 * Returns phys pointer to the low 32bit address of the sense buffer.
2752 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2754 return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
2755 SCSI_SENSE_BUFFERSIZE));
2759 * mpt3sas_base_get_pcie_sgl - obtain a PCIe SGL virt addr
2760 * @ioc: per adapter object
2761 * @smid: system request message index
2763 * Returns virt pointer to a PCIe SGL.
2766 mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2768 return (void *)(ioc->pcie_sg_lookup[smid - 1].pcie_sgl);
2772 * mpt3sas_base_get_pcie_sgl_dma - obtain a PCIe SGL dma addr
2773 * @ioc: per adapter object
2774 * @smid: system request message index
2776 * Returns phys pointer to the address of the PCIe buffer.
2779 mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2781 return ioc->pcie_sg_lookup[smid - 1].pcie_sgl_dma;
2785 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
2786 * @ioc: per adapter object
2787 * @phys_addr: lower 32 physical addr of the reply
2789 * Converts 32bit lower physical addr into a virt address.
2792 mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
2796 return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
2800 _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
2802 return ioc->cpu_msix_table[raw_smp_processor_id()];
2806 * mpt3sas_base_get_smid - obtain a free smid from internal queue
2807 * @ioc: per adapter object
2808 * @cb_idx: callback index
2810 * Returns smid (zero is invalid)
2813 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2815 unsigned long flags;
2816 struct request_tracker *request;
2819 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2820 if (list_empty(&ioc->internal_free_list)) {
2821 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2822 pr_err(MPT3SAS_FMT "%s: smid not available\n",
2823 ioc->name, __func__);
2827 request = list_entry(ioc->internal_free_list.next,
2828 struct request_tracker, tracker_list);
2829 request->cb_idx = cb_idx;
2830 smid = request->smid;
2831 list_del(&request->tracker_list);
2832 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2837 * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
2838 * @ioc: per adapter object
2839 * @cb_idx: callback index
2840 * @scmd: pointer to scsi command object
2842 * Returns smid (zero is invalid)
2845 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
2846 struct scsi_cmnd *scmd)
2848 struct scsiio_tracker *request = scsi_cmd_priv(scmd);
2849 unsigned int tag = scmd->request->tag;
2853 request->cb_idx = cb_idx;
2854 request->msix_io = _base_get_msix_index(ioc);
2855 request->smid = smid;
2856 INIT_LIST_HEAD(&request->chain_list);
2861 * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
2862 * @ioc: per adapter object
2863 * @cb_idx: callback index
2865 * Returns smid (zero is invalid)
2868 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2870 unsigned long flags;
2871 struct request_tracker *request;
2874 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2875 if (list_empty(&ioc->hpr_free_list)) {
2876 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2880 request = list_entry(ioc->hpr_free_list.next,
2881 struct request_tracker, tracker_list);
2882 request->cb_idx = cb_idx;
2883 smid = request->smid;
2884 list_del(&request->tracker_list);
2885 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2890 _base_recovery_check(struct MPT3SAS_ADAPTER *ioc)
2893 * See _wait_for_commands_to_complete() call with regards to this code.
2895 if (ioc->shost_recovery && ioc->pending_io_count) {
2896 ioc->pending_io_count = atomic_read(&ioc->shost->host_busy);
2897 if (ioc->pending_io_count == 0)
2898 wake_up(&ioc->reset_wq);
2902 void mpt3sas_base_clear_st(struct MPT3SAS_ADAPTER *ioc,
2903 struct scsiio_tracker *st)
2905 if (WARN_ON(st->smid == 0))
2909 if (!list_empty(&st->chain_list)) {
2910 unsigned long flags;
2912 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2913 list_splice_init(&st->chain_list, &ioc->free_chain_list);
2914 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2919 * mpt3sas_base_free_smid - put smid back on free_list
2920 * @ioc: per adapter object
2921 * @smid: system request message index
2926 mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2928 unsigned long flags;
2931 if (smid < ioc->hi_priority_smid) {
2932 struct scsiio_tracker *st;
2934 st = _get_st_from_smid(ioc, smid);
2936 _base_recovery_check(ioc);
2939 mpt3sas_base_clear_st(ioc, st);
2940 _base_recovery_check(ioc);
2944 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2945 if (smid < ioc->internal_smid) {
2947 i = smid - ioc->hi_priority_smid;
2948 ioc->hpr_lookup[i].cb_idx = 0xFF;
2949 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
2950 } else if (smid <= ioc->hba_queue_depth) {
2951 /* internal queue */
2952 i = smid - ioc->internal_smid;
2953 ioc->internal_lookup[i].cb_idx = 0xFF;
2954 list_add(&ioc->internal_lookup[i].tracker_list,
2955 &ioc->internal_free_list);
2957 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2961 * _base_writeq - 64 bit write to MMIO
2962 * @ioc: per adapter object
2964 * @addr: address in MMIO space
2965 * @writeq_lock: spin lock
2967 * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
2968 * care of 32 bit environment where its not quarenteed to send the entire word
2971 #if defined(writeq) && defined(CONFIG_64BIT)
2973 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2975 writeq(cpu_to_le64(b), addr);
2979 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2981 unsigned long flags;
2982 __u64 data_out = cpu_to_le64(b);
2984 spin_lock_irqsave(writeq_lock, flags);
2985 writel((u32)(data_out), addr);
2986 writel((u32)(data_out >> 32), (addr + 4));
2987 spin_unlock_irqrestore(writeq_lock, flags);
2992 * _base_put_smid_scsi_io - send SCSI_IO request to firmware
2993 * @ioc: per adapter object
2994 * @smid: system request message index
2995 * @handle: device handle
3000 _base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
3002 Mpi2RequestDescriptorUnion_t descriptor;
3003 u64 *request = (u64 *)&descriptor;
3006 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
3007 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
3008 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
3009 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
3010 descriptor.SCSIIO.LMID = 0;
3011 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
3012 &ioc->scsi_lookup_lock);
3016 * _base_put_smid_fast_path - send fast path request to firmware
3017 * @ioc: per adapter object
3018 * @smid: system request message index
3019 * @handle: device handle
3024 _base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
3027 Mpi2RequestDescriptorUnion_t descriptor;
3028 u64 *request = (u64 *)&descriptor;
3030 descriptor.SCSIIO.RequestFlags =
3031 MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
3032 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
3033 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
3034 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
3035 descriptor.SCSIIO.LMID = 0;
3036 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
3037 &ioc->scsi_lookup_lock);
3041 * _base_put_smid_hi_priority - send Task Management request to firmware
3042 * @ioc: per adapter object
3043 * @smid: system request message index
3044 * @msix_task: msix_task will be same as msix of IO incase of task abort else 0.
3048 _base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
3051 Mpi2RequestDescriptorUnion_t descriptor;
3052 u64 *request = (u64 *)&descriptor;
3054 descriptor.HighPriority.RequestFlags =
3055 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
3056 descriptor.HighPriority.MSIxIndex = msix_task;
3057 descriptor.HighPriority.SMID = cpu_to_le16(smid);
3058 descriptor.HighPriority.LMID = 0;
3059 descriptor.HighPriority.Reserved1 = 0;
3060 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
3061 &ioc->scsi_lookup_lock);
3065 * _base_put_smid_nvme_encap - send NVMe encapsulated request to
3067 * @ioc: per adapter object
3068 * @smid: system request message index
3073 _base_put_smid_nvme_encap(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3075 Mpi2RequestDescriptorUnion_t descriptor;
3076 u64 *request = (u64 *)&descriptor;
3078 descriptor.Default.RequestFlags =
3079 MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED;
3080 descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
3081 descriptor.Default.SMID = cpu_to_le16(smid);
3082 descriptor.Default.LMID = 0;
3083 descriptor.Default.DescriptorTypeDependent = 0;
3084 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
3085 &ioc->scsi_lookup_lock);
3089 * _base_put_smid_default - Default, primarily used for config pages
3090 * @ioc: per adapter object
3091 * @smid: system request message index
3096 _base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3098 Mpi2RequestDescriptorUnion_t descriptor;
3099 u64 *request = (u64 *)&descriptor;
3101 descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
3102 descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
3103 descriptor.Default.SMID = cpu_to_le16(smid);
3104 descriptor.Default.LMID = 0;
3105 descriptor.Default.DescriptorTypeDependent = 0;
3106 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
3107 &ioc->scsi_lookup_lock);
3111 * _base_put_smid_scsi_io_atomic - send SCSI_IO request to firmware using
3112 * Atomic Request Descriptor
3113 * @ioc: per adapter object
3114 * @smid: system request message index
3115 * @handle: device handle, unused in this function, for function type match
3120 _base_put_smid_scsi_io_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
3123 Mpi26AtomicRequestDescriptor_t descriptor;
3124 u32 *request = (u32 *)&descriptor;
3126 descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
3127 descriptor.MSIxIndex = _base_get_msix_index(ioc);
3128 descriptor.SMID = cpu_to_le16(smid);
3130 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
3134 * _base_put_smid_fast_path_atomic - send fast path request to firmware
3135 * using Atomic Request Descriptor
3136 * @ioc: per adapter object
3137 * @smid: system request message index
3138 * @handle: device handle, unused in this function, for function type match
3142 _base_put_smid_fast_path_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
3145 Mpi26AtomicRequestDescriptor_t descriptor;
3146 u32 *request = (u32 *)&descriptor;
3148 descriptor.RequestFlags = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
3149 descriptor.MSIxIndex = _base_get_msix_index(ioc);
3150 descriptor.SMID = cpu_to_le16(smid);
3152 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
3156 * _base_put_smid_hi_priority_atomic - send Task Management request to
3157 * firmware using Atomic Request Descriptor
3158 * @ioc: per adapter object
3159 * @smid: system request message index
3160 * @msix_task: msix_task will be same as msix of IO incase of task abort else 0
3165 _base_put_smid_hi_priority_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
3168 Mpi26AtomicRequestDescriptor_t descriptor;
3169 u32 *request = (u32 *)&descriptor;
3171 descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
3172 descriptor.MSIxIndex = msix_task;
3173 descriptor.SMID = cpu_to_le16(smid);
3175 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
3179 * _base_put_smid_nvme_encap_atomic - send NVMe encapsulated request to
3180 * firmware using Atomic Request Descriptor
3181 * @ioc: per adapter object
3182 * @smid: system request message index
3187 _base_put_smid_nvme_encap_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3189 Mpi26AtomicRequestDescriptor_t descriptor;
3190 u32 *request = (u32 *)&descriptor;
3192 descriptor.RequestFlags = MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED;
3193 descriptor.MSIxIndex = _base_get_msix_index(ioc);
3194 descriptor.SMID = cpu_to_le16(smid);
3196 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
3200 * _base_put_smid_default - Default, primarily used for config pages
3201 * use Atomic Request Descriptor
3202 * @ioc: per adapter object
3203 * @smid: system request message index
3208 _base_put_smid_default_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3210 Mpi26AtomicRequestDescriptor_t descriptor;
3211 u32 *request = (u32 *)&descriptor;
3213 descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
3214 descriptor.MSIxIndex = _base_get_msix_index(ioc);
3215 descriptor.SMID = cpu_to_le16(smid);
3217 writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
3221 * _base_display_OEMs_branding - Display branding string
3222 * @ioc: per adapter object
3227 _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc)
3229 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
3232 switch (ioc->pdev->subsystem_vendor) {
3233 case PCI_VENDOR_ID_INTEL:
3234 switch (ioc->pdev->device) {
3235 case MPI2_MFGPAGE_DEVID_SAS2008:
3236 switch (ioc->pdev->subsystem_device) {
3237 case MPT2SAS_INTEL_RMS2LL080_SSDID:
3238 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3239 MPT2SAS_INTEL_RMS2LL080_BRANDING);
3241 case MPT2SAS_INTEL_RMS2LL040_SSDID:
3242 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3243 MPT2SAS_INTEL_RMS2LL040_BRANDING);
3245 case MPT2SAS_INTEL_SSD910_SSDID:
3246 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3247 MPT2SAS_INTEL_SSD910_BRANDING);
3251 "Intel(R) Controller: Subsystem ID: 0x%X\n",
3252 ioc->name, ioc->pdev->subsystem_device);
3255 case MPI2_MFGPAGE_DEVID_SAS2308_2:
3256 switch (ioc->pdev->subsystem_device) {
3257 case MPT2SAS_INTEL_RS25GB008_SSDID:
3258 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3259 MPT2SAS_INTEL_RS25GB008_BRANDING);
3261 case MPT2SAS_INTEL_RMS25JB080_SSDID:
3262 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3263 MPT2SAS_INTEL_RMS25JB080_BRANDING);
3265 case MPT2SAS_INTEL_RMS25JB040_SSDID:
3266 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3267 MPT2SAS_INTEL_RMS25JB040_BRANDING);
3269 case MPT2SAS_INTEL_RMS25KB080_SSDID:
3270 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3271 MPT2SAS_INTEL_RMS25KB080_BRANDING);
3273 case MPT2SAS_INTEL_RMS25KB040_SSDID:
3274 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3275 MPT2SAS_INTEL_RMS25KB040_BRANDING);
3277 case MPT2SAS_INTEL_RMS25LB040_SSDID:
3278 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3279 MPT2SAS_INTEL_RMS25LB040_BRANDING);
3281 case MPT2SAS_INTEL_RMS25LB080_SSDID:
3282 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3283 MPT2SAS_INTEL_RMS25LB080_BRANDING);
3287 "Intel(R) Controller: Subsystem ID: 0x%X\n",
3288 ioc->name, ioc->pdev->subsystem_device);
3291 case MPI25_MFGPAGE_DEVID_SAS3008:
3292 switch (ioc->pdev->subsystem_device) {
3293 case MPT3SAS_INTEL_RMS3JC080_SSDID:
3294 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3295 MPT3SAS_INTEL_RMS3JC080_BRANDING);
3298 case MPT3SAS_INTEL_RS3GC008_SSDID:
3299 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3300 MPT3SAS_INTEL_RS3GC008_BRANDING);
3302 case MPT3SAS_INTEL_RS3FC044_SSDID:
3303 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3304 MPT3SAS_INTEL_RS3FC044_BRANDING);
3306 case MPT3SAS_INTEL_RS3UC080_SSDID:
3307 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3308 MPT3SAS_INTEL_RS3UC080_BRANDING);
3312 "Intel(R) Controller: Subsystem ID: 0x%X\n",
3313 ioc->name, ioc->pdev->subsystem_device);
3319 "Intel(R) Controller: Subsystem ID: 0x%X\n",
3320 ioc->name, ioc->pdev->subsystem_device);
3324 case PCI_VENDOR_ID_DELL:
3325 switch (ioc->pdev->device) {
3326 case MPI2_MFGPAGE_DEVID_SAS2008:
3327 switch (ioc->pdev->subsystem_device) {
3328 case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
3329 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3330 MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
3332 case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
3333 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3334 MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
3336 case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
3337 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3338 MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
3340 case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
3341 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3342 MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);
3344 case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
3345 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3346 MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING);
3348 case MPT2SAS_DELL_PERC_H200_SSDID:
3349 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3350 MPT2SAS_DELL_PERC_H200_BRANDING);
3352 case MPT2SAS_DELL_6GBPS_SAS_SSDID:
3353 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3354 MPT2SAS_DELL_6GBPS_SAS_BRANDING);
3358 "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
3359 ioc->name, ioc->pdev->subsystem_device);
3363 case MPI25_MFGPAGE_DEVID_SAS3008:
3364 switch (ioc->pdev->subsystem_device) {
3365 case MPT3SAS_DELL_12G_HBA_SSDID:
3366 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3367 MPT3SAS_DELL_12G_HBA_BRANDING);
3371 "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
3372 ioc->name, ioc->pdev->subsystem_device);
3378 "Dell HBA: Subsystem ID: 0x%X\n", ioc->name,
3379 ioc->pdev->subsystem_device);
3383 case PCI_VENDOR_ID_CISCO:
3384 switch (ioc->pdev->device) {
3385 case MPI25_MFGPAGE_DEVID_SAS3008:
3386 switch (ioc->pdev->subsystem_device) {
3387 case MPT3SAS_CISCO_12G_8E_HBA_SSDID:
3388 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3389 MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
3391 case MPT3SAS_CISCO_12G_8I_HBA_SSDID:
3392 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3393 MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
3395 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
3396 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3397 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
3401 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
3402 ioc->name, ioc->pdev->subsystem_device);
3406 case MPI25_MFGPAGE_DEVID_SAS3108_1:
3407 switch (ioc->pdev->subsystem_device) {
3408 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
3409 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3410 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
3412 case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID:
3413 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3414 MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING
3419 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
3420 ioc->name, ioc->pdev->subsystem_device);
3426 "Cisco SAS HBA: Subsystem ID: 0x%X\n",
3427 ioc->name, ioc->pdev->subsystem_device);
3431 case MPT2SAS_HP_3PAR_SSVID:
3432 switch (ioc->pdev->device) {
3433 case MPI2_MFGPAGE_DEVID_SAS2004:
3434 switch (ioc->pdev->subsystem_device) {
3435 case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID:
3436 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3437 MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
3441 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
3442 ioc->name, ioc->pdev->subsystem_device);
3445 case MPI2_MFGPAGE_DEVID_SAS2308_2:
3446 switch (ioc->pdev->subsystem_device) {
3447 case MPT2SAS_HP_2_4_INTERNAL_SSDID:
3448 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3449 MPT2SAS_HP_2_4_INTERNAL_BRANDING);
3451 case MPT2SAS_HP_2_4_EXTERNAL_SSDID:
3452 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3453 MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
3455 case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID:
3456 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3457 MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
3459 case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID:
3460 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3461 MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
3465 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
3466 ioc->name, ioc->pdev->subsystem_device);
3471 "HP SAS HBA: Subsystem ID: 0x%X\n",
3472 ioc->name, ioc->pdev->subsystem_device);
3481 * _base_display_ioc_capabilities - Disply IOC's capabilities.
3482 * @ioc: per adapter object
3487 _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
3491 u32 iounit_pg1_flags;
3494 bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
3495 strncpy(desc, ioc->manu_pg0.ChipName, 16);
3496 pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\
3497 "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
3499 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
3500 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
3501 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
3502 ioc->facts.FWVersion.Word & 0x000000FF,
3503 ioc->pdev->revision,
3504 (bios_version & 0xFF000000) >> 24,
3505 (bios_version & 0x00FF0000) >> 16,
3506 (bios_version & 0x0000FF00) >> 8,
3507 bios_version & 0x000000FF);
3509 _base_display_OEMs_branding(ioc);
3511 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) {
3512 pr_info("%sNVMe", i ? "," : "");
3516 pr_info(MPT3SAS_FMT "Protocol=(", ioc->name);
3518 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
3519 pr_info("Initiator");
3523 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
3524 pr_info("%sTarget", i ? "," : "");
3530 pr_info("Capabilities=(");
3532 if (!ioc->hide_ir_msg) {
3533 if (ioc->facts.IOCCapabilities &
3534 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
3540 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
3541 pr_info("%sTLR", i ? "," : "");
3545 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
3546 pr_info("%sMulticast", i ? "," : "");
3550 if (ioc->facts.IOCCapabilities &
3551 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
3552 pr_info("%sBIDI Target", i ? "," : "");
3556 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
3557 pr_info("%sEEDP", i ? "," : "");
3561 if (ioc->facts.IOCCapabilities &
3562 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
3563 pr_info("%sSnapshot Buffer", i ? "," : "");
3567 if (ioc->facts.IOCCapabilities &
3568 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
3569 pr_info("%sDiag Trace Buffer", i ? "," : "");
3573 if (ioc->facts.IOCCapabilities &
3574 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
3575 pr_info("%sDiag Extended Buffer", i ? "," : "");
3579 if (ioc->facts.IOCCapabilities &
3580 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
3581 pr_info("%sTask Set Full", i ? "," : "");
3585 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
3586 if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
3587 pr_info("%sNCQ", i ? "," : "");
3595 * mpt3sas_base_update_missing_delay - change the missing delay timers
3596 * @ioc: per adapter object
3597 * @device_missing_delay: amount of time till device is reported missing
3598 * @io_missing_delay: interval IO is returned when there is a missing device
3602 * Passed on the command line, this function will modify the device missing
3603 * delay, as well as the io missing delay. This should be called at driver
3607 mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
3608 u16 device_missing_delay, u8 io_missing_delay)
3610 u16 dmd, dmd_new, dmd_orignal;
3611 u8 io_missing_delay_original;
3613 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
3614 Mpi2ConfigReply_t mpi_reply;
3618 mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
3622 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
3623 sizeof(Mpi2SasIOUnit1PhyData_t));
3624 sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
3625 if (!sas_iounit_pg1) {
3626 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
3627 ioc->name, __FILE__, __LINE__, __func__);
3630 if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
3631 sas_iounit_pg1, sz))) {
3632 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
3633 ioc->name, __FILE__, __LINE__, __func__);
3636 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
3637 MPI2_IOCSTATUS_MASK;
3638 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
3639 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
3640 ioc->name, __FILE__, __LINE__, __func__);
3644 /* device missing delay */
3645 dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
3646 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
3647 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
3649 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
3651 if (device_missing_delay > 0x7F) {
3652 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
3653 device_missing_delay;
3655 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
3657 dmd = device_missing_delay;
3658 sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
3660 /* io missing delay */
3661 io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
3662 sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
3664 if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
3666 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
3668 MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
3671 dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
3672 pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n",
3673 ioc->name, dmd_orignal, dmd_new);
3674 pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n",
3675 ioc->name, io_missing_delay_original,
3677 ioc->device_missing_delay = dmd_new;
3678 ioc->io_missing_delay = io_missing_delay;
3682 kfree(sas_iounit_pg1);
3685 * _base_static_config_pages - static start of day config pages
3686 * @ioc: per adapter object
3691 _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
3693 Mpi2ConfigReply_t mpi_reply;
3694 u32 iounit_pg1_flags;
3696 mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
3697 if (ioc->ir_firmware)
3698 mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
3702 * Ensure correct T10 PI operation if vendor left EEDPTagMode
3703 * flag unset in NVDATA.
3705 mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11);
3706 if (ioc->manu_pg11.EEDPTagMode == 0) {
3707 pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
3709 ioc->manu_pg11.EEDPTagMode &= ~0x3;
3710 ioc->manu_pg11.EEDPTagMode |= 0x1;
3711 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
3715 mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
3716 mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
3717 mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
3718 mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
3719 mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
3720 mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
3721 _base_display_ioc_capabilities(ioc);
3724 * Enable task_set_full handling in iounit_pg1 when the
3725 * facts capabilities indicate that its supported.
3727 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
3728 if ((ioc->facts.IOCCapabilities &
3729 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
3731 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
3734 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
3735 ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
3736 mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
3738 if (ioc->iounit_pg8.NumSensors)
3739 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
3743 * _base_release_memory_pools - release memory
3744 * @ioc: per adapter object
3746 * Free memory allocated from _base_allocate_memory_pools.
3751 _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
3754 struct reply_post_struct *rps;
3756 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3760 pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
3761 ioc->request, ioc->request_dma);
3762 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3763 "request_pool(0x%p): free\n",
3764 ioc->name, ioc->request));
3765 ioc->request = NULL;
3769 dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
3770 dma_pool_destroy(ioc->sense_dma_pool);
3771 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3772 "sense_pool(0x%p): free\n",
3773 ioc->name, ioc->sense));
3778 dma_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
3779 dma_pool_destroy(ioc->reply_dma_pool);
3780 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3781 "reply_pool(0x%p): free\n",
3782 ioc->name, ioc->reply));
3786 if (ioc->reply_free) {
3787 dma_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
3788 ioc->reply_free_dma);
3789 dma_pool_destroy(ioc->reply_free_dma_pool);
3790 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3791 "reply_free_pool(0x%p): free\n",
3792 ioc->name, ioc->reply_free));
3793 ioc->reply_free = NULL;
3796 if (ioc->reply_post) {
3798 rps = &ioc->reply_post[i];
3799 if (rps->reply_post_free) {
3801 ioc->reply_post_free_dma_pool,
3802 rps->reply_post_free,
3803 rps->reply_post_free_dma);
3804 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3805 "reply_post_free_pool(0x%p): free\n",
3806 ioc->name, rps->reply_post_free));
3807 rps->reply_post_free = NULL;
3809 } while (ioc->rdpq_array_enable &&
3810 (++i < ioc->reply_queue_count));
3812 dma_pool_destroy(ioc->reply_post_free_dma_pool);
3813 kfree(ioc->reply_post);
3816 if (ioc->pcie_sgl_dma_pool) {
3817 for (i = 0; i < ioc->scsiio_depth; i++) {
3818 dma_pool_free(ioc->pcie_sgl_dma_pool,
3819 ioc->pcie_sg_lookup[i].pcie_sgl,
3820 ioc->pcie_sg_lookup[i].pcie_sgl_dma);
3822 if (ioc->pcie_sgl_dma_pool)
3823 dma_pool_destroy(ioc->pcie_sgl_dma_pool);
3826 if (ioc->config_page) {
3827 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3828 "config_page(0x%p): free\n", ioc->name,
3830 pci_free_consistent(ioc->pdev, ioc->config_page_sz,
3831 ioc->config_page, ioc->config_page_dma);
3834 kfree(ioc->hpr_lookup);
3835 kfree(ioc->internal_lookup);
3836 if (ioc->chain_lookup) {
3837 for (i = 0; i < ioc->chain_depth; i++) {
3838 if (ioc->chain_lookup[i].chain_buffer)
3839 dma_pool_free(ioc->chain_dma_pool,
3840 ioc->chain_lookup[i].chain_buffer,
3841 ioc->chain_lookup[i].chain_buffer_dma);
3843 dma_pool_destroy(ioc->chain_dma_pool);
3844 free_pages((ulong)ioc->chain_lookup, ioc->chain_pages);
3845 ioc->chain_lookup = NULL;
3850 * _base_allocate_memory_pools - allocate start of day memory pools
3851 * @ioc: per adapter object
3853 * Returns 0 success, anything else error
3856 _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
3858 struct mpt3sas_facts *facts;
3859 u16 max_sge_elements;
3860 u16 chains_needed_per_io;
3861 u32 sz, total_sz, reply_post_free_sz;
3863 u16 max_request_credit, nvme_blocks_needed;
3864 unsigned short sg_tablesize;
3868 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3873 facts = &ioc->facts;
3875 /* command line tunables for max sgl entries */
3876 if (max_sgl_entries != -1)
3877 sg_tablesize = max_sgl_entries;
3879 if (ioc->hba_mpi_version_belonged == MPI2_VERSION)
3880 sg_tablesize = MPT2SAS_SG_DEPTH;
3882 sg_tablesize = MPT3SAS_SG_DEPTH;
3885 /* max sgl entries <= MPT_KDUMP_MIN_PHYS_SEGMENTS in KDUMP mode */
3887 sg_tablesize = min_t(unsigned short, sg_tablesize,
3888 MPT_KDUMP_MIN_PHYS_SEGMENTS);
3890 if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS)
3891 sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
3892 else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) {
3893 sg_tablesize = min_t(unsigned short, sg_tablesize,
3896 "sg_tablesize(%u) is bigger than kernel"
3897 " defined SG_CHUNK_SIZE(%u)\n", ioc->name,
3898 sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
3900 ioc->shost->sg_tablesize = sg_tablesize;
3902 ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)),
3903 (facts->RequestCredit / 4));
3904 if (ioc->internal_depth < INTERNAL_CMDS_COUNT) {
3905 if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT +
3906 INTERNAL_SCSIIO_CMDS_COUNT)) {
3907 pr_err(MPT3SAS_FMT "IOC doesn't have enough Request \
3908 Credits, it has just %d number of credits\n",
3909 ioc->name, facts->RequestCredit);
3912 ioc->internal_depth = 10;
3915 ioc->hi_priority_depth = ioc->internal_depth - (5);
3916 /* command line tunables for max controller queue depth */
3917 if (max_queue_depth != -1 && max_queue_depth != 0) {
3918 max_request_credit = min_t(u16, max_queue_depth +
3919 ioc->internal_depth, facts->RequestCredit);
3920 if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
3921 max_request_credit = MAX_HBA_QUEUE_DEPTH;
3922 } else if (reset_devices)
3923 max_request_credit = min_t(u16, facts->RequestCredit,
3924 (MPT3SAS_KDUMP_SCSI_IO_DEPTH + ioc->internal_depth));
3926 max_request_credit = min_t(u16, facts->RequestCredit,
3927 MAX_HBA_QUEUE_DEPTH);
3929 /* Firmware maintains additional facts->HighPriorityCredit number of
3930 * credits for HiPriprity Request messages, so hba queue depth will be
3931 * sum of max_request_credit and high priority queue depth.
3933 ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth;
3935 /* request frame size */
3936 ioc->request_sz = facts->IOCRequestFrameSize * 4;
3938 /* reply frame size */
3939 ioc->reply_sz = facts->ReplyFrameSize * 4;
3941 /* chain segment size */
3942 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
3943 if (facts->IOCMaxChainSegmentSize)
3944 ioc->chain_segment_sz =
3945 facts->IOCMaxChainSegmentSize *
3948 /* set to 128 bytes size if IOCMaxChainSegmentSize is zero */
3949 ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS *
3952 ioc->chain_segment_sz = ioc->request_sz;
3954 /* calculate the max scatter element size */
3955 sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
3959 /* calculate number of sg elements left over in the 1st frame */
3960 max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
3961 sizeof(Mpi2SGEIOUnion_t)) + sge_size);
3962 ioc->max_sges_in_main_message = max_sge_elements/sge_size;
3964 /* now do the same for a chain buffer */
3965 max_sge_elements = ioc->chain_segment_sz - sge_size;
3966 ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
3969 * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
3971 chains_needed_per_io = ((ioc->shost->sg_tablesize -
3972 ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
3974 if (chains_needed_per_io > facts->MaxChainDepth) {
3975 chains_needed_per_io = facts->MaxChainDepth;
3976 ioc->shost->sg_tablesize = min_t(u16,
3977 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
3978 * chains_needed_per_io), ioc->shost->sg_tablesize);
3980 ioc->chains_needed_per_io = chains_needed_per_io;
3982 /* reply free queue sizing - taking into account for 64 FW events */
3983 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
3985 /* calculate reply descriptor post queue depth */
3986 ioc->reply_post_queue_depth = ioc->hba_queue_depth +
3987 ioc->reply_free_queue_depth + 1 ;
3988 /* align the reply post queue on the next 16 count boundary */
3989 if (ioc->reply_post_queue_depth % 16)
3990 ioc->reply_post_queue_depth += 16 -
3991 (ioc->reply_post_queue_depth % 16);
3993 if (ioc->reply_post_queue_depth >
3994 facts->MaxReplyDescriptorPostQueueDepth) {
3995 ioc->reply_post_queue_depth =
3996 facts->MaxReplyDescriptorPostQueueDepth -
3997 (facts->MaxReplyDescriptorPostQueueDepth % 16);
3998 ioc->hba_queue_depth =
3999 ((ioc->reply_post_queue_depth - 64) / 2) - 1;
4000 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
4003 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \
4004 "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
4005 "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
4006 ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
4007 ioc->chains_needed_per_io));
4009 /* reply post queue, 16 byte align */
4010 reply_post_free_sz = ioc->reply_post_queue_depth *
4011 sizeof(Mpi2DefaultReplyDescriptor_t);
4013 sz = reply_post_free_sz;
4014 if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
4015 sz *= ioc->reply_queue_count;
4017 ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ?
4018 (ioc->reply_queue_count):1,
4019 sizeof(struct reply_post_struct), GFP_KERNEL);
4021 if (!ioc->reply_post) {
4022 pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n",
4026 ioc->reply_post_free_dma_pool = dma_pool_create("reply_post_free pool",
4027 &ioc->pdev->dev, sz, 16, 0);
4028 if (!ioc->reply_post_free_dma_pool) {
4030 "reply_post_free pool: dma_pool_create failed\n",
4036 ioc->reply_post[i].reply_post_free =
4037 dma_pool_alloc(ioc->reply_post_free_dma_pool,
4039 &ioc->reply_post[i].reply_post_free_dma);
4040 if (!ioc->reply_post[i].reply_post_free) {
4042 "reply_post_free pool: dma_pool_alloc failed\n",
4046 memset(ioc->reply_post[i].reply_post_free, 0, sz);
4047 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4048 "reply post free pool (0x%p): depth(%d),"
4049 "element_size(%d), pool_size(%d kB)\n", ioc->name,
4050 ioc->reply_post[i].reply_post_free,
4051 ioc->reply_post_queue_depth, 8, sz/1024));
4052 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4053 "reply_post_free_dma = (0x%llx)\n", ioc->name,
4054 (unsigned long long)
4055 ioc->reply_post[i].reply_post_free_dma));
4057 } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
4059 if (ioc->dma_mask == 64) {
4060 if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
4062 "no suitable consistent DMA mask for %s\n",
4063 ioc->name, pci_name(ioc->pdev));
4068 ioc->scsiio_depth = ioc->hba_queue_depth -
4069 ioc->hi_priority_depth - ioc->internal_depth;
4071 /* set the scsi host can_queue depth
4072 * with some internal commands that could be outstanding
4074 ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT;
4075 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4076 "scsi host: can_queue depth (%d)\n",
4077 ioc->name, ioc->shost->can_queue));
4080 /* contiguous pool for request and chains, 16 byte align, one extra "
4083 ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
4084 sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
4086 /* hi-priority queue */
4087 sz += (ioc->hi_priority_depth * ioc->request_sz);
4089 /* internal queue */
4090 sz += (ioc->internal_depth * ioc->request_sz);
4092 ioc->request_dma_sz = sz;
4093 ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
4094 if (!ioc->request) {
4095 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
4096 "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
4097 "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
4098 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
4099 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
4102 ioc->hba_queue_depth -= retry_sz;
4103 _base_release_memory_pools(ioc);
4104 goto retry_allocation;
4108 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
4109 "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
4110 "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
4111 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
4113 /* hi-priority queue */
4114 ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
4116 ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
4119 /* internal queue */
4120 ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
4122 ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
4125 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4126 "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
4127 ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz,
4128 (ioc->hba_queue_depth * ioc->request_sz)/1024));
4130 dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n",
4131 ioc->name, (unsigned long long) ioc->request_dma));
4134 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n",
4135 ioc->name, ioc->request, ioc->scsiio_depth));
4137 ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
4138 sz = ioc->chain_depth * sizeof(struct chain_tracker);
4139 ioc->chain_pages = get_order(sz);
4140 ioc->chain_lookup = (struct chain_tracker *)__get_free_pages(
4141 GFP_KERNEL, ioc->chain_pages);
4142 if (!ioc->chain_lookup) {
4143 pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n",
4147 ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev,
4148 ioc->chain_segment_sz, 16, 0);
4149 if (!ioc->chain_dma_pool) {
4150 pr_err(MPT3SAS_FMT "chain_dma_pool: dma_pool_create failed\n",
4154 for (i = 0; i < ioc->chain_depth; i++) {
4155 ioc->chain_lookup[i].chain_buffer = dma_pool_alloc(
4156 ioc->chain_dma_pool , GFP_KERNEL,
4157 &ioc->chain_lookup[i].chain_buffer_dma);
4158 if (!ioc->chain_lookup[i].chain_buffer) {
4159 ioc->chain_depth = i;
4162 total_sz += ioc->chain_segment_sz;
4165 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4166 "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
4167 ioc->name, ioc->chain_depth, ioc->chain_segment_sz,
4168 ((ioc->chain_depth * ioc->chain_segment_sz))/1024));
4170 /* initialize hi-priority queue smid's */
4171 ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
4172 sizeof(struct request_tracker), GFP_KERNEL);
4173 if (!ioc->hpr_lookup) {
4174 pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n",
4178 ioc->hi_priority_smid = ioc->scsiio_depth + 1;
4179 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4180 "hi_priority(0x%p): depth(%d), start smid(%d)\n",
4181 ioc->name, ioc->hi_priority,
4182 ioc->hi_priority_depth, ioc->hi_priority_smid));
4184 /* initialize internal queue smid's */
4185 ioc->internal_lookup = kcalloc(ioc->internal_depth,
4186 sizeof(struct request_tracker), GFP_KERNEL);
4187 if (!ioc->internal_lookup) {
4188 pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n",
4192 ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
4193 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4194 "internal(0x%p): depth(%d), start smid(%d)\n",
4195 ioc->name, ioc->internal,
4196 ioc->internal_depth, ioc->internal_smid));
4198 * The number of NVMe page sized blocks needed is:
4199 * (((sg_tablesize * 8) - 1) / (page_size - 8)) + 1
4200 * ((sg_tablesize * 8) - 1) is the max PRP's minus the first PRP entry
4201 * that is placed in the main message frame. 8 is the size of each PRP
4202 * entry or PRP list pointer entry. 8 is subtracted from page_size
4203 * because of the PRP list pointer entry at the end of a page, so this
4204 * is not counted as a PRP entry. The 1 added page is a round up.
4206 * To avoid allocation failures due to the amount of memory that could
4207 * be required for NVMe PRP's, only each set of NVMe blocks will be
4208 * contiguous, so a new set is allocated for each possible I/O.
4210 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) {
4211 nvme_blocks_needed =
4212 (ioc->shost->sg_tablesize * NVME_PRP_SIZE) - 1;
4213 nvme_blocks_needed /= (ioc->page_size - NVME_PRP_SIZE);
4214 nvme_blocks_needed++;
4216 sz = sizeof(struct pcie_sg_list) * ioc->scsiio_depth;
4217 ioc->pcie_sg_lookup = kzalloc(sz, GFP_KERNEL);
4218 if (!ioc->pcie_sg_lookup) {
4220 "PCIe SGL lookup: kzalloc failed\n", ioc->name);
4223 sz = nvme_blocks_needed * ioc->page_size;
4224 ioc->pcie_sgl_dma_pool =
4225 dma_pool_create("PCIe SGL pool", &ioc->pdev->dev, sz, 16, 0);
4226 if (!ioc->pcie_sgl_dma_pool) {
4228 "PCIe SGL pool: dma_pool_create failed\n",
4232 for (i = 0; i < ioc->scsiio_depth; i++) {
4233 ioc->pcie_sg_lookup[i].pcie_sgl = dma_pool_alloc(
4234 ioc->pcie_sgl_dma_pool, GFP_KERNEL,
4235 &ioc->pcie_sg_lookup[i].pcie_sgl_dma);
4236 if (!ioc->pcie_sg_lookup[i].pcie_sgl) {
4238 "PCIe SGL pool: dma_pool_alloc failed\n",
4244 dinitprintk(ioc, pr_info(MPT3SAS_FMT "PCIe sgl pool depth(%d), "
4245 "element_size(%d), pool_size(%d kB)\n", ioc->name,
4246 ioc->scsiio_depth, sz, (sz * ioc->scsiio_depth)/1024));
4247 total_sz += sz * ioc->scsiio_depth;
4249 /* sense buffers, 4 byte align */
4250 sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
4251 ioc->sense_dma_pool = dma_pool_create("sense pool", &ioc->pdev->dev, sz,
4253 if (!ioc->sense_dma_pool) {
4254 pr_err(MPT3SAS_FMT "sense pool: dma_pool_create failed\n",
4258 ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, GFP_KERNEL,
4261 pr_err(MPT3SAS_FMT "sense pool: dma_pool_alloc failed\n",
4265 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4266 "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
4267 "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
4268 SCSI_SENSE_BUFFERSIZE, sz/1024));
4269 dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n",
4270 ioc->name, (unsigned long long)ioc->sense_dma));
4273 /* reply pool, 4 byte align */
4274 sz = ioc->reply_free_queue_depth * ioc->reply_sz;
4275 ioc->reply_dma_pool = dma_pool_create("reply pool", &ioc->pdev->dev, sz,
4277 if (!ioc->reply_dma_pool) {
4278 pr_err(MPT3SAS_FMT "reply pool: dma_pool_create failed\n",
4282 ioc->reply = dma_pool_alloc(ioc->reply_dma_pool, GFP_KERNEL,
4285 pr_err(MPT3SAS_FMT "reply pool: dma_pool_alloc failed\n",
4289 ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
4290 ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
4291 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4292 "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
4293 ioc->name, ioc->reply,
4294 ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
4295 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n",
4296 ioc->name, (unsigned long long)ioc->reply_dma));
4299 /* reply free queue, 16 byte align */
4300 sz = ioc->reply_free_queue_depth * 4;
4301 ioc->reply_free_dma_pool = dma_pool_create("reply_free pool",
4302 &ioc->pdev->dev, sz, 16, 0);
4303 if (!ioc->reply_free_dma_pool) {
4304 pr_err(MPT3SAS_FMT "reply_free pool: dma_pool_create failed\n",
4308 ioc->reply_free = dma_pool_alloc(ioc->reply_free_dma_pool, GFP_KERNEL,
4309 &ioc->reply_free_dma);
4310 if (!ioc->reply_free) {
4311 pr_err(MPT3SAS_FMT "reply_free pool: dma_pool_alloc failed\n",
4315 memset(ioc->reply_free, 0, sz);
4316 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \
4317 "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
4318 ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
4319 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4320 "reply_free_dma (0x%llx)\n",
4321 ioc->name, (unsigned long long)ioc->reply_free_dma));
4324 ioc->config_page_sz = 512;
4325 ioc->config_page = pci_alloc_consistent(ioc->pdev,
4326 ioc->config_page_sz, &ioc->config_page_dma);
4327 if (!ioc->config_page) {
4329 "config page: dma_pool_alloc failed\n",
4333 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4334 "config page(0x%p): size(%d)\n",
4335 ioc->name, ioc->config_page, ioc->config_page_sz));
4336 dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n",
4337 ioc->name, (unsigned long long)ioc->config_page_dma));
4338 total_sz += ioc->config_page_sz;
4340 pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n",
4341 ioc->name, total_sz/1024);
4343 "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
4344 ioc->name, ioc->shost->can_queue, facts->RequestCredit);
4345 pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n",
4346 ioc->name, ioc->shost->sg_tablesize);
4354 * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
4355 * @ioc: Pointer to MPT_ADAPTER structure
4356 * @cooked: Request raw or cooked IOC state
4358 * Returns all IOC Doorbell register bits if cooked==0, else just the
4359 * Doorbell bits in MPI_IOC_STATE_MASK.
4362 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
4366 s = readl(&ioc->chip->Doorbell);
4367 sc = s & MPI2_IOC_STATE_MASK;
4368 return cooked ? sc : s;
4372 * _base_wait_on_iocstate - waiting on a particular ioc state
4373 * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
4374 * @timeout: timeout in second
4376 * Returns 0 for success, non-zero for failure.
4379 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout)
4385 cntdn = 1000 * timeout;
4387 current_state = mpt3sas_base_get_iocstate(ioc, 1);
4388 if (current_state == ioc_state)
4390 if (count && current_state == MPI2_IOC_STATE_FAULT)
4393 usleep_range(1000, 1500);
4397 return current_state;
4401 * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
4402 * a write to the doorbell)
4403 * @ioc: per adapter object
4404 * @timeout: timeout in second
4406 * Returns 0 for success, non-zero for failure.
4408 * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
4411 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc);
4414 _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
4420 cntdn = 1000 * timeout;
4422 int_status = readl(&ioc->chip->HostInterruptStatus);
4423 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
4424 dhsprintk(ioc, pr_info(MPT3SAS_FMT
4425 "%s: successful count(%d), timeout(%d)\n",
4426 ioc->name, __func__, count, timeout));
4430 usleep_range(1000, 1500);
4435 "%s: failed due to timeout count(%d), int_status(%x)!\n",
4436 ioc->name, __func__, count, int_status);
4441 _base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
4447 cntdn = 2000 * timeout;
4449 int_status = readl(&ioc->chip->HostInterruptStatus);
4450 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
4451 dhsprintk(ioc, pr_info(MPT3SAS_FMT
4452 "%s: successful count(%d), timeout(%d)\n",
4453 ioc->name, __func__, count, timeout));
4462 "%s: failed due to timeout count(%d), int_status(%x)!\n",
4463 ioc->name, __func__, count, int_status);
4469 * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
4470 * @ioc: per adapter object
4471 * @timeout: timeout in second
4473 * Returns 0 for success, non-zero for failure.
4475 * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
4479 _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout)
4486 cntdn = 1000 * timeout;
4488 int_status = readl(&ioc->chip->HostInterruptStatus);
4489 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
4490 dhsprintk(ioc, pr_info(MPT3SAS_FMT
4491 "%s: successful count(%d), timeout(%d)\n",
4492 ioc->name, __func__, count, timeout));
4494 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
4495 doorbell = readl(&ioc->chip->Doorbell);
4496 if ((doorbell & MPI2_IOC_STATE_MASK) ==
4497 MPI2_IOC_STATE_FAULT) {
4498 mpt3sas_base_fault_info(ioc , doorbell);
4501 } else if (int_status == 0xFFFFFFFF)
4504 usleep_range(1000, 1500);
4510 "%s: failed due to timeout count(%d), int_status(%x)!\n",
4511 ioc->name, __func__, count, int_status);
4516 * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
4517 * @ioc: per adapter object
4518 * @timeout: timeout in second
4520 * Returns 0 for success, non-zero for failure.
4524 _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout)
4530 cntdn = 1000 * timeout;
4532 doorbell_reg = readl(&ioc->chip->Doorbell);
4533 if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
4534 dhsprintk(ioc, pr_info(MPT3SAS_FMT
4535 "%s: successful count(%d), timeout(%d)\n",
4536 ioc->name, __func__, count, timeout));
4540 usleep_range(1000, 1500);
4545 "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
4546 ioc->name, __func__, count, doorbell_reg);
4551 * _base_send_ioc_reset - send doorbell reset
4552 * @ioc: per adapter object
4553 * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
4554 * @timeout: timeout in second
4556 * Returns 0 for success, non-zero for failure.
4559 _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout)
4564 if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
4565 pr_err(MPT3SAS_FMT "%s: unknown reset_type\n",
4566 ioc->name, __func__);
4570 if (!(ioc->facts.IOCCapabilities &
4571 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
4574 pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name);
4576 writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
4577 &ioc->chip->Doorbell);
4578 if ((_base_wait_for_doorbell_ack(ioc, 15))) {
4582 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
4585 "%s: failed going to ready state (ioc_state=0x%x)\n",
4586 ioc->name, __func__, ioc_state);
4591 pr_info(MPT3SAS_FMT "message unit reset: %s\n",
4592 ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
4597 * _base_handshake_req_reply_wait - send request thru doorbell interface
4598 * @ioc: per adapter object
4599 * @request_bytes: request length
4600 * @request: pointer having request payload
4601 * @reply_bytes: reply length
4602 * @reply: pointer to reply payload
4603 * @timeout: timeout in second
4605 * Returns 0 for success, non-zero for failure.
4608 _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
4609 u32 *request, int reply_bytes, u16 *reply, int timeout)
4611 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
4616 /* make sure doorbell is not in use */
4617 if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
4619 "doorbell is in use (line=%d)\n",
4620 ioc->name, __LINE__);
4624 /* clear pending doorbell interrupts from previous state changes */
4625 if (readl(&ioc->chip->HostInterruptStatus) &
4626 MPI2_HIS_IOC2SYS_DB_STATUS)
4627 writel(0, &ioc->chip->HostInterruptStatus);
4629 /* send message to ioc */
4630 writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
4631 ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
4632 &ioc->chip->Doorbell);
4634 if ((_base_spin_on_doorbell_int(ioc, 5))) {
4636 "doorbell handshake int failed (line=%d)\n",
4637 ioc->name, __LINE__);
4640 writel(0, &ioc->chip->HostInterruptStatus);
4642 if ((_base_wait_for_doorbell_ack(ioc, 5))) {
4644 "doorbell handshake ack failed (line=%d)\n",
4645 ioc->name, __LINE__);
4649 /* send message 32-bits at a time */
4650 for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
4651 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
4652 if ((_base_wait_for_doorbell_ack(ioc, 5)))
4658 "doorbell handshake sending request failed (line=%d)\n",
4659 ioc->name, __LINE__);
4663 /* now wait for the reply */
4664 if ((_base_wait_for_doorbell_int(ioc, timeout))) {
4666 "doorbell handshake int failed (line=%d)\n",
4667 ioc->name, __LINE__);
4671 /* read the first two 16-bits, it gives the total length of the reply */
4672 reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
4673 & MPI2_DOORBELL_DATA_MASK);
4674 writel(0, &ioc->chip->HostInterruptStatus);
4675 if ((_base_wait_for_doorbell_int(ioc, 5))) {
4677 "doorbell handshake int failed (line=%d)\n",
4678 ioc->name, __LINE__);
4681 reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
4682 & MPI2_DOORBELL_DATA_MASK);
4683 writel(0, &ioc->chip->HostInterruptStatus);
4685 for (i = 2; i < default_reply->MsgLength * 2; i++) {
4686 if ((_base_wait_for_doorbell_int(ioc, 5))) {
4688 "doorbell handshake int failed (line=%d)\n",
4689 ioc->name, __LINE__);
4692 if (i >= reply_bytes/2) /* overflow case */
4693 readl(&ioc->chip->Doorbell);
4695 reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
4696 & MPI2_DOORBELL_DATA_MASK);
4697 writel(0, &ioc->chip->HostInterruptStatus);
4700 _base_wait_for_doorbell_int(ioc, 5);
4701 if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) {
4702 dhsprintk(ioc, pr_info(MPT3SAS_FMT
4703 "doorbell is in use (line=%d)\n", ioc->name, __LINE__));
4705 writel(0, &ioc->chip->HostInterruptStatus);
4707 if (ioc->logging_level & MPT_DEBUG_INIT) {
4708 mfp = (__le32 *)reply;
4709 pr_info("\toffset:data\n");
4710 for (i = 0; i < reply_bytes/4; i++)
4711 pr_info("\t[0x%02x]:%08x\n", i*4,
4712 le32_to_cpu(mfp[i]));
4718 * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
4719 * @ioc: per adapter object
4720 * @mpi_reply: the reply payload from FW
4721 * @mpi_request: the request payload sent to FW
4723 * The SAS IO Unit Control Request message allows the host to perform low-level
4724 * operations, such as resets on the PHYs of the IO Unit, also allows the host
4725 * to obtain the IOC assigned device handles for a device if it has other
4726 * identifying information about the device, in addition allows the host to
4727 * remove IOC resources associated with the device.
4729 * Returns 0 for success, non-zero for failure.
4732 mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
4733 Mpi2SasIoUnitControlReply_t *mpi_reply,
4734 Mpi2SasIoUnitControlRequest_t *mpi_request)
4738 bool issue_reset = false;
4741 u16 wait_state_count;
4743 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4746 mutex_lock(&ioc->base_cmds.mutex);
4748 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
4749 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
4750 ioc->name, __func__);
4755 wait_state_count = 0;
4756 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4757 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
4758 if (wait_state_count++ == 10) {
4760 "%s: failed due to ioc not operational\n",
4761 ioc->name, __func__);
4766 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4768 "%s: waiting for operational state(count=%d)\n",
4769 ioc->name, __func__, wait_state_count);
4772 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4774 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4775 ioc->name, __func__);
4781 ioc->base_cmds.status = MPT3_CMD_PENDING;
4782 request = mpt3sas_base_get_msg_frame(ioc, smid);
4783 ioc->base_cmds.smid = smid;
4784 memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
4785 if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
4786 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
4787 ioc->ioc_link_reset_in_progress = 1;
4788 init_completion(&ioc->base_cmds.done);
4789 ioc->put_smid_default(ioc, smid);
4790 wait_for_completion_timeout(&ioc->base_cmds.done,
4791 msecs_to_jiffies(10000));
4792 if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
4793 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
4794 ioc->ioc_link_reset_in_progress)
4795 ioc->ioc_link_reset_in_progress = 0;
4796 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4797 pr_err(MPT3SAS_FMT "%s: timeout\n",
4798 ioc->name, __func__);
4799 _debug_dump_mf(mpi_request,
4800 sizeof(Mpi2SasIoUnitControlRequest_t)/4);
4801 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
4803 goto issue_host_reset;
4805 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
4806 memcpy(mpi_reply, ioc->base_cmds.reply,
4807 sizeof(Mpi2SasIoUnitControlReply_t));
4809 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
4810 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4815 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
4816 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4819 mutex_unlock(&ioc->base_cmds.mutex);
4824 * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
4825 * @ioc: per adapter object
4826 * @mpi_reply: the reply payload from FW
4827 * @mpi_request: the request payload sent to FW
4829 * The SCSI Enclosure Processor request message causes the IOC to
4830 * communicate with SES devices to control LED status signals.
4832 * Returns 0 for success, non-zero for failure.
4835 mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
4836 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
4840 bool issue_reset = false;
4843 u16 wait_state_count;
4845 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4848 mutex_lock(&ioc->base_cmds.mutex);
4850 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
4851 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
4852 ioc->name, __func__);
4857 wait_state_count = 0;
4858 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4859 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
4860 if (wait_state_count++ == 10) {
4862 "%s: failed due to ioc not operational\n",
4863 ioc->name, __func__);
4868 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4870 "%s: waiting for operational state(count=%d)\n",
4872 __func__, wait_state_count);
4875 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4877 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4878 ioc->name, __func__);
4884 ioc->base_cmds.status = MPT3_CMD_PENDING;
4885 request = mpt3sas_base_get_msg_frame(ioc, smid);
4886 ioc->base_cmds.smid = smid;
4887 memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
4888 init_completion(&ioc->base_cmds.done);
4889 ioc->put_smid_default(ioc, smid);
4890 wait_for_completion_timeout(&ioc->base_cmds.done,
4891 msecs_to_jiffies(10000));
4892 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4893 pr_err(MPT3SAS_FMT "%s: timeout\n",
4894 ioc->name, __func__);
4895 _debug_dump_mf(mpi_request,
4896 sizeof(Mpi2SepRequest_t)/4);
4897 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
4898 issue_reset = false;
4899 goto issue_host_reset;
4901 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
4902 memcpy(mpi_reply, ioc->base_cmds.reply,
4903 sizeof(Mpi2SepReply_t));
4905 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
4906 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4911 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
4912 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4915 mutex_unlock(&ioc->base_cmds.mutex);
4920 * _base_get_port_facts - obtain port facts reply and save in ioc
4921 * @ioc: per adapter object
4923 * Returns 0 for success, non-zero for failure.
4926 _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port)
4928 Mpi2PortFactsRequest_t mpi_request;
4929 Mpi2PortFactsReply_t mpi_reply;
4930 struct mpt3sas_port_facts *pfacts;
4931 int mpi_reply_sz, mpi_request_sz, r;
4933 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4936 mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
4937 mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
4938 memset(&mpi_request, 0, mpi_request_sz);
4939 mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
4940 mpi_request.PortNumber = port;
4941 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
4942 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
4945 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4946 ioc->name, __func__, r);
4950 pfacts = &ioc->pfacts[port];
4951 memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
4952 pfacts->PortNumber = mpi_reply.PortNumber;
4953 pfacts->VP_ID = mpi_reply.VP_ID;
4954 pfacts->VF_ID = mpi_reply.VF_ID;
4955 pfacts->MaxPostedCmdBuffers =
4956 le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
4962 * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
4963 * @ioc: per adapter object
4966 * Returns 0 for success, non-zero for failure.
4969 _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout)
4974 dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name,
4977 if (ioc->pci_error_recovery) {
4978 dfailprintk(ioc, printk(MPT3SAS_FMT
4979 "%s: host in pci error recovery\n", ioc->name, __func__));
4983 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4984 dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4985 ioc->name, __func__, ioc_state));
4987 if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) ||
4988 (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
4991 if (ioc_state & MPI2_DOORBELL_USED) {
4992 dhsprintk(ioc, printk(MPT3SAS_FMT
4993 "unexpected doorbell active!\n", ioc->name));
4994 goto issue_diag_reset;
4997 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
4998 mpt3sas_base_fault_info(ioc, ioc_state &
4999 MPI2_DOORBELL_DATA_MASK);
5000 goto issue_diag_reset;
5003 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
5005 dfailprintk(ioc, printk(MPT3SAS_FMT
5006 "%s: failed going to ready state (ioc_state=0x%x)\n",
5007 ioc->name, __func__, ioc_state));
5012 rc = _base_diag_reset(ioc);
5017 * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
5018 * @ioc: per adapter object
5020 * Returns 0 for success, non-zero for failure.
5023 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc)
5025 Mpi2IOCFactsRequest_t mpi_request;
5026 Mpi2IOCFactsReply_t mpi_reply;
5027 struct mpt3sas_facts *facts;
5028 int mpi_reply_sz, mpi_request_sz, r;
5030 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5033 r = _base_wait_for_iocstate(ioc, 10);
5035 dfailprintk(ioc, printk(MPT3SAS_FMT
5036 "%s: failed getting to correct state\n",
5037 ioc->name, __func__));
5040 mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
5041 mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
5042 memset(&mpi_request, 0, mpi_request_sz);
5043 mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
5044 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
5045 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
5048 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
5049 ioc->name, __func__, r);
5053 facts = &ioc->facts;
5054 memset(facts, 0, sizeof(struct mpt3sas_facts));
5055 facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
5056 facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
5057 facts->VP_ID = mpi_reply.VP_ID;
5058 facts->VF_ID = mpi_reply.VF_ID;
5059 facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
5060 facts->MaxChainDepth = mpi_reply.MaxChainDepth;
5061 facts->WhoInit = mpi_reply.WhoInit;
5062 facts->NumberOfPorts = mpi_reply.NumberOfPorts;
5063 facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
5064 facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
5065 facts->MaxReplyDescriptorPostQueueDepth =
5066 le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
5067 facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
5068 facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
5069 if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
5070 ioc->ir_firmware = 1;
5071 if ((facts->IOCCapabilities &
5072 MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE) && (!reset_devices))
5073 ioc->rdpq_array_capable = 1;
5074 if (facts->IOCCapabilities & MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ)
5075 ioc->atomic_desc_capable = 1;
5076 facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
5077 facts->IOCRequestFrameSize =
5078 le16_to_cpu(mpi_reply.IOCRequestFrameSize);
5079 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
5080 facts->IOCMaxChainSegmentSize =
5081 le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize);
5083 facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
5084 facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
5085 ioc->shost->max_id = -1;
5086 facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
5087 facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
5088 facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
5089 facts->HighPriorityCredit =
5090 le16_to_cpu(mpi_reply.HighPriorityCredit);
5091 facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
5092 facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
5093 facts->CurrentHostPageSize = mpi_reply.CurrentHostPageSize;
5096 * Get the Page Size from IOC Facts. If it's 0, default to 4k.
5098 ioc->page_size = 1 << facts->CurrentHostPageSize;
5099 if (ioc->page_size == 1) {
5100 pr_info(MPT3SAS_FMT "CurrentHostPageSize is 0: Setting "
5101 "default host page size to 4k\n", ioc->name);
5102 ioc->page_size = 1 << MPT3SAS_HOST_PAGE_SIZE_4K;
5104 dinitprintk(ioc, pr_info(MPT3SAS_FMT "CurrentHostPageSize(%d)\n",
5105 ioc->name, facts->CurrentHostPageSize));
5107 dinitprintk(ioc, pr_info(MPT3SAS_FMT
5108 "hba queue depth(%d), max chains per io(%d)\n",
5109 ioc->name, facts->RequestCredit,
5110 facts->MaxChainDepth));
5111 dinitprintk(ioc, pr_info(MPT3SAS_FMT
5112 "request frame size(%d), reply frame size(%d)\n", ioc->name,
5113 facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
5118 * _base_send_ioc_init - send ioc_init to firmware
5119 * @ioc: per adapter object
5121 * Returns 0 for success, non-zero for failure.
5124 _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc)
5126 Mpi2IOCInitRequest_t mpi_request;
5127 Mpi2IOCInitReply_t mpi_reply;
5129 ktime_t current_time;
5131 u32 reply_post_free_array_sz = 0;
5132 Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL;
5133 dma_addr_t reply_post_free_array_dma;
5135 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5138 memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
5139 mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
5140 mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
5141 mpi_request.VF_ID = 0; /* TODO */
5142 mpi_request.VP_ID = 0;
5143 mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged);
5144 mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
5145 mpi_request.HostPageSize = MPT3SAS_HOST_PAGE_SIZE_4K;
5147 if (_base_is_controller_msix_enabled(ioc))
5148 mpi_request.HostMSIxVectors = ioc->reply_queue_count;
5149 mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
5150 mpi_request.ReplyDescriptorPostQueueDepth =
5151 cpu_to_le16(ioc->reply_post_queue_depth);
5152 mpi_request.ReplyFreeQueueDepth =
5153 cpu_to_le16(ioc->reply_free_queue_depth);
5155 mpi_request.SenseBufferAddressHigh =
5156 cpu_to_le32((u64)ioc->sense_dma >> 32);
5157 mpi_request.SystemReplyAddressHigh =
5158 cpu_to_le32((u64)ioc->reply_dma >> 32);
5159 mpi_request.SystemRequestFrameBaseAddress =
5160 cpu_to_le64((u64)ioc->request_dma);
5161 mpi_request.ReplyFreeQueueAddress =
5162 cpu_to_le64((u64)ioc->reply_free_dma);
5164 if (ioc->rdpq_array_enable) {
5165 reply_post_free_array_sz = ioc->reply_queue_count *
5166 sizeof(Mpi2IOCInitRDPQArrayEntry);
5167 reply_post_free_array = pci_alloc_consistent(ioc->pdev,
5168 reply_post_free_array_sz, &reply_post_free_array_dma);
5169 if (!reply_post_free_array) {
5171 "reply_post_free_array: pci_alloc_consistent failed\n",
5176 memset(reply_post_free_array, 0, reply_post_free_array_sz);
5177 for (i = 0; i < ioc->reply_queue_count; i++)
5178 reply_post_free_array[i].RDPQBaseAddress =
5180 (u64)ioc->reply_post[i].reply_post_free_dma);
5181 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
5182 mpi_request.ReplyDescriptorPostQueueAddress =
5183 cpu_to_le64((u64)reply_post_free_array_dma);
5185 mpi_request.ReplyDescriptorPostQueueAddress =
5186 cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
5189 /* This time stamp specifies number of milliseconds
5190 * since epoch ~ midnight January 1, 1970.
5192 current_time = ktime_get_real();
5193 mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time));
5195 if (ioc->logging_level & MPT_DEBUG_INIT) {
5199 mfp = (__le32 *)&mpi_request;
5200 pr_info("\toffset:data\n");
5201 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
5202 pr_info("\t[0x%02x]:%08x\n", i*4,
5203 le32_to_cpu(mfp[i]));
5206 r = _base_handshake_req_reply_wait(ioc,
5207 sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
5208 sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10);
5211 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
5212 ioc->name, __func__, r);
5216 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
5217 if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
5218 mpi_reply.IOCLogInfo) {
5219 pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__);
5224 if (reply_post_free_array)
5225 pci_free_consistent(ioc->pdev, reply_post_free_array_sz,
5226 reply_post_free_array,
5227 reply_post_free_array_dma);
5232 * mpt3sas_port_enable_done - command completion routine for port enable
5233 * @ioc: per adapter object
5234 * @smid: system request message index
5235 * @msix_index: MSIX table index supplied by the OS
5236 * @reply: reply message frame(lower 32bit addr)
5238 * Return 1 meaning mf should be freed from _base_interrupt
5239 * 0 means the mf is freed from this function.
5242 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
5245 MPI2DefaultReply_t *mpi_reply;
5248 if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
5251 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
5255 if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
5258 ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
5259 ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
5260 ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
5261 memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
5262 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
5263 if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
5264 ioc->port_enable_failed = 1;
5266 if (ioc->is_driver_loading) {
5267 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
5268 mpt3sas_port_enable_complete(ioc);
5271 ioc->start_scan_failed = ioc_status;
5272 ioc->start_scan = 0;
5276 complete(&ioc->port_enable_cmds.done);
5281 * _base_send_port_enable - send port_enable(discovery stuff) to firmware
5282 * @ioc: per adapter object
5284 * Returns 0 for success, non-zero for failure.
5287 _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc)
5289 Mpi2PortEnableRequest_t *mpi_request;
5290 Mpi2PortEnableReply_t *mpi_reply;
5295 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
5297 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
5298 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
5299 ioc->name, __func__);
5303 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
5305 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
5306 ioc->name, __func__);
5310 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
5311 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
5312 ioc->port_enable_cmds.smid = smid;
5313 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
5314 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
5316 init_completion(&ioc->port_enable_cmds.done);
5317 ioc->put_smid_default(ioc, smid);
5318 wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ);
5319 if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
5320 pr_err(MPT3SAS_FMT "%s: timeout\n",
5321 ioc->name, __func__);
5322 _debug_dump_mf(mpi_request,
5323 sizeof(Mpi2PortEnableRequest_t)/4);
5324 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
5331 mpi_reply = ioc->port_enable_cmds.reply;
5332 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
5333 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5334 pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n",
5335 ioc->name, __func__, ioc_status);
5341 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
5342 pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ?
5343 "SUCCESS" : "FAILED"));
5348 * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
5349 * @ioc: per adapter object
5351 * Returns 0 for success, non-zero for failure.
5354 mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
5356 Mpi2PortEnableRequest_t *mpi_request;
5359 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
5361 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
5362 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
5363 ioc->name, __func__);
5367 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
5369 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
5370 ioc->name, __func__);
5374 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
5375 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
5376 ioc->port_enable_cmds.smid = smid;
5377 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
5378 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
5380 ioc->put_smid_default(ioc, smid);
5385 * _base_determine_wait_on_discovery - desposition
5386 * @ioc: per adapter object
5388 * Decide whether to wait on discovery to complete. Used to either
5389 * locate boot device, or report volumes ahead of physical devices.
5391 * Returns 1 for wait, 0 for don't wait
5394 _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
5396 /* We wait for discovery to complete if IR firmware is loaded.
5397 * The sas topology events arrive before PD events, so we need time to
5398 * turn on the bit in ioc->pd_handles to indicate PD
5399 * Also, it maybe required to report Volumes ahead of physical
5400 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
5402 if (ioc->ir_firmware)
5405 /* if no Bios, then we don't need to wait */
5406 if (!ioc->bios_pg3.BiosVersion)
5409 /* Bios is present, then we drop down here.
5411 * If there any entries in the Bios Page 2, then we wait
5412 * for discovery to complete.
5415 /* Current Boot Device */
5416 if ((ioc->bios_pg2.CurrentBootDeviceForm &
5417 MPI2_BIOSPAGE2_FORM_MASK) ==
5418 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
5419 /* Request Boot Device */
5420 (ioc->bios_pg2.ReqBootDeviceForm &
5421 MPI2_BIOSPAGE2_FORM_MASK) ==
5422 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
5423 /* Alternate Request Boot Device */
5424 (ioc->bios_pg2.ReqAltBootDeviceForm &
5425 MPI2_BIOSPAGE2_FORM_MASK) ==
5426 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
5433 * _base_unmask_events - turn on notification for this event
5434 * @ioc: per adapter object
5435 * @event: firmware event
5437 * The mask is stored in ioc->event_masks.
5440 _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
5447 desired_event = (1 << (event % 32));
5450 ioc->event_masks[0] &= ~desired_event;
5451 else if (event < 64)
5452 ioc->event_masks[1] &= ~desired_event;
5453 else if (event < 96)
5454 ioc->event_masks[2] &= ~desired_event;
5455 else if (event < 128)
5456 ioc->event_masks[3] &= ~desired_event;
5460 * _base_event_notification - send event notification
5461 * @ioc: per adapter object
5463 * Returns 0 for success, non-zero for failure.
5466 _base_event_notification(struct MPT3SAS_ADAPTER *ioc)
5468 Mpi2EventNotificationRequest_t *mpi_request;
5473 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5476 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
5477 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
5478 ioc->name, __func__);
5482 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
5484 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
5485 ioc->name, __func__);
5488 ioc->base_cmds.status = MPT3_CMD_PENDING;
5489 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
5490 ioc->base_cmds.smid = smid;
5491 memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
5492 mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
5493 mpi_request->VF_ID = 0; /* TODO */
5494 mpi_request->VP_ID = 0;
5495 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
5496 mpi_request->EventMasks[i] =
5497 cpu_to_le32(ioc->event_masks[i]);
5498 init_completion(&ioc->base_cmds.done);
5499 ioc->put_smid_default(ioc, smid);
5500 wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
5501 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
5502 pr_err(MPT3SAS_FMT "%s: timeout\n",
5503 ioc->name, __func__);
5504 _debug_dump_mf(mpi_request,
5505 sizeof(Mpi2EventNotificationRequest_t)/4);
5506 if (ioc->base_cmds.status & MPT3_CMD_RESET)
5511 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n",
5512 ioc->name, __func__));
5513 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
5518 * mpt3sas_base_validate_event_type - validating event types
5519 * @ioc: per adapter object
5520 * @event: firmware event
5522 * This will turn on firmware event notification when application
5523 * ask for that event. We don't mask events that are already enabled.
5526 mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
5529 u32 event_mask, desired_event;
5530 u8 send_update_to_fw;
5532 for (i = 0, send_update_to_fw = 0; i <
5533 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
5534 event_mask = ~event_type[i];
5536 for (j = 0; j < 32; j++) {
5537 if (!(event_mask & desired_event) &&
5538 (ioc->event_masks[i] & desired_event)) {
5539 ioc->event_masks[i] &= ~desired_event;
5540 send_update_to_fw = 1;
5542 desired_event = (desired_event << 1);
5546 if (!send_update_to_fw)
5549 mutex_lock(&ioc->base_cmds.mutex);
5550 _base_event_notification(ioc);
5551 mutex_unlock(&ioc->base_cmds.mutex);
5555 * _base_diag_reset - the "big hammer" start of day reset
5556 * @ioc: per adapter object
5558 * Returns 0 for success, non-zero for failure.
5561 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
5563 u32 host_diagnostic;
5568 pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name);
5570 drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n",
5575 /* Write magic sequence to WriteSequence register
5576 * Loop until in diagnostic mode
5578 drsprintk(ioc, pr_info(MPT3SAS_FMT
5579 "write magic sequence\n", ioc->name));
5580 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
5581 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
5582 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
5583 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
5584 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
5585 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
5586 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
5594 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
5595 drsprintk(ioc, pr_info(MPT3SAS_FMT
5596 "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
5597 ioc->name, count, host_diagnostic));
5599 } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
5601 hcb_size = readl(&ioc->chip->HCBSize);
5603 drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n",
5605 writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
5606 &ioc->chip->HostDiagnostic);
5608 /*This delay allows the chip PCIe hardware time to finish reset tasks*/
5609 msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
5611 /* Approximately 300 second max wait */
5612 for (count = 0; count < (300000000 /
5613 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
5615 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
5617 if (host_diagnostic == 0xFFFFFFFF)
5619 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
5622 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000);
5625 if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
5627 drsprintk(ioc, pr_info(MPT3SAS_FMT
5628 "restart the adapter assuming the HCB Address points to good F/W\n",
5630 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
5631 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
5632 writel(host_diagnostic, &ioc->chip->HostDiagnostic);
5634 drsprintk(ioc, pr_info(MPT3SAS_FMT
5635 "re-enable the HCDW\n", ioc->name));
5636 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
5637 &ioc->chip->HCBSize);
5640 drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n",
5642 writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
5643 &ioc->chip->HostDiagnostic);
5645 drsprintk(ioc, pr_info(MPT3SAS_FMT
5646 "disable writes to the diagnostic register\n", ioc->name));
5647 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
5649 drsprintk(ioc, pr_info(MPT3SAS_FMT
5650 "Wait for FW to go to the READY state\n", ioc->name));
5651 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20);
5654 "%s: failed going to ready state (ioc_state=0x%x)\n",
5655 ioc->name, __func__, ioc_state);
5659 pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name);
5663 pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name);
5668 * _base_make_ioc_ready - put controller in READY state
5669 * @ioc: per adapter object
5670 * @type: FORCE_BIG_HAMMER or SOFT_RESET
5672 * Returns 0 for success, non-zero for failure.
5675 _base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type)
5681 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5684 if (ioc->pci_error_recovery)
5687 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5688 dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
5689 ioc->name, __func__, ioc_state));
5691 /* if in RESET state, it should move to READY state shortly */
5693 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
5694 while ((ioc_state & MPI2_IOC_STATE_MASK) !=
5695 MPI2_IOC_STATE_READY) {
5696 if (count++ == 10) {
5698 "%s: failed going to ready state (ioc_state=0x%x)\n",
5699 ioc->name, __func__, ioc_state);
5703 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5707 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
5710 if (ioc_state & MPI2_DOORBELL_USED) {
5711 dhsprintk(ioc, pr_info(MPT3SAS_FMT
5712 "unexpected doorbell active!\n",
5714 goto issue_diag_reset;
5717 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
5718 mpt3sas_base_fault_info(ioc, ioc_state &
5719 MPI2_DOORBELL_DATA_MASK);
5720 goto issue_diag_reset;
5723 if (type == FORCE_BIG_HAMMER)
5724 goto issue_diag_reset;
5726 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
5727 if (!(_base_send_ioc_reset(ioc,
5728 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15))) {
5733 rc = _base_diag_reset(ioc);
5738 * _base_make_ioc_operational - put controller in OPERATIONAL state
5739 * @ioc: per adapter object
5741 * Returns 0 for success, non-zero for failure.
5744 _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc)
5747 unsigned long flags;
5750 struct _tr_list *delayed_tr, *delayed_tr_next;
5751 struct _sc_list *delayed_sc, *delayed_sc_next;
5752 struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next;
5754 struct adapter_reply_queue *reply_q;
5755 Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig;
5757 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5760 /* clean the delayed target reset list */
5761 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
5762 &ioc->delayed_tr_list, list) {
5763 list_del(&delayed_tr->list);
5768 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
5769 &ioc->delayed_tr_volume_list, list) {
5770 list_del(&delayed_tr->list);
5774 list_for_each_entry_safe(delayed_sc, delayed_sc_next,
5775 &ioc->delayed_sc_list, list) {
5776 list_del(&delayed_sc->list);
5780 list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next,
5781 &ioc->delayed_event_ack_list, list) {
5782 list_del(&delayed_event_ack->list);
5783 kfree(delayed_event_ack);
5786 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
5788 /* hi-priority queue */
5789 INIT_LIST_HEAD(&ioc->hpr_free_list);
5790 smid = ioc->hi_priority_smid;
5791 for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
5792 ioc->hpr_lookup[i].cb_idx = 0xFF;
5793 ioc->hpr_lookup[i].smid = smid;
5794 list_add_tail(&ioc->hpr_lookup[i].tracker_list,
5795 &ioc->hpr_free_list);
5798 /* internal queue */
5799 INIT_LIST_HEAD(&ioc->internal_free_list);
5800 smid = ioc->internal_smid;
5801 for (i = 0; i < ioc->internal_depth; i++, smid++) {
5802 ioc->internal_lookup[i].cb_idx = 0xFF;
5803 ioc->internal_lookup[i].smid = smid;
5804 list_add_tail(&ioc->internal_lookup[i].tracker_list,
5805 &ioc->internal_free_list);
5809 INIT_LIST_HEAD(&ioc->free_chain_list);
5810 for (i = 0; i < ioc->chain_depth; i++)
5811 list_add_tail(&ioc->chain_lookup[i].tracker_list,
5812 &ioc->free_chain_list);
5814 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
5816 /* initialize Reply Free Queue */
5817 for (i = 0, reply_address = (u32)ioc->reply_dma ;
5818 i < ioc->reply_free_queue_depth ; i++, reply_address +=
5820 ioc->reply_free[i] = cpu_to_le32(reply_address);
5822 /* initialize reply queues */
5823 if (ioc->is_driver_loading)
5824 _base_assign_reply_queues(ioc);
5826 /* initialize Reply Post Free Queue */
5828 reply_post_free_contig = ioc->reply_post[0].reply_post_free;
5829 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
5831 * If RDPQ is enabled, switch to the next allocation.
5832 * Otherwise advance within the contiguous region.
5834 if (ioc->rdpq_array_enable) {
5835 reply_q->reply_post_free =
5836 ioc->reply_post[index++].reply_post_free;
5838 reply_q->reply_post_free = reply_post_free_contig;
5839 reply_post_free_contig += ioc->reply_post_queue_depth;
5842 reply_q->reply_post_host_index = 0;
5843 for (i = 0; i < ioc->reply_post_queue_depth; i++)
5844 reply_q->reply_post_free[i].Words =
5845 cpu_to_le64(ULLONG_MAX);
5846 if (!_base_is_controller_msix_enabled(ioc))
5847 goto skip_init_reply_post_free_queue;
5849 skip_init_reply_post_free_queue:
5851 r = _base_send_ioc_init(ioc);
5855 /* initialize reply free host index */
5856 ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
5857 writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
5859 /* initialize reply post host index */
5860 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
5861 if (ioc->combined_reply_queue)
5862 writel((reply_q->msix_index & 7)<<
5863 MPI2_RPHI_MSIX_INDEX_SHIFT,
5864 ioc->replyPostRegisterIndex[reply_q->msix_index/8]);
5866 writel(reply_q->msix_index <<
5867 MPI2_RPHI_MSIX_INDEX_SHIFT,
5868 &ioc->chip->ReplyPostHostIndex);
5870 if (!_base_is_controller_msix_enabled(ioc))
5871 goto skip_init_reply_post_host_index;
5874 skip_init_reply_post_host_index:
5876 _base_unmask_interrupts(ioc);
5877 r = _base_event_notification(ioc);
5881 _base_static_config_pages(ioc);
5883 if (ioc->is_driver_loading) {
5885 if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier
5888 le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) &
5889 MFG_PAGE10_HIDE_SSDS_MASK);
5890 if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK)
5891 ioc->mfg_pg10_hide_flag = hide_flag;
5894 ioc->wait_for_discovery_to_complete =
5895 _base_determine_wait_on_discovery(ioc);
5897 return r; /* scan_start and scan_finished support */
5900 r = _base_send_port_enable(ioc);
5908 * mpt3sas_base_free_resources - free resources controller resources
5909 * @ioc: per adapter object
5914 mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
5916 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5919 /* synchronizing freeing resource with pci_access_mutex lock */
5920 mutex_lock(&ioc->pci_access_mutex);
5921 if (ioc->chip_phys && ioc->chip) {
5922 _base_mask_interrupts(ioc);
5923 ioc->shost_recovery = 1;
5924 _base_make_ioc_ready(ioc, SOFT_RESET);
5925 ioc->shost_recovery = 0;
5928 mpt3sas_base_unmap_resources(ioc);
5929 mutex_unlock(&ioc->pci_access_mutex);
5934 * mpt3sas_base_attach - attach controller instance
5935 * @ioc: per adapter object
5937 * Returns 0 for success, non-zero for failure.
5940 mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
5943 int cpu_id, last_cpu_id = 0;
5945 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5948 /* setup cpu_msix_table */
5949 ioc->cpu_count = num_online_cpus();
5950 for_each_online_cpu(cpu_id)
5951 last_cpu_id = cpu_id;
5952 ioc->cpu_msix_table_sz = last_cpu_id + 1;
5953 ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
5954 ioc->reply_queue_count = 1;
5955 if (!ioc->cpu_msix_table) {
5956 dfailprintk(ioc, pr_info(MPT3SAS_FMT
5957 "allocation for cpu_msix_table failed!!!\n",
5960 goto out_free_resources;
5963 if (ioc->is_warpdrive) {
5964 ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz,
5965 sizeof(resource_size_t *), GFP_KERNEL);
5966 if (!ioc->reply_post_host_index) {
5967 dfailprintk(ioc, pr_info(MPT3SAS_FMT "allocation "
5968 "for reply_post_host_index failed!!!\n",
5971 goto out_free_resources;
5975 ioc->rdpq_array_enable_assigned = 0;
5977 r = mpt3sas_base_map_resources(ioc);
5979 goto out_free_resources;
5981 pci_set_drvdata(ioc->pdev, ioc->shost);
5982 r = _base_get_ioc_facts(ioc);
5984 goto out_free_resources;
5986 switch (ioc->hba_mpi_version_belonged) {
5988 ioc->build_sg_scmd = &_base_build_sg_scmd;
5989 ioc->build_sg = &_base_build_sg;
5990 ioc->build_zero_len_sge = &_base_build_zero_len_sge;
5996 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
5997 * Target Status - all require the IEEE formated scatter gather
6000 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
6001 ioc->build_sg = &_base_build_sg_ieee;
6002 ioc->build_nvme_prp = &_base_build_nvme_prp;
6003 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
6004 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
6009 if (ioc->atomic_desc_capable) {
6010 ioc->put_smid_default = &_base_put_smid_default_atomic;
6011 ioc->put_smid_scsi_io = &_base_put_smid_scsi_io_atomic;
6012 ioc->put_smid_fast_path = &_base_put_smid_fast_path_atomic;
6013 ioc->put_smid_hi_priority = &_base_put_smid_hi_priority_atomic;
6014 ioc->put_smid_nvme_encap = &_base_put_smid_nvme_encap_atomic;
6016 ioc->put_smid_default = &_base_put_smid_default;
6017 ioc->put_smid_scsi_io = &_base_put_smid_scsi_io;
6018 ioc->put_smid_fast_path = &_base_put_smid_fast_path;
6019 ioc->put_smid_hi_priority = &_base_put_smid_hi_priority;
6020 ioc->put_smid_nvme_encap = &_base_put_smid_nvme_encap;
6025 * These function pointers for other requests that don't
6026 * the require IEEE scatter gather elements.
6028 * For example Configuration Pages and SAS IOUNIT Control don't.
6030 ioc->build_sg_mpi = &_base_build_sg;
6031 ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
6033 r = _base_make_ioc_ready(ioc, SOFT_RESET);
6035 goto out_free_resources;
6037 ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
6038 sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
6041 goto out_free_resources;
6044 for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
6045 r = _base_get_port_facts(ioc, i);
6047 goto out_free_resources;
6050 r = _base_allocate_memory_pools(ioc);
6052 goto out_free_resources;
6054 init_waitqueue_head(&ioc->reset_wq);
6056 /* allocate memory pd handle bitmask list */
6057 ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
6058 if (ioc->facts.MaxDevHandle % 8)
6059 ioc->pd_handles_sz++;
6060 ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
6062 if (!ioc->pd_handles) {
6064 goto out_free_resources;
6066 ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
6068 if (!ioc->blocking_handles) {
6070 goto out_free_resources;
6073 /* allocate memory for pending OS device add list */
6074 ioc->pend_os_device_add_sz = (ioc->facts.MaxDevHandle / 8);
6075 if (ioc->facts.MaxDevHandle % 8)
6076 ioc->pend_os_device_add_sz++;
6077 ioc->pend_os_device_add = kzalloc(ioc->pend_os_device_add_sz,
6079 if (!ioc->pend_os_device_add)
6080 goto out_free_resources;
6082 ioc->device_remove_in_progress_sz = ioc->pend_os_device_add_sz;
6083 ioc->device_remove_in_progress =
6084 kzalloc(ioc->device_remove_in_progress_sz, GFP_KERNEL);
6085 if (!ioc->device_remove_in_progress)
6086 goto out_free_resources;
6088 ioc->fwfault_debug = mpt3sas_fwfault_debug;
6090 /* base internal command bits */
6091 mutex_init(&ioc->base_cmds.mutex);
6092 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
6093 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
6095 /* port_enable command bits */
6096 ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
6097 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
6099 /* transport internal command bits */
6100 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
6101 ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
6102 mutex_init(&ioc->transport_cmds.mutex);
6104 /* scsih internal command bits */
6105 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
6106 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
6107 mutex_init(&ioc->scsih_cmds.mutex);
6109 /* task management internal command bits */
6110 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
6111 ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
6112 mutex_init(&ioc->tm_cmds.mutex);
6114 /* config page internal command bits */
6115 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
6116 ioc->config_cmds.status = MPT3_CMD_NOT_USED;
6117 mutex_init(&ioc->config_cmds.mutex);
6119 /* ctl module internal command bits */
6120 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
6121 ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
6122 ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
6123 mutex_init(&ioc->ctl_cmds.mutex);
6125 if (!ioc->base_cmds.reply || !ioc->port_enable_cmds.reply ||
6126 !ioc->transport_cmds.reply || !ioc->scsih_cmds.reply ||
6127 !ioc->tm_cmds.reply || !ioc->config_cmds.reply ||
6128 !ioc->ctl_cmds.reply || !ioc->ctl_cmds.sense) {
6130 goto out_free_resources;
6133 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
6134 ioc->event_masks[i] = -1;
6136 /* here we enable the events we care about */
6137 _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
6138 _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
6139 _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
6140 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
6141 _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
6142 _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
6143 _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
6144 _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
6145 _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
6146 _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
6147 _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
6148 _base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION);
6149 if (ioc->hba_mpi_version_belonged == MPI26_VERSION) {
6150 if (ioc->is_gen35_ioc) {
6151 _base_unmask_events(ioc,
6152 MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE);
6153 _base_unmask_events(ioc, MPI2_EVENT_PCIE_ENUMERATION);
6154 _base_unmask_events(ioc,
6155 MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
6158 r = _base_make_ioc_operational(ioc);
6160 goto out_free_resources;
6162 ioc->non_operational_loop = 0;
6163 ioc->got_task_abort_from_ioctl = 0;
6168 ioc->remove_host = 1;
6170 mpt3sas_base_free_resources(ioc);
6171 _base_release_memory_pools(ioc);
6172 pci_set_drvdata(ioc->pdev, NULL);
6173 kfree(ioc->cpu_msix_table);
6174 if (ioc->is_warpdrive)
6175 kfree(ioc->reply_post_host_index);
6176 kfree(ioc->pd_handles);
6177 kfree(ioc->blocking_handles);
6178 kfree(ioc->device_remove_in_progress);
6179 kfree(ioc->pend_os_device_add);
6180 kfree(ioc->tm_cmds.reply);
6181 kfree(ioc->transport_cmds.reply);
6182 kfree(ioc->scsih_cmds.reply);
6183 kfree(ioc->config_cmds.reply);
6184 kfree(ioc->base_cmds.reply);
6185 kfree(ioc->port_enable_cmds.reply);
6186 kfree(ioc->ctl_cmds.reply);
6187 kfree(ioc->ctl_cmds.sense);
6189 ioc->ctl_cmds.reply = NULL;
6190 ioc->base_cmds.reply = NULL;
6191 ioc->tm_cmds.reply = NULL;
6192 ioc->scsih_cmds.reply = NULL;
6193 ioc->transport_cmds.reply = NULL;
6194 ioc->config_cmds.reply = NULL;
6201 * mpt3sas_base_detach - remove controller instance
6202 * @ioc: per adapter object
6207 mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
6209 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
6212 mpt3sas_base_stop_watchdog(ioc);
6213 mpt3sas_base_free_resources(ioc);
6214 _base_release_memory_pools(ioc);
6215 pci_set_drvdata(ioc->pdev, NULL);
6216 kfree(ioc->cpu_msix_table);
6217 if (ioc->is_warpdrive)
6218 kfree(ioc->reply_post_host_index);
6219 kfree(ioc->pd_handles);
6220 kfree(ioc->blocking_handles);
6221 kfree(ioc->device_remove_in_progress);
6222 kfree(ioc->pend_os_device_add);
6224 kfree(ioc->ctl_cmds.reply);
6225 kfree(ioc->ctl_cmds.sense);
6226 kfree(ioc->base_cmds.reply);
6227 kfree(ioc->port_enable_cmds.reply);
6228 kfree(ioc->tm_cmds.reply);
6229 kfree(ioc->transport_cmds.reply);
6230 kfree(ioc->scsih_cmds.reply);
6231 kfree(ioc->config_cmds.reply);
6235 * _base_reset_handler - reset callback handler (for base)
6236 * @ioc: per adapter object
6237 * @reset_phase: phase
6239 * The handler for doing any required cleanup or initialization.
6241 * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET,
6242 * MPT3_IOC_DONE_RESET
6247 _base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase)
6249 mpt3sas_scsih_reset_handler(ioc, reset_phase);
6250 mpt3sas_ctl_reset_handler(ioc, reset_phase);
6251 switch (reset_phase) {
6252 case MPT3_IOC_PRE_RESET:
6253 dtmprintk(ioc, pr_info(MPT3SAS_FMT
6254 "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__));
6256 case MPT3_IOC_AFTER_RESET:
6257 dtmprintk(ioc, pr_info(MPT3SAS_FMT
6258 "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__));
6259 if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
6260 ioc->transport_cmds.status |= MPT3_CMD_RESET;
6261 mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
6262 complete(&ioc->transport_cmds.done);
6264 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
6265 ioc->base_cmds.status |= MPT3_CMD_RESET;
6266 mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
6267 complete(&ioc->base_cmds.done);
6269 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
6270 ioc->port_enable_failed = 1;
6271 ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
6272 mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
6273 if (ioc->is_driver_loading) {
6274 ioc->start_scan_failed =
6275 MPI2_IOCSTATUS_INTERNAL_ERROR;
6276 ioc->start_scan = 0;
6277 ioc->port_enable_cmds.status =
6280 complete(&ioc->port_enable_cmds.done);
6282 if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
6283 ioc->config_cmds.status |= MPT3_CMD_RESET;
6284 mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
6285 ioc->config_cmds.smid = USHRT_MAX;
6286 complete(&ioc->config_cmds.done);
6289 case MPT3_IOC_DONE_RESET:
6290 dtmprintk(ioc, pr_info(MPT3SAS_FMT
6291 "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__));
6297 * _wait_for_commands_to_complete - reset controller
6298 * @ioc: Pointer to MPT_ADAPTER structure
6300 * This function is waiting 10s for all pending commands to complete
6301 * prior to putting controller in reset.
6304 _wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc)
6308 ioc->pending_io_count = 0;
6310 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
6311 if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
6314 /* pending command count */
6315 ioc->pending_io_count = atomic_read(&ioc->shost->host_busy);
6317 if (!ioc->pending_io_count)
6320 /* wait for pending commands to complete */
6321 wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
6325 * mpt3sas_base_hard_reset_handler - reset controller
6326 * @ioc: Pointer to MPT_ADAPTER structure
6327 * @type: FORCE_BIG_HAMMER or SOFT_RESET
6329 * Returns 0 for success, non-zero for failure.
6332 mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc,
6333 enum reset_type type)
6336 unsigned long flags;
6338 u8 is_fault = 0, is_trigger = 0;
6340 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name,
6343 if (ioc->pci_error_recovery) {
6344 pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n",
6345 ioc->name, __func__);
6350 if (mpt3sas_fwfault_debug)
6351 mpt3sas_halt_firmware(ioc);
6353 /* wait for an active reset in progress to complete */
6354 if (!mutex_trylock(&ioc->reset_in_progress_mutex)) {
6357 } while (ioc->shost_recovery == 1);
6358 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
6360 return ioc->ioc_reset_in_progress_status;
6363 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
6364 ioc->shost_recovery = 1;
6365 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
6367 if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
6368 MPT3_DIAG_BUFFER_IS_REGISTERED) &&
6369 (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
6370 MPT3_DIAG_BUFFER_IS_RELEASED))) {
6372 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
6373 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
6376 _base_reset_handler(ioc, MPT3_IOC_PRE_RESET);
6377 _wait_for_commands_to_complete(ioc);
6378 _base_mask_interrupts(ioc);
6379 r = _base_make_ioc_ready(ioc, type);
6382 _base_reset_handler(ioc, MPT3_IOC_AFTER_RESET);
6384 /* If this hard reset is called while port enable is active, then
6385 * there is no reason to call make_ioc_operational
6387 if (ioc->is_driver_loading && ioc->port_enable_failed) {
6388 ioc->remove_host = 1;
6392 r = _base_get_ioc_facts(ioc);
6396 if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
6397 panic("%s: Issue occurred with flashing controller firmware."
6398 "Please reboot the system and ensure that the correct"
6399 " firmware version is running\n", ioc->name);
6401 r = _base_make_ioc_operational(ioc);
6403 _base_reset_handler(ioc, MPT3_IOC_DONE_RESET);
6406 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n",
6407 ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
6409 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
6410 ioc->ioc_reset_in_progress_status = r;
6411 ioc->shost_recovery = 0;
6412 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
6413 ioc->ioc_reset_count++;
6414 mutex_unlock(&ioc->reset_in_progress_mutex);
6417 if ((r == 0) && is_trigger) {
6419 mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
6421 mpt3sas_trigger_master(ioc,
6422 MASTER_TRIGGER_ADAPTER_RESET);
6424 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,