1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Broadcom MPI3 Storage Controllers
5 * Copyright (C) 2017-2023 Broadcom Inc.
6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
11 #include <linux/io-64-nonatomic-lo-hi.h>
14 mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u32 reset_reason);
15 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc);
16 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
17 struct mpi3_ioc_facts_data *facts_data);
18 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
19 struct mpi3mr_drv_cmd *drv_cmd);
21 static int poll_queues;
22 module_param(poll_queues, int, 0444);
23 MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)");
25 #if defined(writeq) && defined(CONFIG_64BIT)
26 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
31 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
35 writel((u32)(data_out), addr);
36 writel((u32)(data_out >> 32), (addr + 4));
41 mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q)
43 u16 pi, ci, max_entries;
44 bool is_qfull = false;
47 ci = READ_ONCE(op_req_q->ci);
48 max_entries = op_req_q->num_requests;
50 if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1))))
56 static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc)
60 max_vectors = mrioc->intr_info_count;
62 for (i = 0; i < max_vectors; i++)
63 synchronize_irq(pci_irq_vector(mrioc->pdev, i));
66 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc)
68 mrioc->intr_enabled = 0;
69 mpi3mr_sync_irqs(mrioc);
72 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc)
74 mrioc->intr_enabled = 1;
77 static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc)
81 mpi3mr_ioc_disable_intr(mrioc);
83 if (!mrioc->intr_info)
86 for (i = 0; i < mrioc->intr_info_count; i++)
87 free_irq(pci_irq_vector(mrioc->pdev, i),
88 (mrioc->intr_info + i));
90 kfree(mrioc->intr_info);
91 mrioc->intr_info = NULL;
92 mrioc->intr_info_count = 0;
93 mrioc->is_intr_info_set = false;
94 pci_free_irq_vectors(mrioc->pdev);
97 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
100 struct mpi3_sge_common *sgel = paddr;
103 sgel->length = cpu_to_le32(length);
104 sgel->address = cpu_to_le64(dma_addr);
107 void mpi3mr_build_zero_len_sge(void *paddr)
109 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
111 mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1);
114 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
115 dma_addr_t phys_addr)
120 if ((phys_addr < mrioc->reply_buf_dma) ||
121 (phys_addr > mrioc->reply_buf_dma_max_address))
124 return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma);
127 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
128 dma_addr_t phys_addr)
133 return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma);
136 static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc,
142 spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags);
143 old_idx = mrioc->reply_free_queue_host_index;
144 mrioc->reply_free_queue_host_index = (
145 (mrioc->reply_free_queue_host_index ==
146 (mrioc->reply_free_qsz - 1)) ? 0 :
147 (mrioc->reply_free_queue_host_index + 1));
148 mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma);
149 writel(mrioc->reply_free_queue_host_index,
150 &mrioc->sysif_regs->reply_free_host_index);
151 spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags);
154 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
160 spin_lock_irqsave(&mrioc->sbq_lock, flags);
161 old_idx = mrioc->sbq_host_index;
162 mrioc->sbq_host_index = ((mrioc->sbq_host_index ==
163 (mrioc->sense_buf_q_sz - 1)) ? 0 :
164 (mrioc->sbq_host_index + 1));
165 mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma);
166 writel(mrioc->sbq_host_index,
167 &mrioc->sysif_regs->sense_buffer_free_host_index);
168 spin_unlock_irqrestore(&mrioc->sbq_lock, flags);
171 static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc,
172 struct mpi3_event_notification_reply *event_reply)
177 event = event_reply->event;
180 case MPI3_EVENT_LOG_DATA:
183 case MPI3_EVENT_CHANGE:
184 desc = "Event Change";
186 case MPI3_EVENT_GPIO_INTERRUPT:
187 desc = "GPIO Interrupt";
189 case MPI3_EVENT_CABLE_MGMT:
190 desc = "Cable Management";
192 case MPI3_EVENT_ENERGY_PACK_CHANGE:
193 desc = "Energy Pack Change";
195 case MPI3_EVENT_DEVICE_ADDED:
197 struct mpi3_device_page0 *event_data =
198 (struct mpi3_device_page0 *)event_reply->event_data;
199 ioc_info(mrioc, "Device Added: dev=0x%04x Form=0x%x\n",
200 event_data->dev_handle, event_data->device_form);
203 case MPI3_EVENT_DEVICE_INFO_CHANGED:
205 struct mpi3_device_page0 *event_data =
206 (struct mpi3_device_page0 *)event_reply->event_data;
207 ioc_info(mrioc, "Device Info Changed: dev=0x%04x Form=0x%x\n",
208 event_data->dev_handle, event_data->device_form);
211 case MPI3_EVENT_DEVICE_STATUS_CHANGE:
213 struct mpi3_event_data_device_status_change *event_data =
214 (struct mpi3_event_data_device_status_change *)event_reply->event_data;
215 ioc_info(mrioc, "Device status Change: dev=0x%04x RC=0x%x\n",
216 event_data->dev_handle, event_data->reason_code);
219 case MPI3_EVENT_SAS_DISCOVERY:
221 struct mpi3_event_data_sas_discovery *event_data =
222 (struct mpi3_event_data_sas_discovery *)event_reply->event_data;
223 ioc_info(mrioc, "SAS Discovery: (%s) status (0x%08x)\n",
224 (event_data->reason_code == MPI3_EVENT_SAS_DISC_RC_STARTED) ?
226 le32_to_cpu(event_data->discovery_status));
229 case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE:
230 desc = "SAS Broadcast Primitive";
232 case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE:
233 desc = "SAS Notify Primitive";
235 case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
236 desc = "SAS Init Device Status Change";
238 case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW:
239 desc = "SAS Init Table Overflow";
241 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
242 desc = "SAS Topology Change List";
244 case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE:
245 desc = "Enclosure Device Status Change";
247 case MPI3_EVENT_ENCL_DEVICE_ADDED:
248 desc = "Enclosure Added";
250 case MPI3_EVENT_HARD_RESET_RECEIVED:
251 desc = "Hard Reset Received";
253 case MPI3_EVENT_SAS_PHY_COUNTER:
254 desc = "SAS PHY Counter";
256 case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
257 desc = "SAS Device Discovery Error";
259 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
260 desc = "PCIE Topology Change List";
262 case MPI3_EVENT_PCIE_ENUMERATION:
264 struct mpi3_event_data_pcie_enumeration *event_data =
265 (struct mpi3_event_data_pcie_enumeration *)event_reply->event_data;
266 ioc_info(mrioc, "PCIE Enumeration: (%s)",
267 (event_data->reason_code ==
268 MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : "stop");
269 if (event_data->enumeration_status)
270 ioc_info(mrioc, "enumeration_status(0x%08x)\n",
271 le32_to_cpu(event_data->enumeration_status));
274 case MPI3_EVENT_PREPARE_FOR_RESET:
275 desc = "Prepare For Reset";
282 ioc_info(mrioc, "%s\n", desc);
285 static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc,
286 struct mpi3_default_reply *def_reply)
288 struct mpi3_event_notification_reply *event_reply =
289 (struct mpi3_event_notification_reply *)def_reply;
291 mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count);
292 mpi3mr_print_event_data(mrioc, event_reply);
293 mpi3mr_os_handle_events(mrioc, event_reply);
296 static struct mpi3mr_drv_cmd *
297 mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag,
298 struct mpi3_default_reply *def_reply)
303 case MPI3MR_HOSTTAG_INITCMDS:
304 return &mrioc->init_cmds;
305 case MPI3MR_HOSTTAG_CFG_CMDS:
306 return &mrioc->cfg_cmds;
307 case MPI3MR_HOSTTAG_BSG_CMDS:
308 return &mrioc->bsg_cmds;
309 case MPI3MR_HOSTTAG_BLK_TMS:
310 return &mrioc->host_tm_cmds;
311 case MPI3MR_HOSTTAG_PEL_ABORT:
312 return &mrioc->pel_abort_cmd;
313 case MPI3MR_HOSTTAG_PEL_WAIT:
314 return &mrioc->pel_cmds;
315 case MPI3MR_HOSTTAG_TRANSPORT_CMDS:
316 return &mrioc->transport_cmds;
317 case MPI3MR_HOSTTAG_INVALID:
318 if (def_reply && def_reply->function ==
319 MPI3_FUNCTION_EVENT_NOTIFICATION)
320 mpi3mr_handle_events(mrioc, def_reply);
325 if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN &&
326 host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) {
327 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN;
328 return &mrioc->dev_rmhs_cmds[idx];
331 if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN &&
332 host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) {
333 idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN;
334 return &mrioc->evtack_cmds[idx];
340 static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc,
341 struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma)
343 u16 reply_desc_type, host_tag = 0;
344 u16 ioc_status = MPI3_IOCSTATUS_SUCCESS;
346 struct mpi3_status_reply_descriptor *status_desc;
347 struct mpi3_address_reply_descriptor *addr_desc;
348 struct mpi3_success_reply_descriptor *success_desc;
349 struct mpi3_default_reply *def_reply = NULL;
350 struct mpi3mr_drv_cmd *cmdptr = NULL;
351 struct mpi3_scsi_io_reply *scsi_reply;
352 u8 *sense_buf = NULL;
355 reply_desc_type = le16_to_cpu(reply_desc->reply_flags) &
356 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK;
357 switch (reply_desc_type) {
358 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS:
359 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc;
360 host_tag = le16_to_cpu(status_desc->host_tag);
361 ioc_status = le16_to_cpu(status_desc->ioc_status);
363 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
364 ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info);
365 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK;
367 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY:
368 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc;
369 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address);
370 def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma);
373 host_tag = le16_to_cpu(def_reply->host_tag);
374 ioc_status = le16_to_cpu(def_reply->ioc_status);
376 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
377 ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info);
378 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK;
379 if (def_reply->function == MPI3_FUNCTION_SCSI_IO) {
380 scsi_reply = (struct mpi3_scsi_io_reply *)def_reply;
381 sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc,
382 le64_to_cpu(scsi_reply->sense_data_buffer_address));
385 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS:
386 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc;
387 host_tag = le16_to_cpu(success_desc->host_tag);
393 cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply);
395 if (cmdptr->state & MPI3MR_CMD_PENDING) {
396 cmdptr->state |= MPI3MR_CMD_COMPLETE;
397 cmdptr->ioc_loginfo = ioc_loginfo;
398 cmdptr->ioc_status = ioc_status;
399 cmdptr->state &= ~MPI3MR_CMD_PENDING;
401 cmdptr->state |= MPI3MR_CMD_REPLY_VALID;
402 memcpy((u8 *)cmdptr->reply, (u8 *)def_reply,
405 if (cmdptr->is_waiting) {
406 complete(&cmdptr->done);
407 cmdptr->is_waiting = 0;
408 } else if (cmdptr->callback)
409 cmdptr->callback(mrioc, cmdptr);
414 mpi3mr_repost_sense_buf(mrioc,
415 le64_to_cpu(scsi_reply->sense_data_buffer_address));
418 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc)
420 u32 exp_phase = mrioc->admin_reply_ephase;
421 u32 admin_reply_ci = mrioc->admin_reply_ci;
422 u32 num_admin_replies = 0;
424 struct mpi3_default_reply_descriptor *reply_desc;
426 if (!atomic_add_unless(&mrioc->admin_reply_q_in_use, 1, 1))
429 reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
432 if ((le16_to_cpu(reply_desc->reply_flags) &
433 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
434 atomic_dec(&mrioc->admin_reply_q_in_use);
439 if (mrioc->unrecoverable)
442 mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci);
443 mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma);
445 mpi3mr_repost_reply_buf(mrioc, reply_dma);
447 if (++admin_reply_ci == mrioc->num_admin_replies) {
452 (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
454 if ((le16_to_cpu(reply_desc->reply_flags) &
455 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
459 writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
460 mrioc->admin_reply_ci = admin_reply_ci;
461 mrioc->admin_reply_ephase = exp_phase;
462 atomic_dec(&mrioc->admin_reply_q_in_use);
464 return num_admin_replies;
468 * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to
469 * queue's consumer index from operational reply descriptor queue.
470 * @op_reply_q: op_reply_qinfo object
471 * @reply_ci: operational reply descriptor's queue consumer index
473 * Returns reply descriptor frame address
475 static inline struct mpi3_default_reply_descriptor *
476 mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci)
478 void *segment_base_addr;
479 struct segments *segments = op_reply_q->q_segments;
480 struct mpi3_default_reply_descriptor *reply_desc = NULL;
483 segments[reply_ci / op_reply_q->segment_qd].segment;
484 reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr +
485 (reply_ci % op_reply_q->segment_qd);
490 * mpi3mr_process_op_reply_q - Operational reply queue handler
491 * @mrioc: Adapter instance reference
492 * @op_reply_q: Operational reply queue info
494 * Checks the specific operational reply queue and drains the
495 * reply queue entries until the queue is empty and process the
496 * individual reply descriptors.
498 * Return: 0 if queue is already processed,or number of reply
499 * descriptors processed.
501 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
502 struct op_reply_qinfo *op_reply_q)
504 struct op_req_qinfo *op_req_q;
507 u32 num_op_reply = 0;
509 struct mpi3_default_reply_descriptor *reply_desc;
510 u16 req_q_idx = 0, reply_qidx;
512 reply_qidx = op_reply_q->qid - 1;
514 if (!atomic_add_unless(&op_reply_q->in_use, 1, 1))
517 exp_phase = op_reply_q->ephase;
518 reply_ci = op_reply_q->ci;
520 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
521 if ((le16_to_cpu(reply_desc->reply_flags) &
522 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
523 atomic_dec(&op_reply_q->in_use);
528 if (mrioc->unrecoverable)
531 req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1;
532 op_req_q = &mrioc->req_qinfo[req_q_idx];
534 WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci));
535 mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma,
537 atomic_dec(&op_reply_q->pend_ios);
539 mpi3mr_repost_reply_buf(mrioc, reply_dma);
542 if (++reply_ci == op_reply_q->num_replies) {
547 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
549 if ((le16_to_cpu(reply_desc->reply_flags) &
550 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
552 #ifndef CONFIG_PREEMPT_RT
554 * Exit completion loop to avoid CPU lockup
555 * Ensure remaining completion happens from threaded ISR.
557 if (num_op_reply > mrioc->max_host_ios) {
558 op_reply_q->enable_irq_poll = true;
565 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index);
566 op_reply_q->ci = reply_ci;
567 op_reply_q->ephase = exp_phase;
569 atomic_dec(&op_reply_q->in_use);
574 * mpi3mr_blk_mq_poll - Operational reply queue handler
575 * @shost: SCSI Host reference
576 * @queue_num: Request queue number (w.r.t OS it is hardware context number)
578 * Checks the specific operational reply queue and drains the
579 * reply queue entries until the queue is empty and process the
580 * individual reply descriptors.
582 * Return: 0 if queue is already processed,or number of reply
583 * descriptors processed.
585 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num)
588 struct mpi3mr_ioc *mrioc;
590 mrioc = (struct mpi3mr_ioc *)shost->hostdata;
592 if ((mrioc->reset_in_progress || mrioc->prepare_for_reset ||
593 mrioc->unrecoverable))
596 num_entries = mpi3mr_process_op_reply_q(mrioc,
597 &mrioc->op_reply_qinfo[queue_num]);
602 static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata)
604 struct mpi3mr_intr_info *intr_info = privdata;
605 struct mpi3mr_ioc *mrioc;
607 u32 num_admin_replies = 0, num_op_reply = 0;
612 mrioc = intr_info->mrioc;
614 if (!mrioc->intr_enabled)
617 midx = intr_info->msix_index;
620 num_admin_replies = mpi3mr_process_admin_reply_q(mrioc);
621 if (intr_info->op_reply_q)
622 num_op_reply = mpi3mr_process_op_reply_q(mrioc,
623 intr_info->op_reply_q);
625 if (num_admin_replies || num_op_reply)
631 #ifndef CONFIG_PREEMPT_RT
633 static irqreturn_t mpi3mr_isr(int irq, void *privdata)
635 struct mpi3mr_intr_info *intr_info = privdata;
641 /* Call primary ISR routine */
642 ret = mpi3mr_isr_primary(irq, privdata);
645 * If more IOs are expected, schedule IRQ polling thread.
646 * Otherwise exit from ISR.
648 if (!intr_info->op_reply_q)
651 if (!intr_info->op_reply_q->enable_irq_poll ||
652 !atomic_read(&intr_info->op_reply_q->pend_ios))
655 disable_irq_nosync(intr_info->os_irq);
657 return IRQ_WAKE_THREAD;
661 * mpi3mr_isr_poll - Reply queue polling routine
663 * @privdata: Interrupt info
665 * poll for pending I/O completions in a loop until pending I/Os
666 * present or controller queue depth I/Os are processed.
668 * Return: IRQ_NONE or IRQ_HANDLED
670 static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata)
672 struct mpi3mr_intr_info *intr_info = privdata;
673 struct mpi3mr_ioc *mrioc;
675 u32 num_op_reply = 0;
677 if (!intr_info || !intr_info->op_reply_q)
680 mrioc = intr_info->mrioc;
681 midx = intr_info->msix_index;
683 /* Poll for pending IOs completions */
685 if (!mrioc->intr_enabled || mrioc->unrecoverable)
689 mpi3mr_process_admin_reply_q(mrioc);
690 if (intr_info->op_reply_q)
692 mpi3mr_process_op_reply_q(mrioc,
693 intr_info->op_reply_q);
695 usleep_range(MPI3MR_IRQ_POLL_SLEEP, 10 * MPI3MR_IRQ_POLL_SLEEP);
697 } while (atomic_read(&intr_info->op_reply_q->pend_ios) &&
698 (num_op_reply < mrioc->max_host_ios));
700 intr_info->op_reply_q->enable_irq_poll = false;
701 enable_irq(intr_info->os_irq);
709 * mpi3mr_request_irq - Request IRQ and register ISR
710 * @mrioc: Adapter instance reference
711 * @index: IRQ vector index
713 * Request threaded ISR with primary ISR and secondary
715 * Return: 0 on success and non zero on failures.
717 static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index)
719 struct pci_dev *pdev = mrioc->pdev;
720 struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index;
723 intr_info->mrioc = mrioc;
724 intr_info->msix_index = index;
725 intr_info->op_reply_q = NULL;
727 snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d",
728 mrioc->driver_name, mrioc->id, index);
730 #ifndef CONFIG_PREEMPT_RT
731 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr,
732 mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info);
734 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr_primary,
735 NULL, IRQF_SHARED, intr_info->name, intr_info);
738 ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n",
739 intr_info->name, pci_irq_vector(pdev, index));
743 intr_info->os_irq = pci_irq_vector(pdev, index);
747 static void mpi3mr_calc_poll_queues(struct mpi3mr_ioc *mrioc, u16 max_vectors)
749 if (!mrioc->requested_poll_qcount)
752 /* Reserved for Admin and Default Queue */
753 if (max_vectors > 2 &&
754 (mrioc->requested_poll_qcount < max_vectors - 2)) {
756 "enabled polled queues (%d) msix (%d)\n",
757 mrioc->requested_poll_qcount, max_vectors);
760 "disabled polled queues (%d) msix (%d) because of no resources for default queue\n",
761 mrioc->requested_poll_qcount, max_vectors);
762 mrioc->requested_poll_qcount = 0;
767 * mpi3mr_setup_isr - Setup ISR for the controller
768 * @mrioc: Adapter instance reference
769 * @setup_one: Request one IRQ or more
771 * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR
773 * Return: 0 on success and non zero on failures.
775 static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one)
777 unsigned int irq_flags = PCI_IRQ_MSIX;
778 int max_vectors, min_vec;
781 struct irq_affinity desc = { .pre_vectors = 1, .post_vectors = 1 };
783 if (mrioc->is_intr_info_set)
786 mpi3mr_cleanup_isr(mrioc);
788 if (setup_one || reset_devices) {
790 retval = pci_alloc_irq_vectors(mrioc->pdev,
791 1, max_vectors, irq_flags);
793 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
799 min_t(int, mrioc->cpu_count + 1 +
800 mrioc->requested_poll_qcount, mrioc->msix_count);
802 mpi3mr_calc_poll_queues(mrioc, max_vectors);
805 "MSI-X vectors supported: %d, no of cores: %d,",
806 mrioc->msix_count, mrioc->cpu_count);
808 "MSI-x vectors requested: %d poll_queues %d\n",
809 max_vectors, mrioc->requested_poll_qcount);
811 desc.post_vectors = mrioc->requested_poll_qcount;
812 min_vec = desc.pre_vectors + desc.post_vectors;
813 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES;
815 retval = pci_alloc_irq_vectors_affinity(mrioc->pdev,
816 min_vec, max_vectors, irq_flags, &desc);
819 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
826 * If only one MSI-x is allocated, then MSI-x 0 will be shared
827 * between Admin queue and operational queue
829 if (retval == min_vec)
830 mrioc->op_reply_q_offset = 0;
831 else if (retval != (max_vectors)) {
833 "allocated vectors (%d) are less than configured (%d)\n",
834 retval, max_vectors);
837 max_vectors = retval;
838 mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0;
840 mpi3mr_calc_poll_queues(mrioc, max_vectors);
844 mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors,
846 if (!mrioc->intr_info) {
848 pci_free_irq_vectors(mrioc->pdev);
851 for (i = 0; i < max_vectors; i++) {
852 retval = mpi3mr_request_irq(mrioc, i);
854 mrioc->intr_info_count = i;
858 if (reset_devices || !setup_one)
859 mrioc->is_intr_info_set = true;
860 mrioc->intr_info_count = max_vectors;
861 mpi3mr_ioc_enable_intr(mrioc);
865 mpi3mr_cleanup_isr(mrioc);
870 static const struct {
871 enum mpi3mr_iocstate value;
874 { MRIOC_STATE_READY, "ready" },
875 { MRIOC_STATE_FAULT, "fault" },
876 { MRIOC_STATE_RESET, "reset" },
877 { MRIOC_STATE_BECOMING_READY, "becoming ready" },
878 { MRIOC_STATE_RESET_REQUESTED, "reset requested" },
879 { MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" },
882 static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state)
887 for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) {
888 if (mrioc_states[i].value == mrioc_state) {
889 name = mrioc_states[i].name;
896 /* Reset reason to name mapper structure*/
897 static const struct {
898 enum mpi3mr_reset_reason value;
900 } mpi3mr_reset_reason_codes[] = {
901 { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" },
902 { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" },
903 { MPI3MR_RESET_FROM_APP, "application invocation" },
904 { MPI3MR_RESET_FROM_EH_HOS, "error handling" },
905 { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" },
906 { MPI3MR_RESET_FROM_APP_TIMEOUT, "application command timeout" },
907 { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" },
908 { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" },
909 { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" },
910 { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" },
911 { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" },
912 { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" },
913 { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" },
915 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT,
916 "create request queue timeout"
919 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT,
920 "create reply queue timeout"
922 { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" },
923 { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" },
924 { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" },
925 { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" },
927 MPI3MR_RESET_FROM_CIACTVRST_TIMER,
928 "component image activation timeout"
931 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT,
932 "get package version timeout"
934 { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" },
935 { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" },
936 { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronous reset" },
937 { MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT, "configuration request timeout"},
938 { MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT, "timeout of a SAS transport layer request" },
942 * mpi3mr_reset_rc_name - get reset reason code name
943 * @reason_code: reset reason code value
945 * Map reset reason to an NULL terminated ASCII string
947 * Return: name corresponding to reset reason value or NULL.
949 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code)
954 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_reason_codes); i++) {
955 if (mpi3mr_reset_reason_codes[i].value == reason_code) {
956 name = mpi3mr_reset_reason_codes[i].name;
963 /* Reset type to name mapper structure*/
964 static const struct {
967 } mpi3mr_reset_types[] = {
968 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" },
969 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" },
973 * mpi3mr_reset_type_name - get reset type name
974 * @reset_type: reset type value
976 * Map reset type to an NULL terminated ASCII string
978 * Return: name corresponding to reset type value or NULL.
980 static const char *mpi3mr_reset_type_name(u16 reset_type)
985 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_types); i++) {
986 if (mpi3mr_reset_types[i].reset_type == reset_type) {
987 name = mpi3mr_reset_types[i].name;
995 * mpi3mr_print_fault_info - Display fault information
996 * @mrioc: Adapter instance reference
998 * Display the controller fault information if there is a
1003 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc)
1005 u32 ioc_status, code, code1, code2, code3;
1007 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1009 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1010 code = readl(&mrioc->sysif_regs->fault);
1011 code1 = readl(&mrioc->sysif_regs->fault_info[0]);
1012 code2 = readl(&mrioc->sysif_regs->fault_info[1]);
1013 code3 = readl(&mrioc->sysif_regs->fault_info[2]);
1016 "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n",
1017 code, code1, code2, code3);
1022 * mpi3mr_get_iocstate - Get IOC State
1023 * @mrioc: Adapter instance reference
1025 * Return a proper IOC state enum based on the IOC status and
1026 * IOC configuration and unrcoverable state of the controller.
1028 * Return: Current IOC state.
1030 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc)
1032 u32 ioc_status, ioc_config;
1035 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1036 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1038 if (mrioc->unrecoverable)
1039 return MRIOC_STATE_UNRECOVERABLE;
1040 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)
1041 return MRIOC_STATE_FAULT;
1043 ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY);
1044 enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC);
1046 if (ready && enabled)
1047 return MRIOC_STATE_READY;
1048 if ((!ready) && (!enabled))
1049 return MRIOC_STATE_RESET;
1050 if ((!ready) && (enabled))
1051 return MRIOC_STATE_BECOMING_READY;
1053 return MRIOC_STATE_RESET_REQUESTED;
1057 * mpi3mr_clear_reset_history - clear reset history
1058 * @mrioc: Adapter instance reference
1060 * Write the reset history bit in IOC status to clear the bit,
1061 * if it is already set.
1065 static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc)
1069 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1070 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1071 writel(ioc_status, &mrioc->sysif_regs->ioc_status);
1075 * mpi3mr_issue_and_process_mur - Message unit Reset handler
1076 * @mrioc: Adapter instance reference
1077 * @reset_reason: Reset reason code
1079 * Issue Message unit Reset to the controller and wait for it to
1082 * Return: 0 on success, -1 on failure.
1084 static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc,
1087 u32 ioc_config, timeout, ioc_status;
1090 ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n");
1091 if (mrioc->unrecoverable) {
1092 ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n");
1095 mpi3mr_clear_reset_history(mrioc);
1096 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1097 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1098 ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1099 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1101 timeout = MPI3MR_MUR_TIMEOUT * 10;
1103 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1104 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) {
1105 mpi3mr_clear_reset_history(mrioc);
1108 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1109 mpi3mr_print_fault_info(mrioc);
1113 } while (--timeout);
1115 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1116 if (timeout && !((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1117 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) ||
1118 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1121 ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%x)/(0x%x)\n",
1122 (!retval) ? "successful" : "failed", ioc_status, ioc_config);
1127 * mpi3mr_revalidate_factsdata - validate IOCFacts parameters
1128 * during reset/resume
1129 * @mrioc: Adapter instance reference
1131 * Return zero if the new IOCFacts parameters value is compatible with
1132 * older values else return -EPERM
1135 mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc)
1137 void *removepend_bitmap;
1139 if (mrioc->facts.reply_sz > mrioc->reply_sz) {
1141 "cannot increase reply size from %d to %d\n",
1142 mrioc->reply_sz, mrioc->facts.reply_sz);
1146 if (mrioc->facts.max_op_reply_q < mrioc->num_op_reply_q) {
1148 "cannot reduce number of operational reply queues from %d to %d\n",
1149 mrioc->num_op_reply_q,
1150 mrioc->facts.max_op_reply_q);
1154 if (mrioc->facts.max_op_req_q < mrioc->num_op_req_q) {
1156 "cannot reduce number of operational request queues from %d to %d\n",
1157 mrioc->num_op_req_q, mrioc->facts.max_op_req_q);
1161 if ((mrioc->sas_transport_enabled) && (mrioc->facts.ioc_capabilities &
1162 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED))
1164 "critical error: multipath capability is enabled at the\n"
1165 "\tcontroller while sas transport support is enabled at the\n"
1166 "\tdriver, please reboot the system or reload the driver\n");
1168 if (mrioc->facts.max_devhandle > mrioc->dev_handle_bitmap_bits) {
1169 removepend_bitmap = bitmap_zalloc(mrioc->facts.max_devhandle,
1171 if (!removepend_bitmap) {
1173 "failed to increase removepend_bitmap bits from %d to %d\n",
1174 mrioc->dev_handle_bitmap_bits,
1175 mrioc->facts.max_devhandle);
1178 bitmap_free(mrioc->removepend_bitmap);
1179 mrioc->removepend_bitmap = removepend_bitmap;
1181 "increased bits of dev_handle_bitmap from %d to %d\n",
1182 mrioc->dev_handle_bitmap_bits,
1183 mrioc->facts.max_devhandle);
1184 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
1191 * mpi3mr_bring_ioc_ready - Bring controller to ready state
1192 * @mrioc: Adapter instance reference
1194 * Set Enable IOC bit in IOC configuration register and wait for
1195 * the controller to become ready.
1197 * Return: 0 on success, appropriate error on failure.
1199 static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc)
1201 u32 ioc_config, ioc_status, timeout, host_diagnostic;
1203 enum mpi3mr_iocstate ioc_state;
1206 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1207 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1208 base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information);
1209 ioc_info(mrioc, "ioc_status(0x%08x), ioc_config(0x%08x), ioc_info(0x%016llx) at the bringup\n",
1210 ioc_status, ioc_config, base_info);
1212 /*The timeout value is in 2sec unit, changing it to seconds*/
1213 mrioc->ready_timeout =
1214 ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >>
1215 MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2;
1217 ioc_info(mrioc, "ready timeout: %d seconds\n", mrioc->ready_timeout);
1219 ioc_state = mpi3mr_get_iocstate(mrioc);
1220 ioc_info(mrioc, "controller is in %s state during detection\n",
1221 mpi3mr_iocstate_name(ioc_state));
1223 if (ioc_state == MRIOC_STATE_BECOMING_READY ||
1224 ioc_state == MRIOC_STATE_RESET_REQUESTED) {
1225 timeout = mrioc->ready_timeout * 10;
1228 } while (--timeout);
1230 if (!pci_device_is_present(mrioc->pdev)) {
1231 mrioc->unrecoverable = 1;
1233 "controller is not present while waiting to reset\n");
1235 goto out_device_not_present;
1238 ioc_state = mpi3mr_get_iocstate(mrioc);
1240 "controller is in %s state after waiting to reset\n",
1241 mpi3mr_iocstate_name(ioc_state));
1244 if (ioc_state == MRIOC_STATE_READY) {
1245 ioc_info(mrioc, "issuing message unit reset (MUR) to bring to reset state\n");
1246 retval = mpi3mr_issue_and_process_mur(mrioc,
1247 MPI3MR_RESET_FROM_BRINGUP);
1248 ioc_state = mpi3mr_get_iocstate(mrioc);
1251 "message unit reset failed with error %d current state %s\n",
1252 retval, mpi3mr_iocstate_name(ioc_state));
1254 if (ioc_state != MRIOC_STATE_RESET) {
1255 if (ioc_state == MRIOC_STATE_FAULT) {
1256 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
1257 mpi3mr_print_fault_info(mrioc);
1260 readl(&mrioc->sysif_regs->host_diagnostic);
1261 if (!(host_diagnostic &
1262 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
1264 if (!pci_device_is_present(mrioc->pdev)) {
1265 mrioc->unrecoverable = 1;
1266 ioc_err(mrioc, "controller is not present at the bringup\n");
1267 goto out_device_not_present;
1270 } while (--timeout);
1272 mpi3mr_print_fault_info(mrioc);
1273 ioc_info(mrioc, "issuing soft reset to bring to reset state\n");
1274 retval = mpi3mr_issue_reset(mrioc,
1275 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
1276 MPI3MR_RESET_FROM_BRINGUP);
1279 "soft reset failed with error %d\n", retval);
1283 ioc_state = mpi3mr_get_iocstate(mrioc);
1284 if (ioc_state != MRIOC_STATE_RESET) {
1286 "cannot bring controller to reset state, current state: %s\n",
1287 mpi3mr_iocstate_name(ioc_state));
1290 mpi3mr_clear_reset_history(mrioc);
1291 retval = mpi3mr_setup_admin_qpair(mrioc);
1293 ioc_err(mrioc, "failed to setup admin queues: error %d\n",
1298 ioc_info(mrioc, "bringing controller to ready state\n");
1299 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1300 ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1301 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1303 timeout = mrioc->ready_timeout * 10;
1305 ioc_state = mpi3mr_get_iocstate(mrioc);
1306 if (ioc_state == MRIOC_STATE_READY) {
1308 "successfully transitioned to %s state\n",
1309 mpi3mr_iocstate_name(ioc_state));
1312 if (!pci_device_is_present(mrioc->pdev)) {
1313 mrioc->unrecoverable = 1;
1315 "controller is not present at the bringup\n");
1317 goto out_device_not_present;
1320 } while (--timeout);
1323 ioc_state = mpi3mr_get_iocstate(mrioc);
1325 "failed to bring to ready state, current state: %s\n",
1326 mpi3mr_iocstate_name(ioc_state));
1327 out_device_not_present:
1332 * mpi3mr_soft_reset_success - Check softreset is success or not
1333 * @ioc_status: IOC status register value
1334 * @ioc_config: IOC config register value
1336 * Check whether the soft reset is successful or not based on
1337 * IOC status and IOC config register values.
1339 * Return: True when the soft reset is success, false otherwise.
1342 mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config)
1344 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1345 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1351 * mpi3mr_diagfault_success - Check diag fault is success or not
1352 * @mrioc: Adapter reference
1353 * @ioc_status: IOC status register value
1355 * Check whether the controller hit diag reset fault code.
1357 * Return: True when there is diag fault, false otherwise.
1359 static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc,
1364 if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT))
1366 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
1367 if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) {
1368 mpi3mr_print_fault_info(mrioc);
1375 * mpi3mr_set_diagsave - Set diag save bit for snapdump
1376 * @mrioc: Adapter reference
1378 * Set diag save bit in IOC configuration register to enable
1383 static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc)
1387 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1388 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE;
1389 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1393 * mpi3mr_issue_reset - Issue reset to the controller
1394 * @mrioc: Adapter reference
1395 * @reset_type: Reset type
1396 * @reset_reason: Reset reason code
1398 * Unlock the host diagnostic registers and write the specific
1399 * reset type to that, wait for reset acknowledgment from the
1400 * controller, if the reset is not successful retry for the
1401 * predefined number of times.
1403 * Return: 0 on success, non-zero on failure.
1405 static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type,
1409 u8 unlock_retry_count = 0;
1410 u32 host_diagnostic, ioc_status, ioc_config;
1411 u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
1413 if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) &&
1414 (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT))
1416 if (mrioc->unrecoverable)
1418 if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) {
1423 ioc_info(mrioc, "%s reset due to %s(0x%x)\n",
1424 mpi3mr_reset_type_name(reset_type),
1425 mpi3mr_reset_rc_name(reset_reason), reset_reason);
1427 mpi3mr_clear_reset_history(mrioc);
1430 "Write magic sequence to unlock host diag register (retry=%d)\n",
1431 ++unlock_retry_count);
1432 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) {
1434 "%s reset failed due to unlock failure, host_diagnostic(0x%08x)\n",
1435 mpi3mr_reset_type_name(reset_type),
1437 mrioc->unrecoverable = 1;
1441 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH,
1442 &mrioc->sysif_regs->write_sequence);
1443 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST,
1444 &mrioc->sysif_regs->write_sequence);
1445 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1446 &mrioc->sysif_regs->write_sequence);
1447 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD,
1448 &mrioc->sysif_regs->write_sequence);
1449 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH,
1450 &mrioc->sysif_regs->write_sequence);
1451 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH,
1452 &mrioc->sysif_regs->write_sequence);
1453 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH,
1454 &mrioc->sysif_regs->write_sequence);
1455 usleep_range(1000, 1100);
1456 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
1458 "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n",
1459 unlock_retry_count, host_diagnostic);
1460 } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE));
1462 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1463 writel(host_diagnostic | reset_type,
1464 &mrioc->sysif_regs->host_diagnostic);
1465 switch (reset_type) {
1466 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET:
1468 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1470 readl(&mrioc->sysif_regs->ioc_configuration);
1471 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1472 && mpi3mr_soft_reset_success(ioc_status, ioc_config)
1474 mpi3mr_clear_reset_history(mrioc);
1479 } while (--timeout);
1480 mpi3mr_print_fault_info(mrioc);
1482 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT:
1484 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1485 if (mpi3mr_diagfault_success(mrioc, ioc_status)) {
1490 } while (--timeout);
1496 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1497 &mrioc->sysif_regs->write_sequence);
1499 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1500 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1502 "ioc_status/ioc_onfig after %s reset is (0x%x)/(0x%x)\n",
1503 (!retval)?"successful":"failed", ioc_status,
1506 mrioc->unrecoverable = 1;
1511 * mpi3mr_admin_request_post - Post request to admin queue
1512 * @mrioc: Adapter reference
1513 * @admin_req: MPI3 request
1514 * @admin_req_sz: Request size
1515 * @ignore_reset: Ignore reset in process
1517 * Post the MPI3 request into admin request queue and
1518 * inform the controller, if the queue is full return
1519 * appropriate error.
1521 * Return: 0 on success, non-zero on failure.
1523 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1524 u16 admin_req_sz, u8 ignore_reset)
1526 u16 areq_pi = 0, areq_ci = 0, max_entries = 0;
1528 unsigned long flags;
1531 if (mrioc->unrecoverable) {
1532 ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__);
1536 spin_lock_irqsave(&mrioc->admin_req_lock, flags);
1537 areq_pi = mrioc->admin_req_pi;
1538 areq_ci = mrioc->admin_req_ci;
1539 max_entries = mrioc->num_admin_req;
1540 if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) &&
1541 (areq_pi == (max_entries - 1)))) {
1542 ioc_err(mrioc, "AdminReqQ full condition detected\n");
1546 if (!ignore_reset && mrioc->reset_in_progress) {
1547 ioc_err(mrioc, "AdminReqQ submit reset in progress\n");
1551 areq_entry = (u8 *)mrioc->admin_req_base +
1552 (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ);
1553 memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ);
1554 memcpy(areq_entry, (u8 *)admin_req, admin_req_sz);
1556 if (++areq_pi == max_entries)
1558 mrioc->admin_req_pi = areq_pi;
1560 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
1563 spin_unlock_irqrestore(&mrioc->admin_req_lock, flags);
1569 * mpi3mr_free_op_req_q_segments - free request memory segments
1570 * @mrioc: Adapter instance reference
1571 * @q_idx: operational request queue index
1573 * Free memory segments allocated for operational request queue
1577 static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1581 struct segments *segments;
1583 segments = mrioc->req_qinfo[q_idx].q_segments;
1587 if (mrioc->enable_segqueue) {
1588 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1589 if (mrioc->req_qinfo[q_idx].q_segment_list) {
1590 dma_free_coherent(&mrioc->pdev->dev,
1591 MPI3MR_MAX_SEG_LIST_SIZE,
1592 mrioc->req_qinfo[q_idx].q_segment_list,
1593 mrioc->req_qinfo[q_idx].q_segment_list_dma);
1594 mrioc->req_qinfo[q_idx].q_segment_list = NULL;
1597 size = mrioc->req_qinfo[q_idx].segment_qd *
1598 mrioc->facts.op_req_sz;
1600 for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) {
1601 if (!segments[j].segment)
1603 dma_free_coherent(&mrioc->pdev->dev,
1604 size, segments[j].segment, segments[j].segment_dma);
1605 segments[j].segment = NULL;
1607 kfree(mrioc->req_qinfo[q_idx].q_segments);
1608 mrioc->req_qinfo[q_idx].q_segments = NULL;
1609 mrioc->req_qinfo[q_idx].qid = 0;
1613 * mpi3mr_free_op_reply_q_segments - free reply memory segments
1614 * @mrioc: Adapter instance reference
1615 * @q_idx: operational reply queue index
1617 * Free memory segments allocated for operational reply queue
1621 static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1625 struct segments *segments;
1627 segments = mrioc->op_reply_qinfo[q_idx].q_segments;
1631 if (mrioc->enable_segqueue) {
1632 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1633 if (mrioc->op_reply_qinfo[q_idx].q_segment_list) {
1634 dma_free_coherent(&mrioc->pdev->dev,
1635 MPI3MR_MAX_SEG_LIST_SIZE,
1636 mrioc->op_reply_qinfo[q_idx].q_segment_list,
1637 mrioc->op_reply_qinfo[q_idx].q_segment_list_dma);
1638 mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL;
1641 size = mrioc->op_reply_qinfo[q_idx].segment_qd *
1642 mrioc->op_reply_desc_sz;
1644 for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) {
1645 if (!segments[j].segment)
1647 dma_free_coherent(&mrioc->pdev->dev,
1648 size, segments[j].segment, segments[j].segment_dma);
1649 segments[j].segment = NULL;
1652 kfree(mrioc->op_reply_qinfo[q_idx].q_segments);
1653 mrioc->op_reply_qinfo[q_idx].q_segments = NULL;
1654 mrioc->op_reply_qinfo[q_idx].qid = 0;
1658 * mpi3mr_delete_op_reply_q - delete operational reply queue
1659 * @mrioc: Adapter instance reference
1660 * @qidx: operational reply queue index
1662 * Delete operatinal reply queue by issuing MPI request
1663 * through admin queue.
1665 * Return: 0 on success, non-zero on failure.
1667 static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1669 struct mpi3_delete_reply_queue_request delq_req;
1670 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1672 u16 reply_qid = 0, midx;
1674 reply_qid = op_reply_q->qid;
1676 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1680 ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n");
1684 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount-- :
1685 mrioc->active_poll_qcount--;
1687 memset(&delq_req, 0, sizeof(delq_req));
1688 mutex_lock(&mrioc->init_cmds.mutex);
1689 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1691 ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n");
1692 mutex_unlock(&mrioc->init_cmds.mutex);
1695 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1696 mrioc->init_cmds.is_waiting = 1;
1697 mrioc->init_cmds.callback = NULL;
1698 delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1699 delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE;
1700 delq_req.queue_id = cpu_to_le16(reply_qid);
1702 init_completion(&mrioc->init_cmds.done);
1703 retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req),
1706 ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n");
1709 wait_for_completion_timeout(&mrioc->init_cmds.done,
1710 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1711 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1712 ioc_err(mrioc, "delete reply queue timed out\n");
1713 mpi3mr_check_rh_fault_ioc(mrioc,
1714 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT);
1718 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1719 != MPI3_IOCSTATUS_SUCCESS) {
1721 "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1722 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1723 mrioc->init_cmds.ioc_loginfo);
1727 mrioc->intr_info[midx].op_reply_q = NULL;
1729 mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1731 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1732 mutex_unlock(&mrioc->init_cmds.mutex);
1739 * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool
1740 * @mrioc: Adapter instance reference
1741 * @qidx: request queue index
1743 * Allocate segmented memory pools for operational reply
1746 * Return: 0 on success, non-zero on failure.
1748 static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1750 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1752 u64 *q_segment_list_entry = NULL;
1753 struct segments *segments;
1755 if (mrioc->enable_segqueue) {
1756 op_reply_q->segment_qd =
1757 MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz;
1759 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1761 op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1762 MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma,
1764 if (!op_reply_q->q_segment_list)
1766 q_segment_list_entry = (u64 *)op_reply_q->q_segment_list;
1768 op_reply_q->segment_qd = op_reply_q->num_replies;
1769 size = op_reply_q->num_replies * mrioc->op_reply_desc_sz;
1772 op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies,
1773 op_reply_q->segment_qd);
1775 op_reply_q->q_segments = kcalloc(op_reply_q->num_segments,
1776 sizeof(struct segments), GFP_KERNEL);
1777 if (!op_reply_q->q_segments)
1780 segments = op_reply_q->q_segments;
1781 for (i = 0; i < op_reply_q->num_segments; i++) {
1782 segments[i].segment =
1783 dma_alloc_coherent(&mrioc->pdev->dev,
1784 size, &segments[i].segment_dma, GFP_KERNEL);
1785 if (!segments[i].segment)
1787 if (mrioc->enable_segqueue)
1788 q_segment_list_entry[i] =
1789 (unsigned long)segments[i].segment_dma;
1796 * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool.
1797 * @mrioc: Adapter instance reference
1798 * @qidx: request queue index
1800 * Allocate segmented memory pools for operational request
1803 * Return: 0 on success, non-zero on failure.
1805 static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1807 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
1809 u64 *q_segment_list_entry = NULL;
1810 struct segments *segments;
1812 if (mrioc->enable_segqueue) {
1813 op_req_q->segment_qd =
1814 MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz;
1816 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1818 op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1819 MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma,
1821 if (!op_req_q->q_segment_list)
1823 q_segment_list_entry = (u64 *)op_req_q->q_segment_list;
1826 op_req_q->segment_qd = op_req_q->num_requests;
1827 size = op_req_q->num_requests * mrioc->facts.op_req_sz;
1830 op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests,
1831 op_req_q->segment_qd);
1833 op_req_q->q_segments = kcalloc(op_req_q->num_segments,
1834 sizeof(struct segments), GFP_KERNEL);
1835 if (!op_req_q->q_segments)
1838 segments = op_req_q->q_segments;
1839 for (i = 0; i < op_req_q->num_segments; i++) {
1840 segments[i].segment =
1841 dma_alloc_coherent(&mrioc->pdev->dev,
1842 size, &segments[i].segment_dma, GFP_KERNEL);
1843 if (!segments[i].segment)
1845 if (mrioc->enable_segqueue)
1846 q_segment_list_entry[i] =
1847 (unsigned long)segments[i].segment_dma;
1854 * mpi3mr_create_op_reply_q - create operational reply queue
1855 * @mrioc: Adapter instance reference
1856 * @qidx: operational reply queue index
1858 * Create operatinal reply queue by issuing MPI request
1859 * through admin queue.
1861 * Return: 0 on success, non-zero on failure.
1863 static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1865 struct mpi3_create_reply_queue_request create_req;
1866 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1868 u16 reply_qid = 0, midx;
1870 reply_qid = op_reply_q->qid;
1872 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1876 ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n",
1882 reply_qid = qidx + 1;
1883 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD;
1884 if (!mrioc->pdev->revision)
1885 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K;
1887 op_reply_q->ephase = 1;
1888 atomic_set(&op_reply_q->pend_ios, 0);
1889 atomic_set(&op_reply_q->in_use, 0);
1890 op_reply_q->enable_irq_poll = false;
1892 if (!op_reply_q->q_segments) {
1893 retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx);
1895 mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1900 memset(&create_req, 0, sizeof(create_req));
1901 mutex_lock(&mrioc->init_cmds.mutex);
1902 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1904 ioc_err(mrioc, "CreateRepQ: Init command is in use\n");
1907 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1908 mrioc->init_cmds.is_waiting = 1;
1909 mrioc->init_cmds.callback = NULL;
1910 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1911 create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE;
1912 create_req.queue_id = cpu_to_le16(reply_qid);
1914 if (midx < (mrioc->intr_info_count - mrioc->requested_poll_qcount))
1915 op_reply_q->qtype = MPI3MR_DEFAULT_QUEUE;
1917 op_reply_q->qtype = MPI3MR_POLL_QUEUE;
1919 if (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) {
1921 MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE;
1922 create_req.msix_index =
1923 cpu_to_le16(mrioc->intr_info[midx].msix_index);
1925 create_req.msix_index = cpu_to_le16(mrioc->intr_info_count - 1);
1926 ioc_info(mrioc, "create reply queue(polled): for qid(%d), midx(%d)\n",
1928 if (!mrioc->active_poll_qcount)
1929 disable_irq_nosync(pci_irq_vector(mrioc->pdev,
1930 mrioc->intr_info_count - 1));
1933 if (mrioc->enable_segqueue) {
1935 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
1936 create_req.base_address = cpu_to_le64(
1937 op_reply_q->q_segment_list_dma);
1939 create_req.base_address = cpu_to_le64(
1940 op_reply_q->q_segments[0].segment_dma);
1942 create_req.size = cpu_to_le16(op_reply_q->num_replies);
1944 init_completion(&mrioc->init_cmds.done);
1945 retval = mpi3mr_admin_request_post(mrioc, &create_req,
1946 sizeof(create_req), 1);
1948 ioc_err(mrioc, "CreateRepQ: Admin Post failed\n");
1951 wait_for_completion_timeout(&mrioc->init_cmds.done,
1952 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1953 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1954 ioc_err(mrioc, "create reply queue timed out\n");
1955 mpi3mr_check_rh_fault_ioc(mrioc,
1956 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT);
1960 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1961 != MPI3_IOCSTATUS_SUCCESS) {
1963 "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1964 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1965 mrioc->init_cmds.ioc_loginfo);
1969 op_reply_q->qid = reply_qid;
1970 if (midx < mrioc->intr_info_count)
1971 mrioc->intr_info[midx].op_reply_q = op_reply_q;
1973 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount++ :
1974 mrioc->active_poll_qcount++;
1977 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1978 mutex_unlock(&mrioc->init_cmds.mutex);
1985 * mpi3mr_create_op_req_q - create operational request queue
1986 * @mrioc: Adapter instance reference
1987 * @idx: operational request queue index
1988 * @reply_qid: Reply queue ID
1990 * Create operatinal request queue by issuing MPI request
1991 * through admin queue.
1993 * Return: 0 on success, non-zero on failure.
1995 static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx,
1998 struct mpi3_create_request_queue_request create_req;
1999 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx;
2003 req_qid = op_req_q->qid;
2007 ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n",
2014 op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD;
2017 op_req_q->reply_qid = reply_qid;
2018 spin_lock_init(&op_req_q->q_lock);
2020 if (!op_req_q->q_segments) {
2021 retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx);
2023 mpi3mr_free_op_req_q_segments(mrioc, idx);
2028 memset(&create_req, 0, sizeof(create_req));
2029 mutex_lock(&mrioc->init_cmds.mutex);
2030 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2032 ioc_err(mrioc, "CreateReqQ: Init command is in use\n");
2035 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2036 mrioc->init_cmds.is_waiting = 1;
2037 mrioc->init_cmds.callback = NULL;
2038 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2039 create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE;
2040 create_req.queue_id = cpu_to_le16(req_qid);
2041 if (mrioc->enable_segqueue) {
2043 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
2044 create_req.base_address = cpu_to_le64(
2045 op_req_q->q_segment_list_dma);
2047 create_req.base_address = cpu_to_le64(
2048 op_req_q->q_segments[0].segment_dma);
2049 create_req.reply_queue_id = cpu_to_le16(reply_qid);
2050 create_req.size = cpu_to_le16(op_req_q->num_requests);
2052 init_completion(&mrioc->init_cmds.done);
2053 retval = mpi3mr_admin_request_post(mrioc, &create_req,
2054 sizeof(create_req), 1);
2056 ioc_err(mrioc, "CreateReqQ: Admin Post failed\n");
2059 wait_for_completion_timeout(&mrioc->init_cmds.done,
2060 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2061 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2062 ioc_err(mrioc, "create request queue timed out\n");
2063 mpi3mr_check_rh_fault_ioc(mrioc,
2064 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT);
2068 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2069 != MPI3_IOCSTATUS_SUCCESS) {
2071 "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2072 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2073 mrioc->init_cmds.ioc_loginfo);
2077 op_req_q->qid = req_qid;
2080 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2081 mutex_unlock(&mrioc->init_cmds.mutex);
2088 * mpi3mr_create_op_queues - create operational queue pairs
2089 * @mrioc: Adapter instance reference
2091 * Allocate memory for operational queue meta data and call
2092 * create request and reply queue functions.
2094 * Return: 0 on success, non-zero on failures.
2096 static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc)
2099 u16 num_queues = 0, i = 0, msix_count_op_q = 1;
2101 num_queues = min_t(int, mrioc->facts.max_op_reply_q,
2102 mrioc->facts.max_op_req_q);
2105 mrioc->intr_info_count - mrioc->op_reply_q_offset;
2106 if (!mrioc->num_queues)
2107 mrioc->num_queues = min_t(int, num_queues, msix_count_op_q);
2109 * During reset set the num_queues to the number of queues
2110 * that was set before the reset.
2112 num_queues = mrioc->num_op_reply_q ?
2113 mrioc->num_op_reply_q : mrioc->num_queues;
2114 ioc_info(mrioc, "trying to create %d operational queue pairs\n",
2117 if (!mrioc->req_qinfo) {
2118 mrioc->req_qinfo = kcalloc(num_queues,
2119 sizeof(struct op_req_qinfo), GFP_KERNEL);
2120 if (!mrioc->req_qinfo) {
2125 mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) *
2126 num_queues, GFP_KERNEL);
2127 if (!mrioc->op_reply_qinfo) {
2133 if (mrioc->enable_segqueue)
2135 "allocating operational queues through segmented queues\n");
2137 for (i = 0; i < num_queues; i++) {
2138 if (mpi3mr_create_op_reply_q(mrioc, i)) {
2139 ioc_err(mrioc, "Cannot create OP RepQ %d\n", i);
2142 if (mpi3mr_create_op_req_q(mrioc, i,
2143 mrioc->op_reply_qinfo[i].qid)) {
2144 ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i);
2145 mpi3mr_delete_op_reply_q(mrioc, i);
2151 /* Not even one queue is created successfully*/
2155 mrioc->num_op_reply_q = mrioc->num_op_req_q = i;
2157 "successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n",
2158 mrioc->num_op_reply_q, mrioc->default_qcount,
2159 mrioc->active_poll_qcount);
2163 kfree(mrioc->req_qinfo);
2164 mrioc->req_qinfo = NULL;
2166 kfree(mrioc->op_reply_qinfo);
2167 mrioc->op_reply_qinfo = NULL;
2173 * mpi3mr_op_request_post - Post request to operational queue
2174 * @mrioc: Adapter reference
2175 * @op_req_q: Operational request queue info
2176 * @req: MPI3 request
2178 * Post the MPI3 request into operational request queue and
2179 * inform the controller, if the queue is full return
2180 * appropriate error.
2182 * Return: 0 on success, non-zero on failure.
2184 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
2185 struct op_req_qinfo *op_req_q, u8 *req)
2187 u16 pi = 0, max_entries, reply_qidx = 0, midx;
2189 unsigned long flags;
2191 void *segment_base_addr;
2192 u16 req_sz = mrioc->facts.op_req_sz;
2193 struct segments *segments = op_req_q->q_segments;
2195 reply_qidx = op_req_q->reply_qid - 1;
2197 if (mrioc->unrecoverable)
2200 spin_lock_irqsave(&op_req_q->q_lock, flags);
2202 max_entries = op_req_q->num_requests;
2204 if (mpi3mr_check_req_qfull(op_req_q)) {
2205 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(
2206 reply_qidx, mrioc->op_reply_q_offset);
2207 mpi3mr_process_op_reply_q(mrioc, mrioc->intr_info[midx].op_reply_q);
2209 if (mpi3mr_check_req_qfull(op_req_q)) {
2215 if (mrioc->reset_in_progress) {
2216 ioc_err(mrioc, "OpReqQ submit reset in progress\n");
2221 segment_base_addr = segments[pi / op_req_q->segment_qd].segment;
2222 req_entry = (u8 *)segment_base_addr +
2223 ((pi % op_req_q->segment_qd) * req_sz);
2225 memset(req_entry, 0, req_sz);
2226 memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ);
2228 if (++pi == max_entries)
2232 #ifndef CONFIG_PREEMPT_RT
2233 if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios)
2234 > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT)
2235 mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true;
2237 atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios);
2240 writel(op_req_q->pi,
2241 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index);
2244 spin_unlock_irqrestore(&op_req_q->q_lock, flags);
2249 * mpi3mr_check_rh_fault_ioc - check reset history and fault
2251 * @mrioc: Adapter instance reference
2252 * @reason_code: reason code for the fault.
2254 * This routine will save snapdump and fault the controller with
2255 * the given reason code if it is not already in the fault or
2256 * not asynchronosuly reset. This will be used to handle
2257 * initilaization time faults/resets/timeout as in those cases
2258 * immediate soft reset invocation is not required.
2262 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code)
2264 u32 ioc_status, host_diagnostic, timeout;
2266 if (mrioc->unrecoverable) {
2267 ioc_err(mrioc, "controller is unrecoverable\n");
2271 if (!pci_device_is_present(mrioc->pdev)) {
2272 mrioc->unrecoverable = 1;
2273 ioc_err(mrioc, "controller is not present\n");
2277 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2278 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
2279 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
2280 mpi3mr_print_fault_info(mrioc);
2283 mpi3mr_set_diagsave(mrioc);
2284 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2286 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
2288 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2289 if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
2292 } while (--timeout);
2296 * mpi3mr_sync_timestamp - Issue time stamp sync request
2297 * @mrioc: Adapter reference
2299 * Issue IO unit control MPI request to synchornize firmware
2300 * timestamp with host time.
2302 * Return: 0 on success, non-zero on failure.
2304 static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc)
2306 ktime_t current_time;
2307 struct mpi3_iounit_control_request iou_ctrl;
2310 memset(&iou_ctrl, 0, sizeof(iou_ctrl));
2311 mutex_lock(&mrioc->init_cmds.mutex);
2312 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2314 ioc_err(mrioc, "Issue IOUCTL time_stamp: command is in use\n");
2315 mutex_unlock(&mrioc->init_cmds.mutex);
2318 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2319 mrioc->init_cmds.is_waiting = 1;
2320 mrioc->init_cmds.callback = NULL;
2321 iou_ctrl.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2322 iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL;
2323 iou_ctrl.operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP;
2324 current_time = ktime_get_real();
2325 iou_ctrl.param64[0] = cpu_to_le64(ktime_to_ms(current_time));
2327 init_completion(&mrioc->init_cmds.done);
2328 retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl,
2329 sizeof(iou_ctrl), 0);
2331 ioc_err(mrioc, "Issue IOUCTL time_stamp: Admin Post failed\n");
2335 wait_for_completion_timeout(&mrioc->init_cmds.done,
2336 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2337 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2338 ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n");
2339 mrioc->init_cmds.is_waiting = 0;
2340 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
2341 mpi3mr_soft_reset_handler(mrioc,
2342 MPI3MR_RESET_FROM_TSU_TIMEOUT, 1);
2346 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2347 != MPI3_IOCSTATUS_SUCCESS) {
2349 "Issue IOUCTL time_stamp: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2350 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2351 mrioc->init_cmds.ioc_loginfo);
2357 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2358 mutex_unlock(&mrioc->init_cmds.mutex);
2365 * mpi3mr_print_pkg_ver - display controller fw package version
2366 * @mrioc: Adapter reference
2368 * Retrieve firmware package version from the component image
2369 * header of the controller flash and display it.
2371 * Return: 0 on success and non-zero on failure.
2373 static int mpi3mr_print_pkg_ver(struct mpi3mr_ioc *mrioc)
2375 struct mpi3_ci_upload_request ci_upload;
2378 dma_addr_t data_dma;
2379 struct mpi3_ci_manifest_mpi *manifest;
2380 u32 data_len = sizeof(struct mpi3_ci_manifest_mpi);
2381 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2383 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2388 memset(&ci_upload, 0, sizeof(ci_upload));
2389 mutex_lock(&mrioc->init_cmds.mutex);
2390 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2391 ioc_err(mrioc, "sending get package version failed due to command in use\n");
2392 mutex_unlock(&mrioc->init_cmds.mutex);
2395 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2396 mrioc->init_cmds.is_waiting = 1;
2397 mrioc->init_cmds.callback = NULL;
2398 ci_upload.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2399 ci_upload.function = MPI3_FUNCTION_CI_UPLOAD;
2400 ci_upload.msg_flags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY;
2401 ci_upload.signature1 = cpu_to_le32(MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST);
2402 ci_upload.image_offset = cpu_to_le32(MPI3_IMAGE_HEADER_SIZE);
2403 ci_upload.segment_size = cpu_to_le32(data_len);
2405 mpi3mr_add_sg_single(&ci_upload.sgl, sgl_flags, data_len,
2407 init_completion(&mrioc->init_cmds.done);
2408 retval = mpi3mr_admin_request_post(mrioc, &ci_upload,
2409 sizeof(ci_upload), 1);
2411 ioc_err(mrioc, "posting get package version failed\n");
2414 wait_for_completion_timeout(&mrioc->init_cmds.done,
2415 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2416 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2417 ioc_err(mrioc, "get package version timed out\n");
2418 mpi3mr_check_rh_fault_ioc(mrioc,
2419 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT);
2423 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2424 == MPI3_IOCSTATUS_SUCCESS) {
2425 manifest = (struct mpi3_ci_manifest_mpi *) data;
2426 if (manifest->manifest_type == MPI3_CI_MANIFEST_TYPE_MPI) {
2428 "firmware package version(%d.%d.%d.%d.%05d-%05d)\n",
2429 manifest->package_version.gen_major,
2430 manifest->package_version.gen_minor,
2431 manifest->package_version.phase_major,
2432 manifest->package_version.phase_minor,
2433 manifest->package_version.customer_id,
2434 manifest->package_version.build_num);
2439 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2440 mutex_unlock(&mrioc->init_cmds.mutex);
2444 dma_free_coherent(&mrioc->pdev->dev, data_len, data,
2450 * mpi3mr_watchdog_work - watchdog thread to monitor faults
2451 * @work: work struct
2453 * Watch dog work periodically executed (1 second interval) to
2454 * monitor firmware fault and to issue periodic timer sync to
2459 static void mpi3mr_watchdog_work(struct work_struct *work)
2461 struct mpi3mr_ioc *mrioc =
2462 container_of(work, struct mpi3mr_ioc, watchdog_work.work);
2463 unsigned long flags;
2464 enum mpi3mr_iocstate ioc_state;
2465 u32 fault, host_diagnostic, ioc_status;
2466 u32 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH;
2468 if (mrioc->reset_in_progress)
2471 if (!mrioc->unrecoverable && !pci_device_is_present(mrioc->pdev)) {
2472 ioc_err(mrioc, "watchdog could not detect the controller\n");
2473 mrioc->unrecoverable = 1;
2476 if (mrioc->unrecoverable) {
2478 "flush pending commands for unrecoverable controller\n");
2479 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
2483 if (mrioc->ts_update_counter++ >= MPI3MR_TSUPDATE_INTERVAL) {
2484 mrioc->ts_update_counter = 0;
2485 mpi3mr_sync_timestamp(mrioc);
2488 if ((mrioc->prepare_for_reset) &&
2489 ((mrioc->prepare_for_reset_timeout_counter++) >=
2490 MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) {
2491 mpi3mr_soft_reset_handler(mrioc,
2492 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1);
2496 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2497 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {
2498 mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_FIRMWARE, 0);
2502 /*Check for fault state every one second and issue Soft reset*/
2503 ioc_state = mpi3mr_get_iocstate(mrioc);
2504 if (ioc_state != MRIOC_STATE_FAULT)
2507 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
2508 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2509 if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) {
2510 if (!mrioc->diagsave_timeout) {
2511 mpi3mr_print_fault_info(mrioc);
2512 ioc_warn(mrioc, "diag save in progress\n");
2514 if ((mrioc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT)
2518 mpi3mr_print_fault_info(mrioc);
2519 mrioc->diagsave_timeout = 0;
2522 case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED:
2523 case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED:
2525 "controller requires system power cycle, marking controller as unrecoverable\n");
2526 mrioc->unrecoverable = 1;
2528 case MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS:
2530 case MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET:
2531 reset_reason = MPI3MR_RESET_FROM_CIACTIV_FAULT;
2536 mpi3mr_soft_reset_handler(mrioc, reset_reason, 0);
2540 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2541 if (mrioc->watchdog_work_q)
2542 queue_delayed_work(mrioc->watchdog_work_q,
2543 &mrioc->watchdog_work,
2544 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2545 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2550 * mpi3mr_start_watchdog - Start watchdog
2551 * @mrioc: Adapter instance reference
2553 * Create and start the watchdog thread to monitor controller
2558 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc)
2560 if (mrioc->watchdog_work_q)
2563 INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work);
2564 snprintf(mrioc->watchdog_work_q_name,
2565 sizeof(mrioc->watchdog_work_q_name), "watchdog_%s%d", mrioc->name,
2567 mrioc->watchdog_work_q =
2568 create_singlethread_workqueue(mrioc->watchdog_work_q_name);
2569 if (!mrioc->watchdog_work_q) {
2570 ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__);
2574 if (mrioc->watchdog_work_q)
2575 queue_delayed_work(mrioc->watchdog_work_q,
2576 &mrioc->watchdog_work,
2577 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2581 * mpi3mr_stop_watchdog - Stop watchdog
2582 * @mrioc: Adapter instance reference
2584 * Stop the watchdog thread created to monitor controller
2589 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc)
2591 unsigned long flags;
2592 struct workqueue_struct *wq;
2594 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2595 wq = mrioc->watchdog_work_q;
2596 mrioc->watchdog_work_q = NULL;
2597 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2599 if (!cancel_delayed_work_sync(&mrioc->watchdog_work))
2600 flush_workqueue(wq);
2601 destroy_workqueue(wq);
2606 * mpi3mr_setup_admin_qpair - Setup admin queue pair
2607 * @mrioc: Adapter instance reference
2609 * Allocate memory for admin queue pair if required and register
2610 * the admin queue with the controller.
2612 * Return: 0 on success, non-zero on failures.
2614 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc)
2617 u32 num_admin_entries = 0;
2619 mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE;
2620 mrioc->num_admin_req = mrioc->admin_req_q_sz /
2621 MPI3MR_ADMIN_REQ_FRAME_SZ;
2622 mrioc->admin_req_ci = mrioc->admin_req_pi = 0;
2624 mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE;
2625 mrioc->num_admin_replies = mrioc->admin_reply_q_sz /
2626 MPI3MR_ADMIN_REPLY_FRAME_SZ;
2627 mrioc->admin_reply_ci = 0;
2628 mrioc->admin_reply_ephase = 1;
2629 atomic_set(&mrioc->admin_reply_q_in_use, 0);
2631 if (!mrioc->admin_req_base) {
2632 mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev,
2633 mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL);
2635 if (!mrioc->admin_req_base) {
2640 mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev,
2641 mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma,
2644 if (!mrioc->admin_reply_base) {
2650 num_admin_entries = (mrioc->num_admin_replies << 16) |
2651 (mrioc->num_admin_req);
2652 writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries);
2653 mpi3mr_writeq(mrioc->admin_req_dma,
2654 &mrioc->sysif_regs->admin_request_queue_address);
2655 mpi3mr_writeq(mrioc->admin_reply_dma,
2656 &mrioc->sysif_regs->admin_reply_queue_address);
2657 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
2658 writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
2663 if (mrioc->admin_reply_base) {
2664 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
2665 mrioc->admin_reply_base, mrioc->admin_reply_dma);
2666 mrioc->admin_reply_base = NULL;
2668 if (mrioc->admin_req_base) {
2669 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
2670 mrioc->admin_req_base, mrioc->admin_req_dma);
2671 mrioc->admin_req_base = NULL;
2677 * mpi3mr_issue_iocfacts - Send IOC Facts
2678 * @mrioc: Adapter instance reference
2679 * @facts_data: Cached IOC facts data
2681 * Issue IOC Facts MPI request through admin queue and wait for
2682 * the completion of it or time out.
2684 * Return: 0 on success, non-zero on failures.
2686 static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc,
2687 struct mpi3_ioc_facts_data *facts_data)
2689 struct mpi3_ioc_facts_request iocfacts_req;
2691 dma_addr_t data_dma;
2692 u32 data_len = sizeof(*facts_data);
2694 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2696 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2704 memset(&iocfacts_req, 0, sizeof(iocfacts_req));
2705 mutex_lock(&mrioc->init_cmds.mutex);
2706 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2708 ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n");
2709 mutex_unlock(&mrioc->init_cmds.mutex);
2712 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2713 mrioc->init_cmds.is_waiting = 1;
2714 mrioc->init_cmds.callback = NULL;
2715 iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2716 iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS;
2718 mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len,
2721 init_completion(&mrioc->init_cmds.done);
2722 retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req,
2723 sizeof(iocfacts_req), 1);
2725 ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n");
2728 wait_for_completion_timeout(&mrioc->init_cmds.done,
2729 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2730 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2731 ioc_err(mrioc, "ioc_facts timed out\n");
2732 mpi3mr_check_rh_fault_ioc(mrioc,
2733 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT);
2737 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2738 != MPI3_IOCSTATUS_SUCCESS) {
2740 "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2741 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2742 mrioc->init_cmds.ioc_loginfo);
2746 memcpy(facts_data, (u8 *)data, data_len);
2747 mpi3mr_process_factsdata(mrioc, facts_data);
2749 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2750 mutex_unlock(&mrioc->init_cmds.mutex);
2754 dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma);
2760 * mpi3mr_check_reset_dma_mask - Process IOC facts data
2761 * @mrioc: Adapter instance reference
2763 * Check whether the new DMA mask requested through IOCFacts by
2764 * firmware needs to be set, if so set it .
2766 * Return: 0 on success, non-zero on failure.
2768 static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc)
2770 struct pci_dev *pdev = mrioc->pdev;
2772 u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask);
2774 if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask))
2777 ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n",
2778 mrioc->dma_mask, facts_dma_mask);
2780 r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask);
2782 ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n",
2786 mrioc->dma_mask = facts_dma_mask;
2791 * mpi3mr_process_factsdata - Process IOC facts data
2792 * @mrioc: Adapter instance reference
2793 * @facts_data: Cached IOC facts data
2795 * Convert IOC facts data into cpu endianness and cache it in
2800 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
2801 struct mpi3_ioc_facts_data *facts_data)
2803 u32 ioc_config, req_sz, facts_flags;
2805 if ((le16_to_cpu(facts_data->ioc_facts_data_length)) !=
2806 (sizeof(*facts_data) / 4)) {
2808 "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n",
2809 sizeof(*facts_data),
2810 le16_to_cpu(facts_data->ioc_facts_data_length) * 4);
2813 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
2814 req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >>
2815 MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT);
2816 if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) {
2818 "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n",
2819 req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size));
2822 memset(&mrioc->facts, 0, sizeof(mrioc->facts));
2824 facts_flags = le32_to_cpu(facts_data->flags);
2825 mrioc->facts.op_req_sz = req_sz;
2826 mrioc->op_reply_desc_sz = 1 << ((ioc_config &
2827 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >>
2828 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT);
2830 mrioc->facts.ioc_num = facts_data->ioc_number;
2831 mrioc->facts.who_init = facts_data->who_init;
2832 mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors);
2833 mrioc->facts.personality = (facts_flags &
2834 MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK);
2835 mrioc->facts.dma_mask = (facts_flags &
2836 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >>
2837 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT;
2838 mrioc->facts.protocol_flags = facts_data->protocol_flags;
2839 mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word);
2840 mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_requests);
2841 mrioc->facts.product_id = le16_to_cpu(facts_data->product_id);
2842 mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4;
2843 mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions);
2844 mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id);
2845 mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds);
2846 mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds);
2847 mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds);
2848 mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds);
2849 mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme);
2850 mrioc->facts.max_pcie_switches =
2851 le16_to_cpu(facts_data->max_pcie_switches);
2852 mrioc->facts.max_sasexpanders =
2853 le16_to_cpu(facts_data->max_sas_expanders);
2854 mrioc->facts.max_sasinitiators =
2855 le16_to_cpu(facts_data->max_sas_initiators);
2856 mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures);
2857 mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle);
2858 mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle);
2859 mrioc->facts.max_op_req_q =
2860 le16_to_cpu(facts_data->max_operational_request_queues);
2861 mrioc->facts.max_op_reply_q =
2862 le16_to_cpu(facts_data->max_operational_reply_queues);
2863 mrioc->facts.ioc_capabilities =
2864 le32_to_cpu(facts_data->ioc_capabilities);
2865 mrioc->facts.fw_ver.build_num =
2866 le16_to_cpu(facts_data->fw_version.build_num);
2867 mrioc->facts.fw_ver.cust_id =
2868 le16_to_cpu(facts_data->fw_version.customer_id);
2869 mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor;
2870 mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major;
2871 mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor;
2872 mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major;
2873 mrioc->msix_count = min_t(int, mrioc->msix_count,
2874 mrioc->facts.max_msix_vectors);
2875 mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask;
2876 mrioc->facts.sge_mod_value = facts_data->sge_modifier_value;
2877 mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift;
2878 mrioc->facts.shutdown_timeout =
2879 le16_to_cpu(facts_data->shutdown_timeout);
2881 mrioc->facts.max_dev_per_tg =
2882 facts_data->max_devices_per_throttle_group;
2883 mrioc->facts.io_throttle_data_length =
2884 le16_to_cpu(facts_data->io_throttle_data_length);
2885 mrioc->facts.max_io_throttle_group =
2886 le16_to_cpu(facts_data->max_io_throttle_group);
2887 mrioc->facts.io_throttle_low = le16_to_cpu(facts_data->io_throttle_low);
2888 mrioc->facts.io_throttle_high =
2889 le16_to_cpu(facts_data->io_throttle_high);
2891 /* Store in 512b block count */
2892 if (mrioc->facts.io_throttle_data_length)
2893 mrioc->io_throttle_data_length =
2894 (mrioc->facts.io_throttle_data_length * 2 * 4);
2896 /* set the length to 1MB + 1K to disable throttle */
2897 mrioc->io_throttle_data_length = MPI3MR_MAX_SECTORS + 2;
2899 mrioc->io_throttle_high = (mrioc->facts.io_throttle_high * 2 * 1024);
2900 mrioc->io_throttle_low = (mrioc->facts.io_throttle_low * 2 * 1024);
2902 ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),",
2903 mrioc->facts.ioc_num, mrioc->facts.max_op_req_q,
2904 mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle);
2906 "maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n",
2907 mrioc->facts.max_reqs, mrioc->facts.min_devhandle,
2908 mrioc->facts.max_msix_vectors, mrioc->facts.max_perids);
2909 ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ",
2910 mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value,
2911 mrioc->facts.sge_mod_shift);
2912 ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x\n",
2913 mrioc->facts.dma_mask, (facts_flags &
2914 MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK));
2916 "max_dev_per_throttle_group(%d), max_throttle_groups(%d)\n",
2917 mrioc->facts.max_dev_per_tg, mrioc->facts.max_io_throttle_group);
2919 "io_throttle_data_len(%dKiB), io_throttle_high(%dMiB), io_throttle_low(%dMiB)\n",
2920 mrioc->facts.io_throttle_data_length * 4,
2921 mrioc->facts.io_throttle_high, mrioc->facts.io_throttle_low);
2925 * mpi3mr_alloc_reply_sense_bufs - Send IOC Init
2926 * @mrioc: Adapter instance reference
2928 * Allocate and initialize the reply free buffers, sense
2929 * buffers, reply free queue and sense buffer queue.
2931 * Return: 0 on success, non-zero on failures.
2933 static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc)
2938 if (mrioc->init_cmds.reply)
2941 mrioc->init_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2942 if (!mrioc->init_cmds.reply)
2945 mrioc->bsg_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2946 if (!mrioc->bsg_cmds.reply)
2949 mrioc->transport_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2950 if (!mrioc->transport_cmds.reply)
2953 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
2954 mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->reply_sz,
2956 if (!mrioc->dev_rmhs_cmds[i].reply)
2960 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
2961 mrioc->evtack_cmds[i].reply = kzalloc(mrioc->reply_sz,
2963 if (!mrioc->evtack_cmds[i].reply)
2967 mrioc->host_tm_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2968 if (!mrioc->host_tm_cmds.reply)
2971 mrioc->pel_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2972 if (!mrioc->pel_cmds.reply)
2975 mrioc->pel_abort_cmd.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2976 if (!mrioc->pel_abort_cmd.reply)
2979 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
2980 mrioc->removepend_bitmap = bitmap_zalloc(mrioc->dev_handle_bitmap_bits,
2982 if (!mrioc->removepend_bitmap)
2985 mrioc->devrem_bitmap = bitmap_zalloc(MPI3MR_NUM_DEVRMCMD, GFP_KERNEL);
2986 if (!mrioc->devrem_bitmap)
2989 mrioc->evtack_cmds_bitmap = bitmap_zalloc(MPI3MR_NUM_EVTACKCMD,
2991 if (!mrioc->evtack_cmds_bitmap)
2994 mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES;
2995 mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1;
2996 mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR;
2997 mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1;
2999 /* reply buffer pool, 16 byte align */
3000 sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3001 mrioc->reply_buf_pool = dma_pool_create("reply_buf pool",
3002 &mrioc->pdev->dev, sz, 16, 0);
3003 if (!mrioc->reply_buf_pool) {
3004 ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n");
3008 mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL,
3009 &mrioc->reply_buf_dma);
3010 if (!mrioc->reply_buf)
3013 mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz;
3015 /* reply free queue, 8 byte align */
3016 sz = mrioc->reply_free_qsz * 8;
3017 mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool",
3018 &mrioc->pdev->dev, sz, 8, 0);
3019 if (!mrioc->reply_free_q_pool) {
3020 ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n");
3023 mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool,
3024 GFP_KERNEL, &mrioc->reply_free_q_dma);
3025 if (!mrioc->reply_free_q)
3028 /* sense buffer pool, 4 byte align */
3029 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3030 mrioc->sense_buf_pool = dma_pool_create("sense_buf pool",
3031 &mrioc->pdev->dev, sz, 4, 0);
3032 if (!mrioc->sense_buf_pool) {
3033 ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n");
3036 mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL,
3037 &mrioc->sense_buf_dma);
3038 if (!mrioc->sense_buf)
3041 /* sense buffer queue, 8 byte align */
3042 sz = mrioc->sense_buf_q_sz * 8;
3043 mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool",
3044 &mrioc->pdev->dev, sz, 8, 0);
3045 if (!mrioc->sense_buf_q_pool) {
3046 ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n");
3049 mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool,
3050 GFP_KERNEL, &mrioc->sense_buf_q_dma);
3051 if (!mrioc->sense_buf_q)
3062 * mpimr_initialize_reply_sbuf_queues - initialize reply sense
3064 * @mrioc: Adapter instance reference
3066 * Helper function to initialize reply and sense buffers along
3067 * with some debug prints.
3071 static void mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc *mrioc)
3074 dma_addr_t phy_addr;
3076 sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3078 "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3079 mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->reply_sz,
3080 (sz / 1024), (unsigned long long)mrioc->reply_buf_dma);
3081 sz = mrioc->reply_free_qsz * 8;
3083 "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3084 mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024),
3085 (unsigned long long)mrioc->reply_free_q_dma);
3086 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3088 "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3089 mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ,
3090 (sz / 1024), (unsigned long long)mrioc->sense_buf_dma);
3091 sz = mrioc->sense_buf_q_sz * 8;
3093 "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3094 mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024),
3095 (unsigned long long)mrioc->sense_buf_q_dma);
3097 /* initialize Reply buffer Queue */
3098 for (i = 0, phy_addr = mrioc->reply_buf_dma;
3099 i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->reply_sz)
3100 mrioc->reply_free_q[i] = cpu_to_le64(phy_addr);
3101 mrioc->reply_free_q[i] = cpu_to_le64(0);
3103 /* initialize Sense Buffer Queue */
3104 for (i = 0, phy_addr = mrioc->sense_buf_dma;
3105 i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ)
3106 mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr);
3107 mrioc->sense_buf_q[i] = cpu_to_le64(0);
3111 * mpi3mr_issue_iocinit - Send IOC Init
3112 * @mrioc: Adapter instance reference
3114 * Issue IOC Init MPI request through admin queue and wait for
3115 * the completion of it or time out.
3117 * Return: 0 on success, non-zero on failures.
3119 static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc)
3121 struct mpi3_ioc_init_request iocinit_req;
3122 struct mpi3_driver_info_layout *drv_info;
3123 dma_addr_t data_dma;
3124 u32 data_len = sizeof(*drv_info);
3126 ktime_t current_time;
3128 drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
3134 mpimr_initialize_reply_sbuf_queues(mrioc);
3136 drv_info->information_length = cpu_to_le32(data_len);
3137 strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature));
3138 strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name));
3139 strscpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version));
3140 strscpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name));
3141 strscpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version));
3142 strscpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE,
3143 sizeof(drv_info->driver_release_date));
3144 drv_info->driver_capabilities = 0;
3145 memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info,
3146 sizeof(mrioc->driver_info));
3148 memset(&iocinit_req, 0, sizeof(iocinit_req));
3149 mutex_lock(&mrioc->init_cmds.mutex);
3150 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3152 ioc_err(mrioc, "Issue IOCInit: Init command is in use\n");
3153 mutex_unlock(&mrioc->init_cmds.mutex);
3156 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3157 mrioc->init_cmds.is_waiting = 1;
3158 mrioc->init_cmds.callback = NULL;
3159 iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3160 iocinit_req.function = MPI3_FUNCTION_IOC_INIT;
3161 iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV;
3162 iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT;
3163 iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR;
3164 iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR;
3165 iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER;
3166 iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz);
3167 iocinit_req.reply_free_queue_address =
3168 cpu_to_le64(mrioc->reply_free_q_dma);
3169 iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ);
3170 iocinit_req.sense_buffer_free_queue_depth =
3171 cpu_to_le16(mrioc->sense_buf_q_sz);
3172 iocinit_req.sense_buffer_free_queue_address =
3173 cpu_to_le64(mrioc->sense_buf_q_dma);
3174 iocinit_req.driver_information_address = cpu_to_le64(data_dma);
3176 current_time = ktime_get_real();
3177 iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time));
3179 init_completion(&mrioc->init_cmds.done);
3180 retval = mpi3mr_admin_request_post(mrioc, &iocinit_req,
3181 sizeof(iocinit_req), 1);
3183 ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n");
3186 wait_for_completion_timeout(&mrioc->init_cmds.done,
3187 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3188 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3189 mpi3mr_check_rh_fault_ioc(mrioc,
3190 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT);
3191 ioc_err(mrioc, "ioc_init timed out\n");
3195 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3196 != MPI3_IOCSTATUS_SUCCESS) {
3198 "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3199 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3200 mrioc->init_cmds.ioc_loginfo);
3205 mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs;
3206 writel(mrioc->reply_free_queue_host_index,
3207 &mrioc->sysif_regs->reply_free_host_index);
3209 mrioc->sbq_host_index = mrioc->num_sense_bufs;
3210 writel(mrioc->sbq_host_index,
3211 &mrioc->sysif_regs->sense_buffer_free_host_index);
3213 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3214 mutex_unlock(&mrioc->init_cmds.mutex);
3218 dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info,
3225 * mpi3mr_unmask_events - Unmask events in event mask bitmap
3226 * @mrioc: Adapter instance reference
3227 * @event: MPI event ID
3229 * Un mask the specific event by resetting the event_mask
3232 * Return: 0 on success, non-zero on failures.
3234 static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event)
3242 desired_event = (1 << (event % 32));
3245 mrioc->event_masks[word] &= ~desired_event;
3249 * mpi3mr_issue_event_notification - Send event notification
3250 * @mrioc: Adapter instance reference
3252 * Issue event notification MPI request through admin queue and
3253 * wait for the completion of it or time out.
3255 * Return: 0 on success, non-zero on failures.
3257 static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc)
3259 struct mpi3_event_notification_request evtnotify_req;
3263 memset(&evtnotify_req, 0, sizeof(evtnotify_req));
3264 mutex_lock(&mrioc->init_cmds.mutex);
3265 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3267 ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n");
3268 mutex_unlock(&mrioc->init_cmds.mutex);
3271 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3272 mrioc->init_cmds.is_waiting = 1;
3273 mrioc->init_cmds.callback = NULL;
3274 evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3275 evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION;
3276 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3277 evtnotify_req.event_masks[i] =
3278 cpu_to_le32(mrioc->event_masks[i]);
3279 init_completion(&mrioc->init_cmds.done);
3280 retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req,
3281 sizeof(evtnotify_req), 1);
3283 ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n");
3286 wait_for_completion_timeout(&mrioc->init_cmds.done,
3287 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3288 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3289 ioc_err(mrioc, "event notification timed out\n");
3290 mpi3mr_check_rh_fault_ioc(mrioc,
3291 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT);
3295 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3296 != MPI3_IOCSTATUS_SUCCESS) {
3298 "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3299 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3300 mrioc->init_cmds.ioc_loginfo);
3306 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3307 mutex_unlock(&mrioc->init_cmds.mutex);
3313 * mpi3mr_process_event_ack - Process event acknowledgment
3314 * @mrioc: Adapter instance reference
3315 * @event: MPI3 event ID
3316 * @event_ctx: event context
3318 * Send event acknowledgment through admin queue and wait for
3321 * Return: 0 on success, non-zero on failures.
3323 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
3326 struct mpi3_event_ack_request evtack_req;
3329 memset(&evtack_req, 0, sizeof(evtack_req));
3330 mutex_lock(&mrioc->init_cmds.mutex);
3331 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3333 ioc_err(mrioc, "Send EvtAck: Init command is in use\n");
3334 mutex_unlock(&mrioc->init_cmds.mutex);
3337 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3338 mrioc->init_cmds.is_waiting = 1;
3339 mrioc->init_cmds.callback = NULL;
3340 evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3341 evtack_req.function = MPI3_FUNCTION_EVENT_ACK;
3342 evtack_req.event = event;
3343 evtack_req.event_context = cpu_to_le32(event_ctx);
3345 init_completion(&mrioc->init_cmds.done);
3346 retval = mpi3mr_admin_request_post(mrioc, &evtack_req,
3347 sizeof(evtack_req), 1);
3349 ioc_err(mrioc, "Send EvtAck: Admin Post failed\n");
3352 wait_for_completion_timeout(&mrioc->init_cmds.done,
3353 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3354 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3355 ioc_err(mrioc, "Issue EvtNotify: command timed out\n");
3356 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
3357 mpi3mr_soft_reset_handler(mrioc,
3358 MPI3MR_RESET_FROM_EVTACK_TIMEOUT, 1);
3362 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3363 != MPI3_IOCSTATUS_SUCCESS) {
3365 "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3366 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3367 mrioc->init_cmds.ioc_loginfo);
3373 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3374 mutex_unlock(&mrioc->init_cmds.mutex);
3380 * mpi3mr_alloc_chain_bufs - Allocate chain buffers
3381 * @mrioc: Adapter instance reference
3383 * Allocate chain buffers and set a bitmap to indicate free
3384 * chain buffers. Chain buffers are used to pass the SGE
3385 * information along with MPI3 SCSI IO requests for host I/O.
3387 * Return: 0 on success, non-zero on failure
3389 static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc)
3395 if (mrioc->chain_sgl_list)
3398 num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR;
3400 if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION
3401 | SHOST_DIX_TYPE1_PROTECTION
3402 | SHOST_DIX_TYPE2_PROTECTION
3403 | SHOST_DIX_TYPE3_PROTECTION))
3404 num_chains += (num_chains / MPI3MR_CHAINBUFDIX_FACTOR);
3406 mrioc->chain_buf_count = num_chains;
3407 sz = sizeof(struct chain_element) * num_chains;
3408 mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL);
3409 if (!mrioc->chain_sgl_list)
3412 sz = MPI3MR_PAGE_SIZE_4K;
3413 mrioc->chain_buf_pool = dma_pool_create("chain_buf pool",
3414 &mrioc->pdev->dev, sz, 16, 0);
3415 if (!mrioc->chain_buf_pool) {
3416 ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n");
3420 for (i = 0; i < num_chains; i++) {
3421 mrioc->chain_sgl_list[i].addr =
3422 dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL,
3423 &mrioc->chain_sgl_list[i].dma_addr);
3425 if (!mrioc->chain_sgl_list[i].addr)
3428 mrioc->chain_bitmap = bitmap_zalloc(num_chains, GFP_KERNEL);
3429 if (!mrioc->chain_bitmap)
3438 * mpi3mr_port_enable_complete - Mark port enable complete
3439 * @mrioc: Adapter instance reference
3440 * @drv_cmd: Internal command tracker
3442 * Call back for asynchronous port enable request sets the
3443 * driver command to indicate port enable request is complete.
3447 static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc,
3448 struct mpi3mr_drv_cmd *drv_cmd)
3450 drv_cmd->callback = NULL;
3451 mrioc->scan_started = 0;
3452 if (drv_cmd->state & MPI3MR_CMD_RESET)
3453 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR;
3455 mrioc->scan_failed = drv_cmd->ioc_status;
3456 drv_cmd->state = MPI3MR_CMD_NOTUSED;
3460 * mpi3mr_issue_port_enable - Issue Port Enable
3461 * @mrioc: Adapter instance reference
3462 * @async: Flag to wait for completion or not
3464 * Issue Port Enable MPI request through admin queue and if the
3465 * async flag is not set wait for the completion of the port
3466 * enable or time out.
3468 * Return: 0 on success, non-zero on failures.
3470 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async)
3472 struct mpi3_port_enable_request pe_req;
3474 u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT;
3476 memset(&pe_req, 0, sizeof(pe_req));
3477 mutex_lock(&mrioc->init_cmds.mutex);
3478 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3480 ioc_err(mrioc, "Issue PortEnable: Init command is in use\n");
3481 mutex_unlock(&mrioc->init_cmds.mutex);
3484 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3486 mrioc->init_cmds.is_waiting = 0;
3487 mrioc->init_cmds.callback = mpi3mr_port_enable_complete;
3489 mrioc->init_cmds.is_waiting = 1;
3490 mrioc->init_cmds.callback = NULL;
3491 init_completion(&mrioc->init_cmds.done);
3493 pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3494 pe_req.function = MPI3_FUNCTION_PORT_ENABLE;
3496 retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1);
3498 ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n");
3502 mutex_unlock(&mrioc->init_cmds.mutex);
3506 wait_for_completion_timeout(&mrioc->init_cmds.done, (pe_timeout * HZ));
3507 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3508 ioc_err(mrioc, "port enable timed out\n");
3510 mpi3mr_check_rh_fault_ioc(mrioc, MPI3MR_RESET_FROM_PE_TIMEOUT);
3513 mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds);
3516 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3517 mutex_unlock(&mrioc->init_cmds.mutex);
3522 /* Protocol type to name mapper structure */
3523 static const struct {
3526 } mpi3mr_protocols[] = {
3527 { MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR, "Initiator" },
3528 { MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET, "Target" },
3529 { MPI3_IOCFACTS_PROTOCOL_NVME, "NVMe attachment" },
3532 /* Capability to name mapper structure*/
3533 static const struct {
3536 } mpi3mr_capabilities[] = {
3537 { MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE, "RAID" },
3538 { MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED, "MultiPath" },
3542 * mpi3mr_print_ioc_info - Display controller information
3543 * @mrioc: Adapter instance reference
3545 * Display controller personalit, capability, supported
3551 mpi3mr_print_ioc_info(struct mpi3mr_ioc *mrioc)
3553 int i = 0, bytes_written = 0;
3554 char personality[16];
3555 char protocol[50] = {0};
3556 char capabilities[100] = {0};
3557 struct mpi3mr_compimg_ver *fwver = &mrioc->facts.fw_ver;
3559 switch (mrioc->facts.personality) {
3560 case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA:
3561 strncpy(personality, "Enhanced HBA", sizeof(personality));
3563 case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR:
3564 strncpy(personality, "RAID", sizeof(personality));
3567 strncpy(personality, "Unknown", sizeof(personality));
3571 ioc_info(mrioc, "Running in %s Personality", personality);
3573 ioc_info(mrioc, "FW version(%d.%d.%d.%d.%d.%d)\n",
3574 fwver->gen_major, fwver->gen_minor, fwver->ph_major,
3575 fwver->ph_minor, fwver->cust_id, fwver->build_num);
3577 for (i = 0; i < ARRAY_SIZE(mpi3mr_protocols); i++) {
3578 if (mrioc->facts.protocol_flags &
3579 mpi3mr_protocols[i].protocol) {
3580 bytes_written += scnprintf(protocol + bytes_written,
3581 sizeof(protocol) - bytes_written, "%s%s",
3582 bytes_written ? "," : "",
3583 mpi3mr_protocols[i].name);
3588 for (i = 0; i < ARRAY_SIZE(mpi3mr_capabilities); i++) {
3589 if (mrioc->facts.protocol_flags &
3590 mpi3mr_capabilities[i].capability) {
3591 bytes_written += scnprintf(capabilities + bytes_written,
3592 sizeof(capabilities) - bytes_written, "%s%s",
3593 bytes_written ? "," : "",
3594 mpi3mr_capabilities[i].name);
3598 ioc_info(mrioc, "Protocol=(%s), Capabilities=(%s)\n",
3599 protocol, capabilities);
3603 * mpi3mr_cleanup_resources - Free PCI resources
3604 * @mrioc: Adapter instance reference
3606 * Unmap PCI device memory and disable PCI device.
3608 * Return: 0 on success and non-zero on failure.
3610 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc)
3612 struct pci_dev *pdev = mrioc->pdev;
3614 mpi3mr_cleanup_isr(mrioc);
3616 if (mrioc->sysif_regs) {
3617 iounmap((void __iomem *)mrioc->sysif_regs);
3618 mrioc->sysif_regs = NULL;
3621 if (pci_is_enabled(pdev)) {
3623 pci_release_selected_regions(pdev, mrioc->bars);
3624 pci_disable_device(pdev);
3629 * mpi3mr_setup_resources - Enable PCI resources
3630 * @mrioc: Adapter instance reference
3632 * Enable PCI device memory, MSI-x registers and set DMA mask.
3634 * Return: 0 on success and non-zero on failure.
3636 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc)
3638 struct pci_dev *pdev = mrioc->pdev;
3640 int i, retval = 0, capb = 0;
3641 u16 message_control;
3642 u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask :
3643 ((sizeof(dma_addr_t) > 4) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32));
3645 if (pci_enable_device_mem(pdev)) {
3646 ioc_err(mrioc, "pci_enable_device_mem: failed\n");
3651 capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3653 ioc_err(mrioc, "Unable to find MSI-X Capabilities\n");
3657 mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
3659 if (pci_request_selected_regions(pdev, mrioc->bars,
3660 mrioc->driver_name)) {
3661 ioc_err(mrioc, "pci_request_selected_regions: failed\n");
3666 for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) {
3667 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3668 mrioc->sysif_regs_phys = pci_resource_start(pdev, i);
3669 memap_sz = pci_resource_len(pdev, i);
3671 ioremap(mrioc->sysif_regs_phys, memap_sz);
3676 pci_set_master(pdev);
3678 retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask);
3680 if (dma_mask != DMA_BIT_MASK(32)) {
3681 ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n");
3682 dma_mask = DMA_BIT_MASK(32);
3683 retval = dma_set_mask_and_coherent(&pdev->dev,
3687 mrioc->dma_mask = 0;
3688 ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n");
3692 mrioc->dma_mask = dma_mask;
3694 if (!mrioc->sysif_regs) {
3696 "Unable to map adapter memory or resource not found\n");
3701 pci_read_config_word(pdev, capb + 2, &message_control);
3702 mrioc->msix_count = (message_control & 0x3FF) + 1;
3704 pci_save_state(pdev);
3706 pci_set_drvdata(pdev, mrioc->shost);
3708 mpi3mr_ioc_disable_intr(mrioc);
3710 ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
3711 (unsigned long long)mrioc->sysif_regs_phys,
3712 mrioc->sysif_regs, memap_sz);
3713 ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n",
3716 if (!reset_devices && poll_queues > 0)
3717 mrioc->requested_poll_qcount = min_t(int, poll_queues,
3718 mrioc->msix_count - 2);
3722 mpi3mr_cleanup_resources(mrioc);
3727 * mpi3mr_enable_events - Enable required events
3728 * @mrioc: Adapter instance reference
3730 * This routine unmasks the events required by the driver by
3731 * sennding appropriate event mask bitmapt through an event
3732 * notification request.
3734 * Return: 0 on success and non-zero on failure.
3736 static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc)
3741 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3742 mrioc->event_masks[i] = -1;
3744 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED);
3745 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED);
3746 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE);
3747 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE);
3748 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_ADDED);
3749 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
3750 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY);
3751 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
3752 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE);
3753 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
3754 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION);
3755 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PREPARE_FOR_RESET);
3756 mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT);
3757 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE);
3759 retval = mpi3mr_issue_event_notification(mrioc);
3761 ioc_err(mrioc, "failed to issue event notification %d\n",
3767 * mpi3mr_init_ioc - Initialize the controller
3768 * @mrioc: Adapter instance reference
3770 * This the controller initialization routine, executed either
3771 * after soft reset or from pci probe callback.
3772 * Setup the required resources, memory map the controller
3773 * registers, create admin and operational reply queue pairs,
3774 * allocate required memory for reply pool, sense buffer pool,
3775 * issue IOC init request to the firmware, unmask the events and
3776 * issue port enable to discover SAS/SATA/NVMe devies and RAID
3779 * Return: 0 on success and non-zero on failure.
3781 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc)
3785 struct mpi3_ioc_facts_data facts_data;
3789 retval = mpi3mr_bring_ioc_ready(mrioc);
3791 ioc_err(mrioc, "Failed to bring ioc ready: error %d\n",
3793 goto out_failed_noretry;
3796 retval = mpi3mr_setup_isr(mrioc, 1);
3798 ioc_err(mrioc, "Failed to setup ISR error %d\n",
3800 goto out_failed_noretry;
3803 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
3805 ioc_err(mrioc, "Failed to Issue IOC Facts %d\n",
3810 mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD;
3812 mrioc->num_io_throttle_group = mrioc->facts.max_io_throttle_group;
3813 atomic_set(&mrioc->pend_large_data_sz, 0);
3816 mrioc->max_host_ios = min_t(int, mrioc->max_host_ios,
3817 MPI3MR_HOST_IOS_KDUMP);
3819 if (!(mrioc->facts.ioc_capabilities &
3820 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED)) {
3821 mrioc->sas_transport_enabled = 1;
3822 mrioc->scsi_device_channel = 1;
3823 mrioc->shost->max_channel = 1;
3824 mrioc->shost->transportt = mpi3mr_transport_template;
3827 mrioc->reply_sz = mrioc->facts.reply_sz;
3829 retval = mpi3mr_check_reset_dma_mask(mrioc);
3831 ioc_err(mrioc, "Resetting dma mask failed %d\n",
3833 goto out_failed_noretry;
3836 mpi3mr_print_ioc_info(mrioc);
3838 if (!mrioc->cfg_page) {
3839 dprint_init(mrioc, "allocating config page buffers\n");
3840 mrioc->cfg_page_sz = MPI3MR_DEFAULT_CFG_PAGE_SZ;
3841 mrioc->cfg_page = dma_alloc_coherent(&mrioc->pdev->dev,
3842 mrioc->cfg_page_sz, &mrioc->cfg_page_dma, GFP_KERNEL);
3843 if (!mrioc->cfg_page) {
3845 goto out_failed_noretry;
3849 if (!mrioc->init_cmds.reply) {
3850 retval = mpi3mr_alloc_reply_sense_bufs(mrioc);
3853 "%s :Failed to allocated reply sense buffers %d\n",
3855 goto out_failed_noretry;
3859 if (!mrioc->chain_sgl_list) {
3860 retval = mpi3mr_alloc_chain_bufs(mrioc);
3862 ioc_err(mrioc, "Failed to allocated chain buffers %d\n",
3864 goto out_failed_noretry;
3868 retval = mpi3mr_issue_iocinit(mrioc);
3870 ioc_err(mrioc, "Failed to Issue IOC Init %d\n",
3875 retval = mpi3mr_print_pkg_ver(mrioc);
3877 ioc_err(mrioc, "failed to get package version\n");
3881 retval = mpi3mr_setup_isr(mrioc, 0);
3883 ioc_err(mrioc, "Failed to re-setup ISR, error %d\n",
3885 goto out_failed_noretry;
3888 retval = mpi3mr_create_op_queues(mrioc);
3890 ioc_err(mrioc, "Failed to create OpQueues error %d\n",
3895 if (!mrioc->pel_seqnum_virt) {
3896 dprint_init(mrioc, "allocating memory for pel_seqnum_virt\n");
3897 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
3898 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
3899 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
3901 if (!mrioc->pel_seqnum_virt) {
3903 goto out_failed_noretry;
3907 if (!mrioc->throttle_groups && mrioc->num_io_throttle_group) {
3908 dprint_init(mrioc, "allocating memory for throttle groups\n");
3909 sz = sizeof(struct mpi3mr_throttle_group_info);
3910 mrioc->throttle_groups = kcalloc(mrioc->num_io_throttle_group, sz, GFP_KERNEL);
3911 if (!mrioc->throttle_groups) {
3913 goto out_failed_noretry;
3917 retval = mpi3mr_enable_events(mrioc);
3919 ioc_err(mrioc, "failed to enable events %d\n",
3924 ioc_info(mrioc, "controller initialization completed successfully\n");
3929 ioc_warn(mrioc, "retrying controller initialization, retry_count:%d\n",
3931 mpi3mr_memset_buffers(mrioc);
3936 ioc_err(mrioc, "controller initialization failed\n");
3937 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
3938 MPI3MR_RESET_FROM_CTLR_CLEANUP);
3939 mrioc->unrecoverable = 1;
3944 * mpi3mr_reinit_ioc - Re-Initialize the controller
3945 * @mrioc: Adapter instance reference
3946 * @is_resume: Called from resume or reset path
3948 * This the controller re-initialization routine, executed from
3949 * the soft reset handler or resume callback. Creates
3950 * operational reply queue pairs, allocate required memory for
3951 * reply pool, sense buffer pool, issue IOC init request to the
3952 * firmware, unmask the events and issue port enable to discover
3953 * SAS/SATA/NVMe devices and RAID volumes.
3955 * Return: 0 on success and non-zero on failure.
3957 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume)
3961 struct mpi3_ioc_facts_data facts_data;
3962 u32 pe_timeout, ioc_status;
3966 (MPI3MR_PORTENABLE_TIMEOUT / MPI3MR_PORTENABLE_POLL_INTERVAL);
3968 dprint_reset(mrioc, "bringing up the controller to ready state\n");
3969 retval = mpi3mr_bring_ioc_ready(mrioc);
3971 ioc_err(mrioc, "failed to bring to ready state\n");
3972 goto out_failed_noretry;
3976 dprint_reset(mrioc, "setting up single ISR\n");
3977 retval = mpi3mr_setup_isr(mrioc, 1);
3979 ioc_err(mrioc, "failed to setup ISR\n");
3980 goto out_failed_noretry;
3983 mpi3mr_ioc_enable_intr(mrioc);
3985 dprint_reset(mrioc, "getting ioc_facts\n");
3986 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
3988 ioc_err(mrioc, "failed to get ioc_facts\n");
3992 dprint_reset(mrioc, "validating ioc_facts\n");
3993 retval = mpi3mr_revalidate_factsdata(mrioc);
3995 ioc_err(mrioc, "failed to revalidate ioc_facts data\n");
3996 goto out_failed_noretry;
3999 mpi3mr_print_ioc_info(mrioc);
4001 dprint_reset(mrioc, "sending ioc_init\n");
4002 retval = mpi3mr_issue_iocinit(mrioc);
4004 ioc_err(mrioc, "failed to send ioc_init\n");
4008 dprint_reset(mrioc, "getting package version\n");
4009 retval = mpi3mr_print_pkg_ver(mrioc);
4011 ioc_err(mrioc, "failed to get package version\n");
4016 dprint_reset(mrioc, "setting up multiple ISR\n");
4017 retval = mpi3mr_setup_isr(mrioc, 0);
4019 ioc_err(mrioc, "failed to re-setup ISR\n");
4020 goto out_failed_noretry;
4024 dprint_reset(mrioc, "creating operational queue pairs\n");
4025 retval = mpi3mr_create_op_queues(mrioc);
4027 ioc_err(mrioc, "failed to create operational queue pairs\n");
4031 if (!mrioc->pel_seqnum_virt) {
4032 dprint_reset(mrioc, "allocating memory for pel_seqnum_virt\n");
4033 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
4034 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
4035 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
4037 if (!mrioc->pel_seqnum_virt) {
4039 goto out_failed_noretry;
4043 if (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q) {
4045 "cannot create minimum number of operational queues expected:%d created:%d\n",
4046 mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q);
4048 goto out_failed_noretry;
4051 dprint_reset(mrioc, "enabling events\n");
4052 retval = mpi3mr_enable_events(mrioc);
4054 ioc_err(mrioc, "failed to enable events\n");
4058 mrioc->device_refresh_on = 1;
4059 mpi3mr_add_event_wait_for_device_refresh(mrioc);
4061 ioc_info(mrioc, "sending port enable\n");
4062 retval = mpi3mr_issue_port_enable(mrioc, 1);
4064 ioc_err(mrioc, "failed to issue port enable\n");
4068 ssleep(MPI3MR_PORTENABLE_POLL_INTERVAL);
4069 if (mrioc->init_cmds.state == MPI3MR_CMD_NOTUSED)
4071 if (!pci_device_is_present(mrioc->pdev))
4072 mrioc->unrecoverable = 1;
4073 if (mrioc->unrecoverable) {
4075 goto out_failed_noretry;
4077 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4078 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
4079 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
4080 mpi3mr_print_fault_info(mrioc);
4081 mrioc->init_cmds.is_waiting = 0;
4082 mrioc->init_cmds.callback = NULL;
4083 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4086 } while (--pe_timeout);
4089 ioc_err(mrioc, "port enable timed out\n");
4090 mpi3mr_check_rh_fault_ioc(mrioc,
4091 MPI3MR_RESET_FROM_PE_TIMEOUT);
4092 mrioc->init_cmds.is_waiting = 0;
4093 mrioc->init_cmds.callback = NULL;
4094 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4096 } else if (mrioc->scan_failed) {
4098 "port enable failed with status=0x%04x\n",
4099 mrioc->scan_failed);
4101 ioc_info(mrioc, "port enable completed successfully\n");
4103 ioc_info(mrioc, "controller %s completed successfully\n",
4104 (is_resume)?"resume":"re-initialization");
4109 ioc_warn(mrioc, "retrying controller %s, retry_count:%d\n",
4110 (is_resume)?"resume":"re-initialization", retry);
4111 mpi3mr_memset_buffers(mrioc);
4116 ioc_err(mrioc, "controller %s is failed\n",
4117 (is_resume)?"resume":"re-initialization");
4118 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
4119 MPI3MR_RESET_FROM_CTLR_CLEANUP);
4120 mrioc->unrecoverable = 1;
4125 * mpi3mr_memset_op_reply_q_buffers - memset the operational reply queue's
4127 * @mrioc: Adapter instance reference
4128 * @qidx: Operational reply queue index
4132 static void mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4134 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
4135 struct segments *segments;
4138 if (!op_reply_q->q_segments)
4141 size = op_reply_q->segment_qd * mrioc->op_reply_desc_sz;
4142 segments = op_reply_q->q_segments;
4143 for (i = 0; i < op_reply_q->num_segments; i++)
4144 memset(segments[i].segment, 0, size);
4148 * mpi3mr_memset_op_req_q_buffers - memset the operational request queue's
4150 * @mrioc: Adapter instance reference
4151 * @qidx: Operational request queue index
4155 static void mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4157 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
4158 struct segments *segments;
4161 if (!op_req_q->q_segments)
4164 size = op_req_q->segment_qd * mrioc->facts.op_req_sz;
4165 segments = op_req_q->q_segments;
4166 for (i = 0; i < op_req_q->num_segments; i++)
4167 memset(segments[i].segment, 0, size);
4171 * mpi3mr_memset_buffers - memset memory for a controller
4172 * @mrioc: Adapter instance reference
4174 * clear all the memory allocated for a controller, typically
4175 * called post reset to reuse the memory allocated during the
4180 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc)
4183 struct mpi3mr_throttle_group_info *tg;
4185 mrioc->change_count = 0;
4186 mrioc->active_poll_qcount = 0;
4187 mrioc->default_qcount = 0;
4188 if (mrioc->admin_req_base)
4189 memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz);
4190 if (mrioc->admin_reply_base)
4191 memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz);
4192 atomic_set(&mrioc->admin_reply_q_in_use, 0);
4194 if (mrioc->init_cmds.reply) {
4195 memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply));
4196 memset(mrioc->bsg_cmds.reply, 0,
4197 sizeof(*mrioc->bsg_cmds.reply));
4198 memset(mrioc->host_tm_cmds.reply, 0,
4199 sizeof(*mrioc->host_tm_cmds.reply));
4200 memset(mrioc->pel_cmds.reply, 0,
4201 sizeof(*mrioc->pel_cmds.reply));
4202 memset(mrioc->pel_abort_cmd.reply, 0,
4203 sizeof(*mrioc->pel_abort_cmd.reply));
4204 memset(mrioc->transport_cmds.reply, 0,
4205 sizeof(*mrioc->transport_cmds.reply));
4206 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++)
4207 memset(mrioc->dev_rmhs_cmds[i].reply, 0,
4208 sizeof(*mrioc->dev_rmhs_cmds[i].reply));
4209 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++)
4210 memset(mrioc->evtack_cmds[i].reply, 0,
4211 sizeof(*mrioc->evtack_cmds[i].reply));
4212 bitmap_clear(mrioc->removepend_bitmap, 0,
4213 mrioc->dev_handle_bitmap_bits);
4214 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
4215 bitmap_clear(mrioc->evtack_cmds_bitmap, 0,
4216 MPI3MR_NUM_EVTACKCMD);
4219 for (i = 0; i < mrioc->num_queues; i++) {
4220 mrioc->op_reply_qinfo[i].qid = 0;
4221 mrioc->op_reply_qinfo[i].ci = 0;
4222 mrioc->op_reply_qinfo[i].num_replies = 0;
4223 mrioc->op_reply_qinfo[i].ephase = 0;
4224 atomic_set(&mrioc->op_reply_qinfo[i].pend_ios, 0);
4225 atomic_set(&mrioc->op_reply_qinfo[i].in_use, 0);
4226 mpi3mr_memset_op_reply_q_buffers(mrioc, i);
4228 mrioc->req_qinfo[i].ci = 0;
4229 mrioc->req_qinfo[i].pi = 0;
4230 mrioc->req_qinfo[i].num_requests = 0;
4231 mrioc->req_qinfo[i].qid = 0;
4232 mrioc->req_qinfo[i].reply_qid = 0;
4233 spin_lock_init(&mrioc->req_qinfo[i].q_lock);
4234 mpi3mr_memset_op_req_q_buffers(mrioc, i);
4237 atomic_set(&mrioc->pend_large_data_sz, 0);
4238 if (mrioc->throttle_groups) {
4239 tg = mrioc->throttle_groups;
4240 for (i = 0; i < mrioc->num_io_throttle_group; i++, tg++) {
4243 tg->modified_qd = 0;
4245 tg->need_qd_reduction = 0;
4248 tg->qd_reduction = 0;
4249 atomic_set(&tg->pend_large_data_sz, 0);
4255 * mpi3mr_free_mem - Free memory allocated for a controller
4256 * @mrioc: Adapter instance reference
4258 * Free all the memory allocated for a controller.
4262 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc)
4265 struct mpi3mr_intr_info *intr_info;
4267 mpi3mr_free_enclosure_list(mrioc);
4269 if (mrioc->sense_buf_pool) {
4270 if (mrioc->sense_buf)
4271 dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf,
4272 mrioc->sense_buf_dma);
4273 dma_pool_destroy(mrioc->sense_buf_pool);
4274 mrioc->sense_buf = NULL;
4275 mrioc->sense_buf_pool = NULL;
4277 if (mrioc->sense_buf_q_pool) {
4278 if (mrioc->sense_buf_q)
4279 dma_pool_free(mrioc->sense_buf_q_pool,
4280 mrioc->sense_buf_q, mrioc->sense_buf_q_dma);
4281 dma_pool_destroy(mrioc->sense_buf_q_pool);
4282 mrioc->sense_buf_q = NULL;
4283 mrioc->sense_buf_q_pool = NULL;
4286 if (mrioc->reply_buf_pool) {
4287 if (mrioc->reply_buf)
4288 dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf,
4289 mrioc->reply_buf_dma);
4290 dma_pool_destroy(mrioc->reply_buf_pool);
4291 mrioc->reply_buf = NULL;
4292 mrioc->reply_buf_pool = NULL;
4294 if (mrioc->reply_free_q_pool) {
4295 if (mrioc->reply_free_q)
4296 dma_pool_free(mrioc->reply_free_q_pool,
4297 mrioc->reply_free_q, mrioc->reply_free_q_dma);
4298 dma_pool_destroy(mrioc->reply_free_q_pool);
4299 mrioc->reply_free_q = NULL;
4300 mrioc->reply_free_q_pool = NULL;
4303 for (i = 0; i < mrioc->num_op_req_q; i++)
4304 mpi3mr_free_op_req_q_segments(mrioc, i);
4306 for (i = 0; i < mrioc->num_op_reply_q; i++)
4307 mpi3mr_free_op_reply_q_segments(mrioc, i);
4309 for (i = 0; i < mrioc->intr_info_count; i++) {
4310 intr_info = mrioc->intr_info + i;
4311 intr_info->op_reply_q = NULL;
4314 kfree(mrioc->req_qinfo);
4315 mrioc->req_qinfo = NULL;
4316 mrioc->num_op_req_q = 0;
4318 kfree(mrioc->op_reply_qinfo);
4319 mrioc->op_reply_qinfo = NULL;
4320 mrioc->num_op_reply_q = 0;
4322 kfree(mrioc->init_cmds.reply);
4323 mrioc->init_cmds.reply = NULL;
4325 kfree(mrioc->bsg_cmds.reply);
4326 mrioc->bsg_cmds.reply = NULL;
4328 kfree(mrioc->host_tm_cmds.reply);
4329 mrioc->host_tm_cmds.reply = NULL;
4331 kfree(mrioc->pel_cmds.reply);
4332 mrioc->pel_cmds.reply = NULL;
4334 kfree(mrioc->pel_abort_cmd.reply);
4335 mrioc->pel_abort_cmd.reply = NULL;
4337 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4338 kfree(mrioc->evtack_cmds[i].reply);
4339 mrioc->evtack_cmds[i].reply = NULL;
4342 bitmap_free(mrioc->removepend_bitmap);
4343 mrioc->removepend_bitmap = NULL;
4345 bitmap_free(mrioc->devrem_bitmap);
4346 mrioc->devrem_bitmap = NULL;
4348 bitmap_free(mrioc->evtack_cmds_bitmap);
4349 mrioc->evtack_cmds_bitmap = NULL;
4351 bitmap_free(mrioc->chain_bitmap);
4352 mrioc->chain_bitmap = NULL;
4354 kfree(mrioc->transport_cmds.reply);
4355 mrioc->transport_cmds.reply = NULL;
4357 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4358 kfree(mrioc->dev_rmhs_cmds[i].reply);
4359 mrioc->dev_rmhs_cmds[i].reply = NULL;
4362 if (mrioc->chain_buf_pool) {
4363 for (i = 0; i < mrioc->chain_buf_count; i++) {
4364 if (mrioc->chain_sgl_list[i].addr) {
4365 dma_pool_free(mrioc->chain_buf_pool,
4366 mrioc->chain_sgl_list[i].addr,
4367 mrioc->chain_sgl_list[i].dma_addr);
4368 mrioc->chain_sgl_list[i].addr = NULL;
4371 dma_pool_destroy(mrioc->chain_buf_pool);
4372 mrioc->chain_buf_pool = NULL;
4375 kfree(mrioc->chain_sgl_list);
4376 mrioc->chain_sgl_list = NULL;
4378 if (mrioc->admin_reply_base) {
4379 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
4380 mrioc->admin_reply_base, mrioc->admin_reply_dma);
4381 mrioc->admin_reply_base = NULL;
4383 if (mrioc->admin_req_base) {
4384 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
4385 mrioc->admin_req_base, mrioc->admin_req_dma);
4386 mrioc->admin_req_base = NULL;
4388 if (mrioc->cfg_page) {
4389 dma_free_coherent(&mrioc->pdev->dev, mrioc->cfg_page_sz,
4390 mrioc->cfg_page, mrioc->cfg_page_dma);
4391 mrioc->cfg_page = NULL;
4393 if (mrioc->pel_seqnum_virt) {
4394 dma_free_coherent(&mrioc->pdev->dev, mrioc->pel_seqnum_sz,
4395 mrioc->pel_seqnum_virt, mrioc->pel_seqnum_dma);
4396 mrioc->pel_seqnum_virt = NULL;
4399 kfree(mrioc->throttle_groups);
4400 mrioc->throttle_groups = NULL;
4402 kfree(mrioc->logdata_buf);
4403 mrioc->logdata_buf = NULL;
4408 * mpi3mr_issue_ioc_shutdown - shutdown controller
4409 * @mrioc: Adapter instance reference
4411 * Send shutodwn notification to the controller and wait for the
4412 * shutdown_timeout for it to be completed.
4416 static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc)
4418 u32 ioc_config, ioc_status;
4420 u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10;
4422 ioc_info(mrioc, "Issuing shutdown Notification\n");
4423 if (mrioc->unrecoverable) {
4425 "IOC is unrecoverable shutdown is not issued\n");
4428 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4429 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4430 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) {
4431 ioc_info(mrioc, "shutdown already in progress\n");
4435 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4436 ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL;
4437 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ;
4439 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
4441 if (mrioc->facts.shutdown_timeout)
4442 timeout = mrioc->facts.shutdown_timeout * 10;
4445 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4446 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4447 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) {
4452 } while (--timeout);
4454 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4455 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4458 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4459 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS)
4461 "shutdown still in progress after timeout\n");
4465 "Base IOC Sts/Config after %s shutdown is (0x%x)/(0x%x)\n",
4466 (!retval) ? "successful" : "failed", ioc_status,
4471 * mpi3mr_cleanup_ioc - Cleanup controller
4472 * @mrioc: Adapter instance reference
4474 * controller cleanup handler, Message unit reset or soft reset
4475 * and shutdown notification is issued to the controller.
4479 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc)
4481 enum mpi3mr_iocstate ioc_state;
4483 dprint_exit(mrioc, "cleaning up the controller\n");
4484 mpi3mr_ioc_disable_intr(mrioc);
4486 ioc_state = mpi3mr_get_iocstate(mrioc);
4488 if ((!mrioc->unrecoverable) && (!mrioc->reset_in_progress) &&
4489 (ioc_state == MRIOC_STATE_READY)) {
4490 if (mpi3mr_issue_and_process_mur(mrioc,
4491 MPI3MR_RESET_FROM_CTLR_CLEANUP))
4492 mpi3mr_issue_reset(mrioc,
4493 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
4494 MPI3MR_RESET_FROM_MUR_FAILURE);
4495 mpi3mr_issue_ioc_shutdown(mrioc);
4497 dprint_exit(mrioc, "controller cleanup completed\n");
4501 * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command
4502 * @mrioc: Adapter instance reference
4503 * @cmdptr: Internal command tracker
4505 * Complete an internal driver commands with state indicating it
4506 * is completed due to reset.
4510 static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc *mrioc,
4511 struct mpi3mr_drv_cmd *cmdptr)
4513 if (cmdptr->state & MPI3MR_CMD_PENDING) {
4514 cmdptr->state |= MPI3MR_CMD_RESET;
4515 cmdptr->state &= ~MPI3MR_CMD_PENDING;
4516 if (cmdptr->is_waiting) {
4517 complete(&cmdptr->done);
4518 cmdptr->is_waiting = 0;
4519 } else if (cmdptr->callback)
4520 cmdptr->callback(mrioc, cmdptr);
4525 * mpi3mr_flush_drv_cmds - Flush internaldriver commands
4526 * @mrioc: Adapter instance reference
4528 * Flush all internal driver commands post reset
4532 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc)
4534 struct mpi3mr_drv_cmd *cmdptr;
4537 cmdptr = &mrioc->init_cmds;
4538 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4540 cmdptr = &mrioc->cfg_cmds;
4541 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4543 cmdptr = &mrioc->bsg_cmds;
4544 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4545 cmdptr = &mrioc->host_tm_cmds;
4546 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4548 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4549 cmdptr = &mrioc->dev_rmhs_cmds[i];
4550 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4553 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4554 cmdptr = &mrioc->evtack_cmds[i];
4555 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4558 cmdptr = &mrioc->pel_cmds;
4559 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4561 cmdptr = &mrioc->pel_abort_cmd;
4562 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4564 cmdptr = &mrioc->transport_cmds;
4565 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4569 * mpi3mr_pel_wait_post - Issue PEL Wait
4570 * @mrioc: Adapter instance reference
4571 * @drv_cmd: Internal command tracker
4573 * Issue PEL Wait MPI request through admin queue and return.
4577 static void mpi3mr_pel_wait_post(struct mpi3mr_ioc *mrioc,
4578 struct mpi3mr_drv_cmd *drv_cmd)
4580 struct mpi3_pel_req_action_wait pel_wait;
4582 mrioc->pel_abort_requested = false;
4584 memset(&pel_wait, 0, sizeof(pel_wait));
4585 drv_cmd->state = MPI3MR_CMD_PENDING;
4586 drv_cmd->is_waiting = 0;
4587 drv_cmd->callback = mpi3mr_pel_wait_complete;
4588 drv_cmd->ioc_status = 0;
4589 drv_cmd->ioc_loginfo = 0;
4590 pel_wait.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
4591 pel_wait.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
4592 pel_wait.action = MPI3_PEL_ACTION_WAIT;
4593 pel_wait.starting_sequence_number = cpu_to_le32(mrioc->pel_newest_seqnum);
4594 pel_wait.locale = cpu_to_le16(mrioc->pel_locale);
4595 pel_wait.class = cpu_to_le16(mrioc->pel_class);
4596 pel_wait.wait_time = MPI3_PEL_WAITTIME_INFINITE_WAIT;
4597 dprint_bsg_info(mrioc, "sending pel_wait seqnum(%d), class(%d), locale(0x%08x)\n",
4598 mrioc->pel_newest_seqnum, mrioc->pel_class, mrioc->pel_locale);
4600 if (mpi3mr_admin_request_post(mrioc, &pel_wait, sizeof(pel_wait), 0)) {
4601 dprint_bsg_err(mrioc,
4602 "Issuing PELWait: Admin post failed\n");
4603 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4604 drv_cmd->callback = NULL;
4605 drv_cmd->retry_count = 0;
4606 mrioc->pel_enabled = false;
4611 * mpi3mr_pel_get_seqnum_post - Issue PEL Get Sequence number
4612 * @mrioc: Adapter instance reference
4613 * @drv_cmd: Internal command tracker
4615 * Issue PEL get sequence number MPI request through admin queue
4618 * Return: 0 on success, non-zero on failure.
4620 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,
4621 struct mpi3mr_drv_cmd *drv_cmd)
4623 struct mpi3_pel_req_action_get_sequence_numbers pel_getseq_req;
4624 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
4627 memset(&pel_getseq_req, 0, sizeof(pel_getseq_req));
4628 mrioc->pel_cmds.state = MPI3MR_CMD_PENDING;
4629 mrioc->pel_cmds.is_waiting = 0;
4630 mrioc->pel_cmds.ioc_status = 0;
4631 mrioc->pel_cmds.ioc_loginfo = 0;
4632 mrioc->pel_cmds.callback = mpi3mr_pel_get_seqnum_complete;
4633 pel_getseq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
4634 pel_getseq_req.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
4635 pel_getseq_req.action = MPI3_PEL_ACTION_GET_SEQNUM;
4636 mpi3mr_add_sg_single(&pel_getseq_req.sgl, sgl_flags,
4637 mrioc->pel_seqnum_sz, mrioc->pel_seqnum_dma);
4639 retval = mpi3mr_admin_request_post(mrioc, &pel_getseq_req,
4640 sizeof(pel_getseq_req), 0);
4643 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4644 drv_cmd->callback = NULL;
4645 drv_cmd->retry_count = 0;
4647 mrioc->pel_enabled = false;
4654 * mpi3mr_pel_wait_complete - PELWait Completion callback
4655 * @mrioc: Adapter instance reference
4656 * @drv_cmd: Internal command tracker
4658 * This is a callback handler for the PELWait request and
4659 * firmware completes a PELWait request when it is aborted or a
4660 * new PEL entry is available. This sends AEN to the application
4661 * and if the PELwait completion is not due to PELAbort then
4662 * this will send a request for new PEL Sequence number
4666 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
4667 struct mpi3mr_drv_cmd *drv_cmd)
4669 struct mpi3_pel_reply *pel_reply = NULL;
4670 u16 ioc_status, pe_log_status;
4671 bool do_retry = false;
4673 if (drv_cmd->state & MPI3MR_CMD_RESET)
4674 goto cleanup_drv_cmd;
4676 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
4677 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
4678 ioc_err(mrioc, "%s: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
4679 __func__, ioc_status, drv_cmd->ioc_loginfo);
4680 dprint_bsg_err(mrioc,
4681 "pel_wait: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
4682 ioc_status, drv_cmd->ioc_loginfo);
4686 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
4687 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
4690 dprint_bsg_err(mrioc,
4691 "pel_wait: failed due to no reply\n");
4695 pe_log_status = le16_to_cpu(pel_reply->pe_log_status);
4696 if ((pe_log_status != MPI3_PEL_STATUS_SUCCESS) &&
4697 (pe_log_status != MPI3_PEL_STATUS_ABORTED)) {
4698 ioc_err(mrioc, "%s: Failed pe_log_status(0x%04x)\n",
4699 __func__, pe_log_status);
4700 dprint_bsg_err(mrioc,
4701 "pel_wait: failed due to pel_log_status(0x%04x)\n",
4707 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
4708 drv_cmd->retry_count++;
4709 dprint_bsg_err(mrioc, "pel_wait: retrying(%d)\n",
4710 drv_cmd->retry_count);
4711 mpi3mr_pel_wait_post(mrioc, drv_cmd);
4714 dprint_bsg_err(mrioc,
4715 "pel_wait: failed after all retries(%d)\n",
4716 drv_cmd->retry_count);
4719 atomic64_inc(&event_counter);
4720 if (!mrioc->pel_abort_requested) {
4721 mrioc->pel_cmds.retry_count = 0;
4722 mpi3mr_pel_get_seqnum_post(mrioc, &mrioc->pel_cmds);
4727 mrioc->pel_enabled = false;
4729 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4730 drv_cmd->callback = NULL;
4731 drv_cmd->retry_count = 0;
4735 * mpi3mr_pel_get_seqnum_complete - PELGetSeqNum Completion callback
4736 * @mrioc: Adapter instance reference
4737 * @drv_cmd: Internal command tracker
4739 * This is a callback handler for the PEL get sequence number
4740 * request and a new PEL wait request will be issued to the
4741 * firmware from this
4745 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
4746 struct mpi3mr_drv_cmd *drv_cmd)
4748 struct mpi3_pel_reply *pel_reply = NULL;
4749 struct mpi3_pel_seq *pel_seqnum_virt;
4751 bool do_retry = false;
4753 pel_seqnum_virt = (struct mpi3_pel_seq *)mrioc->pel_seqnum_virt;
4755 if (drv_cmd->state & MPI3MR_CMD_RESET)
4756 goto cleanup_drv_cmd;
4758 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
4759 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
4760 dprint_bsg_err(mrioc,
4761 "pel_get_seqnum: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
4762 ioc_status, drv_cmd->ioc_loginfo);
4766 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
4767 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
4769 dprint_bsg_err(mrioc,
4770 "pel_get_seqnum: failed due to no reply\n");
4774 if (le16_to_cpu(pel_reply->pe_log_status) != MPI3_PEL_STATUS_SUCCESS) {
4775 dprint_bsg_err(mrioc,
4776 "pel_get_seqnum: failed due to pel_log_status(0x%04x)\n",
4777 le16_to_cpu(pel_reply->pe_log_status));
4782 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
4783 drv_cmd->retry_count++;
4784 dprint_bsg_err(mrioc,
4785 "pel_get_seqnum: retrying(%d)\n",
4786 drv_cmd->retry_count);
4787 mpi3mr_pel_get_seqnum_post(mrioc, drv_cmd);
4791 dprint_bsg_err(mrioc,
4792 "pel_get_seqnum: failed after all retries(%d)\n",
4793 drv_cmd->retry_count);
4796 mrioc->pel_newest_seqnum = le32_to_cpu(pel_seqnum_virt->newest) + 1;
4797 drv_cmd->retry_count = 0;
4798 mpi3mr_pel_wait_post(mrioc, drv_cmd);
4802 mrioc->pel_enabled = false;
4804 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4805 drv_cmd->callback = NULL;
4806 drv_cmd->retry_count = 0;
4810 * mpi3mr_soft_reset_handler - Reset the controller
4811 * @mrioc: Adapter instance reference
4812 * @reset_reason: Reset reason code
4813 * @snapdump: Flag to generate snapdump in firmware or not
4815 * This is an handler for recovering controller by issuing soft
4816 * reset are diag fault reset. This is a blocking function and
4817 * when one reset is executed if any other resets they will be
4818 * blocked. All BSG requests will be blocked during the reset. If
4819 * controller reset is successful then the controller will be
4820 * reinitalized, otherwise the controller will be marked as not
4823 * In snapdump bit is set, the controller is issued with diag
4824 * fault reset so that the firmware can create a snap dump and
4825 * post that the firmware will result in F000 fault and the
4826 * driver will issue soft reset to recover from that.
4828 * Return: 0 on success, non-zero on failure.
4830 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
4831 u32 reset_reason, u8 snapdump)
4834 unsigned long flags;
4835 u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
4837 /* Block the reset handler until diag save in progress*/
4839 "soft_reset_handler: check and block on diagsave_timeout(%d)\n",
4840 mrioc->diagsave_timeout);
4841 while (mrioc->diagsave_timeout)
4844 * Block new resets until the currently executing one is finished and
4845 * return the status of the existing reset for all blocked resets
4847 dprint_reset(mrioc, "soft_reset_handler: acquiring reset_mutex\n");
4848 if (!mutex_trylock(&mrioc->reset_mutex)) {
4850 "controller reset triggered by %s is blocked due to another reset in progress\n",
4851 mpi3mr_reset_rc_name(reset_reason));
4854 } while (mrioc->reset_in_progress == 1);
4856 "returning previous reset result(%d) for the reset triggered by %s\n",
4857 mrioc->prev_reset_result,
4858 mpi3mr_reset_rc_name(reset_reason));
4859 return mrioc->prev_reset_result;
4861 ioc_info(mrioc, "controller reset is triggered by %s\n",
4862 mpi3mr_reset_rc_name(reset_reason));
4864 mrioc->device_refresh_on = 0;
4865 mrioc->reset_in_progress = 1;
4866 mrioc->stop_bsgs = 1;
4867 mrioc->prev_reset_result = -1;
4869 if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) &&
4870 (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) &&
4871 (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) {
4872 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4873 mrioc->event_masks[i] = -1;
4875 dprint_reset(mrioc, "soft_reset_handler: masking events\n");
4876 mpi3mr_issue_event_notification(mrioc);
4879 mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT);
4881 mpi3mr_ioc_disable_intr(mrioc);
4884 mpi3mr_set_diagsave(mrioc);
4885 retval = mpi3mr_issue_reset(mrioc,
4886 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
4890 readl(&mrioc->sysif_regs->host_diagnostic);
4891 if (!(host_diagnostic &
4892 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
4895 } while (--timeout);
4899 retval = mpi3mr_issue_reset(mrioc,
4900 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason);
4902 ioc_err(mrioc, "Failed to issue soft reset to the ioc\n");
4905 if (mrioc->num_io_throttle_group !=
4906 mrioc->facts.max_io_throttle_group) {
4908 "max io throttle group doesn't match old(%d), new(%d)\n",
4909 mrioc->num_io_throttle_group,
4910 mrioc->facts.max_io_throttle_group);
4915 mpi3mr_flush_delayed_cmd_lists(mrioc);
4916 mpi3mr_flush_drv_cmds(mrioc);
4917 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
4918 bitmap_clear(mrioc->removepend_bitmap, 0,
4919 mrioc->dev_handle_bitmap_bits);
4920 bitmap_clear(mrioc->evtack_cmds_bitmap, 0, MPI3MR_NUM_EVTACKCMD);
4921 mpi3mr_flush_host_io(mrioc);
4922 mpi3mr_cleanup_fwevt_list(mrioc);
4923 mpi3mr_invalidate_devhandles(mrioc);
4924 mpi3mr_free_enclosure_list(mrioc);
4926 if (mrioc->prepare_for_reset) {
4927 mrioc->prepare_for_reset = 0;
4928 mrioc->prepare_for_reset_timeout_counter = 0;
4930 mpi3mr_memset_buffers(mrioc);
4931 retval = mpi3mr_reinit_ioc(mrioc, 0);
4933 pr_err(IOCNAME "reinit after soft reset failed: reason %d\n",
4934 mrioc->name, reset_reason);
4937 ssleep(MPI3MR_RESET_TOPOLOGY_SETTLE_TIME);
4941 mrioc->diagsave_timeout = 0;
4942 mrioc->reset_in_progress = 0;
4943 mrioc->pel_abort_requested = 0;
4944 if (mrioc->pel_enabled) {
4945 mrioc->pel_cmds.retry_count = 0;
4946 mpi3mr_pel_wait_post(mrioc, &mrioc->pel_cmds);
4949 mrioc->device_refresh_on = 0;
4951 mrioc->ts_update_counter = 0;
4952 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
4953 if (mrioc->watchdog_work_q)
4954 queue_delayed_work(mrioc->watchdog_work_q,
4955 &mrioc->watchdog_work,
4956 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
4957 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
4958 mrioc->stop_bsgs = 0;
4959 if (mrioc->pel_enabled)
4960 atomic64_inc(&event_counter);
4962 mpi3mr_issue_reset(mrioc,
4963 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
4964 mrioc->device_refresh_on = 0;
4965 mrioc->unrecoverable = 1;
4966 mrioc->reset_in_progress = 0;
4968 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
4970 mrioc->prev_reset_result = retval;
4971 mutex_unlock(&mrioc->reset_mutex);
4972 ioc_info(mrioc, "controller reset is %s\n",
4973 ((retval == 0) ? "successful" : "failed"));
4979 * mpi3mr_free_config_dma_memory - free memory for config page
4980 * @mrioc: Adapter instance reference
4981 * @mem_desc: memory descriptor structure
4983 * Check whether the size of the buffer specified by the memory
4984 * descriptor is greater than the default page size if so then
4985 * free the memory pointed by the descriptor.
4989 static void mpi3mr_free_config_dma_memory(struct mpi3mr_ioc *mrioc,
4990 struct dma_memory_desc *mem_desc)
4992 if ((mem_desc->size > mrioc->cfg_page_sz) && mem_desc->addr) {
4993 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size,
4994 mem_desc->addr, mem_desc->dma_addr);
4995 mem_desc->addr = NULL;
5000 * mpi3mr_alloc_config_dma_memory - Alloc memory for config page
5001 * @mrioc: Adapter instance reference
5002 * @mem_desc: Memory descriptor to hold dma memory info
5004 * This function allocates new dmaable memory or provides the
5005 * default config page dmaable memory based on the memory size
5006 * described by the descriptor.
5008 * Return: 0 on success, non-zero on failure.
5010 static int mpi3mr_alloc_config_dma_memory(struct mpi3mr_ioc *mrioc,
5011 struct dma_memory_desc *mem_desc)
5013 if (mem_desc->size > mrioc->cfg_page_sz) {
5014 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev,
5015 mem_desc->size, &mem_desc->dma_addr, GFP_KERNEL);
5016 if (!mem_desc->addr)
5019 mem_desc->addr = mrioc->cfg_page;
5020 mem_desc->dma_addr = mrioc->cfg_page_dma;
5021 memset(mem_desc->addr, 0, mrioc->cfg_page_sz);
5027 * mpi3mr_post_cfg_req - Issue config requests and wait
5028 * @mrioc: Adapter instance reference
5029 * @cfg_req: Configuration request
5030 * @timeout: Timeout in seconds
5031 * @ioc_status: Pointer to return ioc status
5033 * A generic function for posting MPI3 configuration request to
5034 * the firmware. This blocks for the completion of request for
5035 * timeout seconds and if the request times out this function
5036 * faults the controller with proper reason code.
5038 * On successful completion of the request this function returns
5039 * appropriate ioc status from the firmware back to the caller.
5041 * Return: 0 on success, non-zero on failure.
5043 static int mpi3mr_post_cfg_req(struct mpi3mr_ioc *mrioc,
5044 struct mpi3_config_request *cfg_req, int timeout, u16 *ioc_status)
5048 mutex_lock(&mrioc->cfg_cmds.mutex);
5049 if (mrioc->cfg_cmds.state & MPI3MR_CMD_PENDING) {
5051 ioc_err(mrioc, "sending config request failed due to command in use\n");
5052 mutex_unlock(&mrioc->cfg_cmds.mutex);
5055 mrioc->cfg_cmds.state = MPI3MR_CMD_PENDING;
5056 mrioc->cfg_cmds.is_waiting = 1;
5057 mrioc->cfg_cmds.callback = NULL;
5058 mrioc->cfg_cmds.ioc_status = 0;
5059 mrioc->cfg_cmds.ioc_loginfo = 0;
5061 cfg_req->host_tag = cpu_to_le16(MPI3MR_HOSTTAG_CFG_CMDS);
5062 cfg_req->function = MPI3_FUNCTION_CONFIG;
5064 init_completion(&mrioc->cfg_cmds.done);
5065 dprint_cfg_info(mrioc, "posting config request\n");
5066 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5067 dprint_dump(cfg_req, sizeof(struct mpi3_config_request),
5069 retval = mpi3mr_admin_request_post(mrioc, cfg_req, sizeof(*cfg_req), 1);
5071 ioc_err(mrioc, "posting config request failed\n");
5074 wait_for_completion_timeout(&mrioc->cfg_cmds.done, (timeout * HZ));
5075 if (!(mrioc->cfg_cmds.state & MPI3MR_CMD_COMPLETE)) {
5076 mpi3mr_check_rh_fault_ioc(mrioc,
5077 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT);
5078 ioc_err(mrioc, "config request timed out\n");
5082 *ioc_status = mrioc->cfg_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5083 if ((*ioc_status) != MPI3_IOCSTATUS_SUCCESS)
5084 dprint_cfg_err(mrioc,
5085 "cfg_page request returned with ioc_status(0x%04x), log_info(0x%08x)\n",
5086 *ioc_status, mrioc->cfg_cmds.ioc_loginfo);
5089 mrioc->cfg_cmds.state = MPI3MR_CMD_NOTUSED;
5090 mutex_unlock(&mrioc->cfg_cmds.mutex);
5097 * mpi3mr_process_cfg_req - config page request processor
5098 * @mrioc: Adapter instance reference
5099 * @cfg_req: Configuration request
5100 * @cfg_hdr: Configuration page header
5101 * @timeout: Timeout in seconds
5102 * @ioc_status: Pointer to return ioc status
5103 * @cfg_buf: Memory pointer to copy config page or header
5104 * @cfg_buf_sz: Size of the memory to get config page or header
5106 * This is handler for config page read, write and config page
5107 * header read operations.
5109 * This function expects the cfg_req to be populated with page
5110 * type, page number, action for the header read and with page
5111 * address for all other operations.
5113 * The cfg_hdr can be passed as null for reading required header
5114 * details for read/write pages the cfg_hdr should point valid
5115 * configuration page header.
5117 * This allocates dmaable memory based on the size of the config
5118 * buffer and set the SGE of the cfg_req.
5120 * For write actions, the config page data has to be passed in
5121 * the cfg_buf and size of the data has to be mentioned in the
5124 * For read/header actions, on successful completion of the
5125 * request with successful ioc_status the data will be copied
5126 * into the cfg_buf limited to a minimum of actual page size and
5130 * Return: 0 on success, non-zero on failure.
5132 static int mpi3mr_process_cfg_req(struct mpi3mr_ioc *mrioc,
5133 struct mpi3_config_request *cfg_req,
5134 struct mpi3_config_page_header *cfg_hdr, int timeout, u16 *ioc_status,
5135 void *cfg_buf, u32 cfg_buf_sz)
5137 struct dma_memory_desc mem_desc;
5139 u8 invalid_action = 0;
5140 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
5142 memset(&mem_desc, 0, sizeof(struct dma_memory_desc));
5144 if (cfg_req->action == MPI3_CONFIG_ACTION_PAGE_HEADER)
5145 mem_desc.size = sizeof(struct mpi3_config_page_header);
5148 ioc_err(mrioc, "null config header passed for config action(%d), page_type(0x%02x), page_num(%d)\n",
5149 cfg_req->action, cfg_req->page_type,
5150 cfg_req->page_number);
5153 switch (cfg_hdr->page_attribute & MPI3_CONFIG_PAGEATTR_MASK) {
5154 case MPI3_CONFIG_PAGEATTR_READ_ONLY:
5156 != MPI3_CONFIG_ACTION_READ_CURRENT)
5159 case MPI3_CONFIG_PAGEATTR_CHANGEABLE:
5160 if ((cfg_req->action ==
5161 MPI3_CONFIG_ACTION_READ_PERSISTENT) ||
5163 MPI3_CONFIG_ACTION_WRITE_PERSISTENT))
5166 case MPI3_CONFIG_PAGEATTR_PERSISTENT:
5170 if (invalid_action) {
5172 "config action(%d) is not allowed for page_type(0x%02x), page_num(%d) with page_attribute(0x%02x)\n",
5173 cfg_req->action, cfg_req->page_type,
5174 cfg_req->page_number, cfg_hdr->page_attribute);
5177 mem_desc.size = le16_to_cpu(cfg_hdr->page_length) * 4;
5178 cfg_req->page_length = cfg_hdr->page_length;
5179 cfg_req->page_version = cfg_hdr->page_version;
5181 if (mpi3mr_alloc_config_dma_memory(mrioc, &mem_desc))
5184 mpi3mr_add_sg_single(&cfg_req->sgl, sgl_flags, mem_desc.size,
5187 if ((cfg_req->action == MPI3_CONFIG_ACTION_WRITE_PERSISTENT) ||
5188 (cfg_req->action == MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5189 memcpy(mem_desc.addr, cfg_buf, min_t(u16, mem_desc.size,
5191 dprint_cfg_info(mrioc, "config buffer to be written\n");
5192 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5193 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5196 if (mpi3mr_post_cfg_req(mrioc, cfg_req, timeout, ioc_status))
5200 if ((*ioc_status == MPI3_IOCSTATUS_SUCCESS) &&
5201 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_PERSISTENT) &&
5202 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5203 memcpy(cfg_buf, mem_desc.addr, min_t(u16, mem_desc.size,
5205 dprint_cfg_info(mrioc, "config buffer read\n");
5206 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5207 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5211 mpi3mr_free_config_dma_memory(mrioc, &mem_desc);
5216 * mpi3mr_cfg_get_dev_pg0 - Read current device page0
5217 * @mrioc: Adapter instance reference
5218 * @ioc_status: Pointer to return ioc status
5219 * @dev_pg0: Pointer to return device page 0
5220 * @pg_sz: Size of the memory allocated to the page pointer
5221 * @form: The form to be used for addressing the page
5222 * @form_spec: Form specific information like device handle
5224 * This is handler for config page read for a specific device
5225 * page0. The ioc_status has the controller returned ioc_status.
5226 * This routine doesn't check ioc_status to decide whether the
5227 * page read is success or not and it is the callers
5230 * Return: 0 on success, non-zero on failure.
5232 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5233 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec)
5235 struct mpi3_config_page_header cfg_hdr;
5236 struct mpi3_config_request cfg_req;
5239 memset(dev_pg0, 0, pg_sz);
5240 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5241 memset(&cfg_req, 0, sizeof(cfg_req));
5243 cfg_req.function = MPI3_FUNCTION_CONFIG;
5244 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5245 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DEVICE;
5246 cfg_req.page_number = 0;
5247 cfg_req.page_address = 0;
5249 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5250 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5251 ioc_err(mrioc, "device page0 header read failed\n");
5254 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5255 ioc_err(mrioc, "device page0 header read failed with ioc_status(0x%04x)\n",
5259 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5260 page_address = ((form & MPI3_DEVICE_PGAD_FORM_MASK) |
5261 (form_spec & MPI3_DEVICE_PGAD_HANDLE_MASK));
5262 cfg_req.page_address = cpu_to_le32(page_address);
5263 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5264 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, dev_pg0, pg_sz)) {
5265 ioc_err(mrioc, "device page0 read failed\n");
5275 * mpi3mr_cfg_get_sas_phy_pg0 - Read current SAS Phy page0
5276 * @mrioc: Adapter instance reference
5277 * @ioc_status: Pointer to return ioc status
5278 * @phy_pg0: Pointer to return SAS Phy page 0
5279 * @pg_sz: Size of the memory allocated to the page pointer
5280 * @form: The form to be used for addressing the page
5281 * @form_spec: Form specific information like phy number
5283 * This is handler for config page read for a specific SAS Phy
5284 * page0. The ioc_status has the controller returned ioc_status.
5285 * This routine doesn't check ioc_status to decide whether the
5286 * page read is success or not and it is the callers
5289 * Return: 0 on success, non-zero on failure.
5291 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5292 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form,
5295 struct mpi3_config_page_header cfg_hdr;
5296 struct mpi3_config_request cfg_req;
5299 memset(phy_pg0, 0, pg_sz);
5300 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5301 memset(&cfg_req, 0, sizeof(cfg_req));
5303 cfg_req.function = MPI3_FUNCTION_CONFIG;
5304 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5305 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5306 cfg_req.page_number = 0;
5307 cfg_req.page_address = 0;
5309 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5310 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5311 ioc_err(mrioc, "sas phy page0 header read failed\n");
5314 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5315 ioc_err(mrioc, "sas phy page0 header read failed with ioc_status(0x%04x)\n",
5319 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5320 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5321 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5322 cfg_req.page_address = cpu_to_le32(page_address);
5323 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5324 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg0, pg_sz)) {
5325 ioc_err(mrioc, "sas phy page0 read failed\n");
5334 * mpi3mr_cfg_get_sas_phy_pg1 - Read current SAS Phy page1
5335 * @mrioc: Adapter instance reference
5336 * @ioc_status: Pointer to return ioc status
5337 * @phy_pg1: Pointer to return SAS Phy page 1
5338 * @pg_sz: Size of the memory allocated to the page pointer
5339 * @form: The form to be used for addressing the page
5340 * @form_spec: Form specific information like phy number
5342 * This is handler for config page read for a specific SAS Phy
5343 * page1. The ioc_status has the controller returned ioc_status.
5344 * This routine doesn't check ioc_status to decide whether the
5345 * page read is success or not and it is the callers
5348 * Return: 0 on success, non-zero on failure.
5350 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5351 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form,
5354 struct mpi3_config_page_header cfg_hdr;
5355 struct mpi3_config_request cfg_req;
5358 memset(phy_pg1, 0, pg_sz);
5359 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5360 memset(&cfg_req, 0, sizeof(cfg_req));
5362 cfg_req.function = MPI3_FUNCTION_CONFIG;
5363 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5364 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5365 cfg_req.page_number = 1;
5366 cfg_req.page_address = 0;
5368 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5369 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5370 ioc_err(mrioc, "sas phy page1 header read failed\n");
5373 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5374 ioc_err(mrioc, "sas phy page1 header read failed with ioc_status(0x%04x)\n",
5378 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5379 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5380 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5381 cfg_req.page_address = cpu_to_le32(page_address);
5382 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5383 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg1, pg_sz)) {
5384 ioc_err(mrioc, "sas phy page1 read failed\n");
5394 * mpi3mr_cfg_get_sas_exp_pg0 - Read current SAS Expander page0
5395 * @mrioc: Adapter instance reference
5396 * @ioc_status: Pointer to return ioc status
5397 * @exp_pg0: Pointer to return SAS Expander page 0
5398 * @pg_sz: Size of the memory allocated to the page pointer
5399 * @form: The form to be used for addressing the page
5400 * @form_spec: Form specific information like device handle
5402 * This is handler for config page read for a specific SAS
5403 * Expander page0. The ioc_status has the controller returned
5404 * ioc_status. This routine doesn't check ioc_status to decide
5405 * whether the page read is success or not and it is the callers
5408 * Return: 0 on success, non-zero on failure.
5410 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5411 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form,
5414 struct mpi3_config_page_header cfg_hdr;
5415 struct mpi3_config_request cfg_req;
5418 memset(exp_pg0, 0, pg_sz);
5419 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5420 memset(&cfg_req, 0, sizeof(cfg_req));
5422 cfg_req.function = MPI3_FUNCTION_CONFIG;
5423 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5424 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5425 cfg_req.page_number = 0;
5426 cfg_req.page_address = 0;
5428 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5429 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5430 ioc_err(mrioc, "expander page0 header read failed\n");
5433 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5434 ioc_err(mrioc, "expander page0 header read failed with ioc_status(0x%04x)\n",
5438 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5439 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5440 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5441 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5442 cfg_req.page_address = cpu_to_le32(page_address);
5443 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5444 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg0, pg_sz)) {
5445 ioc_err(mrioc, "expander page0 read failed\n");
5454 * mpi3mr_cfg_get_sas_exp_pg1 - Read current SAS Expander page1
5455 * @mrioc: Adapter instance reference
5456 * @ioc_status: Pointer to return ioc status
5457 * @exp_pg1: Pointer to return SAS Expander page 1
5458 * @pg_sz: Size of the memory allocated to the page pointer
5459 * @form: The form to be used for addressing the page
5460 * @form_spec: Form specific information like phy number
5462 * This is handler for config page read for a specific SAS
5463 * Expander page1. The ioc_status has the controller returned
5464 * ioc_status. This routine doesn't check ioc_status to decide
5465 * whether the page read is success or not and it is the callers
5468 * Return: 0 on success, non-zero on failure.
5470 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5471 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form,
5474 struct mpi3_config_page_header cfg_hdr;
5475 struct mpi3_config_request cfg_req;
5478 memset(exp_pg1, 0, pg_sz);
5479 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5480 memset(&cfg_req, 0, sizeof(cfg_req));
5482 cfg_req.function = MPI3_FUNCTION_CONFIG;
5483 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5484 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5485 cfg_req.page_number = 1;
5486 cfg_req.page_address = 0;
5488 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5489 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5490 ioc_err(mrioc, "expander page1 header read failed\n");
5493 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5494 ioc_err(mrioc, "expander page1 header read failed with ioc_status(0x%04x)\n",
5498 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5499 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5500 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5501 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5502 cfg_req.page_address = cpu_to_le32(page_address);
5503 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5504 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg1, pg_sz)) {
5505 ioc_err(mrioc, "expander page1 read failed\n");
5514 * mpi3mr_cfg_get_enclosure_pg0 - Read current Enclosure page0
5515 * @mrioc: Adapter instance reference
5516 * @ioc_status: Pointer to return ioc status
5517 * @encl_pg0: Pointer to return Enclosure page 0
5518 * @pg_sz: Size of the memory allocated to the page pointer
5519 * @form: The form to be used for addressing the page
5520 * @form_spec: Form specific information like device handle
5522 * This is handler for config page read for a specific Enclosure
5523 * page0. The ioc_status has the controller returned ioc_status.
5524 * This routine doesn't check ioc_status to decide whether the
5525 * page read is success or not and it is the callers
5528 * Return: 0 on success, non-zero on failure.
5530 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5531 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form,
5534 struct mpi3_config_page_header cfg_hdr;
5535 struct mpi3_config_request cfg_req;
5538 memset(encl_pg0, 0, pg_sz);
5539 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5540 memset(&cfg_req, 0, sizeof(cfg_req));
5542 cfg_req.function = MPI3_FUNCTION_CONFIG;
5543 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5544 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_ENCLOSURE;
5545 cfg_req.page_number = 0;
5546 cfg_req.page_address = 0;
5548 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5549 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5550 ioc_err(mrioc, "enclosure page0 header read failed\n");
5553 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5554 ioc_err(mrioc, "enclosure page0 header read failed with ioc_status(0x%04x)\n",
5558 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5559 page_address = ((form & MPI3_ENCLOS_PGAD_FORM_MASK) |
5560 (form_spec & MPI3_ENCLOS_PGAD_HANDLE_MASK));
5561 cfg_req.page_address = cpu_to_le32(page_address);
5562 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5563 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, encl_pg0, pg_sz)) {
5564 ioc_err(mrioc, "enclosure page0 read failed\n");
5574 * mpi3mr_cfg_get_sas_io_unit_pg0 - Read current SASIOUnit page0
5575 * @mrioc: Adapter instance reference
5576 * @sas_io_unit_pg0: Pointer to return SAS IO Unit page 0
5577 * @pg_sz: Size of the memory allocated to the page pointer
5579 * This is handler for config page read for the SAS IO Unit
5580 * page0. This routine checks ioc_status to decide whether the
5581 * page read is success or not.
5583 * Return: 0 on success, non-zero on failure.
5585 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc,
5586 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz)
5588 struct mpi3_config_page_header cfg_hdr;
5589 struct mpi3_config_request cfg_req;
5592 memset(sas_io_unit_pg0, 0, pg_sz);
5593 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5594 memset(&cfg_req, 0, sizeof(cfg_req));
5596 cfg_req.function = MPI3_FUNCTION_CONFIG;
5597 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5598 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5599 cfg_req.page_number = 0;
5600 cfg_req.page_address = 0;
5602 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5603 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5604 ioc_err(mrioc, "sas io unit page0 header read failed\n");
5607 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5608 ioc_err(mrioc, "sas io unit page0 header read failed with ioc_status(0x%04x)\n",
5612 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5614 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5615 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg0, pg_sz)) {
5616 ioc_err(mrioc, "sas io unit page0 read failed\n");
5619 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5620 ioc_err(mrioc, "sas io unit page0 read failed with ioc_status(0x%04x)\n",
5630 * mpi3mr_cfg_get_sas_io_unit_pg1 - Read current SASIOUnit page1
5631 * @mrioc: Adapter instance reference
5632 * @sas_io_unit_pg1: Pointer to return SAS IO Unit page 1
5633 * @pg_sz: Size of the memory allocated to the page pointer
5635 * This is handler for config page read for the SAS IO Unit
5636 * page1. This routine checks ioc_status to decide whether the
5637 * page read is success or not.
5639 * Return: 0 on success, non-zero on failure.
5641 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
5642 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
5644 struct mpi3_config_page_header cfg_hdr;
5645 struct mpi3_config_request cfg_req;
5648 memset(sas_io_unit_pg1, 0, pg_sz);
5649 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5650 memset(&cfg_req, 0, sizeof(cfg_req));
5652 cfg_req.function = MPI3_FUNCTION_CONFIG;
5653 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5654 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5655 cfg_req.page_number = 1;
5656 cfg_req.page_address = 0;
5658 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5659 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5660 ioc_err(mrioc, "sas io unit page1 header read failed\n");
5663 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5664 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
5668 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5670 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5671 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5672 ioc_err(mrioc, "sas io unit page1 read failed\n");
5675 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5676 ioc_err(mrioc, "sas io unit page1 read failed with ioc_status(0x%04x)\n",
5686 * mpi3mr_cfg_set_sas_io_unit_pg1 - Write SASIOUnit page1
5687 * @mrioc: Adapter instance reference
5688 * @sas_io_unit_pg1: Pointer to the SAS IO Unit page 1 to write
5689 * @pg_sz: Size of the memory allocated to the page pointer
5691 * This is handler for config page write for the SAS IO Unit
5692 * page1. This routine checks ioc_status to decide whether the
5693 * page read is success or not. This will modify both current
5694 * and persistent page.
5696 * Return: 0 on success, non-zero on failure.
5698 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
5699 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
5701 struct mpi3_config_page_header cfg_hdr;
5702 struct mpi3_config_request cfg_req;
5705 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5706 memset(&cfg_req, 0, sizeof(cfg_req));
5708 cfg_req.function = MPI3_FUNCTION_CONFIG;
5709 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5710 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5711 cfg_req.page_number = 1;
5712 cfg_req.page_address = 0;
5714 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5715 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5716 ioc_err(mrioc, "sas io unit page1 header read failed\n");
5719 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5720 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
5724 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_CURRENT;
5726 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5727 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5728 ioc_err(mrioc, "sas io unit page1 write current failed\n");
5731 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5732 ioc_err(mrioc, "sas io unit page1 write current failed with ioc_status(0x%04x)\n",
5737 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_PERSISTENT;
5739 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5740 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5741 ioc_err(mrioc, "sas io unit page1 write persistent failed\n");
5744 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5745 ioc_err(mrioc, "sas io unit page1 write persistent failed with ioc_status(0x%04x)\n",
5755 * mpi3mr_cfg_get_driver_pg1 - Read current Driver page1
5756 * @mrioc: Adapter instance reference
5757 * @driver_pg1: Pointer to return Driver page 1
5758 * @pg_sz: Size of the memory allocated to the page pointer
5760 * This is handler for config page read for the Driver page1.
5761 * This routine checks ioc_status to decide whether the page
5762 * read is success or not.
5764 * Return: 0 on success, non-zero on failure.
5766 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc,
5767 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz)
5769 struct mpi3_config_page_header cfg_hdr;
5770 struct mpi3_config_request cfg_req;
5773 memset(driver_pg1, 0, pg_sz);
5774 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5775 memset(&cfg_req, 0, sizeof(cfg_req));
5777 cfg_req.function = MPI3_FUNCTION_CONFIG;
5778 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5779 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER;
5780 cfg_req.page_number = 1;
5781 cfg_req.page_address = 0;
5783 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5784 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5785 ioc_err(mrioc, "driver page1 header read failed\n");
5788 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5789 ioc_err(mrioc, "driver page1 header read failed with ioc_status(0x%04x)\n",
5793 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5795 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5796 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg1, pg_sz)) {
5797 ioc_err(mrioc, "driver page1 read failed\n");
5800 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5801 ioc_err(mrioc, "driver page1 read failed with ioc_status(0x%04x)\n",