1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Driver for Broadcom MPI3 Storage Controllers
5 * Copyright (C) 2017-2022 Broadcom Inc.
6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
10 #ifndef MPI3MR_H_INCLUDED
11 #define MPI3MR_H_INCLUDED
13 #include <linux/blkdev.h>
14 #include <linux/blk-mq.h>
15 #include <linux/blk-mq-pci.h>
16 #include <linux/delay.h>
17 #include <linux/dmapool.h>
18 #include <linux/errno.h>
19 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/miscdevice.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/poll.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/types.h>
30 #include <linux/uaccess.h>
31 #include <linux/utsname.h>
32 #include <linux/version.h>
33 #include <linux/workqueue.h>
34 #include <asm/unaligned.h>
35 #include <scsi/scsi.h>
36 #include <scsi/scsi_cmnd.h>
37 #include <scsi/scsi_dbg.h>
38 #include <scsi/scsi_device.h>
39 #include <scsi/scsi_host.h>
40 #include <scsi/scsi_tcq.h>
41 #include <uapi/scsi/scsi_bsg_mpi3mr.h>
43 #include "mpi/mpi30_transport.h"
44 #include "mpi/mpi30_cnfg.h"
45 #include "mpi/mpi30_image.h"
46 #include "mpi/mpi30_init.h"
47 #include "mpi/mpi30_ioc.h"
48 #include "mpi/mpi30_sas.h"
49 #include "mpi/mpi30_pci.h"
50 #include "mpi3mr_debug.h"
52 /* Global list and lock for storing multiple adapters managed by the driver */
53 extern spinlock_t mrioc_list_lock;
54 extern struct list_head mrioc_list;
56 extern atomic64_t event_counter;
58 #define MPI3MR_DRIVER_VERSION "8.0.0.69.0"
59 #define MPI3MR_DRIVER_RELDATE "16-March-2022"
61 #define MPI3MR_DRIVER_NAME "mpi3mr"
62 #define MPI3MR_DRIVER_LICENSE "GPL"
63 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>"
64 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver"
66 #define MPI3MR_NAME_LENGTH 32
67 #define IOCNAME "%s: "
69 #define MPI3MR_MAX_SECTORS 2048
71 /* Definitions for internal SGL and Chain SGL buffers */
72 #define MPI3MR_PAGE_SIZE_4K 4096
73 #define MPI3MR_SG_DEPTH (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common))
75 /* Definitions for MAX values for shost */
76 #define MPI3MR_MAX_CMDS_LUN 128
77 #define MPI3MR_MAX_CDB_LENGTH 32
79 /* Admin queue management definitions */
80 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K)
81 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K)
82 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128
83 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16
85 /* Operational queue management definitions */
86 #define MPI3MR_OP_REQ_Q_QD 512
87 #define MPI3MR_OP_REP_Q_QD 1024
88 #define MPI3MR_OP_REP_Q_QD4K 4096
89 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096
90 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096
91 #define MPI3MR_MAX_SEG_LIST_SIZE 4096
93 /* Reserved Host Tag definitions */
94 #define MPI3MR_HOSTTAG_INVALID 0xFFFF
95 #define MPI3MR_HOSTTAG_INITCMDS 1
96 #define MPI3MR_HOSTTAG_BSG_CMDS 2
97 #define MPI3MR_HOSTTAG_PEL_ABORT 3
98 #define MPI3MR_HOSTTAG_PEL_WAIT 4
99 #define MPI3MR_HOSTTAG_BLK_TMS 5
100 #define MPI3MR_HOSTTAG_CFG_CMDS 6
102 #define MPI3MR_NUM_DEVRMCMD 16
103 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_BLK_TMS + 1)
104 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \
105 MPI3MR_NUM_DEVRMCMD - 1)
107 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX
108 #define MPI3MR_NUM_EVTACKCMD 4
109 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1)
110 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \
111 MPI3MR_NUM_EVTACKCMD - 1)
113 /* Reduced resource count definition for crash kernel */
114 #define MPI3MR_HOST_IOS_KDUMP 128
116 /* command/controller interaction timeout definitions in seconds */
117 #define MPI3MR_INTADMCMD_TIMEOUT 60
118 #define MPI3MR_PORTENABLE_TIMEOUT 300
119 #define MPI3MR_ABORTTM_TIMEOUT 60
120 #define MPI3MR_RESETTM_TIMEOUT 60
121 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5
122 #define MPI3MR_TSUPDATE_INTERVAL 900
123 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120
124 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180
125 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180
126 #define MPI3MR_RESET_ACK_TIMEOUT 30
128 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */
130 #define MPI3MR_DEFAULT_CFG_PAGE_SZ 1024 /* in bytes */
132 #define MPI3MR_SCMD_TIMEOUT (60 * HZ)
133 #define MPI3MR_EH_SCMD_TIMEOUT (60 * HZ)
135 /* Internal admin command state definitions*/
136 #define MPI3MR_CMD_NOTUSED 0x8000
137 #define MPI3MR_CMD_COMPLETE 0x0001
138 #define MPI3MR_CMD_PENDING 0x0002
139 #define MPI3MR_CMD_REPLY_VALID 0x0004
140 #define MPI3MR_CMD_RESET 0x0008
142 /* Definitions for Event replies and sense buffer allocated per controller */
143 #define MPI3MR_NUM_EVT_REPLIES 64
144 #define MPI3MR_SENSE_BUF_SZ 256
145 #define MPI3MR_SENSEBUF_FACTOR 3
146 #define MPI3MR_CHAINBUF_FACTOR 3
147 #define MPI3MR_CHAINBUFDIX_FACTOR 2
149 /* Invalid target device handle */
150 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF
152 /* Controller Reset related definitions */
153 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5
154 #define MPI3MR_MAX_RESET_RETRY_COUNT 3
156 /* ResponseCode definitions */
157 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF)
158 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \
159 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC
161 #define MPI3MR_DEFAULT_MDTS (128 * 1024)
162 #define MPI3MR_DEFAULT_PGSZEXP (12)
164 /* Command retry count definitions */
165 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3
166 #define MPI3MR_PEL_RETRY_COUNT 3
168 /* Default target device queue depth */
169 #define MPI3MR_DEFAULT_SDEV_QD 32
171 /* Definitions for Threaded IRQ poll*/
172 #define MPI3MR_IRQ_POLL_SLEEP 2
173 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8
175 /* Definitions for the controller security status*/
176 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C
177 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02
179 #define MPI3MR_INVALID_DEVICE 0x00
180 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04
181 #define MPI3MR_HARD_SECURE_DEVICE 0x08
182 #define MPI3MR_TAMPERED_DEVICE 0x0C
184 /* SGE Flag definition */
185 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \
186 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \
187 MPI3_SGE_FLAGS_END_OF_LIST)
189 /* MSI Index from Reply Queue Index */
190 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset)
193 * Maximum data transfer size definitions for management
194 * application commands
196 #define MPI3MR_MAX_APP_XFER_SIZE (1 * 1024 * 1024)
197 #define MPI3MR_MAX_APP_XFER_SEGMENTS 512
199 * 2048 sectors are for data buffers and additional 512 sectors for
202 #define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512)
205 * struct mpi3mr_nvme_pt_sge - Structure to store SGEs for NVMe
206 * Encapsulated commands.
208 * @base_addr: Physical address
209 * @length: SGE length
212 * @sgl_type: sgl type
214 struct mpi3mr_nvme_pt_sge {
223 * struct mpi3mr_buf_map - local structure to
224 * track kernel and user buffers associated with an BSG
227 * @bsg_buf: BSG buffer virtual address
228 * @bsg_buf_len: BSG buffer length
229 * @kern_buf: Kernel buffer virtual address
230 * @kern_buf_len: Kernel buffer length
231 * @kern_buf_dma: Kernel buffer DMA address
232 * @data_dir: Data direction.
234 struct mpi3mr_buf_map {
239 dma_addr_t kern_buf_dma;
243 /* IOC State definitions */
244 enum mpi3mr_iocstate {
245 MRIOC_STATE_READY = 1,
248 MRIOC_STATE_BECOMING_READY,
249 MRIOC_STATE_RESET_REQUESTED,
250 MRIOC_STATE_UNRECOVERABLE,
253 /* Reset reason code definitions*/
254 enum mpi3mr_reset_reason {
255 MPI3MR_RESET_FROM_BRINGUP = 1,
256 MPI3MR_RESET_FROM_FAULT_WATCH = 2,
257 MPI3MR_RESET_FROM_APP = 3,
258 MPI3MR_RESET_FROM_EH_HOS = 4,
259 MPI3MR_RESET_FROM_TM_TIMEOUT = 5,
260 MPI3MR_RESET_FROM_APP_TIMEOUT = 6,
261 MPI3MR_RESET_FROM_MUR_FAILURE = 7,
262 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8,
263 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9,
264 MPI3MR_RESET_FROM_PE_TIMEOUT = 10,
265 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11,
266 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12,
267 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13,
268 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14,
269 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15,
270 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16,
271 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17,
272 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18,
273 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19,
274 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20,
275 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21,
276 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22,
277 MPI3MR_RESET_FROM_SYSFS = 23,
278 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24,
279 MPI3MR_RESET_FROM_FIRMWARE = 27,
280 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT = 29,
283 /* Queue type definitions */
285 MPI3MR_DEFAULT_QUEUE = 0,
290 * struct mpi3mr_compimg_ver - replica of component image
291 * version defined in mpi30_image.h in host endianness
294 struct mpi3mr_compimg_ver {
304 * struct mpi3mr_ioc_facs - replica of component image version
305 * defined in mpi30_ioc.h in host endianness
308 struct mpi3mr_ioc_facts {
309 u32 ioc_capabilities;
310 struct mpi3mr_compimg_ver fw_ver;
319 u16 max_sasexpanders;
320 u16 max_sasinitiators;
322 u16 max_pcie_switches;
332 u16 shutdown_timeout;
335 u16 max_msix_vectors;
343 u16 max_io_throttle_group;
344 u16 io_throttle_data_length;
346 u16 io_throttle_high;
351 * struct segments - memory descriptor structure to store
352 * virtual and dma addresses for operational queue segments.
354 * @segment: virtual address
355 * @segment_dma: dma address
359 dma_addr_t segment_dma;
363 * struct op_req_qinfo - Operational Request Queue Information
365 * @ci: consumer index
366 * @pi: producer index
367 * @num_request: Maximum number of entries in the queue
368 * @qid: Queue Id starting from 1
369 * @reply_qid: Associated reply queue Id
370 * @num_segments: Number of discontiguous memory segments
371 * @segment_qd: Depth of each segments
372 * @q_lock: Concurrent queue access lock
373 * @q_segments: Segment descriptor pointer
374 * @q_segment_list: Segment list base virtual address
375 * @q_segment_list_dma: Segment list base DMA address
377 struct op_req_qinfo {
386 struct segments *q_segments;
387 void *q_segment_list;
388 dma_addr_t q_segment_list_dma;
392 * struct op_reply_qinfo - Operational Reply Queue Information
394 * @ci: consumer index
395 * @qid: Queue Id starting from 1
396 * @num_replies: Maximum number of entries in the queue
397 * @num_segments: Number of discontiguous memory segments
398 * @segment_qd: Depth of each segments
399 * @q_segments: Segment descriptor pointer
400 * @q_segment_list: Segment list base virtual address
401 * @q_segment_list_dma: Segment list base DMA address
402 * @ephase: Expected phased identifier for the reply queue
403 * @pend_ios: Number of IOs pending in HW for this queue
404 * @enable_irq_poll: Flag to indicate polling is enabled
405 * @in_use: Queue is handled by poll/ISR
406 * @qtype: Type of queue (types defined in enum queue_type)
408 struct op_reply_qinfo {
414 struct segments *q_segments;
415 void *q_segment_list;
416 dma_addr_t q_segment_list_dma;
419 bool enable_irq_poll;
421 enum queue_type qtype;
425 * struct mpi3mr_intr_info - Interrupt cookie information
427 * @mrioc: Adapter instance reference
428 * @msix_index: MSIx index
429 * @op_reply_q: Associated operational reply queue
430 * @name: Dev name for the irq claiming device
432 struct mpi3mr_intr_info {
433 struct mpi3mr_ioc *mrioc;
435 struct op_reply_qinfo *op_reply_q;
436 char name[MPI3MR_NAME_LENGTH];
440 * struct mpi3mr_throttle_group_info - Throttle group info
442 * @io_divert: Flag indicates io divert is on or off for the TG
443 * @need_qd_reduction: Flag to indicate QD reduction is needed
444 * @qd_reduction: Queue Depth reduction in units of 10%
445 * @fw_qd: QueueDepth value reported by the firmware
446 * @modified_qd: Modified QueueDepth value due to throttling
447 * @id: Throttle Group ID.
448 * @high: High limit to turn on throttling in 512 byte blocks
449 * @low: Low limit to turn off throttling in 512 byte blocks
450 * @pend_large_data_sz: Counter to track pending large data
452 struct mpi3mr_throttle_group_info {
454 u8 need_qd_reduction;
461 atomic_t pend_large_data_sz;
465 * struct mpi3mr_enclosure_node - enclosure information
466 * @list: List of enclosures
467 * @pg0: Enclosure page 0;
469 struct mpi3mr_enclosure_node {
470 struct list_head list;
471 struct mpi3_enclosure_page0 pg0;
475 * struct tgt_dev_sas_sata - SAS/SATA device specific
476 * information cached from firmware given data
478 * @sas_address: World wide unique SAS address
479 * @dev_info: Device information bits
481 struct tgt_dev_sas_sata {
487 * struct tgt_dev_pcie - PCIe device specific information cached
488 * from firmware given data
490 * @mdts: Maximum data transfer size
491 * @capb: Device capabilities
492 * @pgsz: Device page size
493 * @abort_to: Timeout for abort TM
494 * @reset_to: Timeout for Target/LUN reset TM
495 * @dev_info: Device information bits
497 struct tgt_dev_pcie {
507 * struct tgt_dev_vd - virtual device specific information
508 * cached from firmware given data
510 * @state: State of the VD
511 * @tg_qd_reduction: Queue Depth reduction in units of 10%
512 * @tg_id: VDs throttle group ID
513 * @high: High limit to turn on throttling in 512 byte blocks
514 * @low: Low limit to turn off throttling in 512 byte blocks
515 * @tg: Pointer to throttle group info
523 struct mpi3mr_throttle_group_info *tg;
528 * union _form_spec_inf - union of device specific information
530 union _form_spec_inf {
531 struct tgt_dev_sas_sata sas_sata_inf;
532 struct tgt_dev_pcie pcie_inf;
533 struct tgt_dev_vd vd_inf;
539 * struct mpi3mr_tgt_dev - target device data structure
541 * @list: List pointer
542 * @starget: Scsi_target pointer
543 * @dev_handle: FW device handle
544 * @parent_handle: FW parent device handle
546 * @encl_handle: FW enclosure handle
547 * @perst_id: FW assigned Persistent ID
548 * @devpg0_flag: Device Page0 flag
549 * @dev_type: SAS/SATA/PCIE device type
550 * @is_hidden: Should be exposed to upper layers or not
551 * @host_exposed: Already exposed to host or not
552 * @io_throttle_enabled: I/O throttling needed or not
553 * @q_depth: Device specific Queue Depth
554 * @wwid: World wide ID
555 * @enclosure_logical_id: Enclosure logical identifier
556 * @dev_spec: Device type specific information
557 * @ref_count: Reference count
559 struct mpi3mr_tgt_dev {
560 struct list_head list;
561 struct scsi_target *starget;
571 u8 io_throttle_enabled;
574 u64 enclosure_logical_id;
575 union _form_spec_inf dev_spec;
576 struct kref ref_count;
580 * mpi3mr_tgtdev_get - k reference incrementor
581 * @s: Target device reference
583 * Increment target device reference count.
585 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s)
587 kref_get(&s->ref_count);
591 * mpi3mr_free_tgtdev - target device memory dealloctor
592 * @r: k reference pointer of the target device
594 * Free target device memory when no reference.
596 static inline void mpi3mr_free_tgtdev(struct kref *r)
598 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count));
602 * mpi3mr_tgtdev_put - k reference decrementor
603 * @s: Target device reference
605 * Decrement target device reference count.
607 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s)
609 kref_put(&s->ref_count, mpi3mr_free_tgtdev);
614 * struct mpi3mr_stgt_priv_data - SCSI target private structure
616 * @starget: Scsi_target pointer
617 * @dev_handle: FW device handle
618 * @perst_id: FW assigned Persistent ID
619 * @num_luns: Number of Logical Units
620 * @block_io: I/O blocked to the device or not
621 * @dev_removed: Device removed in the Firmware
622 * @dev_removedelay: Device is waiting to be removed in FW
623 * @dev_type: Device type
624 * @io_throttle_enabled: I/O throttling needed or not
625 * @io_divert: Flag indicates io divert is on or off for the dev
626 * @throttle_group: Pointer to throttle group info
627 * @tgt_dev: Internal target device pointer
628 * @pend_count: Counter to track pending I/Os during error
631 struct mpi3mr_stgt_priv_data {
632 struct scsi_target *starget;
640 u8 io_throttle_enabled;
642 struct mpi3mr_throttle_group_info *throttle_group;
643 struct mpi3mr_tgt_dev *tgt_dev;
648 * struct mpi3mr_stgt_priv_data - SCSI device private structure
650 * @tgt_priv_data: Scsi_target private data pointer
651 * @lun_id: LUN ID of the device
652 * @ncq_prio_enable: NCQ priority enable for SATA device
653 * @pend_count: Counter to track pending I/Os during error
656 struct mpi3mr_sdev_priv_data {
657 struct mpi3mr_stgt_priv_data *tgt_priv_data;
664 * struct mpi3mr_drv_cmd - Internal command tracker
666 * @mutex: Command mutex
667 * @done: Completeor for wakeup
668 * @reply: Firmware reply for internal commands
669 * @sensebuf: Sensebuf for SCSI IO commands
670 * @iou_rc: IO Unit control reason code
671 * @state: Command State
672 * @dev_handle: Firmware handle for device specific commands
673 * @ioc_status: IOC status from the firmware
674 * @ioc_loginfo:IOC log info from the firmware
675 * @is_waiting: Is the command issued in block mode
676 * @is_sense: Is Sense data present
677 * @retry_count: Retry count for retriable commands
678 * @host_tag: Host tag used by the command
679 * @callback: Callback for non blocking commands
681 struct mpi3mr_drv_cmd {
683 struct completion done;
696 void (*callback)(struct mpi3mr_ioc *mrioc,
697 struct mpi3mr_drv_cmd *drv_cmd);
701 * struct dma_memory_desc - memory descriptor structure to store
702 * virtual address, dma address and size for any generic dma
703 * memory allocations in the driver.
706 * @addr: virtual address
707 * @dma_addr: dma address
709 struct dma_memory_desc {
717 * struct chain_element - memory descriptor structure to store
718 * virtual and dma addresses for chain elements.
720 * @addr: virtual address
721 * @dma_addr: dma address
723 struct chain_element {
729 * struct scmd_priv - SCSI command private data
731 * @host_tag: Host tag specific to operational queue
732 * @in_lld_scope: Command in LLD scope or not
733 * @meta_sg_valid: DIX command with meta data SGL or not
734 * @scmd: SCSI Command pointer
735 * @req_q_idx: Operational request queue index
736 * @chain_idx: Chain frame index
737 * @meta_chain_idx: Chain frame index of meta data SGL
738 * @mpi3mr_scsiio_req: MPI SCSI IO request
744 struct scsi_cmnd *scmd;
748 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ];
752 * struct mpi3mr_ioc - Adapter anchor structure stored in shost
755 * @list: List pointer
756 * @pdev: PCI device pointer
757 * @shost: Scsi_Host pointer
759 * @cpu_count: Number of online CPUs
760 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll
761 * @name: Controller ASCII name
762 * @driver_name: Driver ASCII name
763 * @sysif_regs: System interface registers virtual address
764 * @sysif_regs_phys: System interface registers physical address
766 * @dma_mask: DMA mask
767 * @msix_count: Number of MSIX vectors used
768 * @intr_enabled: Is interrupts enabled
769 * @num_admin_req: Number of admin requests
770 * @admin_req_q_sz: Admin request queue size
771 * @admin_req_pi: Admin request queue producer index
772 * @admin_req_ci: Admin request queue consumer index
773 * @admin_req_base: Admin request queue base virtual address
774 * @admin_req_dma: Admin request queue base dma address
775 * @admin_req_lock: Admin queue access lock
776 * @num_admin_replies: Number of admin replies
777 * @admin_reply_q_sz: Admin reply queue size
778 * @admin_reply_ci: Admin reply queue consumer index
779 * @admin_reply_ephase:Admin reply queue expected phase
780 * @admin_reply_base: Admin reply queue base virtual address
781 * @admin_reply_dma: Admin reply queue base dma address
782 * @ready_timeout: Controller ready timeout
783 * @intr_info: Interrupt cookie pointer
784 * @intr_info_count: Number of interrupt cookies
785 * @is_intr_info_set: Flag to indicate intr info is setup
786 * @num_queues: Number of operational queues
787 * @num_op_req_q: Number of operational request queues
788 * @req_qinfo: Operational request queue info pointer
789 * @num_op_reply_q: Number of operational reply queues
790 * @op_reply_qinfo: Operational reply queue info pointer
791 * @init_cmds: Command tracker for initialization commands
792 * @cfg_cmds: Command tracker for configuration requests
793 * @facts: Cached IOC facts data
794 * @op_reply_desc_sz: Operational reply descriptor size
795 * @num_reply_bufs: Number of reply buffers allocated
796 * @reply_buf_pool: Reply buffer pool
797 * @reply_buf: Reply buffer base virtual address
798 * @reply_buf_dma: Reply buffer DMA address
799 * @reply_buf_dma_max_address: Reply DMA address max limit
800 * @reply_free_qsz: Reply free queue size
801 * @reply_free_q_pool: Reply free queue pool
802 * @reply_free_q: Reply free queue base virtual address
803 * @reply_free_q_dma: Reply free queue base DMA address
804 * @reply_free_queue_lock: Reply free queue lock
805 * @reply_free_queue_host_index: Reply free queue host index
806 * @num_sense_bufs: Number of sense buffers
807 * @sense_buf_pool: Sense buffer pool
808 * @sense_buf: Sense buffer base virtual address
809 * @sense_buf_dma: Sense buffer base DMA address
810 * @sense_buf_q_sz: Sense buffer queue size
811 * @sense_buf_q_pool: Sense buffer queue pool
812 * @sense_buf_q: Sense buffer queue virtual address
813 * @sense_buf_q_dma: Sense buffer queue DMA address
814 * @sbq_lock: Sense buffer queue lock
815 * @sbq_host_index: Sense buffer queuehost index
816 * @event_masks: Event mask bitmap
817 * @fwevt_worker_name: Firmware event worker thread name
818 * @fwevt_worker_thread: Firmware event worker thread
819 * @fwevt_lock: Firmware event lock
820 * @fwevt_list: Firmware event list
821 * @watchdog_work_q_name: Fault watchdog worker thread name
822 * @watchdog_work_q: Fault watchdog worker thread
823 * @watchdog_work: Fault watchdog work
824 * @watchdog_lock: Fault watchdog lock
825 * @is_driver_loading: Is driver still loading
826 * @scan_started: Async scan started
827 * @scan_failed: Asycn scan failed
828 * @stop_drv_processing: Stop all command processing
829 * @max_host_ios: Maximum host I/O count
830 * @chain_buf_count: Chain buffer count
831 * @chain_buf_pool: Chain buffer pool
832 * @chain_sgl_list: Chain SGL list
833 * @chain_bitmap_sz: Chain buffer allocator bitmap size
834 * @chain_bitmap: Chain buffer allocator bitmap
835 * @chain_buf_lock: Chain buffer list lock
836 * @bsg_cmds: Command tracker for BSG command
837 * @host_tm_cmds: Command tracker for task management commands
838 * @dev_rmhs_cmds: Command tracker for device removal commands
839 * @evtack_cmds: Command tracker for event ack commands
840 * @devrem_bitmap_sz: Device removal bitmap size
841 * @devrem_bitmap: Device removal bitmap
842 * @dev_handle_bitmap_sz: Device handle bitmap size
843 * @removepend_bitmap: Remove pending bitmap
844 * @delayed_rmhs_list: Delayed device removal list
845 * @evtack_cmds_bitmap_sz: Event Ack bitmap size
846 * @evtack_cmds_bitmap: Event Ack bitmap
847 * @delayed_evtack_cmds_list: Delayed event acknowledgment list
848 * @ts_update_counter: Timestamp update counter
849 * @reset_in_progress: Reset in progress flag
850 * @unrecoverable: Controller unrecoverable flag
851 * @prev_reset_result: Result of previous reset
852 * @reset_mutex: Controller reset mutex
853 * @reset_waitq: Controller reset wait queue
854 * @prepare_for_reset: Prepare for reset event received
855 * @prepare_for_reset_timeout_counter: Prepare for reset timeout
856 * @prp_list_virt: NVMe encapsulated PRP list virtual base
857 * @prp_list_dma: NVMe encapsulated PRP list DMA
858 * @prp_sz: NVME encapsulated PRP list size
859 * @diagsave_timeout: Diagnostic information save timeout
860 * @logging_level: Controller debug logging level
861 * @flush_io_count: I/O count to flush after reset
862 * @current_event: Firmware event currently in process
863 * @driver_info: Driver, Kernel, OS information to firmware
864 * @change_count: Topology change count
865 * @pel_enabled: Persistent Event Log(PEL) enabled or not
866 * @pel_abort_requested: PEL abort is requested or not
867 * @pel_class: PEL Class identifier
868 * @pel_locale: PEL Locale identifier
869 * @pel_cmds: Command tracker for PEL wait command
870 * @pel_abort_cmd: Command tracker for PEL abort command
871 * @pel_newest_seqnum: Newest PEL sequenece number
872 * @pel_seqnum_virt: PEL sequence number virtual address
873 * @pel_seqnum_dma: PEL sequence number DMA address
874 * @pel_seqnum_sz: PEL sequenece number size
875 * @op_reply_q_offset: Operational reply queue offset with MSIx
876 * @default_qcount: Total Default queues
877 * @active_poll_qcount: Currently active poll queue count
878 * @requested_poll_qcount: User requested poll queue count
879 * @bsg_dev: BSG device structure
880 * @bsg_queue: Request queue for BSG device
881 * @stop_bsgs: Stop BSG request flag
882 * @logdata_buf: Circular buffer to store log data entries
883 * @logdata_buf_idx: Index of entry in buffer to store
884 * @logdata_entry_sz: log data entry size
885 * @pend_large_data_sz: Counter to track pending large data
886 * @io_throttle_data_length: I/O size to track in 512b blocks
887 * @io_throttle_high: I/O size to start throttle in 512b blocks
888 * @io_throttle_low: I/O size to stop throttle in 512b blocks
889 * @num_io_throttle_group: Maximum number of throttle groups
890 * @throttle_groups: Pointer to throttle group info structures
891 * @cfg_page: Default memory for configuration pages
892 * @cfg_page_dma: Configuration page DMA address
893 * @cfg_page_sz: Default configuration page memory size
894 * @enclosure_list: List of Enclosure objects
897 struct list_head list;
898 struct pci_dev *pdev;
899 struct Scsi_Host *shost;
902 bool enable_segqueue;
905 char name[MPI3MR_NAME_LENGTH];
906 char driver_name[MPI3MR_NAME_LENGTH];
908 volatile struct mpi3_sysif_registers __iomem *sysif_regs;
909 resource_size_t sysif_regs_phys;
920 void *admin_req_base;
921 dma_addr_t admin_req_dma;
922 spinlock_t admin_req_lock;
924 u16 num_admin_replies;
925 u32 admin_reply_q_sz;
927 u8 admin_reply_ephase;
928 void *admin_reply_base;
929 dma_addr_t admin_reply_dma;
933 struct mpi3mr_intr_info *intr_info;
935 bool is_intr_info_set;
939 struct op_req_qinfo *req_qinfo;
942 struct op_reply_qinfo *op_reply_qinfo;
944 struct mpi3mr_drv_cmd init_cmds;
945 struct mpi3mr_drv_cmd cfg_cmds;
946 struct mpi3mr_ioc_facts facts;
947 u16 op_reply_desc_sz;
950 struct dma_pool *reply_buf_pool;
952 dma_addr_t reply_buf_dma;
953 dma_addr_t reply_buf_dma_max_address;
957 struct dma_pool *reply_free_q_pool;
958 __le64 *reply_free_q;
959 dma_addr_t reply_free_q_dma;
960 spinlock_t reply_free_queue_lock;
961 u32 reply_free_queue_host_index;
964 struct dma_pool *sense_buf_pool;
966 dma_addr_t sense_buf_dma;
969 struct dma_pool *sense_buf_q_pool;
971 dma_addr_t sense_buf_q_dma;
974 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS];
976 char fwevt_worker_name[MPI3MR_NAME_LENGTH];
977 struct workqueue_struct *fwevt_worker_thread;
978 spinlock_t fwevt_lock;
979 struct list_head fwevt_list;
981 char watchdog_work_q_name[20];
982 struct workqueue_struct *watchdog_work_q;
983 struct delayed_work watchdog_work;
984 spinlock_t watchdog_lock;
986 u8 is_driver_loading;
989 u8 stop_drv_processing;
992 spinlock_t tgtdev_lock;
993 struct list_head tgtdev_list;
996 struct dma_pool *chain_buf_pool;
997 struct chain_element *chain_sgl_list;
1000 spinlock_t chain_buf_lock;
1002 struct mpi3mr_drv_cmd bsg_cmds;
1003 struct mpi3mr_drv_cmd host_tm_cmds;
1004 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD];
1005 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD];
1006 u16 devrem_bitmap_sz;
1007 void *devrem_bitmap;
1008 u16 dev_handle_bitmap_sz;
1009 void *removepend_bitmap;
1010 struct list_head delayed_rmhs_list;
1011 u16 evtack_cmds_bitmap_sz;
1012 void *evtack_cmds_bitmap;
1013 struct list_head delayed_evtack_cmds_list;
1015 u32 ts_update_counter;
1016 u8 reset_in_progress;
1018 int prev_reset_result;
1019 struct mutex reset_mutex;
1020 wait_queue_head_t reset_waitq;
1022 u8 prepare_for_reset;
1023 u16 prepare_for_reset_timeout_counter;
1025 void *prp_list_virt;
1026 dma_addr_t prp_list_dma;
1029 u16 diagsave_timeout;
1033 struct mpi3mr_fwevt *current_event;
1034 struct mpi3_driver_info_layout driver_info;
1038 u8 pel_abort_requested;
1041 struct mpi3mr_drv_cmd pel_cmds;
1042 struct mpi3mr_drv_cmd pel_abort_cmd;
1044 u32 pel_newest_seqnum;
1045 void *pel_seqnum_virt;
1046 dma_addr_t pel_seqnum_dma;
1049 u16 op_reply_q_offset;
1051 u16 active_poll_qcount;
1052 u16 requested_poll_qcount;
1054 struct device bsg_dev;
1055 struct request_queue *bsg_queue;
1058 u16 logdata_buf_idx;
1059 u16 logdata_entry_sz;
1061 atomic_t pend_large_data_sz;
1062 u32 io_throttle_data_length;
1063 u32 io_throttle_high;
1064 u32 io_throttle_low;
1065 u16 num_io_throttle_group;
1066 struct mpi3mr_throttle_group_info *throttle_groups;
1069 dma_addr_t cfg_page_dma;
1072 struct list_head enclosure_list;
1076 * struct mpi3mr_fwevt - Firmware event structure.
1079 * @work: Work structure
1080 * @mrioc: Adapter instance reference
1081 * @event_id: MPI3 firmware event ID
1082 * @send_ack: Event acknowledgment required or not
1083 * @process_evt: Bottomhalf processing required or not
1084 * @evt_ctx: Event context to send in Ack
1085 * @event_data_size: size of the event data in bytes
1086 * @pending_at_sml: waiting for device add/remove API to complete
1087 * @discard: discard this event
1088 * @ref_count: kref count
1089 * @event_data: Actual MPI3 event data
1091 struct mpi3mr_fwevt {
1092 struct list_head list;
1093 struct work_struct work;
1094 struct mpi3mr_ioc *mrioc;
1099 u16 event_data_size;
1100 bool pending_at_sml;
1102 struct kref ref_count;
1103 char event_data[] __aligned(4);
1108 * struct delayed_dev_rmhs_node - Delayed device removal node
1111 * @handle: Device handle
1112 * @iou_rc: IO Unit Control Reason Code
1114 struct delayed_dev_rmhs_node {
1115 struct list_head list;
1121 * struct delayed_evt_ack_node - Delayed event ack node
1123 * @event: MPI3 event ID
1124 * @event_ctx: event context
1126 struct delayed_evt_ack_node {
1127 struct list_head list;
1132 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc);
1133 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc);
1134 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc);
1135 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume);
1136 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc);
1137 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async);
1138 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1139 u16 admin_req_sz, u8 ignore_reset);
1140 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
1141 struct op_req_qinfo *opreqq, u8 *req);
1142 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
1143 dma_addr_t dma_addr);
1144 void mpi3mr_build_zero_len_sge(void *paddr);
1145 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
1146 dma_addr_t phys_addr);
1147 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
1148 dma_addr_t phys_addr);
1149 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
1152 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc);
1153 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc);
1154 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc,
1155 struct mpi3_event_notification_reply *event_reply);
1156 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc,
1157 struct mpi3_default_reply_descriptor *reply_desc,
1158 u64 *reply_dma, u16 qidx);
1159 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc);
1160 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc);
1162 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
1163 u32 reset_reason, u8 snapdump);
1164 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc);
1165 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc);
1167 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc);
1168 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
1171 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout);
1172 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc);
1173 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc);
1174 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc);
1175 void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc);
1176 void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc);
1177 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
1178 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc);
1179 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
1180 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
1181 struct op_reply_qinfo *op_reply_q);
1182 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num);
1183 void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc);
1184 void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc);
1185 int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type,
1186 u16 handle, uint lun, u16 htag, ulong timeout,
1187 struct mpi3mr_drv_cmd *drv_cmd,
1188 u8 *resp_code, struct scsi_cmnd *scmd);
1189 struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle(
1190 struct mpi3mr_ioc *mrioc, u16 handle);
1191 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
1192 struct mpi3mr_drv_cmd *drv_cmd);
1193 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,
1194 struct mpi3mr_drv_cmd *drv_cmd);
1195 void mpi3mr_app_save_logdata(struct mpi3mr_ioc *mrioc, char *event_data,
1196 u16 event_data_size);
1197 struct mpi3mr_enclosure_node *mpi3mr_enclosure_find_by_handle(
1198 struct mpi3mr_ioc *mrioc, u16 handle);
1199 extern const struct attribute_group *mpi3mr_host_groups[];
1200 extern const struct attribute_group *mpi3mr_dev_groups[];
1202 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1203 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec);
1204 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1205 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form,
1207 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1208 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form,
1210 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1211 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form,
1213 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1214 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form,
1216 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1217 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form,
1219 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc,
1220 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz);
1221 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
1222 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz);
1223 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
1224 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz);
1225 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc,
1226 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz);
1227 #endif /*MPI3MR_H_INCLUDED*/