drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  *  Copyright 2017-2021 Broadcom Inc. All rights reserved.
   4  *
   5  */
   6 #ifndef MPI30_CNFG_H
   7 #define MPI30_CNFG_H     1
   8 #define MPI3_CONFIG_PAGETYPE_IO_UNIT                    (0x00)
   9 #define MPI3_CONFIG_PAGETYPE_MANUFACTURING              (0x01)
  10 #define MPI3_CONFIG_PAGETYPE_IOC                        (0x02)
  11 #define MPI3_CONFIG_PAGETYPE_DRIVER                     (0x03)
  12 #define MPI3_CONFIG_PAGETYPE_SECURITY                   (0x04)
  13 #define MPI3_CONFIG_PAGETYPE_ENCLOSURE                  (0x11)
  14 #define MPI3_CONFIG_PAGETYPE_DEVICE                     (0x12)
  15 #define MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT                (0x20)
  16 #define MPI3_CONFIG_PAGETYPE_SAS_EXPANDER               (0x21)
  17 #define MPI3_CONFIG_PAGETYPE_SAS_PHY                    (0x23)
  18 #define MPI3_CONFIG_PAGETYPE_SAS_PORT                   (0x24)
  19 #define MPI3_CONFIG_PAGETYPE_PCIE_IO_UNIT               (0x30)
  20 #define MPI3_CONFIG_PAGETYPE_PCIE_SWITCH                (0x31)
  21 #define MPI3_CONFIG_PAGETYPE_PCIE_LINK                  (0x33)
  22 #define MPI3_CONFIG_PAGEATTR_MASK                       (0xf0)
  23 #define MPI3_CONFIG_PAGEATTR_READ_ONLY                  (0x00)
  24 #define MPI3_CONFIG_PAGEATTR_CHANGEABLE                 (0x10)
  25 #define MPI3_CONFIG_PAGEATTR_PERSISTENT                 (0x20)
  26 #define MPI3_CONFIG_ACTION_PAGE_HEADER                  (0x00)
  27 #define MPI3_CONFIG_ACTION_READ_DEFAULT                 (0x01)
  28 #define MPI3_CONFIG_ACTION_READ_CURRENT                 (0x02)
  29 #define MPI3_CONFIG_ACTION_WRITE_CURRENT                (0x03)
  30 #define MPI3_CONFIG_ACTION_READ_PERSISTENT              (0x04)
  31 #define MPI3_CONFIG_ACTION_WRITE_PERSISTENT             (0x05)
  32 #define MPI3_DEVICE_PGAD_FORM_MASK                      (0xf0000000)
  33 #define MPI3_DEVICE_PGAD_FORM_GET_NEXT_HANDLE           (0x00000000)
  34 #define MPI3_DEVICE_PGAD_FORM_HANDLE                    (0x20000000)
  35 #define MPI3_DEVICE_PGAD_HANDLE_MASK                    (0x0000ffff)
  36 #define MPI3_SAS_EXPAND_PGAD_FORM_MASK                  (0xf0000000)
  37 #define MPI3_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE       (0x00000000)
  38 #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM        (0x10000000)
  39 #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE                (0x20000000)
  40 #define MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK                (0x00ff0000)
  41 #define MPI3_SAS_EXPAND_PGAD_PHYNUM_SHIFT               (16)
  42 #define MPI3_SAS_EXPAND_PGAD_HANDLE_MASK                (0x0000ffff)
  43 #define MPI3_SAS_PHY_PGAD_FORM_MASK                     (0xf0000000)
  44 #define MPI3_SAS_PHY_PGAD_FORM_PHY_NUMBER               (0x00000000)
  45 #define MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK               (0x000000ff)
  46 #define MPI3_SASPORT_PGAD_FORM_MASK                     (0xf0000000)
  47 #define MPI3_SASPORT_PGAD_FORM_GET_NEXT_PORT            (0x00000000)
  48 #define MPI3_SASPORT_PGAD_FORM_PORT_NUM                 (0x10000000)
  49 #define MPI3_SASPORT_PGAD_PORT_NUMBER_MASK              (0x000000ff)
  50 #define MPI3_ENCLOS_PGAD_FORM_MASK                      (0xf0000000)
  51 #define MPI3_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE           (0x00000000)
  52 #define MPI3_ENCLOS_PGAD_FORM_HANDLE                    (0x10000000)
  53 #define MPI3_ENCLOS_PGAD_HANDLE_MASK                    (0x0000ffff)
  54 #define MPI3_PCIE_SWITCH_PGAD_FORM_MASK                 (0xf0000000)
  55 #define MPI3_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HANDLE      (0x00000000)
  56 #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE_PORT_NUM      (0x10000000)
  57 #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE               (0x20000000)
  58 #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_MASK              (0x00ff0000)
  59 #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_SHIFT             (16)
  60 #define MPI3_PCIE_SWITCH_PGAD_HANDLE_MASK               (0x0000ffff)
  61 #define MPI3_PCIE_LINK_PGAD_FORM_MASK                   (0xf0000000)
  62 #define MPI3_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK          (0x00000000)
  63 #define MPI3_PCIE_LINK_PGAD_FORM_LINK_NUM               (0x10000000)
  64 #define MPI3_PCIE_LINK_PGAD_LINKNUM_MASK                (0x000000ff)
  65 #define MPI3_SECURITY_PGAD_FORM_MASK                    (0xf0000000)
  66 #define MPI3_SECURITY_PGAD_FORM_GET_NEXT_SLOT           (0x00000000)
  67 #define MPI3_SECURITY_PGAD_FORM_SOT_NUM                 (0x10000000)
  68 #define MPI3_SECURITY_PGAD_SLOT_GROUP_MASK              (0x0000ff00)
  69 #define MPI3_SECURITY_PGAD_SLOT_MASK                    (0x000000ff)
  70 struct mpi3_config_request {
  71         __le16             host_tag;
  72         u8                 ioc_use_only02;
  73         u8                 function;
  74         __le16             ioc_use_only04;
  75         u8                 ioc_use_only06;
  76         u8                 msg_flags;
  77         __le16             change_count;
  78         __le16             reserved0a;
  79         u8                 page_version;
  80         u8                 page_number;
  81         u8                 page_type;
  82         u8                 action;
  83         __le32             page_address;
  84         __le16             page_length;
  85         __le16             reserved16;
  86         __le32             reserved18[2];
  87         union mpi3_sge_union  sgl;
  88 };
  89
  90 struct mpi3_config_page_header {
  91         u8                 page_version;
  92         u8                 reserved01;
  93         u8                 page_number;
  94         u8                 page_attribute;
  95         __le16             page_length;
  96         u8                 page_type;
  97         u8                 reserved07;
  98 };
  99
 100 #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_MASK             (0xf0)
 101 #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_SHIFT            (4)
 102 #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_MASK            (0x0f)
 103 #define MPI3_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE        (0x00)
 104 #define MPI3_SAS_NEG_LINK_RATE_PHY_DISABLED             (0x01)
 105 #define MPI3_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED       (0x02)
 106 #define MPI3_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE        (0x03)
 107 #define MPI3_SAS_NEG_LINK_RATE_PORT_SELECTOR            (0x04)
 108 #define MPI3_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS    (0x05)
 109 #define MPI3_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY          (0x06)
 110 #define MPI3_SAS_NEG_LINK_RATE_1_5                      (0x08)
 111 #define MPI3_SAS_NEG_LINK_RATE_3_0                      (0x09)
 112 #define MPI3_SAS_NEG_LINK_RATE_6_0                      (0x0a)
 113 #define MPI3_SAS_NEG_LINK_RATE_12_0                     (0x0b)
 114 #define MPI3_SAS_NEG_LINK_RATE_22_5                     (0x0c)
 115 #define MPI3_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT       (0x00000040)
 116 #define MPI3_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS        (0x00000020)
 117 #define MPI3_SAS_APHYINFO_BREAK_REPLY_CAPABLE           (0x00000010)
 118 #define MPI3_SAS_APHYINFO_REASON_MASK                   (0x0000000f)
 119 #define MPI3_SAS_APHYINFO_REASON_UNKNOWN                (0x00000000)
 120 #define MPI3_SAS_APHYINFO_REASON_POWER_ON               (0x00000001)
 121 #define MPI3_SAS_APHYINFO_REASON_HARD_RESET             (0x00000002)
 122 #define MPI3_SAS_APHYINFO_REASON_SMP_PHY_CONTROL        (0x00000003)
 123 #define MPI3_SAS_APHYINFO_REASON_LOSS_OF_SYNC           (0x00000004)
 124 #define MPI3_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ       (0x00000005)
 125 #define MPI3_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER    (0x00000006)
 126 #define MPI3_SAS_APHYINFO_REASON_BREAK_TIMEOUT          (0x00000007)
 127 #define MPI3_SAS_APHYINFO_REASON_PHY_TEST_STOPPED       (0x00000008)
 128 #define MPI3_SAS_APHYINFO_REASON_EXP_REDUCED_FUNC       (0x00000009)
 129 #define MPI3_SAS_PHYINFO_STATUS_MASK                    (0xc0000000)
 130 #define MPI3_SAS_PHYINFO_STATUS_SHIFT                   (30)
 131 #define MPI3_SAS_PHYINFO_STATUS_ACCESSIBLE              (0x00000000)
 132 #define MPI3_SAS_PHYINFO_STATUS_NOT_EXIST               (0x40000000)
 133 #define MPI3_SAS_PHYINFO_STATUS_VACANT                  (0x80000000)
 134 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_MASK       (0x18000000)
 135 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_ACTIVE     (0x00000000)
 136 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_PARTIAL    (0x08000000)
 137 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SLUMBER    (0x10000000)
 138 #define MPI3_SAS_PHYINFO_REASON_MASK                    (0x000f0000)
 139 #define MPI3_SAS_PHYINFO_REASON_UNKNOWN                 (0x00000000)
 140 #define MPI3_SAS_PHYINFO_REASON_POWER_ON                (0x00010000)
 141 #define MPI3_SAS_PHYINFO_REASON_HARD_RESET              (0x00020000)
 142 #define MPI3_SAS_PHYINFO_REASON_SMP_PHY_CONTROL         (0x00030000)
 143 #define MPI3_SAS_PHYINFO_REASON_LOSS_OF_SYNC            (0x00040000)
 144 #define MPI3_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ        (0x00050000)
 145 #define MPI3_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER     (0x00060000)
 146 #define MPI3_SAS_PHYINFO_REASON_BREAK_TIMEOUT           (0x00070000)
 147 #define MPI3_SAS_PHYINFO_REASON_PHY_TEST_STOPPED        (0x00080000)
 148 #define MPI3_SAS_PHYINFO_REASON_EXP_REDUCED_FUNC        (0x00090000)
 149 #define MPI3_SAS_PHYINFO_SATA_PORT_ACTIVE               (0x00004000)
 150 #define MPI3_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT     (0x00002000)
 151 #define MPI3_SAS_PHYINFO_VIRTUAL_PHY                    (0x00001000)
 152 #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_MASK      (0x00000f00)
 153 #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_SHIFT     (8)
 154 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_MASK         (0x000000f0)
 155 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_DIRECT       (0x00000000)
 156 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_SUBTRACTIVE  (0x00000010)
 157 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_TABLE        (0x00000020)
 158 #define MPI3_SAS_PRATE_MAX_RATE_MASK                    (0xf0)
 159 #define MPI3_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE        (0x00)
 160 #define MPI3_SAS_PRATE_MAX_RATE_1_5                     (0x80)
 161 #define MPI3_SAS_PRATE_MAX_RATE_3_0                     (0x90)
 162 #define MPI3_SAS_PRATE_MAX_RATE_6_0                     (0xa0)
 163 #define MPI3_SAS_PRATE_MAX_RATE_12_0                    (0xb0)
 164 #define MPI3_SAS_PRATE_MAX_RATE_22_5                    (0xc0)
 165 #define MPI3_SAS_PRATE_MIN_RATE_MASK                    (0x0f)
 166 #define MPI3_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE        (0x00)
 167 #define MPI3_SAS_PRATE_MIN_RATE_1_5                     (0x08)
 168 #define MPI3_SAS_PRATE_MIN_RATE_3_0                     (0x09)
 169 #define MPI3_SAS_PRATE_MIN_RATE_6_0                     (0x0a)
 170 #define MPI3_SAS_PRATE_MIN_RATE_12_0                    (0x0b)
 171 #define MPI3_SAS_PRATE_MIN_RATE_22_5                    (0x0c)
 172 #define MPI3_SAS_HWRATE_MAX_RATE_MASK                   (0xf0)
 173 #define MPI3_SAS_HWRATE_MAX_RATE_1_5                    (0x80)
 174 #define MPI3_SAS_HWRATE_MAX_RATE_3_0                    (0x90)
 175 #define MPI3_SAS_HWRATE_MAX_RATE_6_0                    (0xa0)
 176 #define MPI3_SAS_HWRATE_MAX_RATE_12_0                   (0xb0)
 177 #define MPI3_SAS_HWRATE_MAX_RATE_22_5                   (0xc0)
 178 #define MPI3_SAS_HWRATE_MIN_RATE_MASK                   (0x0f)
 179 #define MPI3_SAS_HWRATE_MIN_RATE_1_5                    (0x08)
 180 #define MPI3_SAS_HWRATE_MIN_RATE_3_0                    (0x09)
 181 #define MPI3_SAS_HWRATE_MIN_RATE_6_0                    (0x0a)
 182 #define MPI3_SAS_HWRATE_MIN_RATE_12_0                   (0x0b)
 183 #define MPI3_SAS_HWRATE_MIN_RATE_22_5                   (0x0c)
 184 #define MPI3_SLOT_INVALID                               (0xffff)
 185 #define MPI3_SLOT_INDEX_INVALID                         (0xffff)
 186 #define MPI3_LINK_CHANGE_COUNT_INVALID                   (0xffff)
 187 #define MPI3_RATE_CHANGE_COUNT_INVALID                   (0xffff)
 188 #define MPI3_TEMP_SENSOR_LOCATION_INTERNAL              (0x0)
 189 #define MPI3_TEMP_SENSOR_LOCATION_INLET                 (0x1)
 190 #define MPI3_TEMP_SENSOR_LOCATION_OUTLET                (0x2)
 191 #define MPI3_TEMP_SENSOR_LOCATION_DRAM                  (0x3)
 192 #define MPI3_MFGPAGE_VENDORID_BROADCOM                  (0x1000)
 193 #define MPI3_MFGPAGE_DEVID_SAS4116                      (0x00a5)
 194 #define MPI3_MFGPAGE_DEVID_SAS4016                      (0x00a7)
 195 struct mpi3_man_page0 {
 196         struct mpi3_config_page_header         header;
 197         u8                                 chip_revision[8];
 198         u8                                 chip_name[32];
 199         u8                                 board_name[32];
 200         u8                                 board_assembly[32];
 201         u8                                 board_tracer_number[32];
 202         __le32                             board_power;
 203         __le32                             reserved94;
 204         __le32                             reserved98;
 205         u8                                 oem;
 206         u8                                 sub_oem;
 207         __le16                             flags;
 208         u8                                 board_mfg_day;
 209         u8                                 board_mfg_month;
 210         __le16                             board_mfg_year;
 211         u8                                 board_rework_day;
 212         u8                                 board_rework_month;
 213         __le16                             board_rework_year;
 214         __le64                             board_revision;
 215         u8                                 e_pack_fru[16];
 216         u8                                 product_name[256];
 217 };
 218
 219 #define MPI3_MAN0_PAGEVERSION       (0x00)
 220 #define MPI3_MAN0_FLAGS_SWITCH_PRESENT                       (0x0002)
 221 #define MPI3_MAN0_FLAGS_EXPANDER_PRESENT                     (0x0001)
 222 #define MPI3_MAN1_VPD_SIZE                                   (512)
 223 struct mpi3_man_page1 {
 224         struct mpi3_config_page_header         header;
 225         __le32                             reserved08[2];
 226         u8                                 vpd[MPI3_MAN1_VPD_SIZE];
 227 };
 228
 229 #define MPI3_MAN1_PAGEVERSION                                 (0x00)
 230 struct mpi3_man5_phy_entry {
 231         __le64     ioc_wwid;
 232         __le64     device_name;
 233         __le64     sata_wwid;
 234 };
 235
 236 #ifndef MPI3_MAN5_PHY_MAX
 237 #define MPI3_MAN5_PHY_MAX                                   (1)
 238 #endif
 239 struct mpi3_man_page5 {
 240         struct mpi3_config_page_header         header;
 241         u8                                 num_phys;
 242         u8                                 reserved09[3];
 243         __le32                             reserved0c;
 244         struct mpi3_man5_phy_entry             phy[MPI3_MAN5_PHY_MAX];
 245 };
 246
 247 #define MPI3_MAN5_PAGEVERSION                                (0x00)
 248 struct mpi3_man6_gpio_entry {
 249         u8         function_code;
 250         u8         function_flags;
 251         __le16     flags;
 252         u8         param1;
 253         u8         param2;
 254         __le16     reserved06;
 255         __le32     param3;
 256 };
 257
 258 #define MPI3_MAN6_GPIO_FUNCTION_GENERIC                                       (0x00)
 259 #define MPI3_MAN6_GPIO_FUNCTION_ALTERNATE                                     (0x01)
 260 #define MPI3_MAN6_GPIO_FUNCTION_EXT_INTERRUPT                                 (0x02)
 261 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_ACTIVITY                               (0x03)
 262 #define MPI3_MAN6_GPIO_FUNCTION_OVER_TEMPERATURE                              (0x04)
 263 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_GREEN                             (0x05)
 264 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_YELLOW                            (0x06)
 265 #define MPI3_MAN6_GPIO_FUNCTION_CABLE_MANAGEMENT                              (0x07)
 266 #define MPI3_MAN6_GPIO_FUNCTION_BKPLANE_MGMT_TYPE                             (0x08)
 267 #define MPI3_MAN6_GPIO_FUNCTION_ISTWI_RESET                                   (0x0a)
 268 #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET                            (0x0b)
 269 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_FAULT                                  (0x0c)
 270 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_ATTN                                    (0x0d)
 271 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_ONLINE                                  (0x0e)
 272 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_FAULT                                   (0x0f)
 273 #define MPI3_MAN6_GPIO_FUNCTION_CTRL_TYPE                                     (0x10)
 274 #define MPI3_MAN6_GPIO_FUNCTION_LICENSE                                       (0x11)
 275 #define MPI3_MAN6_GPIO_FUNCTION_REFCLK_CONTROL                                (0x12)
 276 #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET_CLAMP                      (0x13)
 277 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_MASK               (0x01)
 278 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_ISTWI              (0x00)
 279 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_RECEPTACLEID       (0x01)
 280 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_MASK                        (0xf0)
 281 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_GENERIC                     (0x00)
 282 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_CABLE_MGMT                  (0x10)
 283 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_ACTIVE_CABLE_OVERCURRENT    (0x20)
 284 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK                       (0x01)
 285 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE                       (0x00)
 286 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL                      (0x01)
 287 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ALL_UP                    (0x00)
 288 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ONE_OR_MORE_UP            (0x01)
 289 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_MODULE_PRESENT             (0x00)
 290 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_ACTIVE_CABLE_ENABLE        (0x01)
 291 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_CABLE_MGMT_ENABLE          (0x02)
 292 #define MPI3_MAN6_GPIO_LICENSE_PARAM1_TYPE_IBUTTON                            (0x00)
 293 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_MASK                                   (0x0100)
 294 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_FAST_EDGE                              (0x0100)
 295 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_SLOW_EDGE                              (0x0000)
 296 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_MASK                              (0x00c0)
 297 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_100OHM                            (0x0000)
 298 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_66OHM                             (0x0040)
 299 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_50OHM                             (0x0080)
 300 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_33OHM                             (0x00c0)
 301 #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_MASK                                (0x0030)
 302 #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_SHIFT                               (4)
 303 #define MPI3_MAN6_GPIO_FLAGS_ACTIVE_HIGH                                      (0x0008)
 304 #define MPI3_MAN6_GPIO_FLAGS_BI_DIR_ENABLED                                   (0x0004)
 305 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_MASK                                   (0x0003)
 306 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_INPUT                                  (0x0000)
 307 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_DRAIN_OUTPUT                      (0x0001)
 308 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_SOURCE_OUTPUT                     (0x0002)
 309 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_PUSH_PULL_OUTPUT                       (0x0003)
 310 #ifndef MPI3_MAN6_GPIO_MAX
 311 #define MPI3_MAN6_GPIO_MAX                                                    (1)
 312 #endif
 313 struct mpi3_man_page6 {
 314         struct mpi3_config_page_header         header;
 315         __le16                             flags;
 316         __le16                             reserved0a;
 317         u8                                 num_gpio;
 318         u8                                 reserved0d[3];
 319         struct mpi3_man6_gpio_entry            gpio[MPI3_MAN6_GPIO_MAX];
 320 };
 321
 322 #define MPI3_MAN6_PAGEVERSION                                                 (0x00)
 323 #define MPI3_MAN6_FLAGS_HEARTBEAT_LED_DISABLED                                (0x0001)
 324 struct mpi3_man7_receptacle_info {
 325         __le32                             name[4];
 326         u8                                 location;
 327         u8                                 connector_type;
 328         u8                                 ped_clk;
 329         u8                                 connector_id;
 330         __le32                             reserved14;
 331 };
 332
 333 #define MPI3_MAN7_LOCATION_UNKNOWN                         (0x00)
 334 #define MPI3_MAN7_LOCATION_INTERNAL                        (0x01)
 335 #define MPI3_MAN7_LOCATION_EXTERNAL                        (0x02)
 336 #define MPI3_MAN7_LOCATION_VIRTUAL                         (0x03)
 337 #define MPI3_MAN7_PEDCLK_ROUTING_MASK                      (0x10)
 338 #define MPI3_MAN7_PEDCLK_ROUTING_DIRECT                    (0x00)
 339 #define MPI3_MAN7_PEDCLK_ROUTING_CLOCK_BUFFER              (0x10)
 340 #define MPI3_MAN7_PEDCLK_ID_MASK                           (0x0f)
 341 #ifndef MPI3_MAN7_RECEPTACLE_INFO_MAX
 342 #define MPI3_MAN7_RECEPTACLE_INFO_MAX                      (1)
 343 #endif
 344 struct mpi3_man_page7 {
 345         struct mpi3_config_page_header         header;
 346         __le32                             flags;
 347         u8                                 num_receptacles;
 348         u8                                 reserved0d[3];
 349         __le32                             enclosure_name[4];
 350         struct mpi3_man7_receptacle_info       receptacle_info[MPI3_MAN7_RECEPTACLE_INFO_MAX];
 351 };
 352
 353 #define MPI3_MAN7_PAGEVERSION                              (0x00)
 354 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_MASK          (0x01)
 355 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_0             (0x00)
 356 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_1             (0x01)
 357 struct mpi3_man8_phy_info {
 358         u8                                 receptacle_id;
 359         u8                                 connector_lane;
 360         __le16                             reserved02;
 361         __le16                             slotx1;
 362         __le16                             slotx2;
 363         __le16                             slotx4;
 364         __le16                             reserved0a;
 365         __le32                             reserved0c;
 366 };
 367
 368 #define MPI3_MAN8_PHY_INFO_RECEPTACLE_ID_HOST_PHY          (0xff)
 369 #ifndef MPI3_MAN8_PHY_INFO_MAX
 370 #define MPI3_MAN8_PHY_INFO_MAX                      (1)
 371 #endif
 372 struct mpi3_man_page8 {
 373         struct mpi3_config_page_header         header;
 374         __le32                             reserved08;
 375         u8                                 num_phys;
 376         u8                                 reserved0d[3];
 377         struct mpi3_man8_phy_info              phy_info[MPI3_MAN8_PHY_INFO_MAX];
 378 };
 379
 380 #define MPI3_MAN8_PAGEVERSION                   (0x00)
 381 struct mpi3_man9_rsrc_entry {
 382         __le32     maximum;
 383         __le32     decrement;
 384         __le32     minimum;
 385         __le32     actual;
 386 };
 387
 388 enum mpi3_man9_resources {
 389         MPI3_MAN9_RSRC_OUTSTANDING_REQS    = 0,
 390         MPI3_MAN9_RSRC_TARGET_CMDS         = 1,
 391         MPI3_MAN9_RSRC_RESERVED02          = 2,
 392         MPI3_MAN9_RSRC_NVME                = 3,
 393         MPI3_MAN9_RSRC_INITIATORS          = 4,
 394         MPI3_MAN9_RSRC_VDS                 = 5,
 395         MPI3_MAN9_RSRC_ENCLOSURES          = 6,
 396         MPI3_MAN9_RSRC_ENCLOSURE_PHYS      = 7,
 397         MPI3_MAN9_RSRC_EXPANDERS           = 8,
 398         MPI3_MAN9_RSRC_PCIE_SWITCHES       = 9,
 399         MPI3_MAN9_RSRC_RESERVED10          = 10,
 400         MPI3_MAN9_RSRC_HOST_PD_DRIVES      = 11,
 401         MPI3_MAN9_RSRC_ADV_HOST_PD_DRIVES  = 12,
 402         MPI3_MAN9_RSRC_RAID_PD_DRIVES      = 13,
 403         MPI3_MAN9_RSRC_DRV_DIAG_BUF        = 14,
 404         MPI3_MAN9_RSRC_NAMESPACE_COUNT     = 15,
 405         MPI3_MAN9_RSRC_NUM_RESOURCES
 406 };
 407
 408 #define MPI3_MAN9_MIN_OUTSTANDING_REQS      (1)
 409 #define MPI3_MAN9_MAX_OUTSTANDING_REQS      (65000)
 410 #define MPI3_MAN9_MIN_TARGET_CMDS           (0)
 411 #define MPI3_MAN9_MAX_TARGET_CMDS           (65535)
 412 #define MPI3_MAN9_MIN_SAS_TARGETS           (0)
 413 #define MPI3_MAN9_MAX_SAS_TARGETS           (65535)
 414 #define MPI3_MAN9_MIN_PCIE_TARGETS          (0)
 415 #define MPI3_MAN9_MIN_INITIATORS            (0)
 416 #define MPI3_MAN9_MAX_INITIATORS            (65535)
 417 #define MPI3_MAN9_MIN_ENCLOSURES            (0)
 418 #define MPI3_MAN9_MAX_ENCLOSURES            (65535)
 419 #define MPI3_MAN9_MIN_ENCLOSURE_PHYS        (0)
 420 #define MPI3_MAN9_MIN_NAMESPACE_COUNT       (1)
 421 #define MPI3_MAN9_MIN_EXPANDERS             (0)
 422 #define MPI3_MAN9_MAX_EXPANDERS             (65535)
 423 #define MPI3_MAN9_MIN_PCIE_SWITCHES         (0)
 424 struct mpi3_man_page9 {
 425         struct mpi3_config_page_header         header;
 426         u8                                 num_resources;
 427         u8                                 reserved09;
 428         __le16                             reserved0a;
 429         __le32                             reserved0c;
 430         __le32                             reserved10;
 431         __le32                             reserved14;
 432         __le32                             reserved18;
 433         __le32                             reserved1c;
 434         struct mpi3_man9_rsrc_entry            resource[MPI3_MAN9_RSRC_NUM_RESOURCES];
 435 };
 436
 437 #define MPI3_MAN9_PAGEVERSION                   (0x00)
 438 struct mpi3_man10_istwi_ctrlr_entry {
 439         __le16     slave_address;
 440         __le16     flags;
 441         u8         scl_low_override;
 442         u8         scl_high_override;
 443         __le16     reserved06;
 444 };
 445
 446 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK         (0x000c)
 447 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_100K         (0x0000)
 448 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_400K         (0x0004)
 449 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_SLAVE_ENABLED          (0x0002)
 450 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_MASTER_ENABLED         (0x0001)
 451 #ifndef MPI3_MAN10_ISTWI_CTRLR_MAX
 452 #define MPI3_MAN10_ISTWI_CTRLR_MAX          (1)
 453 #endif
 454 struct mpi3_man_page10 {
 455         struct mpi3_config_page_header         header;
 456         __le32                             reserved08;
 457         u8                                 num_istwi_ctrl;
 458         u8                                 reserved0d[3];
 459         struct mpi3_man10_istwi_ctrlr_entry    istwi_controller[MPI3_MAN10_ISTWI_CTRLR_MAX];
 460 };
 461
 462 #define MPI3_MAN10_PAGEVERSION                  (0x00)
 463 struct mpi3_man11_mux_device_format {
 464         u8         max_channel;
 465         u8         reserved01[3];
 466         __le32     reserved04;
 467 };
 468
 469 struct mpi3_man11_temp_sensor_device_format {
 470         u8         type;
 471         u8         reserved01[3];
 472         u8         temp_channel[4];
 473 };
 474
 475 #define MPI3_MAN11_TEMP_SENSOR_TYPE_MAX6654                (0x00)
 476 #define MPI3_MAN11_TEMP_SENSOR_TYPE_EMC1442                (0x01)
 477 #define MPI3_MAN11_TEMP_SENSOR_TYPE_ADT7476                (0x02)
 478 #define MPI3_MAN11_TEMP_SENSOR_TYPE_SE97B                  (0x03)
 479 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_MASK       (0xe0)
 480 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_SHIFT      (5)
 481 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_ENABLED             (0x01)
 482 struct mpi3_man11_seeprom_device_format {
 483         u8         size;
 484         u8         page_write_size;
 485         __le16     reserved02;
 486         __le32     reserved04;
 487 };
 488
 489 #define MPI3_MAN11_SEEPROM_SIZE_1KBITS              (0x01)
 490 #define MPI3_MAN11_SEEPROM_SIZE_2KBITS              (0x02)
 491 #define MPI3_MAN11_SEEPROM_SIZE_4KBITS              (0x03)
 492 #define MPI3_MAN11_SEEPROM_SIZE_8KBITS              (0x04)
 493 #define MPI3_MAN11_SEEPROM_SIZE_16KBITS             (0x05)
 494 #define MPI3_MAN11_SEEPROM_SIZE_32KBITS             (0x06)
 495 #define MPI3_MAN11_SEEPROM_SIZE_64KBITS             (0x07)
 496 #define MPI3_MAN11_SEEPROM_SIZE_128KBITS            (0x08)
 497 struct mpi3_man11_ddr_spd_device_format {
 498         u8         channel;
 499         u8         reserved01[3];
 500         __le32     reserved04;
 501 };
 502
 503 struct mpi3_man11_cable_mgmt_device_format {
 504         u8         type;
 505         u8         receptacle_id;
 506         __le16     reserved02;
 507         __le32     reserved04;
 508 };
 509
 510 #define MPI3_MAN11_CABLE_MGMT_TYPE_SFF_8636           (0x00)
 511 struct mpi3_man11_bkplane_spec_ubm_format {
 512         __le16     flags;
 513         __le16     reserved02;
 514 };
 515
 516 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED  (0x0200)
 517 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_FORCE_POLLING                 (0x0100)
 518 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_MASK                  (0x00f0)
 519 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_SHIFT                 (4)
 520 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_MASK            (0x000f)
 521 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_SHIFT           (0)
 522 struct mpi3_man11_bkplane_spec_non_ubm_format {
 523         __le16     flags;
 524         u8         reserved02;
 525         u8         type;
 526 };
 527
 528 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_MASK                    (0xf000)
 529 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_SHIFT                   (12)
 530 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED  (0x0200)
 531 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_MASK          (0x0030)
 532 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_GPIO          (0x0000)
 533 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_REG           (0x0010)
 534 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_MASK            (0x000f)
 535 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_SHIFT           (0)
 536 #define MPI3_MAN11_BKPLANE_NON_UBM_TYPE_VPP                            (0x00)
 537 union mpi3_man11_bkplane_spec_format {
 538         struct mpi3_man11_bkplane_spec_ubm_format         ubm;
 539         struct mpi3_man11_bkplane_spec_non_ubm_format     non_ubm;
 540 };
 541
 542 struct mpi3_man11_bkplane_mgmt_device_format {
 543         u8                                        type;
 544         u8                                        receptacle_id;
 545         u8                                        reset_info;
 546         u8                                        reserved03;
 547         union mpi3_man11_bkplane_spec_format         backplane_mgmt_specific;
 548 };
 549
 550 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_UBM            (0x00)
 551 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_NON_UBM        (0x01)
 552 #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_MASK       (0xf0)
 553 #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_SHIFT      (4)
 554 #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_MASK        (0x0f)
 555 #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_SHIFT       (0)
 556 struct mpi3_man11_gas_gauge_device_format {
 557         u8         type;
 558         u8         reserved01[3];
 559         __le32     reserved04;
 560 };
 561
 562 #define MPI3_MAN11_GAS_GAUGE_TYPE_STANDARD          (0x00)
 563 struct mpi3_man11_mgmt_ctrlr_device_format {
 564         __le32     reserved00;
 565         __le32     reserved04;
 566 };
 567
 568 union mpi3_man11_device_specific_format {
 569         struct mpi3_man11_mux_device_format            mux;
 570         struct mpi3_man11_temp_sensor_device_format    temp_sensor;
 571         struct mpi3_man11_seeprom_device_format        seeprom;
 572         struct mpi3_man11_ddr_spd_device_format        ddr_spd;
 573         struct mpi3_man11_cable_mgmt_device_format     cable_mgmt;
 574         struct mpi3_man11_bkplane_mgmt_device_format   bkplane_mgmt;
 575         struct mpi3_man11_gas_gauge_device_format      gas_gauge;
 576         struct mpi3_man11_mgmt_ctrlr_device_format     mgmt_controller;
 577         __le32                                     words[2];
 578 };
 579
 580 struct mpi3_man11_istwi_device_format {
 581         u8                                     device_type;
 582         u8                                     controller;
 583         u8                                     reserved02;
 584         u8                                     flags;
 585         __le16                                 device_address;
 586         u8                                     mux_channel;
 587         u8                                     mux_index;
 588         union mpi3_man11_device_specific_format   device_specific;
 589 };
 590
 591 #define MPI3_MAN11_ISTWI_DEVTYPE_MUX                  (0x00)
 592 #define MPI3_MAN11_ISTWI_DEVTYPE_TEMP_SENSOR          (0x01)
 593 #define MPI3_MAN11_ISTWI_DEVTYPE_SEEPROM              (0x02)
 594 #define MPI3_MAN11_ISTWI_DEVTYPE_DDR_SPD              (0x03)
 595 #define MPI3_MAN11_ISTWI_DEVTYPE_CABLE_MGMT           (0x04)
 596 #define MPI3_MAN11_ISTWI_DEVTYPE_BACKPLANE_MGMT       (0x05)
 597 #define MPI3_MAN11_ISTWI_DEVTYPE_GAS_GAUGE            (0x06)
 598 #define MPI3_MAN11_ISTWI_DEVTYPE_MGMT_CONTROLLER      (0x07)
 599 #define MPI3_MAN11_ISTWI_FLAGS_MUX_PRESENT            (0x01)
 600 #ifndef MPI3_MAN11_ISTWI_DEVICE_MAX
 601 #define MPI3_MAN11_ISTWI_DEVICE_MAX             (1)
 602 #endif
 603 struct mpi3_man_page11 {
 604         struct mpi3_config_page_header         header;
 605         __le32                             reserved08;
 606         u8                                 num_istwi_dev;
 607         u8                                 reserved0d[3];
 608         struct mpi3_man11_istwi_device_format  istwi_device[MPI3_MAN11_ISTWI_DEVICE_MAX];
 609 };
 610
 611 #define MPI3_MAN11_PAGEVERSION                  (0x00)
 612 #ifndef MPI3_MAN12_NUM_SGPIO_MAX
 613 #define MPI3_MAN12_NUM_SGPIO_MAX                                     (1)
 614 #endif
 615 struct mpi3_man12_sgpio_info {
 616         u8                                 slot_count;
 617         u8                                 reserved01[3];
 618         __le32                             reserved04;
 619         u8                                 phy_order[32];
 620 };
 621
 622 struct mpi3_man_page12 {
 623         struct mpi3_config_page_header         header;
 624         __le32                             flags;
 625         __le32                             s_clock_freq;
 626         __le32                             activity_modulation;
 627         u8                                 num_sgpio;
 628         u8                                 reserved15[3];
 629         __le32                             reserved18;
 630         __le32                             reserved1c;
 631         __le32                             pattern[8];
 632         struct mpi3_man12_sgpio_info           sgpio_info[MPI3_MAN12_NUM_SGPIO_MAX];
 633 };
 634
 635 #define MPI3_MAN12_PAGEVERSION                                       (0x00)
 636 #define MPI3_MAN12_FLAGS_ERROR_PRESENCE_ENABLED                      (0x0400)
 637 #define MPI3_MAN12_FLAGS_ACTIVITY_INVERT_ENABLED                     (0x0200)
 638 #define MPI3_MAN12_FLAGS_GROUP_ID_DISABLED                           (0x0100)
 639 #define MPI3_MAN12_FLAGS_SIO_CLK_FILTER_ENABLED                      (0x0004)
 640 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_MASK                      (0x0002)
 641 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_PUSH_PULL                 (0x0000)
 642 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_OPEN_DRAIN                (0x0002)
 643 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_MASK                          (0x0001)
 644 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_PUSH_PULL                     (0x0000)
 645 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_OPEN_DRAIN                    (0x0001)
 646 #define MPI3_MAN12_SIO_CLK_FREQ_MIN                                  (32)
 647 #define MPI3_MAN12_SIO_CLK_FREQ_MAX                                  (100000)
 648 #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_MASK                (0x0000f000)
 649 #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_SHIFT               (12)
 650 #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_MASK                   (0x00000f00)
 651 #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_SHIFT                  (8)
 652 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_MASK              (0x000000f0)
 653 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_SHIFT             (4)
 654 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_MASK               (0x0000000f)
 655 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_SHIFT              (0)
 656 #define MPI3_MAN12_PATTERN_RATE_MASK                                 (0xe0000000)
 657 #define MPI3_MAN12_PATTERN_RATE_2_HZ                                 (0x00000000)
 658 #define MPI3_MAN12_PATTERN_RATE_4_HZ                                 (0x20000000)
 659 #define MPI3_MAN12_PATTERN_RATE_8_HZ                                 (0x40000000)
 660 #define MPI3_MAN12_PATTERN_RATE_16_HZ                                (0x60000000)
 661 #define MPI3_MAN12_PATTERN_RATE_10_HZ                                (0x80000000)
 662 #define MPI3_MAN12_PATTERN_RATE_20_HZ                                (0xa0000000)
 663 #define MPI3_MAN12_PATTERN_RATE_40_HZ                                (0xc0000000)
 664 #define MPI3_MAN12_PATTERN_LENGTH_MASK                               (0x1f000000)
 665 #define MPI3_MAN12_PATTERN_LENGTH_SHIFT                              (24)
 666 #define MPI3_MAN12_PATTERN_BIT_PATTERN_MASK                          (0x00ffffff)
 667 #define MPI3_MAN12_PATTERN_BIT_PATTERN_SHIFT                         (0)
 668 #ifndef MPI3_MAN13_NUM_TRANSLATION_MAX
 669 #define MPI3_MAN13_NUM_TRANSLATION_MAX                               (1)
 670 #endif
 671 struct mpi3_man13_translation_info {
 672         __le32                             slot_status;
 673         __le32                             mask;
 674         u8                                 activity;
 675         u8                                 locate;
 676         u8                                 error;
 677         u8                                 reserved0b;
 678 };
 679
 680 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_FAULT                     (0x20000000)
 681 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_OFF                (0x10000000)
 682 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_ACTIVITY           (0x00800000)
 683 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DO_NOT_REMOVE             (0x00400000)
 684 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_MISSING            (0x00100000)
 685 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_INSERT                    (0x00080000)
 686 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REMOVAL                   (0x00040000)
 687 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IDENTIFY                  (0x00020000)
 688 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_OK                        (0x00008000)
 689 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_RESERVED_DEVICE           (0x00004000)
 690 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_HOT_SPARE                 (0x00002000)
 691 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_CONSISTENCY_CHECK         (0x00001000)
 692 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_CRITICAL_ARRAY         (0x00000800)
 693 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_FAILED_ARRAY           (0x00000400)
 694 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP             (0x00000200)
 695 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP_ABORT       (0x00000100)
 696 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_PREDICTED_FAILURE         (0x00000040)
 697 #define MPI3_MAN13_BLINK_PATTERN_FORCE_OFF                          (0x00)
 698 #define MPI3_MAN13_BLINK_PATTERN_FORCE_ON                           (0x01)
 699 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_0                          (0x02)
 700 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_1                          (0x03)
 701 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_2                          (0x04)
 702 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_3                          (0x05)
 703 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_4                          (0x06)
 704 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_5                          (0x07)
 705 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_6                          (0x08)
 706 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_7                          (0x09)
 707 #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY                           (0x0a)
 708 #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY_TRAIL                     (0x0b)
 709 struct mpi3_man_page13 {
 710         struct mpi3_config_page_header         header;
 711         u8                                 num_trans;
 712         u8                                 reserved09[3];
 713         __le32                             reserved0c;
 714         struct mpi3_man13_translation_info     translation[MPI3_MAN13_NUM_TRANSLATION_MAX];
 715 };
 716
 717 #define MPI3_MAN13_PAGEVERSION                                       (0x00)
 718 struct mpi3_man_page14 {
 719         struct mpi3_config_page_header         header;
 720         __le16                             flags;
 721         __le16                             reserved0a;
 722         u8                                 num_slot_groups;
 723         u8                                 num_slots;
 724         __le16                             max_cert_chain_length;
 725         __le32                             sealed_slots;
 726 };
 727
 728 #define MPI3_MAN14_PAGEVERSION                                       (0x00)
 729 #define MPI3_MAN14_FLAGS_AUTH_SESSION_REQ                            (0x01)
 730 #define MPI3_MAN14_FLAGS_AUTH_API_MASK                               (0x0e)
 731 #define MPI3_MAN14_FLAGS_AUTH_API_NONE                               (0x00)
 732 #define MPI3_MAN14_FLAGS_AUTH_API_CERBERUS                           (0x02)
 733 #define MPI3_MAN14_FLAGS_AUTH_API_SPDM                               (0x04)
 734 #ifndef MPI3_MAN15_VERSION_RECORD_MAX
 735 #define MPI3_MAN15_VERSION_RECORD_MAX      1
 736 #endif
 737 struct mpi3_man15_version_record {
 738         __le16                             spdm_version;
 739         __le16                             reserved02;
 740 };
 741
 742 struct mpi3_man_page15 {
 743         struct mpi3_config_page_header         header;
 744         u8                                 num_version_records;
 745         u8                                 reserved09[3];
 746         __le32                             reserved0c;
 747         struct mpi3_man15_version_record       version_record[MPI3_MAN15_VERSION_RECORD_MAX];
 748 };
 749
 750 #define MPI3_MAN15_PAGEVERSION                                       (0x00)
 751 #ifndef MPI3_MAN16_CERT_ALGO_MAX
 752 #define MPI3_MAN16_CERT_ALGO_MAX      1
 753 #endif
 754 struct mpi3_man16_certificate_algorithm {
 755         u8                                      slot_group;
 756         u8                                      reserved01[3];
 757         __le32                                  base_asym_algo;
 758         __le32                                  base_hash_algo;
 759         __le32                                  reserved0c[3];
 760 };
 761
 762 struct mpi3_man_page16 {
 763         struct mpi3_config_page_header              header;
 764         __le32                                  reserved08;
 765         u8                                      num_cert_algos;
 766         u8                                      reserved0d[3];
 767         struct mpi3_man16_certificate_algorithm     certificate_algorithm[MPI3_MAN16_CERT_ALGO_MAX];
 768 };
 769
 770 #define MPI3_MAN16_PAGEVERSION                                       (0x00)
 771 #ifndef MPI3_MAN17_HASH_ALGORITHM_MAX
 772 #define MPI3_MAN17_HASH_ALGORITHM_MAX      1
 773 #endif
 774 struct mpi3_man17_hash_algorithm {
 775         u8                                 meas_specification;
 776         u8                                 reserved01[3];
 777         __le32                             measurement_hash_algo;
 778         __le32                             reserved08[2];
 779 };
 780
 781 struct mpi3_man_page17 {
 782         struct mpi3_config_page_header         header;
 783         __le32                             reserved08;
 784         u8                                 num_hash_algos;
 785         u8                                 reserved0d[3];
 786         struct mpi3_man17_hash_algorithm       hash_algorithm[MPI3_MAN17_HASH_ALGORITHM_MAX];
 787 };
 788
 789 #define MPI3_MAN17_PAGEVERSION                                       (0x00)
 790 struct mpi3_man_page20 {
 791         struct mpi3_config_page_header         header;
 792         __le32                             reserved08;
 793         __le32                             nonpremium_features;
 794         u8                                 allowed_personalities;
 795         u8                                 reserved11[3];
 796 };
 797
 798 #define MPI3_MAN20_PAGEVERSION                                       (0x00)
 799 #define MPI3_MAN20_ALLOWEDPERSON_RAID_MASK                           (0x02)
 800 #define MPI3_MAN20_ALLOWEDPERSON_RAID_ALLOWED                        (0x02)
 801 #define MPI3_MAN20_ALLOWEDPERSON_RAID_NOT_ALLOWED                    (0x00)
 802 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_MASK                           (0x01)
 803 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_ALLOWED                        (0x01)
 804 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_NOT_ALLOWED                    (0x00)
 805 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_MASK               (0x01)
 806 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_ENABLED            (0x00)
 807 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_DISABLED           (0x01)
 808 struct mpi3_man_page21 {
 809         struct mpi3_config_page_header         header;
 810         __le32                             reserved08;
 811         __le32                             flags;
 812 };
 813
 814 #define MPI3_MAN21_PAGEVERSION                                       (0x00)
 815 #define MPI3_MAN21_FLAGS_HOST_METADATA_CAPABILITY_MASK               (0x80)
 816 #define MPI3_MAN21_FLAGS_HOST_METADATA_CAPABILITY_ENABLED            (0x80)
 817 #define MPI3_MAN21_FLAGS_HOST_METADATA_CAPABILITY_DISABLED           (0x00)
 818 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_MASK                     (0x60)
 819 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_BLOCK                    (0x00)
 820 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_ALLOW                    (0x20)
 821 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_WARN                     (0x40)
 822 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_MASK              (0x08)
 823 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_ALLOW             (0x00)
 824 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_PREVENT           (0x08)
 825 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_MASK                          (0x01)
 826 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_DEFAULT                       (0x00)
 827 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_OEM_SPECIFIC                  (0x01)
 828 #ifndef MPI3_MAN_PROD_SPECIFIC_MAX
 829 #define MPI3_MAN_PROD_SPECIFIC_MAX                      (1)
 830 #endif
 831 struct mpi3_man_page_product_specific {
 832         struct mpi3_config_page_header         header;
 833         __le32                             product_specific_info[MPI3_MAN_PROD_SPECIFIC_MAX];
 834 };
 835
 836 struct mpi3_io_unit_page0 {
 837         struct mpi3_config_page_header         header;
 838         __le64                             unique_value;
 839         __le32                             nvdata_version_default;
 840         __le32                             nvdata_version_persistent;
 841 };
 842
 843 #define MPI3_IOUNIT0_PAGEVERSION                (0x00)
 844 struct mpi3_io_unit_page1 {
 845         struct mpi3_config_page_header         header;
 846         __le32                             flags;
 847         u8                                 dmd_io_delay;
 848         u8                                 dmd_report_pcie;
 849         u8                                 dmd_report_sata;
 850         u8                                 dmd_report_sas;
 851 };
 852
 853 #define MPI3_IOUNIT1_PAGEVERSION                (0x00)
 854 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_MASK                   (0x00000030)
 855 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_ENABLE                 (0x00000000)
 856 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_DISABLE                (0x00000010)
 857 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_NO_MODIFY              (0x00000020)
 858 #define MPI3_IOUNIT1_FLAGS_ATA_SECURITY_FREEZE_LOCK                (0x00000008)
 859 #define MPI3_IOUNIT1_FLAGS_WRITE_SAME_BUFFER                       (0x00000004)
 860 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_MASK                   (0x00000003)
 861 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_ENABLE                 (0x00000000)
 862 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_DISABLE                (0x00000001)
 863 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_UNCHANGED              (0x00000002)
 864 #define MPI3_IOUNIT1_DMD_REPORT_DELAY_TIME_MASK                    (0x7f)
 865 #define MPI3_IOUNIT1_DMD_REPORT_UNIT_16_SEC                        (0x80)
 866 #ifndef MPI3_IO_UNIT2_GPIO_VAL_MAX
 867 #define MPI3_IO_UNIT2_GPIO_VAL_MAX      (1)
 868 #endif
 869 struct mpi3_io_unit_page2 {
 870         struct mpi3_config_page_header         header;
 871         u8                                 gpio_count;
 872         u8                                 reserved09[3];
 873         __le16                             gpio_val[MPI3_IO_UNIT2_GPIO_VAL_MAX];
 874 };
 875
 876 #define MPI3_IOUNIT2_PAGEVERSION                (0x00)
 877 #define MPI3_IOUNIT2_GPIO_FUNCTION_MASK         (0xfffc)
 878 #define MPI3_IOUNIT2_GPIO_FUNCTION_SHIFT        (2)
 879 #define MPI3_IOUNIT2_GPIO_SETTING_MASK          (0x0001)
 880 #define MPI3_IOUNIT2_GPIO_SETTING_OFF           (0x0000)
 881 #define MPI3_IOUNIT2_GPIO_SETTING_ON            (0x0001)
 882 struct mpi3_io_unit3_sensor {
 883         __le16             flags;
 884         u8                 threshold_margin;
 885         u8                 reserved03;
 886         __le16             threshold[3];
 887         __le16             reserved0a;
 888         __le32             reserved0c;
 889         __le32             reserved10;
 890         __le32             reserved14;
 891 };
 892
 893 #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_EVENT_ENABLED           (0x0010)
 894 #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_ACTION_ENABLED          (0x0008)
 895 #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_EVENT_ENABLED        (0x0004)
 896 #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_ACTION_ENABLED       (0x0002)
 897 #define MPI3_IOUNIT3_SENSOR_FLAGS_WARNING_EVENT_ENABLED         (0x0001)
 898 #ifndef MPI3_IO_UNIT3_SENSOR_MAX
 899 #define MPI3_IO_UNIT3_SENSOR_MAX                                (1)
 900 #endif
 901 struct mpi3_io_unit_page3 {
 902         struct mpi3_config_page_header         header;
 903         __le32                             reserved08;
 904         u8                                 num_sensors;
 905         u8                                 nominal_poll_interval;
 906         u8                                 warning_poll_interval;
 907         u8                                 reserved0f;
 908         struct mpi3_io_unit3_sensor            sensor[MPI3_IO_UNIT3_SENSOR_MAX];
 909 };
 910
 911 #define MPI3_IOUNIT3_PAGEVERSION                (0x00)
 912 struct mpi3_io_unit4_sensor {
 913         __le16             current_temperature;
 914         __le16             reserved02;
 915         u8                 flags;
 916         u8                 reserved05[3];
 917         __le16             istwi_index;
 918         u8                 channel;
 919         u8                 reserved0b;
 920         __le32             reserved0c;
 921 };
 922
 923 #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_MASK          (0xe0)
 924 #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_SHIFT         (5)
 925 #define MPI3_IOUNIT4_SENSOR_FLAGS_TEMP_VALID        (0x01)
 926 #define MPI3_IOUNIT4_SENSOR_ISTWI_INDEX_INTERNAL    (0xffff)
 927 #define MPI3_IOUNIT4_SENSOR_CHANNEL_RESERVED        (0xff)
 928 #ifndef MPI3_IO_UNIT4_SENSOR_MAX
 929 #define MPI3_IO_UNIT4_SENSOR_MAX                                (1)
 930 #endif
 931 struct mpi3_io_unit_page4 {
 932         struct mpi3_config_page_header         header;
 933         __le32                             reserved08;
 934         u8                                 num_sensors;
 935         u8                                 reserved0d[3];
 936         struct mpi3_io_unit4_sensor            sensor[MPI3_IO_UNIT4_SENSOR_MAX];
 937 };
 938
 939 #define MPI3_IOUNIT4_PAGEVERSION                (0x00)
 940 struct mpi3_io_unit5_spinup_group {
 941         u8                 max_target_spinup;
 942         u8                 spinup_delay;
 943         u8                 spinup_flags;
 944         u8                 reserved03;
 945 };
 946
 947 #define MPI3_IOUNIT5_SPINUP_FLAGS_DISABLE       (0x01)
 948 #ifndef MPI3_IO_UNIT5_PHY_MAX
 949 #define MPI3_IO_UNIT5_PHY_MAX       (4)
 950 #endif
 951 struct mpi3_io_unit_page5 {
 952         struct mpi3_config_page_header         header;
 953         struct mpi3_io_unit5_spinup_group      spinup_group_parameters[4];
 954         __le32                             reserved18;
 955         __le32                             reserved1c;
 956         __le16                             device_shutdown;
 957         __le16                             reserved22;
 958         u8                                 pcie_device_wait_time;
 959         u8                                 sata_device_wait_time;
 960         u8                                 spinup_encl_drive_count;
 961         u8                                 spinup_encl_delay;
 962         u8                                 num_phys;
 963         u8                                 pe_initial_spinup_delay;
 964         u8                                 topology_stable_time;
 965         u8                                 flags;
 966         u8                                 phy[MPI3_IO_UNIT5_PHY_MAX];
 967 };
 968
 969 #define MPI3_IOUNIT5_PAGEVERSION                           (0x00)
 970 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NO_ACTION             (0x00)
 971 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_ATTACHED       (0x01)
 972 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_EXPANDER_ATTACHED     (0x02)
 973 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SWITCH_ATTACHED       (0x02)
 974 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_EXPANDER   (0x03)
 975 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_SWITCH     (0x03)
 976 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_MASK         (0x0300)
 977 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_SHIFT        (8)
 978 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_MASK          (0x00c0)
 979 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_SHIFT         (6)
 980 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_MASK         (0x0030)
 981 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_SHIFT        (4)
 982 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_MASK         (0x000c)
 983 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_SHIFT        (2)
 984 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_MASK          (0x0003)
 985 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAA_SSD_SHIFT         (0)
 986 #define MPI3_IOUNIT5_FLAGS_POWER_CAPABLE_SPINUP            (0x02)
 987 #define MPI3_IOUNIT5_FLAGS_AUTO_PORT_ENABLE                (0x01)
 988 #define MPI3_IOUNIT5_PHY_SPINUP_GROUP_MASK                 (0x03)
 989 struct mpi3_io_unit_page6 {
 990         struct mpi3_config_page_header         header;
 991         __le32                             board_power_requirement;
 992         __le32                             pci_slot_power_allocation;
 993         u8                                 flags;
 994         u8                                 reserved11[3];
 995 };
 996
 997 #define MPI3_IOUNIT6_PAGEVERSION                (0x00)
 998 #define MPI3_IOUNIT6_FLAGS_ACT_CABLE_PWR_EXC    (0x01)
 999 struct mpi3_io_unit_page7 {
1000         struct mpi3_config_page_header         header;
1001         __le32                             reserved08;
1002 };
1003
1004 #define MPI3_IOUNIT7_PAGEVERSION                (0x00)
1005 #ifndef MPI3_IOUNIT8_DIGEST_MAX
1006 #define MPI3_IOUNIT8_DIGEST_MAX                   (1)
1007 #endif
1008 union mpi3_iounit8_digest {
1009         __le32                             dword[16];
1010         __le16                             word[32];
1011         u8                                 byte[64];
1012 };
1013
1014 struct mpi3_io_unit_page8 {
1015         struct mpi3_config_page_header         header;
1016         u8                                 sb_mode;
1017         u8                                 sb_state;
1018         __le16                             reserved0a;
1019         u8                                 num_slots;
1020         u8                                 slots_available;
1021         u8                                 current_key_encryption_algo;
1022         u8                                 key_digest_hash_algo;
1023         __le32                             reserved10[2];
1024         __le32                             current_key[128];
1025         union mpi3_iounit8_digest             digest[MPI3_IOUNIT8_DIGEST_MAX];
1026 };
1027
1028 #define MPI3_IOUNIT8_PAGEVERSION                  (0x00)
1029 #define MPI3_IOUNIT8_SBMODE_SECURE_DEBUG          (0x04)
1030 #define MPI3_IOUNIT8_SBMODE_HARD_SECURE           (0x02)
1031 #define MPI3_IOUNIT8_SBMODE_CONFIG_SECURE         (0x01)
1032 #define MPI3_IOUNIT8_SBSTATE_KEY_UPDATE_PENDING   (0x02)
1033 #define MPI3_IOUNIT8_SBSTATE_SECURE_BOOT_ENABLED  (0x01)
1034 struct mpi3_io_unit_page9 {
1035         struct mpi3_config_page_header         header;
1036         __le32                             flags;
1037         __le16                             first_device;
1038         __le16                             reserved0e;
1039 };
1040
1041 #define MPI3_IOUNIT9_PAGEVERSION                  (0x00)
1042 #define MPI3_IOUNIT9_FLAGS_VDFIRST_ENABLED         (0x01)
1043 #define MPI3_IOUNIT9_FIRSTDEVICE_UNKNOWN          (0xffff)
1044 struct mpi3_ioc_page0 {
1045         struct mpi3_config_page_header         header;
1046         __le32                             reserved08;
1047         __le16                             vendor_id;
1048         __le16                             device_id;
1049         u8                                 revision_id;
1050         u8                                 reserved11[3];
1051         __le32                             class_code;
1052         __le16                             subsystem_vendor_id;
1053         __le16                             subsystem_id;
1054 };
1055
1056 #define MPI3_IOC0_PAGEVERSION               (0x00)
1057 struct mpi3_ioc_page1 {
1058         struct mpi3_config_page_header         header;
1059         __le32                             coalescing_timeout;
1060         u8                                 coalescing_depth;
1061         u8                                 pci_slot_num;
1062         __le16                             reserved0e;
1063 };
1064
1065 #define MPI3_IOC1_PAGEVERSION               (0x00)
1066 #define MPI3_IOC1_PCISLOTNUM_UNKNOWN        (0xff)
1067 #ifndef MPI3_IOC2_EVENTMASK_WORDS
1068 #define MPI3_IOC2_EVENTMASK_WORDS           (4)
1069 #endif
1070 struct mpi3_ioc_page2 {
1071         struct mpi3_config_page_header         header;
1072         __le32                             reserved08;
1073         __le16                             sas_broadcast_primitive_masks;
1074         __le16                             sas_notify_primitive_masks;
1075         __le32                             event_masks[MPI3_IOC2_EVENTMASK_WORDS];
1076 };
1077
1078 #define MPI3_IOC2_PAGEVERSION               (0x00)
1079 #define MPI3_DRIVER_FLAGS_ADMINRAIDPD_BLOCKED               (0x0010)
1080 #define MPI3_DRIVER_FLAGS_OOBRAIDPD_BLOCKED                 (0x0008)
1081 #define MPI3_DRIVER_FLAGS_OOBRAIDVD_BLOCKED                 (0x0004)
1082 #define MPI3_DRIVER_FLAGS_OOBADVHOSTPD_BLOCKED              (0x0002)
1083 #define MPI3_DRIVER_FLAGS_OOBHOSTPD_BLOCKED                 (0x0001)
1084 struct mpi3_allowed_cmd_scsi {
1085         __le16                             service_action;
1086         u8                                 operation_code;
1087         u8                                 command_flags;
1088 };
1089
1090 struct mpi3_allowed_cmd_ata {
1091         u8                                 subcommand;
1092         u8                                 reserved01;
1093         u8                                 command;
1094         u8                                 command_flags;
1095 };
1096
1097 struct mpi3_allowed_cmd_nvme {
1098         u8                                 reserved00;
1099         u8                                 nvme_cmd_flags;
1100         u8                                 op_code;
1101         u8                                 command_flags;
1102 };
1103
1104 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_MASK     (0x80)
1105 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_IO       (0x00)
1106 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_ADMIN    (0x80)
1107 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_MASK        (0x3f)
1108 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_NVM         (0x00)
1109 union mpi3_allowed_cmd {
1110         struct mpi3_allowed_cmd_scsi           scsi;
1111         struct mpi3_allowed_cmd_ata            ata;
1112         struct mpi3_allowed_cmd_nvme           nvme;
1113 };
1114
1115 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_ADMINRAIDPD_BLOCKED    (0x20)
1116 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDPD_BLOCKED      (0x10)
1117 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDVD_BLOCKED      (0x08)
1118 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBADVHOSTPD_BLOCKED   (0x04)
1119 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBHOSTPD_BLOCKED      (0x02)
1120 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_CHECKSUBCMD_ENABLED    (0x01)
1121 #ifndef MPI3_ALLOWED_CMDS_MAX
1122 #define MPI3_ALLOWED_CMDS_MAX           (1)
1123 #endif
1124 struct mpi3_driver_page0 {
1125         struct mpi3_config_page_header         header;
1126         __le32                             bsd_options;
1127         u8                                 ssu_timeout;
1128         u8                                 io_timeout;
1129         u8                                 tur_retries;
1130         u8                                 tur_interval;
1131         u8                                 reserved10;
1132         u8                                 security_key_timeout;
1133         __le16                             reserved12;
1134         __le32                             reserved14;
1135         __le32                             reserved18;
1136 };
1137
1138 #define MPI3_DRIVER0_PAGEVERSION               (0x00)
1139 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_MASK              (0x00000003)
1140 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_DEVS      (0x00000000)
1141 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_ONLY          (0x00000001)
1142 #define MPI3_DRIVER0_BSDOPTS_DIS_HII_CONFIG_UTIL            (0x00000004)
1143 #define MPI3_DRIVER0_BSDOPTS_EN_ADV_ADAPTER_CONFIG          (0x00000008)
1144 struct mpi3_driver_page1 {
1145         struct mpi3_config_page_header         header;
1146         __le32                             flags;
1147         __le32                             reserved0c;
1148         __le16                             host_diag_trace_max_size;
1149         __le16                             host_diag_trace_min_size;
1150         __le16                             host_diag_trace_decrement_size;
1151         __le16                             reserved16;
1152         __le16                             host_diag_fw_max_size;
1153         __le16                             host_diag_fw_min_size;
1154         __le16                             host_diag_fw_decrement_size;
1155         __le16                             reserved1e;
1156         __le16                             host_diag_driver_max_size;
1157         __le16                             host_diag_driver_min_size;
1158         __le16                             host_diag_driver_decrement_size;
1159         __le16                             reserved26;
1160 };
1161
1162 #define MPI3_DRIVER1_PAGEVERSION               (0x00)
1163 #ifndef MPI3_DRIVER2_TRIGGER_MAX
1164 #define MPI3_DRIVER2_TRIGGER_MAX           (1)
1165 #endif
1166 struct mpi3_driver2_trigger_event {
1167         u8                                 type;
1168         u8                                 flags;
1169         u8                                 reserved02;
1170         u8                                 event;
1171         __le32                             reserved04[3];
1172 };
1173
1174 struct mpi3_driver2_trigger_scsi_sense {
1175         u8                                 type;
1176         u8                                 flags;
1177         __le16                             reserved02;
1178         u8                                 ascq;
1179         u8                                 asc;
1180         u8                                 sense_key;
1181         u8                                 reserved07;
1182         __le32                             reserved08[2];
1183 };
1184
1185 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASCQ_MATCH_ALL                        (0xff)
1186 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASC_MATCH_ALL                         (0xff)
1187 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_SENSE_KEY_MATCH_ALL                   (0xff)
1188 struct mpi3_driver2_trigger_reply {
1189         u8                                 type;
1190         u8                                 flags;
1191         __le16                             ioc_status;
1192         __le32                             ioc_log_info;
1193         __le32                             ioc_log_info_mask;
1194         __le32                             reserved0c;
1195 };
1196
1197 #define MPI3_DRIVER2_TRIGGER_REPLY_IOCSTATUS_MATCH_ALL                        (0xffff)
1198 union mpi3_driver2_trigger_element {
1199         struct mpi3_driver2_trigger_event             event;
1200         struct mpi3_driver2_trigger_scsi_sense        scsi_sense;
1201         struct mpi3_driver2_trigger_reply             reply;
1202 };
1203
1204 #define MPI3_DRIVER2_TRIGGER_TYPE_EVENT                                       (0x00)
1205 #define MPI3_DRIVER2_TRIGGER_TYPE_SCSI_SENSE                                  (0x01)
1206 #define MPI3_DRIVER2_TRIGGER_TYPE_REPLY                                       (0x02)
1207 #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_TRACE_RELEASE                         (0x02)
1208 #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_FW_RELEASE                            (0x01)
1209 struct mpi3_driver_page2 {
1210         struct mpi3_config_page_header         header;
1211         __le64                             master_trigger;
1212         __le32                             reserved10[3];
1213         u8                                 num_triggers;
1214         u8                                 reserved1d[3];
1215         union mpi3_driver2_trigger_element    trigger[MPI3_DRIVER2_TRIGGER_MAX];
1216 };
1217
1218 #define MPI3_DRIVER2_PAGEVERSION               (0x00)
1219 #define MPI3_DRIVER2_MASTERTRIGGER_DIAG_TRACE_RELEASE                       (0x8000000000000000ULL)
1220 #define MPI3_DRIVER2_MASTERTRIGGER_DIAG_FW_RELEASE                          (0x4000000000000000ULL)
1221 #define MPI3_DRIVER2_MASTERTRIGGER_SNAPDUMP                                 (0x2000000000000000ULL)
1222 #define MPI3_DRIVER2_MASTERTRIGGER_DEVICE_REMOVAL_ENABLED                   (0x0000000000000004ULL)
1223 #define MPI3_DRIVER2_MASTERTRIGGER_TASK_MANAGEMENT_ENABLED                  (0x0000000000000002ULL)
1224 struct mpi3_driver_page10 {
1225         struct mpi3_config_page_header         header;
1226         __le16                             flags;
1227         __le16                             reserved0a;
1228         u8                                 num_allowed_commands;
1229         u8                                 reserved0d[3];
1230         union mpi3_allowed_cmd                allowed_command[MPI3_ALLOWED_CMDS_MAX];
1231 };
1232
1233 #define MPI3_DRIVER10_PAGEVERSION               (0x00)
1234 struct mpi3_driver_page20 {
1235         struct mpi3_config_page_header         header;
1236         __le16                             flags;
1237         __le16                             reserved0a;
1238         u8                                 num_allowed_commands;
1239         u8                                 reserved0d[3];
1240         union mpi3_allowed_cmd                allowed_command[MPI3_ALLOWED_CMDS_MAX];
1241 };
1242
1243 #define MPI3_DRIVER20_PAGEVERSION               (0x00)
1244 struct mpi3_driver_page30 {
1245         struct mpi3_config_page_header         header;
1246         __le16                             flags;
1247         __le16                             reserved0a;
1248         u8                                 num_allowed_commands;
1249         u8                                 reserved0d[3];
1250         union mpi3_allowed_cmd                allowed_command[MPI3_ALLOWED_CMDS_MAX];
1251 };
1252
1253 #define MPI3_DRIVER30_PAGEVERSION               (0x00)
1254 union mpi3_security_mac {
1255         __le32                             dword[16];
1256         __le16                             word[32];
1257         u8                                 byte[64];
1258 };
1259
1260 union mpi3_security_nonce {
1261         __le32                             dword[16];
1262         __le16                             word[32];
1263         u8                                 byte[64];
1264 };
1265
1266 union mpi3_security0_cert_chain {
1267         __le32                             dword[1024];
1268         __le16                             word[2048];
1269         u8                                 byte[4096];
1270 };
1271
1272 struct mpi3_security_page0 {
1273         struct mpi3_config_page_header         header;
1274         u8                                 slot_num_group;
1275         u8                                 slot_num;
1276         __le16                             cert_chain_length;
1277         u8                                 cert_chain_flags;
1278         u8                                 reserved0d[3];
1279         __le32                             base_asym_algo;
1280         __le32                             base_hash_algo;
1281         __le32                             reserved18[4];
1282         union mpi3_security_mac               mac;
1283         union mpi3_security_nonce             nonce;
1284         union mpi3_security0_cert_chain       certificate_chain;
1285 };
1286
1287 #define MPI3_SECURITY0_PAGEVERSION               (0x00)
1288 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_MASK       (0x0e)
1289 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_UNUSED     (0x00)
1290 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_CERBERUS   (0x02)
1291 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_SPDM       (0x04)
1292 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_SEALED              (0x01)
1293 #ifndef MPI3_SECURITY1_KEY_RECORD_MAX
1294 #define MPI3_SECURITY1_KEY_RECORD_MAX      1
1295 #endif
1296 #ifndef MPI3_SECURITY1_PAD_MAX
1297 #define MPI3_SECURITY1_PAD_MAX      1
1298 #endif
1299 union mpi3_security1_key_data {
1300         __le32                             dword[128];
1301         __le16                             word[256];
1302         u8                                 byte[512];
1303 };
1304
1305 struct mpi3_security1_key_record {
1306         u8                                 flags;
1307         u8                                 consumer;
1308         __le16                             key_data_size;
1309         __le32                             additional_key_data;
1310         __le32                             reserved08[2];
1311         union mpi3_security1_key_data         key_data;
1312 };
1313
1314 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_MASK            (0x1f)
1315 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_NOT_VALID       (0x00)
1316 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_HMAC            (0x01)
1317 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_AES             (0x02)
1318 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PRIVATE   (0x03)
1319 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PUBLIC    (0x04)
1320 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_NOT_VALID         (0x00)
1321 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_SAFESTORE         (0x01)
1322 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CERT_CHAIN        (0x02)
1323 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_DEVICE_KEY        (0x03)
1324 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CACHE_OFFLOAD     (0x04)
1325 struct mpi3_security_page1 {
1326         struct mpi3_config_page_header         header;
1327         __le32                             reserved08[2];
1328         union mpi3_security_mac               mac;
1329         union mpi3_security_nonce             nonce;
1330         u8                                 num_keys;
1331         u8                                 reserved91[3];
1332         __le32                             reserved94[3];
1333         struct mpi3_security1_key_record       key_record[MPI3_SECURITY1_KEY_RECORD_MAX];
1334         u8                                 pad[MPI3_SECURITY1_PAD_MAX];
1335 };
1336
1337 #define MPI3_SECURITY1_PAGEVERSION               (0x00)
1338 struct mpi3_sas_io_unit0_phy_data {
1339         u8                 io_unit_port;
1340         u8                 port_flags;
1341         u8                 phy_flags;
1342         u8                 negotiated_link_rate;
1343         __le16             controller_phy_device_info;
1344         __le16             reserved06;
1345         __le16             attached_dev_handle;
1346         __le16             controller_dev_handle;
1347         __le32             discovery_status;
1348         __le32             reserved10;
1349 };
1350
1351 #ifndef MPI3_SAS_IO_UNIT0_PHY_MAX
1352 #define MPI3_SAS_IO_UNIT0_PHY_MAX           (1)
1353 #endif
1354 struct mpi3_sas_io_unit_page0 {
1355         struct mpi3_config_page_header         header;
1356         __le32                             reserved08;
1357         u8                                 num_phys;
1358         u8                                 init_status;
1359         __le16                             reserved0e;
1360         struct mpi3_sas_io_unit0_phy_data      phy_data[MPI3_SAS_IO_UNIT0_PHY_MAX];
1361 };
1362
1363 #define MPI3_SASIOUNIT0_PAGEVERSION                          (0x00)
1364 #define MPI3_SASIOUNIT0_INITSTATUS_NO_ERRORS                 (0x00)
1365 #define MPI3_SASIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION      (0x01)
1366 #define MPI3_SASIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED      (0x02)
1367 #define MPI3_SASIOUNIT0_INITSTATUS_BAD_NUM_PHYS              (0x04)
1368 #define MPI3_SASIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG        (0x05)
1369 #define MPI3_SASIOUNIT0_INITSTATUS_HOST_PHYS_ENABLED         (0x06)
1370 #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MIN      (0xf0)
1371 #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MAX      (0xff)
1372 #define MPI3_SASIOUNIT0_PORTFLAGS_DISC_IN_PROGRESS           (0x08)
1373 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_MASK      (0x03)
1374 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_IOUNIT1   (0x00)
1375 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_DYNAMIC   (0x01)
1376 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_BACKPLANE (0x02)
1377 #define MPI3_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT        (0x40)
1378 #define MPI3_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT        (0x20)
1379 #define MPI3_SASIOUNIT0_PHYFLAGS_PHY_DISABLED                (0x08)
1380 #define MPI3_SASIOUNIT0_PHYFLAGS_VIRTUAL_PHY                 (0x02)
1381 #define MPI3_SASIOUNIT0_PHYFLAGS_HOST_PHY                    (0x01)
1382 struct mpi3_sas_io_unit1_phy_data {
1383         u8                 io_unit_port;
1384         u8                 port_flags;
1385         u8                 phy_flags;
1386         u8                 max_min_link_rate;
1387         __le16             controller_phy_device_info;
1388         __le16             max_target_port_connect_time;
1389         __le32             reserved08;
1390 };
1391
1392 #ifndef MPI3_SAS_IO_UNIT1_PHY_MAX
1393 #define MPI3_SAS_IO_UNIT1_PHY_MAX           (1)
1394 #endif
1395 struct mpi3_sas_io_unit_page1 {
1396         struct mpi3_config_page_header         header;
1397         __le16                             control_flags;
1398         __le16                             sas_narrow_max_queue_depth;
1399         __le16                             additional_control_flags;
1400         __le16                             sas_wide_max_queue_depth;
1401         u8                                 num_phys;
1402         u8                                 sata_max_q_depth;
1403         __le16                             reserved12;
1404         struct mpi3_sas_io_unit1_phy_data      phy_data[MPI3_SAS_IO_UNIT1_PHY_MAX];
1405 };
1406
1407 #define MPI3_SASIOUNIT1_PAGEVERSION                                 (0x00)
1408 #define MPI3_SASIOUNIT1_CONTROL_CONTROLLER_DEVICE_SELF_TEST         (0x8000)
1409 #define MPI3_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE                    (0x1000)
1410 #define MPI3_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED             (0x0080)
1411 #define MPI3_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED                 (0x0040)
1412 #define MPI3_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED                   (0x0020)
1413 #define MPI3_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED                   (0x0010)
1414 #define MPI3_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL           (0x0008)
1415 #define MPI3_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL                 (0x0004)
1416 #define MPI3_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY                 (0x0002)
1417 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_MASK                     (0x0001)
1418 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_DEVICE_NAME              (0x0000)
1419 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_SAS_ADDRESS              (0x0001)
1420 #define MPI3_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT                 (0x0100)
1421 #define MPI3_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL          (0x0080)
1422 #define MPI3_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION    (0x0040)
1423 #define MPI3_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION        (0x0020)
1424 #define MPI3_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET   (0x0010)
1425 #define MPI3_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET  (0x0008)
1426 #define MPI3_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET   (0x0004)
1427 #define MPI3_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET     (0x0002)
1428 #define MPI3_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE               (0x0001)
1429 #define MPI3_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG                 (0x01)
1430 #define MPI3_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT               (0x40)
1431 #define MPI3_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT               (0x20)
1432 #define MPI3_SASIOUNIT1_PHYFLAGS_PHY_DISABLE                        (0x08)
1433 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_MASK                          (0xf0)
1434 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_SHIFT                         (4)
1435 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_6_0                           (0xa0)
1436 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_12_0                          (0xb0)
1437 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_22_5                          (0xc0)
1438 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_MASK                          (0x0f)
1439 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_6_0                           (0x0a)
1440 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_12_0                          (0x0b)
1441 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_22_5                          (0x0c)
1442 struct mpi3_sas_io_unit2_phy_pm_settings {
1443         u8                 control_flags;
1444         u8                 reserved01;
1445         __le16             inactivity_timer_exponent;
1446         u8                 sata_partial_timeout;
1447         u8                 reserved05;
1448         u8                 sata_slumber_timeout;
1449         u8                 reserved07;
1450         u8                 sas_partial_timeout;
1451         u8                 reserved09;
1452         u8                 sas_slumber_timeout;
1453         u8                 reserved0b;
1454 };
1455
1456 #ifndef MPI3_SAS_IO_UNIT2_PHY_MAX
1457 #define MPI3_SAS_IO_UNIT2_PHY_MAX           (1)
1458 #endif
1459 struct mpi3_sas_io_unit_page2 {
1460         struct mpi3_config_page_header             header;
1461         u8                                     num_phys;
1462         u8                                     reserved09[3];
1463         __le32                                 reserved0c;
1464         struct mpi3_sas_io_unit2_phy_pm_settings   sas_phy_power_management_settings[MPI3_SAS_IO_UNIT2_PHY_MAX];
1465 };
1466
1467 #define MPI3_SASIOUNIT2_PAGEVERSION                     (0x00)
1468 #define MPI3_SASIOUNIT2_CONTROL_SAS_SLUMBER_ENABLE      (0x08)
1469 #define MPI3_SASIOUNIT2_CONTROL_SAS_PARTIAL_ENABLE      (0x04)
1470 #define MPI3_SASIOUNIT2_CONTROL_SATA_SLUMBER_ENABLE     (0x02)
1471 #define MPI3_SASIOUNIT2_CONTROL_SATA_PARTIAL_ENABLE     (0x01)
1472 #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_MASK            (0x7000)
1473 #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_SHIFT           (12)
1474 #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_MASK            (0x0700)
1475 #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_SHIFT           (8)
1476 #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_MASK           (0x0070)
1477 #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_SHIFT          (4)
1478 #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_MASK           (0x0007)
1479 #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_SHIFT          (0)
1480 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_SECONDS             (7)
1481 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_SECOND              (6)
1482 #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MILLISECONDS    (5)
1483 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MILLISECONDS        (4)
1484 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MILLISECOND         (3)
1485 #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MICROSECONDS    (2)
1486 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MICROSECONDS        (1)
1487 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MICROSECOND         (0)
1488 struct mpi3_sas_io_unit_page3 {
1489         struct mpi3_config_page_header         header;
1490         __le32                             reserved08;
1491         __le32                             power_management_capabilities;
1492 };
1493
1494 #define MPI3_SASIOUNIT3_PAGEVERSION                     (0x00)
1495 #define MPI3_SASIOUNIT3_PM_HOST_SAS_SLUMBER_MODE        (0x00000800)
1496 #define MPI3_SASIOUNIT3_PM_HOST_SAS_PARTIAL_MODE        (0x00000400)
1497 #define MPI3_SASIOUNIT3_PM_HOST_SATA_SLUMBER_MODE       (0x00000200)
1498 #define MPI3_SASIOUNIT3_PM_HOST_SATA_PARTIAL_MODE       (0x00000100)
1499 #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_SLUMBER_MODE      (0x00000008)
1500 #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_PARTIAL_MODE      (0x00000004)
1501 #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_SLUMBER_MODE     (0x00000002)
1502 #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_PARTIAL_MODE     (0x00000001)
1503 struct mpi3_sas_expander_page0 {
1504         struct mpi3_config_page_header         header;
1505         u8                                 io_unit_port;
1506         u8                                 report_gen_length;
1507         __le16                             enclosure_handle;
1508         __le32                             reserved0c;
1509         __le64                             sas_address;
1510         __le32                             discovery_status;
1511         __le16                             dev_handle;
1512         __le16                             parent_dev_handle;
1513         __le16                             expander_change_count;
1514         __le16                             expander_route_indexes;
1515         u8                                 num_phys;
1516         u8                                 sas_level;
1517         __le16                             flags;
1518         __le16                             stp_bus_inactivity_time_limit;
1519         __le16                             stp_max_connect_time_limit;
1520         __le16                             stp_smp_nexus_loss_time;
1521         __le16                             max_num_routed_sas_addresses;
1522         __le64                             active_zone_manager_sas_address;
1523         __le16                             zone_lock_inactivity_limit;
1524         __le16                             reserved3a;
1525         u8                                 time_to_reduced_func;
1526         u8                                 initial_time_to_reduced_func;
1527         u8                                 max_reduced_func_time;
1528         u8                                 exp_status;
1529 };
1530
1531 #define MPI3_SASEXPANDER0_PAGEVERSION                       (0x00)
1532 #define MPI3_SASEXPANDER0_FLAGS_REDUCED_FUNCTIONALITY       (0x2000)
1533 #define MPI3_SASEXPANDER0_FLAGS_ZONE_LOCKED                 (0x1000)
1534 #define MPI3_SASEXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES     (0x0800)
1535 #define MPI3_SASEXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES      (0x0400)
1536 #define MPI3_SASEXPANDER0_FLAGS_ZONING_SUPPORT              (0x0200)
1537 #define MPI3_SASEXPANDER0_FLAGS_ENABLED_ZONING              (0x0100)
1538 #define MPI3_SASEXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT      (0x0080)
1539 #define MPI3_SASEXPANDER0_FLAGS_CONNECTOR_END_DEVICE        (0x0010)
1540 #define MPI3_SASEXPANDER0_FLAGS_OTHERS_CONFIG               (0x0004)
1541 #define MPI3_SASEXPANDER0_FLAGS_CONFIG_IN_PROGRESS          (0x0002)
1542 #define MPI3_SASEXPANDER0_FLAGS_ROUTE_TABLE_CONFIG          (0x0001)
1543 #define MPI3_SASEXPANDER0_ES_NOT_RESPONDING                 (0x02)
1544 #define MPI3_SASEXPANDER0_ES_RESPONDING                     (0x03)
1545 #define MPI3_SASEXPANDER0_ES_DELAY_NOT_RESPONDING           (0x04)
1546 struct mpi3_sas_expander_page1 {
1547         struct mpi3_config_page_header         header;
1548         u8                                 io_unit_port;
1549         u8                                 reserved09[3];
1550         u8                                 num_phys;
1551         u8                                 phy;
1552         __le16                             num_table_entries_programmed;
1553         u8                                 programmed_link_rate;
1554         u8                                 hw_link_rate;
1555         __le16                             attached_dev_handle;
1556         __le32                             phy_info;
1557         __le16                             attached_device_info;
1558         __le16                             reserved1a;
1559         __le16                             expander_dev_handle;
1560         u8                                 change_count;
1561         u8                                 negotiated_link_rate;
1562         u8                                 phy_identifier;
1563         u8                                 attached_phy_identifier;
1564         u8                                 reserved22;
1565         u8                                 discovery_info;
1566         __le32                             attached_phy_info;
1567         u8                                 zone_group;
1568         u8                                 self_config_status;
1569         __le16                             reserved2a;
1570         __le16                             slot;
1571         __le16                             slot_index;
1572 };
1573
1574 #define MPI3_SASEXPANDER1_PAGEVERSION                   (0x00)
1575 #define MPI3_SASEXPANDER1_DISCINFO_BAD_PHY_DISABLED     (0x04)
1576 #define MPI3_SASEXPANDER1_DISCINFO_LINK_STATUS_CHANGE   (0x02)
1577 #define MPI3_SASEXPANDER1_DISCINFO_NO_ROUTING_ENTRIES   (0x01)
1578 #ifndef MPI3_SASEXPANDER2_MAX_NUM_PHYS
1579 #define MPI3_SASEXPANDER2_MAX_NUM_PHYS                               (1)
1580 #endif
1581 struct mpi3_sasexpander2_phy_element {
1582         u8                                 link_change_count;
1583         u8                                 reserved01;
1584         __le16                             rate_change_count;
1585         __le32                             reserved04;
1586 };
1587
1588 struct mpi3_sas_expander_page2 {
1589         struct mpi3_config_page_header         header;
1590         u8                                 num_phys;
1591         u8                                 reserved09;
1592         __le16                             dev_handle;
1593         __le32                             reserved0c;
1594         struct mpi3_sasexpander2_phy_element   phy[MPI3_SASEXPANDER2_MAX_NUM_PHYS];
1595 };
1596
1597 #define MPI3_SASEXPANDER2_PAGEVERSION                   (0x00)
1598 struct mpi3_sas_port_page0 {
1599         struct mpi3_config_page_header         header;
1600         u8                                 port_number;
1601         u8                                 reserved09;
1602         u8                                 port_width;
1603         u8                                 reserved0b;
1604         u8                                 zone_group;
1605         u8                                 reserved0d[3];
1606         __le64                             sas_address;
1607         __le16                             device_info;
1608         __le16                             reserved1a;
1609         __le32                             reserved1c;
1610 };
1611
1612 #define MPI3_SASPORT0_PAGEVERSION                       (0x00)
1613 struct mpi3_sas_phy_page0 {
1614         struct mpi3_config_page_header         header;
1615         __le16                             owner_dev_handle;
1616         __le16                             reserved0a;
1617         __le16                             attached_dev_handle;
1618         u8                                 attached_phy_identifier;
1619         u8                                 reserved0f;
1620         __le32                             attached_phy_info;
1621         u8                                 programmed_link_rate;
1622         u8                                 hw_link_rate;
1623         u8                                 change_count;
1624         u8                                 flags;
1625         __le32                             phy_info;
1626         u8                                 negotiated_link_rate;
1627         u8                                 reserved1d[3];
1628         __le16                             slot;
1629         __le16                             slot_index;
1630 };
1631
1632 #define MPI3_SASPHY0_PAGEVERSION                        (0x00)
1633 #define MPI3_SASPHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC      (0x01)
1634 struct mpi3_sas_phy_page1 {
1635         struct mpi3_config_page_header         header;
1636         __le32                             reserved08;
1637         __le32                             invalid_dword_count;
1638         __le32                             running_disparity_error_count;
1639         __le32                             loss_dword_synch_count;
1640         __le32                             phy_reset_problem_count;
1641 };
1642
1643 #define MPI3_SASPHY1_PAGEVERSION                        (0x00)
1644 struct mpi3_sas_phy2_phy_event {
1645         u8         phy_event_code;
1646         u8         reserved01[3];
1647         __le32     phy_event_info;
1648 };
1649
1650 #ifndef MPI3_SAS_PHY2_PHY_EVENT_MAX
1651 #define MPI3_SAS_PHY2_PHY_EVENT_MAX         (1)
1652 #endif
1653 struct mpi3_sas_phy_page2 {
1654         struct mpi3_config_page_header         header;
1655         __le32                             reserved08;
1656         u8                                 num_phy_events;
1657         u8                                 reserved0d[3];
1658         struct mpi3_sas_phy2_phy_event         phy_event[MPI3_SAS_PHY2_PHY_EVENT_MAX];
1659 };
1660
1661 #define MPI3_SASPHY2_PAGEVERSION                        (0x00)
1662 struct mpi3_sas_phy3_phy_event_config {
1663         u8         phy_event_code;
1664         u8         reserved01[3];
1665         u8         counter_type;
1666         u8         threshold_window;
1667         u8         time_units;
1668         u8         reserved07;
1669         __le32     event_threshold;
1670         __le16     threshold_flags;
1671         __le16     reserved0e;
1672 };
1673
1674 #define MPI3_SASPHY3_EVENT_CODE_NO_EVENT                    (0x00)
1675 #define MPI3_SASPHY3_EVENT_CODE_INVALID_DWORD               (0x01)
1676 #define MPI3_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR     (0x02)
1677 #define MPI3_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC             (0x03)
1678 #define MPI3_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM           (0x04)
1679 #define MPI3_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW     (0x05)
1680 #define MPI3_SASPHY3_EVENT_CODE_RX_ERROR                    (0x06)
1681 #define MPI3_SASPHY3_EVENT_CODE_INV_SPL_PACKETS             (0x07)
1682 #define MPI3_SASPHY3_EVENT_CODE_LOSS_SPL_PACKET_SYNC        (0x08)
1683 #define MPI3_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR         (0x20)
1684 #define MPI3_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT           (0x21)
1685 #define MPI3_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT           (0x22)
1686 #define MPI3_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT           (0x23)
1687 #define MPI3_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT           (0x24)
1688 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON   (0x25)
1689 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON   (0x26)
1690 #define MPI3_SASPHY3_EVENT_CODE_TX_BREAK                    (0x27)
1691 #define MPI3_SASPHY3_EVENT_CODE_RX_BREAK                    (0x28)
1692 #define MPI3_SASPHY3_EVENT_CODE_BREAK_TIMEOUT               (0x29)
1693 #define MPI3_SASPHY3_EVENT_CODE_CONNECTION                  (0x2a)
1694 #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED      (0x2b)
1695 #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME        (0x2c)
1696 #define MPI3_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME          (0x2d)
1697 #define MPI3_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME           (0x2e)
1698 #define MPI3_SASPHY3_EVENT_CODE_PERSIST_CONN                (0x2f)
1699 #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_FRAMES               (0x40)
1700 #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_FRAMES               (0x41)
1701 #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES         (0x42)
1702 #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES         (0x43)
1703 #define MPI3_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED           (0x44)
1704 #define MPI3_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED           (0x45)
1705 #define MPI3_SASPHY3_EVENT_CODE_TX_SATA_FRAMES              (0x50)
1706 #define MPI3_SASPHY3_EVENT_CODE_RX_SATA_FRAMES              (0x51)
1707 #define MPI3_SASPHY3_EVENT_CODE_SATA_OVERFLOW               (0x52)
1708 #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_FRAMES               (0x60)
1709 #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_FRAMES               (0x61)
1710 #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES         (0x63)
1711 #define MPI3_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT             (0xd0)
1712 #define MPI3_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE    (0xd1)
1713 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP                      (0xd2)
1714 #define MPI3_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME             (0xd3)
1715 #define MPI3_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME    (0xd4)
1716 #define MPI3_SASPHY3_EVENT_CODE_LCCONN_TIME                 (0xd5)
1717 #define MPI3_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT       (0xd6)
1718 #define MPI3_SASPHY3_EVENT_CODE_SATA_TX_START               (0xd7)
1719 #define MPI3_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT        (0xd8)
1720 #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN           (0xd9)
1721 #define MPI3_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE        (0xda)
1722 #define MPI3_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE       (0xdb)
1723 #define MPI3_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE        (0xdc)
1724 #define MPI3_SASPHY3_COUNTER_TYPE_WRAPPING                  (0x00)
1725 #define MPI3_SASPHY3_COUNTER_TYPE_SATURATING                (0x01)
1726 #define MPI3_SASPHY3_COUNTER_TYPE_PEAK_VALUE                (0x02)
1727 #define MPI3_SASPHY3_TIME_UNITS_10_MICROSECONDS             (0x00)
1728 #define MPI3_SASPHY3_TIME_UNITS_100_MICROSECONDS            (0x01)
1729 #define MPI3_SASPHY3_TIME_UNITS_1_MILLISECOND               (0x02)
1730 #define MPI3_SASPHY3_TIME_UNITS_10_MILLISECONDS             (0x03)
1731 #define MPI3_SASPHY3_TFLAGS_PHY_RESET                       (0x0002)
1732 #define MPI3_SASPHY3_TFLAGS_EVENT_NOTIFY                    (0x0001)
1733 #ifndef MPI3_SAS_PHY3_PHY_EVENT_MAX
1734 #define MPI3_SAS_PHY3_PHY_EVENT_MAX         (1)
1735 #endif
1736 struct mpi3_sas_phy_page3 {
1737         struct mpi3_config_page_header         header;
1738         __le32                             reserved08;
1739         u8                                 num_phy_events;
1740         u8                                 reserved0d[3];
1741         struct mpi3_sas_phy3_phy_event_config  phy_event_config[MPI3_SAS_PHY3_PHY_EVENT_MAX];
1742 };
1743
1744 #define MPI3_SASPHY3_PAGEVERSION                        (0x00)
1745 struct mpi3_sas_phy_page4 {
1746         struct mpi3_config_page_header         header;
1747         u8                                 reserved08[3];
1748         u8                                 flags;
1749         u8                                 initial_frame[28];
1750 };
1751
1752 #define MPI3_SASPHY4_PAGEVERSION                        (0x00)
1753 #define MPI3_SASPHY4_FLAGS_FRAME_VALID                  (0x02)
1754 #define MPI3_SASPHY4_FLAGS_SATA_FRAME                   (0x01)
1755 #define MPI3_PCIE_LINK_RETIMERS_MASK                    (0x30)
1756 #define MPI3_PCIE_LINK_RETIMERS_SHIFT                   (4)
1757 #define MPI3_PCIE_NEG_LINK_RATE_MASK                    (0x0f)
1758 #define MPI3_PCIE_NEG_LINK_RATE_UNKNOWN                 (0x00)
1759 #define MPI3_PCIE_NEG_LINK_RATE_PHY_DISABLED            (0x01)
1760 #define MPI3_PCIE_NEG_LINK_RATE_2_5                     (0x02)
1761 #define MPI3_PCIE_NEG_LINK_RATE_5_0                     (0x03)
1762 #define MPI3_PCIE_NEG_LINK_RATE_8_0                     (0x04)
1763 #define MPI3_PCIE_NEG_LINK_RATE_16_0                    (0x05)
1764 #define MPI3_PCIE_NEG_LINK_RATE_32_0                    (0x06)
1765 #define MPI3_PCIE_ASPM_ENABLE_NONE                      (0x0)
1766 #define MPI3_PCIE_ASPM_ENABLE_L0S                       (0x1)
1767 #define MPI3_PCIE_ASPM_ENABLE_L1                        (0x2)
1768 #define MPI3_PCIE_ASPM_ENABLE_L0S_L1                    (0x3)
1769 #define MPI3_PCIE_ASPM_SUPPORT_NONE                     (0x0)
1770 #define MPI3_PCIE_ASPM_SUPPORT_L0S                      (0x1)
1771 #define MPI3_PCIE_ASPM_SUPPORT_L1                       (0x2)
1772 #define MPI3_PCIE_ASPM_SUPPORT_L0S_L1                   (0x3)
1773 struct mpi3_pcie_io_unit0_phy_data {
1774         u8         link;
1775         u8         link_flags;
1776         u8         phy_flags;
1777         u8         negotiated_link_rate;
1778         __le16     attached_dev_handle;
1779         __le16     controller_dev_handle;
1780         __le32     enumeration_status;
1781         u8         io_unit_port;
1782         u8         reserved0d[3];
1783 };
1784
1785 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_MASK      (0x10)
1786 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_IOUNIT1   (0x00)
1787 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_BKPLANE   (0x10)
1788 #define MPI3_PCIEIOUNIT0_LINKFLAGS_ENUM_IN_PROGRESS        (0x08)
1789 #define MPI3_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED          (0x08)
1790 #define MPI3_PCIEIOUNIT0_PHYFLAGS_HOST_PHY              (0x01)
1791 #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCH_DEPTH_EXCEEDED   (0x80000000)
1792 #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED       (0x40000000)
1793 #define MPI3_PCIEIOUNIT0_ES_MAX_ENDPOINTS_EXCEEDED      (0x20000000)
1794 #define MPI3_PCIEIOUNIT0_ES_INSUFFICIENT_RESOURCES      (0x10000000)
1795 #ifndef MPI3_PCIE_IO_UNIT0_PHY_MAX
1796 #define MPI3_PCIE_IO_UNIT0_PHY_MAX      (1)
1797 #endif
1798 struct mpi3_pcie_io_unit_page0 {
1799         struct mpi3_config_page_header         header;
1800         __le32                             reserved08;
1801         u8                                 num_phys;
1802         u8                                 init_status;
1803         u8                                 aspm;
1804         u8                                 reserved0f;
1805         struct mpi3_pcie_io_unit0_phy_data     phy_data[MPI3_PCIE_IO_UNIT0_PHY_MAX];
1806 };
1807
1808 #define MPI3_PCIEIOUNIT0_PAGEVERSION                        (0x00)
1809 #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_ERRORS               (0x00)
1810 #define MPI3_PCIEIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION    (0x01)
1811 #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED    (0x02)
1812 #define MPI3_PCIEIOUNIT0_INITSTATUS_RESOURCE_ALLOC_FAILED   (0x03)
1813 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_NUM_PHYS            (0x04)
1814 #define MPI3_PCIEIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG      (0x05)
1815 #define MPI3_PCIEIOUNIT0_INITSTATUS_HOST_PORT_MISMATCH      (0x06)
1816 #define MPI3_PCIEIOUNIT0_INITSTATUS_PHYS_NOT_CONSECUTIVE    (0x07)
1817 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_CLOCKING_MODE       (0x08)
1818 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_START         (0xf0)
1819 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_END           (0xff)
1820 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_MASK            (0xc0)
1821 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_SHIFT              (6)
1822 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_MASK            (0x30)
1823 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_SHIFT              (4)
1824 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_MASK           (0x0c)
1825 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_SHIFT             (2)
1826 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_MASK           (0x03)
1827 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_SHIFT             (0)
1828 struct mpi3_pcie_io_unit1_phy_data {
1829         u8         link;
1830         u8         link_flags;
1831         u8         phy_flags;
1832         u8         max_min_link_rate;
1833         __le32     reserved04;
1834         __le32     reserved08;
1835 };
1836
1837 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_MASK                     (0x03)
1838 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_DIS_SEPARATE_REFCLK      (0x00)
1839 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRIS                  (0x01)
1840 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRNS                  (0x02)
1841 #define MPI3_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE                             (0x08)
1842 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_MASK                               (0xf0)
1843 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_SHIFT                                 (4)
1844 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_2_5                                (0x20)
1845 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_5_0                                (0x30)
1846 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_8_0                                (0x40)
1847 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_16_0                               (0x50)
1848 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_32_0                               (0x60)
1849 #ifndef MPI3_PCIE_IO_UNIT1_PHY_MAX
1850 #define MPI3_PCIE_IO_UNIT1_PHY_MAX                                           (1)
1851 #endif
1852 struct mpi3_pcie_io_unit_page1 {
1853         struct mpi3_config_page_header         header;
1854         __le32                             control_flags;
1855         __le32                             reserved0c;
1856         u8                                 num_phys;
1857         u8                                 reserved11;
1858         u8                                 aspm;
1859         u8                                 reserved13;
1860         struct mpi3_pcie_io_unit1_phy_data     phy_data[MPI3_PCIE_IO_UNIT1_PHY_MAX];
1861 };
1862
1863 #define MPI3_PCIEIOUNIT1_PAGEVERSION                                           (0x00)
1864 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_OVERRIDE_DISABLE                   (0x80)
1865 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_DISABLE                  (0x40)
1866 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_MASK                (0x30)
1867 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SHIFT               (4)
1868 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_SRNS_DISABLED  (0x00)
1869 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_ENABLED        (0x10)
1870 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRNS_ENABLED        (0x20)
1871 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MASK                 (0x0f)
1872 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_2_5              (0x02)
1873 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_5_0              (0x03)
1874 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_8_0              (0x04)
1875 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_16_0             (0x05)
1876 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_32_0             (0x06)
1877 #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_MASK                                 (0x0c)
1878 #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_SHIFT                                   (2)
1879 #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_MASK                                 (0x03)
1880 #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_SHIFT                                   (0)
1881 struct mpi3_pcie_io_unit_page2 {
1882         struct mpi3_config_page_header         header;
1883         __le16                             nvme_max_q_dx1;
1884         __le16                             nvme_max_q_dx2;
1885         u8                                 nvme_abort_to;
1886         u8                                 reserved0d;
1887         __le16                             nvme_max_q_dx4;
1888 };
1889
1890 #define MPI3_PCIEIOUNIT2_PAGEVERSION                        (0x00)
1891 #define MPI3_PCIEIOUNIT3_ERROR_RECEIVER_ERROR               (0)
1892 #define MPI3_PCIEIOUNIT3_ERROR_RECOVERY                     (1)
1893 #define MPI3_PCIEIOUNIT3_ERROR_CORRECTABLE_ERROR_MSG        (2)
1894 #define MPI3_PCIEIOUNIT3_ERROR_BAD_DLLP                     (3)
1895 #define MPI3_PCIEIOUNIT3_ERROR_BAD_TLP                      (4)
1896 #define MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX                    (5)
1897 struct mpi3_pcie_io_unit3_error {
1898         __le16                             threshold_count;
1899         __le16                             reserved02;
1900 };
1901
1902 struct mpi3_pcie_io_unit_page3 {
1903         struct mpi3_config_page_header         header;
1904         u8                                 threshold_window;
1905         u8                                 threshold_action;
1906         u8                                 escalation_count;
1907         u8                                 escalation_action;
1908         u8                                 num_errors;
1909         u8                                 reserved0d[3];
1910         struct mpi3_pcie_io_unit3_error        error[MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX];
1911 };
1912
1913 #define MPI3_PCIEIOUNIT3_PAGEVERSION                        (0x00)
1914 #define MPI3_PCIEIOUNIT3_ACTION_NO_ACTION                   (0x00)
1915 #define MPI3_PCIEIOUNIT3_ACTION_HOT_RESET                   (0x01)
1916 #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_ONLY       (0x02)
1917 #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_NO_ACCESS  (0x03)
1918 struct mpi3_pcie_switch_page0 {
1919         struct mpi3_config_page_header     header;
1920         u8                             io_unit_port;
1921         u8                             switch_status;
1922         u8                             reserved0a[2];
1923         __le16                         dev_handle;
1924         __le16                         parent_dev_handle;
1925         u8                             num_ports;
1926         u8                             pcie_level;
1927         __le16                         reserved12;
1928         __le32                         reserved14;
1929         __le32                         reserved18;
1930         __le32                         reserved1c;
1931 };
1932
1933 #define MPI3_PCIESWITCH0_PAGEVERSION                  (0x00)
1934 #define MPI3_PCIESWITCH0_SS_NOT_RESPONDING            (0x02)
1935 #define MPI3_PCIESWITCH0_SS_RESPONDING                (0x03)
1936 #define MPI3_PCIESWITCH0_SS_DELAY_NOT_RESPONDING      (0x04)
1937 struct mpi3_pcie_switch_page1 {
1938         struct mpi3_config_page_header     header;
1939         u8                             io_unit_port;
1940         u8                             flags;
1941         __le16                         reserved0a;
1942         u8                             num_ports;
1943         u8                             port_num;
1944         __le16                         attached_dev_handle;
1945         __le16                         switch_dev_handle;
1946         u8                             negotiated_port_width;
1947         u8                             negotiated_link_rate;
1948         __le16                         slot;
1949         __le16                         slot_index;
1950         __le32                         reserved18;
1951 };
1952
1953 #define MPI3_PCIESWITCH1_PAGEVERSION        (0x00)
1954 #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_MASK     (0x0c)
1955 #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_SHIFT    (2)
1956 #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_MASK     (0x03)
1957 #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_SHIFT    (0)
1958 #ifndef MPI3_PCIESWITCH2_MAX_NUM_PORTS
1959 #define MPI3_PCIESWITCH2_MAX_NUM_PORTS                               (1)
1960 #endif
1961 struct mpi3_pcieswitch2_port_element {
1962         __le16                             link_change_count;
1963         __le16                             rate_change_count;
1964         __le32                             reserved04;
1965 };
1966
1967 struct mpi3_pcie_switch_page2 {
1968         struct mpi3_config_page_header         header;
1969         u8                                 num_ports;
1970         u8                                 reserved09;
1971         __le16                             dev_handle;
1972         __le32                             reserved0c;
1973         struct mpi3_pcieswitch2_port_element   port[MPI3_PCIESWITCH2_MAX_NUM_PORTS];
1974 };
1975
1976 #define MPI3_PCIESWITCH2_PAGEVERSION        (0x00)
1977 struct mpi3_pcie_link_page0 {
1978         struct mpi3_config_page_header     header;
1979         u8                             link;
1980         u8                             reserved09[3];
1981         __le32                         reserved0c;
1982         __le32                         receiver_error_count;
1983         __le32                         recovery_count;
1984         __le32                         corr_error_msg_count;
1985         __le32                         non_fatal_error_msg_count;
1986         __le32                         fatal_error_msg_count;
1987         __le32                         non_fatal_error_count;
1988         __le32                         fatal_error_count;
1989         __le32                         bad_dllp_count;
1990         __le32                         bad_tlp_count;
1991 };
1992
1993 #define MPI3_PCIELINK0_PAGEVERSION          (0x00)
1994 struct mpi3_enclosure_page0 {
1995         struct mpi3_config_page_header         header;
1996         __le64                             enclosure_logical_id;
1997         __le16                             flags;
1998         __le16                             enclosure_handle;
1999         __le16                             num_slots;
2000         __le16                             reserved16;
2001         u8                                 io_unit_port;
2002         u8                                 enclosure_level;
2003         __le16                             sep_dev_handle;
2004         u8                                 chassis_slot;
2005         u8                                 reserved1d[3];
2006 };
2007
2008 #define MPI3_ENCLOSURE0_PAGEVERSION                     (0x00)
2009 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_MASK                (0xc000)
2010 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_VIRTUAL             (0x0000)
2011 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_SAS                 (0x4000)
2012 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_PCIE                (0x8000)
2013 #define MPI3_ENCLS0_FLAGS_CHASSIS_SLOT_VALID            (0x0020)
2014 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT_MASK         (0x0010)
2015 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_NOT_FOUND            (0x0000)
2016 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT              (0x0010)
2017 #define MPI3_ENCLS0_FLAGS_MNG_MASK                      (0x000f)
2018 #define MPI3_ENCLS0_FLAGS_MNG_UNKNOWN                   (0x0000)
2019 #define MPI3_ENCLS0_FLAGS_MNG_IOC_SES                   (0x0001)
2020 #define MPI3_ENCLS0_FLAGS_MNG_SES_ENCLOSURE             (0x0002)
2021 #define MPI3_DEVICE_DEVFORM_SAS_SATA                    (0x00)
2022 #define MPI3_DEVICE_DEVFORM_PCIE                        (0x01)
2023 #define MPI3_DEVICE_DEVFORM_VD                          (0x02)
2024 struct mpi3_device0_sas_sata_format {
2025         __le64     sas_address;
2026         __le16     flags;
2027         __le16     device_info;
2028         u8         phy_num;
2029         u8         attached_phy_identifier;
2030         u8         max_port_connections;
2031         u8         zone_group;
2032 };
2033
2034 #define MPI3_DEVICE0_SASSATA_FLAGS_WRITE_SAME_UNMAP_NCQ (0x0400)
2035 #define MPI3_DEVICE0_SASSATA_FLAGS_SLUMBER_CAP          (0x0200)
2036 #define MPI3_DEVICE0_SASSATA_FLAGS_PARTIAL_CAP          (0x0100)
2037 #define MPI3_DEVICE0_SASSATA_FLAGS_ASYNC_NOTIFY         (0x0080)
2038 #define MPI3_DEVICE0_SASSATA_FLAGS_SW_PRESERVE          (0x0040)
2039 #define MPI3_DEVICE0_SASSATA_FLAGS_UNSUPP_DEV           (0x0020)
2040 #define MPI3_DEVICE0_SASSATA_FLAGS_48BIT_LBA            (0x0010)
2041 #define MPI3_DEVICE0_SASSATA_FLAGS_SMART_SUPP           (0x0008)
2042 #define MPI3_DEVICE0_SASSATA_FLAGS_NCQ_SUPP             (0x0004)
2043 #define MPI3_DEVICE0_SASSATA_FLAGS_FUA_SUPP             (0x0002)
2044 #define MPI3_DEVICE0_SASSATA_FLAGS_PERSIST_CAP          (0x0001)
2045 struct mpi3_device0_pcie_format {
2046         u8         supported_link_rates;
2047         u8         max_port_width;
2048         u8         negotiated_port_width;
2049         u8         negotiated_link_rate;
2050         u8         port_num;
2051         u8         controller_reset_to;
2052         __le16     device_info;
2053         __le32     maximum_data_transfer_size;
2054         __le32     capabilities;
2055         __le16     noiob;
2056         u8         nvme_abort_to;
2057         u8         page_size;
2058         __le16     shutdown_latency;
2059         u8         recovery_info;
2060         u8         reserved17;
2061 };
2062
2063 #define MPI3_DEVICE0_PCIE_LINK_RATE_32_0_SUPP           (0x10)
2064 #define MPI3_DEVICE0_PCIE_LINK_RATE_16_0_SUPP           (0x08)
2065 #define MPI3_DEVICE0_PCIE_LINK_RATE_8_0_SUPP            (0x04)
2066 #define MPI3_DEVICE0_PCIE_LINK_RATE_5_0_SUPP            (0x02)
2067 #define MPI3_DEVICE0_PCIE_LINK_RATE_2_5_SUPP            (0x01)
2068 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK             (0x0007)
2069 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NO_DEVICE        (0x0000)
2070 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE      (0x0001)
2071 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SWITCH_DEVICE    (0x0002)
2072 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SCSI_DEVICE      (0x0003)
2073 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_MASK             (0x0030)
2074 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_SHIFT            (4)
2075 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_MASK           (0x00c0)
2076 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_SHIFT          (6)
2077 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_0              (0x0000)
2078 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_1              (0x0040)
2079 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_2              (0x0080)
2080 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_3              (0x00c0)
2081 #define MPI3_DEVICE0_PCIE_CAP_SGL_EXTRA_LENGTH_SUPPORTED    (0x00000020)
2082 #define MPI3_DEVICE0_PCIE_CAP_METADATA_SEPARATED            (0x00000010)
2083 #define MPI3_DEVICE0_PCIE_CAP_SGL_DWORD_ALIGN_REQUIRED      (0x00000008)
2084 #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_SGL                (0x00000004)
2085 #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_PRP                (0x00000000)
2086 #define MPI3_DEVICE0_PCIE_CAP_BIT_BUCKET_SGL_SUPP           (0x00000002)
2087 #define MPI3_DEVICE0_PCIE_CAP_SGL_SUPP                      (0x00000001)
2088 #define MPI3_DEVICE0_PCIE_CAP_ASPM_MASK                     (0x000000c0)
2089 #define MPI3_DEVICE0_PCIE_CAP_ASPM_SHIFT                    (6)
2090 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_MASK               (0xe0)
2091 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_NS_MGMT            (0x00)
2092 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_FORMAT             (0x20)
2093 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_MASK               (0x1f)
2094 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NS              (0x00)
2095 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NSID_1          (0x01)
2096 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_TOO_MANY_NS        (0x02)
2097 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_PROTECTION         (0x03)
2098 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_METADATA_SZ        (0x04)
2099 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_LBA_DATA_SZ        (0x05)
2100 struct mpi3_device0_vd_format {
2101         u8         vd_state;
2102         u8         raid_level;
2103         __le16     device_info;
2104         __le16     flags;
2105         __le16     reserved06;
2106         __le32     reserved08[2];
2107 };
2108
2109 #define MPI3_DEVICE0_VD_STATE_OFFLINE                       (0x00)
2110 #define MPI3_DEVICE0_VD_STATE_PARTIALLY_DEGRADED            (0x01)
2111 #define MPI3_DEVICE0_VD_STATE_DEGRADED                      (0x02)
2112 #define MPI3_DEVICE0_VD_STATE_OPTIMAL                       (0x03)
2113 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_0                    (0)
2114 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_1                    (1)
2115 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_5                    (5)
2116 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_6                    (6)
2117 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_10                   (10)
2118 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_50                   (50)
2119 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_60                   (60)
2120 #define MPI3_DEVICE0_VD_DEVICE_INFO_HDD                     (0x0010)
2121 #define MPI3_DEVICE0_VD_DEVICE_INFO_SSD                     (0x0008)
2122 #define MPI3_DEVICE0_VD_DEVICE_INFO_NVME                    (0x0004)
2123 #define MPI3_DEVICE0_VD_DEVICE_INFO_SATA                    (0x0002)
2124 #define MPI3_DEVICE0_VD_DEVICE_INFO_SAS                     (0x0001)
2125 #define MPI3_DEVICE0_VD_FLAGS_METADATA_MODE_MASK            (0x0003)
2126 #define MPI3_DEVICE0_VD_FLAGS_METADATA_MODE_NONE            (0x0000)
2127 #define MPI3_DEVICE0_VD_FLAGS_METADATA_MODE_HOST            (0x0001)
2128 #define MPI3_DEVICE0_VD_FLAGS_METADATA_MODE_IOC             (0x0002)
2129 union mpi3_device0_dev_spec_format {
2130         struct mpi3_device0_sas_sata_format        sas_sata_format;
2131         struct mpi3_device0_pcie_format            pcie_format;
2132         struct mpi3_device0_vd_format              vd_format;
2133 };
2134
2135 struct mpi3_device_page0 {
2136         struct mpi3_config_page_header         header;
2137         __le16                             dev_handle;
2138         __le16                             parent_dev_handle;
2139         __le16                             slot;
2140         __le16                             enclosure_handle;
2141         __le64                             wwid;
2142         __le16                             persistent_id;
2143         u8                                 io_unit_port;
2144         u8                                 access_status;
2145         __le16                             flags;
2146         __le16                             reserved1e;
2147         __le16                             slot_index;
2148         __le16                             queue_depth;
2149         u8                                 reserved24[3];
2150         u8                                 device_form;
2151         union mpi3_device0_dev_spec_format    device_specific;
2152 };
2153
2154 #define MPI3_DEVICE0_PAGEVERSION                        (0x00)
2155 #define MPI3_DEVICE0_PARENT_INVALID                     (0xffff)
2156 #define MPI3_DEVICE0_ENCLOSURE_HANDLE_NO_ENCLOSURE      (0x0000)
2157 #define MPI3_DEVICE0_WWID_INVALID                       (0xffffffffffffffff)
2158 #define MPI3_DEVICE0_PERSISTENTID_INVALID               (0xffff)
2159 #define MPI3_DEVICE0_IOUNITPORT_INVALID                 (0xff)
2160 #define MPI3_DEVICE0_ASTATUS_NO_ERRORS                              (0x00)
2161 #define MPI3_DEVICE0_ASTATUS_NEEDS_INITIALIZATION                   (0x01)
2162 #define MPI3_DEVICE0_ASTATUS_CAP_UNSUPPORTED                        (0x02)
2163 #define MPI3_DEVICE0_ASTATUS_DEVICE_BLOCKED                         (0x03)
2164 #define MPI3_DEVICE0_ASTATUS_UNAUTHORIZED                           (0x04)
2165 #define MPI3_DEVICE0_ASTATUS_DEVICE_MISSING_DELAY                   (0x05)
2166 #define MPI3_DEVICE0_ASTATUS_PREPARE                                (0x06)
2167 #define MPI3_DEVICE0_ASTATUS_SAFE_MODE                              (0x07)
2168 #define MPI3_DEVICE0_ASTATUS_GENERIC_MAX                            (0x0f)
2169 #define MPI3_DEVICE0_ASTATUS_SAS_UNKNOWN                            (0x10)
2170 #define MPI3_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE                  (0x11)
2171 #define MPI3_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE              (0x12)
2172 #define MPI3_DEVICE0_ASTATUS_SAS_MAX                                (0x1f)
2173 #define MPI3_DEVICE0_ASTATUS_SIF_UNKNOWN                            (0x20)
2174 #define MPI3_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT               (0x21)
2175 #define MPI3_DEVICE0_ASTATUS_SIF_DIAG                               (0x22)
2176 #define MPI3_DEVICE0_ASTATUS_SIF_IDENTIFICATION                     (0x23)
2177 #define MPI3_DEVICE0_ASTATUS_SIF_CHECK_POWER                        (0x24)
2178 #define MPI3_DEVICE0_ASTATUS_SIF_PIO_SN                             (0x25)
2179 #define MPI3_DEVICE0_ASTATUS_SIF_MDMA_SN                            (0x26)
2180 #define MPI3_DEVICE0_ASTATUS_SIF_UDMA_SN                            (0x27)
2181 #define MPI3_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION                   (0x28)
2182 #define MPI3_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE                    (0x29)
2183 #define MPI3_DEVICE0_ASTATUS_SIF_MAX                                (0x2f)
2184 #define MPI3_DEVICE0_ASTATUS_PCIE_UNKNOWN                           (0x30)
2185 #define MPI3_DEVICE0_ASTATUS_PCIE_MEM_SPACE_ACCESS                  (0x31)
2186 #define MPI3_DEVICE0_ASTATUS_PCIE_UNSUPPORTED                       (0x32)
2187 #define MPI3_DEVICE0_ASTATUS_PCIE_MSIX_REQUIRED                     (0x33)
2188 #define MPI3_DEVICE0_ASTATUS_PCIE_ECRC_REQUIRED                     (0x34)
2189 #define MPI3_DEVICE0_ASTATUS_PCIE_MAX                               (0x3f)
2190 #define MPI3_DEVICE0_ASTATUS_NVME_UNKNOWN                           (0x40)
2191 #define MPI3_DEVICE0_ASTATUS_NVME_READY_TIMEOUT                     (0x41)
2192 #define MPI3_DEVICE0_ASTATUS_NVME_DEVCFG_UNSUPPORTED                (0x42)
2193 #define MPI3_DEVICE0_ASTATUS_NVME_IDENTIFY_FAILED                   (0x43)
2194 #define MPI3_DEVICE0_ASTATUS_NVME_QCONFIG_FAILED                    (0x44)
2195 #define MPI3_DEVICE0_ASTATUS_NVME_QCREATION_FAILED                  (0x45)
2196 #define MPI3_DEVICE0_ASTATUS_NVME_EVENTCFG_FAILED                   (0x46)
2197 #define MPI3_DEVICE0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED           (0x47)
2198 #define MPI3_DEVICE0_ASTATUS_NVME_IDLE_TIMEOUT                      (0x48)
2199 #define MPI3_DEVICE0_ASTATUS_NVME_CTRL_FAILURE_STATUS               (0x49)
2200 #define MPI3_DEVICE0_ASTATUS_NVME_INSUFFICIENT_POWER                (0x4a)
2201 #define MPI3_DEVICE0_ASTATUS_NVME_DOORBELL_STRIDE                   (0x4b)
2202 #define MPI3_DEVICE0_ASTATUS_NVME_MEM_PAGE_MIN_SIZE                 (0x4c)
2203 #define MPI3_DEVICE0_ASTATUS_NVME_MEMORY_ALLOCATION                 (0x4d)
2204 #define MPI3_DEVICE0_ASTATUS_NVME_COMPLETION_TIME                   (0x4e)
2205 #define MPI3_DEVICE0_ASTATUS_NVME_BAR                               (0x4f)
2206 #define MPI3_DEVICE0_ASTATUS_NVME_NS_DESCRIPTOR                     (0x50)
2207 #define MPI3_DEVICE0_ASTATUS_NVME_INCOMPATIBLE_SETTINGS             (0x51)
2208 #define MPI3_DEVICE0_ASTATUS_NVME_MAX                               (0x5f)
2209 #define MPI3_DEVICE0_ASTATUS_VD_UNKNOWN                             (0x80)
2210 #define MPI3_DEVICE0_ASTATUS_VD_MAX                                 (0x8f)
2211 #define MPI3_DEVICE0_FLAGS_CONTROLLER_DEV_HANDLE        (0x0080)
2212 #define MPI3_DEVICE0_FLAGS_HIDDEN                       (0x0008)
2213 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_MASK              (0x0006)
2214 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_NOT_DIR_ATTACHED  (0x0000)
2215 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_DIR_ATTACHED      (0x0002)
2216 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_VIRTUAL           (0x0004)
2217 #define MPI3_DEVICE0_FLAGS_DEVICE_PRESENT               (0x0001)
2218 #define MPI3_DEVICE0_QUEUE_DEPTH_NOT_APPLICABLE         (0x0000)
2219 struct mpi3_device1_sas_sata_format {
2220         __le32                             reserved00;
2221 };
2222
2223 struct mpi3_device1_pcie_format {
2224         __le16                             vendor_id;
2225         __le16                             device_id;
2226         __le16                             subsystem_vendor_id;
2227         __le16                             subsystem_id;
2228         __le32                             reserved08;
2229         u8                                 revision_id;
2230         u8                                 reserved0d;
2231         __le16                             pci_parameters;
2232 };
2233
2234 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_128B              (0x0)
2235 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_256B              (0x1)
2236 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_512B              (0x2)
2237 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_1024B             (0x3)
2238 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_2048B             (0x4)
2239 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_4096B             (0x5)
2240 #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_MASK           (0x01c0)
2241 #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_SHIFT          (6)
2242 #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_MASK       (0x0038)
2243 #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_SHIFT      (3)
2244 #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_MASK       (0x0007)
2245 #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_SHIFT      (0)
2246 struct mpi3_device1_vd_format {
2247         __le32                             reserved00;
2248 };
2249
2250 union mpi3_device1_dev_spec_format {
2251         struct mpi3_device1_sas_sata_format    sas_sata_format;
2252         struct mpi3_device1_pcie_format        pcie_format;
2253         struct mpi3_device1_vd_format          vd_format;
2254 };
2255
2256 struct mpi3_device_page1 {
2257         struct mpi3_config_page_header         header;
2258         __le16                             dev_handle;
2259         __le16                             reserved0a;
2260         __le16                             link_change_count;
2261         __le16                             rate_change_count;
2262         __le16                             tm_count;
2263         __le16                             reserved12;
2264         __le32                             reserved14[10];
2265         u8                                 reserved3c[3];
2266         u8                                 device_form;
2267         union mpi3_device1_dev_spec_format    device_specific;
2268 };
2269
2270 #define MPI3_DEVICE1_PAGEVERSION                            (0x00)
2271 #define MPI3_DEVICE1_COUNTER_MAX                            (0xfffe)
2272 #define MPI3_DEVICE1_COUNTER_INVALID                        (0xffff)
2273 #endif