drivers/scsi/mesh.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
   4  * bus adaptor found on Power Macintosh computers.
   5  * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
   6  * controller.
   7  *
   8  * Paul Mackerras, August 1996.
   9  * Copyright (C) 1996 Paul Mackerras.
  10  *
  11  * Apr. 21 2002  - BenH         Rework bus reset code for new error handler
  12  *                              Add delay after initial bus reset
  13  *                              Add module parameters
  14  *
  15  * Sep. 27 2003  - BenH         Move to new driver model, fix some write posting
  16  *                              issues
  17  * To do:
  18  * - handle aborts correctly
  19  * - retry arbitration if lost (unless higher levels do this for us)
  20  * - power down the chip when no device is detected
  21  */
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/delay.h>
  25 #include <linux/types.h>
  26 #include <linux/string.h>
  27 #include <linux/blkdev.h>
  28 #include <linux/proc_fs.h>
  29 #include <linux/stat.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/reboot.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/pci.h>
  34 #include <linux/pgtable.h>
  35 #include <asm/dbdma.h>
  36 #include <asm/io.h>
  37 #include <asm/prom.h>
  38 #include <asm/irq.h>
  39 #include <asm/hydra.h>
  40 #include <asm/processor.h>
  41 #include <asm/machdep.h>
  42 #include <asm/pmac_feature.h>
  43 #include <asm/macio.h>
  44
  45 #include <scsi/scsi.h>
  46 #include <scsi/scsi_cmnd.h>
  47 #include <scsi/scsi_device.h>
  48 #include <scsi/scsi_host.h>
  49
  50 #include "mesh.h"
  51
  52 #if 1
  53 #undef KERN_DEBUG
  54 #define KERN_DEBUG KERN_WARNING
  55 #endif
  56
  57 MODULE_AUTHOR("Paul Mackerras (paulus@samba.org)");
  58 MODULE_DESCRIPTION("PowerMac MESH SCSI driver");
  59 MODULE_LICENSE("GPL");
  60
  61 static int sync_rate = CONFIG_SCSI_MESH_SYNC_RATE;
  62 static int sync_targets = 0xff;
  63 static int resel_targets = 0xff;
  64 static int debug_targets = 0;   /* print debug for these targets */
  65 static int init_reset_delay = CONFIG_SCSI_MESH_RESET_DELAY_MS;
  66
  67 module_param(sync_rate, int, 0);
  68 MODULE_PARM_DESC(sync_rate, "Synchronous rate (0..10, 0=async)");
  69 module_param(sync_targets, int, 0);
  70 MODULE_PARM_DESC(sync_targets, "Bitmask of targets allowed to set synchronous");
  71 module_param(resel_targets, int, 0);
  72 MODULE_PARM_DESC(resel_targets, "Bitmask of targets allowed to set disconnect");
  73 module_param(debug_targets, int, 0644);
  74 MODULE_PARM_DESC(debug_targets, "Bitmask of debugged targets");
  75 module_param(init_reset_delay, int, 0);
  76 MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)");
  77
  78 static int mesh_sync_period = 100;
  79 static int mesh_sync_offset = 0;
  80 static unsigned char use_active_neg = 0;  /* bit mask for SEQ_ACTIVE_NEG if used */
  81
  82 #define ALLOW_SYNC(tgt)         ((sync_targets >> (tgt)) & 1)
  83 #define ALLOW_RESEL(tgt)        ((resel_targets >> (tgt)) & 1)
  84 #define ALLOW_DEBUG(tgt)        ((debug_targets >> (tgt)) & 1)
  85 #define DEBUG_TARGET(cmd)       ((cmd) && ALLOW_DEBUG((cmd)->device->id))
  86
  87 #undef MESH_DBG
  88 #define N_DBG_LOG       50
  89 #define N_DBG_SLOG      20
  90 #define NUM_DBG_EVENTS  13
  91 #undef  DBG_USE_TB              /* bombs on 601 */
  92
  93 struct dbglog {
  94         char    *fmt;
  95         u32     tb;
  96         u8      phase;
  97         u8      bs0;
  98         u8      bs1;
  99         u8      tgt;
 100         int     d;
 101 };
 102
 103 enum mesh_phase {
 104         idle,
 105         arbitrating,
 106         selecting,
 107         commanding,
 108         dataing,
 109         statusing,
 110         busfreeing,
 111         disconnecting,
 112         reselecting,
 113         sleeping
 114 };
 115
 116 enum msg_phase {
 117         msg_none,
 118         msg_out,
 119         msg_out_xxx,
 120         msg_out_last,
 121         msg_in,
 122         msg_in_bad,
 123 };
 124
 125 enum sdtr_phase {
 126         do_sdtr,
 127         sdtr_sent,
 128         sdtr_done
 129 };
 130
 131 struct mesh_target {
 132         enum sdtr_phase sdtr_state;
 133         int     sync_params;
 134         int     data_goes_out;          /* guess as to data direction */
 135         struct scsi_cmnd *current_req;
 136         u32     saved_ptr;
 137 #ifdef MESH_DBG
 138         int     log_ix;
 139         int     n_log;
 140         struct dbglog log[N_DBG_LOG];
 141 #endif
 142 };
 143
 144 struct mesh_state {
 145         volatile struct mesh_regs __iomem *mesh;
 146         int     meshintr;
 147         volatile struct dbdma_regs __iomem *dma;
 148         int     dmaintr;
 149         struct  Scsi_Host *host;
 150         struct  mesh_state *next;
 151         struct scsi_cmnd *request_q;
 152         struct scsi_cmnd *request_qtail;
 153         enum mesh_phase phase;          /* what we're currently trying to do */
 154         enum msg_phase msgphase;
 155         int     conn_tgt;               /* target we're connected to */
 156         struct scsi_cmnd *current_req;          /* req we're currently working on */
 157         int     data_ptr;
 158         int     dma_started;
 159         int     dma_count;
 160         int     stat;
 161         int     aborting;
 162         int     expect_reply;
 163         int     n_msgin;
 164         u8      msgin[16];
 165         int     n_msgout;
 166         int     last_n_msgout;
 167         u8      msgout[16];
 168         struct dbdma_cmd *dma_cmds;     /* space for dbdma commands, aligned */
 169         dma_addr_t dma_cmd_bus;
 170         void    *dma_cmd_space;
 171         int     dma_cmd_size;
 172         int     clk_freq;
 173         struct mesh_target tgts[8];
 174         struct macio_dev *mdev;
 175         struct pci_dev* pdev;
 176 #ifdef MESH_DBG
 177         int     log_ix;
 178         int     n_log;
 179         struct dbglog log[N_DBG_SLOG];
 180 #endif
 181 };
 182
 183 /*
 184  * Driver is too messy, we need a few prototypes...
 185  */
 186 static void mesh_done(struct mesh_state *ms, int start_next);
 187 static void mesh_interrupt(struct mesh_state *ms);
 188 static void cmd_complete(struct mesh_state *ms);
 189 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd);
 190 static void halt_dma(struct mesh_state *ms);
 191 static void phase_mismatch(struct mesh_state *ms);
 192
 193
 194 /*
 195  * Some debugging & logging routines
 196  */
 197
 198 #ifdef MESH_DBG
 199
 200 static inline u32 readtb(void)
 201 {
 202         u32 tb;
 203
 204 #ifdef DBG_USE_TB
 205         /* Beware: if you enable this, it will crash on 601s. */
 206         asm ("mftb %0" : "=r" (tb) : );
 207 #else
 208         tb = 0;
 209 #endif
 210         return tb;
 211 }
 212
 213 static void dlog(struct mesh_state *ms, char *fmt, int a)
 214 {
 215         struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
 216         struct dbglog *tlp, *slp;
 217
 218         tlp = &tp->log[tp->log_ix];
 219         slp = &ms->log[ms->log_ix];
 220         tlp->fmt = fmt;
 221         tlp->tb = readtb();
 222         tlp->phase = (ms->msgphase << 4) + ms->phase;
 223         tlp->bs0 = ms->mesh->bus_status0;
 224         tlp->bs1 = ms->mesh->bus_status1;
 225         tlp->tgt = ms->conn_tgt;
 226         tlp->d = a;
 227         *slp = *tlp;
 228         if (++tp->log_ix >= N_DBG_LOG)
 229                 tp->log_ix = 0;
 230         if (tp->n_log < N_DBG_LOG)
 231                 ++tp->n_log;
 232         if (++ms->log_ix >= N_DBG_SLOG)
 233                 ms->log_ix = 0;
 234         if (ms->n_log < N_DBG_SLOG)
 235                 ++ms->n_log;
 236 }
 237
 238 static void dumplog(struct mesh_state *ms, int t)
 239 {
 240         struct mesh_target *tp = &ms->tgts[t];
 241         struct dbglog *lp;
 242         int i;
 243
 244         if (tp->n_log == 0)
 245                 return;
 246         i = tp->log_ix - tp->n_log;
 247         if (i < 0)
 248                 i += N_DBG_LOG;
 249         tp->n_log = 0;
 250         do {
 251                 lp = &tp->log[i];
 252                 printk(KERN_DEBUG "mesh log %d: bs=%.2x%.2x ph=%.2x ",
 253                        t, lp->bs1, lp->bs0, lp->phase);
 254 #ifdef DBG_USE_TB
 255                 printk("tb=%10u ", lp->tb);
 256 #endif
 257                 printk(lp->fmt, lp->d);
 258                 printk("\n");
 259                 if (++i >= N_DBG_LOG)
 260                         i = 0;
 261         } while (i != tp->log_ix);
 262 }
 263
 264 static void dumpslog(struct mesh_state *ms)
 265 {
 266         struct dbglog *lp;
 267         int i;
 268
 269         if (ms->n_log == 0)
 270                 return;
 271         i = ms->log_ix - ms->n_log;
 272         if (i < 0)
 273                 i += N_DBG_SLOG;
 274         ms->n_log = 0;
 275         do {
 276                 lp = &ms->log[i];
 277                 printk(KERN_DEBUG "mesh log: bs=%.2x%.2x ph=%.2x t%d ",
 278                        lp->bs1, lp->bs0, lp->phase, lp->tgt);
 279 #ifdef DBG_USE_TB
 280                 printk("tb=%10u ", lp->tb);
 281 #endif
 282                 printk(lp->fmt, lp->d);
 283                 printk("\n");
 284                 if (++i >= N_DBG_SLOG)
 285                         i = 0;
 286         } while (i != ms->log_ix);
 287 }
 288
 289 #else
 290
 291 static inline void dlog(struct mesh_state *ms, char *fmt, int a)
 292 {}
 293 static inline void dumplog(struct mesh_state *ms, int tgt)
 294 {}
 295 static inline void dumpslog(struct mesh_state *ms)
 296 {}
 297
 298 #endif /* MESH_DBG */
 299
 300 #define MKWORD(a, b, c, d)      (((a) << 24) + ((b) << 16) + ((c) << 8) + (d))
 301
 302 static void
 303 mesh_dump_regs(struct mesh_state *ms)
 304 {
 305         volatile struct mesh_regs __iomem *mr = ms->mesh;
 306         volatile struct dbdma_regs __iomem *md = ms->dma;
 307         int t;
 308         struct mesh_target *tp;
 309
 310         printk(KERN_DEBUG "mesh: state at %p, regs at %p, dma at %p\n",
 311                ms, mr, md);
 312         printk(KERN_DEBUG "    ct=%4x seq=%2x bs=%4x fc=%2x "
 313                "exc=%2x err=%2x im=%2x int=%2x sp=%2x\n",
 314                (mr->count_hi << 8) + mr->count_lo, mr->sequence,
 315                (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count,
 316                mr->exception, mr->error, mr->intr_mask, mr->interrupt,
 317                mr->sync_params);
 318         while(in_8(&mr->fifo_count))
 319                 printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo));
 320         printk(KERN_DEBUG "    dma stat=%x cmdptr=%x\n",
 321                in_le32(&md->status), in_le32(&md->cmdptr));
 322         printk(KERN_DEBUG "    phase=%d msgphase=%d conn_tgt=%d data_ptr=%d\n",
 323                ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr);
 324         printk(KERN_DEBUG "    dma_st=%d dma_ct=%d n_msgout=%d\n",
 325                ms->dma_started, ms->dma_count, ms->n_msgout);
 326         for (t = 0; t < 8; ++t) {
 327                 tp = &ms->tgts[t];
 328                 if (tp->current_req == NULL)
 329                         continue;
 330                 printk(KERN_DEBUG "    target %d: req=%p goes_out=%d saved_ptr=%d\n",
 331                        t, tp->current_req, tp->data_goes_out, tp->saved_ptr);
 332         }
 333 }
 334
 335
 336 /*
 337  * Flush write buffers on the bus path to the mesh
 338  */
 339 static inline void mesh_flush_io(volatile struct mesh_regs __iomem *mr)
 340 {
 341         (void)in_8(&mr->mesh_id);
 342 }
 343
 344
 345 /*
 346  * Complete a SCSI command
 347  */
 348 static void mesh_completed(struct mesh_state *ms, struct scsi_cmnd *cmd)
 349 {
 350         (*cmd->scsi_done)(cmd);
 351 }
 352
 353
 354 /* Called with  meshinterrupt disabled, initialize the chipset
 355  * and eventually do the initial bus reset. The lock must not be
 356  * held since we can schedule.
 357  */
 358 static void mesh_init(struct mesh_state *ms)
 359 {
 360         volatile struct mesh_regs __iomem *mr = ms->mesh;
 361         volatile struct dbdma_regs __iomem *md = ms->dma;
 362
 363         mesh_flush_io(mr);
 364         udelay(100);
 365
 366         /* Reset controller */
 367         out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16);   /* stop dma */
 368         out_8(&mr->exception, 0xff);    /* clear all exception bits */
 369         out_8(&mr->error, 0xff);        /* clear all error bits */
 370         out_8(&mr->sequence, SEQ_RESETMESH);
 371         mesh_flush_io(mr);
 372         udelay(10);
 373         out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 374         out_8(&mr->source_id, ms->host->this_id);
 375         out_8(&mr->sel_timeout, 25);    /* 250ms */
 376         out_8(&mr->sync_params, ASYNC_PARAMS);
 377
 378         if (init_reset_delay) {
 379                 printk(KERN_INFO "mesh: performing initial bus reset...\n");
 380
 381                 /* Reset bus */
 382                 out_8(&mr->bus_status1, BS1_RST);       /* assert RST */
 383                 mesh_flush_io(mr);
 384                 udelay(30);                     /* leave it on for >= 25us */
 385                 out_8(&mr->bus_status1, 0);     /* negate RST */
 386                 mesh_flush_io(mr);
 387
 388                 /* Wait for bus to come back */
 389                 msleep(init_reset_delay);
 390         }
 391
 392         /* Reconfigure controller */
 393         out_8(&mr->interrupt, 0xff);    /* clear all interrupt bits */
 394         out_8(&mr->sequence, SEQ_FLUSHFIFO);
 395         mesh_flush_io(mr);
 396         udelay(1);
 397         out_8(&mr->sync_params, ASYNC_PARAMS);
 398         out_8(&mr->sequence, SEQ_ENBRESEL);
 399
 400         ms->phase = idle;
 401         ms->msgphase = msg_none;
 402 }
 403
 404
 405 static void mesh_start_cmd(struct mesh_state *ms, struct scsi_cmnd *cmd)
 406 {
 407         volatile struct mesh_regs __iomem *mr = ms->mesh;
 408         int t, id;
 409
 410         id = cmd->device->id;
 411         ms->current_req = cmd;
 412         ms->tgts[id].data_goes_out = cmd->sc_data_direction == DMA_TO_DEVICE;
 413         ms->tgts[id].current_req = cmd;
 414
 415 #if 1
 416         if (DEBUG_TARGET(cmd)) {
 417                 int i;
 418                 printk(KERN_DEBUG "mesh_start: %p tgt=%d cmd=", cmd, id);
 419                 for (i = 0; i < cmd->cmd_len; ++i)
 420                         printk(" %x", cmd->cmnd[i]);
 421                 printk(" use_sg=%d buffer=%p bufflen=%u\n",
 422                        scsi_sg_count(cmd), scsi_sglist(cmd), scsi_bufflen(cmd));
 423         }
 424 #endif
 425         if (ms->dma_started)
 426                 panic("mesh: double DMA start !\n");
 427
 428         ms->phase = arbitrating;
 429         ms->msgphase = msg_none;
 430         ms->data_ptr = 0;
 431         ms->dma_started = 0;
 432         ms->n_msgout = 0;
 433         ms->last_n_msgout = 0;
 434         ms->expect_reply = 0;
 435         ms->conn_tgt = id;
 436         ms->tgts[id].saved_ptr = 0;
 437         ms->stat = DID_OK;
 438         ms->aborting = 0;
 439 #ifdef MESH_DBG
 440         ms->tgts[id].n_log = 0;
 441         dlog(ms, "start cmd=%x", (int) cmd);
 442 #endif
 443
 444         /* Off we go */
 445         dlog(ms, "about to arb, intr/exc/err/fc=%.8x",
 446              MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
 447         out_8(&mr->interrupt, INT_CMDDONE);
 448         out_8(&mr->sequence, SEQ_ENBRESEL);
 449         mesh_flush_io(mr);
 450         udelay(1);
 451
 452         if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
 453                 /*
 454                  * Some other device has the bus or is arbitrating for it -
 455                  * probably a target which is about to reselect us.
 456                  */
 457                 dlog(ms, "busy b4 arb, intr/exc/err/fc=%.8x",
 458                      MKWORD(mr->interrupt, mr->exception,
 459                             mr->error, mr->fifo_count));
 460                 for (t = 100; t > 0; --t) {
 461                         if ((in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) == 0)
 462                                 break;
 463                         if (in_8(&mr->interrupt) != 0) {
 464                                 dlog(ms, "intr b4 arb, intr/exc/err/fc=%.8x",
 465                                      MKWORD(mr->interrupt, mr->exception,
 466                                             mr->error, mr->fifo_count));
 467                                 mesh_interrupt(ms);
 468                                 if (ms->phase != arbitrating)
 469                                         return;
 470                         }
 471                         udelay(1);
 472                 }
 473                 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
 474                         /* XXX should try again in a little while */
 475                         ms->stat = DID_BUS_BUSY;
 476                         ms->phase = idle;
 477                         mesh_done(ms, 0);
 478                         return;
 479                 }
 480         }
 481
 482         /*
 483          * Apparently the mesh has a bug where it will assert both its
 484          * own bit and the target's bit on the bus during arbitration.
 485          */
 486         out_8(&mr->dest_id, mr->source_id);
 487
 488         /*
 489          * There appears to be a race with reselection sometimes,
 490          * where a target reselects us just as we issue the
 491          * arbitrate command.  It seems that then the arbitrate
 492          * command just hangs waiting for the bus to be free
 493          * without giving us a reselection exception.
 494          * The only way I have found to get it to respond correctly
 495          * is this: disable reselection before issuing the arbitrate
 496          * command, then after issuing it, if it looks like a target
 497          * is trying to reselect us, reset the mesh and then enable
 498          * reselection.
 499          */
 500         out_8(&mr->sequence, SEQ_DISRESEL);
 501         if (in_8(&mr->interrupt) != 0) {
 502                 dlog(ms, "intr after disresel, intr/exc/err/fc=%.8x",
 503                      MKWORD(mr->interrupt, mr->exception,
 504                             mr->error, mr->fifo_count));
 505                 mesh_interrupt(ms);
 506                 if (ms->phase != arbitrating)
 507                         return;
 508                 dlog(ms, "after intr after disresel, intr/exc/err/fc=%.8x",
 509                      MKWORD(mr->interrupt, mr->exception,
 510                             mr->error, mr->fifo_count));
 511         }
 512
 513         out_8(&mr->sequence, SEQ_ARBITRATE);
 514
 515         for (t = 230; t > 0; --t) {
 516                 if (in_8(&mr->interrupt) != 0)
 517                         break;
 518                 udelay(1);
 519         }
 520         dlog(ms, "after arb, intr/exc/err/fc=%.8x",
 521              MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
 522         if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
 523             && (in_8(&mr->bus_status0) & BS0_IO)) {
 524                 /* looks like a reselection - try resetting the mesh */
 525                 dlog(ms, "resel? after arb, intr/exc/err/fc=%.8x",
 526                      MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
 527                 out_8(&mr->sequence, SEQ_RESETMESH);
 528                 mesh_flush_io(mr);
 529                 udelay(10);
 530                 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 531                 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 532                 out_8(&mr->sequence, SEQ_ENBRESEL);
 533                 mesh_flush_io(mr);
 534                 for (t = 10; t > 0 && in_8(&mr->interrupt) == 0; --t)
 535                         udelay(1);
 536                 dlog(ms, "tried reset after arb, intr/exc/err/fc=%.8x",
 537                      MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
 538 #ifndef MESH_MULTIPLE_HOSTS
 539                 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
 540                     && (in_8(&mr->bus_status0) & BS0_IO)) {
 541                         printk(KERN_ERR "mesh: controller not responding"
 542                                " to reselection!\n");
 543                         /*
 544                          * If this is a target reselecting us, and the
 545                          * mesh isn't responding, the higher levels of
 546                          * the scsi code will eventually time out and
 547                          * reset the bus.
 548                          */
 549                 }
 550 #endif
 551         }
 552 }
 553
 554 /*
 555  * Start the next command for a MESH.
 556  * Should be called with interrupts disabled.
 557  */
 558 static void mesh_start(struct mesh_state *ms)
 559 {
 560         struct scsi_cmnd *cmd, *prev, *next;
 561
 562         if (ms->phase != idle || ms->current_req != NULL) {
 563                 printk(KERN_ERR "inappropriate mesh_start (phase=%d, ms=%p)",
 564                        ms->phase, ms);
 565                 return;
 566         }
 567
 568         while (ms->phase == idle) {
 569                 prev = NULL;
 570                 for (cmd = ms->request_q; ; cmd = (struct scsi_cmnd *) cmd->host_scribble) {
 571                         if (cmd == NULL)
 572                                 return;
 573                         if (ms->tgts[cmd->device->id].current_req == NULL)
 574                                 break;
 575                         prev = cmd;
 576                 }
 577                 next = (struct scsi_cmnd *) cmd->host_scribble;
 578                 if (prev == NULL)
 579                         ms->request_q = next;
 580                 else
 581                         prev->host_scribble = (void *) next;
 582                 if (next == NULL)
 583                         ms->request_qtail = prev;
 584
 585                 mesh_start_cmd(ms, cmd);
 586         }
 587 }
 588
 589 static void mesh_done(struct mesh_state *ms, int start_next)
 590 {
 591         struct scsi_cmnd *cmd;
 592         struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
 593
 594         cmd = ms->current_req;
 595         ms->current_req = NULL;
 596         tp->current_req = NULL;
 597         if (cmd) {
 598                 set_host_byte(cmd, ms->stat);
 599                 set_status_byte(cmd, cmd->SCp.Status);
 600                 if (ms->stat == DID_OK)
 601                         scsi_msg_to_host_byte(cmd, cmd->SCp.Message);
 602                 if (DEBUG_TARGET(cmd)) {
 603                         printk(KERN_DEBUG "mesh_done: result = %x, data_ptr=%d, buflen=%d\n",
 604                                cmd->result, ms->data_ptr, scsi_bufflen(cmd));
 605 #if 0
 606                         /* needs to use sg? */
 607                         if ((cmd->cmnd[0] == 0 || cmd->cmnd[0] == 0x12 || cmd->cmnd[0] == 3)
 608                             && cmd->request_buffer != 0) {
 609                                 unsigned char *b = cmd->request_buffer;
 610                                 printk(KERN_DEBUG "buffer = %x %x %x %x %x %x %x %x\n",
 611                                        b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
 612                         }
 613 #endif
 614                 }
 615                 cmd->SCp.this_residual -= ms->data_ptr;
 616                 mesh_completed(ms, cmd);
 617         }
 618         if (start_next) {
 619                 out_8(&ms->mesh->sequence, SEQ_ENBRESEL);
 620                 mesh_flush_io(ms->mesh);
 621                 udelay(1);
 622                 ms->phase = idle;
 623                 mesh_start(ms);
 624         }
 625 }
 626
 627 static inline void add_sdtr_msg(struct mesh_state *ms)
 628 {
 629         int i = ms->n_msgout;
 630
 631         ms->msgout[i] = EXTENDED_MESSAGE;
 632         ms->msgout[i+1] = 3;
 633         ms->msgout[i+2] = EXTENDED_SDTR;
 634         ms->msgout[i+3] = mesh_sync_period/4;
 635         ms->msgout[i+4] = (ALLOW_SYNC(ms->conn_tgt)? mesh_sync_offset: 0);
 636         ms->n_msgout = i + 5;
 637 }
 638
 639 static void set_sdtr(struct mesh_state *ms, int period, int offset)
 640 {
 641         struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
 642         volatile struct mesh_regs __iomem *mr = ms->mesh;
 643         int v, tr;
 644
 645         tp->sdtr_state = sdtr_done;
 646         if (offset == 0) {
 647                 /* asynchronous */
 648                 if (SYNC_OFF(tp->sync_params))
 649                         printk(KERN_INFO "mesh: target %d now asynchronous\n",
 650                                ms->conn_tgt);
 651                 tp->sync_params = ASYNC_PARAMS;
 652                 out_8(&mr->sync_params, ASYNC_PARAMS);
 653                 return;
 654         }
 655         /*
 656          * We need to compute ceil(clk_freq * period / 500e6) - 2
 657          * without incurring overflow.
 658          */
 659         v = (ms->clk_freq / 5000) * period;
 660         if (v <= 250000) {
 661                 /* special case: sync_period == 5 * clk_period */
 662                 v = 0;
 663                 /* units of tr are 100kB/s */
 664                 tr = (ms->clk_freq + 250000) / 500000;
 665         } else {
 666                 /* sync_period == (v + 2) * 2 * clk_period */
 667                 v = (v + 99999) / 100000 - 2;
 668                 if (v > 15)
 669                         v = 15; /* oops */
 670                 tr = ((ms->clk_freq / (v + 2)) + 199999) / 200000;
 671         }
 672         if (offset > 15)
 673                 offset = 15;    /* can't happen */
 674         tp->sync_params = SYNC_PARAMS(offset, v);
 675         out_8(&mr->sync_params, tp->sync_params);
 676         printk(KERN_INFO "mesh: target %d synchronous at %d.%d MB/s\n",
 677                ms->conn_tgt, tr/10, tr%10);
 678 }
 679
 680 static void start_phase(struct mesh_state *ms)
 681 {
 682         int i, seq, nb;
 683         volatile struct mesh_regs __iomem *mr = ms->mesh;
 684         volatile struct dbdma_regs __iomem *md = ms->dma;
 685         struct scsi_cmnd *cmd = ms->current_req;
 686         struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
 687
 688         dlog(ms, "start_phase nmo/exc/fc/seq = %.8x",
 689              MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence));
 690         out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 691         seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
 692         switch (ms->msgphase) {
 693         case msg_none:
 694                 break;
 695
 696         case msg_in:
 697                 out_8(&mr->count_hi, 0);
 698                 out_8(&mr->count_lo, 1);
 699                 out_8(&mr->sequence, SEQ_MSGIN + seq);
 700                 ms->n_msgin = 0;
 701                 return;
 702
 703         case msg_out:
 704                 /*
 705                  * To make sure ATN drops before we assert ACK for
 706                  * the last byte of the message, we have to do the
 707                  * last byte specially.
 708                  */
 709                 if (ms->n_msgout <= 0) {
 710                         printk(KERN_ERR "mesh: msg_out but n_msgout=%d\n",
 711                                ms->n_msgout);
 712                         mesh_dump_regs(ms);
 713                         ms->msgphase = msg_none;
 714                         break;
 715                 }
 716                 if (ALLOW_DEBUG(ms->conn_tgt)) {
 717                         printk(KERN_DEBUG "mesh: sending %d msg bytes:",
 718                                ms->n_msgout);
 719                         for (i = 0; i < ms->n_msgout; ++i)
 720                                 printk(" %x", ms->msgout[i]);
 721                         printk("\n");
 722                 }
 723                 dlog(ms, "msgout msg=%.8x", MKWORD(ms->n_msgout, ms->msgout[0],
 724                                                 ms->msgout[1], ms->msgout[2]));
 725                 out_8(&mr->count_hi, 0);
 726                 out_8(&mr->sequence, SEQ_FLUSHFIFO);
 727                 mesh_flush_io(mr);
 728                 udelay(1);
 729                 /*
 730                  * If ATN is not already asserted, we assert it, then
 731                  * issue a SEQ_MSGOUT to get the mesh to drop ACK.
 732                  */
 733                 if ((in_8(&mr->bus_status0) & BS0_ATN) == 0) {
 734                         dlog(ms, "bus0 was %.2x explicitly asserting ATN", mr->bus_status0);
 735                         out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */
 736                         mesh_flush_io(mr);
 737                         udelay(1);
 738                         out_8(&mr->count_lo, 1);
 739                         out_8(&mr->sequence, SEQ_MSGOUT + seq);
 740                         out_8(&mr->bus_status0, 0); /* release explicit ATN */
 741                         dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0);
 742                 }
 743                 if (ms->n_msgout == 1) {
 744                         /*
 745                          * We can't issue the SEQ_MSGOUT without ATN
 746                          * until the target has asserted REQ.  The logic
 747                          * in cmd_complete handles both situations:
 748                          * REQ already asserted or not.
 749                          */
 750                         cmd_complete(ms);
 751                 } else {
 752                         out_8(&mr->count_lo, ms->n_msgout - 1);
 753                         out_8(&mr->sequence, SEQ_MSGOUT + seq);
 754                         for (i = 0; i < ms->n_msgout - 1; ++i)
 755                                 out_8(&mr->fifo, ms->msgout[i]);
 756                 }
 757                 return;
 758
 759         default:
 760                 printk(KERN_ERR "mesh bug: start_phase msgphase=%d\n",
 761                        ms->msgphase);
 762         }
 763
 764         switch (ms->phase) {
 765         case selecting:
 766                 out_8(&mr->dest_id, ms->conn_tgt);
 767                 out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN);
 768                 break;
 769         case commanding:
 770                 out_8(&mr->sync_params, tp->sync_params);
 771                 out_8(&mr->count_hi, 0);
 772                 if (cmd) {
 773                         out_8(&mr->count_lo, cmd->cmd_len);
 774                         out_8(&mr->sequence, SEQ_COMMAND + seq);
 775                         for (i = 0; i < cmd->cmd_len; ++i)
 776                                 out_8(&mr->fifo, cmd->cmnd[i]);
 777                 } else {
 778                         out_8(&mr->count_lo, 6);
 779                         out_8(&mr->sequence, SEQ_COMMAND + seq);
 780                         for (i = 0; i < 6; ++i)
 781                                 out_8(&mr->fifo, 0);
 782                 }
 783                 break;
 784         case dataing:
 785                 /* transfer data, if any */
 786                 if (!ms->dma_started) {
 787                         set_dma_cmds(ms, cmd);
 788                         out_le32(&md->cmdptr, virt_to_phys(ms->dma_cmds));
 789                         out_le32(&md->control, (RUN << 16) | RUN);
 790                         ms->dma_started = 1;
 791                 }
 792                 nb = ms->dma_count;
 793                 if (nb > 0xfff0)
 794                         nb = 0xfff0;
 795                 ms->dma_count -= nb;
 796                 ms->data_ptr += nb;
 797                 out_8(&mr->count_lo, nb);
 798                 out_8(&mr->count_hi, nb >> 8);
 799                 out_8(&mr->sequence, (tp->data_goes_out?
 800                                 SEQ_DATAOUT: SEQ_DATAIN) + SEQ_DMA_MODE + seq);
 801                 break;
 802         case statusing:
 803                 out_8(&mr->count_hi, 0);
 804                 out_8(&mr->count_lo, 1);
 805                 out_8(&mr->sequence, SEQ_STATUS + seq);
 806                 break;
 807         case busfreeing:
 808         case disconnecting:
 809                 out_8(&mr->sequence, SEQ_ENBRESEL);
 810                 mesh_flush_io(mr);
 811                 udelay(1);
 812                 dlog(ms, "enbresel intr/exc/err/fc=%.8x",
 813                      MKWORD(mr->interrupt, mr->exception, mr->error,
 814                             mr->fifo_count));
 815                 out_8(&mr->sequence, SEQ_BUSFREE);
 816                 break;
 817         default:
 818                 printk(KERN_ERR "mesh: start_phase called with phase=%d\n",
 819                        ms->phase);
 820                 dumpslog(ms);
 821         }
 822
 823 }
 824
 825 static inline void get_msgin(struct mesh_state *ms)
 826 {
 827         volatile struct mesh_regs __iomem *mr = ms->mesh;
 828         int i, n;
 829
 830         n = mr->fifo_count;
 831         if (n != 0) {
 832                 i = ms->n_msgin;
 833                 ms->n_msgin = i + n;
 834                 for (; n > 0; --n)
 835                         ms->msgin[i++] = in_8(&mr->fifo);
 836         }
 837 }
 838
 839 static inline int msgin_length(struct mesh_state *ms)
 840 {
 841         int b, n;
 842
 843         n = 1;
 844         if (ms->n_msgin > 0) {
 845                 b = ms->msgin[0];
 846                 if (b == 1) {
 847                         /* extended message */
 848                         n = ms->n_msgin < 2? 2: ms->msgin[1] + 2;
 849                 } else if (0x20 <= b && b <= 0x2f) {
 850                         /* 2-byte message */
 851                         n = 2;
 852                 }
 853         }
 854         return n;
 855 }
 856
 857 static void reselected(struct mesh_state *ms)
 858 {
 859         volatile struct mesh_regs __iomem *mr = ms->mesh;
 860         struct scsi_cmnd *cmd;
 861         struct mesh_target *tp;
 862         int b, t, prev;
 863
 864         switch (ms->phase) {
 865         case idle:
 866                 break;
 867         case arbitrating:
 868                 if ((cmd = ms->current_req) != NULL) {
 869                         /* put the command back on the queue */
 870                         cmd->host_scribble = (void *) ms->request_q;
 871                         if (ms->request_q == NULL)
 872                                 ms->request_qtail = cmd;
 873                         ms->request_q = cmd;
 874                         tp = &ms->tgts[cmd->device->id];
 875                         tp->current_req = NULL;
 876                 }
 877                 break;
 878         case busfreeing:
 879                 ms->phase = reselecting;
 880                 mesh_done(ms, 0);
 881                 break;
 882         case disconnecting:
 883                 break;
 884         default:
 885                 printk(KERN_ERR "mesh: reselected in phase %d/%d tgt %d\n",
 886                        ms->msgphase, ms->phase, ms->conn_tgt);
 887                 dumplog(ms, ms->conn_tgt);
 888                 dumpslog(ms);
 889         }
 890
 891         if (ms->dma_started) {
 892                 printk(KERN_ERR "mesh: reselected with DMA started !\n");
 893                 halt_dma(ms);
 894         }
 895         ms->current_req = NULL;
 896         ms->phase = dataing;
 897         ms->msgphase = msg_in;
 898         ms->n_msgout = 0;
 899         ms->last_n_msgout = 0;
 900         prev = ms->conn_tgt;
 901
 902         /*
 903          * We seem to get abortive reselections sometimes.
 904          */
 905         while ((in_8(&mr->bus_status1) & BS1_BSY) == 0) {
 906                 static int mesh_aborted_resels;
 907                 mesh_aborted_resels++;
 908                 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 909                 mesh_flush_io(mr);
 910                 udelay(1);
 911                 out_8(&mr->sequence, SEQ_ENBRESEL);
 912                 mesh_flush_io(mr);
 913                 udelay(5);
 914                 dlog(ms, "extra resel err/exc/fc = %.6x",
 915                      MKWORD(0, mr->error, mr->exception, mr->fifo_count));
 916         }
 917         out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 918         mesh_flush_io(mr);
 919         udelay(1);
 920         out_8(&mr->sequence, SEQ_ENBRESEL);
 921         mesh_flush_io(mr);
 922         udelay(1);
 923         out_8(&mr->sync_params, ASYNC_PARAMS);
 924
 925         /*
 926          * Find out who reselected us.
 927          */
 928         if (in_8(&mr->fifo_count) == 0) {
 929                 printk(KERN_ERR "mesh: reselection but nothing in fifo?\n");
 930                 ms->conn_tgt = ms->host->this_id;
 931                 goto bogus;
 932         }
 933         /* get the last byte in the fifo */
 934         do {
 935                 b = in_8(&mr->fifo);
 936                 dlog(ms, "reseldata %x", b);
 937         } while (in_8(&mr->fifo_count));
 938         for (t = 0; t < 8; ++t)
 939                 if ((b & (1 << t)) != 0 && t != ms->host->this_id)
 940                         break;
 941         if (b != (1 << t) + (1 << ms->host->this_id)) {
 942                 printk(KERN_ERR "mesh: bad reselection data %x\n", b);
 943                 ms->conn_tgt = ms->host->this_id;
 944                 goto bogus;
 945         }
 946
 947
 948         /*
 949          * Set up to continue with that target's transfer.
 950          */
 951         ms->conn_tgt = t;
 952         tp = &ms->tgts[t];
 953         out_8(&mr->sync_params, tp->sync_params);
 954         if (ALLOW_DEBUG(t)) {
 955                 printk(KERN_DEBUG "mesh: reselected by target %d\n", t);
 956                 printk(KERN_DEBUG "mesh: saved_ptr=%x goes_out=%d cmd=%p\n",
 957                        tp->saved_ptr, tp->data_goes_out, tp->current_req);
 958         }
 959         ms->current_req = tp->current_req;
 960         if (tp->current_req == NULL) {
 961                 printk(KERN_ERR "mesh: reselected by tgt %d but no cmd!\n", t);
 962                 goto bogus;
 963         }
 964         ms->data_ptr = tp->saved_ptr;
 965         dlog(ms, "resel prev tgt=%d", prev);
 966         dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception));
 967         start_phase(ms);
 968         return;
 969
 970 bogus:
 971         dumplog(ms, ms->conn_tgt);
 972         dumpslog(ms);
 973         ms->data_ptr = 0;
 974         ms->aborting = 1;
 975         start_phase(ms);
 976 }
 977
 978 static void do_abort(struct mesh_state *ms)
 979 {
 980         ms->msgout[0] = ABORT;
 981         ms->n_msgout = 1;
 982         ms->aborting = 1;
 983         ms->stat = DID_ABORT;
 984         dlog(ms, "abort", 0);
 985 }
 986
 987 static void handle_reset(struct mesh_state *ms)
 988 {
 989         int tgt;
 990         struct mesh_target *tp;
 991         struct scsi_cmnd *cmd;
 992         volatile struct mesh_regs __iomem *mr = ms->mesh;
 993
 994         for (tgt = 0; tgt < 8; ++tgt) {
 995                 tp = &ms->tgts[tgt];
 996                 if ((cmd = tp->current_req) != NULL) {
 997                         set_host_byte(cmd, DID_RESET);
 998                         tp->current_req = NULL;
 999                         mesh_completed(ms, cmd);
1000                 }
1001                 ms->tgts[tgt].sdtr_state = do_sdtr;
1002                 ms->tgts[tgt].sync_params = ASYNC_PARAMS;
1003         }
1004         ms->current_req = NULL;
1005         while ((cmd = ms->request_q) != NULL) {
1006                 ms->request_q = (struct scsi_cmnd *) cmd->host_scribble;
1007                 set_host_byte(cmd, DID_RESET);
1008                 mesh_completed(ms, cmd);
1009         }
1010         ms->phase = idle;
1011         ms->msgphase = msg_none;
1012         out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1013         out_8(&mr->sequence, SEQ_FLUSHFIFO);
1014         mesh_flush_io(mr);
1015         udelay(1);
1016         out_8(&mr->sync_params, ASYNC_PARAMS);
1017         out_8(&mr->sequence, SEQ_ENBRESEL);
1018 }
1019
1020 static irqreturn_t do_mesh_interrupt(int irq, void *dev_id)
1021 {
1022         unsigned long flags;
1023         struct mesh_state *ms = dev_id;
1024         struct Scsi_Host *dev = ms->host;
1025
1026         spin_lock_irqsave(dev->host_lock, flags);
1027         mesh_interrupt(ms);
1028         spin_unlock_irqrestore(dev->host_lock, flags);
1029         return IRQ_HANDLED;
1030 }
1031
1032 static void handle_error(struct mesh_state *ms)
1033 {
1034         int err, exc, count;
1035         volatile struct mesh_regs __iomem *mr = ms->mesh;
1036
1037         err = in_8(&mr->error);
1038         exc = in_8(&mr->exception);
1039         out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1040         dlog(ms, "error err/exc/fc/cl=%.8x",
1041              MKWORD(err, exc, mr->fifo_count, mr->count_lo));
1042         if (err & ERR_SCSIRESET) {
1043                 /* SCSI bus was reset */
1044                 printk(KERN_INFO "mesh: SCSI bus reset detected: "
1045                        "waiting for end...");
1046                 while ((in_8(&mr->bus_status1) & BS1_RST) != 0)
1047                         udelay(1);
1048                 printk("done\n");
1049                 if (ms->dma_started)
1050                         halt_dma(ms);
1051                 handle_reset(ms);
1052                 /* request_q is empty, no point in mesh_start() */
1053                 return;
1054         }
1055         if (err & ERR_UNEXPDISC) {
1056                 /* Unexpected disconnect */
1057                 if (exc & EXC_RESELECTED) {
1058                         reselected(ms);
1059                         return;
1060                 }
1061                 if (!ms->aborting) {
1062                         printk(KERN_WARNING "mesh: target %d aborted\n",
1063                                ms->conn_tgt);
1064                         dumplog(ms, ms->conn_tgt);
1065                         dumpslog(ms);
1066                 }
1067                 out_8(&mr->interrupt, INT_CMDDONE);
1068                 ms->stat = DID_ABORT;
1069                 mesh_done(ms, 1);
1070                 return;
1071         }
1072         if (err & ERR_PARITY) {
1073                 if (ms->msgphase == msg_in) {
1074                         printk(KERN_ERR "mesh: msg parity error, target %d\n",
1075                                ms->conn_tgt);
1076                         ms->msgout[0] = MSG_PARITY_ERROR;
1077                         ms->n_msgout = 1;
1078                         ms->msgphase = msg_in_bad;
1079                         cmd_complete(ms);
1080                         return;
1081                 }
1082                 if (ms->stat == DID_OK) {
1083                         printk(KERN_ERR "mesh: parity error, target %d\n",
1084                                ms->conn_tgt);
1085                         ms->stat = DID_PARITY;
1086                 }
1087                 count = (mr->count_hi << 8) + mr->count_lo;
1088                 if (count == 0) {
1089                         cmd_complete(ms);
1090                 } else {
1091                         /* reissue the data transfer command */
1092                         out_8(&mr->sequence, mr->sequence);
1093                 }
1094                 return;
1095         }
1096         if (err & ERR_SEQERR) {
1097                 if (exc & EXC_RESELECTED) {
1098                         /* This can happen if we issue a command to
1099                            get the bus just after the target reselects us. */
1100                         static int mesh_resel_seqerr;
1101                         mesh_resel_seqerr++;
1102                         reselected(ms);
1103                         return;
1104                 }
1105                 if (exc == EXC_PHASEMM) {
1106                         static int mesh_phasemm_seqerr;
1107                         mesh_phasemm_seqerr++;
1108                         phase_mismatch(ms);
1109                         return;
1110                 }
1111                 printk(KERN_ERR "mesh: sequence error (err=%x exc=%x)\n",
1112                        err, exc);
1113         } else {
1114                 printk(KERN_ERR "mesh: unknown error %x (exc=%x)\n", err, exc);
1115         }
1116         mesh_dump_regs(ms);
1117         dumplog(ms, ms->conn_tgt);
1118         if (ms->phase > selecting && (in_8(&mr->bus_status1) & BS1_BSY)) {
1119                 /* try to do what the target wants */
1120                 do_abort(ms);
1121                 phase_mismatch(ms);
1122                 return;
1123         }
1124         ms->stat = DID_ERROR;
1125         mesh_done(ms, 1);
1126 }
1127
1128 static void handle_exception(struct mesh_state *ms)
1129 {
1130         int exc;
1131         volatile struct mesh_regs __iomem *mr = ms->mesh;
1132
1133         exc = in_8(&mr->exception);
1134         out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE);
1135         if (exc & EXC_RESELECTED) {
1136                 static int mesh_resel_exc;
1137                 mesh_resel_exc++;
1138                 reselected(ms);
1139         } else if (exc == EXC_ARBLOST) {
1140                 printk(KERN_DEBUG "mesh: lost arbitration\n");
1141                 ms->stat = DID_BUS_BUSY;
1142                 mesh_done(ms, 1);
1143         } else if (exc == EXC_SELTO) {
1144                 /* selection timed out */
1145                 ms->stat = DID_BAD_TARGET;
1146                 mesh_done(ms, 1);
1147         } else if (exc == EXC_PHASEMM) {
1148                 /* target wants to do something different:
1149                    find out what it wants and do it. */
1150                 phase_mismatch(ms);
1151         } else {
1152                 printk(KERN_ERR "mesh: can't cope with exception %x\n", exc);
1153                 mesh_dump_regs(ms);
1154                 dumplog(ms, ms->conn_tgt);
1155                 do_abort(ms);
1156                 phase_mismatch(ms);
1157         }
1158 }
1159
1160 static void handle_msgin(struct mesh_state *ms)
1161 {
1162         int i, code;
1163         struct scsi_cmnd *cmd = ms->current_req;
1164         struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1165
1166         if (ms->n_msgin == 0)
1167                 return;
1168         code = ms->msgin[0];
1169         if (ALLOW_DEBUG(ms->conn_tgt)) {
1170                 printk(KERN_DEBUG "got %d message bytes:", ms->n_msgin);
1171                 for (i = 0; i < ms->n_msgin; ++i)
1172                         printk(" %x", ms->msgin[i]);
1173                 printk("\n");
1174         }
1175         dlog(ms, "msgin msg=%.8x",
1176              MKWORD(ms->n_msgin, code, ms->msgin[1], ms->msgin[2]));
1177
1178         ms->expect_reply = 0;
1179         ms->n_msgout = 0;
1180         if (ms->n_msgin < msgin_length(ms))
1181                 goto reject;
1182         if (cmd)
1183                 cmd->SCp.Message = code;
1184         switch (code) {
1185         case COMMAND_COMPLETE:
1186                 break;
1187         case EXTENDED_MESSAGE:
1188                 switch (ms->msgin[2]) {
1189                 case EXTENDED_MODIFY_DATA_POINTER:
1190                         ms->data_ptr += (ms->msgin[3] << 24) + ms->msgin[6]
1191                                 + (ms->msgin[4] << 16) + (ms->msgin[5] << 8);
1192                         break;
1193                 case EXTENDED_SDTR:
1194                         if (tp->sdtr_state != sdtr_sent) {
1195                                 /* reply with an SDTR */
1196                                 add_sdtr_msg(ms);
1197                                 /* limit period to at least his value,
1198                                    offset to no more than his */
1199                                 if (ms->msgout[3] < ms->msgin[3])
1200                                         ms->msgout[3] = ms->msgin[3];
1201                                 if (ms->msgout[4] > ms->msgin[4])
1202                                         ms->msgout[4] = ms->msgin[4];
1203                                 set_sdtr(ms, ms->msgout[3], ms->msgout[4]);
1204                                 ms->msgphase = msg_out;
1205                         } else {
1206                                 set_sdtr(ms, ms->msgin[3], ms->msgin[4]);
1207                         }
1208                         break;
1209                 default:
1210                         goto reject;
1211                 }
1212                 break;
1213         case SAVE_POINTERS:
1214                 tp->saved_ptr = ms->data_ptr;
1215                 break;
1216         case RESTORE_POINTERS:
1217                 ms->data_ptr = tp->saved_ptr;
1218                 break;
1219         case DISCONNECT:
1220                 ms->phase = disconnecting;
1221                 break;
1222         case ABORT:
1223                 break;
1224         case MESSAGE_REJECT:
1225                 if (tp->sdtr_state == sdtr_sent)
1226                         set_sdtr(ms, 0, 0);
1227                 break;
1228         case NOP:
1229                 break;
1230         default:
1231                 if (IDENTIFY_BASE <= code && code <= IDENTIFY_BASE + 7) {
1232                         if (cmd == NULL) {
1233                                 do_abort(ms);
1234                                 ms->msgphase = msg_out;
1235                         } else if (code != cmd->device->lun + IDENTIFY_BASE) {
1236                                 printk(KERN_WARNING "mesh: lun mismatch "
1237                                        "(%d != %llu) on reselection from "
1238                                        "target %d\n", code - IDENTIFY_BASE,
1239                                        cmd->device->lun, ms->conn_tgt);
1240                         }
1241                         break;
1242                 }
1243                 goto reject;
1244         }
1245         return;
1246
1247  reject:
1248         printk(KERN_WARNING "mesh: rejecting message from target %d:",
1249                ms->conn_tgt);
1250         for (i = 0; i < ms->n_msgin; ++i)
1251                 printk(" %x", ms->msgin[i]);
1252         printk("\n");
1253         ms->msgout[0] = MESSAGE_REJECT;
1254         ms->n_msgout = 1;
1255         ms->msgphase = msg_out;
1256 }
1257
1258 /*
1259  * Set up DMA commands for transferring data.
1260  */
1261 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd)
1262 {
1263         int i, dma_cmd, total, off, dtot;
1264         struct scatterlist *scl;
1265         struct dbdma_cmd *dcmds;
1266
1267         dma_cmd = ms->tgts[ms->conn_tgt].data_goes_out?
1268                 OUTPUT_MORE: INPUT_MORE;
1269         dcmds = ms->dma_cmds;
1270         dtot = 0;
1271         if (cmd) {
1272                 int nseg;
1273
1274                 cmd->SCp.this_residual = scsi_bufflen(cmd);
1275
1276                 nseg = scsi_dma_map(cmd);
1277                 BUG_ON(nseg < 0);
1278
1279                 if (nseg) {
1280                         total = 0;
1281                         off = ms->data_ptr;
1282
1283                         scsi_for_each_sg(cmd, scl, nseg, i) {
1284                                 u32 dma_addr = sg_dma_address(scl);
1285                                 u32 dma_len = sg_dma_len(scl);
1286
1287                                 total += scl->length;
1288                                 if (off >= dma_len) {
1289                                         off -= dma_len;
1290                                         continue;
1291                                 }
1292                                 if (dma_len > 0xffff)
1293                                         panic("mesh: scatterlist element >= 64k");
1294                                 dcmds->req_count = cpu_to_le16(dma_len - off);
1295                                 dcmds->command = cpu_to_le16(dma_cmd);
1296                                 dcmds->phy_addr = cpu_to_le32(dma_addr + off);
1297                                 dcmds->xfer_status = 0;
1298                                 ++dcmds;
1299                                 dtot += dma_len - off;
1300                                 off = 0;
1301                         }
1302                 }
1303         }
1304         if (dtot == 0) {
1305                 /* Either the target has overrun our buffer,
1306                    or the caller didn't provide a buffer. */
1307                 static char mesh_extra_buf[64];
1308
1309                 dtot = sizeof(mesh_extra_buf);
1310                 dcmds->req_count = cpu_to_le16(dtot);
1311                 dcmds->phy_addr = cpu_to_le32(virt_to_phys(mesh_extra_buf));
1312                 dcmds->xfer_status = 0;
1313                 ++dcmds;
1314         }
1315         dma_cmd += OUTPUT_LAST - OUTPUT_MORE;
1316         dcmds[-1].command = cpu_to_le16(dma_cmd);
1317         memset(dcmds, 0, sizeof(*dcmds));
1318         dcmds->command = cpu_to_le16(DBDMA_STOP);
1319         ms->dma_count = dtot;
1320 }
1321
1322 static void halt_dma(struct mesh_state *ms)
1323 {
1324         volatile struct dbdma_regs __iomem *md = ms->dma;
1325         volatile struct mesh_regs __iomem *mr = ms->mesh;
1326         struct scsi_cmnd *cmd = ms->current_req;
1327         int t, nb;
1328
1329         if (!ms->tgts[ms->conn_tgt].data_goes_out) {
1330                 /* wait a little while until the fifo drains */
1331                 t = 50;
1332                 while (t > 0 && in_8(&mr->fifo_count) != 0
1333                        && (in_le32(&md->status) & ACTIVE) != 0) {
1334                         --t;
1335                         udelay(1);
1336                 }
1337         }
1338         out_le32(&md->control, RUN << 16);      /* turn off RUN bit */
1339         nb = (mr->count_hi << 8) + mr->count_lo;
1340         dlog(ms, "halt_dma fc/count=%.6x",
1341              MKWORD(0, mr->fifo_count, 0, nb));
1342         if (ms->tgts[ms->conn_tgt].data_goes_out)
1343                 nb += mr->fifo_count;
1344         /* nb is the number of bytes not yet transferred
1345            to/from the target. */
1346         ms->data_ptr -= nb;
1347         dlog(ms, "data_ptr %x", ms->data_ptr);
1348         if (ms->data_ptr < 0) {
1349                 printk(KERN_ERR "mesh: halt_dma: data_ptr=%d (nb=%d, ms=%p)\n",
1350                        ms->data_ptr, nb, ms);
1351                 ms->data_ptr = 0;
1352 #ifdef MESH_DBG
1353                 dumplog(ms, ms->conn_tgt);
1354                 dumpslog(ms);
1355 #endif /* MESH_DBG */
1356         } else if (cmd && scsi_bufflen(cmd) &&
1357                    ms->data_ptr > scsi_bufflen(cmd)) {
1358                 printk(KERN_DEBUG "mesh: target %d overrun, "
1359                        "data_ptr=%x total=%x goes_out=%d\n",
1360                        ms->conn_tgt, ms->data_ptr, scsi_bufflen(cmd),
1361                        ms->tgts[ms->conn_tgt].data_goes_out);
1362         }
1363         if (cmd)
1364                 scsi_dma_unmap(cmd);
1365         ms->dma_started = 0;
1366 }
1367
1368 static void phase_mismatch(struct mesh_state *ms)
1369 {
1370         volatile struct mesh_regs __iomem *mr = ms->mesh;
1371         int phase;
1372
1373         dlog(ms, "phasemm ch/cl/seq/fc=%.8x",
1374              MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count));
1375         phase = in_8(&mr->bus_status0) & BS0_PHASE;
1376         if (ms->msgphase == msg_out_xxx && phase == BP_MSGOUT) {
1377                 /* output the last byte of the message, without ATN */
1378                 out_8(&mr->count_lo, 1);
1379                 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1380                 mesh_flush_io(mr);
1381                 udelay(1);
1382                 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1383                 ms->msgphase = msg_out_last;
1384                 return;
1385         }
1386
1387         if (ms->msgphase == msg_in) {
1388                 get_msgin(ms);
1389                 if (ms->n_msgin)
1390                         handle_msgin(ms);
1391         }
1392
1393         if (ms->dma_started)
1394                 halt_dma(ms);
1395         if (mr->fifo_count) {
1396                 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1397                 mesh_flush_io(mr);
1398                 udelay(1);
1399         }
1400
1401         ms->msgphase = msg_none;
1402         switch (phase) {
1403         case BP_DATAIN:
1404                 ms->tgts[ms->conn_tgt].data_goes_out = 0;
1405                 ms->phase = dataing;
1406                 break;
1407         case BP_DATAOUT:
1408                 ms->tgts[ms->conn_tgt].data_goes_out = 1;
1409                 ms->phase = dataing;
1410                 break;
1411         case BP_COMMAND:
1412                 ms->phase = commanding;
1413                 break;
1414         case BP_STATUS:
1415                 ms->phase = statusing;
1416                 break;
1417         case BP_MSGIN:
1418                 ms->msgphase = msg_in;
1419                 ms->n_msgin = 0;
1420                 break;
1421         case BP_MSGOUT:
1422                 ms->msgphase = msg_out;
1423                 if (ms->n_msgout == 0) {
1424                         if (ms->aborting) {
1425                                 do_abort(ms);
1426                         } else {
1427                                 if (ms->last_n_msgout == 0) {
1428                                         printk(KERN_DEBUG
1429                                                "mesh: no msg to repeat\n");
1430                                         ms->msgout[0] = NOP;
1431                                         ms->last_n_msgout = 1;
1432                                 }
1433                                 ms->n_msgout = ms->last_n_msgout;
1434                         }
1435                 }
1436                 break;
1437         default:
1438                 printk(KERN_DEBUG "mesh: unknown scsi phase %x\n", phase);
1439                 ms->stat = DID_ERROR;
1440                 mesh_done(ms, 1);
1441                 return;
1442         }
1443
1444         start_phase(ms);
1445 }
1446
1447 static void cmd_complete(struct mesh_state *ms)
1448 {
1449         volatile struct mesh_regs __iomem *mr = ms->mesh;
1450         struct scsi_cmnd *cmd = ms->current_req;
1451         struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1452         int seq, n, t;
1453
1454         dlog(ms, "cmd_complete fc=%x", mr->fifo_count);
1455         seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
1456         switch (ms->msgphase) {
1457         case msg_out_xxx:
1458                 /* huh?  we expected a phase mismatch */
1459                 ms->n_msgin = 0;
1460                 ms->msgphase = msg_in;
1461                 fallthrough;
1462
1463         case msg_in:
1464                 /* should have some message bytes in fifo */
1465                 get_msgin(ms);
1466                 n = msgin_length(ms);
1467                 if (ms->n_msgin < n) {
1468                         out_8(&mr->count_lo, n - ms->n_msgin);
1469                         out_8(&mr->sequence, SEQ_MSGIN + seq);
1470                 } else {
1471                         ms->msgphase = msg_none;
1472                         handle_msgin(ms);
1473                         start_phase(ms);
1474                 }
1475                 break;
1476
1477         case msg_in_bad:
1478                 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1479                 mesh_flush_io(mr);
1480                 udelay(1);
1481                 out_8(&mr->count_lo, 1);
1482                 out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg);
1483                 break;
1484
1485         case msg_out:
1486                 /*
1487                  * To get the right timing on ATN wrt ACK, we have
1488                  * to get the MESH to drop ACK, wait until REQ gets
1489                  * asserted, then drop ATN.  To do this we first
1490                  * issue a SEQ_MSGOUT with ATN and wait for REQ,
1491                  * then change the command to a SEQ_MSGOUT w/o ATN.
1492                  * If we don't see REQ in a reasonable time, we
1493                  * change the command to SEQ_MSGIN with ATN,
1494                  * wait for the phase mismatch interrupt, then
1495                  * issue the SEQ_MSGOUT without ATN.
1496                  */
1497                 out_8(&mr->count_lo, 1);
1498                 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN);
1499                 t = 30;         /* wait up to 30us */
1500                 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0 && --t >= 0)
1501                         udelay(1);
1502                 dlog(ms, "last_mbyte err/exc/fc/cl=%.8x",
1503                      MKWORD(mr->error, mr->exception,
1504                             mr->fifo_count, mr->count_lo));
1505                 if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) {
1506                         /* whoops, target didn't do what we expected */
1507                         ms->last_n_msgout = ms->n_msgout;
1508                         ms->n_msgout = 0;
1509                         if (in_8(&mr->interrupt) & INT_ERROR) {
1510                                 printk(KERN_ERR "mesh: error %x in msg_out\n",
1511                                        in_8(&mr->error));
1512                                 handle_error(ms);
1513                                 return;
1514                         }
1515                         if (in_8(&mr->exception) != EXC_PHASEMM)
1516                                 printk(KERN_ERR "mesh: exc %x in msg_out\n",
1517                                        in_8(&mr->exception));
1518                         else
1519                                 printk(KERN_DEBUG "mesh: bs0=%x in msg_out\n",
1520                                        in_8(&mr->bus_status0));
1521                         handle_exception(ms);
1522                         return;
1523                 }
1524                 if (in_8(&mr->bus_status0) & BS0_REQ) {
1525                         out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1526                         mesh_flush_io(mr);
1527                         udelay(1);
1528                         out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1529                         ms->msgphase = msg_out_last;
1530                 } else {
1531                         out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN);
1532                         ms->msgphase = msg_out_xxx;
1533                 }
1534                 break;
1535
1536         case msg_out_last:
1537                 ms->last_n_msgout = ms->n_msgout;
1538                 ms->n_msgout = 0;
1539                 ms->msgphase = ms->expect_reply? msg_in: msg_none;
1540                 start_phase(ms);
1541                 break;
1542
1543         case msg_none:
1544                 switch (ms->phase) {
1545                 case idle:
1546                         printk(KERN_ERR "mesh: interrupt in idle phase?\n");
1547                         dumpslog(ms);
1548                         return;
1549                 case selecting:
1550                         dlog(ms, "Selecting phase at command completion",0);
1551                         ms->msgout[0] = IDENTIFY(ALLOW_RESEL(ms->conn_tgt),
1552                                                  (cmd? cmd->device->lun: 0));
1553                         ms->n_msgout = 1;
1554                         ms->expect_reply = 0;
1555                         if (ms->aborting) {
1556                                 ms->msgout[0] = ABORT;
1557                                 ms->n_msgout++;
1558                         } else if (tp->sdtr_state == do_sdtr) {
1559                                 /* add SDTR message */
1560                                 add_sdtr_msg(ms);
1561                                 ms->expect_reply = 1;
1562                                 tp->sdtr_state = sdtr_sent;
1563                         }
1564                         ms->msgphase = msg_out;
1565                         /*
1566                          * We need to wait for REQ before dropping ATN.
1567                          * We wait for at most 30us, then fall back to
1568                          * a scheme where we issue a SEQ_COMMAND with ATN,
1569                          * which will give us a phase mismatch interrupt
1570                          * when REQ does come, and then we send the message.
1571                          */
1572                         t = 230;                /* wait up to 230us */
1573                         while ((in_8(&mr->bus_status0) & BS0_REQ) == 0) {
1574                                 if (--t < 0) {
1575                                         dlog(ms, "impatient for req", ms->n_msgout);
1576                                         ms->msgphase = msg_none;
1577                                         break;
1578                                 }
1579                                 udelay(1);
1580                         }
1581                         break;
1582                 case dataing:
1583                         if (ms->dma_count != 0) {
1584                                 start_phase(ms);
1585                                 return;
1586                         }
1587                         /*
1588                          * We can get a phase mismatch here if the target
1589                          * changes to the status phase, even though we have
1590                          * had a command complete interrupt.  Then, if we
1591                          * issue the SEQ_STATUS command, we'll get a sequence
1592                          * error interrupt.  Which isn't so bad except that
1593                          * occasionally the mesh actually executes the
1594                          * SEQ_STATUS *as well as* giving us the sequence
1595                          * error and phase mismatch exception.
1596                          */
1597                         out_8(&mr->sequence, 0);
1598                         out_8(&mr->interrupt,
1599                               INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1600                         halt_dma(ms);
1601                         break;
1602                 case statusing:
1603                         if (cmd) {
1604                                 cmd->SCp.Status = mr->fifo;
1605                                 if (DEBUG_TARGET(cmd))
1606                                         printk(KERN_DEBUG "mesh: status is %x\n",
1607                                                cmd->SCp.Status);
1608                         }
1609                         ms->msgphase = msg_in;
1610                         break;
1611                 case busfreeing:
1612                         mesh_done(ms, 1);
1613                         return;
1614                 case disconnecting:
1615                         ms->current_req = NULL;
1616                         ms->phase = idle;
1617                         mesh_start(ms);
1618                         return;
1619                 default:
1620                         break;
1621                 }
1622                 ++ms->phase;
1623                 start_phase(ms);
1624                 break;
1625         }
1626 }
1627
1628
1629 /*
1630  * Called by midlayer with host locked to queue a new
1631  * request
1632  */
1633 static int mesh_queue_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
1634 {
1635         struct mesh_state *ms;
1636
1637         cmd->scsi_done = done;
1638         cmd->host_scribble = NULL;
1639
1640         ms = (struct mesh_state *) cmd->device->host->hostdata;
1641
1642         if (ms->request_q == NULL)
1643                 ms->request_q = cmd;
1644         else
1645                 ms->request_qtail->host_scribble = (void *) cmd;
1646         ms->request_qtail = cmd;
1647
1648         if (ms->phase == idle)
1649                 mesh_start(ms);
1650
1651         return 0;
1652 }
1653
1654 static DEF_SCSI_QCMD(mesh_queue)
1655
1656 /*
1657  * Called to handle interrupts, either call by the interrupt
1658  * handler (do_mesh_interrupt) or by other functions in
1659  * exceptional circumstances
1660  */
1661 static void mesh_interrupt(struct mesh_state *ms)
1662 {
1663         volatile struct mesh_regs __iomem *mr = ms->mesh;
1664         int intr;
1665
1666 #if 0
1667         if (ALLOW_DEBUG(ms->conn_tgt))
1668                 printk(KERN_DEBUG "mesh_intr, bs0=%x int=%x exc=%x err=%x "
1669                        "phase=%d msgphase=%d\n", mr->bus_status0,
1670                        mr->interrupt, mr->exception, mr->error,
1671                        ms->phase, ms->msgphase);
1672 #endif
1673         while ((intr = in_8(&mr->interrupt)) != 0) {
1674                 dlog(ms, "interrupt intr/err/exc/seq=%.8x",
1675                      MKWORD(intr, mr->error, mr->exception, mr->sequence));
1676                 if (intr & INT_ERROR) {
1677                         handle_error(ms);
1678                 } else if (intr & INT_EXCEPTION) {
1679                         handle_exception(ms);
1680                 } else if (intr & INT_CMDDONE) {
1681                         out_8(&mr->interrupt, INT_CMDDONE);
1682                         cmd_complete(ms);
1683                 }
1684         }
1685 }
1686
1687 /* Todo: here we can at least try to remove the command from the
1688  * queue if it isn't connected yet, and for pending command, assert
1689  * ATN until the bus gets freed.
1690  */
1691 static int mesh_abort(struct scsi_cmnd *cmd)
1692 {
1693         struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata;
1694
1695         printk(KERN_DEBUG "mesh_abort(%p)\n", cmd);
1696         mesh_dump_regs(ms);
1697         dumplog(ms, cmd->device->id);
1698         dumpslog(ms);
1699         return FAILED;
1700 }
1701
1702 /*
1703  * Called by the midlayer with the lock held to reset the
1704  * SCSI host and bus.
1705  * The midlayer will wait for devices to come back, we don't need
1706  * to do that ourselves
1707  */
1708 static int mesh_host_reset(struct scsi_cmnd *cmd)
1709 {
1710         struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata;
1711         volatile struct mesh_regs __iomem *mr = ms->mesh;
1712         volatile struct dbdma_regs __iomem *md = ms->dma;
1713         unsigned long flags;
1714
1715         printk(KERN_DEBUG "mesh_host_reset\n");
1716
1717         spin_lock_irqsave(ms->host->host_lock, flags);
1718
1719         if (ms->dma_started)
1720                 halt_dma(ms);
1721
1722         /* Reset the controller & dbdma channel */
1723         out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16);   /* stop dma */
1724         out_8(&mr->exception, 0xff);    /* clear all exception bits */
1725         out_8(&mr->error, 0xff);        /* clear all error bits */
1726         out_8(&mr->sequence, SEQ_RESETMESH);
1727         mesh_flush_io(mr);
1728         udelay(1);
1729         out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1730         out_8(&mr->source_id, ms->host->this_id);
1731         out_8(&mr->sel_timeout, 25);    /* 250ms */
1732         out_8(&mr->sync_params, ASYNC_PARAMS);
1733
1734         /* Reset the bus */
1735         out_8(&mr->bus_status1, BS1_RST);       /* assert RST */
1736         mesh_flush_io(mr);
1737         udelay(30);                     /* leave it on for >= 25us */
1738         out_8(&mr->bus_status1, 0);     /* negate RST */
1739
1740         /* Complete pending commands */
1741         handle_reset(ms);
1742
1743         spin_unlock_irqrestore(ms->host->host_lock, flags);
1744         return SUCCESS;
1745 }
1746
1747 static void set_mesh_power(struct mesh_state *ms, int state)
1748 {
1749         if (!machine_is(powermac))
1750                 return;
1751         if (state) {
1752                 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 1);
1753                 msleep(200);
1754         } else {
1755                 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 0);
1756                 msleep(10);
1757         }
1758 }
1759
1760
1761 #ifdef CONFIG_PM
1762 static int mesh_suspend(struct macio_dev *mdev, pm_message_t mesg)
1763 {
1764         struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1765         unsigned long flags;
1766
1767         switch (mesg.event) {
1768         case PM_EVENT_SUSPEND:
1769         case PM_EVENT_HIBERNATE:
1770         case PM_EVENT_FREEZE:
1771                 break;
1772         default:
1773                 return 0;
1774         }
1775         if (ms->phase == sleeping)
1776                 return 0;
1777
1778         scsi_block_requests(ms->host);
1779         spin_lock_irqsave(ms->host->host_lock, flags);
1780         while(ms->phase != idle) {
1781                 spin_unlock_irqrestore(ms->host->host_lock, flags);
1782                 msleep(10);
1783                 spin_lock_irqsave(ms->host->host_lock, flags);
1784         }
1785         ms->phase = sleeping;
1786         spin_unlock_irqrestore(ms->host->host_lock, flags);
1787         disable_irq(ms->meshintr);
1788         set_mesh_power(ms, 0);
1789
1790         return 0;
1791 }
1792
1793 static int mesh_resume(struct macio_dev *mdev)
1794 {
1795         struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1796         unsigned long flags;
1797
1798         if (ms->phase != sleeping)
1799                 return 0;
1800
1801         set_mesh_power(ms, 1);
1802         mesh_init(ms);
1803         spin_lock_irqsave(ms->host->host_lock, flags);
1804         mesh_start(ms);
1805         spin_unlock_irqrestore(ms->host->host_lock, flags);
1806         enable_irq(ms->meshintr);
1807         scsi_unblock_requests(ms->host);
1808
1809         return 0;
1810 }
1811
1812 #endif /* CONFIG_PM */
1813
1814 /*
1815  * If we leave drives set for synchronous transfers (especially
1816  * CDROMs), and reboot to MacOS, it gets confused, poor thing.
1817  * So, on reboot we reset the SCSI bus.
1818  */
1819 static int mesh_shutdown(struct macio_dev *mdev)
1820 {
1821         struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1822         volatile struct mesh_regs __iomem *mr;
1823         unsigned long flags;
1824
1825         printk(KERN_INFO "resetting MESH scsi bus(es)\n");
1826         spin_lock_irqsave(ms->host->host_lock, flags);
1827         mr = ms->mesh;
1828         out_8(&mr->intr_mask, 0);
1829         out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1830         out_8(&mr->bus_status1, BS1_RST);
1831         mesh_flush_io(mr);
1832         udelay(30);
1833         out_8(&mr->bus_status1, 0);
1834         spin_unlock_irqrestore(ms->host->host_lock, flags);
1835
1836         return 0;
1837 }
1838
1839 static struct scsi_host_template mesh_template = {
1840         .proc_name                      = "mesh",
1841         .name                           = "MESH",
1842         .queuecommand                   = mesh_queue,
1843         .eh_abort_handler               = mesh_abort,
1844         .eh_host_reset_handler          = mesh_host_reset,
1845         .can_queue                      = 20,
1846         .this_id                        = 7,
1847         .sg_tablesize                   = SG_ALL,
1848         .cmd_per_lun                    = 2,
1849         .max_segment_size               = 65535,
1850 };
1851
1852 static int mesh_probe(struct macio_dev *mdev, const struct of_device_id *match)
1853 {
1854         struct device_node *mesh = macio_get_of_node(mdev);
1855         struct pci_dev* pdev = macio_get_pci_dev(mdev);
1856         int tgt, minper;
1857         const int *cfp;
1858         struct mesh_state *ms;
1859         struct Scsi_Host *mesh_host;
1860         void *dma_cmd_space;
1861         dma_addr_t dma_cmd_bus;
1862
1863         switch (mdev->bus->chip->type) {
1864         case macio_heathrow:
1865         case macio_gatwick:
1866         case macio_paddington:
1867                 use_active_neg = 0;
1868                 break;
1869         default:
1870                 use_active_neg = SEQ_ACTIVE_NEG;
1871         }
1872
1873         if (macio_resource_count(mdev) != 2 || macio_irq_count(mdev) != 2) {
1874                 printk(KERN_ERR "mesh: expected 2 addrs and 2 intrs"
1875                        " (got %d,%d)\n", macio_resource_count(mdev),
1876                        macio_irq_count(mdev));
1877                 return -ENODEV;
1878         }
1879
1880         if (macio_request_resources(mdev, "mesh") != 0) {
1881                 printk(KERN_ERR "mesh: unable to request memory resources");
1882                 return -EBUSY;
1883         }
1884         mesh_host = scsi_host_alloc(&mesh_template, sizeof(struct mesh_state));
1885         if (mesh_host == NULL) {
1886                 printk(KERN_ERR "mesh: couldn't register host");
1887                 goto out_release;
1888         }
1889
1890         /* Old junk for root discovery, that will die ultimately */
1891 #if !defined(MODULE)
1892         note_scsi_host(mesh, mesh_host);
1893 #endif
1894
1895         mesh_host->base = macio_resource_start(mdev, 0);
1896         mesh_host->irq = macio_irq(mdev, 0);
1897         ms = (struct mesh_state *) mesh_host->hostdata;
1898         macio_set_drvdata(mdev, ms);
1899         ms->host = mesh_host;
1900         ms->mdev = mdev;
1901         ms->pdev = pdev;
1902
1903         ms->mesh = ioremap(macio_resource_start(mdev, 0), 0x1000);
1904         if (ms->mesh == NULL) {
1905                 printk(KERN_ERR "mesh: can't map registers\n");
1906                 goto out_free;
1907         }
1908         ms->dma = ioremap(macio_resource_start(mdev, 1), 0x1000);
1909         if (ms->dma == NULL) {
1910                 printk(KERN_ERR "mesh: can't map registers\n");
1911                 iounmap(ms->mesh);
1912                 goto out_free;
1913         }
1914
1915         ms->meshintr = macio_irq(mdev, 0);
1916         ms->dmaintr = macio_irq(mdev, 1);
1917
1918         /* Space for dma command list: +1 for stop command,
1919          * +1 to allow for aligning.
1920          */
1921         ms->dma_cmd_size = (mesh_host->sg_tablesize + 2) * sizeof(struct dbdma_cmd);
1922
1923         /* We use the PCI APIs for now until the generic one gets fixed
1924          * enough or until we get some macio-specific versions
1925          */
1926         dma_cmd_space = dma_alloc_coherent(&macio_get_pci_dev(mdev)->dev,
1927                                            ms->dma_cmd_size, &dma_cmd_bus,
1928                                            GFP_KERNEL);
1929         if (dma_cmd_space == NULL) {
1930                 printk(KERN_ERR "mesh: can't allocate DMA table\n");
1931                 goto out_unmap;
1932         }
1933
1934         ms->dma_cmds = (struct dbdma_cmd *) DBDMA_ALIGN(dma_cmd_space);
1935         ms->dma_cmd_space = dma_cmd_space;
1936         ms->dma_cmd_bus = dma_cmd_bus + ((unsigned long)ms->dma_cmds)
1937                 - (unsigned long)dma_cmd_space;
1938         ms->current_req = NULL;
1939         for (tgt = 0; tgt < 8; ++tgt) {
1940                 ms->tgts[tgt].sdtr_state = do_sdtr;
1941                 ms->tgts[tgt].sync_params = ASYNC_PARAMS;
1942                 ms->tgts[tgt].current_req = NULL;
1943         }
1944
1945         if ((cfp = of_get_property(mesh, "clock-frequency", NULL)))
1946                 ms->clk_freq = *cfp;
1947         else {
1948                 printk(KERN_INFO "mesh: assuming 50MHz clock frequency\n");
1949                 ms->clk_freq = 50000000;
1950         }
1951
1952         /* The maximum sync rate is clock / 5; increase
1953          * mesh_sync_period if necessary.
1954          */
1955         minper = 1000000000 / (ms->clk_freq / 5); /* ns */
1956         if (mesh_sync_period < minper)
1957                 mesh_sync_period = minper;
1958
1959         /* Power up the chip */
1960         set_mesh_power(ms, 1);
1961
1962         /* Set it up */
1963         mesh_init(ms);
1964
1965         /* Request interrupt */
1966         if (request_irq(ms->meshintr, do_mesh_interrupt, 0, "MESH", ms)) {
1967                 printk(KERN_ERR "MESH: can't get irq %d\n", ms->meshintr);
1968                 goto out_shutdown;
1969         }
1970
1971         /* Add scsi host & scan */
1972         if (scsi_add_host(mesh_host, &mdev->ofdev.dev))
1973                 goto out_release_irq;
1974         scsi_scan_host(mesh_host);
1975
1976         return 0;
1977
1978  out_release_irq:
1979         free_irq(ms->meshintr, ms);
1980  out_shutdown:
1981         /* shutdown & reset bus in case of error or macos can be confused
1982          * at reboot if the bus was set to synchronous mode already
1983          */
1984         mesh_shutdown(mdev);
1985         set_mesh_power(ms, 0);
1986         dma_free_coherent(&macio_get_pci_dev(mdev)->dev, ms->dma_cmd_size,
1987                             ms->dma_cmd_space, ms->dma_cmd_bus);
1988  out_unmap:
1989         iounmap(ms->dma);
1990         iounmap(ms->mesh);
1991  out_free:
1992         scsi_host_put(mesh_host);
1993  out_release:
1994         macio_release_resources(mdev);
1995
1996         return -ENODEV;
1997 }
1998
1999 static int mesh_remove(struct macio_dev *mdev)
2000 {
2001         struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
2002         struct Scsi_Host *mesh_host = ms->host;
2003
2004         scsi_remove_host(mesh_host);
2005
2006         free_irq(ms->meshintr, ms);
2007
2008         /* Reset scsi bus */
2009         mesh_shutdown(mdev);
2010
2011         /* Shut down chip & termination */
2012         set_mesh_power(ms, 0);
2013
2014         /* Unmap registers & dma controller */
2015         iounmap(ms->mesh);
2016         iounmap(ms->dma);
2017
2018         /* Free DMA commands memory */
2019         dma_free_coherent(&macio_get_pci_dev(mdev)->dev, ms->dma_cmd_size,
2020                             ms->dma_cmd_space, ms->dma_cmd_bus);
2021
2022         /* Release memory resources */
2023         macio_release_resources(mdev);
2024
2025         scsi_host_put(mesh_host);
2026
2027         return 0;
2028 }
2029
2030
2031 static struct of_device_id mesh_match[] =
2032 {
2033         {
2034         .name           = "mesh",
2035         },
2036         {
2037         .type           = "scsi",
2038         .compatible     = "chrp,mesh0"
2039         },
2040         {},
2041 };
2042 MODULE_DEVICE_TABLE (of, mesh_match);
2043
2044 static struct macio_driver mesh_driver =
2045 {
2046         .driver = {
2047                 .name           = "mesh",
2048                 .owner          = THIS_MODULE,
2049                 .of_match_table = mesh_match,
2050         },
2051         .probe          = mesh_probe,
2052         .remove         = mesh_remove,
2053         .shutdown       = mesh_shutdown,
2054 #ifdef CONFIG_PM
2055         .suspend        = mesh_suspend,
2056         .resume         = mesh_resume,
2057 #endif
2058 };
2059
2060
2061 static int __init init_mesh(void)
2062 {
2063
2064         /* Calculate sync rate from module parameters */
2065         if (sync_rate > 10)
2066                 sync_rate = 10;
2067         if (sync_rate > 0) {
2068                 printk(KERN_INFO "mesh: configured for synchronous %d MB/s\n", sync_rate);
2069                 mesh_sync_period = 1000 / sync_rate;    /* ns */
2070                 mesh_sync_offset = 15;
2071         } else
2072                 printk(KERN_INFO "mesh: configured for asynchronous\n");
2073
2074         return macio_register_driver(&mesh_driver);
2075 }
2076
2077 static void __exit exit_mesh(void)
2078 {
2079         return macio_unregister_driver(&mesh_driver);
2080 }
2081
2082 module_init(init_mesh);
2083 module_exit(exit_mesh);