1 // SPDX-License-Identifier: GPL-2.0-only
3 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
4 * bus adaptor found on Power Macintosh computers.
5 * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
8 * Paul Mackerras, August 1996.
9 * Copyright (C) 1996 Paul Mackerras.
11 * Apr. 21 2002 - BenH Rework bus reset code for new error handler
12 * Add delay after initial bus reset
13 * Add module parameters
15 * Sep. 27 2003 - BenH Move to new driver model, fix some write posting
18 * - handle aborts correctly
19 * - retry arbitration if lost (unless higher levels do this for us)
20 * - power down the chip when no device is detected
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/delay.h>
25 #include <linux/types.h>
26 #include <linux/string.h>
27 #include <linux/blkdev.h>
28 #include <linux/proc_fs.h>
29 #include <linux/stat.h>
30 #include <linux/interrupt.h>
31 #include <linux/reboot.h>
32 #include <linux/spinlock.h>
33 #include <linux/pci.h>
34 #include <linux/pgtable.h>
35 #include <asm/dbdma.h>
39 #include <asm/hydra.h>
40 #include <asm/processor.h>
41 #include <asm/machdep.h>
42 #include <asm/pmac_feature.h>
43 #include <asm/macio.h>
45 #include <scsi/scsi.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <scsi/scsi_device.h>
48 #include <scsi/scsi_host.h>
54 #define KERN_DEBUG KERN_WARNING
57 MODULE_AUTHOR("Paul Mackerras (paulus@samba.org)");
58 MODULE_DESCRIPTION("PowerMac MESH SCSI driver");
59 MODULE_LICENSE("GPL");
61 static int sync_rate = CONFIG_SCSI_MESH_SYNC_RATE;
62 static int sync_targets = 0xff;
63 static int resel_targets = 0xff;
64 static int debug_targets = 0; /* print debug for these targets */
65 static int init_reset_delay = CONFIG_SCSI_MESH_RESET_DELAY_MS;
67 module_param(sync_rate, int, 0);
68 MODULE_PARM_DESC(sync_rate, "Synchronous rate (0..10, 0=async)");
69 module_param(sync_targets, int, 0);
70 MODULE_PARM_DESC(sync_targets, "Bitmask of targets allowed to set synchronous");
71 module_param(resel_targets, int, 0);
72 MODULE_PARM_DESC(resel_targets, "Bitmask of targets allowed to set disconnect");
73 module_param(debug_targets, int, 0644);
74 MODULE_PARM_DESC(debug_targets, "Bitmask of debugged targets");
75 module_param(init_reset_delay, int, 0);
76 MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)");
78 static int mesh_sync_period = 100;
79 static int mesh_sync_offset = 0;
80 static unsigned char use_active_neg = 0; /* bit mask for SEQ_ACTIVE_NEG if used */
82 #define ALLOW_SYNC(tgt) ((sync_targets >> (tgt)) & 1)
83 #define ALLOW_RESEL(tgt) ((resel_targets >> (tgt)) & 1)
84 #define ALLOW_DEBUG(tgt) ((debug_targets >> (tgt)) & 1)
85 #define DEBUG_TARGET(cmd) ((cmd) && ALLOW_DEBUG((cmd)->device->id))
90 #define NUM_DBG_EVENTS 13
91 #undef DBG_USE_TB /* bombs on 601 */
132 enum sdtr_phase sdtr_state;
134 int data_goes_out; /* guess as to data direction */
135 struct scsi_cmnd *current_req;
140 struct dbglog log[N_DBG_LOG];
145 volatile struct mesh_regs __iomem *mesh;
147 volatile struct dbdma_regs __iomem *dma;
149 struct Scsi_Host *host;
150 struct mesh_state *next;
151 struct scsi_cmnd *request_q;
152 struct scsi_cmnd *request_qtail;
153 enum mesh_phase phase; /* what we're currently trying to do */
154 enum msg_phase msgphase;
155 int conn_tgt; /* target we're connected to */
156 struct scsi_cmnd *current_req; /* req we're currently working on */
168 struct dbdma_cmd *dma_cmds; /* space for dbdma commands, aligned */
169 dma_addr_t dma_cmd_bus;
173 struct mesh_target tgts[8];
174 struct macio_dev *mdev;
175 struct pci_dev* pdev;
179 struct dbglog log[N_DBG_SLOG];
184 * Driver is too messy, we need a few prototypes...
186 static void mesh_done(struct mesh_state *ms, int start_next);
187 static void mesh_interrupt(struct mesh_state *ms);
188 static void cmd_complete(struct mesh_state *ms);
189 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd);
190 static void halt_dma(struct mesh_state *ms);
191 static void phase_mismatch(struct mesh_state *ms);
195 * Some debugging & logging routines
200 static inline u32 readtb(void)
205 /* Beware: if you enable this, it will crash on 601s. */
206 asm ("mftb %0" : "=r" (tb) : );
213 static void dlog(struct mesh_state *ms, char *fmt, int a)
215 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
216 struct dbglog *tlp, *slp;
218 tlp = &tp->log[tp->log_ix];
219 slp = &ms->log[ms->log_ix];
222 tlp->phase = (ms->msgphase << 4) + ms->phase;
223 tlp->bs0 = ms->mesh->bus_status0;
224 tlp->bs1 = ms->mesh->bus_status1;
225 tlp->tgt = ms->conn_tgt;
228 if (++tp->log_ix >= N_DBG_LOG)
230 if (tp->n_log < N_DBG_LOG)
232 if (++ms->log_ix >= N_DBG_SLOG)
234 if (ms->n_log < N_DBG_SLOG)
238 static void dumplog(struct mesh_state *ms, int t)
240 struct mesh_target *tp = &ms->tgts[t];
246 i = tp->log_ix - tp->n_log;
252 printk(KERN_DEBUG "mesh log %d: bs=%.2x%.2x ph=%.2x ",
253 t, lp->bs1, lp->bs0, lp->phase);
255 printk("tb=%10u ", lp->tb);
257 printk(lp->fmt, lp->d);
259 if (++i >= N_DBG_LOG)
261 } while (i != tp->log_ix);
264 static void dumpslog(struct mesh_state *ms)
271 i = ms->log_ix - ms->n_log;
277 printk(KERN_DEBUG "mesh log: bs=%.2x%.2x ph=%.2x t%d ",
278 lp->bs1, lp->bs0, lp->phase, lp->tgt);
280 printk("tb=%10u ", lp->tb);
282 printk(lp->fmt, lp->d);
284 if (++i >= N_DBG_SLOG)
286 } while (i != ms->log_ix);
291 static inline void dlog(struct mesh_state *ms, char *fmt, int a)
293 static inline void dumplog(struct mesh_state *ms, int tgt)
295 static inline void dumpslog(struct mesh_state *ms)
298 #endif /* MESH_DBG */
300 #define MKWORD(a, b, c, d) (((a) << 24) + ((b) << 16) + ((c) << 8) + (d))
303 mesh_dump_regs(struct mesh_state *ms)
305 volatile struct mesh_regs __iomem *mr = ms->mesh;
306 volatile struct dbdma_regs __iomem *md = ms->dma;
308 struct mesh_target *tp;
310 printk(KERN_DEBUG "mesh: state at %p, regs at %p, dma at %p\n",
312 printk(KERN_DEBUG " ct=%4x seq=%2x bs=%4x fc=%2x "
313 "exc=%2x err=%2x im=%2x int=%2x sp=%2x\n",
314 (mr->count_hi << 8) + mr->count_lo, mr->sequence,
315 (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count,
316 mr->exception, mr->error, mr->intr_mask, mr->interrupt,
318 while(in_8(&mr->fifo_count))
319 printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo));
320 printk(KERN_DEBUG " dma stat=%x cmdptr=%x\n",
321 in_le32(&md->status), in_le32(&md->cmdptr));
322 printk(KERN_DEBUG " phase=%d msgphase=%d conn_tgt=%d data_ptr=%d\n",
323 ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr);
324 printk(KERN_DEBUG " dma_st=%d dma_ct=%d n_msgout=%d\n",
325 ms->dma_started, ms->dma_count, ms->n_msgout);
326 for (t = 0; t < 8; ++t) {
328 if (tp->current_req == NULL)
330 printk(KERN_DEBUG " target %d: req=%p goes_out=%d saved_ptr=%d\n",
331 t, tp->current_req, tp->data_goes_out, tp->saved_ptr);
337 * Flush write buffers on the bus path to the mesh
339 static inline void mesh_flush_io(volatile struct mesh_regs __iomem *mr)
341 (void)in_8(&mr->mesh_id);
346 * Complete a SCSI command
348 static void mesh_completed(struct mesh_state *ms, struct scsi_cmnd *cmd)
350 (*cmd->scsi_done)(cmd);
354 /* Called with meshinterrupt disabled, initialize the chipset
355 * and eventually do the initial bus reset. The lock must not be
356 * held since we can schedule.
358 static void mesh_init(struct mesh_state *ms)
360 volatile struct mesh_regs __iomem *mr = ms->mesh;
361 volatile struct dbdma_regs __iomem *md = ms->dma;
366 /* Reset controller */
367 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */
368 out_8(&mr->exception, 0xff); /* clear all exception bits */
369 out_8(&mr->error, 0xff); /* clear all error bits */
370 out_8(&mr->sequence, SEQ_RESETMESH);
373 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
374 out_8(&mr->source_id, ms->host->this_id);
375 out_8(&mr->sel_timeout, 25); /* 250ms */
376 out_8(&mr->sync_params, ASYNC_PARAMS);
378 if (init_reset_delay) {
379 printk(KERN_INFO "mesh: performing initial bus reset...\n");
382 out_8(&mr->bus_status1, BS1_RST); /* assert RST */
384 udelay(30); /* leave it on for >= 25us */
385 out_8(&mr->bus_status1, 0); /* negate RST */
388 /* Wait for bus to come back */
389 msleep(init_reset_delay);
392 /* Reconfigure controller */
393 out_8(&mr->interrupt, 0xff); /* clear all interrupt bits */
394 out_8(&mr->sequence, SEQ_FLUSHFIFO);
397 out_8(&mr->sync_params, ASYNC_PARAMS);
398 out_8(&mr->sequence, SEQ_ENBRESEL);
401 ms->msgphase = msg_none;
405 static void mesh_start_cmd(struct mesh_state *ms, struct scsi_cmnd *cmd)
407 volatile struct mesh_regs __iomem *mr = ms->mesh;
410 id = cmd->device->id;
411 ms->current_req = cmd;
412 ms->tgts[id].data_goes_out = cmd->sc_data_direction == DMA_TO_DEVICE;
413 ms->tgts[id].current_req = cmd;
416 if (DEBUG_TARGET(cmd)) {
418 printk(KERN_DEBUG "mesh_start: %p tgt=%d cmd=", cmd, id);
419 for (i = 0; i < cmd->cmd_len; ++i)
420 printk(" %x", cmd->cmnd[i]);
421 printk(" use_sg=%d buffer=%p bufflen=%u\n",
422 scsi_sg_count(cmd), scsi_sglist(cmd), scsi_bufflen(cmd));
426 panic("mesh: double DMA start !\n");
428 ms->phase = arbitrating;
429 ms->msgphase = msg_none;
433 ms->last_n_msgout = 0;
434 ms->expect_reply = 0;
436 ms->tgts[id].saved_ptr = 0;
440 ms->tgts[id].n_log = 0;
441 dlog(ms, "start cmd=%x", (int) cmd);
445 dlog(ms, "about to arb, intr/exc/err/fc=%.8x",
446 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
447 out_8(&mr->interrupt, INT_CMDDONE);
448 out_8(&mr->sequence, SEQ_ENBRESEL);
452 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
454 * Some other device has the bus or is arbitrating for it -
455 * probably a target which is about to reselect us.
457 dlog(ms, "busy b4 arb, intr/exc/err/fc=%.8x",
458 MKWORD(mr->interrupt, mr->exception,
459 mr->error, mr->fifo_count));
460 for (t = 100; t > 0; --t) {
461 if ((in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) == 0)
463 if (in_8(&mr->interrupt) != 0) {
464 dlog(ms, "intr b4 arb, intr/exc/err/fc=%.8x",
465 MKWORD(mr->interrupt, mr->exception,
466 mr->error, mr->fifo_count));
468 if (ms->phase != arbitrating)
473 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
474 /* XXX should try again in a little while */
475 ms->stat = DID_BUS_BUSY;
483 * Apparently the mesh has a bug where it will assert both its
484 * own bit and the target's bit on the bus during arbitration.
486 out_8(&mr->dest_id, mr->source_id);
489 * There appears to be a race with reselection sometimes,
490 * where a target reselects us just as we issue the
491 * arbitrate command. It seems that then the arbitrate
492 * command just hangs waiting for the bus to be free
493 * without giving us a reselection exception.
494 * The only way I have found to get it to respond correctly
495 * is this: disable reselection before issuing the arbitrate
496 * command, then after issuing it, if it looks like a target
497 * is trying to reselect us, reset the mesh and then enable
500 out_8(&mr->sequence, SEQ_DISRESEL);
501 if (in_8(&mr->interrupt) != 0) {
502 dlog(ms, "intr after disresel, intr/exc/err/fc=%.8x",
503 MKWORD(mr->interrupt, mr->exception,
504 mr->error, mr->fifo_count));
506 if (ms->phase != arbitrating)
508 dlog(ms, "after intr after disresel, intr/exc/err/fc=%.8x",
509 MKWORD(mr->interrupt, mr->exception,
510 mr->error, mr->fifo_count));
513 out_8(&mr->sequence, SEQ_ARBITRATE);
515 for (t = 230; t > 0; --t) {
516 if (in_8(&mr->interrupt) != 0)
520 dlog(ms, "after arb, intr/exc/err/fc=%.8x",
521 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
522 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
523 && (in_8(&mr->bus_status0) & BS0_IO)) {
524 /* looks like a reselection - try resetting the mesh */
525 dlog(ms, "resel? after arb, intr/exc/err/fc=%.8x",
526 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
527 out_8(&mr->sequence, SEQ_RESETMESH);
530 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
531 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
532 out_8(&mr->sequence, SEQ_ENBRESEL);
534 for (t = 10; t > 0 && in_8(&mr->interrupt) == 0; --t)
536 dlog(ms, "tried reset after arb, intr/exc/err/fc=%.8x",
537 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
538 #ifndef MESH_MULTIPLE_HOSTS
539 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
540 && (in_8(&mr->bus_status0) & BS0_IO)) {
541 printk(KERN_ERR "mesh: controller not responding"
542 " to reselection!\n");
544 * If this is a target reselecting us, and the
545 * mesh isn't responding, the higher levels of
546 * the scsi code will eventually time out and
555 * Start the next command for a MESH.
556 * Should be called with interrupts disabled.
558 static void mesh_start(struct mesh_state *ms)
560 struct scsi_cmnd *cmd, *prev, *next;
562 if (ms->phase != idle || ms->current_req != NULL) {
563 printk(KERN_ERR "inappropriate mesh_start (phase=%d, ms=%p)",
568 while (ms->phase == idle) {
570 for (cmd = ms->request_q; ; cmd = (struct scsi_cmnd *) cmd->host_scribble) {
573 if (ms->tgts[cmd->device->id].current_req == NULL)
577 next = (struct scsi_cmnd *) cmd->host_scribble;
579 ms->request_q = next;
581 prev->host_scribble = (void *) next;
583 ms->request_qtail = prev;
585 mesh_start_cmd(ms, cmd);
589 static void mesh_done(struct mesh_state *ms, int start_next)
591 struct scsi_cmnd *cmd;
592 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
594 cmd = ms->current_req;
595 ms->current_req = NULL;
596 tp->current_req = NULL;
598 set_host_byte(cmd, ms->stat);
599 set_status_byte(cmd, cmd->SCp.Status);
600 if (ms->stat == DID_OK)
601 scsi_msg_to_host_byte(cmd, cmd->SCp.Message);
602 if (DEBUG_TARGET(cmd)) {
603 printk(KERN_DEBUG "mesh_done: result = %x, data_ptr=%d, buflen=%d\n",
604 cmd->result, ms->data_ptr, scsi_bufflen(cmd));
606 /* needs to use sg? */
607 if ((cmd->cmnd[0] == 0 || cmd->cmnd[0] == 0x12 || cmd->cmnd[0] == 3)
608 && cmd->request_buffer != 0) {
609 unsigned char *b = cmd->request_buffer;
610 printk(KERN_DEBUG "buffer = %x %x %x %x %x %x %x %x\n",
611 b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
615 cmd->SCp.this_residual -= ms->data_ptr;
616 mesh_completed(ms, cmd);
619 out_8(&ms->mesh->sequence, SEQ_ENBRESEL);
620 mesh_flush_io(ms->mesh);
627 static inline void add_sdtr_msg(struct mesh_state *ms)
629 int i = ms->n_msgout;
631 ms->msgout[i] = EXTENDED_MESSAGE;
633 ms->msgout[i+2] = EXTENDED_SDTR;
634 ms->msgout[i+3] = mesh_sync_period/4;
635 ms->msgout[i+4] = (ALLOW_SYNC(ms->conn_tgt)? mesh_sync_offset: 0);
636 ms->n_msgout = i + 5;
639 static void set_sdtr(struct mesh_state *ms, int period, int offset)
641 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
642 volatile struct mesh_regs __iomem *mr = ms->mesh;
645 tp->sdtr_state = sdtr_done;
648 if (SYNC_OFF(tp->sync_params))
649 printk(KERN_INFO "mesh: target %d now asynchronous\n",
651 tp->sync_params = ASYNC_PARAMS;
652 out_8(&mr->sync_params, ASYNC_PARAMS);
656 * We need to compute ceil(clk_freq * period / 500e6) - 2
657 * without incurring overflow.
659 v = (ms->clk_freq / 5000) * period;
661 /* special case: sync_period == 5 * clk_period */
663 /* units of tr are 100kB/s */
664 tr = (ms->clk_freq + 250000) / 500000;
666 /* sync_period == (v + 2) * 2 * clk_period */
667 v = (v + 99999) / 100000 - 2;
670 tr = ((ms->clk_freq / (v + 2)) + 199999) / 200000;
673 offset = 15; /* can't happen */
674 tp->sync_params = SYNC_PARAMS(offset, v);
675 out_8(&mr->sync_params, tp->sync_params);
676 printk(KERN_INFO "mesh: target %d synchronous at %d.%d MB/s\n",
677 ms->conn_tgt, tr/10, tr%10);
680 static void start_phase(struct mesh_state *ms)
683 volatile struct mesh_regs __iomem *mr = ms->mesh;
684 volatile struct dbdma_regs __iomem *md = ms->dma;
685 struct scsi_cmnd *cmd = ms->current_req;
686 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
688 dlog(ms, "start_phase nmo/exc/fc/seq = %.8x",
689 MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence));
690 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
691 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
692 switch (ms->msgphase) {
697 out_8(&mr->count_hi, 0);
698 out_8(&mr->count_lo, 1);
699 out_8(&mr->sequence, SEQ_MSGIN + seq);
705 * To make sure ATN drops before we assert ACK for
706 * the last byte of the message, we have to do the
707 * last byte specially.
709 if (ms->n_msgout <= 0) {
710 printk(KERN_ERR "mesh: msg_out but n_msgout=%d\n",
713 ms->msgphase = msg_none;
716 if (ALLOW_DEBUG(ms->conn_tgt)) {
717 printk(KERN_DEBUG "mesh: sending %d msg bytes:",
719 for (i = 0; i < ms->n_msgout; ++i)
720 printk(" %x", ms->msgout[i]);
723 dlog(ms, "msgout msg=%.8x", MKWORD(ms->n_msgout, ms->msgout[0],
724 ms->msgout[1], ms->msgout[2]));
725 out_8(&mr->count_hi, 0);
726 out_8(&mr->sequence, SEQ_FLUSHFIFO);
730 * If ATN is not already asserted, we assert it, then
731 * issue a SEQ_MSGOUT to get the mesh to drop ACK.
733 if ((in_8(&mr->bus_status0) & BS0_ATN) == 0) {
734 dlog(ms, "bus0 was %.2x explicitly asserting ATN", mr->bus_status0);
735 out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */
738 out_8(&mr->count_lo, 1);
739 out_8(&mr->sequence, SEQ_MSGOUT + seq);
740 out_8(&mr->bus_status0, 0); /* release explicit ATN */
741 dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0);
743 if (ms->n_msgout == 1) {
745 * We can't issue the SEQ_MSGOUT without ATN
746 * until the target has asserted REQ. The logic
747 * in cmd_complete handles both situations:
748 * REQ already asserted or not.
752 out_8(&mr->count_lo, ms->n_msgout - 1);
753 out_8(&mr->sequence, SEQ_MSGOUT + seq);
754 for (i = 0; i < ms->n_msgout - 1; ++i)
755 out_8(&mr->fifo, ms->msgout[i]);
760 printk(KERN_ERR "mesh bug: start_phase msgphase=%d\n",
766 out_8(&mr->dest_id, ms->conn_tgt);
767 out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN);
770 out_8(&mr->sync_params, tp->sync_params);
771 out_8(&mr->count_hi, 0);
773 out_8(&mr->count_lo, cmd->cmd_len);
774 out_8(&mr->sequence, SEQ_COMMAND + seq);
775 for (i = 0; i < cmd->cmd_len; ++i)
776 out_8(&mr->fifo, cmd->cmnd[i]);
778 out_8(&mr->count_lo, 6);
779 out_8(&mr->sequence, SEQ_COMMAND + seq);
780 for (i = 0; i < 6; ++i)
785 /* transfer data, if any */
786 if (!ms->dma_started) {
787 set_dma_cmds(ms, cmd);
788 out_le32(&md->cmdptr, virt_to_phys(ms->dma_cmds));
789 out_le32(&md->control, (RUN << 16) | RUN);
797 out_8(&mr->count_lo, nb);
798 out_8(&mr->count_hi, nb >> 8);
799 out_8(&mr->sequence, (tp->data_goes_out?
800 SEQ_DATAOUT: SEQ_DATAIN) + SEQ_DMA_MODE + seq);
803 out_8(&mr->count_hi, 0);
804 out_8(&mr->count_lo, 1);
805 out_8(&mr->sequence, SEQ_STATUS + seq);
809 out_8(&mr->sequence, SEQ_ENBRESEL);
812 dlog(ms, "enbresel intr/exc/err/fc=%.8x",
813 MKWORD(mr->interrupt, mr->exception, mr->error,
815 out_8(&mr->sequence, SEQ_BUSFREE);
818 printk(KERN_ERR "mesh: start_phase called with phase=%d\n",
825 static inline void get_msgin(struct mesh_state *ms)
827 volatile struct mesh_regs __iomem *mr = ms->mesh;
835 ms->msgin[i++] = in_8(&mr->fifo);
839 static inline int msgin_length(struct mesh_state *ms)
844 if (ms->n_msgin > 0) {
847 /* extended message */
848 n = ms->n_msgin < 2? 2: ms->msgin[1] + 2;
849 } else if (0x20 <= b && b <= 0x2f) {
857 static void reselected(struct mesh_state *ms)
859 volatile struct mesh_regs __iomem *mr = ms->mesh;
860 struct scsi_cmnd *cmd;
861 struct mesh_target *tp;
868 if ((cmd = ms->current_req) != NULL) {
869 /* put the command back on the queue */
870 cmd->host_scribble = (void *) ms->request_q;
871 if (ms->request_q == NULL)
872 ms->request_qtail = cmd;
874 tp = &ms->tgts[cmd->device->id];
875 tp->current_req = NULL;
879 ms->phase = reselecting;
885 printk(KERN_ERR "mesh: reselected in phase %d/%d tgt %d\n",
886 ms->msgphase, ms->phase, ms->conn_tgt);
887 dumplog(ms, ms->conn_tgt);
891 if (ms->dma_started) {
892 printk(KERN_ERR "mesh: reselected with DMA started !\n");
895 ms->current_req = NULL;
897 ms->msgphase = msg_in;
899 ms->last_n_msgout = 0;
903 * We seem to get abortive reselections sometimes.
905 while ((in_8(&mr->bus_status1) & BS1_BSY) == 0) {
906 static int mesh_aborted_resels;
907 mesh_aborted_resels++;
908 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
911 out_8(&mr->sequence, SEQ_ENBRESEL);
914 dlog(ms, "extra resel err/exc/fc = %.6x",
915 MKWORD(0, mr->error, mr->exception, mr->fifo_count));
917 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
920 out_8(&mr->sequence, SEQ_ENBRESEL);
923 out_8(&mr->sync_params, ASYNC_PARAMS);
926 * Find out who reselected us.
928 if (in_8(&mr->fifo_count) == 0) {
929 printk(KERN_ERR "mesh: reselection but nothing in fifo?\n");
930 ms->conn_tgt = ms->host->this_id;
933 /* get the last byte in the fifo */
936 dlog(ms, "reseldata %x", b);
937 } while (in_8(&mr->fifo_count));
938 for (t = 0; t < 8; ++t)
939 if ((b & (1 << t)) != 0 && t != ms->host->this_id)
941 if (b != (1 << t) + (1 << ms->host->this_id)) {
942 printk(KERN_ERR "mesh: bad reselection data %x\n", b);
943 ms->conn_tgt = ms->host->this_id;
949 * Set up to continue with that target's transfer.
953 out_8(&mr->sync_params, tp->sync_params);
954 if (ALLOW_DEBUG(t)) {
955 printk(KERN_DEBUG "mesh: reselected by target %d\n", t);
956 printk(KERN_DEBUG "mesh: saved_ptr=%x goes_out=%d cmd=%p\n",
957 tp->saved_ptr, tp->data_goes_out, tp->current_req);
959 ms->current_req = tp->current_req;
960 if (tp->current_req == NULL) {
961 printk(KERN_ERR "mesh: reselected by tgt %d but no cmd!\n", t);
964 ms->data_ptr = tp->saved_ptr;
965 dlog(ms, "resel prev tgt=%d", prev);
966 dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception));
971 dumplog(ms, ms->conn_tgt);
978 static void do_abort(struct mesh_state *ms)
980 ms->msgout[0] = ABORT;
983 ms->stat = DID_ABORT;
984 dlog(ms, "abort", 0);
987 static void handle_reset(struct mesh_state *ms)
990 struct mesh_target *tp;
991 struct scsi_cmnd *cmd;
992 volatile struct mesh_regs __iomem *mr = ms->mesh;
994 for (tgt = 0; tgt < 8; ++tgt) {
996 if ((cmd = tp->current_req) != NULL) {
997 set_host_byte(cmd, DID_RESET);
998 tp->current_req = NULL;
999 mesh_completed(ms, cmd);
1001 ms->tgts[tgt].sdtr_state = do_sdtr;
1002 ms->tgts[tgt].sync_params = ASYNC_PARAMS;
1004 ms->current_req = NULL;
1005 while ((cmd = ms->request_q) != NULL) {
1006 ms->request_q = (struct scsi_cmnd *) cmd->host_scribble;
1007 set_host_byte(cmd, DID_RESET);
1008 mesh_completed(ms, cmd);
1011 ms->msgphase = msg_none;
1012 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1013 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1016 out_8(&mr->sync_params, ASYNC_PARAMS);
1017 out_8(&mr->sequence, SEQ_ENBRESEL);
1020 static irqreturn_t do_mesh_interrupt(int irq, void *dev_id)
1022 unsigned long flags;
1023 struct mesh_state *ms = dev_id;
1024 struct Scsi_Host *dev = ms->host;
1026 spin_lock_irqsave(dev->host_lock, flags);
1028 spin_unlock_irqrestore(dev->host_lock, flags);
1032 static void handle_error(struct mesh_state *ms)
1034 int err, exc, count;
1035 volatile struct mesh_regs __iomem *mr = ms->mesh;
1037 err = in_8(&mr->error);
1038 exc = in_8(&mr->exception);
1039 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1040 dlog(ms, "error err/exc/fc/cl=%.8x",
1041 MKWORD(err, exc, mr->fifo_count, mr->count_lo));
1042 if (err & ERR_SCSIRESET) {
1043 /* SCSI bus was reset */
1044 printk(KERN_INFO "mesh: SCSI bus reset detected: "
1045 "waiting for end...");
1046 while ((in_8(&mr->bus_status1) & BS1_RST) != 0)
1049 if (ms->dma_started)
1052 /* request_q is empty, no point in mesh_start() */
1055 if (err & ERR_UNEXPDISC) {
1056 /* Unexpected disconnect */
1057 if (exc & EXC_RESELECTED) {
1061 if (!ms->aborting) {
1062 printk(KERN_WARNING "mesh: target %d aborted\n",
1064 dumplog(ms, ms->conn_tgt);
1067 out_8(&mr->interrupt, INT_CMDDONE);
1068 ms->stat = DID_ABORT;
1072 if (err & ERR_PARITY) {
1073 if (ms->msgphase == msg_in) {
1074 printk(KERN_ERR "mesh: msg parity error, target %d\n",
1076 ms->msgout[0] = MSG_PARITY_ERROR;
1078 ms->msgphase = msg_in_bad;
1082 if (ms->stat == DID_OK) {
1083 printk(KERN_ERR "mesh: parity error, target %d\n",
1085 ms->stat = DID_PARITY;
1087 count = (mr->count_hi << 8) + mr->count_lo;
1091 /* reissue the data transfer command */
1092 out_8(&mr->sequence, mr->sequence);
1096 if (err & ERR_SEQERR) {
1097 if (exc & EXC_RESELECTED) {
1098 /* This can happen if we issue a command to
1099 get the bus just after the target reselects us. */
1100 static int mesh_resel_seqerr;
1101 mesh_resel_seqerr++;
1105 if (exc == EXC_PHASEMM) {
1106 static int mesh_phasemm_seqerr;
1107 mesh_phasemm_seqerr++;
1111 printk(KERN_ERR "mesh: sequence error (err=%x exc=%x)\n",
1114 printk(KERN_ERR "mesh: unknown error %x (exc=%x)\n", err, exc);
1117 dumplog(ms, ms->conn_tgt);
1118 if (ms->phase > selecting && (in_8(&mr->bus_status1) & BS1_BSY)) {
1119 /* try to do what the target wants */
1124 ms->stat = DID_ERROR;
1128 static void handle_exception(struct mesh_state *ms)
1131 volatile struct mesh_regs __iomem *mr = ms->mesh;
1133 exc = in_8(&mr->exception);
1134 out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE);
1135 if (exc & EXC_RESELECTED) {
1136 static int mesh_resel_exc;
1139 } else if (exc == EXC_ARBLOST) {
1140 printk(KERN_DEBUG "mesh: lost arbitration\n");
1141 ms->stat = DID_BUS_BUSY;
1143 } else if (exc == EXC_SELTO) {
1144 /* selection timed out */
1145 ms->stat = DID_BAD_TARGET;
1147 } else if (exc == EXC_PHASEMM) {
1148 /* target wants to do something different:
1149 find out what it wants and do it. */
1152 printk(KERN_ERR "mesh: can't cope with exception %x\n", exc);
1154 dumplog(ms, ms->conn_tgt);
1160 static void handle_msgin(struct mesh_state *ms)
1163 struct scsi_cmnd *cmd = ms->current_req;
1164 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1166 if (ms->n_msgin == 0)
1168 code = ms->msgin[0];
1169 if (ALLOW_DEBUG(ms->conn_tgt)) {
1170 printk(KERN_DEBUG "got %d message bytes:", ms->n_msgin);
1171 for (i = 0; i < ms->n_msgin; ++i)
1172 printk(" %x", ms->msgin[i]);
1175 dlog(ms, "msgin msg=%.8x",
1176 MKWORD(ms->n_msgin, code, ms->msgin[1], ms->msgin[2]));
1178 ms->expect_reply = 0;
1180 if (ms->n_msgin < msgin_length(ms))
1183 cmd->SCp.Message = code;
1185 case COMMAND_COMPLETE:
1187 case EXTENDED_MESSAGE:
1188 switch (ms->msgin[2]) {
1189 case EXTENDED_MODIFY_DATA_POINTER:
1190 ms->data_ptr += (ms->msgin[3] << 24) + ms->msgin[6]
1191 + (ms->msgin[4] << 16) + (ms->msgin[5] << 8);
1194 if (tp->sdtr_state != sdtr_sent) {
1195 /* reply with an SDTR */
1197 /* limit period to at least his value,
1198 offset to no more than his */
1199 if (ms->msgout[3] < ms->msgin[3])
1200 ms->msgout[3] = ms->msgin[3];
1201 if (ms->msgout[4] > ms->msgin[4])
1202 ms->msgout[4] = ms->msgin[4];
1203 set_sdtr(ms, ms->msgout[3], ms->msgout[4]);
1204 ms->msgphase = msg_out;
1206 set_sdtr(ms, ms->msgin[3], ms->msgin[4]);
1214 tp->saved_ptr = ms->data_ptr;
1216 case RESTORE_POINTERS:
1217 ms->data_ptr = tp->saved_ptr;
1220 ms->phase = disconnecting;
1224 case MESSAGE_REJECT:
1225 if (tp->sdtr_state == sdtr_sent)
1231 if (IDENTIFY_BASE <= code && code <= IDENTIFY_BASE + 7) {
1234 ms->msgphase = msg_out;
1235 } else if (code != cmd->device->lun + IDENTIFY_BASE) {
1236 printk(KERN_WARNING "mesh: lun mismatch "
1237 "(%d != %llu) on reselection from "
1238 "target %d\n", code - IDENTIFY_BASE,
1239 cmd->device->lun, ms->conn_tgt);
1248 printk(KERN_WARNING "mesh: rejecting message from target %d:",
1250 for (i = 0; i < ms->n_msgin; ++i)
1251 printk(" %x", ms->msgin[i]);
1253 ms->msgout[0] = MESSAGE_REJECT;
1255 ms->msgphase = msg_out;
1259 * Set up DMA commands for transferring data.
1261 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd)
1263 int i, dma_cmd, total, off, dtot;
1264 struct scatterlist *scl;
1265 struct dbdma_cmd *dcmds;
1267 dma_cmd = ms->tgts[ms->conn_tgt].data_goes_out?
1268 OUTPUT_MORE: INPUT_MORE;
1269 dcmds = ms->dma_cmds;
1274 cmd->SCp.this_residual = scsi_bufflen(cmd);
1276 nseg = scsi_dma_map(cmd);
1283 scsi_for_each_sg(cmd, scl, nseg, i) {
1284 u32 dma_addr = sg_dma_address(scl);
1285 u32 dma_len = sg_dma_len(scl);
1287 total += scl->length;
1288 if (off >= dma_len) {
1292 if (dma_len > 0xffff)
1293 panic("mesh: scatterlist element >= 64k");
1294 dcmds->req_count = cpu_to_le16(dma_len - off);
1295 dcmds->command = cpu_to_le16(dma_cmd);
1296 dcmds->phy_addr = cpu_to_le32(dma_addr + off);
1297 dcmds->xfer_status = 0;
1299 dtot += dma_len - off;
1305 /* Either the target has overrun our buffer,
1306 or the caller didn't provide a buffer. */
1307 static char mesh_extra_buf[64];
1309 dtot = sizeof(mesh_extra_buf);
1310 dcmds->req_count = cpu_to_le16(dtot);
1311 dcmds->phy_addr = cpu_to_le32(virt_to_phys(mesh_extra_buf));
1312 dcmds->xfer_status = 0;
1315 dma_cmd += OUTPUT_LAST - OUTPUT_MORE;
1316 dcmds[-1].command = cpu_to_le16(dma_cmd);
1317 memset(dcmds, 0, sizeof(*dcmds));
1318 dcmds->command = cpu_to_le16(DBDMA_STOP);
1319 ms->dma_count = dtot;
1322 static void halt_dma(struct mesh_state *ms)
1324 volatile struct dbdma_regs __iomem *md = ms->dma;
1325 volatile struct mesh_regs __iomem *mr = ms->mesh;
1326 struct scsi_cmnd *cmd = ms->current_req;
1329 if (!ms->tgts[ms->conn_tgt].data_goes_out) {
1330 /* wait a little while until the fifo drains */
1332 while (t > 0 && in_8(&mr->fifo_count) != 0
1333 && (in_le32(&md->status) & ACTIVE) != 0) {
1338 out_le32(&md->control, RUN << 16); /* turn off RUN bit */
1339 nb = (mr->count_hi << 8) + mr->count_lo;
1340 dlog(ms, "halt_dma fc/count=%.6x",
1341 MKWORD(0, mr->fifo_count, 0, nb));
1342 if (ms->tgts[ms->conn_tgt].data_goes_out)
1343 nb += mr->fifo_count;
1344 /* nb is the number of bytes not yet transferred
1345 to/from the target. */
1347 dlog(ms, "data_ptr %x", ms->data_ptr);
1348 if (ms->data_ptr < 0) {
1349 printk(KERN_ERR "mesh: halt_dma: data_ptr=%d (nb=%d, ms=%p)\n",
1350 ms->data_ptr, nb, ms);
1353 dumplog(ms, ms->conn_tgt);
1355 #endif /* MESH_DBG */
1356 } else if (cmd && scsi_bufflen(cmd) &&
1357 ms->data_ptr > scsi_bufflen(cmd)) {
1358 printk(KERN_DEBUG "mesh: target %d overrun, "
1359 "data_ptr=%x total=%x goes_out=%d\n",
1360 ms->conn_tgt, ms->data_ptr, scsi_bufflen(cmd),
1361 ms->tgts[ms->conn_tgt].data_goes_out);
1364 scsi_dma_unmap(cmd);
1365 ms->dma_started = 0;
1368 static void phase_mismatch(struct mesh_state *ms)
1370 volatile struct mesh_regs __iomem *mr = ms->mesh;
1373 dlog(ms, "phasemm ch/cl/seq/fc=%.8x",
1374 MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count));
1375 phase = in_8(&mr->bus_status0) & BS0_PHASE;
1376 if (ms->msgphase == msg_out_xxx && phase == BP_MSGOUT) {
1377 /* output the last byte of the message, without ATN */
1378 out_8(&mr->count_lo, 1);
1379 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1382 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1383 ms->msgphase = msg_out_last;
1387 if (ms->msgphase == msg_in) {
1393 if (ms->dma_started)
1395 if (mr->fifo_count) {
1396 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1401 ms->msgphase = msg_none;
1404 ms->tgts[ms->conn_tgt].data_goes_out = 0;
1405 ms->phase = dataing;
1408 ms->tgts[ms->conn_tgt].data_goes_out = 1;
1409 ms->phase = dataing;
1412 ms->phase = commanding;
1415 ms->phase = statusing;
1418 ms->msgphase = msg_in;
1422 ms->msgphase = msg_out;
1423 if (ms->n_msgout == 0) {
1427 if (ms->last_n_msgout == 0) {
1429 "mesh: no msg to repeat\n");
1430 ms->msgout[0] = NOP;
1431 ms->last_n_msgout = 1;
1433 ms->n_msgout = ms->last_n_msgout;
1438 printk(KERN_DEBUG "mesh: unknown scsi phase %x\n", phase);
1439 ms->stat = DID_ERROR;
1447 static void cmd_complete(struct mesh_state *ms)
1449 volatile struct mesh_regs __iomem *mr = ms->mesh;
1450 struct scsi_cmnd *cmd = ms->current_req;
1451 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1454 dlog(ms, "cmd_complete fc=%x", mr->fifo_count);
1455 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
1456 switch (ms->msgphase) {
1458 /* huh? we expected a phase mismatch */
1460 ms->msgphase = msg_in;
1464 /* should have some message bytes in fifo */
1466 n = msgin_length(ms);
1467 if (ms->n_msgin < n) {
1468 out_8(&mr->count_lo, n - ms->n_msgin);
1469 out_8(&mr->sequence, SEQ_MSGIN + seq);
1471 ms->msgphase = msg_none;
1478 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1481 out_8(&mr->count_lo, 1);
1482 out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg);
1487 * To get the right timing on ATN wrt ACK, we have
1488 * to get the MESH to drop ACK, wait until REQ gets
1489 * asserted, then drop ATN. To do this we first
1490 * issue a SEQ_MSGOUT with ATN and wait for REQ,
1491 * then change the command to a SEQ_MSGOUT w/o ATN.
1492 * If we don't see REQ in a reasonable time, we
1493 * change the command to SEQ_MSGIN with ATN,
1494 * wait for the phase mismatch interrupt, then
1495 * issue the SEQ_MSGOUT without ATN.
1497 out_8(&mr->count_lo, 1);
1498 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN);
1499 t = 30; /* wait up to 30us */
1500 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0 && --t >= 0)
1502 dlog(ms, "last_mbyte err/exc/fc/cl=%.8x",
1503 MKWORD(mr->error, mr->exception,
1504 mr->fifo_count, mr->count_lo));
1505 if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) {
1506 /* whoops, target didn't do what we expected */
1507 ms->last_n_msgout = ms->n_msgout;
1509 if (in_8(&mr->interrupt) & INT_ERROR) {
1510 printk(KERN_ERR "mesh: error %x in msg_out\n",
1515 if (in_8(&mr->exception) != EXC_PHASEMM)
1516 printk(KERN_ERR "mesh: exc %x in msg_out\n",
1517 in_8(&mr->exception));
1519 printk(KERN_DEBUG "mesh: bs0=%x in msg_out\n",
1520 in_8(&mr->bus_status0));
1521 handle_exception(ms);
1524 if (in_8(&mr->bus_status0) & BS0_REQ) {
1525 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1528 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1529 ms->msgphase = msg_out_last;
1531 out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN);
1532 ms->msgphase = msg_out_xxx;
1537 ms->last_n_msgout = ms->n_msgout;
1539 ms->msgphase = ms->expect_reply? msg_in: msg_none;
1544 switch (ms->phase) {
1546 printk(KERN_ERR "mesh: interrupt in idle phase?\n");
1550 dlog(ms, "Selecting phase at command completion",0);
1551 ms->msgout[0] = IDENTIFY(ALLOW_RESEL(ms->conn_tgt),
1552 (cmd? cmd->device->lun: 0));
1554 ms->expect_reply = 0;
1556 ms->msgout[0] = ABORT;
1558 } else if (tp->sdtr_state == do_sdtr) {
1559 /* add SDTR message */
1561 ms->expect_reply = 1;
1562 tp->sdtr_state = sdtr_sent;
1564 ms->msgphase = msg_out;
1566 * We need to wait for REQ before dropping ATN.
1567 * We wait for at most 30us, then fall back to
1568 * a scheme where we issue a SEQ_COMMAND with ATN,
1569 * which will give us a phase mismatch interrupt
1570 * when REQ does come, and then we send the message.
1572 t = 230; /* wait up to 230us */
1573 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0) {
1575 dlog(ms, "impatient for req", ms->n_msgout);
1576 ms->msgphase = msg_none;
1583 if (ms->dma_count != 0) {
1588 * We can get a phase mismatch here if the target
1589 * changes to the status phase, even though we have
1590 * had a command complete interrupt. Then, if we
1591 * issue the SEQ_STATUS command, we'll get a sequence
1592 * error interrupt. Which isn't so bad except that
1593 * occasionally the mesh actually executes the
1594 * SEQ_STATUS *as well as* giving us the sequence
1595 * error and phase mismatch exception.
1597 out_8(&mr->sequence, 0);
1598 out_8(&mr->interrupt,
1599 INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1604 cmd->SCp.Status = mr->fifo;
1605 if (DEBUG_TARGET(cmd))
1606 printk(KERN_DEBUG "mesh: status is %x\n",
1609 ms->msgphase = msg_in;
1615 ms->current_req = NULL;
1630 * Called by midlayer with host locked to queue a new
1633 static int mesh_queue_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
1635 struct mesh_state *ms;
1637 cmd->scsi_done = done;
1638 cmd->host_scribble = NULL;
1640 ms = (struct mesh_state *) cmd->device->host->hostdata;
1642 if (ms->request_q == NULL)
1643 ms->request_q = cmd;
1645 ms->request_qtail->host_scribble = (void *) cmd;
1646 ms->request_qtail = cmd;
1648 if (ms->phase == idle)
1654 static DEF_SCSI_QCMD(mesh_queue)
1657 * Called to handle interrupts, either call by the interrupt
1658 * handler (do_mesh_interrupt) or by other functions in
1659 * exceptional circumstances
1661 static void mesh_interrupt(struct mesh_state *ms)
1663 volatile struct mesh_regs __iomem *mr = ms->mesh;
1667 if (ALLOW_DEBUG(ms->conn_tgt))
1668 printk(KERN_DEBUG "mesh_intr, bs0=%x int=%x exc=%x err=%x "
1669 "phase=%d msgphase=%d\n", mr->bus_status0,
1670 mr->interrupt, mr->exception, mr->error,
1671 ms->phase, ms->msgphase);
1673 while ((intr = in_8(&mr->interrupt)) != 0) {
1674 dlog(ms, "interrupt intr/err/exc/seq=%.8x",
1675 MKWORD(intr, mr->error, mr->exception, mr->sequence));
1676 if (intr & INT_ERROR) {
1678 } else if (intr & INT_EXCEPTION) {
1679 handle_exception(ms);
1680 } else if (intr & INT_CMDDONE) {
1681 out_8(&mr->interrupt, INT_CMDDONE);
1687 /* Todo: here we can at least try to remove the command from the
1688 * queue if it isn't connected yet, and for pending command, assert
1689 * ATN until the bus gets freed.
1691 static int mesh_abort(struct scsi_cmnd *cmd)
1693 struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata;
1695 printk(KERN_DEBUG "mesh_abort(%p)\n", cmd);
1697 dumplog(ms, cmd->device->id);
1703 * Called by the midlayer with the lock held to reset the
1704 * SCSI host and bus.
1705 * The midlayer will wait for devices to come back, we don't need
1706 * to do that ourselves
1708 static int mesh_host_reset(struct scsi_cmnd *cmd)
1710 struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata;
1711 volatile struct mesh_regs __iomem *mr = ms->mesh;
1712 volatile struct dbdma_regs __iomem *md = ms->dma;
1713 unsigned long flags;
1715 printk(KERN_DEBUG "mesh_host_reset\n");
1717 spin_lock_irqsave(ms->host->host_lock, flags);
1719 if (ms->dma_started)
1722 /* Reset the controller & dbdma channel */
1723 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */
1724 out_8(&mr->exception, 0xff); /* clear all exception bits */
1725 out_8(&mr->error, 0xff); /* clear all error bits */
1726 out_8(&mr->sequence, SEQ_RESETMESH);
1729 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1730 out_8(&mr->source_id, ms->host->this_id);
1731 out_8(&mr->sel_timeout, 25); /* 250ms */
1732 out_8(&mr->sync_params, ASYNC_PARAMS);
1735 out_8(&mr->bus_status1, BS1_RST); /* assert RST */
1737 udelay(30); /* leave it on for >= 25us */
1738 out_8(&mr->bus_status1, 0); /* negate RST */
1740 /* Complete pending commands */
1743 spin_unlock_irqrestore(ms->host->host_lock, flags);
1747 static void set_mesh_power(struct mesh_state *ms, int state)
1749 if (!machine_is(powermac))
1752 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 1);
1755 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 0);
1762 static int mesh_suspend(struct macio_dev *mdev, pm_message_t mesg)
1764 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1765 unsigned long flags;
1767 switch (mesg.event) {
1768 case PM_EVENT_SUSPEND:
1769 case PM_EVENT_HIBERNATE:
1770 case PM_EVENT_FREEZE:
1775 if (ms->phase == sleeping)
1778 scsi_block_requests(ms->host);
1779 spin_lock_irqsave(ms->host->host_lock, flags);
1780 while(ms->phase != idle) {
1781 spin_unlock_irqrestore(ms->host->host_lock, flags);
1783 spin_lock_irqsave(ms->host->host_lock, flags);
1785 ms->phase = sleeping;
1786 spin_unlock_irqrestore(ms->host->host_lock, flags);
1787 disable_irq(ms->meshintr);
1788 set_mesh_power(ms, 0);
1793 static int mesh_resume(struct macio_dev *mdev)
1795 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1796 unsigned long flags;
1798 if (ms->phase != sleeping)
1801 set_mesh_power(ms, 1);
1803 spin_lock_irqsave(ms->host->host_lock, flags);
1805 spin_unlock_irqrestore(ms->host->host_lock, flags);
1806 enable_irq(ms->meshintr);
1807 scsi_unblock_requests(ms->host);
1812 #endif /* CONFIG_PM */
1815 * If we leave drives set for synchronous transfers (especially
1816 * CDROMs), and reboot to MacOS, it gets confused, poor thing.
1817 * So, on reboot we reset the SCSI bus.
1819 static int mesh_shutdown(struct macio_dev *mdev)
1821 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1822 volatile struct mesh_regs __iomem *mr;
1823 unsigned long flags;
1825 printk(KERN_INFO "resetting MESH scsi bus(es)\n");
1826 spin_lock_irqsave(ms->host->host_lock, flags);
1828 out_8(&mr->intr_mask, 0);
1829 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1830 out_8(&mr->bus_status1, BS1_RST);
1833 out_8(&mr->bus_status1, 0);
1834 spin_unlock_irqrestore(ms->host->host_lock, flags);
1839 static struct scsi_host_template mesh_template = {
1840 .proc_name = "mesh",
1842 .queuecommand = mesh_queue,
1843 .eh_abort_handler = mesh_abort,
1844 .eh_host_reset_handler = mesh_host_reset,
1847 .sg_tablesize = SG_ALL,
1849 .max_segment_size = 65535,
1852 static int mesh_probe(struct macio_dev *mdev, const struct of_device_id *match)
1854 struct device_node *mesh = macio_get_of_node(mdev);
1855 struct pci_dev* pdev = macio_get_pci_dev(mdev);
1858 struct mesh_state *ms;
1859 struct Scsi_Host *mesh_host;
1860 void *dma_cmd_space;
1861 dma_addr_t dma_cmd_bus;
1863 switch (mdev->bus->chip->type) {
1864 case macio_heathrow:
1866 case macio_paddington:
1870 use_active_neg = SEQ_ACTIVE_NEG;
1873 if (macio_resource_count(mdev) != 2 || macio_irq_count(mdev) != 2) {
1874 printk(KERN_ERR "mesh: expected 2 addrs and 2 intrs"
1875 " (got %d,%d)\n", macio_resource_count(mdev),
1876 macio_irq_count(mdev));
1880 if (macio_request_resources(mdev, "mesh") != 0) {
1881 printk(KERN_ERR "mesh: unable to request memory resources");
1884 mesh_host = scsi_host_alloc(&mesh_template, sizeof(struct mesh_state));
1885 if (mesh_host == NULL) {
1886 printk(KERN_ERR "mesh: couldn't register host");
1890 /* Old junk for root discovery, that will die ultimately */
1891 #if !defined(MODULE)
1892 note_scsi_host(mesh, mesh_host);
1895 mesh_host->base = macio_resource_start(mdev, 0);
1896 mesh_host->irq = macio_irq(mdev, 0);
1897 ms = (struct mesh_state *) mesh_host->hostdata;
1898 macio_set_drvdata(mdev, ms);
1899 ms->host = mesh_host;
1903 ms->mesh = ioremap(macio_resource_start(mdev, 0), 0x1000);
1904 if (ms->mesh == NULL) {
1905 printk(KERN_ERR "mesh: can't map registers\n");
1908 ms->dma = ioremap(macio_resource_start(mdev, 1), 0x1000);
1909 if (ms->dma == NULL) {
1910 printk(KERN_ERR "mesh: can't map registers\n");
1915 ms->meshintr = macio_irq(mdev, 0);
1916 ms->dmaintr = macio_irq(mdev, 1);
1918 /* Space for dma command list: +1 for stop command,
1919 * +1 to allow for aligning.
1921 ms->dma_cmd_size = (mesh_host->sg_tablesize + 2) * sizeof(struct dbdma_cmd);
1923 /* We use the PCI APIs for now until the generic one gets fixed
1924 * enough or until we get some macio-specific versions
1926 dma_cmd_space = dma_alloc_coherent(&macio_get_pci_dev(mdev)->dev,
1927 ms->dma_cmd_size, &dma_cmd_bus,
1929 if (dma_cmd_space == NULL) {
1930 printk(KERN_ERR "mesh: can't allocate DMA table\n");
1934 ms->dma_cmds = (struct dbdma_cmd *) DBDMA_ALIGN(dma_cmd_space);
1935 ms->dma_cmd_space = dma_cmd_space;
1936 ms->dma_cmd_bus = dma_cmd_bus + ((unsigned long)ms->dma_cmds)
1937 - (unsigned long)dma_cmd_space;
1938 ms->current_req = NULL;
1939 for (tgt = 0; tgt < 8; ++tgt) {
1940 ms->tgts[tgt].sdtr_state = do_sdtr;
1941 ms->tgts[tgt].sync_params = ASYNC_PARAMS;
1942 ms->tgts[tgt].current_req = NULL;
1945 if ((cfp = of_get_property(mesh, "clock-frequency", NULL)))
1946 ms->clk_freq = *cfp;
1948 printk(KERN_INFO "mesh: assuming 50MHz clock frequency\n");
1949 ms->clk_freq = 50000000;
1952 /* The maximum sync rate is clock / 5; increase
1953 * mesh_sync_period if necessary.
1955 minper = 1000000000 / (ms->clk_freq / 5); /* ns */
1956 if (mesh_sync_period < minper)
1957 mesh_sync_period = minper;
1959 /* Power up the chip */
1960 set_mesh_power(ms, 1);
1965 /* Request interrupt */
1966 if (request_irq(ms->meshintr, do_mesh_interrupt, 0, "MESH", ms)) {
1967 printk(KERN_ERR "MESH: can't get irq %d\n", ms->meshintr);
1971 /* Add scsi host & scan */
1972 if (scsi_add_host(mesh_host, &mdev->ofdev.dev))
1973 goto out_release_irq;
1974 scsi_scan_host(mesh_host);
1979 free_irq(ms->meshintr, ms);
1981 /* shutdown & reset bus in case of error or macos can be confused
1982 * at reboot if the bus was set to synchronous mode already
1984 mesh_shutdown(mdev);
1985 set_mesh_power(ms, 0);
1986 dma_free_coherent(&macio_get_pci_dev(mdev)->dev, ms->dma_cmd_size,
1987 ms->dma_cmd_space, ms->dma_cmd_bus);
1992 scsi_host_put(mesh_host);
1994 macio_release_resources(mdev);
1999 static int mesh_remove(struct macio_dev *mdev)
2001 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
2002 struct Scsi_Host *mesh_host = ms->host;
2004 scsi_remove_host(mesh_host);
2006 free_irq(ms->meshintr, ms);
2008 /* Reset scsi bus */
2009 mesh_shutdown(mdev);
2011 /* Shut down chip & termination */
2012 set_mesh_power(ms, 0);
2014 /* Unmap registers & dma controller */
2018 /* Free DMA commands memory */
2019 dma_free_coherent(&macio_get_pci_dev(mdev)->dev, ms->dma_cmd_size,
2020 ms->dma_cmd_space, ms->dma_cmd_bus);
2022 /* Release memory resources */
2023 macio_release_resources(mdev);
2025 scsi_host_put(mesh_host);
2031 static struct of_device_id mesh_match[] =
2038 .compatible = "chrp,mesh0"
2042 MODULE_DEVICE_TABLE (of, mesh_match);
2044 static struct macio_driver mesh_driver =
2048 .owner = THIS_MODULE,
2049 .of_match_table = mesh_match,
2051 .probe = mesh_probe,
2052 .remove = mesh_remove,
2053 .shutdown = mesh_shutdown,
2055 .suspend = mesh_suspend,
2056 .resume = mesh_resume,
2061 static int __init init_mesh(void)
2064 /* Calculate sync rate from module parameters */
2067 if (sync_rate > 0) {
2068 printk(KERN_INFO "mesh: configured for synchronous %d MB/s\n", sync_rate);
2069 mesh_sync_period = 1000 / sync_rate; /* ns */
2070 mesh_sync_offset = 15;
2072 printk(KERN_INFO "mesh: configured for asynchronous\n");
2074 return macio_register_driver(&mesh_driver);
2077 static void __exit exit_mesh(void)
2079 return macio_unregister_driver(&mesh_driver);
2082 module_init(init_mesh);
2083 module_exit(exit_mesh);