2 * ipr.h -- driver for IBM Power Linux RAID adapters
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
6 * Copyright (C) 2003, 2004 IBM Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
29 #include <asm/unaligned.h>
30 #include <linux/types.h>
31 #include <linux/completion.h>
32 #include <linux/libata.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <scsi/scsi.h>
36 #include <scsi/scsi_cmnd.h>
41 #define IPR_DRIVER_VERSION "2.5.4"
42 #define IPR_DRIVER_DATE "(July 11, 2012)"
45 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
46 * ops per device for devices not running tagged command queuing.
47 * This can be adjusted at runtime through sysfs device attributes.
49 #define IPR_MAX_CMD_PER_LUN 6
50 #define IPR_MAX_CMD_PER_ATA_LUN 1
53 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
54 * ops the mid-layer can send to the adapter.
56 #define IPR_NUM_BASE_CMD_BLKS (ioa_cfg->max_cmds)
58 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
60 #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
61 #define PCI_DEVICE_ID_IBM_CROCODILE 0x034A
63 #define IPR_SUBS_DEV_ID_2780 0x0264
64 #define IPR_SUBS_DEV_ID_5702 0x0266
65 #define IPR_SUBS_DEV_ID_5703 0x0278
66 #define IPR_SUBS_DEV_ID_572E 0x028D
67 #define IPR_SUBS_DEV_ID_573E 0x02D3
68 #define IPR_SUBS_DEV_ID_573D 0x02D4
69 #define IPR_SUBS_DEV_ID_571A 0x02C0
70 #define IPR_SUBS_DEV_ID_571B 0x02BE
71 #define IPR_SUBS_DEV_ID_571E 0x02BF
72 #define IPR_SUBS_DEV_ID_571F 0x02D5
73 #define IPR_SUBS_DEV_ID_572A 0x02C1
74 #define IPR_SUBS_DEV_ID_572B 0x02C2
75 #define IPR_SUBS_DEV_ID_572F 0x02C3
76 #define IPR_SUBS_DEV_ID_574E 0x030A
77 #define IPR_SUBS_DEV_ID_575B 0x030D
78 #define IPR_SUBS_DEV_ID_575C 0x0338
79 #define IPR_SUBS_DEV_ID_57B3 0x033A
80 #define IPR_SUBS_DEV_ID_57B7 0x0360
81 #define IPR_SUBS_DEV_ID_57B8 0x02C2
83 #define IPR_SUBS_DEV_ID_57B4 0x033B
84 #define IPR_SUBS_DEV_ID_57B2 0x035F
85 #define IPR_SUBS_DEV_ID_57C0 0x0352
86 #define IPR_SUBS_DEV_ID_57C3 0x0353
87 #define IPR_SUBS_DEV_ID_57C4 0x0354
88 #define IPR_SUBS_DEV_ID_57C6 0x0357
89 #define IPR_SUBS_DEV_ID_57CC 0x035C
91 #define IPR_SUBS_DEV_ID_57B5 0x033C
92 #define IPR_SUBS_DEV_ID_57CE 0x035E
93 #define IPR_SUBS_DEV_ID_57B1 0x0355
95 #define IPR_SUBS_DEV_ID_574D 0x0356
96 #define IPR_SUBS_DEV_ID_57C8 0x035D
98 #define IPR_SUBS_DEV_ID_57D5 0x03FB
99 #define IPR_SUBS_DEV_ID_57D6 0x03FC
100 #define IPR_SUBS_DEV_ID_57D7 0x03FF
101 #define IPR_SUBS_DEV_ID_57D8 0x03FE
102 #define IPR_NAME "ipr"
107 #define IPR_RC_JOB_CONTINUE 1
108 #define IPR_RC_JOB_RETURN 2
113 #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
114 #define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
115 #define IPR_IOASC_SYNC_REQUIRED 0x023f0000
116 #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
117 #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
118 #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
119 #define IPR_IOASC_IOASC_MASK 0xFFFFFF00
120 #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
121 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
122 #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
123 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
124 #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
125 #define IPR_IOASC_BUS_WAS_RESET 0x06290000
126 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
127 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
129 #define IPR_FIRST_DRIVER_IOASC 0x10000000
130 #define IPR_IOASC_IOA_WAS_RESET 0x10000001
131 #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
133 /* Driver data flags */
134 #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
135 #define IPR_USE_PCI_WARM_RESET 0x00000002
137 #define IPR_DEFAULT_MAX_ERROR_DUMP 984
138 #define IPR_NUM_LOG_HCAMS 2
139 #define IPR_NUM_CFG_CHG_HCAMS 2
140 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
142 #define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
143 #define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
145 #define IPR_MAX_NUM_TARGETS_PER_BUS 256
146 #define IPR_MAX_NUM_LUNS_PER_TARGET 256
147 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
148 #define IPR_VSET_BUS 0xff
149 #define IPR_IOA_BUS 0xff
150 #define IPR_IOA_TARGET 0xff
151 #define IPR_IOA_LUN 0xff
152 #define IPR_MAX_NUM_BUSES 16
153 #define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
155 #define IPR_NUM_RESET_RELOAD_RETRIES 3
157 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
158 #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
159 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
161 #define IPR_MAX_COMMANDS 100
162 #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
163 IPR_NUM_INTERNAL_CMD_BLKS)
165 #define IPR_MAX_PHYSICAL_DEVS 192
166 #define IPR_DEFAULT_SIS64_DEVS 1024
167 #define IPR_MAX_SIS64_DEVS 4096
169 #define IPR_MAX_SGLIST 64
170 #define IPR_IOA_MAX_SECTORS 32767
171 #define IPR_VSET_MAX_SECTORS 512
172 #define IPR_MAX_CDB_LEN 16
173 #define IPR_MAX_HRRQ_RETRIES 3
175 #define IPR_DEFAULT_BUS_WIDTH 16
176 #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
177 #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
178 #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
179 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
181 #define IPR_IOA_RES_HANDLE 0xffffffff
182 #define IPR_INVALID_RES_HANDLE 0
183 #define IPR_IOA_RES_ADDR 0x00ffffff
188 #define IPR_QUERY_RSRC_STATE 0xC2
189 #define IPR_RESET_DEVICE 0xC3
190 #define IPR_RESET_TYPE_SELECT 0x80
191 #define IPR_LUN_RESET 0x40
192 #define IPR_TARGET_RESET 0x20
193 #define IPR_BUS_RESET 0x10
194 #define IPR_ATA_PHY_RESET 0x80
195 #define IPR_ID_HOST_RR_Q 0xC4
196 #define IPR_QUERY_IOA_CONFIG 0xC5
197 #define IPR_CANCEL_ALL_REQUESTS 0xCE
198 #define IPR_HOST_CONTROLLED_ASYNC 0xCF
199 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
200 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
201 #define IPR_SET_SUPPORTED_DEVICES 0xFB
202 #define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
203 #define IPR_IOA_SHUTDOWN 0xF7
204 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
209 #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
210 #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
211 #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
212 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
213 #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
214 #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
215 #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
216 #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
217 #define IPR_WRITE_BUFFER_TIMEOUT (30 * 60 * HZ)
218 #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
219 #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
220 #define IPR_OPERATIONAL_TIMEOUT (5 * 60)
221 #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
222 #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
223 #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
224 #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
225 #define IPR_PCI_RESET_TIMEOUT (HZ / 2)
226 #define IPR_SIS32_DUMP_TIMEOUT (15 * HZ)
227 #define IPR_SIS64_DUMP_TIMEOUT (40 * HZ)
228 #define IPR_DUMP_DELAY_SECONDS 4
229 #define IPR_DUMP_DELAY_TIMEOUT (IPR_DUMP_DELAY_SECONDS * HZ)
234 #define IPR_VENDOR_ID_LEN 8
235 #define IPR_PROD_ID_LEN 16
236 #define IPR_SERIAL_NUM_LEN 8
241 #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
242 #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
243 #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
244 #define IPR_GET_FMT2_BAR_SEL(mbx) \
245 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
246 #define IPR_SDT_FMT2_BAR0_SEL 0x0
247 #define IPR_SDT_FMT2_BAR1_SEL 0x1
248 #define IPR_SDT_FMT2_BAR2_SEL 0x2
249 #define IPR_SDT_FMT2_BAR3_SEL 0x3
250 #define IPR_SDT_FMT2_BAR4_SEL 0x4
251 #define IPR_SDT_FMT2_BAR5_SEL 0x5
252 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
253 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
254 #define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
255 #define IPR_DOORBELL 0x82800000
256 #define IPR_RUNTIME_RESET 0x40000000
258 #define IPR_IPL_INIT_MIN_STAGE_TIME 5
259 #define IPR_IPL_INIT_DEFAULT_STAGE_TIME 15
260 #define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
261 #define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
262 #define IPR_IPL_INIT_STAGE_MASK 0xff000000
263 #define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
264 #define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
266 #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
267 #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
268 #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
269 #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
270 #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
271 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
272 #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
273 #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
274 #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
275 #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
276 #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
278 #define IPR_PCII_ERROR_INTERRUPTS \
279 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
280 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
282 #define IPR_PCII_OPER_INTERRUPTS \
283 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
285 #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
286 #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
287 #define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23)
289 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
290 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
295 #define IPR_FMT2_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
296 #define IPR_FMT3_MAX_IOA_DUMP_SIZE (32 * 1024 * 1024)
297 #define IPR_FMT2_NUM_SDT_ENTRIES 511
298 #define IPR_FMT3_NUM_SDT_ENTRIES 0xFFF
299 #define IPR_FMT2_MAX_NUM_DUMP_PAGES ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
300 #define IPR_FMT3_MAX_NUM_DUMP_PAGES ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
305 #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
306 #define IPR_MAX_MSIX_VECTORS 0x5
307 #define IPR_MAX_HRRQ_NUM 0x10
308 #define IPR_INIT_HRRQ 0x0
311 * Adapter interface types
314 struct ipr_res_addr {
319 #define IPR_GET_PHYS_LOC(res_addr) \
320 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
321 }__attribute__((packed, aligned (4)));
323 struct ipr_std_inq_vpids {
324 u8 vendor_id[IPR_VENDOR_ID_LEN];
325 u8 product_id[IPR_PROD_ID_LEN];
326 }__attribute__((packed));
329 struct ipr_std_inq_vpids vpids;
330 u8 sn[IPR_SERIAL_NUM_LEN];
331 }__attribute__((packed));
336 }__attribute__((packed));
338 struct ipr_ext_vpd64 {
341 }__attribute__((packed));
343 struct ipr_std_inq_data {
344 u8 peri_qual_dev_type;
345 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
346 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
348 u8 removeable_medium_rsvd;
349 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
351 #define IPR_IS_DASD_DEVICE(std_inq) \
352 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
353 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
355 #define IPR_IS_SES_DEVICE(std_inq) \
356 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
365 struct ipr_std_inq_vpids vpids;
367 u8 ros_rsvd_ram_rsvd[4];
369 u8 serial_num[IPR_SERIAL_NUM_LEN];
370 }__attribute__ ((packed));
372 #define IPR_RES_TYPE_AF_DASD 0x00
373 #define IPR_RES_TYPE_GENERIC_SCSI 0x01
374 #define IPR_RES_TYPE_VOLUME_SET 0x02
375 #define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
376 #define IPR_RES_TYPE_GENERIC_ATA 0x04
377 #define IPR_RES_TYPE_ARRAY 0x05
378 #define IPR_RES_TYPE_IOAFP 0xff
380 struct ipr_config_table_entry {
382 #define IPR_PROTO_SATA 0x02
383 #define IPR_PROTO_SATA_ATAPI 0x03
384 #define IPR_PROTO_SAS_STP 0x06
385 #define IPR_PROTO_SAS_STP_ATAPI 0x07
388 #define IPR_IS_IOA_RESOURCE 0x80
391 #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
392 #define IPR_QUEUE_FROZEN_MODEL 0
393 #define IPR_QUEUE_NACA_MODEL 1
395 struct ipr_res_addr res_addr;
398 struct ipr_std_inq_data std_inq_data;
399 }__attribute__ ((packed, aligned (4)));
401 struct ipr_config_table_entry64 {
408 #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
415 #define IPR_MAX_RES_PATH_LENGTH 48
417 struct ipr_std_inq_data std_inq_data;
421 }__attribute__ ((packed, aligned (8)));
423 struct ipr_config_table_hdr {
426 #define IPR_UCODE_DOWNLOAD_REQ 0x10
428 }__attribute__((packed, aligned (4)));
430 struct ipr_config_table_hdr64 {
435 }__attribute__((packed, aligned (4)));
437 struct ipr_config_table {
438 struct ipr_config_table_hdr hdr;
439 struct ipr_config_table_entry dev[0];
440 }__attribute__((packed, aligned (4)));
442 struct ipr_config_table64 {
443 struct ipr_config_table_hdr64 hdr64;
444 struct ipr_config_table_entry64 dev[0];
445 }__attribute__((packed, aligned (8)));
447 struct ipr_config_table_entry_wrapper {
449 struct ipr_config_table_entry *cfgte;
450 struct ipr_config_table_entry64 *cfgte64;
454 struct ipr_hostrcb_cfg_ch_not {
456 struct ipr_config_table_entry cfgte;
457 struct ipr_config_table_entry64 cfgte64;
460 }__attribute__((packed, aligned (4)));
462 struct ipr_supported_device {
466 struct ipr_std_inq_vpids vpids;
468 }__attribute__((packed, aligned (4)));
470 struct ipr_hrr_queue {
471 struct ipr_ioa_cfg *ioa_cfg;
473 dma_addr_t host_rrq_dma;
474 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
475 #define IPR_HRRQ_RESP_BIT_SET 0x00000002
476 #define IPR_HRRQ_TOGGLE_BIT 0x00000001
477 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
478 #define IPR_ID_HRRQ_SELE_ENABLE 0x02
479 volatile __be32 *hrrq_start;
480 volatile __be32 *hrrq_end;
481 volatile __be32 *hrrq_curr;
483 struct list_head hrrq_free_q;
484 struct list_head hrrq_pending_q;
488 volatile u32 toggle_bit;
492 u8 allow_interrupts:1;
497 /* Command packet structure */
499 u8 reserved; /* Reserved by IOA */
502 #define IPR_RQTYPE_SCSICDB 0x00
503 #define IPR_RQTYPE_IOACMD 0x01
504 #define IPR_RQTYPE_HCAM 0x02
505 #define IPR_RQTYPE_ATA_PASSTHRU 0x04
510 #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
511 #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
512 #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
513 #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
514 #define IPR_FLAGS_HI_NO_LINK_DESC 0x04
517 #define IPR_FLAGS_LO_ALIGNED_BFR 0x20
518 #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
519 #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
520 #define IPR_FLAGS_LO_SIMPLE_TASK 0x02
521 #define IPR_FLAGS_LO_ORDERED_TASK 0x04
522 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
523 #define IPR_FLAGS_LO_ACA_TASK 0x08
527 }__attribute__ ((packed, aligned(4)));
529 struct ipr_ioarcb_ata_regs { /* 22 bytes */
531 #define IPR_ATA_FLAG_PACKET_CMD 0x80
532 #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
533 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
551 }__attribute__ ((packed, aligned(4)));
553 struct ipr_ioadl_desc {
554 __be32 flags_and_data_len;
555 #define IPR_IOADL_FLAGS_MASK 0xff000000
556 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
557 #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
558 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
559 #define IPR_IOADL_FLAGS_READ 0x48000000
560 #define IPR_IOADL_FLAGS_READ_LAST 0x49000000
561 #define IPR_IOADL_FLAGS_WRITE 0x68000000
562 #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
563 #define IPR_IOADL_FLAGS_LAST 0x01000000
566 }__attribute__((packed, aligned (8)));
568 struct ipr_ioadl64_desc {
572 }__attribute__((packed, aligned (16)));
574 struct ipr_ata64_ioadl {
575 struct ipr_ioarcb_ata_regs regs;
577 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
578 }__attribute__((packed, aligned (16)));
580 struct ipr_ioarcb_add_data {
582 struct ipr_ioarcb_ata_regs regs;
583 struct ipr_ioadl_desc ioadl[5];
584 __be32 add_cmd_parms[10];
586 }__attribute__ ((packed, aligned (4)));
588 struct ipr_ioarcb_sis64_add_addr_ecb {
589 __be64 ioasa_host_pci_addr;
590 __be64 data_ioadl_addr;
592 __be32 ext_control_buf[4];
593 }__attribute__((packed, aligned (8)));
595 /* IOA Request Control Block 128 bytes */
598 __be32 ioarcb_host_pci_addr;
599 __be64 ioarcb_host_pci_addr64;
602 __be32 host_response_handle;
607 __be32 data_transfer_length;
608 __be32 read_data_transfer_length;
609 __be32 write_ioadl_addr;
611 __be32 read_ioadl_addr;
612 __be32 read_ioadl_len;
614 __be32 ioasa_host_pci_addr;
618 struct ipr_cmd_pkt cmd_pkt;
620 __be16 add_cmd_parms_offset;
621 __be16 add_cmd_parms_len;
624 struct ipr_ioarcb_add_data add_data;
625 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
628 }__attribute__((packed, aligned (4)));
630 struct ipr_ioasa_vset {
631 __be32 failing_lba_hi;
632 __be32 failing_lba_lo;
634 }__attribute__((packed, aligned (4)));
636 struct ipr_ioasa_af_dasd {
639 }__attribute__((packed, aligned (4)));
641 struct ipr_ioasa_gpdd {
646 }__attribute__((packed, aligned (4)));
648 struct ipr_ioasa_gata {
650 u8 nsect; /* Interrupt reason */
656 u8 alt_status; /* ATA CTL */
661 }__attribute__((packed, aligned (4)));
663 struct ipr_auto_sense {
664 __be16 auto_sense_len;
666 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
669 struct ipr_ioasa_hdr {
671 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
672 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
673 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
674 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
676 __be16 ret_stat_len; /* Length of the returned IOASA */
678 __be16 avail_stat_len; /* Total Length of status available. */
680 __be32 residual_data_len; /* number of bytes in the host data */
681 /* buffers that were not used by the IOARCB command. */
684 #define IPR_NO_ILID 0
685 #define IPR_DRIVER_ILID 0xffffffff
689 __be32 fd_phys_locator;
691 __be32 fd_res_handle;
693 __be32 ioasc_specific; /* status code specific field */
694 #define IPR_ADDITIONAL_STATUS_FMT 0x80000000
695 #define IPR_AUTOSENSE_VALID 0x40000000
696 #define IPR_ATA_DEVICE_WAS_RESET 0x20000000
697 #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
698 #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
699 #define IPR_FIELD_POINTER_MASK 0x0000ffff
701 }__attribute__((packed, aligned (4)));
704 struct ipr_ioasa_hdr hdr;
707 struct ipr_ioasa_vset vset;
708 struct ipr_ioasa_af_dasd dasd;
709 struct ipr_ioasa_gpdd gpdd;
710 struct ipr_ioasa_gata gata;
713 struct ipr_auto_sense auto_sense;
714 }__attribute__((packed, aligned (4)));
717 struct ipr_ioasa_hdr hdr;
721 struct ipr_ioasa_vset vset;
722 struct ipr_ioasa_af_dasd dasd;
723 struct ipr_ioasa_gpdd gpdd;
724 struct ipr_ioasa_gata gata;
727 struct ipr_auto_sense auto_sense;
728 }__attribute__((packed, aligned (4)));
730 struct ipr_mode_parm_hdr {
733 u8 device_spec_parms;
735 }__attribute__((packed));
737 struct ipr_mode_pages {
738 struct ipr_mode_parm_hdr hdr;
739 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
740 }__attribute__((packed));
742 struct ipr_mode_page_hdr {
744 #define IPR_MODE_PAGE_PS 0x80
745 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
747 }__attribute__ ((packed));
749 struct ipr_dev_bus_entry {
750 struct ipr_res_addr res_addr;
752 #define IPR_SCSI_ATTR_ENABLE_QAS 0x80
753 #define IPR_SCSI_ATTR_DISABLE_QAS 0x40
754 #define IPR_SCSI_ATTR_QAS_MASK 0xC0
755 #define IPR_SCSI_ATTR_ENABLE_TM 0x20
756 #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
757 #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
758 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
762 u8 extended_reset_delay;
763 #define IPR_EXTENDED_RESET_DELAY 7
765 __be32 max_xfer_rate;
770 }__attribute__((packed, aligned (4)));
772 struct ipr_mode_page28 {
773 struct ipr_mode_page_hdr hdr;
776 struct ipr_dev_bus_entry bus[0];
777 }__attribute__((packed));
779 struct ipr_mode_page24 {
780 struct ipr_mode_page_hdr hdr;
782 #define IPR_ENABLE_DUAL_IOA_AF 0x80
783 }__attribute__((packed));
786 struct ipr_std_inq_data std_inq_data;
787 u8 ascii_part_num[12];
789 u8 ascii_plant_code[4];
790 }__attribute__((packed));
792 struct ipr_inquiry_page3 {
793 u8 peri_qual_dev_type;
805 }__attribute__((packed));
807 struct ipr_inquiry_cap {
808 u8 peri_qual_dev_type;
816 #define IPR_CAP_DUAL_IOA_RAID 0x80
818 }__attribute__((packed));
820 #define IPR_INQUIRY_PAGE0_ENTRIES 20
821 struct ipr_inquiry_page0 {
822 u8 peri_qual_dev_type;
826 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
827 }__attribute__((packed));
829 struct ipr_hostrcb_device_data_entry {
831 struct ipr_res_addr dev_res_addr;
832 struct ipr_vpd new_vpd;
833 struct ipr_vpd ioa_last_with_dev_vpd;
834 struct ipr_vpd cfc_last_with_dev_vpd;
836 }__attribute__((packed, aligned (4)));
838 struct ipr_hostrcb_device_data_entry_enhanced {
839 struct ipr_ext_vpd vpd;
841 struct ipr_res_addr dev_res_addr;
842 struct ipr_ext_vpd new_vpd;
844 struct ipr_ext_vpd ioa_last_with_dev_vpd;
845 struct ipr_ext_vpd cfc_last_with_dev_vpd;
846 }__attribute__((packed, aligned (4)));
848 struct ipr_hostrcb64_device_data_entry_enhanced {
849 struct ipr_ext_vpd vpd;
852 struct ipr_ext_vpd new_vpd;
854 struct ipr_ext_vpd ioa_last_with_dev_vpd;
855 struct ipr_ext_vpd cfc_last_with_dev_vpd;
856 }__attribute__((packed, aligned (4)));
858 struct ipr_hostrcb_array_data_entry {
860 struct ipr_res_addr expected_dev_res_addr;
861 struct ipr_res_addr dev_res_addr;
862 }__attribute__((packed, aligned (4)));
864 struct ipr_hostrcb64_array_data_entry {
865 struct ipr_ext_vpd vpd;
867 u8 expected_res_path[8];
869 }__attribute__((packed, aligned (4)));
871 struct ipr_hostrcb_array_data_entry_enhanced {
872 struct ipr_ext_vpd vpd;
874 struct ipr_res_addr expected_dev_res_addr;
875 struct ipr_res_addr dev_res_addr;
876 }__attribute__((packed, aligned (4)));
878 struct ipr_hostrcb_type_ff_error {
879 __be32 ioa_data[758];
880 }__attribute__((packed, aligned (4)));
882 struct ipr_hostrcb_type_01_error {
886 __be32 ioa_data[236];
887 }__attribute__((packed, aligned (4)));
889 struct ipr_hostrcb_type_02_error {
890 struct ipr_vpd ioa_vpd;
891 struct ipr_vpd cfc_vpd;
892 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
893 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
895 }__attribute__((packed, aligned (4)));
897 struct ipr_hostrcb_type_12_error {
898 struct ipr_ext_vpd ioa_vpd;
899 struct ipr_ext_vpd cfc_vpd;
900 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
901 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
903 }__attribute__((packed, aligned (4)));
905 struct ipr_hostrcb_type_03_error {
906 struct ipr_vpd ioa_vpd;
907 struct ipr_vpd cfc_vpd;
908 __be32 errors_detected;
909 __be32 errors_logged;
911 struct ipr_hostrcb_device_data_entry dev[3];
912 }__attribute__((packed, aligned (4)));
914 struct ipr_hostrcb_type_13_error {
915 struct ipr_ext_vpd ioa_vpd;
916 struct ipr_ext_vpd cfc_vpd;
917 __be32 errors_detected;
918 __be32 errors_logged;
919 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
920 }__attribute__((packed, aligned (4)));
922 struct ipr_hostrcb_type_23_error {
923 struct ipr_ext_vpd ioa_vpd;
924 struct ipr_ext_vpd cfc_vpd;
925 __be32 errors_detected;
926 __be32 errors_logged;
927 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
928 }__attribute__((packed, aligned (4)));
930 struct ipr_hostrcb_type_04_error {
931 struct ipr_vpd ioa_vpd;
932 struct ipr_vpd cfc_vpd;
934 struct ipr_hostrcb_array_data_entry array_member[10];
935 __be32 exposed_mode_adn;
937 struct ipr_vpd incomp_dev_vpd;
939 struct ipr_hostrcb_array_data_entry array_member2[8];
940 struct ipr_res_addr last_func_vset_res_addr;
941 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
942 u8 protection_level[8];
943 }__attribute__((packed, aligned (4)));
945 struct ipr_hostrcb_type_14_error {
946 struct ipr_ext_vpd ioa_vpd;
947 struct ipr_ext_vpd cfc_vpd;
948 __be32 exposed_mode_adn;
950 struct ipr_res_addr last_func_vset_res_addr;
951 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
952 u8 protection_level[8];
954 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
955 }__attribute__((packed, aligned (4)));
957 struct ipr_hostrcb_type_24_error {
958 struct ipr_ext_vpd ioa_vpd;
959 struct ipr_ext_vpd cfc_vpd;
962 #define IPR_INVALID_ARRAY_DEV_NUM 0xff
965 u8 protection_level[8];
966 struct ipr_ext_vpd64 array_vpd;
970 struct ipr_hostrcb64_array_data_entry array_member[32];
971 }__attribute__((packed, aligned (4)));
973 struct ipr_hostrcb_type_07_error {
974 u8 failure_reason[64];
977 }__attribute__((packed, aligned (4)));
979 struct ipr_hostrcb_type_17_error {
980 u8 failure_reason[64];
981 struct ipr_ext_vpd vpd;
983 }__attribute__((packed, aligned (4)));
985 struct ipr_hostrcb_config_element {
987 #define IPR_PATH_CFG_TYPE_MASK 0xF0
988 #define IPR_PATH_CFG_NOT_EXIST 0x00
989 #define IPR_PATH_CFG_IOA_PORT 0x10
990 #define IPR_PATH_CFG_EXP_PORT 0x20
991 #define IPR_PATH_CFG_DEVICE_PORT 0x30
992 #define IPR_PATH_CFG_DEVICE_LUN 0x40
994 #define IPR_PATH_CFG_STATUS_MASK 0x0F
995 #define IPR_PATH_CFG_NO_PROB 0x00
996 #define IPR_PATH_CFG_DEGRADED 0x01
997 #define IPR_PATH_CFG_FAILED 0x02
998 #define IPR_PATH_CFG_SUSPECT 0x03
999 #define IPR_PATH_NOT_DETECTED 0x04
1000 #define IPR_PATH_INCORRECT_CONN 0x05
1002 u8 cascaded_expander;
1005 #define IPR_PHY_LINK_RATE_MASK 0x0F
1008 }__attribute__((packed, aligned (4)));
1010 struct ipr_hostrcb64_config_element {
1013 #define IPR_DESCRIPTOR_MASK 0xC0
1014 #define IPR_DESCRIPTOR_SIS64 0x00
1024 }__attribute__((packed, aligned (8)));
1026 struct ipr_hostrcb_fabric_desc {
1029 u8 cascaded_expander;
1032 #define IPR_PATH_ACTIVE_MASK 0xC0
1033 #define IPR_PATH_NO_INFO 0x00
1034 #define IPR_PATH_ACTIVE 0x40
1035 #define IPR_PATH_NOT_ACTIVE 0x80
1037 #define IPR_PATH_STATE_MASK 0x0F
1038 #define IPR_PATH_STATE_NO_INFO 0x00
1039 #define IPR_PATH_HEALTHY 0x01
1040 #define IPR_PATH_DEGRADED 0x02
1041 #define IPR_PATH_FAILED 0x03
1044 struct ipr_hostrcb_config_element elem[1];
1045 }__attribute__((packed, aligned (4)));
1047 struct ipr_hostrcb64_fabric_desc {
1058 struct ipr_hostrcb64_config_element elem[1];
1059 }__attribute__((packed, aligned (8)));
1061 #define for_each_hrrq(hrrq, ioa_cfg) \
1062 for (hrrq = (ioa_cfg)->hrrq; \
1063 hrrq < ((ioa_cfg)->hrrq + (ioa_cfg)->hrrq_num); hrrq++)
1065 #define for_each_fabric_cfg(fabric, cfg) \
1066 for (cfg = (fabric)->elem; \
1067 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1070 struct ipr_hostrcb_type_20_error {
1071 u8 failure_reason[64];
1074 struct ipr_hostrcb_fabric_desc desc[1];
1075 }__attribute__((packed, aligned (4)));
1077 struct ipr_hostrcb_type_30_error {
1078 u8 failure_reason[64];
1081 struct ipr_hostrcb64_fabric_desc desc[1];
1082 }__attribute__((packed, aligned (4)));
1084 struct ipr_hostrcb_error {
1086 struct ipr_res_addr fd_res_addr;
1087 __be32 fd_res_handle;
1090 struct ipr_hostrcb_type_ff_error type_ff_error;
1091 struct ipr_hostrcb_type_01_error type_01_error;
1092 struct ipr_hostrcb_type_02_error type_02_error;
1093 struct ipr_hostrcb_type_03_error type_03_error;
1094 struct ipr_hostrcb_type_04_error type_04_error;
1095 struct ipr_hostrcb_type_07_error type_07_error;
1096 struct ipr_hostrcb_type_12_error type_12_error;
1097 struct ipr_hostrcb_type_13_error type_13_error;
1098 struct ipr_hostrcb_type_14_error type_14_error;
1099 struct ipr_hostrcb_type_17_error type_17_error;
1100 struct ipr_hostrcb_type_20_error type_20_error;
1102 }__attribute__((packed, aligned (4)));
1104 struct ipr_hostrcb64_error {
1106 __be32 ioa_fw_level;
1107 __be32 fd_res_handle;
1115 struct ipr_hostrcb_type_ff_error type_ff_error;
1116 struct ipr_hostrcb_type_12_error type_12_error;
1117 struct ipr_hostrcb_type_17_error type_17_error;
1118 struct ipr_hostrcb_type_23_error type_23_error;
1119 struct ipr_hostrcb_type_24_error type_24_error;
1120 struct ipr_hostrcb_type_30_error type_30_error;
1122 }__attribute__((packed, aligned (8)));
1124 struct ipr_hostrcb_raw {
1125 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1126 }__attribute__((packed, aligned (4)));
1130 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1131 #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1134 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1135 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1136 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1137 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1138 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1140 u8 notifications_lost;
1141 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1142 #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1145 #define IPR_HOSTRCB_INTERNAL_OPER 0x80
1146 #define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1149 #define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1150 #define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1151 #define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1152 #define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1153 #define IPR_HOST_RCB_OVERLAY_ID_6 0x06
1154 #define IPR_HOST_RCB_OVERLAY_ID_7 0x07
1155 #define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1156 #define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1157 #define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1158 #define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1159 #define IPR_HOST_RCB_OVERLAY_ID_17 0x17
1160 #define IPR_HOST_RCB_OVERLAY_ID_20 0x20
1161 #define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1162 #define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1163 #define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1164 #define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1165 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1169 __be32 time_since_last_ioa_reset;
1174 struct ipr_hostrcb_error error;
1175 struct ipr_hostrcb64_error error64;
1176 struct ipr_hostrcb_cfg_ch_not ccn;
1177 struct ipr_hostrcb_raw raw;
1179 }__attribute__((packed, aligned (4)));
1181 struct ipr_hostrcb {
1182 struct ipr_hcam hcam;
1183 dma_addr_t hostrcb_dma;
1184 struct list_head queue;
1185 struct ipr_ioa_cfg *ioa_cfg;
1186 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1189 /* IPR smart dump table structures */
1190 struct ipr_sdt_entry {
1196 #define IPR_SDT_ENDIAN 0x80
1197 #define IPR_SDT_VALID_ENTRY 0x20
1201 }__attribute__((packed, aligned (4)));
1203 struct ipr_sdt_header {
1206 __be32 num_entries_used;
1208 }__attribute__((packed, aligned (4)));
1211 struct ipr_sdt_header hdr;
1212 struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES];
1213 }__attribute__((packed, aligned (4)));
1216 struct ipr_sdt_header hdr;
1217 struct ipr_sdt_entry entry[1];
1218 }__attribute__((packed, aligned (4)));
1223 struct ipr_bus_attributes {
1231 struct ipr_sata_port {
1232 struct ipr_ioa_cfg *ioa_cfg;
1233 struct ata_port *ap;
1234 struct ipr_resource_entry *res;
1235 struct ipr_ioasa_gata ioasa;
1238 struct ipr_resource_entry {
1239 u8 needs_sync_complete:1;
1243 u8 resetting_device:1;
1245 u32 bus; /* AKA channel */
1246 u32 target; /* AKA id */
1248 #define IPR_ARRAY_VIRTUAL_BUS 0x1
1249 #define IPR_VSET_VIRTUAL_BUS 0x2
1250 #define IPR_IOAFP_VIRTUAL_BUS 0x3
1252 #define IPR_GET_RES_PHYS_LOC(res) \
1253 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1263 struct ipr_std_inq_data std_inq_data;
1268 struct scsi_lun dev_lun;
1271 struct ipr_ioa_cfg *ioa_cfg;
1272 struct scsi_device *sdev;
1273 struct ipr_sata_port *sata_port;
1274 struct list_head queue;
1275 }; /* struct ipr_resource_entry */
1277 struct ipr_resource_hdr {
1282 struct ipr_misc_cbs {
1283 struct ipr_ioa_vpd ioa_vpd;
1284 struct ipr_inquiry_page0 page0_data;
1285 struct ipr_inquiry_page3 page3_data;
1286 struct ipr_inquiry_cap cap;
1287 struct ipr_mode_pages mode_pages;
1288 struct ipr_supported_device supp_dev;
1291 struct ipr_interrupt_offsets {
1292 unsigned long set_interrupt_mask_reg;
1293 unsigned long clr_interrupt_mask_reg;
1294 unsigned long clr_interrupt_mask_reg32;
1295 unsigned long sense_interrupt_mask_reg;
1296 unsigned long sense_interrupt_mask_reg32;
1297 unsigned long clr_interrupt_reg;
1298 unsigned long clr_interrupt_reg32;
1300 unsigned long sense_interrupt_reg;
1301 unsigned long sense_interrupt_reg32;
1302 unsigned long ioarrin_reg;
1303 unsigned long sense_uproc_interrupt_reg;
1304 unsigned long sense_uproc_interrupt_reg32;
1305 unsigned long set_uproc_interrupt_reg;
1306 unsigned long set_uproc_interrupt_reg32;
1307 unsigned long clr_uproc_interrupt_reg;
1308 unsigned long clr_uproc_interrupt_reg32;
1310 unsigned long init_feedback_reg;
1312 unsigned long dump_addr_reg;
1313 unsigned long dump_data_reg;
1315 #define IPR_ENDIAN_SWAP_KEY 0x00080800
1316 unsigned long endian_swap_reg;
1319 struct ipr_interrupts {
1320 void __iomem *set_interrupt_mask_reg;
1321 void __iomem *clr_interrupt_mask_reg;
1322 void __iomem *clr_interrupt_mask_reg32;
1323 void __iomem *sense_interrupt_mask_reg;
1324 void __iomem *sense_interrupt_mask_reg32;
1325 void __iomem *clr_interrupt_reg;
1326 void __iomem *clr_interrupt_reg32;
1328 void __iomem *sense_interrupt_reg;
1329 void __iomem *sense_interrupt_reg32;
1330 void __iomem *ioarrin_reg;
1331 void __iomem *sense_uproc_interrupt_reg;
1332 void __iomem *sense_uproc_interrupt_reg32;
1333 void __iomem *set_uproc_interrupt_reg;
1334 void __iomem *set_uproc_interrupt_reg32;
1335 void __iomem *clr_uproc_interrupt_reg;
1336 void __iomem *clr_uproc_interrupt_reg32;
1338 void __iomem *init_feedback_reg;
1340 void __iomem *dump_addr_reg;
1341 void __iomem *dump_data_reg;
1343 void __iomem *endian_swap_reg;
1346 struct ipr_chip_cfg_t {
1351 struct ipr_interrupt_offsets regs;
1358 #define IPR_USE_LSI 0x00
1359 #define IPR_USE_MSI 0x01
1360 #define IPR_USE_MSIX 0x02
1362 #define IPR_SIS32 0x00
1363 #define IPR_SIS64 0x01
1365 #define IPR_PCI_CFG 0x00
1366 #define IPR_MMIO 0x01
1367 const struct ipr_chip_cfg_t *cfg;
1370 enum ipr_shutdown_type {
1371 IPR_SHUTDOWN_NORMAL = 0x00,
1372 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1373 IPR_SHUTDOWN_ABBREV = 0x80,
1374 IPR_SHUTDOWN_NONE = 0x100
1377 struct ipr_trace_entry {
1383 #define IPR_TRACE_START 0x00
1384 #define IPR_TRACE_FINISH 0xff
1400 struct scatterlist scatterlist[1];
1403 enum ipr_sdt_state {
1412 /* Per-controller data */
1413 struct ipr_ioa_cfg {
1414 char eye_catcher[8];
1415 #define IPR_EYECATCHER "iprcfg"
1417 struct list_head queue;
1419 u8 in_reset_reload:1;
1420 u8 in_ioa_bringdown:1;
1421 u8 ioa_unit_checked:1;
1423 u8 allow_ml_add_del:1;
1424 u8 needs_hard_reset:1;
1426 u8 needs_warm_reset:1;
1436 * Bitmaps for SIS64 generated target values
1438 unsigned long *target_ids;
1439 unsigned long *array_ids;
1440 unsigned long *vset_ids;
1442 u16 type; /* CCIN of the card */
1445 #define IPR_MAX_LOG_LEVEL 4
1446 #define IPR_DEFAULT_LOG_LEVEL 2
1448 #define IPR_NUM_TRACE_INDEX_BITS 8
1449 #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1450 #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1451 char trace_start[8];
1452 #define IPR_TRACE_START_LABEL "trace"
1453 struct ipr_trace_entry *trace;
1454 atomic_t trace_index;
1456 char cfg_table_start[8];
1457 #define IPR_CFG_TBL_START "cfg"
1459 struct ipr_config_table *cfg_table;
1460 struct ipr_config_table64 *cfg_table64;
1462 dma_addr_t cfg_table_dma;
1464 u32 max_devs_supported;
1466 char resource_table_label[8];
1467 #define IPR_RES_TABLE_LABEL "res_tbl"
1468 struct ipr_resource_entry *res_entries;
1469 struct list_head free_res_q;
1470 struct list_head used_res_q;
1472 char ipr_hcam_label[8];
1473 #define IPR_HCAM_LABEL "hcams"
1474 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1475 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1476 struct list_head hostrcb_free_q;
1477 struct list_head hostrcb_pending_q;
1479 struct ipr_hrr_queue hrrq[IPR_MAX_HRRQ_NUM];
1481 atomic_t hrrq_index;
1482 u16 identify_hrrq_index;
1484 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1486 unsigned int transop_timeout;
1487 const struct ipr_chip_cfg_t *chip_cfg;
1488 const struct ipr_chip_t *ipr_chip;
1490 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1491 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1492 void __iomem *ioa_mailbox;
1493 struct ipr_interrupts regs;
1495 u16 saved_pcix_cmd_reg;
1501 struct Scsi_Host *host;
1502 struct pci_dev *pdev;
1503 struct ipr_sglist *ucode_sglist;
1504 u8 saved_mode_page_len;
1506 struct work_struct work_q;
1508 wait_queue_head_t reset_wait_q;
1509 wait_queue_head_t msi_wait_q;
1511 struct ipr_dump *dump;
1512 enum ipr_sdt_state sdt_state;
1514 struct ipr_misc_cbs *vpd_cbs;
1515 dma_addr_t vpd_cbs_dma;
1517 struct pci_pool *ipr_cmd_pool;
1519 struct ipr_cmnd *reset_cmd;
1520 int (*reset) (struct ipr_cmnd *);
1522 struct ata_host ata_host;
1523 char ipr_cmd_label[8];
1524 #define IPR_CMD_LABEL "ipr_cmd"
1526 struct ipr_cmnd **ipr_cmnd_list;
1527 dma_addr_t *ipr_cmnd_list_dma;
1530 unsigned int nvectors;
1535 } vectors_info[IPR_MAX_MSIX_VECTORS];
1537 }; /* struct ipr_ioa_cfg */
1540 struct ipr_ioarcb ioarcb;
1542 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1543 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1544 struct ipr_ata64_ioadl ata_ioadl;
1547 struct ipr_ioasa ioasa;
1548 struct ipr_ioasa64 ioasa64;
1550 struct list_head queue;
1551 struct scsi_cmnd *scsi_cmd;
1552 struct ata_queued_cmd *qc;
1553 struct completion completion;
1554 struct timer_list timer;
1555 void (*fast_done) (struct ipr_cmnd *);
1556 void (*done) (struct ipr_cmnd *);
1557 int (*job_step) (struct ipr_cmnd *);
1558 int (*job_step_failed) (struct ipr_cmnd *);
1560 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1561 dma_addr_t sense_buffer_dma;
1562 unsigned short dma_use_sg;
1563 dma_addr_t dma_addr;
1564 struct ipr_cmnd *sibling;
1566 enum ipr_shutdown_type shutdown_type;
1567 struct ipr_hostrcb *hostrcb;
1568 unsigned long time_left;
1569 unsigned long scratch;
1570 struct ipr_resource_entry *res;
1571 struct scsi_device *sdev;
1574 struct ipr_hrr_queue *hrrq;
1575 struct ipr_ioa_cfg *ioa_cfg;
1578 struct ipr_ses_table_entry {
1579 char product_id[17];
1580 char compare_product_id_byte[17];
1581 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1584 struct ipr_dump_header {
1586 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1589 u32 first_entry_offset;
1591 #define IPR_DUMP_STATUS_SUCCESS 0
1592 #define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1593 #define IPR_DUMP_STATUS_FAILED 0xffffffff
1595 #define IPR_DUMP_OS_LINUX 0x4C4E5558
1597 #define IPR_DUMP_DRIVER_NAME 0x49505232
1598 }__attribute__((packed, aligned (4)));
1600 struct ipr_dump_entry_header {
1602 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1607 #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1608 #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1610 #define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1611 #define IPR_DUMP_LOCATION_ID 0x4C4F4341
1612 #define IPR_DUMP_TRACE_ID 0x54524143
1613 #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1614 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1615 #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1616 #define IPR_DUMP_PEND_OPS 0x414F5053
1618 }__attribute__((packed, aligned (4)));
1620 struct ipr_dump_location_entry {
1621 struct ipr_dump_entry_header hdr;
1623 }__attribute__((packed));
1625 struct ipr_dump_trace_entry {
1626 struct ipr_dump_entry_header hdr;
1627 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1628 }__attribute__((packed, aligned (4)));
1630 struct ipr_dump_version_entry {
1631 struct ipr_dump_entry_header hdr;
1632 u8 version[sizeof(IPR_DRIVER_VERSION)];
1635 struct ipr_dump_ioa_type_entry {
1636 struct ipr_dump_entry_header hdr;
1641 struct ipr_driver_dump {
1642 struct ipr_dump_header hdr;
1643 struct ipr_dump_version_entry version_entry;
1644 struct ipr_dump_location_entry location_entry;
1645 struct ipr_dump_ioa_type_entry ioa_type_entry;
1646 struct ipr_dump_trace_entry trace_entry;
1647 }__attribute__((packed));
1649 struct ipr_ioa_dump {
1650 struct ipr_dump_entry_header hdr;
1654 u32 next_page_index;
1657 }__attribute__((packed, aligned (4)));
1661 struct ipr_ioa_cfg *ioa_cfg;
1662 struct ipr_driver_dump driver_dump;
1663 struct ipr_ioa_dump ioa_dump;
1666 struct ipr_error_table_t {
1673 struct ipr_software_inq_lid_info {
1675 __be32 timestamp[3];
1676 }__attribute__((packed, aligned (4)));
1678 struct ipr_ucode_image_header {
1679 __be32 header_length;
1680 __be32 lid_table_offset;
1683 u8 minor_release[2];
1685 char eyecatcher[16];
1687 struct ipr_software_inq_lid_info lid[1];
1688 }__attribute__((packed, aligned (4)));
1693 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1695 #ifdef CONFIG_SCSI_IPR_TRACE
1696 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1697 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1699 #define ipr_create_trace_file(kobj, attr) 0
1700 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1703 #ifdef CONFIG_SCSI_IPR_DUMP
1704 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1705 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1707 #define ipr_create_dump_file(kobj, attr) 0
1708 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1712 * Error logging macros
1714 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1715 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1716 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1718 #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1719 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1720 bus, target, lun, ##__VA_ARGS__)
1722 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1723 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1725 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1726 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1727 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1729 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1730 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1732 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1734 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1735 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1737 ipr_err(fmt": %d:%d:%d:%d\n", \
1738 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1739 (res).bus, (res).target, (res).lun); \
1743 #define ipr_hcam_err(hostrcb, fmt, ...) \
1745 if (ipr_is_device(hostrcb)) { \
1746 if ((hostrcb)->ioa_cfg->sis64) { \
1747 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
1748 ipr_format_res_path(hostrcb->ioa_cfg, \
1749 hostrcb->hcam.u.error64.fd_res_path, \
1750 hostrcb->rp_buffer, \
1751 sizeof(hostrcb->rp_buffer)), \
1754 ipr_ra_err((hostrcb)->ioa_cfg, \
1755 (hostrcb)->hcam.u.error.fd_res_addr, \
1756 fmt, __VA_ARGS__); \
1759 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1763 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1764 __FILE__, __func__, __LINE__)
1766 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1767 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1769 #define ipr_err_separator \
1770 ipr_err("----------------------------------------------------------\n")
1778 * ipr_is_ioa_resource - Determine if a resource is the IOA
1779 * @res: resource entry struct
1782 * 1 if IOA / 0 if not IOA
1784 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1786 return res->type == IPR_RES_TYPE_IOAFP;
1790 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1791 * @res: resource entry struct
1794 * 1 if AF DASD / 0 if not AF DASD
1796 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1798 return res->type == IPR_RES_TYPE_AF_DASD ||
1799 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1803 * ipr_is_vset_device - Determine if a resource is a VSET
1804 * @res: resource entry struct
1807 * 1 if VSET / 0 if not VSET
1809 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1811 return res->type == IPR_RES_TYPE_VOLUME_SET;
1815 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1816 * @res: resource entry struct
1819 * 1 if GSCSI / 0 if not GSCSI
1821 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1823 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1827 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1828 * @res: resource entry struct
1831 * 1 if SCSI disk / 0 if not SCSI disk
1833 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1835 if (ipr_is_af_dasd_device(res) ||
1836 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1843 * ipr_is_gata - Determine if a resource is a generic ATA resource
1844 * @res: resource entry struct
1847 * 1 if GATA / 0 if not GATA
1849 static inline int ipr_is_gata(struct ipr_resource_entry *res)
1851 return res->type == IPR_RES_TYPE_GENERIC_ATA;
1855 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1856 * @res: resource entry struct
1859 * 1 if NACA queueing model / 0 if not NACA queueing model
1861 static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1863 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1869 * ipr_is_device - Determine if the hostrcb structure is related to a device
1870 * @hostrcb: host resource control blocks struct
1873 * 1 if AF / 0 if not AF
1875 static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1877 struct ipr_res_addr *res_addr;
1880 if (hostrcb->ioa_cfg->sis64) {
1881 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1882 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1883 res_path[0] == 0x81) && res_path[2] != 0xFF)
1886 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1888 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1889 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1896 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1897 * @sdt_word: SDT address
1900 * 1 if format 2 / 0 if not
1902 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1904 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1907 case IPR_SDT_FMT2_BAR0_SEL:
1908 case IPR_SDT_FMT2_BAR1_SEL:
1909 case IPR_SDT_FMT2_BAR2_SEL:
1910 case IPR_SDT_FMT2_BAR3_SEL:
1911 case IPR_SDT_FMT2_BAR4_SEL:
1912 case IPR_SDT_FMT2_BAR5_SEL:
1913 case IPR_SDT_FMT2_EXP_ROM_SEL:
1921 static inline void writeq(u64 val, void __iomem *addr)
1923 writel(((u32) (val >> 32)), addr);
1924 writel(((u32) (val)), (addr + 4));