2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2014-2015 PMC-Sierra, Inc.
4 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
15 * Questions/Comments/Bugfixes to storagedev@pmcs.com
21 #include <scsi/scsicam.h>
28 struct access_method {
29 void (*submit_command)(struct ctlr_info *h,
30 struct CommandList *c);
31 void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
32 bool (*intr_pending)(struct ctlr_info *h);
33 unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
36 struct hpsa_scsi_dev_t {
38 int bus, target, lun; /* as presented to the OS */
39 unsigned char scsi3addr[8]; /* as presented to the HW */
40 u8 physical_device : 1;
42 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
43 unsigned char device_id[16]; /* from inquiry pg. 0x83 */
44 unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
45 unsigned char model[16]; /* bytes 16-31 of inquiry data */
46 unsigned char raid_level; /* from inquiry page 0xC1 */
47 unsigned char volume_offline; /* discovered via TUR or VPD */
48 u16 queue_depth; /* max queue_depth for this device */
49 atomic_t reset_cmds_out; /* Count of commands to-be affected */
50 atomic_t ioaccel_cmds_out; /* Only used for physical devices
51 * counts commands sent to physical
52 * device via "ioaccel" path.
59 u16 phys_connector[8];
60 int offload_config; /* I/O accel RAID offload configured */
61 int offload_enabled; /* I/O accel RAID offload enabled */
62 int offload_to_be_enabled;
63 int hba_ioaccel_enabled;
64 int offload_to_mirror; /* Send next I/O accelerator RAID
65 * offload request to mirror drive
67 struct raid_map_data raid_map; /* I/O accelerator RAID map */
70 * Pointers from logical drive map indices to the phys drives that
71 * make those logical drives. Note, multiple logical drives may
72 * share physical drives. You can have for instance 5 physical
73 * drives with 3 logical drives each using those same 5 physical
74 * disks. We need these pointers for counting i/o's out to physical
75 * devices in order to honor physical device queue depth limits.
77 struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES];
80 int external; /* 1-from external array 0-not <0-unknown */
83 struct reply_queue_buffer {
92 struct bmic_controller_parameters {
94 u8 enable_command_list_verification;
95 u8 backed_out_write_drives;
96 u16 stripes_for_parity;
97 u8 parity_distribution_mode_flags;
98 u16 max_driver_requests;
99 u16 elevator_trend_count;
101 u8 force_scan_complete;
102 u8 scsi_transfer_mode;
106 u8 host_sdb_asic_fix;
107 u8 pdpi_burst_from_host_disabled;
108 char software_name[64];
109 char hardware_name[32];
111 u8 snapshot_priority;
113 u8 post_prompt_timeout;
114 u8 automatic_drive_slamming;
117 u8 cache_nvram_flags;
118 u8 drive_config_flags;
120 u8 temp_warning_level;
121 u8 temp_shutdown_level;
122 u8 temp_condition_reset;
123 u8 max_coalesce_commands;
124 u32 max_coalesce_delay;
135 struct pci_dev *pdev;
139 int nr_cmds; /* Number of commands allowed on this controller */
140 #define HPSA_CMDS_RESERVED_FOR_ABORTS 2
141 #define HPSA_CMDS_RESERVED_FOR_DRIVER 1
142 struct CfgTable __iomem *cfgtable;
143 int interrupts_enabled;
145 atomic_t commands_outstanding;
146 # define PERF_MODE_INT 0
147 # define DOORBELL_INT 1
148 # define SIMPLE_MODE_INT 2
149 # define MEMQ_MODE_INT 3
150 unsigned int intr[MAX_REPLY_QUEUES];
151 unsigned int msix_vector;
152 unsigned int msi_vector;
153 int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
154 struct access_method access;
156 /* queue and queue Info */
161 u8 max_cmd_sg_entries;
163 struct SGDescriptor **cmd_sg_list;
164 struct ioaccel2_sg_element **ioaccel2_cmd_sg_list;
166 /* pointers to command and error info pool */
167 struct CommandList *cmd_pool;
168 dma_addr_t cmd_pool_dhandle;
169 struct io_accel1_cmd *ioaccel_cmd_pool;
170 dma_addr_t ioaccel_cmd_pool_dhandle;
171 struct io_accel2_cmd *ioaccel2_cmd_pool;
172 dma_addr_t ioaccel2_cmd_pool_dhandle;
173 struct ErrorInfo *errinfo_pool;
174 dma_addr_t errinfo_pool_dhandle;
175 unsigned long *cmd_pool_bits;
177 spinlock_t scan_lock;
178 wait_queue_head_t scan_wait_queue;
180 struct Scsi_Host *scsi_host;
181 spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
182 int ndevices; /* number of used elements in .dev[] array. */
183 struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
185 * Performant mode tables.
189 struct TransTable_struct __iomem *transtable;
190 unsigned long transMethod;
192 /* cap concurrent passthrus at some reasonable maximum */
193 #define HPSA_MAX_CONCURRENT_PASSTHRUS (10)
194 atomic_t passthru_cmds_avail;
197 * Performant mode completion buffers
199 size_t reply_queue_size;
200 struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES];
202 u32 *blockFetchTable;
203 u32 *ioaccel1_blockFetchTable;
204 u32 *ioaccel2_blockFetchTable;
205 u32 __iomem *ioaccel2_bft2_regs;
206 unsigned char *hba_inquiry_data;
211 u64 last_intr_timestamp;
213 u64 last_heartbeat_timestamp;
214 u32 heartbeat_sample_interval;
215 atomic_t firmware_flash_in_progress;
216 u32 __percpu *lockup_detected;
217 struct delayed_work monitor_ctlr_work;
218 struct delayed_work rescan_ctlr_work;
219 int remove_in_progress;
220 /* Address of h->q[x] is passed to intr handler to know which queue */
221 u8 q[MAX_REPLY_QUEUES];
222 char intrname[MAX_REPLY_QUEUES][16]; /* "hpsa0-msix00" names */
223 u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
224 #define HPSATMF_BITS_SUPPORTED (1 << 0)
225 #define HPSATMF_PHYS_LUN_RESET (1 << 1)
226 #define HPSATMF_PHYS_NEX_RESET (1 << 2)
227 #define HPSATMF_PHYS_TASK_ABORT (1 << 3)
228 #define HPSATMF_PHYS_TSET_ABORT (1 << 4)
229 #define HPSATMF_PHYS_CLEAR_ACA (1 << 5)
230 #define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
231 #define HPSATMF_PHYS_QRY_TASK (1 << 7)
232 #define HPSATMF_PHYS_QRY_TSET (1 << 8)
233 #define HPSATMF_PHYS_QRY_ASYNC (1 << 9)
234 #define HPSATMF_IOACCEL_ENABLED (1 << 15)
235 #define HPSATMF_MASK_SUPPORTED (1 << 16)
236 #define HPSATMF_LOG_LUN_RESET (1 << 17)
237 #define HPSATMF_LOG_NEX_RESET (1 << 18)
238 #define HPSATMF_LOG_TASK_ABORT (1 << 19)
239 #define HPSATMF_LOG_TSET_ABORT (1 << 20)
240 #define HPSATMF_LOG_CLEAR_ACA (1 << 21)
241 #define HPSATMF_LOG_CLEAR_TSET (1 << 22)
242 #define HPSATMF_LOG_QRY_TASK (1 << 23)
243 #define HPSATMF_LOG_QRY_TSET (1 << 24)
244 #define HPSATMF_LOG_QRY_ASYNC (1 << 25)
246 #define CTLR_STATE_CHANGE_EVENT (1 << 0)
247 #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1)
248 #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4)
249 #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5)
250 #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6)
251 #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30)
252 #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31)
254 #define RESCAN_REQUIRED_EVENT_BITS \
255 (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \
256 CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \
257 CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \
258 CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \
259 CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE)
260 spinlock_t offline_device_lock;
261 struct list_head offline_device_list;
262 int acciopath_status;
264 int raid_offload_debug;
265 int discovery_polling;
266 struct ReportLUNdata *lastlogicals;
267 int needs_abort_tags_swizzled;
268 struct workqueue_struct *resubmit_wq;
269 struct workqueue_struct *rescan_ctlr_wq;
270 atomic_t abort_cmds_available;
271 wait_queue_head_t abort_cmd_wait_queue;
272 wait_queue_head_t event_sync_wait_queue;
273 struct mutex reset_mutex;
274 u8 reset_in_progress;
277 struct offline_device_entry {
278 unsigned char scsi3addr[8];
279 struct list_head offline_list;
282 #define HPSA_ABORT_MSG 0
283 #define HPSA_DEVICE_RESET_MSG 1
284 #define HPSA_RESET_TYPE_CONTROLLER 0x00
285 #define HPSA_RESET_TYPE_BUS 0x01
286 #define HPSA_RESET_TYPE_TARGET 0x03
287 #define HPSA_RESET_TYPE_LUN 0x04
288 #define HPSA_PHYS_TARGET_RESET 0x99 /* not defined by cciss spec */
289 #define HPSA_MSG_SEND_RETRY_LIMIT 10
290 #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
292 /* Maximum time in seconds driver will wait for command completions
293 * when polling before giving up.
295 #define HPSA_MAX_POLL_TIME_SECS (20)
297 /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
298 * how many times to retry TEST UNIT READY on a device
299 * while waiting for it to become ready before giving up.
300 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
301 * between sending TURs while waiting for a device
304 #define HPSA_TUR_RETRY_LIMIT (20)
305 #define HPSA_MAX_WAIT_INTERVAL_SECS (30)
307 /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
308 * to become ready, in seconds, before giving up on it.
309 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
310 * between polling the board to see if it is ready, in
311 * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
312 * HPSA_BOARD_READY_ITERATIONS are derived from those.
314 #define HPSA_BOARD_READY_WAIT_SECS (120)
315 #define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
316 #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
317 #define HPSA_BOARD_READY_POLL_INTERVAL \
318 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
319 #define HPSA_BOARD_READY_ITERATIONS \
320 ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
321 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
322 #define HPSA_BOARD_NOT_READY_ITERATIONS \
323 ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
324 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
325 #define HPSA_POST_RESET_PAUSE_MSECS (3000)
326 #define HPSA_POST_RESET_NOOP_RETRIES (12)
328 /* Defining the diffent access_menthods */
330 * Memory mapped FIFO interface (SMART 53xx cards)
332 #define SA5_DOORBELL 0x20
333 #define SA5_REQUEST_PORT_OFFSET 0x40
334 #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0
335 #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4
336 #define SA5_REPLY_INTR_MASK_OFFSET 0x34
337 #define SA5_REPLY_PORT_OFFSET 0x44
338 #define SA5_INTR_STATUS 0x30
339 #define SA5_SCRATCHPAD_OFFSET 0xB0
341 #define SA5_CTCFG_OFFSET 0xB4
342 #define SA5_CTMEM_OFFSET 0xB8
344 #define SA5_INTR_OFF 0x08
345 #define SA5B_INTR_OFF 0x04
346 #define SA5_INTR_PENDING 0x08
347 #define SA5B_INTR_PENDING 0x04
348 #define FIFO_EMPTY 0xffffffff
349 #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
351 #define HPSA_ERROR_BIT 0x02
353 /* Performant mode flags */
354 #define SA5_PERF_INTR_PENDING 0x04
355 #define SA5_PERF_INTR_OFF 0x05
356 #define SA5_OUTDB_STATUS_PERF_BIT 0x01
357 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
358 #define SA5_OUTDB_CLEAR 0xA0
359 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
360 #define SA5_OUTDB_STATUS 0x9C
363 #define HPSA_INTR_ON 1
364 #define HPSA_INTR_OFF 0
367 * Inbound Post Queue offsets for IO Accelerator Mode 2
369 #define IOACCEL2_INBOUND_POSTQ_32 0x48
370 #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0
371 #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4
373 #define HPSA_PHYSICAL_DEVICE_BUS 0
374 #define HPSA_RAID_VOLUME_BUS 1
375 #define HPSA_EXTERNAL_RAID_VOLUME_BUS 2
376 #define HPSA_HBA_BUS 3
379 Send the command to the hardware
381 static void SA5_submit_command(struct ctlr_info *h,
382 struct CommandList *c)
384 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
385 (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
388 static void SA5_submit_command_no_read(struct ctlr_info *h,
389 struct CommandList *c)
391 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
394 static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
395 struct CommandList *c)
397 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
401 * This card is the opposite of the other cards.
402 * 0 turns interrupts on...
403 * 0x08 turns them off...
405 static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
407 if (val) { /* Turn interrupts on */
408 h->interrupts_enabled = 1;
409 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
410 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
411 } else { /* Turn them off */
412 h->interrupts_enabled = 0;
414 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
415 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
419 static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
421 if (val) { /* turn on interrupts */
422 h->interrupts_enabled = 1;
423 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
424 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
426 h->interrupts_enabled = 0;
427 writel(SA5_PERF_INTR_OFF,
428 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
429 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
433 static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
435 struct reply_queue_buffer *rq = &h->reply_queue[q];
436 unsigned long register_value = FIFO_EMPTY;
438 /* msi auto clears the interrupt pending bit. */
439 if (unlikely(!(h->msi_vector || h->msix_vector))) {
440 /* flush the controller write of the reply queue by reading
441 * outbound doorbell status register.
443 (void) readl(h->vaddr + SA5_OUTDB_STATUS);
444 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
445 /* Do a read in order to flush the write to the controller
448 (void) readl(h->vaddr + SA5_OUTDB_STATUS);
451 if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) {
452 register_value = rq->head[rq->current_entry];
454 atomic_dec(&h->commands_outstanding);
456 register_value = FIFO_EMPTY;
458 /* Check for wraparound */
459 if (rq->current_entry == h->max_commands) {
460 rq->current_entry = 0;
463 return register_value;
467 * returns value read from hardware.
468 * returns FIFO_EMPTY if there is nothing to read
470 static unsigned long SA5_completed(struct ctlr_info *h,
471 __attribute__((unused)) u8 q)
473 unsigned long register_value
474 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
476 if (register_value != FIFO_EMPTY)
477 atomic_dec(&h->commands_outstanding);
480 if (register_value != FIFO_EMPTY)
481 dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
484 dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
487 return register_value;
490 * Returns true if an interrupt is pending..
492 static bool SA5_intr_pending(struct ctlr_info *h)
494 unsigned long register_value =
495 readl(h->vaddr + SA5_INTR_STATUS);
496 return register_value & SA5_INTR_PENDING;
499 static bool SA5_performant_intr_pending(struct ctlr_info *h)
501 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
506 /* Read outbound doorbell to flush */
507 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
508 return register_value & SA5_OUTDB_STATUS_PERF_BIT;
511 #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100
513 static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
515 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
517 return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ?
521 #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0
522 #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8
523 #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC
524 #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL
526 static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
529 struct reply_queue_buffer *rq = &h->reply_queue[q];
531 BUG_ON(q >= h->nreply_queues);
533 register_value = rq->head[rq->current_entry];
534 if (register_value != IOACCEL_MODE1_REPLY_UNUSED) {
535 rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;
536 if (++rq->current_entry == rq->size)
537 rq->current_entry = 0;
541 * Don't really need to write the new index after each command,
542 * but with current driver design this is easiest.
545 writel((q << 24) | rq->current_entry, h->vaddr +
546 IOACCEL_MODE1_CONSUMER_INDEX);
547 atomic_dec(&h->commands_outstanding);
549 return (unsigned long) register_value;
552 static struct access_method SA5_access = {
559 static struct access_method SA5_ioaccel_mode1_access = {
561 SA5_performant_intr_mask,
562 SA5_ioaccel_mode1_intr_pending,
563 SA5_ioaccel_mode1_completed,
566 static struct access_method SA5_ioaccel_mode2_access = {
567 SA5_submit_command_ioaccel2,
568 SA5_performant_intr_mask,
569 SA5_performant_intr_pending,
570 SA5_performant_completed,
573 static struct access_method SA5_performant_access = {
575 SA5_performant_intr_mask,
576 SA5_performant_intr_pending,
577 SA5_performant_completed,
580 static struct access_method SA5_performant_access_no_read = {
581 SA5_submit_command_no_read,
582 SA5_performant_intr_mask,
583 SA5_performant_intr_pending,
584 SA5_performant_completed,
590 struct access_method *access;