drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

   1 /*
   2  * Copyright (c) 2017 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  */
  10
  11 #include "hisi_sas.h"
  12 #define DRV_NAME "hisi_sas_v3_hw"
  13
  14 /* global registers need init*/
  15 #define DLVRY_QUEUE_ENABLE              0x0
  16 #define IOST_BASE_ADDR_LO               0x8
  17 #define IOST_BASE_ADDR_HI               0xc
  18 #define ITCT_BASE_ADDR_LO               0x10
  19 #define ITCT_BASE_ADDR_HI               0x14
  20 #define IO_BROKEN_MSG_ADDR_LO           0x18
  21 #define IO_BROKEN_MSG_ADDR_HI           0x1c
  22 #define PHY_CONTEXT                     0x20
  23 #define PHY_STATE                       0x24
  24 #define PHY_PORT_NUM_MA                 0x28
  25 #define PHY_CONN_RATE                   0x30
  26 #define ITCT_CLR                        0x44
  27 #define ITCT_CLR_EN_OFF                 16
  28 #define ITCT_CLR_EN_MSK                 (0x1 << ITCT_CLR_EN_OFF)
  29 #define ITCT_DEV_OFF                    0
  30 #define ITCT_DEV_MSK                    (0x7ff << ITCT_DEV_OFF)
  31 #define IO_SATA_BROKEN_MSG_ADDR_LO      0x58
  32 #define IO_SATA_BROKEN_MSG_ADDR_HI      0x5c
  33 #define SATA_INITI_D2H_STORE_ADDR_LO    0x60
  34 #define SATA_INITI_D2H_STORE_ADDR_HI    0x64
  35 #define CFG_MAX_TAG                     0x68
  36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
  37 #define HGC_SAS_TXFAIL_RETRY_CTRL       0x88
  38 #define HGC_GET_ITV_TIME                0x90
  39 #define DEVICE_MSG_WORK_MODE            0x94
  40 #define OPENA_WT_CONTI_TIME             0x9c
  41 #define I_T_NEXUS_LOSS_TIME             0xa0
  42 #define MAX_CON_TIME_LIMIT_TIME         0xa4
  43 #define BUS_INACTIVE_LIMIT_TIME         0xa8
  44 #define REJECT_TO_OPEN_LIMIT_TIME       0xac
  45 #define CFG_AGING_TIME                  0xbc
  46 #define HGC_DFX_CFG2                    0xc0
  47 #define CFG_ABT_SET_QUERY_IPTT  0xd4
  48 #define CFG_SET_ABORTED_IPTT_OFF        0
  49 #define CFG_SET_ABORTED_IPTT_MSK        (0xfff << CFG_SET_ABORTED_IPTT_OFF)
  50 #define CFG_SET_ABORTED_EN_OFF  12
  51 #define CFG_ABT_SET_IPTT_DONE   0xd8
  52 #define CFG_ABT_SET_IPTT_DONE_OFF       0
  53 #define HGC_IOMB_PROC1_STATUS   0x104
  54 #define CHNL_INT_STATUS                 0x148
  55 #define HGC_AXI_FIFO_ERR_INFO  0x154
  56 #define AXI_ERR_INFO_OFF               0
  57 #define AXI_ERR_INFO_MSK               (0xff << AXI_ERR_INFO_OFF)
  58 #define FIFO_ERR_INFO_OFF              8
  59 #define FIFO_ERR_INFO_MSK              (0xff << FIFO_ERR_INFO_OFF)
  60 #define INT_COAL_EN                     0x19c
  61 #define OQ_INT_COAL_TIME                0x1a0
  62 #define OQ_INT_COAL_CNT                 0x1a4
  63 #define ENT_INT_COAL_TIME               0x1a8
  64 #define ENT_INT_COAL_CNT                0x1ac
  65 #define OQ_INT_SRC                      0x1b0
  66 #define OQ_INT_SRC_MSK                  0x1b4
  67 #define ENT_INT_SRC1                    0x1b8
  68 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF    0
  69 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
  70 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF    8
  71 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
  72 #define ENT_INT_SRC2                    0x1bc
  73 #define ENT_INT_SRC3                    0x1c0
  74 #define ENT_INT_SRC3_WP_DEPTH_OFF               8
  75 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF      9
  76 #define ENT_INT_SRC3_RP_DEPTH_OFF               10
  77 #define ENT_INT_SRC3_AXI_OFF                    11
  78 #define ENT_INT_SRC3_FIFO_OFF                   12
  79 #define ENT_INT_SRC3_LM_OFF                             14
  80 #define ENT_INT_SRC3_ITC_INT_OFF        15
  81 #define ENT_INT_SRC3_ITC_INT_MSK        (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
  82 #define ENT_INT_SRC3_ABT_OFF            16
  83 #define ENT_INT_SRC_MSK1                0x1c4
  84 #define ENT_INT_SRC_MSK2                0x1c8
  85 #define ENT_INT_SRC_MSK3                0x1cc
  86 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF  31
  87 #define CHNL_PHYUPDOWN_INT_MSK          0x1d0
  88 #define CHNL_ENT_INT_MSK                        0x1d4
  89 #define HGC_COM_INT_MSK                         0x1d8
  90 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK  (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
  91 #define SAS_ECC_INTR                    0x1e8
  92 #define SAS_ECC_INTR_MSK                0x1ec
  93 #define HGC_ERR_STAT_EN                 0x238
  94 #define CQE_SEND_CNT                    0x248
  95 #define DLVRY_Q_0_BASE_ADDR_LO          0x260
  96 #define DLVRY_Q_0_BASE_ADDR_HI          0x264
  97 #define DLVRY_Q_0_DEPTH                 0x268
  98 #define DLVRY_Q_0_WR_PTR                0x26c
  99 #define DLVRY_Q_0_RD_PTR                0x270
 100 #define HYPER_STREAM_ID_EN_CFG          0xc80
 101 #define OQ0_INT_SRC_MSK                 0xc90
 102 #define COMPL_Q_0_BASE_ADDR_LO          0x4e0
 103 #define COMPL_Q_0_BASE_ADDR_HI          0x4e4
 104 #define COMPL_Q_0_DEPTH                 0x4e8
 105 #define COMPL_Q_0_WR_PTR                0x4ec
 106 #define COMPL_Q_0_RD_PTR                0x4f0
 107 #define AWQOS_AWCACHE_CFG       0xc84
 108 #define ARQOS_ARCACHE_CFG       0xc88
 109 #define HILINK_ERR_DFX          0xe04
 110 #define SAS_GPIO_CFG_0          0x1000
 111 #define SAS_GPIO_CFG_1          0x1004
 112 #define SAS_GPIO_TX_0_1 0x1040
 113 #define SAS_CFG_DRIVE_VLD       0x1070
 114
 115 /* phy registers requiring init */
 116 #define PORT_BASE                       (0x2000)
 117 #define PHY_CFG                         (PORT_BASE + 0x0)
 118 #define HARD_PHY_LINKRATE               (PORT_BASE + 0x4)
 119 #define PHY_CFG_ENA_OFF                 0
 120 #define PHY_CFG_ENA_MSK                 (0x1 << PHY_CFG_ENA_OFF)
 121 #define PHY_CFG_DC_OPT_OFF              2
 122 #define PHY_CFG_DC_OPT_MSK              (0x1 << PHY_CFG_DC_OPT_OFF)
 123 #define PHY_CFG_PHY_RST_OFF             3
 124 #define PHY_CFG_PHY_RST_MSK             (0x1 << PHY_CFG_PHY_RST_OFF)
 125 #define PROG_PHY_LINK_RATE              (PORT_BASE + 0x8)
 126 #define PHY_CTRL                        (PORT_BASE + 0x14)
 127 #define PHY_CTRL_RESET_OFF              0
 128 #define PHY_CTRL_RESET_MSK              (0x1 << PHY_CTRL_RESET_OFF)
 129 #define SL_CFG                          (PORT_BASE + 0x84)
 130 #define AIP_LIMIT                       (PORT_BASE + 0x90)
 131 #define SL_CONTROL                      (PORT_BASE + 0x94)
 132 #define SL_CONTROL_NOTIFY_EN_OFF        0
 133 #define SL_CONTROL_NOTIFY_EN_MSK        (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
 134 #define SL_CTA_OFF              17
 135 #define SL_CTA_MSK              (0x1 << SL_CTA_OFF)
 136 #define RX_PRIMS_STATUS                 (PORT_BASE + 0x98)
 137 #define RX_BCAST_CHG_OFF                1
 138 #define RX_BCAST_CHG_MSK                (0x1 << RX_BCAST_CHG_OFF)
 139 #define TX_ID_DWORD0                    (PORT_BASE + 0x9c)
 140 #define TX_ID_DWORD1                    (PORT_BASE + 0xa0)
 141 #define TX_ID_DWORD2                    (PORT_BASE + 0xa4)
 142 #define TX_ID_DWORD3                    (PORT_BASE + 0xa8)
 143 #define TX_ID_DWORD4                    (PORT_BASE + 0xaC)
 144 #define TX_ID_DWORD5                    (PORT_BASE + 0xb0)
 145 #define TX_ID_DWORD6                    (PORT_BASE + 0xb4)
 146 #define TXID_AUTO                               (PORT_BASE + 0xb8)
 147 #define CT3_OFF         1
 148 #define CT3_MSK         (0x1 << CT3_OFF)
 149 #define TX_HARDRST_OFF          2
 150 #define TX_HARDRST_MSK          (0x1 << TX_HARDRST_OFF)
 151 #define RX_IDAF_DWORD0                  (PORT_BASE + 0xc4)
 152 #define RXOP_CHECK_CFG_H                (PORT_BASE + 0xfc)
 153 #define STP_LINK_TIMER                  (PORT_BASE + 0x120)
 154 #define STP_LINK_TIMEOUT_STATE          (PORT_BASE + 0x124)
 155 #define CON_CFG_DRIVER                  (PORT_BASE + 0x130)
 156 #define SAS_SSP_CON_TIMER_CFG           (PORT_BASE + 0x134)
 157 #define SAS_SMP_CON_TIMER_CFG           (PORT_BASE + 0x138)
 158 #define SAS_STP_CON_TIMER_CFG           (PORT_BASE + 0x13c)
 159 #define CHL_INT0                        (PORT_BASE + 0x1b4)
 160 #define CHL_INT0_HOTPLUG_TOUT_OFF       0
 161 #define CHL_INT0_HOTPLUG_TOUT_MSK       (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
 162 #define CHL_INT0_SL_RX_BCST_ACK_OFF     1
 163 #define CHL_INT0_SL_RX_BCST_ACK_MSK     (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
 164 #define CHL_INT0_SL_PHY_ENABLE_OFF      2
 165 #define CHL_INT0_SL_PHY_ENABLE_MSK      (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
 166 #define CHL_INT0_NOT_RDY_OFF            4
 167 #define CHL_INT0_NOT_RDY_MSK            (0x1 << CHL_INT0_NOT_RDY_OFF)
 168 #define CHL_INT0_PHY_RDY_OFF            5
 169 #define CHL_INT0_PHY_RDY_MSK            (0x1 << CHL_INT0_PHY_RDY_OFF)
 170 #define CHL_INT1                        (PORT_BASE + 0x1b8)
 171 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF    15
 172 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
 173 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF    17
 174 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
 175 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
 176 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
 177 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
 178 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
 179 #define CHL_INT2                        (PORT_BASE + 0x1bc)
 180 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF  0
 181 #define CHL_INT2_RX_INVLD_DW_OFF        30
 182 #define CHL_INT2_STP_LINK_TIMEOUT_OFF   31
 183 #define CHL_INT0_MSK                    (PORT_BASE + 0x1c0)
 184 #define CHL_INT1_MSK                    (PORT_BASE + 0x1c4)
 185 #define CHL_INT2_MSK                    (PORT_BASE + 0x1c8)
 186 #define CHL_INT_COAL_EN                 (PORT_BASE + 0x1d0)
 187 #define SAS_RX_TRAIN_TIMER              (PORT_BASE + 0x2a4)
 188 #define PHY_CTRL_RDY_MSK                (PORT_BASE + 0x2b0)
 189 #define PHYCTRL_NOT_RDY_MSK             (PORT_BASE + 0x2b4)
 190 #define PHYCTRL_DWS_RESET_MSK           (PORT_BASE + 0x2b8)
 191 #define PHYCTRL_PHY_ENA_MSK             (PORT_BASE + 0x2bc)
 192 #define SL_RX_BCAST_CHK_MSK             (PORT_BASE + 0x2c0)
 193 #define PHYCTRL_OOB_RESTART_MSK         (PORT_BASE + 0x2c4)
 194 #define DMA_TX_STATUS                   (PORT_BASE + 0x2d0)
 195 #define DMA_TX_STATUS_BUSY_OFF          0
 196 #define DMA_TX_STATUS_BUSY_MSK          (0x1 << DMA_TX_STATUS_BUSY_OFF)
 197 #define DMA_RX_STATUS                   (PORT_BASE + 0x2e8)
 198 #define DMA_RX_STATUS_BUSY_OFF          0
 199 #define DMA_RX_STATUS_BUSY_MSK          (0x1 << DMA_RX_STATUS_BUSY_OFF)
 200
 201 #define COARSETUNE_TIME                 (PORT_BASE + 0x304)
 202 #define ERR_CNT_DWS_LOST                (PORT_BASE + 0x380)
 203 #define ERR_CNT_RESET_PROB              (PORT_BASE + 0x384)
 204 #define ERR_CNT_INVLD_DW                (PORT_BASE + 0x390)
 205 #define ERR_CNT_DISP_ERR                (PORT_BASE + 0x398)
 206
 207 #define DEFAULT_ITCT_HW         2048 /* reset value, not reprogrammed */
 208 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
 209 #error Max ITCT exceeded
 210 #endif
 211
 212 #define AXI_MASTER_CFG_BASE             (0x5000)
 213 #define AM_CTRL_GLOBAL                  (0x0)
 214 #define AM_CTRL_SHUTDOWN_REQ_OFF        0
 215 #define AM_CTRL_SHUTDOWN_REQ_MSK        (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF)
 216 #define AM_CURR_TRANS_RETURN    (0x150)
 217
 218 #define AM_CFG_MAX_TRANS                (0x5010)
 219 #define AM_CFG_SINGLE_PORT_MAX_TRANS    (0x5014)
 220 #define AXI_CFG                                 (0x5100)
 221 #define AM_ROB_ECC_ERR_ADDR             (0x510c)
 222 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF  0
 223 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK  (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF)
 224 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF  8
 225 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK  (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF)
 226
 227 /* RAS registers need init */
 228 #define RAS_BASE                (0x6000)
 229 #define SAS_RAS_INTR0                   (RAS_BASE)
 230 #define SAS_RAS_INTR1                   (RAS_BASE + 0x04)
 231 #define SAS_RAS_INTR0_MASK              (RAS_BASE + 0x08)
 232 #define SAS_RAS_INTR1_MASK              (RAS_BASE + 0x0c)
 233 #define CFG_SAS_RAS_INTR_MASK           (RAS_BASE + 0x1c)
 234 #define SAS_RAS_INTR2                   (RAS_BASE + 0x20)
 235 #define SAS_RAS_INTR2_MASK              (RAS_BASE + 0x24)
 236
 237 /* HW dma structures */
 238 /* Delivery queue header */
 239 /* dw0 */
 240 #define CMD_HDR_ABORT_FLAG_OFF          0
 241 #define CMD_HDR_ABORT_FLAG_MSK          (0x3 << CMD_HDR_ABORT_FLAG_OFF)
 242 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF   2
 243 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK   (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
 244 #define CMD_HDR_RESP_REPORT_OFF         5
 245 #define CMD_HDR_RESP_REPORT_MSK         (0x1 << CMD_HDR_RESP_REPORT_OFF)
 246 #define CMD_HDR_TLR_CTRL_OFF            6
 247 #define CMD_HDR_TLR_CTRL_MSK            (0x3 << CMD_HDR_TLR_CTRL_OFF)
 248 #define CMD_HDR_PORT_OFF                18
 249 #define CMD_HDR_PORT_MSK                (0xf << CMD_HDR_PORT_OFF)
 250 #define CMD_HDR_PRIORITY_OFF            27
 251 #define CMD_HDR_PRIORITY_MSK            (0x1 << CMD_HDR_PRIORITY_OFF)
 252 #define CMD_HDR_CMD_OFF                 29
 253 #define CMD_HDR_CMD_MSK                 (0x7 << CMD_HDR_CMD_OFF)
 254 /* dw1 */
 255 #define CMD_HDR_UNCON_CMD_OFF   3
 256 #define CMD_HDR_DIR_OFF                 5
 257 #define CMD_HDR_DIR_MSK                 (0x3 << CMD_HDR_DIR_OFF)
 258 #define CMD_HDR_RESET_OFF               7
 259 #define CMD_HDR_RESET_MSK               (0x1 << CMD_HDR_RESET_OFF)
 260 #define CMD_HDR_VDTL_OFF                10
 261 #define CMD_HDR_VDTL_MSK                (0x1 << CMD_HDR_VDTL_OFF)
 262 #define CMD_HDR_FRAME_TYPE_OFF          11
 263 #define CMD_HDR_FRAME_TYPE_MSK          (0x1f << CMD_HDR_FRAME_TYPE_OFF)
 264 #define CMD_HDR_DEV_ID_OFF              16
 265 #define CMD_HDR_DEV_ID_MSK              (0xffff << CMD_HDR_DEV_ID_OFF)
 266 /* dw2 */
 267 #define CMD_HDR_CFL_OFF                 0
 268 #define CMD_HDR_CFL_MSK                 (0x1ff << CMD_HDR_CFL_OFF)
 269 #define CMD_HDR_NCQ_TAG_OFF             10
 270 #define CMD_HDR_NCQ_TAG_MSK             (0x1f << CMD_HDR_NCQ_TAG_OFF)
 271 #define CMD_HDR_MRFL_OFF                15
 272 #define CMD_HDR_MRFL_MSK                (0x1ff << CMD_HDR_MRFL_OFF)
 273 #define CMD_HDR_SG_MOD_OFF              24
 274 #define CMD_HDR_SG_MOD_MSK              (0x3 << CMD_HDR_SG_MOD_OFF)
 275 /* dw3 */
 276 #define CMD_HDR_IPTT_OFF                0
 277 #define CMD_HDR_IPTT_MSK                (0xffff << CMD_HDR_IPTT_OFF)
 278 /* dw6 */
 279 #define CMD_HDR_DIF_SGL_LEN_OFF         0
 280 #define CMD_HDR_DIF_SGL_LEN_MSK         (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
 281 #define CMD_HDR_DATA_SGL_LEN_OFF        16
 282 #define CMD_HDR_DATA_SGL_LEN_MSK        (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
 283 /* dw7 */
 284 #define CMD_HDR_ADDR_MODE_SEL_OFF               15
 285 #define CMD_HDR_ADDR_MODE_SEL_MSK               (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
 286 #define CMD_HDR_ABORT_IPTT_OFF          16
 287 #define CMD_HDR_ABORT_IPTT_MSK          (0xffff << CMD_HDR_ABORT_IPTT_OFF)
 288
 289 /* Completion header */
 290 /* dw0 */
 291 #define CMPLT_HDR_CMPLT_OFF             0
 292 #define CMPLT_HDR_CMPLT_MSK             (0x3 << CMPLT_HDR_CMPLT_OFF)
 293 #define CMPLT_HDR_ERROR_PHASE_OFF   2
 294 #define CMPLT_HDR_ERROR_PHASE_MSK   (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
 295 #define CMPLT_HDR_RSPNS_XFRD_OFF        10
 296 #define CMPLT_HDR_RSPNS_XFRD_MSK        (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
 297 #define CMPLT_HDR_ERX_OFF               12
 298 #define CMPLT_HDR_ERX_MSK               (0x1 << CMPLT_HDR_ERX_OFF)
 299 #define CMPLT_HDR_ABORT_STAT_OFF        13
 300 #define CMPLT_HDR_ABORT_STAT_MSK        (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
 301 /* abort_stat */
 302 #define STAT_IO_NOT_VALID               0x1
 303 #define STAT_IO_NO_DEVICE               0x2
 304 #define STAT_IO_COMPLETE                0x3
 305 #define STAT_IO_ABORTED                 0x4
 306 /* dw1 */
 307 #define CMPLT_HDR_IPTT_OFF              0
 308 #define CMPLT_HDR_IPTT_MSK              (0xffff << CMPLT_HDR_IPTT_OFF)
 309 #define CMPLT_HDR_DEV_ID_OFF            16
 310 #define CMPLT_HDR_DEV_ID_MSK            (0xffff << CMPLT_HDR_DEV_ID_OFF)
 311 /* dw3 */
 312 #define CMPLT_HDR_IO_IN_TARGET_OFF      17
 313 #define CMPLT_HDR_IO_IN_TARGET_MSK      (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
 314
 315 /* ITCT header */
 316 /* qw0 */
 317 #define ITCT_HDR_DEV_TYPE_OFF           0
 318 #define ITCT_HDR_DEV_TYPE_MSK           (0x3 << ITCT_HDR_DEV_TYPE_OFF)
 319 #define ITCT_HDR_VALID_OFF              2
 320 #define ITCT_HDR_VALID_MSK              (0x1 << ITCT_HDR_VALID_OFF)
 321 #define ITCT_HDR_MCR_OFF                5
 322 #define ITCT_HDR_MCR_MSK                (0xf << ITCT_HDR_MCR_OFF)
 323 #define ITCT_HDR_VLN_OFF                9
 324 #define ITCT_HDR_VLN_MSK                (0xf << ITCT_HDR_VLN_OFF)
 325 #define ITCT_HDR_SMP_TIMEOUT_OFF        16
 326 #define ITCT_HDR_AWT_CONTINUE_OFF       25
 327 #define ITCT_HDR_PORT_ID_OFF            28
 328 #define ITCT_HDR_PORT_ID_MSK            (0xf << ITCT_HDR_PORT_ID_OFF)
 329 /* qw2 */
 330 #define ITCT_HDR_INLT_OFF               0
 331 #define ITCT_HDR_INLT_MSK               (0xffffULL << ITCT_HDR_INLT_OFF)
 332 #define ITCT_HDR_RTOLT_OFF              48
 333 #define ITCT_HDR_RTOLT_MSK              (0xffffULL << ITCT_HDR_RTOLT_OFF)
 334
 335 struct hisi_sas_complete_v3_hdr {
 336         __le32 dw0;
 337         __le32 dw1;
 338         __le32 act;
 339         __le32 dw3;
 340 };
 341
 342 struct hisi_sas_err_record_v3 {
 343         /* dw0 */
 344         __le32 trans_tx_fail_type;
 345
 346         /* dw1 */
 347         __le32 trans_rx_fail_type;
 348
 349         /* dw2 */
 350         __le16 dma_tx_err_type;
 351         __le16 sipc_rx_err_type;
 352
 353         /* dw3 */
 354         __le32 dma_rx_err_type;
 355 };
 356
 357 #define RX_DATA_LEN_UNDERFLOW_OFF       6
 358 #define RX_DATA_LEN_UNDERFLOW_MSK       (1 << RX_DATA_LEN_UNDERFLOW_OFF)
 359
 360 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
 361 #define HISI_SAS_MSI_COUNT_V3_HW 32
 362
 363 #define DIR_NO_DATA 0
 364 #define DIR_TO_INI 1
 365 #define DIR_TO_DEVICE 2
 366 #define DIR_RESERVED 3
 367
 368 #define FIS_CMD_IS_UNCONSTRAINED(fis) \
 369         ((fis.command == ATA_CMD_READ_LOG_EXT) || \
 370         (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
 371         ((fis.command == ATA_CMD_DEV_RESET) && \
 372         ((fis.control & ATA_SRST) != 0)))
 373
 374 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
 375 {
 376         void __iomem *regs = hisi_hba->regs + off;
 377
 378         return readl(regs);
 379 }
 380
 381 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
 382 {
 383         void __iomem *regs = hisi_hba->regs + off;
 384
 385         return readl_relaxed(regs);
 386 }
 387
 388 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
 389 {
 390         void __iomem *regs = hisi_hba->regs + off;
 391
 392         writel(val, regs);
 393 }
 394
 395 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
 396                                  u32 off, u32 val)
 397 {
 398         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 399
 400         writel(val, regs);
 401 }
 402
 403 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
 404                                       int phy_no, u32 off)
 405 {
 406         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 407
 408         return readl(regs);
 409 }
 410
 411 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us,          \
 412                                      timeout_us)                        \
 413 ({                                                                      \
 414         void __iomem *regs = hisi_hba->regs + off;                      \
 415         readl_poll_timeout(regs, val, cond, delay_us, timeout_us);      \
 416 })
 417
 418 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us,   \
 419                                             timeout_us)                 \
 420 ({                                                                      \
 421         void __iomem *regs = hisi_hba->regs + off;                      \
 422         readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\
 423 })
 424
 425 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
 426 {
 427         struct pci_dev *pdev = hisi_hba->pci_dev;
 428         int i;
 429
 430         /* Global registers init */
 431         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
 432                          (u32)((1ULL << hisi_hba->queue_count) - 1));
 433         hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
 434         hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
 435         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
 436         hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
 437         hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
 438         hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
 439         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
 440         hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
 441         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
 442         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
 443         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
 444         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
 445         if (pdev->revision >= 0x21)
 446                 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffff7aff);
 447         else
 448                 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff);
 449         hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
 450         hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
 451         hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
 452         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0);
 453         hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
 454         hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
 455         for (i = 0; i < hisi_hba->queue_count; i++)
 456                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
 457
 458         hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
 459
 460         for (i = 0; i < hisi_hba->n_phy; i++) {
 461                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
 462                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
 463                 u32 prog_phy_link_rate = 0x800;
 464
 465                 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
 466                                 SAS_LINK_RATE_1_5_GBPS)) {
 467                         prog_phy_link_rate = 0x855;
 468                 } else {
 469                         enum sas_linkrate max = sas_phy->phy->maximum_linkrate;
 470
 471                         prog_phy_link_rate =
 472                                 hisi_sas_get_prog_phy_linkrate_mask(max) |
 473                                 0x800;
 474                 }
 475                 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
 476                         prog_phy_link_rate);
 477                 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
 478                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
 479                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
 480                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
 481                 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
 482                 if (pdev->revision >= 0x21)
 483                         hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK,
 484                                         0xffffffff);
 485                 else
 486                         hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK,
 487                                         0xff87ffff);
 488                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
 489                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
 490                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
 491                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
 492                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
 493                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
 494                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
 495                 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
 496                 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01);
 497
 498                 /* used for 12G negotiate */
 499                 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
 500                 hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff);
 501         }
 502
 503         for (i = 0; i < hisi_hba->queue_count; i++) {
 504                 /* Delivery queue */
 505                 hisi_sas_write32(hisi_hba,
 506                                  DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
 507                                  upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
 508
 509                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
 510                                  lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
 511
 512                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
 513                                  HISI_SAS_QUEUE_SLOTS);
 514
 515                 /* Completion queue */
 516                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
 517                                  upper_32_bits(hisi_hba->complete_hdr_dma[i]));
 518
 519                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
 520                                  lower_32_bits(hisi_hba->complete_hdr_dma[i]));
 521
 522                 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
 523                                  HISI_SAS_QUEUE_SLOTS);
 524         }
 525
 526         /* itct */
 527         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
 528                          lower_32_bits(hisi_hba->itct_dma));
 529
 530         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
 531                          upper_32_bits(hisi_hba->itct_dma));
 532
 533         /* iost */
 534         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
 535                          lower_32_bits(hisi_hba->iost_dma));
 536
 537         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
 538                          upper_32_bits(hisi_hba->iost_dma));
 539
 540         /* breakpoint */
 541         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
 542                          lower_32_bits(hisi_hba->breakpoint_dma));
 543
 544         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
 545                          upper_32_bits(hisi_hba->breakpoint_dma));
 546
 547         /* SATA broken msg */
 548         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
 549                          lower_32_bits(hisi_hba->sata_breakpoint_dma));
 550
 551         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
 552                          upper_32_bits(hisi_hba->sata_breakpoint_dma));
 553
 554         /* SATA initial fis */
 555         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
 556                          lower_32_bits(hisi_hba->initial_fis_dma));
 557
 558         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
 559                          upper_32_bits(hisi_hba->initial_fis_dma));
 560
 561         /* RAS registers init */
 562         hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
 563         hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
 564         hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0);
 565         hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0);
 566
 567         /* LED registers init */
 568         hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff);
 569         hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080);
 570         hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080);
 571         /* Configure blink generator rate A to 1Hz and B to 4Hz */
 572         hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700);
 573         hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000);
 574 }
 575
 576 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 577 {
 578         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 579
 580         cfg &= ~PHY_CFG_DC_OPT_MSK;
 581         cfg |= 1 << PHY_CFG_DC_OPT_OFF;
 582         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 583 }
 584
 585 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 586 {
 587         struct sas_identify_frame identify_frame;
 588         u32 *identify_buffer;
 589
 590         memset(&identify_frame, 0, sizeof(identify_frame));
 591         identify_frame.dev_type = SAS_END_DEVICE;
 592         identify_frame.frame_type = 0;
 593         identify_frame._un1 = 1;
 594         identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
 595         identify_frame.target_bits = SAS_PROTOCOL_NONE;
 596         memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 597         memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 598         identify_frame.phy_id = phy_no;
 599         identify_buffer = (u32 *)(&identify_frame);
 600
 601         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
 602                         __swab32(identify_buffer[0]));
 603         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
 604                         __swab32(identify_buffer[1]));
 605         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
 606                         __swab32(identify_buffer[2]));
 607         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
 608                         __swab32(identify_buffer[3]));
 609         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
 610                         __swab32(identify_buffer[4]));
 611         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
 612                         __swab32(identify_buffer[5]));
 613 }
 614
 615 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
 616                              struct hisi_sas_device *sas_dev)
 617 {
 618         struct domain_device *device = sas_dev->sas_device;
 619         struct device *dev = hisi_hba->dev;
 620         u64 qw0, device_id = sas_dev->device_id;
 621         struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
 622         struct domain_device *parent_dev = device->parent;
 623         struct asd_sas_port *sas_port = device->port;
 624         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
 625
 626         memset(itct, 0, sizeof(*itct));
 627
 628         /* qw0 */
 629         qw0 = 0;
 630         switch (sas_dev->dev_type) {
 631         case SAS_END_DEVICE:
 632         case SAS_EDGE_EXPANDER_DEVICE:
 633         case SAS_FANOUT_EXPANDER_DEVICE:
 634                 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
 635                 break;
 636         case SAS_SATA_DEV:
 637         case SAS_SATA_PENDING:
 638                 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
 639                         qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
 640                 else
 641                         qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
 642                 break;
 643         default:
 644                 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
 645                          sas_dev->dev_type);
 646         }
 647
 648         qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
 649                 (device->linkrate << ITCT_HDR_MCR_OFF) |
 650                 (1 << ITCT_HDR_VLN_OFF) |
 651                 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
 652                 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
 653                 (port->id << ITCT_HDR_PORT_ID_OFF));
 654         itct->qw0 = cpu_to_le64(qw0);
 655
 656         /* qw1 */
 657         memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
 658         itct->sas_addr = __swab64(itct->sas_addr);
 659
 660         /* qw2 */
 661         if (!dev_is_sata(device))
 662                 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
 663                                         (0x1ULL << ITCT_HDR_RTOLT_OFF));
 664 }
 665
 666 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba,
 667                               struct hisi_sas_device *sas_dev)
 668 {
 669         DECLARE_COMPLETION_ONSTACK(completion);
 670         u64 dev_id = sas_dev->device_id;
 671         struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
 672         u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
 673
 674         sas_dev->completion = &completion;
 675
 676         /* clear the itct interrupt state */
 677         if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
 678                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
 679                                  ENT_INT_SRC3_ITC_INT_MSK);
 680
 681         /* clear the itct table*/
 682         reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
 683         hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
 684
 685         wait_for_completion(sas_dev->completion);
 686         memset(itct, 0, sizeof(struct hisi_sas_itct));
 687 }
 688
 689 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
 690                                 struct domain_device *device)
 691 {
 692         struct hisi_sas_slot *slot, *slot2;
 693         struct hisi_sas_device *sas_dev = device->lldd_dev;
 694         u32 cfg_abt_set_query_iptt;
 695
 696         cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
 697                 CFG_ABT_SET_QUERY_IPTT);
 698         list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
 699                 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
 700                 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
 701                         (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
 702                 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
 703                         cfg_abt_set_query_iptt);
 704         }
 705         cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
 706         hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
 707                 cfg_abt_set_query_iptt);
 708         hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
 709                                         1 << CFG_ABT_SET_IPTT_DONE_OFF);
 710 }
 711
 712 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
 713 {
 714         struct device *dev = hisi_hba->dev;
 715         int ret;
 716         u32 val;
 717
 718         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
 719
 720         /* Disable all of the PHYs */
 721         hisi_sas_stop_phys(hisi_hba);
 722         udelay(50);
 723
 724         /* Ensure axi bus idle */
 725         ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
 726                                            20000, 1000000);
 727         if (ret) {
 728                 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
 729                 return -EIO;
 730         }
 731
 732         if (ACPI_HANDLE(dev)) {
 733                 acpi_status s;
 734
 735                 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
 736                 if (ACPI_FAILURE(s)) {
 737                         dev_err(dev, "Reset failed\n");
 738                         return -EIO;
 739                 }
 740         } else {
 741                 dev_err(dev, "no reset method!\n");
 742                 return -EINVAL;
 743         }
 744
 745         return 0;
 746 }
 747
 748 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
 749 {
 750         struct device *dev = hisi_hba->dev;
 751         int rc;
 752
 753         rc = reset_hw_v3_hw(hisi_hba);
 754         if (rc) {
 755                 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
 756                 return rc;
 757         }
 758
 759         msleep(100);
 760         init_reg_v3_hw(hisi_hba);
 761
 762         return 0;
 763 }
 764
 765 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 766 {
 767         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 768
 769         cfg |= PHY_CFG_ENA_MSK;
 770         cfg &= ~PHY_CFG_PHY_RST_MSK;
 771         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 772 }
 773
 774 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 775 {
 776         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 777         u32 state;
 778
 779         cfg &= ~PHY_CFG_ENA_MSK;
 780         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 781
 782         mdelay(50);
 783
 784         state = hisi_sas_read32(hisi_hba, PHY_STATE);
 785         if (state & BIT(phy_no)) {
 786                 cfg |= PHY_CFG_PHY_RST_MSK;
 787                 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 788         }
 789 }
 790
 791 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 792 {
 793         config_id_frame_v3_hw(hisi_hba, phy_no);
 794         config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
 795         enable_phy_v3_hw(hisi_hba, phy_no);
 796 }
 797
 798 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 799 {
 800         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
 801         u32 txid_auto;
 802
 803         disable_phy_v3_hw(hisi_hba, phy_no);
 804         if (phy->identify.device_type == SAS_END_DEVICE) {
 805                 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
 806                 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
 807                                         txid_auto | TX_HARDRST_MSK);
 808         }
 809         msleep(100);
 810         start_phy_v3_hw(hisi_hba, phy_no);
 811 }
 812
 813 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
 814 {
 815         return SAS_LINK_RATE_12_0_GBPS;
 816 }
 817
 818 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
 819 {
 820         int i;
 821
 822         for (i = 0; i < hisi_hba->n_phy; i++) {
 823                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
 824                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
 825
 826                 if (!sas_phy->phy->enabled)
 827                         continue;
 828
 829                 start_phy_v3_hw(hisi_hba, i);
 830         }
 831 }
 832
 833 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 834 {
 835         u32 sl_control;
 836
 837         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 838         sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
 839         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 840         msleep(1);
 841         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 842         sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
 843         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 844 }
 845
 846 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
 847 {
 848         int i, bitmap = 0;
 849         u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
 850         u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
 851
 852         for (i = 0; i < hisi_hba->n_phy; i++)
 853                 if (phy_state & BIT(i))
 854                         if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
 855                                 bitmap |= BIT(i);
 856
 857         return bitmap;
 858 }
 859
 860 /**
 861  * The callpath to this function and upto writing the write
 862  * queue pointer should be safe from interruption.
 863  */
 864 static int
 865 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
 866 {
 867         struct device *dev = hisi_hba->dev;
 868         int queue = dq->id;
 869         u32 r, w;
 870
 871         w = dq->wr_point;
 872         r = hisi_sas_read32_relaxed(hisi_hba,
 873                                 DLVRY_Q_0_RD_PTR + (queue * 0x14));
 874         if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
 875                 dev_warn(dev, "full queue=%d r=%d w=%d\n",
 876                                 queue, r, w);
 877                 return -EAGAIN;
 878         }
 879
 880         dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS;
 881
 882         return w;
 883 }
 884
 885 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
 886 {
 887         struct hisi_hba *hisi_hba = dq->hisi_hba;
 888         struct hisi_sas_slot *s, *s1, *s2 = NULL;
 889         struct list_head *dq_list;
 890         int dlvry_queue = dq->id;
 891         int wp;
 892
 893         dq_list = &dq->list;
 894         list_for_each_entry_safe(s, s1, &dq->list, delivery) {
 895                 if (!s->ready)
 896                         break;
 897                 s2 = s;
 898                 list_del(&s->delivery);
 899         }
 900
 901         if (!s2)
 902                 return;
 903
 904         /*
 905          * Ensure that memories for slots built on other CPUs is observed.
 906          */
 907         smp_rmb();
 908         wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
 909
 910         hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
 911 }
 912
 913 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
 914                               struct hisi_sas_slot *slot,
 915                               struct hisi_sas_cmd_hdr *hdr,
 916                               struct scatterlist *scatter,
 917                               int n_elem)
 918 {
 919         struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
 920         struct scatterlist *sg;
 921         int i;
 922
 923         for_each_sg(scatter, sg, n_elem, i) {
 924                 struct hisi_sas_sge *entry = &sge_page->sge[i];
 925
 926                 entry->addr = cpu_to_le64(sg_dma_address(sg));
 927                 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
 928                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
 929                 entry->data_off = 0;
 930         }
 931
 932         hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
 933
 934         hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
 935 }
 936
 937 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
 938                           struct hisi_sas_slot *slot)
 939 {
 940         struct sas_task *task = slot->task;
 941         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
 942         struct domain_device *device = task->dev;
 943         struct hisi_sas_device *sas_dev = device->lldd_dev;
 944         struct hisi_sas_port *port = slot->port;
 945         struct sas_ssp_task *ssp_task = &task->ssp_task;
 946         struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
 947         struct hisi_sas_tmf_task *tmf = slot->tmf;
 948         int has_data = 0, priority = !!tmf;
 949         u8 *buf_cmd;
 950         u32 dw1 = 0, dw2 = 0;
 951
 952         hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
 953                                (2 << CMD_HDR_TLR_CTRL_OFF) |
 954                                (port->id << CMD_HDR_PORT_OFF) |
 955                                (priority << CMD_HDR_PRIORITY_OFF) |
 956                                (1 << CMD_HDR_CMD_OFF)); /* ssp */
 957
 958         dw1 = 1 << CMD_HDR_VDTL_OFF;
 959         if (tmf) {
 960                 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
 961                 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
 962         } else {
 963                 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
 964                 switch (scsi_cmnd->sc_data_direction) {
 965                 case DMA_TO_DEVICE:
 966                         has_data = 1;
 967                         dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
 968                         break;
 969                 case DMA_FROM_DEVICE:
 970                         has_data = 1;
 971                         dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
 972                         break;
 973                 default:
 974                         dw1 &= ~CMD_HDR_DIR_MSK;
 975                 }
 976         }
 977
 978         /* map itct entry */
 979         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
 980         hdr->dw1 = cpu_to_le32(dw1);
 981
 982         dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
 983               + 3) / 4) << CMD_HDR_CFL_OFF) |
 984               ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
 985               (2 << CMD_HDR_SG_MOD_OFF);
 986         hdr->dw2 = cpu_to_le32(dw2);
 987         hdr->transfer_tags = cpu_to_le32(slot->idx);
 988
 989         if (has_data)
 990                 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
 991                                         slot->n_elem);
 992
 993         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
 994         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
 995         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
 996
 997         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
 998                 sizeof(struct ssp_frame_hdr);
 999
1000         memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1001         if (!tmf) {
1002                 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
1003                 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
1004         } else {
1005                 buf_cmd[10] = tmf->tmf;
1006                 switch (tmf->tmf) {
1007                 case TMF_ABORT_TASK:
1008                 case TMF_QUERY_TASK:
1009                         buf_cmd[12] =
1010                                 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1011                         buf_cmd[13] =
1012                                 tmf->tag_of_task_to_be_managed & 0xff;
1013                         break;
1014                 default:
1015                         break;
1016                 }
1017         }
1018 }
1019
1020 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
1021                           struct hisi_sas_slot *slot)
1022 {
1023         struct sas_task *task = slot->task;
1024         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1025         struct domain_device *device = task->dev;
1026         struct hisi_sas_port *port = slot->port;
1027         struct scatterlist *sg_req;
1028         struct hisi_sas_device *sas_dev = device->lldd_dev;
1029         dma_addr_t req_dma_addr;
1030         unsigned int req_len;
1031
1032         /* req */
1033         sg_req = &task->smp_task.smp_req;
1034         req_len = sg_dma_len(sg_req);
1035         req_dma_addr = sg_dma_address(sg_req);
1036
1037         /* create header */
1038         /* dw0 */
1039         hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1040                                (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1041                                (2 << CMD_HDR_CMD_OFF)); /* smp */
1042
1043         /* map itct entry */
1044         hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1045                                (1 << CMD_HDR_FRAME_TYPE_OFF) |
1046                                (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1047
1048         /* dw2 */
1049         hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1050                                (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1051                                CMD_HDR_MRFL_OFF));
1052
1053         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1054
1055         hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1056         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1057
1058 }
1059
1060 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1061                           struct hisi_sas_slot *slot)
1062 {
1063         struct sas_task *task = slot->task;
1064         struct domain_device *device = task->dev;
1065         struct domain_device *parent_dev = device->parent;
1066         struct hisi_sas_device *sas_dev = device->lldd_dev;
1067         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1068         struct asd_sas_port *sas_port = device->port;
1069         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1070         u8 *buf_cmd;
1071         int has_data = 0, hdr_tag = 0;
1072         u32 dw1 = 0, dw2 = 0;
1073
1074         hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1075         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1076                 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1077         else
1078                 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1079
1080         switch (task->data_dir) {
1081         case DMA_TO_DEVICE:
1082                 has_data = 1;
1083                 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1084                 break;
1085         case DMA_FROM_DEVICE:
1086                 has_data = 1;
1087                 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1088                 break;
1089         default:
1090                 dw1 &= ~CMD_HDR_DIR_MSK;
1091         }
1092
1093         if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1094                         (task->ata_task.fis.control & ATA_SRST))
1095                 dw1 |= 1 << CMD_HDR_RESET_OFF;
1096
1097         dw1 |= (hisi_sas_get_ata_protocol(
1098                 &task->ata_task.fis, task->data_dir))
1099                 << CMD_HDR_FRAME_TYPE_OFF;
1100         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1101
1102         if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
1103                 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1104
1105         hdr->dw1 = cpu_to_le32(dw1);
1106
1107         /* dw2 */
1108         if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
1109                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1110                 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1111         }
1112
1113         dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1114                         2 << CMD_HDR_SG_MOD_OFF;
1115         hdr->dw2 = cpu_to_le32(dw2);
1116
1117         /* dw3 */
1118         hdr->transfer_tags = cpu_to_le32(slot->idx);
1119
1120         if (has_data)
1121                 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1122                                         slot->n_elem);
1123
1124         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1125         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1126         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1127
1128         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1129
1130         if (likely(!task->ata_task.device_control_reg_update))
1131                 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1132         /* fill in command FIS */
1133         memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1134 }
1135
1136 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1137                 struct hisi_sas_slot *slot,
1138                 int device_id, int abort_flag, int tag_to_abort)
1139 {
1140         struct sas_task *task = slot->task;
1141         struct domain_device *dev = task->dev;
1142         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1143         struct hisi_sas_port *port = slot->port;
1144
1145         /* dw0 */
1146         hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
1147                                (port->id << CMD_HDR_PORT_OFF) |
1148                                    (dev_is_sata(dev)
1149                                         << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1150                                         (abort_flag
1151                                          << CMD_HDR_ABORT_FLAG_OFF));
1152
1153         /* dw1 */
1154         hdr->dw1 = cpu_to_le32(device_id
1155                         << CMD_HDR_DEV_ID_OFF);
1156
1157         /* dw7 */
1158         hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1159         hdr->transfer_tags = cpu_to_le32(slot->idx);
1160
1161 }
1162
1163 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1164 {
1165         int i, res;
1166         u32 context, port_id, link_rate;
1167         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1168         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1169         struct device *dev = hisi_hba->dev;
1170         unsigned long flags;
1171
1172         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1173
1174         port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1175         port_id = (port_id >> (4 * phy_no)) & 0xf;
1176         link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1177         link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1178
1179         if (port_id == 0xf) {
1180                 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1181                 res = IRQ_NONE;
1182                 goto end;
1183         }
1184         sas_phy->linkrate = link_rate;
1185         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1186
1187         /* Check for SATA dev */
1188         context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1189         if (context & (1 << phy_no)) {
1190                 struct hisi_sas_initial_fis *initial_fis;
1191                 struct dev_to_host_fis *fis;
1192                 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1193
1194                 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1195                 initial_fis = &hisi_hba->initial_fis[phy_no];
1196                 fis = &initial_fis->fis;
1197
1198                 /* check ERR bit of Status Register */
1199                 if (fis->status & ATA_ERR) {
1200                         dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n",
1201                                  phy_no, fis->status);
1202                         hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1203                         res = IRQ_NONE;
1204                         goto end;
1205                 }
1206
1207                 sas_phy->oob_mode = SATA_OOB_MODE;
1208                 attached_sas_addr[0] = 0x50;
1209                 attached_sas_addr[7] = phy_no;
1210                 memcpy(sas_phy->attached_sas_addr,
1211                        attached_sas_addr,
1212                        SAS_ADDR_SIZE);
1213                 memcpy(sas_phy->frame_rcvd, fis,
1214                        sizeof(struct dev_to_host_fis));
1215                 phy->phy_type |= PORT_TYPE_SATA;
1216                 phy->identify.device_type = SAS_SATA_DEV;
1217                 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1218                 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1219         } else {
1220                 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1221                 struct sas_identify_frame *id =
1222                         (struct sas_identify_frame *)frame_rcvd;
1223
1224                 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1225                 for (i = 0; i < 6; i++) {
1226                         u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1227                                                RX_IDAF_DWORD0 + (i * 4));
1228                         frame_rcvd[i] = __swab32(idaf);
1229                 }
1230                 sas_phy->oob_mode = SAS_OOB_MODE;
1231                 memcpy(sas_phy->attached_sas_addr,
1232                        &id->sas_addr,
1233                        SAS_ADDR_SIZE);
1234                 phy->phy_type |= PORT_TYPE_SAS;
1235                 phy->identify.device_type = id->dev_type;
1236                 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1237                 if (phy->identify.device_type == SAS_END_DEVICE)
1238                         phy->identify.target_port_protocols =
1239                                 SAS_PROTOCOL_SSP;
1240                 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1241                         phy->identify.target_port_protocols =
1242                                 SAS_PROTOCOL_SMP;
1243         }
1244
1245         phy->port_id = port_id;
1246         phy->phy_attached = 1;
1247         hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
1248         res = IRQ_HANDLED;
1249         spin_lock_irqsave(&phy->lock, flags);
1250         if (phy->reset_completion) {
1251                 phy->in_reset = 0;
1252                 complete(phy->reset_completion);
1253         }
1254         spin_unlock_irqrestore(&phy->lock, flags);
1255 end:
1256         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1257                              CHL_INT0_SL_PHY_ENABLE_MSK);
1258         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1259
1260         return res;
1261 }
1262
1263 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1264 {
1265         u32 phy_state, sl_ctrl, txid_auto;
1266         struct device *dev = hisi_hba->dev;
1267
1268         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1269
1270         phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1271         dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1272         hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1273
1274         sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1275         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1276                                                 sl_ctrl&(~SL_CTA_MSK));
1277
1278         txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1279         hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1280                                                 txid_auto | CT3_MSK);
1281
1282         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1283         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1284
1285         return IRQ_HANDLED;
1286 }
1287
1288 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1289 {
1290         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1291         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1292         struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1293         u32 bcast_status;
1294
1295         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1296         bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
1297         if ((bcast_status & RX_BCAST_CHG_MSK) &&
1298             !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
1299                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1300         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1301                              CHL_INT0_SL_RX_BCST_ACK_MSK);
1302         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1303
1304         return IRQ_HANDLED;
1305 }
1306
1307 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1308 {
1309         struct hisi_hba *hisi_hba = p;
1310         u32 irq_msk;
1311         int phy_no = 0;
1312         irqreturn_t res = IRQ_NONE;
1313
1314         irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1315                                 & 0x11111111;
1316         while (irq_msk) {
1317                 if (irq_msk  & 1) {
1318                         u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1319                                                             CHL_INT0);
1320                         u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1321                         int rdy = phy_state & (1 << phy_no);
1322
1323                         if (rdy) {
1324                                 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1325                                         /* phy up */
1326                                         if (phy_up_v3_hw(phy_no, hisi_hba)
1327                                                         == IRQ_HANDLED)
1328                                                 res = IRQ_HANDLED;
1329                                 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1330                                         /* phy bcast */
1331                                         if (phy_bcast_v3_hw(phy_no, hisi_hba)
1332                                                         == IRQ_HANDLED)
1333                                                 res = IRQ_HANDLED;
1334                         } else {
1335                                 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1336                                         /* phy down */
1337                                         if (phy_down_v3_hw(phy_no, hisi_hba)
1338                                                         == IRQ_HANDLED)
1339                                                 res = IRQ_HANDLED;
1340                         }
1341                 }
1342                 irq_msk >>= 4;
1343                 phy_no++;
1344         }
1345
1346         return res;
1347 }
1348
1349 static const struct hisi_sas_hw_error port_axi_error[] = {
1350         {
1351                 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1352                 .msg = "dma_tx_axi_wr_err",
1353         },
1354         {
1355                 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1356                 .msg = "dma_tx_axi_rd_err",
1357         },
1358         {
1359                 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1360                 .msg = "dma_rx_axi_wr_err",
1361         },
1362         {
1363                 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1364                 .msg = "dma_rx_axi_rd_err",
1365         },
1366 };
1367
1368 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1369 {
1370         u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1);
1371         u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK);
1372         struct device *dev = hisi_hba->dev;
1373         int i;
1374
1375         irq_value &= ~irq_msk;
1376         if (!irq_value)
1377                 return;
1378
1379         for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1380                 const struct hisi_sas_hw_error *error = &port_axi_error[i];
1381
1382                 if (!(irq_value & error->irq_msk))
1383                         continue;
1384
1385                 dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1386                         error->msg, phy_no, irq_value);
1387                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1388         }
1389
1390         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value);
1391 }
1392
1393 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1394 {
1395         u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
1396         u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1397         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1398         struct pci_dev *pci_dev = hisi_hba->pci_dev;
1399         struct device *dev = hisi_hba->dev;
1400
1401         irq_value &= ~irq_msk;
1402         if (!irq_value)
1403                 return;
1404
1405         if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1406                 dev_warn(dev, "phy%d identify timeout\n", phy_no);
1407                 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1408         }
1409
1410         if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1411                 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1412                                 STP_LINK_TIMEOUT_STATE);
1413
1414                 dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1415                          phy_no, reg_value);
1416                 if (reg_value & BIT(4))
1417                         hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1418         }
1419
1420         if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) &&
1421             (pci_dev->revision == 0x20)) {
1422                 u32 reg_value;
1423                 int rc;
1424
1425                 rc = hisi_sas_read32_poll_timeout_atomic(
1426                                 HILINK_ERR_DFX, reg_value,
1427                                 !((reg_value >> 8) & BIT(phy_no)),
1428                                 1000, 10000);
1429                 if (rc)
1430                         hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1431         }
1432
1433         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value);
1434 }
1435
1436 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1437 {
1438         struct hisi_hba *hisi_hba = p;
1439         u32 irq_msk;
1440         int phy_no = 0;
1441
1442         irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1443                                 & 0xeeeeeeee;
1444
1445         while (irq_msk) {
1446                 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1447                                                      CHL_INT0);
1448
1449                 if (irq_msk & (4 << (phy_no * 4)))
1450                         handle_chl_int1_v3_hw(hisi_hba, phy_no);
1451
1452                 if (irq_msk & (8 << (phy_no * 4)))
1453                         handle_chl_int2_v3_hw(hisi_hba, phy_no);
1454
1455                 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) {
1456                         hisi_sas_phy_write32(hisi_hba, phy_no,
1457                                         CHL_INT0, irq_value0
1458                                         & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1459                                         & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1460                                         & (~CHL_INT0_NOT_RDY_MSK));
1461                 }
1462                 irq_msk &= ~(0xe << (phy_no * 4));
1463                 phy_no++;
1464         }
1465
1466         return IRQ_HANDLED;
1467 }
1468
1469 static const struct hisi_sas_hw_error axi_error[] = {
1470         { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
1471         { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
1472         { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
1473         { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
1474         { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
1475         { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
1476         { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
1477         { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
1478         {},
1479 };
1480
1481 static const struct hisi_sas_hw_error fifo_error[] = {
1482         { .msk = BIT(8),  .msg = "CQE_WINFO_FIFO" },
1483         { .msk = BIT(9),  .msg = "CQE_MSG_FIFIO" },
1484         { .msk = BIT(10), .msg = "GETDQE_FIFO" },
1485         { .msk = BIT(11), .msg = "CMDP_FIFO" },
1486         { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
1487         {},
1488 };
1489
1490 static const struct hisi_sas_hw_error fatal_axi_error[] = {
1491         {
1492                 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
1493                 .msg = "write pointer and depth",
1494         },
1495         {
1496                 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
1497                 .msg = "iptt no match slot",
1498         },
1499         {
1500                 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
1501                 .msg = "read pointer and depth",
1502         },
1503         {
1504                 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
1505                 .reg = HGC_AXI_FIFO_ERR_INFO,
1506                 .sub = axi_error,
1507         },
1508         {
1509                 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
1510                 .reg = HGC_AXI_FIFO_ERR_INFO,
1511                 .sub = fifo_error,
1512         },
1513         {
1514                 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
1515                 .msg = "LM add/fetch list",
1516         },
1517         {
1518                 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
1519                 .msg = "SAS_HGC_ABT fetch LM list",
1520         },
1521 };
1522
1523 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
1524 {
1525         u32 irq_value, irq_msk;
1526         struct hisi_hba *hisi_hba = p;
1527         struct device *dev = hisi_hba->dev;
1528         int i;
1529
1530         irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1531         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
1532
1533         irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
1534         irq_value &= ~irq_msk;
1535
1536         for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
1537                 const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
1538
1539                 if (!(irq_value & error->irq_msk))
1540                         continue;
1541
1542                 if (error->sub) {
1543                         const struct hisi_sas_hw_error *sub = error->sub;
1544                         u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
1545
1546                         for (; sub->msk || sub->msg; sub++) {
1547                                 if (!(err_value & sub->msk))
1548                                         continue;
1549
1550                                 dev_err(dev, "%s error (0x%x) found!\n",
1551                                         sub->msg, irq_value);
1552                                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1553                         }
1554                 } else {
1555                         dev_err(dev, "%s error (0x%x) found!\n",
1556                                 error->msg, irq_value);
1557                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1558                 }
1559         }
1560
1561         if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
1562                 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
1563                 u32 dev_id = reg_val & ITCT_DEV_MSK;
1564                 struct hisi_sas_device *sas_dev =
1565                                 &hisi_hba->devices[dev_id];
1566
1567                 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
1568                 dev_dbg(dev, "clear ITCT ok\n");
1569                 complete(sas_dev->completion);
1570         }
1571
1572         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
1573         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
1574
1575         return IRQ_HANDLED;
1576 }
1577
1578 static void
1579 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1580                struct hisi_sas_slot *slot)
1581 {
1582         struct task_status_struct *ts = &task->task_status;
1583         struct hisi_sas_complete_v3_hdr *complete_queue =
1584                         hisi_hba->complete_hdr[slot->cmplt_queue];
1585         struct hisi_sas_complete_v3_hdr *complete_hdr =
1586                         &complete_queue[slot->cmplt_queue_slot];
1587         struct hisi_sas_err_record_v3 *record =
1588                         hisi_sas_status_buf_addr_mem(slot);
1589         u32 dma_rx_err_type = record->dma_rx_err_type;
1590         u32 trans_tx_fail_type = record->trans_tx_fail_type;
1591
1592         switch (task->task_proto) {
1593         case SAS_PROTOCOL_SSP:
1594                 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1595                         ts->residual = trans_tx_fail_type;
1596                         ts->stat = SAS_DATA_UNDERRUN;
1597                 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1598                         ts->stat = SAS_QUEUE_FULL;
1599                         slot->abort = 1;
1600                 } else {
1601                         ts->stat = SAS_OPEN_REJECT;
1602                         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1603                 }
1604                 break;
1605         case SAS_PROTOCOL_SATA:
1606         case SAS_PROTOCOL_STP:
1607         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1608                 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1609                         ts->residual = trans_tx_fail_type;
1610                         ts->stat = SAS_DATA_UNDERRUN;
1611                 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1612                         ts->stat = SAS_PHY_DOWN;
1613                         slot->abort = 1;
1614                 } else {
1615                         ts->stat = SAS_OPEN_REJECT;
1616                         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1617                 }
1618                 hisi_sas_sata_done(task, slot);
1619                 break;
1620         case SAS_PROTOCOL_SMP:
1621                 ts->stat = SAM_STAT_CHECK_CONDITION;
1622                 break;
1623         default:
1624                 break;
1625         }
1626 }
1627
1628 static int
1629 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
1630 {
1631         struct sas_task *task = slot->task;
1632         struct hisi_sas_device *sas_dev;
1633         struct device *dev = hisi_hba->dev;
1634         struct task_status_struct *ts;
1635         struct domain_device *device;
1636         struct sas_ha_struct *ha;
1637         enum exec_status sts;
1638         struct hisi_sas_complete_v3_hdr *complete_queue =
1639                         hisi_hba->complete_hdr[slot->cmplt_queue];
1640         struct hisi_sas_complete_v3_hdr *complete_hdr =
1641                         &complete_queue[slot->cmplt_queue_slot];
1642         unsigned long flags;
1643         bool is_internal = slot->is_internal;
1644
1645         if (unlikely(!task || !task->lldd_task || !task->dev))
1646                 return -EINVAL;
1647
1648         ts = &task->task_status;
1649         device = task->dev;
1650         ha = device->port->ha;
1651         sas_dev = device->lldd_dev;
1652
1653         spin_lock_irqsave(&task->task_state_lock, flags);
1654         task->task_state_flags &=
1655                 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1656         spin_unlock_irqrestore(&task->task_state_lock, flags);
1657
1658         memset(ts, 0, sizeof(*ts));
1659         ts->resp = SAS_TASK_COMPLETE;
1660
1661         if (unlikely(!sas_dev)) {
1662                 dev_dbg(dev, "slot complete: port has not device\n");
1663                 ts->stat = SAS_PHY_DOWN;
1664                 goto out;
1665         }
1666
1667         /*
1668          * Use SAS+TMF status codes
1669          */
1670         switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
1671                         >> CMPLT_HDR_ABORT_STAT_OFF) {
1672         case STAT_IO_ABORTED:
1673                 /* this IO has been aborted by abort command */
1674                 ts->stat = SAS_ABORTED_TASK;
1675                 goto out;
1676         case STAT_IO_COMPLETE:
1677                 /* internal abort command complete */
1678                 ts->stat = TMF_RESP_FUNC_SUCC;
1679                 goto out;
1680         case STAT_IO_NO_DEVICE:
1681                 ts->stat = TMF_RESP_FUNC_COMPLETE;
1682                 goto out;
1683         case STAT_IO_NOT_VALID:
1684                 /*
1685                  * abort single IO, the controller can't find the IO
1686                  */
1687                 ts->stat = TMF_RESP_FUNC_FAILED;
1688                 goto out;
1689         default:
1690                 break;
1691         }
1692
1693         /* check for erroneous completion */
1694         if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
1695                 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
1696
1697                 slot_err_v3_hw(hisi_hba, task, slot);
1698                 if (ts->stat != SAS_DATA_UNDERRUN)
1699                         dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d "
1700                                 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
1701                                 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
1702                                 slot->idx, task, sas_dev->device_id,
1703                                 complete_hdr->dw0, complete_hdr->dw1,
1704                                 complete_hdr->act, complete_hdr->dw3,
1705                                 error_info[0], error_info[1],
1706                                 error_info[2], error_info[3]);
1707                 if (unlikely(slot->abort))
1708                         return ts->stat;
1709                 goto out;
1710         }
1711
1712         switch (task->task_proto) {
1713         case SAS_PROTOCOL_SSP: {
1714                 struct ssp_response_iu *iu =
1715                         hisi_sas_status_buf_addr_mem(slot) +
1716                         sizeof(struct hisi_sas_err_record);
1717
1718                 sas_ssp_task_response(dev, task, iu);
1719                 break;
1720         }
1721         case SAS_PROTOCOL_SMP: {
1722                 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1723                 void *to;
1724
1725                 ts->stat = SAM_STAT_GOOD;
1726                 to = kmap_atomic(sg_page(sg_resp));
1727
1728                 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1729                              DMA_FROM_DEVICE);
1730                 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1731                              DMA_TO_DEVICE);
1732                 memcpy(to + sg_resp->offset,
1733                         hisi_sas_status_buf_addr_mem(slot) +
1734                        sizeof(struct hisi_sas_err_record),
1735                        sg_dma_len(sg_resp));
1736                 kunmap_atomic(to);
1737                 break;
1738         }
1739         case SAS_PROTOCOL_SATA:
1740         case SAS_PROTOCOL_STP:
1741         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1742                 ts->stat = SAM_STAT_GOOD;
1743                 hisi_sas_sata_done(task, slot);
1744                 break;
1745         default:
1746                 ts->stat = SAM_STAT_CHECK_CONDITION;
1747                 break;
1748         }
1749
1750         if (!slot->port->port_attached) {
1751                 dev_warn(dev, "slot complete: port %d has removed\n",
1752                         slot->port->sas_port.id);
1753                 ts->stat = SAS_PHY_DOWN;
1754         }
1755
1756 out:
1757         sts = ts->stat;
1758         spin_lock_irqsave(&task->task_state_lock, flags);
1759         if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
1760                 spin_unlock_irqrestore(&task->task_state_lock, flags);
1761                 dev_info(dev, "slot complete: task(%p) aborted\n", task);
1762                 return SAS_ABORTED_TASK;
1763         }
1764         task->task_state_flags |= SAS_TASK_STATE_DONE;
1765         spin_unlock_irqrestore(&task->task_state_lock, flags);
1766         hisi_sas_slot_task_free(hisi_hba, task, slot);
1767
1768         if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
1769                 spin_lock_irqsave(&device->done_lock, flags);
1770                 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
1771                         spin_unlock_irqrestore(&device->done_lock, flags);
1772                         dev_info(dev, "slot complete: task(%p) ignored\n ",
1773                                  task);
1774                         return sts;
1775                 }
1776                 spin_unlock_irqrestore(&device->done_lock, flags);
1777         }
1778
1779         if (task->task_done)
1780                 task->task_done(task);
1781
1782         return sts;
1783 }
1784
1785 static void cq_tasklet_v3_hw(unsigned long val)
1786 {
1787         struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
1788         struct hisi_hba *hisi_hba = cq->hisi_hba;
1789         struct hisi_sas_slot *slot;
1790         struct hisi_sas_complete_v3_hdr *complete_queue;
1791         u32 rd_point = cq->rd_point, wr_point;
1792         int queue = cq->id;
1793
1794         complete_queue = hisi_hba->complete_hdr[queue];
1795
1796         wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
1797                                    (0x14 * queue));
1798
1799         while (rd_point != wr_point) {
1800                 struct hisi_sas_complete_v3_hdr *complete_hdr;
1801                 struct device *dev = hisi_hba->dev;
1802                 int iptt;
1803
1804                 complete_hdr = &complete_queue[rd_point];
1805
1806                 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
1807                 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
1808                         slot = &hisi_hba->slot_info[iptt];
1809                         slot->cmplt_queue_slot = rd_point;
1810                         slot->cmplt_queue = queue;
1811                         slot_complete_v3_hw(hisi_hba, slot);
1812                 } else
1813                         dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt);
1814
1815                 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1816                         rd_point = 0;
1817         }
1818
1819         /* update rd_point */
1820         cq->rd_point = rd_point;
1821         hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1822 }
1823
1824 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
1825 {
1826         struct hisi_sas_cq *cq = p;
1827         struct hisi_hba *hisi_hba = cq->hisi_hba;
1828         int queue = cq->id;
1829
1830         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1831
1832         tasklet_schedule(&cq->tasklet);
1833
1834         return IRQ_HANDLED;
1835 }
1836
1837 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
1838 {
1839         struct device *dev = hisi_hba->dev;
1840         struct pci_dev *pdev = hisi_hba->pci_dev;
1841         int vectors, rc;
1842         int i, k;
1843         int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
1844
1845         vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1,
1846                                         max_msi, PCI_IRQ_MSI);
1847         if (vectors < max_msi) {
1848                 dev_err(dev, "could not allocate all msi (%d)\n", vectors);
1849                 return -ENOENT;
1850         }
1851
1852         rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
1853                               int_phy_up_down_bcast_v3_hw, 0,
1854                               DRV_NAME " phy", hisi_hba);
1855         if (rc) {
1856                 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
1857                 rc = -ENOENT;
1858                 goto free_irq_vectors;
1859         }
1860
1861         rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
1862                               int_chnl_int_v3_hw, 0,
1863                               DRV_NAME " channel", hisi_hba);
1864         if (rc) {
1865                 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
1866                 rc = -ENOENT;
1867                 goto free_phy_irq;
1868         }
1869
1870         rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
1871                               fatal_axi_int_v3_hw, 0,
1872                               DRV_NAME " fatal", hisi_hba);
1873         if (rc) {
1874                 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
1875                 rc = -ENOENT;
1876                 goto free_chnl_interrupt;
1877         }
1878
1879         /* Init tasklets for cq only */
1880         for (i = 0; i < hisi_hba->queue_count; i++) {
1881                 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
1882                 struct tasklet_struct *t = &cq->tasklet;
1883
1884                 rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16),
1885                                           cq_interrupt_v3_hw, 0,
1886                                           DRV_NAME " cq", cq);
1887                 if (rc) {
1888                         dev_err(dev,
1889                                 "could not request cq%d interrupt, rc=%d\n",
1890                                 i, rc);
1891                         rc = -ENOENT;
1892                         goto free_cq_irqs;
1893                 }
1894
1895                 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq);
1896         }
1897
1898         return 0;
1899
1900 free_cq_irqs:
1901         for (k = 0; k < i; k++) {
1902                 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
1903
1904                 free_irq(pci_irq_vector(pdev, k+16), cq);
1905         }
1906         free_irq(pci_irq_vector(pdev, 11), hisi_hba);
1907 free_chnl_interrupt:
1908         free_irq(pci_irq_vector(pdev, 2), hisi_hba);
1909 free_phy_irq:
1910         free_irq(pci_irq_vector(pdev, 1), hisi_hba);
1911 free_irq_vectors:
1912         pci_free_irq_vectors(pdev);
1913         return rc;
1914 }
1915
1916 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
1917 {
1918         int rc;
1919
1920         rc = hw_init_v3_hw(hisi_hba);
1921         if (rc)
1922                 return rc;
1923
1924         rc = interrupt_init_v3_hw(hisi_hba);
1925         if (rc)
1926                 return rc;
1927
1928         return 0;
1929 }
1930
1931 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
1932                 struct sas_phy_linkrates *r)
1933 {
1934         enum sas_linkrate max = r->maximum_linkrate;
1935         u32 prog_phy_link_rate = 0x800;
1936
1937         prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
1938         hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1939                              prog_phy_link_rate);
1940 }
1941
1942 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
1943 {
1944         struct pci_dev *pdev = hisi_hba->pci_dev;
1945         int i;
1946
1947         synchronize_irq(pci_irq_vector(pdev, 1));
1948         synchronize_irq(pci_irq_vector(pdev, 2));
1949         synchronize_irq(pci_irq_vector(pdev, 11));
1950         for (i = 0; i < hisi_hba->queue_count; i++) {
1951                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
1952                 synchronize_irq(pci_irq_vector(pdev, i + 16));
1953         }
1954
1955         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
1956         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
1957         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
1958         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
1959
1960         for (i = 0; i < hisi_hba->n_phy; i++) {
1961                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1962                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
1963                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
1964                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
1965                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
1966         }
1967 }
1968
1969 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
1970 {
1971         return hisi_sas_read32(hisi_hba, PHY_STATE);
1972 }
1973
1974 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1975 {
1976         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1977         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1978         struct sas_phy *sphy = sas_phy->phy;
1979         u32 reg_value;
1980
1981         /* loss dword sync */
1982         reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1983         sphy->loss_of_dword_sync_count += reg_value;
1984
1985         /* phy reset problem */
1986         reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1987         sphy->phy_reset_problem_count += reg_value;
1988
1989         /* invalid dword */
1990         reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1991         sphy->invalid_dword_count += reg_value;
1992
1993         /* disparity err */
1994         reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1995         sphy->running_disparity_error_count += reg_value;
1996
1997 }
1998
1999 static int disable_host_v3_hw(struct hisi_hba *hisi_hba)
2000 {
2001         struct device *dev = hisi_hba->dev;
2002         u32 status, reg_val;
2003         int rc;
2004
2005         interrupt_disable_v3_hw(hisi_hba);
2006         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2007         hisi_sas_kill_tasklets(hisi_hba);
2008
2009         hisi_sas_stop_phys(hisi_hba);
2010
2011         mdelay(10);
2012
2013         reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2014                                   AM_CTRL_GLOBAL);
2015         reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2016         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2017                          AM_CTRL_GLOBAL, reg_val);
2018
2019         /* wait until bus idle */
2020         rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
2021                                           AM_CURR_TRANS_RETURN, status,
2022                                           status == 0x3, 10, 100);
2023         if (rc) {
2024                 dev_err(dev, "axi bus is not idle, rc=%d\n", rc);
2025                 return rc;
2026         }
2027
2028         return 0;
2029 }
2030
2031 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
2032 {
2033         struct device *dev = hisi_hba->dev;
2034         int rc;
2035
2036         rc = disable_host_v3_hw(hisi_hba);
2037         if (rc) {
2038                 dev_err(dev, "soft reset: disable host failed rc=%d\n", rc);
2039                 return rc;
2040         }
2041
2042         hisi_sas_init_mem(hisi_hba);
2043
2044         return hw_init_v3_hw(hisi_hba);
2045 }
2046
2047 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type,
2048                         u8 reg_index, u8 reg_count, u8 *write_data)
2049 {
2050         struct device *dev = hisi_hba->dev;
2051         u32 *data = (u32 *)write_data;
2052         int i;
2053
2054         switch (reg_type) {
2055         case SAS_GPIO_REG_TX:
2056                 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) {
2057                         dev_err(dev, "write gpio: invalid reg range[%d, %d]\n",
2058                                 reg_index, reg_index + reg_count - 1);
2059                         return -EINVAL;
2060                 }
2061
2062                 for (i = 0; i < reg_count; i++)
2063                         hisi_sas_write32(hisi_hba,
2064                                          SAS_GPIO_TX_0_1 + (reg_index + i) * 4,
2065                                          data[i]);
2066                 break;
2067         default:
2068                 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
2069                                 reg_type);
2070                 return -EINVAL;
2071         }
2072
2073         return 0;
2074 }
2075
2076 static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
2077                                              int delay_ms, int timeout_ms)
2078 {
2079         struct device *dev = hisi_hba->dev;
2080         int entries, entries_old = 0, time;
2081
2082         for (time = 0; time < timeout_ms; time += delay_ms) {
2083                 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
2084                 if (entries == entries_old)
2085                         break;
2086
2087                 entries_old = entries;
2088                 msleep(delay_ms);
2089         }
2090
2091         dev_dbg(dev, "wait commands complete %dms\n", time);
2092 }
2093
2094 static struct scsi_host_template sht_v3_hw = {
2095         .name                   = DRV_NAME,
2096         .module                 = THIS_MODULE,
2097         .queuecommand           = sas_queuecommand,
2098         .target_alloc           = sas_target_alloc,
2099         .slave_configure        = hisi_sas_slave_configure,
2100         .scan_finished          = hisi_sas_scan_finished,
2101         .scan_start             = hisi_sas_scan_start,
2102         .change_queue_depth     = sas_change_queue_depth,
2103         .bios_param             = sas_bios_param,
2104         .this_id                = -1,
2105         .sg_tablesize           = SG_ALL,
2106         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
2107         .use_clustering         = ENABLE_CLUSTERING,
2108         .eh_device_reset_handler = sas_eh_device_reset_handler,
2109         .eh_target_reset_handler = sas_eh_target_reset_handler,
2110         .target_destroy         = sas_target_destroy,
2111         .ioctl                  = sas_ioctl,
2112         .shost_attrs            = host_attrs,
2113         .tag_alloc_policy       = BLK_TAG_ALLOC_RR,
2114 };
2115
2116 static const struct hisi_sas_hw hisi_sas_v3_hw = {
2117         .hw_init = hisi_sas_v3_init,
2118         .setup_itct = setup_itct_v3_hw,
2119         .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
2120         .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
2121         .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
2122         .clear_itct = clear_itct_v3_hw,
2123         .sl_notify = sl_notify_v3_hw,
2124         .prep_ssp = prep_ssp_v3_hw,
2125         .prep_smp = prep_smp_v3_hw,
2126         .prep_stp = prep_ata_v3_hw,
2127         .prep_abort = prep_abort_v3_hw,
2128         .get_free_slot = get_free_slot_v3_hw,
2129         .start_delivery = start_delivery_v3_hw,
2130         .slot_complete = slot_complete_v3_hw,
2131         .phys_init = phys_init_v3_hw,
2132         .phy_start = start_phy_v3_hw,
2133         .phy_disable = disable_phy_v3_hw,
2134         .phy_hard_reset = phy_hard_reset_v3_hw,
2135         .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
2136         .phy_set_linkrate = phy_set_linkrate_v3_hw,
2137         .dereg_device = dereg_device_v3_hw,
2138         .soft_reset = soft_reset_v3_hw,
2139         .get_phys_state = get_phys_state_v3_hw,
2140         .get_events = phy_get_events_v3_hw,
2141         .write_gpio = write_gpio_v3_hw,
2142         .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw,
2143 };
2144
2145 static struct Scsi_Host *
2146 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
2147 {
2148         struct Scsi_Host *shost;
2149         struct hisi_hba *hisi_hba;
2150         struct device *dev = &pdev->dev;
2151
2152         shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba));
2153         if (!shost) {
2154                 dev_err(dev, "shost alloc failed\n");
2155                 return NULL;
2156         }
2157         hisi_hba = shost_priv(shost);
2158
2159         INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
2160         hisi_hba->hw = &hisi_sas_v3_hw;
2161         hisi_hba->pci_dev = pdev;
2162         hisi_hba->dev = dev;
2163         hisi_hba->shost = shost;
2164         SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
2165
2166         timer_setup(&hisi_hba->timer, NULL, 0);
2167
2168         if (hisi_sas_get_fw_info(hisi_hba) < 0)
2169                 goto err_out;
2170
2171         if (hisi_sas_alloc(hisi_hba, shost)) {
2172                 hisi_sas_free(hisi_hba);
2173                 goto err_out;
2174         }
2175
2176         return shost;
2177 err_out:
2178         scsi_host_put(shost);
2179         dev_err(dev, "shost alloc failed\n");
2180         return NULL;
2181 }
2182
2183 static int
2184 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2185 {
2186         struct Scsi_Host *shost;
2187         struct hisi_hba *hisi_hba;
2188         struct device *dev = &pdev->dev;
2189         struct asd_sas_phy **arr_phy;
2190         struct asd_sas_port **arr_port;
2191         struct sas_ha_struct *sha;
2192         int rc, phy_nr, port_nr, i;
2193
2194         rc = pci_enable_device(pdev);
2195         if (rc)
2196                 goto err_out;
2197
2198         pci_set_master(pdev);
2199
2200         rc = pci_request_regions(pdev, DRV_NAME);
2201         if (rc)
2202                 goto err_out_disable_device;
2203
2204         if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
2205             (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
2206                 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
2207                    (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
2208                         dev_err(dev, "No usable DMA addressing method\n");
2209                         rc = -EIO;
2210                         goto err_out_regions;
2211                 }
2212         }
2213
2214         shost = hisi_sas_shost_alloc_pci(pdev);
2215         if (!shost) {
2216                 rc = -ENOMEM;
2217                 goto err_out_regions;
2218         }
2219
2220         sha = SHOST_TO_SAS_HA(shost);
2221         hisi_hba = shost_priv(shost);
2222         dev_set_drvdata(dev, sha);
2223
2224         hisi_hba->regs = pcim_iomap(pdev, 5, 0);
2225         if (!hisi_hba->regs) {
2226                 dev_err(dev, "cannot map register.\n");
2227                 rc = -ENOMEM;
2228                 goto err_out_ha;
2229         }
2230
2231         phy_nr = port_nr = hisi_hba->n_phy;
2232
2233         arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
2234         arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
2235         if (!arr_phy || !arr_port) {
2236                 rc = -ENOMEM;
2237                 goto err_out_ha;
2238         }
2239
2240         sha->sas_phy = arr_phy;
2241         sha->sas_port = arr_port;
2242         sha->core.shost = shost;
2243         sha->lldd_ha = hisi_hba;
2244
2245         shost->transportt = hisi_sas_stt;
2246         shost->max_id = HISI_SAS_MAX_DEVICES;
2247         shost->max_lun = ~0;
2248         shost->max_channel = 1;
2249         shost->max_cmd_len = 16;
2250         shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT);
2251         shost->can_queue = hisi_hba->hw->max_command_entries -
2252                 HISI_SAS_RESERVED_IPTT_CNT;
2253         shost->cmd_per_lun = hisi_hba->hw->max_command_entries -
2254                 HISI_SAS_RESERVED_IPTT_CNT;
2255
2256         sha->sas_ha_name = DRV_NAME;
2257         sha->dev = dev;
2258         sha->lldd_module = THIS_MODULE;
2259         sha->sas_addr = &hisi_hba->sas_addr[0];
2260         sha->num_phys = hisi_hba->n_phy;
2261         sha->core.shost = hisi_hba->shost;
2262
2263         for (i = 0; i < hisi_hba->n_phy; i++) {
2264                 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
2265                 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
2266         }
2267
2268         rc = scsi_add_host(shost, dev);
2269         if (rc)
2270                 goto err_out_ha;
2271
2272         rc = sas_register_ha(sha);
2273         if (rc)
2274                 goto err_out_register_ha;
2275
2276         rc = hisi_hba->hw->hw_init(hisi_hba);
2277         if (rc)
2278                 goto err_out_register_ha;
2279
2280         scsi_scan_host(shost);
2281
2282         return 0;
2283
2284 err_out_register_ha:
2285         scsi_remove_host(shost);
2286 err_out_ha:
2287         scsi_host_put(shost);
2288 err_out_regions:
2289         pci_release_regions(pdev);
2290 err_out_disable_device:
2291         pci_disable_device(pdev);
2292 err_out:
2293         return rc;
2294 }
2295
2296 static void
2297 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
2298 {
2299         int i;
2300
2301         free_irq(pci_irq_vector(pdev, 1), hisi_hba);
2302         free_irq(pci_irq_vector(pdev, 2), hisi_hba);
2303         free_irq(pci_irq_vector(pdev, 11), hisi_hba);
2304         for (i = 0; i < hisi_hba->queue_count; i++) {
2305                 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2306
2307                 free_irq(pci_irq_vector(pdev, i+16), cq);
2308         }
2309         pci_free_irq_vectors(pdev);
2310 }
2311
2312 static void hisi_sas_v3_remove(struct pci_dev *pdev)
2313 {
2314         struct device *dev = &pdev->dev;
2315         struct sas_ha_struct *sha = dev_get_drvdata(dev);
2316         struct hisi_hba *hisi_hba = sha->lldd_ha;
2317         struct Scsi_Host *shost = sha->core.shost;
2318
2319         if (timer_pending(&hisi_hba->timer))
2320                 del_timer(&hisi_hba->timer);
2321
2322         sas_unregister_ha(sha);
2323         sas_remove_host(sha->core.shost);
2324
2325         hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
2326         hisi_sas_kill_tasklets(hisi_hba);
2327         pci_release_regions(pdev);
2328         pci_disable_device(pdev);
2329         hisi_sas_free(hisi_hba);
2330         scsi_host_put(shost);
2331 }
2332
2333 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = {
2334         { .irq_msk = BIT(19), .msg = "HILINK_INT" },
2335         { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" },
2336         { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" },
2337         { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" },
2338         { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" },
2339         { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" },
2340         { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" },
2341         { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" },
2342         { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" },
2343         { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" },
2344         { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" },
2345         { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" },
2346         { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" },
2347 };
2348
2349 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = {
2350         { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" },
2351         { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" },
2352         { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" },
2353         { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" },
2354         { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" },
2355         { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" },
2356         { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" },
2357         { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" },
2358         { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" },
2359         { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" },
2360         { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" },
2361         { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" },
2362         { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" },
2363         { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" },
2364         { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" },
2365         { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" },
2366         { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" },
2367         { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" },
2368         { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" },
2369         { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" },
2370         { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" },
2371         { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" },
2372         { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" },
2373         { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" },
2374         { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" },
2375         { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" },
2376         { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" },
2377         { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" },
2378         { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" },
2379         { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" },
2380         { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" },
2381 };
2382
2383 static const struct hisi_sas_hw_error sas_ras_intr2_nfe[] = {
2384         { .irq_msk = BIT(0), .msg = "DMAC0_AXI_BUS_ERR" },
2385         { .irq_msk = BIT(1), .msg = "DMAC1_AXI_BUS_ERR" },
2386         { .irq_msk = BIT(2), .msg = "DMAC2_AXI_BUS_ERR" },
2387         { .irq_msk = BIT(3), .msg = "DMAC3_AXI_BUS_ERR" },
2388         { .irq_msk = BIT(4), .msg = "DMAC4_AXI_BUS_ERR" },
2389         { .irq_msk = BIT(5), .msg = "DMAC5_AXI_BUS_ERR" },
2390         { .irq_msk = BIT(6), .msg = "DMAC6_AXI_BUS_ERR" },
2391         { .irq_msk = BIT(7), .msg = "DMAC7_AXI_BUS_ERR" },
2392         { .irq_msk = BIT(8), .msg = "DMAC0_FIFO_OMIT_ERR" },
2393         { .irq_msk = BIT(9), .msg = "DMAC1_FIFO_OMIT_ERR" },
2394         { .irq_msk = BIT(10), .msg = "DMAC2_FIFO_OMIT_ERR" },
2395         { .irq_msk = BIT(11), .msg = "DMAC3_FIFO_OMIT_ERR" },
2396         { .irq_msk = BIT(12), .msg = "DMAC4_FIFO_OMIT_ERR" },
2397         { .irq_msk = BIT(13), .msg = "DMAC5_FIFO_OMIT_ERR" },
2398         { .irq_msk = BIT(14), .msg = "DMAC6_FIFO_OMIT_ERR" },
2399         { .irq_msk = BIT(15), .msg = "DMAC7_FIFO_OMIT_ERR" },
2400         { .irq_msk = BIT(16), .msg = "HGC_RLSE_SLOT_UNMATCH" },
2401         { .irq_msk = BIT(17), .msg = "HGC_LM_ADD_FCH_LIST_ERR" },
2402         { .irq_msk = BIT(18), .msg = "HGC_AXI_BUS_ERR" },
2403         { .irq_msk = BIT(19), .msg = "HGC_FIFO_OMIT_ERR" },
2404 };
2405
2406 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba)
2407 {
2408         struct device *dev = hisi_hba->dev;
2409         const struct hisi_sas_hw_error *ras_error;
2410         bool need_reset = false;
2411         u32 irq_value;
2412         int i;
2413
2414         irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0);
2415         for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) {
2416                 ras_error = &sas_ras_intr0_nfe[i];
2417                 if (ras_error->irq_msk & irq_value) {
2418                         dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n",
2419                                         ras_error->msg, irq_value);
2420                         need_reset = true;
2421                 }
2422         }
2423         hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value);
2424
2425         irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1);
2426         for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) {
2427                 ras_error = &sas_ras_intr1_nfe[i];
2428                 if (ras_error->irq_msk & irq_value) {
2429                         dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n",
2430                                         ras_error->msg, irq_value);
2431                         need_reset = true;
2432                 }
2433         }
2434         hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value);
2435
2436         irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR2);
2437         for (i = 0; i < ARRAY_SIZE(sas_ras_intr2_nfe); i++) {
2438                 ras_error = &sas_ras_intr2_nfe[i];
2439                 if (ras_error->irq_msk & irq_value) {
2440                         dev_warn(dev, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n",
2441                                         ras_error->msg, irq_value);
2442                         need_reset = true;
2443                 }
2444         }
2445         hisi_sas_write32(hisi_hba, SAS_RAS_INTR2, irq_value);
2446
2447         return need_reset;
2448 }
2449
2450 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev,
2451                 pci_channel_state_t state)
2452 {
2453         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2454         struct hisi_hba *hisi_hba = sha->lldd_ha;
2455         struct device *dev = hisi_hba->dev;
2456
2457         dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state);
2458         if (state == pci_channel_io_perm_failure)
2459                 return PCI_ERS_RESULT_DISCONNECT;
2460
2461         if (process_non_fatal_error_v3_hw(hisi_hba))
2462                 return PCI_ERS_RESULT_NEED_RESET;
2463
2464         return PCI_ERS_RESULT_CAN_RECOVER;
2465 }
2466
2467 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev)
2468 {
2469         return PCI_ERS_RESULT_RECOVERED;
2470 }
2471
2472 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev)
2473 {
2474         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2475         struct hisi_hba *hisi_hba = sha->lldd_ha;
2476         struct device *dev = hisi_hba->dev;
2477         HISI_SAS_DECLARE_RST_WORK_ON_STACK(r);
2478
2479         dev_info(dev, "PCI error: slot reset callback!!\n");
2480         queue_work(hisi_hba->wq, &r.work);
2481         wait_for_completion(r.completion);
2482         if (r.done)
2483                 return PCI_ERS_RESULT_RECOVERED;
2484
2485         return PCI_ERS_RESULT_DISCONNECT;
2486 }
2487
2488 static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev)
2489 {
2490         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2491         struct hisi_hba *hisi_hba = sha->lldd_ha;
2492         struct device *dev = hisi_hba->dev;
2493         int rc;
2494
2495         dev_info(dev, "FLR prepare\n");
2496         set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2497         hisi_sas_controller_reset_prepare(hisi_hba);
2498
2499         rc = disable_host_v3_hw(hisi_hba);
2500         if (rc)
2501                 dev_err(dev, "FLR: disable host failed rc=%d\n", rc);
2502 }
2503
2504 static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev)
2505 {
2506         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2507         struct hisi_hba *hisi_hba = sha->lldd_ha;
2508         struct device *dev = hisi_hba->dev;
2509         int rc;
2510
2511         hisi_sas_init_mem(hisi_hba);
2512
2513         rc = hw_init_v3_hw(hisi_hba);
2514         if (rc) {
2515                 dev_err(dev, "FLR: hw init failed rc=%d\n", rc);
2516                 return;
2517         }
2518
2519         hisi_sas_controller_reset_done(hisi_hba);
2520         dev_info(dev, "FLR done\n");
2521 }
2522
2523 enum {
2524         /* instances of the controller */
2525         hip08,
2526 };
2527
2528 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state)
2529 {
2530         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2531         struct hisi_hba *hisi_hba = sha->lldd_ha;
2532         struct device *dev = hisi_hba->dev;
2533         struct Scsi_Host *shost = hisi_hba->shost;
2534         u32 device_state;
2535         int rc;
2536
2537         if (!pdev->pm_cap) {
2538                 dev_err(dev, "PCI PM not supported\n");
2539                 return -ENODEV;
2540         }
2541
2542         if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
2543                 return -1;
2544
2545         scsi_block_requests(shost);
2546         set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2547         flush_workqueue(hisi_hba->wq);
2548
2549         rc = disable_host_v3_hw(hisi_hba);
2550         if (rc) {
2551                 dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc);
2552                 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2553                 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2554                 scsi_unblock_requests(shost);
2555                 return rc;
2556         }
2557
2558         hisi_sas_init_mem(hisi_hba);
2559
2560         device_state = pci_choose_state(pdev, state);
2561         dev_warn(dev, "entering operating state [D%d]\n",
2562                         device_state);
2563         pci_save_state(pdev);
2564         pci_disable_device(pdev);
2565         pci_set_power_state(pdev, device_state);
2566
2567         hisi_sas_release_tasks(hisi_hba);
2568
2569         sas_suspend_ha(sha);
2570         return 0;
2571 }
2572
2573 static int hisi_sas_v3_resume(struct pci_dev *pdev)
2574 {
2575         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2576         struct hisi_hba *hisi_hba = sha->lldd_ha;
2577         struct Scsi_Host *shost = hisi_hba->shost;
2578         struct device *dev = hisi_hba->dev;
2579         unsigned int rc;
2580         u32 device_state = pdev->current_state;
2581
2582         dev_warn(dev, "resuming from operating state [D%d]\n",
2583                         device_state);
2584         pci_set_power_state(pdev, PCI_D0);
2585         pci_enable_wake(pdev, PCI_D0, 0);
2586         pci_restore_state(pdev);
2587         rc = pci_enable_device(pdev);
2588         if (rc)
2589                 dev_err(dev, "enable device failed during resume (%d)\n", rc);
2590
2591         pci_set_master(pdev);
2592         scsi_unblock_requests(shost);
2593         clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2594
2595         sas_prep_resume_ha(sha);
2596         init_reg_v3_hw(hisi_hba);
2597         hisi_hba->hw->phys_init(hisi_hba);
2598         sas_resume_ha(sha);
2599         clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2600
2601         return 0;
2602 }
2603
2604 static const struct pci_device_id sas_v3_pci_table[] = {
2605         { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
2606         {}
2607 };
2608 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
2609
2610 static const struct pci_error_handlers hisi_sas_err_handler = {
2611         .error_detected = hisi_sas_error_detected_v3_hw,
2612         .mmio_enabled   = hisi_sas_mmio_enabled_v3_hw,
2613         .slot_reset     = hisi_sas_slot_reset_v3_hw,
2614         .reset_prepare  = hisi_sas_reset_prepare_v3_hw,
2615         .reset_done     = hisi_sas_reset_done_v3_hw,
2616 };
2617
2618 static struct pci_driver sas_v3_pci_driver = {
2619         .name           = DRV_NAME,
2620         .id_table       = sas_v3_pci_table,
2621         .probe          = hisi_sas_v3_probe,
2622         .remove         = hisi_sas_v3_remove,
2623         .suspend        = hisi_sas_v3_suspend,
2624         .resume         = hisi_sas_v3_resume,
2625         .err_handler    = &hisi_sas_err_handler,
2626 };
2627
2628 module_pci_driver(sas_v3_pci_driver);
2629
2630 MODULE_LICENSE("GPL");
2631 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2632 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
2633 MODULE_ALIAS("pci:" DRV_NAME);