1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2017 Hisilicon Limited.
6 #include <linux/sched/clock.h>
8 #define DRV_NAME "hisi_sas_v3_hw"
10 /* global registers need init */
11 #define DLVRY_QUEUE_ENABLE 0x0
12 #define IOST_BASE_ADDR_LO 0x8
13 #define IOST_BASE_ADDR_HI 0xc
14 #define ITCT_BASE_ADDR_LO 0x10
15 #define ITCT_BASE_ADDR_HI 0x14
16 #define IO_BROKEN_MSG_ADDR_LO 0x18
17 #define IO_BROKEN_MSG_ADDR_HI 0x1c
18 #define PHY_CONTEXT 0x20
19 #define PHY_STATE 0x24
20 #define PHY_PORT_NUM_MA 0x28
21 #define PHY_CONN_RATE 0x30
23 #define ITCT_CLR_EN_OFF 16
24 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
25 #define ITCT_DEV_OFF 0
26 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
27 #define SAS_AXI_USER3 0x50
28 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
29 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
30 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
31 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
32 #define CFG_MAX_TAG 0x68
33 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
34 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
35 #define HGC_GET_ITV_TIME 0x90
36 #define DEVICE_MSG_WORK_MODE 0x94
37 #define OPENA_WT_CONTI_TIME 0x9c
38 #define I_T_NEXUS_LOSS_TIME 0xa0
39 #define MAX_CON_TIME_LIMIT_TIME 0xa4
40 #define BUS_INACTIVE_LIMIT_TIME 0xa8
41 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
42 #define CQ_INT_CONVERGE_EN 0xb0
43 #define CFG_AGING_TIME 0xbc
44 #define HGC_DFX_CFG2 0xc0
45 #define CFG_ABT_SET_QUERY_IPTT 0xd4
46 #define CFG_SET_ABORTED_IPTT_OFF 0
47 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
48 #define CFG_SET_ABORTED_EN_OFF 12
49 #define CFG_ABT_SET_IPTT_DONE 0xd8
50 #define CFG_ABT_SET_IPTT_DONE_OFF 0
51 #define HGC_IOMB_PROC1_STATUS 0x104
52 #define HGC_LM_DFX_STATUS2 0x128
53 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
54 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
55 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
56 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
57 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
58 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
59 #define HGC_CQE_ECC_ADDR 0x13c
60 #define HGC_CQE_ECC_1B_ADDR_OFF 0
61 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
62 #define HGC_CQE_ECC_MB_ADDR_OFF 8
63 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
64 #define HGC_IOST_ECC_ADDR 0x140
65 #define HGC_IOST_ECC_1B_ADDR_OFF 0
66 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
67 #define HGC_IOST_ECC_MB_ADDR_OFF 16
68 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
69 #define HGC_DQE_ECC_ADDR 0x144
70 #define HGC_DQE_ECC_1B_ADDR_OFF 0
71 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
72 #define HGC_DQE_ECC_MB_ADDR_OFF 16
73 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
74 #define CHNL_INT_STATUS 0x148
76 #define HGC_ITCT_ECC_ADDR 0x150
77 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
78 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
79 HGC_ITCT_ECC_1B_ADDR_OFF)
80 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
81 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
82 HGC_ITCT_ECC_MB_ADDR_OFF)
83 #define HGC_AXI_FIFO_ERR_INFO 0x154
84 #define AXI_ERR_INFO_OFF 0
85 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
86 #define FIFO_ERR_INFO_OFF 8
87 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
88 #define TAB_RD_TYPE 0x15c
89 #define INT_COAL_EN 0x19c
90 #define OQ_INT_COAL_TIME 0x1a0
91 #define OQ_INT_COAL_CNT 0x1a4
92 #define ENT_INT_COAL_TIME 0x1a8
93 #define ENT_INT_COAL_CNT 0x1ac
94 #define OQ_INT_SRC 0x1b0
95 #define OQ_INT_SRC_MSK 0x1b4
96 #define ENT_INT_SRC1 0x1b8
97 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
98 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
99 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
100 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
101 #define ENT_INT_SRC2 0x1bc
102 #define ENT_INT_SRC3 0x1c0
103 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
104 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
105 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
106 #define ENT_INT_SRC3_AXI_OFF 11
107 #define ENT_INT_SRC3_FIFO_OFF 12
108 #define ENT_INT_SRC3_LM_OFF 14
109 #define ENT_INT_SRC3_ITC_INT_OFF 15
110 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
111 #define ENT_INT_SRC3_ABT_OFF 16
112 #define ENT_INT_SRC3_DQE_POISON_OFF 18
113 #define ENT_INT_SRC3_IOST_POISON_OFF 19
114 #define ENT_INT_SRC3_ITCT_POISON_OFF 20
115 #define ENT_INT_SRC3_ITCT_NCQ_POISON_OFF 21
116 #define ENT_INT_SRC_MSK1 0x1c4
117 #define ENT_INT_SRC_MSK2 0x1c8
118 #define ENT_INT_SRC_MSK3 0x1cc
119 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
120 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
121 #define CHNL_ENT_INT_MSK 0x1d4
122 #define HGC_COM_INT_MSK 0x1d8
123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
124 #define SAS_ECC_INTR 0x1e8
125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
129 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 4
130 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 5
131 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 6
132 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 7
133 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 8
134 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 9
135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 12
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 13
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 14
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 15
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 16
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 17
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 18
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 19
145 #define SAS_ECC_INTR_OOO_RAM_ECC_1B_OFF 20
146 #define SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF 21
147 #define SAS_ECC_INTR_MSK 0x1ec
148 #define HGC_ERR_STAT_EN 0x238
149 #define CQE_SEND_CNT 0x248
150 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
151 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
152 #define DLVRY_Q_0_DEPTH 0x268
153 #define DLVRY_Q_0_WR_PTR 0x26c
154 #define DLVRY_Q_0_RD_PTR 0x270
155 #define HYPER_STREAM_ID_EN_CFG 0xc80
156 #define OQ0_INT_SRC_MSK 0xc90
157 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
158 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
159 #define COMPL_Q_0_DEPTH 0x4e8
160 #define COMPL_Q_0_WR_PTR 0x4ec
161 #define COMPL_Q_0_RD_PTR 0x4f0
162 #define HGC_RXM_DFX_STATUS14 0xae8
163 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
164 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
165 HGC_RXM_DFX_STATUS14_MEM0_OFF)
166 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
167 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
168 HGC_RXM_DFX_STATUS14_MEM1_OFF)
169 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
170 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
171 HGC_RXM_DFX_STATUS14_MEM2_OFF)
172 #define HGC_RXM_DFX_STATUS15 0xaec
173 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
174 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
175 HGC_RXM_DFX_STATUS15_MEM3_OFF)
176 #define AWQOS_AWCACHE_CFG 0xc84
177 #define ARQOS_ARCACHE_CFG 0xc88
178 #define HILINK_ERR_DFX 0xe04
179 #define SAS_GPIO_CFG_0 0x1000
180 #define SAS_GPIO_CFG_1 0x1004
181 #define SAS_GPIO_TX_0_1 0x1040
182 #define SAS_CFG_DRIVE_VLD 0x1070
184 /* phy registers requiring init */
185 #define PORT_BASE (0x2000)
186 #define PHY_CFG (PORT_BASE + 0x0)
187 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
188 #define PHY_CFG_ENA_OFF 0
189 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
190 #define PHY_CFG_DC_OPT_OFF 2
191 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
192 #define PHY_CFG_PHY_RST_OFF 3
193 #define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF)
194 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
195 #define CFG_PROG_PHY_LINK_RATE_OFF 0
196 #define CFG_PROG_PHY_LINK_RATE_MSK (0xff << CFG_PROG_PHY_LINK_RATE_OFF)
197 #define CFG_PROG_OOB_PHY_LINK_RATE_OFF 8
198 #define CFG_PROG_OOB_PHY_LINK_RATE_MSK (0xf << CFG_PROG_OOB_PHY_LINK_RATE_OFF)
199 #define PHY_CTRL (PORT_BASE + 0x14)
200 #define PHY_CTRL_RESET_OFF 0
201 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
202 #define CMD_HDR_PIR_OFF 8
203 #define CMD_HDR_PIR_MSK (0x1 << CMD_HDR_PIR_OFF)
204 #define SERDES_CFG (PORT_BASE + 0x1c)
205 #define CFG_ALOS_CHK_DISABLE_OFF 9
206 #define CFG_ALOS_CHK_DISABLE_MSK (0x1 << CFG_ALOS_CHK_DISABLE_OFF)
207 #define SAS_PHY_BIST_CTRL (PORT_BASE + 0x2c)
208 #define CFG_BIST_MODE_SEL_OFF 0
209 #define CFG_BIST_MODE_SEL_MSK (0xf << CFG_BIST_MODE_SEL_OFF)
210 #define CFG_LOOP_TEST_MODE_OFF 14
211 #define CFG_LOOP_TEST_MODE_MSK (0x3 << CFG_LOOP_TEST_MODE_OFF)
212 #define CFG_RX_BIST_EN_OFF 16
213 #define CFG_RX_BIST_EN_MSK (0x1 << CFG_RX_BIST_EN_OFF)
214 #define CFG_TX_BIST_EN_OFF 17
215 #define CFG_TX_BIST_EN_MSK (0x1 << CFG_TX_BIST_EN_OFF)
216 #define CFG_BIST_TEST_OFF 18
217 #define CFG_BIST_TEST_MSK (0x1 << CFG_BIST_TEST_OFF)
218 #define SAS_PHY_BIST_CODE (PORT_BASE + 0x30)
219 #define SAS_PHY_BIST_CODE1 (PORT_BASE + 0x34)
220 #define SAS_BIST_ERR_CNT (PORT_BASE + 0x38)
221 #define SL_CFG (PORT_BASE + 0x84)
222 #define AIP_LIMIT (PORT_BASE + 0x90)
223 #define SL_CONTROL (PORT_BASE + 0x94)
224 #define SL_CONTROL_NOTIFY_EN_OFF 0
225 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
226 #define SL_CTA_OFF 17
227 #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
228 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
229 #define RX_BCAST_CHG_OFF 1
230 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
231 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
232 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
233 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
234 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
235 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
236 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
237 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
238 #define TXID_AUTO (PORT_BASE + 0xb8)
240 #define CT3_MSK (0x1 << CT3_OFF)
241 #define TX_HARDRST_OFF 2
242 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
243 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
244 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
245 #define STP_LINK_TIMER (PORT_BASE + 0x120)
246 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124)
247 #define CON_CFG_DRIVER (PORT_BASE + 0x130)
248 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
249 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
250 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
251 #define CHL_INT0 (PORT_BASE + 0x1b4)
252 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
253 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
254 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
255 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
256 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
257 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
258 #define CHL_INT0_NOT_RDY_OFF 4
259 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
260 #define CHL_INT0_PHY_RDY_OFF 5
261 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
262 #define CHL_INT1 (PORT_BASE + 0x1b8)
263 #define CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF 15
264 #define CHL_INT1_DMAC_TX_ECC_1B_ERR_OFF 16
265 #define CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF 17
266 #define CHL_INT1_DMAC_RX_ECC_1B_ERR_OFF 18
267 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
268 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
269 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
270 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
271 #define CHL_INT1_DMAC_TX_FIFO_ERR_OFF 23
272 #define CHL_INT1_DMAC_RX_FIFO_ERR_OFF 24
273 #define CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF 26
274 #define CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF 27
275 #define CHL_INT2 (PORT_BASE + 0x1bc)
276 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
277 #define CHL_INT2_RX_DISP_ERR_OFF 28
278 #define CHL_INT2_RX_CODE_ERR_OFF 29
279 #define CHL_INT2_RX_INVLD_DW_OFF 30
280 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31
281 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
282 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
283 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
284 #define SAS_EC_INT_COAL_TIME (PORT_BASE + 0x1cc)
285 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
286 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4)
287 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
288 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
289 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
290 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
291 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
292 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
293 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
294 #define DMA_TX_STATUS_BUSY_OFF 0
295 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
296 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
297 #define DMA_RX_STATUS_BUSY_OFF 0
298 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
300 #define COARSETUNE_TIME (PORT_BASE + 0x304)
301 #define TXDEEMPH_G1 (PORT_BASE + 0x350)
302 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
303 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
304 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
305 #define ERR_CNT_CODE_ERR (PORT_BASE + 0x394)
306 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
307 #define DFX_FIFO_CTRL (PORT_BASE + 0x3a0)
308 #define DFX_FIFO_CTRL_TRIGGER_MODE_OFF 0
309 #define DFX_FIFO_CTRL_TRIGGER_MODE_MSK (0x7 << DFX_FIFO_CTRL_TRIGGER_MODE_OFF)
310 #define DFX_FIFO_CTRL_DUMP_MODE_OFF 3
311 #define DFX_FIFO_CTRL_DUMP_MODE_MSK (0x7 << DFX_FIFO_CTRL_DUMP_MODE_OFF)
312 #define DFX_FIFO_CTRL_SIGNAL_SEL_OFF 6
313 #define DFX_FIFO_CTRL_SIGNAL_SEL_MSK (0xF << DFX_FIFO_CTRL_SIGNAL_SEL_OFF)
314 #define DFX_FIFO_CTRL_DUMP_DISABLE_OFF 10
315 #define DFX_FIFO_CTRL_DUMP_DISABLE_MSK (0x1 << DFX_FIFO_CTRL_DUMP_DISABLE_OFF)
316 #define DFX_FIFO_TRIGGER (PORT_BASE + 0x3a4)
317 #define DFX_FIFO_TRIGGER_MSK (PORT_BASE + 0x3a8)
318 #define DFX_FIFO_DUMP_MSK (PORT_BASE + 0x3aC)
319 #define DFX_FIFO_RD_DATA (PORT_BASE + 0x3b0)
321 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
322 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
323 #error Max ITCT exceeded
326 #define AXI_MASTER_CFG_BASE (0x5000)
327 #define AM_CTRL_GLOBAL (0x0)
328 #define AM_CTRL_SHUTDOWN_REQ_OFF 0
329 #define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF)
330 #define AM_CURR_TRANS_RETURN (0x150)
332 #define AM_CFG_MAX_TRANS (0x5010)
333 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
334 #define AXI_CFG (0x5100)
335 #define AM_ROB_ECC_ERR_ADDR (0x510c)
336 #define AM_ROB_ECC_ERR_ADDR_OFF 0
337 #define AM_ROB_ECC_ERR_ADDR_MSK 0xffffffff
339 /* RAS registers need init */
340 #define RAS_BASE (0x6000)
341 #define SAS_RAS_INTR0 (RAS_BASE)
342 #define SAS_RAS_INTR1 (RAS_BASE + 0x04)
343 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08)
344 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c)
345 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c)
346 #define SAS_RAS_INTR2 (RAS_BASE + 0x20)
347 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24)
349 /* HW dma structures */
350 /* Delivery queue header */
352 #define CMD_HDR_ABORT_FLAG_OFF 0
353 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
354 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
355 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
356 #define CMD_HDR_RESP_REPORT_OFF 5
357 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
358 #define CMD_HDR_TLR_CTRL_OFF 6
359 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
360 #define CMD_HDR_PORT_OFF 18
361 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
362 #define CMD_HDR_PRIORITY_OFF 27
363 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
364 #define CMD_HDR_CMD_OFF 29
365 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
367 #define CMD_HDR_UNCON_CMD_OFF 3
368 #define CMD_HDR_DIR_OFF 5
369 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
370 #define CMD_HDR_RESET_OFF 7
371 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
372 #define CMD_HDR_VDTL_OFF 10
373 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
374 #define CMD_HDR_FRAME_TYPE_OFF 11
375 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
376 #define CMD_HDR_DEV_ID_OFF 16
377 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
379 #define CMD_HDR_CFL_OFF 0
380 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
381 #define CMD_HDR_NCQ_TAG_OFF 10
382 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
383 #define CMD_HDR_MRFL_OFF 15
384 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
385 #define CMD_HDR_SG_MOD_OFF 24
386 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
388 #define CMD_HDR_IPTT_OFF 0
389 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
391 #define CMD_HDR_DIF_SGL_LEN_OFF 0
392 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
393 #define CMD_HDR_DATA_SGL_LEN_OFF 16
394 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
396 #define CMD_HDR_ADDR_MODE_SEL_OFF 15
397 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
398 #define CMD_HDR_ABORT_IPTT_OFF 16
399 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
401 /* Completion header */
403 #define CMPLT_HDR_CMPLT_OFF 0
404 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
405 #define CMPLT_HDR_ERROR_PHASE_OFF 2
406 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
407 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
408 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
409 #define CMPLT_HDR_RSPNS_GOOD_OFF 11
410 #define CMPLT_HDR_RSPNS_GOOD_MSK (0x1 << CMPLT_HDR_RSPNS_GOOD_OFF)
411 #define CMPLT_HDR_ERX_OFF 12
412 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
413 #define CMPLT_HDR_ABORT_STAT_OFF 13
414 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
416 #define STAT_IO_NOT_VALID 0x1
417 #define STAT_IO_NO_DEVICE 0x2
418 #define STAT_IO_COMPLETE 0x3
419 #define STAT_IO_ABORTED 0x4
421 #define CMPLT_HDR_IPTT_OFF 0
422 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
423 #define CMPLT_HDR_DEV_ID_OFF 16
424 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
426 #define CMPLT_HDR_IO_IN_TARGET_OFF 17
427 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
431 #define ITCT_HDR_DEV_TYPE_OFF 0
432 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
433 #define ITCT_HDR_VALID_OFF 2
434 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
435 #define ITCT_HDR_MCR_OFF 5
436 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
437 #define ITCT_HDR_VLN_OFF 9
438 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
439 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
440 #define ITCT_HDR_AWT_CONTINUE_OFF 25
441 #define ITCT_HDR_PORT_ID_OFF 28
442 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
444 #define ITCT_HDR_INLT_OFF 0
445 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
446 #define ITCT_HDR_RTOLT_OFF 48
447 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
449 struct hisi_sas_protect_iu_v3_hw {
459 struct hisi_sas_complete_v3_hdr {
466 struct hisi_sas_err_record_v3 {
468 __le32 trans_tx_fail_type;
471 __le32 trans_rx_fail_type;
474 __le16 dma_tx_err_type;
475 __le16 sipc_rx_err_type;
478 __le32 dma_rx_err_type;
481 #define RX_DATA_LEN_UNDERFLOW_OFF 6
482 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
484 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
485 #define HISI_SAS_MSI_COUNT_V3_HW 32
487 #define DIR_NO_DATA 0
489 #define DIR_TO_DEVICE 2
490 #define DIR_RESERVED 3
492 #define FIS_CMD_IS_UNCONSTRAINED(fis) \
493 ((fis.command == ATA_CMD_READ_LOG_EXT) || \
494 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
495 ((fis.command == ATA_CMD_DEV_RESET) && \
496 ((fis.control & ATA_SRST) != 0)))
498 #define T10_INSRT_EN_OFF 0
499 #define T10_INSRT_EN_MSK (1 << T10_INSRT_EN_OFF)
500 #define T10_RMV_EN_OFF 1
501 #define T10_RMV_EN_MSK (1 << T10_RMV_EN_OFF)
502 #define T10_RPLC_EN_OFF 2
503 #define T10_RPLC_EN_MSK (1 << T10_RPLC_EN_OFF)
504 #define T10_CHK_EN_OFF 3
505 #define T10_CHK_EN_MSK (1 << T10_CHK_EN_OFF)
506 #define INCR_LBRT_OFF 5
507 #define INCR_LBRT_MSK (1 << INCR_LBRT_OFF)
508 #define USR_DATA_BLOCK_SZ_OFF 20
509 #define USR_DATA_BLOCK_SZ_MSK (0x3 << USR_DATA_BLOCK_SZ_OFF)
510 #define T10_CHK_MSK_OFF 16
511 #define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF)
512 #define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF)
514 #define BASE_VECTORS_V3_HW 16
515 #define MIN_AFFINE_VECTORS_V3_HW (BASE_VECTORS_V3_HW + 1)
517 #define CHNL_INT_STS_MSK 0xeeeeeeee
518 #define CHNL_INT_STS_PHY_MSK 0xe
519 #define CHNL_INT_STS_INT0_MSK BIT(1)
520 #define CHNL_INT_STS_INT1_MSK BIT(2)
521 #define CHNL_INT_STS_INT2_MSK BIT(3)
524 #define BAR_NO_V3_HW 5
527 DSM_FUNC_ERR_HANDLE_MSI = 0,
530 static bool hisi_sas_intr_conv;
531 MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)");
533 /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */
534 static int prot_mask;
535 module_param(prot_mask, int, 0444);
536 MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 ");
538 static void debugfs_work_handler_v3_hw(struct work_struct *work);
539 static void debugfs_snapshot_regs_v3_hw(struct hisi_hba *hisi_hba);
541 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
543 void __iomem *regs = hisi_hba->regs + off;
548 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
550 void __iomem *regs = hisi_hba->regs + off;
555 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
558 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
563 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
566 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
571 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \
574 void __iomem *regs = hisi_hba->regs + off; \
575 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \
578 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \
581 void __iomem *regs = hisi_hba->regs + off; \
582 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\
585 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
589 /* Global registers init */
590 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
591 (u32)((1ULL << hisi_hba->queue_count) - 1));
592 hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0);
593 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
594 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
595 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
596 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
597 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
598 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
599 hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN,
601 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
602 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
603 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
604 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
605 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
606 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
607 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffc220ff);
608 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
609 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
610 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
611 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x155555);
612 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
613 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
614 for (i = 0; i < hisi_hba->queue_count; i++)
615 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0);
617 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
619 for (i = 0; i < hisi_hba->n_phy; i++) {
620 enum sas_linkrate max;
621 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
622 struct asd_sas_phy *sas_phy = &phy->sas_phy;
623 u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, i,
626 prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
627 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
628 SAS_LINK_RATE_1_5_GBPS))
629 max = SAS_LINK_RATE_12_0_GBPS;
631 max = sas_phy->phy->maximum_linkrate;
632 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
633 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
635 hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00);
636 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
637 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
638 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
639 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
640 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
641 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xf2057fff);
642 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
643 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
644 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
645 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
646 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
647 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
648 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
649 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
650 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01);
651 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32);
652 hisi_sas_phy_write32(hisi_hba, i, SAS_EC_INT_COAL_TIME,
654 /* used for 12G negotiate */
655 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
656 hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff);
658 /* get default FFE configuration for BIST */
659 for (j = 0; j < FFE_CFG_MAX; j++) {
660 u32 val = hisi_sas_phy_read32(hisi_hba, i,
661 TXDEEMPH_G1 + (j * 0x4));
662 hisi_hba->debugfs_bist_ffe[i][j] = val;
666 for (i = 0; i < hisi_hba->queue_count; i++) {
668 hisi_sas_write32(hisi_hba,
669 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
670 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
672 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
673 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
675 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
676 HISI_SAS_QUEUE_SLOTS);
678 /* Completion queue */
679 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
680 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
682 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
683 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
685 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
686 HISI_SAS_QUEUE_SLOTS);
690 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
691 lower_32_bits(hisi_hba->itct_dma));
693 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
694 upper_32_bits(hisi_hba->itct_dma));
697 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
698 lower_32_bits(hisi_hba->iost_dma));
700 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
701 upper_32_bits(hisi_hba->iost_dma));
704 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
705 lower_32_bits(hisi_hba->breakpoint_dma));
707 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
708 upper_32_bits(hisi_hba->breakpoint_dma));
710 /* SATA broken msg */
711 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
712 lower_32_bits(hisi_hba->sata_breakpoint_dma));
714 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
715 upper_32_bits(hisi_hba->sata_breakpoint_dma));
717 /* SATA initial fis */
718 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
719 lower_32_bits(hisi_hba->initial_fis_dma));
721 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
722 upper_32_bits(hisi_hba->initial_fis_dma));
724 /* RAS registers init */
725 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
726 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
727 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0);
728 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0);
730 /* LED registers init */
731 hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff);
732 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080);
733 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080);
734 /* Configure blink generator rate A to 1Hz and B to 4Hz */
735 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700);
736 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000);
739 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
741 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
743 cfg &= ~PHY_CFG_DC_OPT_MSK;
744 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
745 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
748 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
750 struct sas_identify_frame identify_frame;
751 u32 *identify_buffer;
753 memset(&identify_frame, 0, sizeof(identify_frame));
754 identify_frame.dev_type = SAS_END_DEVICE;
755 identify_frame.frame_type = 0;
756 identify_frame._un1 = 1;
757 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
758 identify_frame.target_bits = SAS_PROTOCOL_NONE;
759 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
760 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
761 identify_frame.phy_id = phy_no;
762 identify_buffer = (u32 *)(&identify_frame);
764 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
765 __swab32(identify_buffer[0]));
766 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
767 __swab32(identify_buffer[1]));
768 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
769 __swab32(identify_buffer[2]));
770 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
771 __swab32(identify_buffer[3]));
772 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
773 __swab32(identify_buffer[4]));
774 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
775 __swab32(identify_buffer[5]));
778 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
779 struct hisi_sas_device *sas_dev)
781 struct domain_device *device = sas_dev->sas_device;
782 struct device *dev = hisi_hba->dev;
783 u64 qw0, device_id = sas_dev->device_id;
784 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
785 struct domain_device *parent_dev = device->parent;
786 struct asd_sas_port *sas_port = device->port;
787 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
790 memset(itct, 0, sizeof(*itct));
794 switch (sas_dev->dev_type) {
796 case SAS_EDGE_EXPANDER_DEVICE:
797 case SAS_FANOUT_EXPANDER_DEVICE:
798 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
801 case SAS_SATA_PENDING:
802 if (parent_dev && dev_is_expander(parent_dev->dev_type))
803 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
805 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
808 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
812 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
813 (device->linkrate << ITCT_HDR_MCR_OFF) |
814 (1 << ITCT_HDR_VLN_OFF) |
815 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
816 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
817 (port->id << ITCT_HDR_PORT_ID_OFF));
818 itct->qw0 = cpu_to_le64(qw0);
821 memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
822 itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
825 if (!dev_is_sata(device))
826 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
827 (0x1ULL << ITCT_HDR_RTOLT_OFF));
830 static int clear_itct_v3_hw(struct hisi_hba *hisi_hba,
831 struct hisi_sas_device *sas_dev)
833 DECLARE_COMPLETION_ONSTACK(completion);
834 u64 dev_id = sas_dev->device_id;
835 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
836 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
837 struct device *dev = hisi_hba->dev;
839 sas_dev->completion = &completion;
841 /* clear the itct interrupt state */
842 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
843 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
844 ENT_INT_SRC3_ITC_INT_MSK);
846 /* clear the itct table */
847 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
848 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
850 if (!wait_for_completion_timeout(sas_dev->completion,
851 HISI_SAS_CLEAR_ITCT_TIMEOUT)) {
852 dev_warn(dev, "failed to clear ITCT\n");
856 memset(itct, 0, sizeof(struct hisi_sas_itct));
860 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
861 struct domain_device *device)
863 struct hisi_sas_slot *slot, *slot2;
864 struct hisi_sas_device *sas_dev = device->lldd_dev;
865 u32 cfg_abt_set_query_iptt;
867 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
868 CFG_ABT_SET_QUERY_IPTT);
869 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
870 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
871 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
872 (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
873 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
874 cfg_abt_set_query_iptt);
876 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
877 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
878 cfg_abt_set_query_iptt);
879 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
880 1 << CFG_ABT_SET_IPTT_DONE_OFF);
883 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
885 struct device *dev = hisi_hba->dev;
889 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
891 /* Disable all of the PHYs */
892 hisi_sas_stop_phys(hisi_hba);
895 /* Ensure axi bus idle */
896 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
899 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
903 if (ACPI_HANDLE(dev)) {
906 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
907 if (ACPI_FAILURE(s)) {
908 dev_err(dev, "Reset failed\n");
912 dev_err(dev, "no reset method!\n");
919 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
921 struct device *dev = hisi_hba->dev;
922 struct acpi_device *acpi_dev;
923 union acpi_object *obj;
927 rc = reset_hw_v3_hw(hisi_hba);
929 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d\n", rc);
934 init_reg_v3_hw(hisi_hba);
936 if (guid_parse("D5918B4B-37AE-4E10-A99F-E5E8A6EF4C1F", &guid)) {
937 dev_err(dev, "Parse GUID failed\n");
942 * This DSM handles some hardware-related configurations:
943 * 1. Switch over to MSI error handling in kernel
944 * 2. BIOS *may* reset some register values through this method
946 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 0,
947 DSM_FUNC_ERR_HANDLE_MSI, NULL);
949 dev_warn(dev, "can not find DSM method, ignore\n");
953 acpi_dev = ACPI_COMPANION(dev);
954 if (!acpi_device_power_manageable(acpi_dev))
955 dev_notice(dev, "neither _PS0 nor _PR0 is defined\n");
959 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
961 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
963 cfg |= PHY_CFG_ENA_MSK;
964 cfg &= ~PHY_CFG_PHY_RST_MSK;
965 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
968 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
970 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
971 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
972 static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
973 BIT(CHL_INT2_RX_CODE_ERR_OFF) |
974 BIT(CHL_INT2_RX_INVLD_DW_OFF);
977 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk);
979 cfg &= ~PHY_CFG_ENA_MSK;
980 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
984 state = hisi_sas_read32(hisi_hba, PHY_STATE);
985 if (state & BIT(phy_no)) {
986 cfg |= PHY_CFG_PHY_RST_MSK;
987 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
992 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
993 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
994 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
996 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk);
997 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk);
1000 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1002 config_id_frame_v3_hw(hisi_hba, phy_no);
1003 config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
1004 enable_phy_v3_hw(hisi_hba, phy_no);
1007 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1009 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1012 hisi_sas_phy_enable(hisi_hba, phy_no, 0);
1013 if (phy->identify.device_type == SAS_END_DEVICE) {
1014 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1015 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1016 txid_auto | TX_HARDRST_MSK);
1019 hisi_sas_phy_enable(hisi_hba, phy_no, 1);
1022 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
1024 return SAS_LINK_RATE_12_0_GBPS;
1027 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
1031 for (i = 0; i < hisi_hba->n_phy; i++) {
1032 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1033 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1035 if (!sas_phy->phy->enabled)
1038 hisi_sas_phy_enable(hisi_hba, i, 1);
1042 static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1046 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1047 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1048 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1050 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1051 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1052 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1055 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
1058 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1059 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1061 for (i = 0; i < hisi_hba->n_phy; i++)
1062 if (phy_state & BIT(i))
1063 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1069 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
1071 struct hisi_hba *hisi_hba = dq->hisi_hba;
1072 struct hisi_sas_slot *s, *s1, *s2 = NULL;
1073 int dlvry_queue = dq->id;
1076 list_for_each_entry_safe(s, s1, &dq->list, delivery) {
1080 list_del(&s->delivery);
1087 * Ensure that memories for slots built on other CPUs is observed.
1090 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
1092 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
1095 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
1096 struct hisi_sas_slot *slot,
1097 struct hisi_sas_cmd_hdr *hdr,
1098 struct scatterlist *scatter,
1101 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1102 struct scatterlist *sg;
1105 for_each_sg(scatter, sg, n_elem, i) {
1106 struct hisi_sas_sge *entry = &sge_page->sge[i];
1108 entry->addr = cpu_to_le64(sg_dma_address(sg));
1109 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1110 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1111 entry->data_off = 0;
1114 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1116 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1119 static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba,
1120 struct hisi_sas_slot *slot,
1121 struct hisi_sas_cmd_hdr *hdr,
1122 struct scatterlist *scatter,
1125 struct hisi_sas_sge_dif_page *sge_dif_page;
1126 struct scatterlist *sg;
1129 sge_dif_page = hisi_sas_sge_dif_addr_mem(slot);
1131 for_each_sg(scatter, sg, n_elem, i) {
1132 struct hisi_sas_sge *entry = &sge_dif_page->sge[i];
1134 entry->addr = cpu_to_le64(sg_dma_address(sg));
1135 entry->page_ctrl_0 = 0;
1136 entry->page_ctrl_1 = 0;
1137 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1138 entry->data_off = 0;
1141 hdr->dif_prd_table_addr =
1142 cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot));
1144 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF);
1147 static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd)
1149 unsigned char prot_flags = scsi_cmnd->prot_flags;
1151 if (prot_flags & SCSI_PROT_REF_CHECK)
1152 return T10_CHK_APP_TAG_MSK;
1153 return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK;
1156 static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd,
1157 struct hisi_sas_protect_iu_v3_hw *prot)
1159 unsigned char prot_op = scsi_get_prot_op(scsi_cmnd);
1160 unsigned int interval = scsi_prot_interval(scsi_cmnd);
1161 u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmd_to_rq(scsi_cmnd));
1164 case SCSI_PROT_READ_INSERT:
1165 prot->dw0 |= T10_INSRT_EN_MSK;
1166 prot->lbrtgv = lbrt_chk_val;
1168 case SCSI_PROT_READ_STRIP:
1169 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1170 prot->lbrtcv = lbrt_chk_val;
1171 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1173 case SCSI_PROT_READ_PASS:
1174 prot->dw0 |= T10_CHK_EN_MSK;
1175 prot->lbrtcv = lbrt_chk_val;
1176 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1178 case SCSI_PROT_WRITE_INSERT:
1179 prot->dw0 |= T10_INSRT_EN_MSK;
1180 prot->lbrtgv = lbrt_chk_val;
1182 case SCSI_PROT_WRITE_STRIP:
1183 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1184 prot->lbrtcv = lbrt_chk_val;
1186 case SCSI_PROT_WRITE_PASS:
1187 prot->dw0 |= T10_CHK_EN_MSK;
1188 prot->lbrtcv = lbrt_chk_val;
1189 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1192 WARN(1, "prot_op(0x%x) is not valid\n", prot_op);
1200 prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF);
1203 prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF);
1206 WARN(1, "protection interval (0x%x) invalid\n",
1211 prot->dw0 |= INCR_LBRT_MSK;
1214 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
1215 struct hisi_sas_slot *slot)
1217 struct sas_task *task = slot->task;
1218 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1219 struct domain_device *device = task->dev;
1220 struct hisi_sas_device *sas_dev = device->lldd_dev;
1221 struct hisi_sas_port *port = slot->port;
1222 struct sas_ssp_task *ssp_task = &task->ssp_task;
1223 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1224 struct sas_tmf_task *tmf = slot->tmf;
1225 int has_data = 0, priority = !!tmf;
1226 unsigned char prot_op;
1228 u32 dw1 = 0, dw2 = 0, len = 0;
1230 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1231 (2 << CMD_HDR_TLR_CTRL_OFF) |
1232 (port->id << CMD_HDR_PORT_OFF) |
1233 (priority << CMD_HDR_PRIORITY_OFF) |
1234 (1 << CMD_HDR_CMD_OFF)); /* ssp */
1236 dw1 = 1 << CMD_HDR_VDTL_OFF;
1238 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1239 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1241 prot_op = scsi_get_prot_op(scsi_cmnd);
1242 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1243 switch (scsi_cmnd->sc_data_direction) {
1246 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1248 case DMA_FROM_DEVICE:
1250 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1253 dw1 &= ~CMD_HDR_DIR_MSK;
1257 /* map itct entry */
1258 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1260 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1261 + 3) / 4) << CMD_HDR_CFL_OFF) |
1262 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1263 (2 << CMD_HDR_SG_MOD_OFF);
1264 hdr->dw2 = cpu_to_le32(dw2);
1265 hdr->transfer_tags = cpu_to_le32(slot->idx);
1268 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1271 if (scsi_prot_sg_count(scsi_cmnd))
1272 prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr,
1273 scsi_prot_sglist(scsi_cmnd),
1277 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1278 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1280 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1281 sizeof(struct ssp_frame_hdr);
1283 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1285 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
1286 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
1288 buf_cmd[10] = tmf->tmf;
1290 case TMF_ABORT_TASK:
1291 case TMF_QUERY_TASK:
1293 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1295 tmf->tag_of_task_to_be_managed & 0xff;
1302 if (has_data && (prot_op != SCSI_PROT_NORMAL)) {
1303 struct hisi_sas_protect_iu_v3_hw prot;
1306 hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF);
1307 dw1 |= CMD_HDR_PIR_MSK;
1308 buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) +
1309 sizeof(struct ssp_frame_hdr) +
1310 sizeof(struct ssp_command_iu);
1312 memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw));
1313 fill_prot_v3_hw(scsi_cmnd, &prot);
1314 memcpy(buf_cmd_prot, &prot,
1315 sizeof(struct hisi_sas_protect_iu_v3_hw));
1317 * For READ, we need length of info read to memory, while for
1318 * WRITE we need length of data written to the disk.
1320 if (prot_op == SCSI_PROT_WRITE_INSERT ||
1321 prot_op == SCSI_PROT_READ_INSERT ||
1322 prot_op == SCSI_PROT_WRITE_PASS ||
1323 prot_op == SCSI_PROT_READ_PASS) {
1324 unsigned int interval = scsi_prot_interval(scsi_cmnd);
1325 unsigned int ilog2_interval = ilog2(interval);
1327 len = (task->total_xfer_len >> ilog2_interval) * 8;
1331 hdr->dw1 = cpu_to_le32(dw1);
1333 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len);
1336 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
1337 struct hisi_sas_slot *slot)
1339 struct sas_task *task = slot->task;
1340 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1341 struct domain_device *device = task->dev;
1342 struct hisi_sas_port *port = slot->port;
1343 struct scatterlist *sg_req;
1344 struct hisi_sas_device *sas_dev = device->lldd_dev;
1345 dma_addr_t req_dma_addr;
1346 unsigned int req_len;
1349 sg_req = &task->smp_task.smp_req;
1350 req_len = sg_dma_len(sg_req);
1351 req_dma_addr = sg_dma_address(sg_req);
1355 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1356 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1357 (2 << CMD_HDR_CMD_OFF)); /* smp */
1359 /* map itct entry */
1360 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1361 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1362 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1365 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1366 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1369 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1371 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1372 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1375 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1376 struct hisi_sas_slot *slot)
1378 struct sas_task *task = slot->task;
1379 struct domain_device *device = task->dev;
1380 struct domain_device *parent_dev = device->parent;
1381 struct hisi_sas_device *sas_dev = device->lldd_dev;
1382 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1383 struct asd_sas_port *sas_port = device->port;
1384 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1386 int has_data = 0, hdr_tag = 0;
1387 u32 dw1 = 0, dw2 = 0;
1389 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1390 if (parent_dev && dev_is_expander(parent_dev->dev_type))
1391 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1393 hdr->dw0 |= cpu_to_le32(4U << CMD_HDR_CMD_OFF);
1395 switch (task->data_dir) {
1398 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1400 case DMA_FROM_DEVICE:
1402 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1405 dw1 &= ~CMD_HDR_DIR_MSK;
1408 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1409 (task->ata_task.fis.control & ATA_SRST))
1410 dw1 |= 1 << CMD_HDR_RESET_OFF;
1412 dw1 |= (hisi_sas_get_ata_protocol(
1413 &task->ata_task.fis, task->data_dir))
1414 << CMD_HDR_FRAME_TYPE_OFF;
1415 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1417 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
1418 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1420 hdr->dw1 = cpu_to_le32(dw1);
1423 if (task->ata_task.use_ncq) {
1424 struct ata_queued_cmd *qc = task->uldd_task;
1427 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1428 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1431 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1432 2 << CMD_HDR_SG_MOD_OFF;
1433 hdr->dw2 = cpu_to_le32(dw2);
1436 hdr->transfer_tags = cpu_to_le32(slot->idx);
1439 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1442 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1443 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1444 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1446 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1448 if (likely(!task->ata_task.device_control_reg_update))
1449 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1450 /* fill in command FIS */
1451 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1454 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1455 struct hisi_sas_slot *slot)
1457 struct sas_task *task = slot->task;
1458 struct sas_internal_abort_task *abort = &task->abort_task;
1459 struct domain_device *dev = task->dev;
1460 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1461 struct hisi_sas_port *port = slot->port;
1462 struct hisi_sas_device *sas_dev = dev->lldd_dev;
1463 bool sata = dev_is_sata(dev);
1466 hdr->dw0 = cpu_to_le32((5U << CMD_HDR_CMD_OFF) | /* abort */
1467 (port->id << CMD_HDR_PORT_OFF) |
1468 (sata << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1469 (abort->type << CMD_HDR_ABORT_FLAG_OFF));
1472 hdr->dw1 = cpu_to_le32(sas_dev->device_id
1473 << CMD_HDR_DEV_ID_OFF);
1476 hdr->dw7 = cpu_to_le32(abort->tag << CMD_HDR_ABORT_IPTT_OFF);
1477 hdr->transfer_tags = cpu_to_le32(slot->idx);
1480 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1484 u32 context, port_id, link_rate;
1485 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1486 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1487 struct device *dev = hisi_hba->dev;
1489 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1491 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1492 port_id = (port_id >> (4 * phy_no)) & 0xf;
1493 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1494 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1496 if (port_id == 0xf) {
1497 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1501 sas_phy->linkrate = link_rate;
1502 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1504 /* Check for SATA dev */
1505 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1506 if (context & (1 << phy_no)) {
1507 struct hisi_sas_initial_fis *initial_fis;
1508 struct dev_to_host_fis *fis;
1509 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1510 struct Scsi_Host *shost = hisi_hba->shost;
1512 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1513 initial_fis = &hisi_hba->initial_fis[phy_no];
1514 fis = &initial_fis->fis;
1516 /* check ERR bit of Status Register */
1517 if (fis->status & ATA_ERR) {
1518 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n",
1519 phy_no, fis->status);
1520 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1525 sas_phy->oob_mode = SATA_OOB_MODE;
1526 attached_sas_addr[0] = 0x50;
1527 attached_sas_addr[6] = shost->host_no;
1528 attached_sas_addr[7] = phy_no;
1529 memcpy(sas_phy->attached_sas_addr,
1532 memcpy(sas_phy->frame_rcvd, fis,
1533 sizeof(struct dev_to_host_fis));
1534 phy->phy_type |= PORT_TYPE_SATA;
1535 phy->identify.device_type = SAS_SATA_DEV;
1536 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1537 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1539 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1540 struct sas_identify_frame *id =
1541 (struct sas_identify_frame *)frame_rcvd;
1543 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1544 for (i = 0; i < 6; i++) {
1545 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1546 RX_IDAF_DWORD0 + (i * 4));
1547 frame_rcvd[i] = __swab32(idaf);
1549 sas_phy->oob_mode = SAS_OOB_MODE;
1550 memcpy(sas_phy->attached_sas_addr,
1553 phy->phy_type |= PORT_TYPE_SAS;
1554 phy->identify.device_type = id->dev_type;
1555 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1556 if (phy->identify.device_type == SAS_END_DEVICE)
1557 phy->identify.target_port_protocols =
1559 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1560 phy->identify.target_port_protocols =
1564 phy->port_id = port_id;
1567 * Call pm_runtime_get_noresume() which pairs with
1568 * hisi_sas_phyup_pm_work() -> pm_runtime_put_sync().
1569 * For failure call pm_runtime_put() as we are in a hardirq context.
1571 pm_runtime_get_noresume(dev);
1572 res = hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP_PM);
1574 pm_runtime_put(dev);
1578 spin_lock(&phy->lock);
1579 /* Delete timer and set phy_attached atomically */
1580 del_timer(&phy->timer);
1581 phy->phy_attached = 1;
1582 spin_unlock(&phy->lock);
1584 if (phy->reset_completion)
1585 complete(phy->reset_completion);
1586 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1587 CHL_INT0_SL_PHY_ENABLE_MSK);
1588 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1593 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1595 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1596 u32 phy_state, sl_ctrl, txid_auto;
1597 struct device *dev = hisi_hba->dev;
1599 atomic_inc(&phy->down_cnt);
1601 del_timer(&phy->timer);
1602 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1604 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1605 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1606 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0,
1609 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1610 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1611 sl_ctrl&(~SL_CTA_MSK));
1613 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1614 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1615 txid_auto | CT3_MSK);
1617 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1618 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1623 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1625 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1626 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1629 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1630 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
1631 if ((bcast_status & RX_BCAST_CHG_MSK) &&
1632 !test_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags))
1633 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
1635 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1636 CHL_INT0_SL_RX_BCST_ACK_MSK);
1637 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1642 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1644 struct hisi_hba *hisi_hba = p;
1647 irqreturn_t res = IRQ_NONE;
1649 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1653 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1655 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1656 int rdy = phy_state & (1 << phy_no);
1659 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1661 if (phy_up_v3_hw(phy_no, hisi_hba)
1664 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1666 if (phy_bcast_v3_hw(phy_no, hisi_hba)
1670 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1672 if (phy_down_v3_hw(phy_no, hisi_hba)
1684 static const struct hisi_sas_hw_error port_axi_error[] = {
1686 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF),
1687 .msg = "dmac_tx_ecc_bad_err",
1690 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF),
1691 .msg = "dmac_rx_ecc_bad_err",
1694 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1695 .msg = "dma_tx_axi_wr_err",
1698 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1699 .msg = "dma_tx_axi_rd_err",
1702 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1703 .msg = "dma_rx_axi_wr_err",
1706 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1707 .msg = "dma_rx_axi_rd_err",
1710 .irq_msk = BIT(CHL_INT1_DMAC_TX_FIFO_ERR_OFF),
1711 .msg = "dma_tx_fifo_err",
1714 .irq_msk = BIT(CHL_INT1_DMAC_RX_FIFO_ERR_OFF),
1715 .msg = "dma_rx_fifo_err",
1718 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF),
1719 .msg = "dma_tx_axi_ruser_err",
1722 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF),
1723 .msg = "dma_rx_axi_ruser_err",
1727 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1729 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1);
1730 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK);
1731 struct device *dev = hisi_hba->dev;
1734 irq_value &= ~irq_msk;
1736 dev_warn(dev, "phy%d channel int 1 received with status bits cleared\n",
1741 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1742 const struct hisi_sas_hw_error *error = &port_axi_error[i];
1744 if (!(irq_value & error->irq_msk))
1747 dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1748 error->msg, phy_no, irq_value);
1749 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1752 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value);
1755 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1757 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1758 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1759 struct sas_phy *sphy = sas_phy->phy;
1760 unsigned long flags;
1763 spin_lock_irqsave(&phy->lock, flags);
1765 /* loss dword sync */
1766 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1767 sphy->loss_of_dword_sync_count += reg_value;
1769 /* phy reset problem */
1770 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1771 sphy->phy_reset_problem_count += reg_value;
1774 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1775 sphy->invalid_dword_count += reg_value;
1778 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1779 sphy->running_disparity_error_count += reg_value;
1781 /* code violation error */
1782 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
1783 phy->code_violation_err_count += reg_value;
1785 spin_unlock_irqrestore(&phy->lock, flags);
1788 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1790 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
1791 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1792 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1793 struct pci_dev *pci_dev = hisi_hba->pci_dev;
1794 struct device *dev = hisi_hba->dev;
1795 static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
1796 BIT(CHL_INT2_RX_CODE_ERR_OFF) |
1797 BIT(CHL_INT2_RX_INVLD_DW_OFF);
1799 irq_value &= ~irq_msk;
1801 dev_warn(dev, "phy%d channel int 2 received with status bits cleared\n",
1806 if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1807 dev_warn(dev, "phy%d identify timeout\n", phy_no);
1808 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1811 if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1812 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1813 STP_LINK_TIMEOUT_STATE);
1815 dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1817 if (reg_value & BIT(4))
1818 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1821 if (pci_dev->revision > 0x20 && (irq_value & msk)) {
1822 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1823 struct sas_phy *sphy = sas_phy->phy;
1825 phy_get_events_v3_hw(hisi_hba, phy_no);
1827 if (irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF))
1828 dev_info(dev, "phy%d invalid dword cnt: %u\n", phy_no,
1829 sphy->invalid_dword_count);
1831 if (irq_value & BIT(CHL_INT2_RX_CODE_ERR_OFF))
1832 dev_info(dev, "phy%d code violation cnt: %u\n", phy_no,
1833 phy->code_violation_err_count);
1835 if (irq_value & BIT(CHL_INT2_RX_DISP_ERR_OFF))
1836 dev_info(dev, "phy%d disparity error cnt: %u\n", phy_no,
1837 sphy->running_disparity_error_count);
1840 if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) &&
1841 (pci_dev->revision == 0x20)) {
1845 rc = hisi_sas_read32_poll_timeout_atomic(
1846 HILINK_ERR_DFX, reg_value,
1847 !((reg_value >> 8) & BIT(phy_no)),
1850 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1853 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value);
1856 static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1858 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1860 if (irq_value0 & CHL_INT0_PHY_RDY_MSK)
1861 hisi_sas_phy_oob_ready(hisi_hba, phy_no);
1863 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1864 irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1865 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1866 & (~CHL_INT0_NOT_RDY_MSK));
1869 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1871 struct hisi_hba *hisi_hba = p;
1875 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1879 if (irq_msk & (CHNL_INT_STS_INT0_MSK << (phy_no * CHNL_WIDTH)))
1880 handle_chl_int0_v3_hw(hisi_hba, phy_no);
1882 if (irq_msk & (CHNL_INT_STS_INT1_MSK << (phy_no * CHNL_WIDTH)))
1883 handle_chl_int1_v3_hw(hisi_hba, phy_no);
1885 if (irq_msk & (CHNL_INT_STS_INT2_MSK << (phy_no * CHNL_WIDTH)))
1886 handle_chl_int2_v3_hw(hisi_hba, phy_no);
1888 irq_msk &= ~(CHNL_INT_STS_PHY_MSK << (phy_no * CHNL_WIDTH));
1895 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
1897 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
1898 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
1899 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
1900 .msg = "hgc_dqe_eccbad_intr",
1901 .reg = HGC_DQE_ECC_ADDR,
1904 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
1905 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
1906 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
1907 .msg = "hgc_iost_eccbad_intr",
1908 .reg = HGC_IOST_ECC_ADDR,
1911 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
1912 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
1913 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
1914 .msg = "hgc_itct_eccbad_intr",
1915 .reg = HGC_ITCT_ECC_ADDR,
1918 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
1919 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
1920 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
1921 .msg = "hgc_iostl_eccbad_intr",
1922 .reg = HGC_LM_DFX_STATUS2,
1925 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
1926 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
1927 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
1928 .msg = "hgc_itctl_eccbad_intr",
1929 .reg = HGC_LM_DFX_STATUS2,
1932 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
1933 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
1934 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
1935 .msg = "hgc_cqe_eccbad_intr",
1936 .reg = HGC_CQE_ECC_ADDR,
1939 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
1940 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
1941 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
1942 .msg = "rxm_mem0_eccbad_intr",
1943 .reg = HGC_RXM_DFX_STATUS14,
1946 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
1947 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
1948 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
1949 .msg = "rxm_mem1_eccbad_intr",
1950 .reg = HGC_RXM_DFX_STATUS14,
1953 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
1954 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
1955 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
1956 .msg = "rxm_mem2_eccbad_intr",
1957 .reg = HGC_RXM_DFX_STATUS14,
1960 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
1961 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
1962 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
1963 .msg = "rxm_mem3_eccbad_intr",
1964 .reg = HGC_RXM_DFX_STATUS15,
1967 .irq_msk = BIT(SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF),
1968 .msk = AM_ROB_ECC_ERR_ADDR_MSK,
1969 .shift = AM_ROB_ECC_ERR_ADDR_OFF,
1970 .msg = "ooo_ram_eccbad_intr",
1971 .reg = AM_ROB_ECC_ERR_ADDR,
1975 static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba,
1978 struct device *dev = hisi_hba->dev;
1979 const struct hisi_sas_hw_error *ecc_error;
1983 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
1984 ecc_error = &multi_bit_ecc_errors[i];
1985 if (irq_value & ecc_error->irq_msk) {
1986 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
1987 val &= ecc_error->msk;
1988 val >>= ecc_error->shift;
1989 dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n",
1990 ecc_error->msg, irq_value, val);
1991 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1996 static void fatal_ecc_int_v3_hw(struct hisi_hba *hisi_hba)
1998 u32 irq_value, irq_msk;
2000 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
2001 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
2003 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
2005 multi_bit_ecc_error_process_v3_hw(hisi_hba, irq_value);
2007 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
2008 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
2011 static const struct hisi_sas_hw_error axi_error[] = {
2012 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
2013 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
2014 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
2015 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
2016 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
2017 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
2018 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
2019 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
2023 static const struct hisi_sas_hw_error fifo_error[] = {
2024 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
2025 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
2026 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
2027 { .msk = BIT(11), .msg = "CMDP_FIFO" },
2028 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
2032 static const struct hisi_sas_hw_error fatal_axi_error[] = {
2034 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
2035 .msg = "write pointer and depth",
2038 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
2039 .msg = "iptt no match slot",
2042 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
2043 .msg = "read pointer and depth",
2046 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
2047 .reg = HGC_AXI_FIFO_ERR_INFO,
2051 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
2052 .reg = HGC_AXI_FIFO_ERR_INFO,
2056 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
2057 .msg = "LM add/fetch list",
2060 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
2061 .msg = "SAS_HGC_ABT fetch LM list",
2064 .irq_msk = BIT(ENT_INT_SRC3_DQE_POISON_OFF),
2065 .msg = "read dqe poison",
2068 .irq_msk = BIT(ENT_INT_SRC3_IOST_POISON_OFF),
2069 .msg = "read iost poison",
2072 .irq_msk = BIT(ENT_INT_SRC3_ITCT_POISON_OFF),
2073 .msg = "read itct poison",
2076 .irq_msk = BIT(ENT_INT_SRC3_ITCT_NCQ_POISON_OFF),
2077 .msg = "read itct ncq poison",
2082 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
2084 u32 irq_value, irq_msk;
2085 struct hisi_hba *hisi_hba = p;
2086 struct device *dev = hisi_hba->dev;
2087 struct pci_dev *pdev = hisi_hba->pci_dev;
2090 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2091 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
2093 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
2094 irq_value &= ~irq_msk;
2096 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
2097 const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
2099 if (!(irq_value & error->irq_msk))
2103 const struct hisi_sas_hw_error *sub = error->sub;
2104 u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
2106 for (; sub->msk || sub->msg; sub++) {
2107 if (!(err_value & sub->msk))
2110 dev_err(dev, "%s error (0x%x) found!\n",
2111 sub->msg, irq_value);
2112 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2115 dev_err(dev, "%s error (0x%x) found!\n",
2116 error->msg, irq_value);
2117 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2120 if (pdev->revision < 0x21) {
2123 reg_val = hisi_sas_read32(hisi_hba,
2124 AXI_MASTER_CFG_BASE +
2126 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2127 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2128 AM_CTRL_GLOBAL, reg_val);
2132 fatal_ecc_int_v3_hw(hisi_hba);
2134 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
2135 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
2136 u32 dev_id = reg_val & ITCT_DEV_MSK;
2137 struct hisi_sas_device *sas_dev =
2138 &hisi_hba->devices[dev_id];
2140 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
2141 dev_dbg(dev, "clear ITCT ok\n");
2142 complete(sas_dev->completion);
2145 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
2146 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
2152 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
2153 struct hisi_sas_slot *slot)
2155 struct task_status_struct *ts = &task->task_status;
2156 struct hisi_sas_complete_v3_hdr *complete_queue =
2157 hisi_hba->complete_hdr[slot->cmplt_queue];
2158 struct hisi_sas_complete_v3_hdr *complete_hdr =
2159 &complete_queue[slot->cmplt_queue_slot];
2160 struct hisi_sas_err_record_v3 *record =
2161 hisi_sas_status_buf_addr_mem(slot);
2162 u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type);
2163 u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type);
2164 u32 dw3 = le32_to_cpu(complete_hdr->dw3);
2166 switch (task->task_proto) {
2167 case SAS_PROTOCOL_SSP:
2168 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
2170 * If returned response frame is incorrect because of data underflow,
2171 * but I/O information has been written to the host memory, we examine
2174 if (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_GOOD_MSK) &&
2175 (complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))
2178 ts->residual = trans_tx_fail_type;
2179 ts->stat = SAS_DATA_UNDERRUN;
2180 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
2181 ts->stat = SAS_QUEUE_FULL;
2184 ts->stat = SAS_OPEN_REJECT;
2185 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2188 case SAS_PROTOCOL_SATA:
2189 case SAS_PROTOCOL_STP:
2190 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2191 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
2192 ts->residual = trans_tx_fail_type;
2193 ts->stat = SAS_DATA_UNDERRUN;
2194 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
2195 ts->stat = SAS_PHY_DOWN;
2198 ts->stat = SAS_OPEN_REJECT;
2199 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2201 hisi_sas_sata_done(task, slot);
2203 case SAS_PROTOCOL_SMP:
2204 ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
2212 static void slot_complete_v3_hw(struct hisi_hba *hisi_hba,
2213 struct hisi_sas_slot *slot)
2215 struct sas_task *task = slot->task;
2216 struct hisi_sas_device *sas_dev;
2217 struct device *dev = hisi_hba->dev;
2218 struct task_status_struct *ts;
2219 struct domain_device *device;
2220 struct sas_ha_struct *ha;
2221 struct hisi_sas_complete_v3_hdr *complete_queue =
2222 hisi_hba->complete_hdr[slot->cmplt_queue];
2223 struct hisi_sas_complete_v3_hdr *complete_hdr =
2224 &complete_queue[slot->cmplt_queue_slot];
2225 unsigned long flags;
2226 bool is_internal = slot->is_internal;
2229 if (unlikely(!task || !task->lldd_task || !task->dev))
2232 ts = &task->task_status;
2234 ha = device->port->ha;
2235 sas_dev = device->lldd_dev;
2237 spin_lock_irqsave(&task->task_state_lock, flags);
2238 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2239 spin_unlock_irqrestore(&task->task_state_lock, flags);
2241 memset(ts, 0, sizeof(*ts));
2242 ts->resp = SAS_TASK_COMPLETE;
2244 if (unlikely(!sas_dev)) {
2245 dev_dbg(dev, "slot complete: port has not device\n");
2246 ts->stat = SAS_PHY_DOWN;
2250 dw0 = le32_to_cpu(complete_hdr->dw0);
2251 dw1 = le32_to_cpu(complete_hdr->dw1);
2252 dw3 = le32_to_cpu(complete_hdr->dw3);
2255 * Use SAS+TMF status codes
2257 switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) {
2258 case STAT_IO_ABORTED:
2259 /* this IO has been aborted by abort command */
2260 ts->stat = SAS_ABORTED_TASK;
2262 case STAT_IO_COMPLETE:
2263 /* internal abort command complete */
2264 ts->stat = TMF_RESP_FUNC_SUCC;
2266 case STAT_IO_NO_DEVICE:
2267 ts->stat = TMF_RESP_FUNC_COMPLETE;
2269 case STAT_IO_NOT_VALID:
2271 * abort single IO, the controller can't find the IO
2273 ts->stat = TMF_RESP_FUNC_FAILED;
2279 /* check for erroneous completion */
2280 if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
2281 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2283 if (slot_err_v3_hw(hisi_hba, task, slot)) {
2284 if (ts->stat != SAS_DATA_UNDERRUN)
2285 dev_info(dev, "erroneous completion iptt=%d task=%pK dev id=%d addr=%016llx CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n",
2286 slot->idx, task, sas_dev->device_id,
2287 SAS_ADDR(device->sas_addr),
2288 dw0, dw1, complete_hdr->act, dw3,
2289 error_info[0], error_info[1],
2290 error_info[2], error_info[3]);
2291 if (unlikely(slot->abort)) {
2292 sas_task_abort(task);
2299 switch (task->task_proto) {
2300 case SAS_PROTOCOL_SSP: {
2301 struct ssp_response_iu *iu =
2302 hisi_sas_status_buf_addr_mem(slot) +
2303 sizeof(struct hisi_sas_err_record);
2305 sas_ssp_task_response(dev, task, iu);
2308 case SAS_PROTOCOL_SMP: {
2309 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2310 void *to = page_address(sg_page(sg_resp));
2312 ts->stat = SAS_SAM_STAT_GOOD;
2314 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2316 memcpy(to + sg_resp->offset,
2317 hisi_sas_status_buf_addr_mem(slot) +
2318 sizeof(struct hisi_sas_err_record),
2322 case SAS_PROTOCOL_SATA:
2323 case SAS_PROTOCOL_STP:
2324 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2325 ts->stat = SAS_SAM_STAT_GOOD;
2326 hisi_sas_sata_done(task, slot);
2329 ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
2333 if (!slot->port->port_attached) {
2334 dev_warn(dev, "slot complete: port %d has removed\n",
2335 slot->port->sas_port.id);
2336 ts->stat = SAS_PHY_DOWN;
2340 spin_lock_irqsave(&task->task_state_lock, flags);
2341 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
2342 spin_unlock_irqrestore(&task->task_state_lock, flags);
2343 dev_info(dev, "slot complete: task(%pK) aborted\n", task);
2346 task->task_state_flags |= SAS_TASK_STATE_DONE;
2347 spin_unlock_irqrestore(&task->task_state_lock, flags);
2348 hisi_sas_slot_task_free(hisi_hba, task, slot);
2350 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
2351 spin_lock_irqsave(&device->done_lock, flags);
2352 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
2353 spin_unlock_irqrestore(&device->done_lock, flags);
2354 dev_info(dev, "slot complete: task(%pK) ignored\n ",
2358 spin_unlock_irqrestore(&device->done_lock, flags);
2361 if (task->task_done)
2362 task->task_done(task);
2365 static irqreturn_t cq_thread_v3_hw(int irq_no, void *p)
2367 struct hisi_sas_cq *cq = p;
2368 struct hisi_hba *hisi_hba = cq->hisi_hba;
2369 struct hisi_sas_slot *slot;
2370 struct hisi_sas_complete_v3_hdr *complete_queue;
2371 u32 rd_point = cq->rd_point, wr_point;
2374 complete_queue = hisi_hba->complete_hdr[queue];
2376 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
2379 while (rd_point != wr_point) {
2380 struct hisi_sas_complete_v3_hdr *complete_hdr;
2381 struct device *dev = hisi_hba->dev;
2385 complete_hdr = &complete_queue[rd_point];
2386 dw1 = le32_to_cpu(complete_hdr->dw1);
2388 iptt = dw1 & CMPLT_HDR_IPTT_MSK;
2389 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
2390 slot = &hisi_hba->slot_info[iptt];
2391 slot->cmplt_queue_slot = rd_point;
2392 slot->cmplt_queue = queue;
2393 slot_complete_v3_hw(hisi_hba, slot);
2395 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt);
2397 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
2401 /* update rd_point */
2402 cq->rd_point = rd_point;
2403 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
2408 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
2410 struct hisi_sas_cq *cq = p;
2411 struct hisi_hba *hisi_hba = cq->hisi_hba;
2414 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
2416 return IRQ_WAKE_THREAD;
2419 static void hisi_sas_v3_free_vectors(void *data)
2421 struct pci_dev *pdev = data;
2423 pci_free_irq_vectors(pdev);
2426 static int interrupt_preinit_v3_hw(struct hisi_hba *hisi_hba)
2429 int max_msi = HISI_SAS_MSI_COUNT_V3_HW, min_msi;
2430 struct Scsi_Host *shost = hisi_hba->shost;
2431 struct pci_dev *pdev = hisi_hba->pci_dev;
2432 struct irq_affinity desc = {
2433 .pre_vectors = BASE_VECTORS_V3_HW,
2436 min_msi = MIN_AFFINE_VECTORS_V3_HW;
2437 vectors = pci_alloc_irq_vectors_affinity(pdev,
2446 hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW;
2447 shost->nr_hw_queues = hisi_hba->cq_nvecs;
2449 devm_add_action(&pdev->dev, hisi_sas_v3_free_vectors, pdev);
2453 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
2455 struct device *dev = hisi_hba->dev;
2456 struct pci_dev *pdev = hisi_hba->pci_dev;
2459 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
2460 int_phy_up_down_bcast_v3_hw, 0,
2461 DRV_NAME " phy", hisi_hba);
2463 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
2467 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
2468 int_chnl_int_v3_hw, 0,
2469 DRV_NAME " channel", hisi_hba);
2471 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
2475 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
2476 fatal_axi_int_v3_hw, 0,
2477 DRV_NAME " fatal", hisi_hba);
2479 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
2483 if (hisi_sas_intr_conv)
2484 dev_info(dev, "Enable interrupt converge\n");
2486 for (i = 0; i < hisi_hba->cq_nvecs; i++) {
2487 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2488 int nr = hisi_sas_intr_conv ? 16 : 16 + i;
2489 unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED :
2492 cq->irq_no = pci_irq_vector(pdev, nr);
2493 rc = devm_request_threaded_irq(dev, cq->irq_no,
2497 DRV_NAME " cq", cq);
2499 dev_err(dev, "could not request cq%d interrupt, rc=%d\n",
2503 cq->irq_mask = pci_irq_get_affinity(pdev, i + BASE_VECTORS_V3_HW);
2504 if (!cq->irq_mask) {
2505 dev_err(dev, "could not get cq%d irq affinity!\n", i);
2513 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
2517 rc = hw_init_v3_hw(hisi_hba);
2521 rc = interrupt_init_v3_hw(hisi_hba);
2528 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
2529 struct sas_phy_linkrates *r)
2531 enum sas_linkrate max = r->maximum_linkrate;
2532 u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, phy_no,
2533 PROG_PHY_LINK_RATE);
2535 prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
2536 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
2537 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
2538 prog_phy_link_rate);
2541 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
2543 struct pci_dev *pdev = hisi_hba->pci_dev;
2546 synchronize_irq(pci_irq_vector(pdev, 1));
2547 synchronize_irq(pci_irq_vector(pdev, 2));
2548 synchronize_irq(pci_irq_vector(pdev, 11));
2549 for (i = 0; i < hisi_hba->queue_count; i++)
2550 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
2552 for (i = 0; i < hisi_hba->cq_nvecs; i++)
2553 synchronize_irq(pci_irq_vector(pdev, i + 16));
2555 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
2556 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
2557 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
2558 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
2560 for (i = 0; i < hisi_hba->n_phy; i++) {
2561 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
2562 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
2563 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
2564 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
2565 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
2569 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
2571 return hisi_sas_read32(hisi_hba, PHY_STATE);
2574 static int disable_host_v3_hw(struct hisi_hba *hisi_hba)
2576 struct device *dev = hisi_hba->dev;
2577 u32 status, reg_val;
2580 interrupt_disable_v3_hw(hisi_hba);
2581 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2583 hisi_sas_stop_phys(hisi_hba);
2587 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2589 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2590 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2591 AM_CTRL_GLOBAL, reg_val);
2593 /* wait until bus idle */
2594 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
2595 AM_CURR_TRANS_RETURN, status,
2596 status == 0x3, 10, 100);
2598 dev_err(dev, "axi bus is not idle, rc=%d\n", rc);
2605 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
2607 struct device *dev = hisi_hba->dev;
2610 rc = disable_host_v3_hw(hisi_hba);
2612 dev_err(dev, "soft reset: disable host failed rc=%d\n", rc);
2616 hisi_sas_init_mem(hisi_hba);
2618 return hw_init_v3_hw(hisi_hba);
2621 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type,
2622 u8 reg_index, u8 reg_count, u8 *write_data)
2624 struct device *dev = hisi_hba->dev;
2625 u32 *data = (u32 *)write_data;
2629 case SAS_GPIO_REG_TX:
2630 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) {
2631 dev_err(dev, "write gpio: invalid reg range[%d, %d]\n",
2632 reg_index, reg_index + reg_count - 1);
2636 for (i = 0; i < reg_count; i++)
2637 hisi_sas_write32(hisi_hba,
2638 SAS_GPIO_TX_0_1 + (reg_index + i) * 4,
2642 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
2650 static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
2651 int delay_ms, int timeout_ms)
2653 struct device *dev = hisi_hba->dev;
2654 int entries, entries_old = 0, time;
2656 for (time = 0; time < timeout_ms; time += delay_ms) {
2657 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
2658 if (entries == entries_old)
2661 entries_old = entries;
2665 if (time >= timeout_ms) {
2666 dev_dbg(dev, "Wait commands complete timeout!\n");
2670 dev_dbg(dev, "wait commands complete %dms\n", time);
2673 static ssize_t intr_conv_v3_hw_show(struct device *dev,
2674 struct device_attribute *attr, char *buf)
2676 return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv);
2678 static DEVICE_ATTR_RO(intr_conv_v3_hw);
2680 static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba)
2682 /* config those registers between enable and disable PHYs */
2683 hisi_sas_stop_phys(hisi_hba);
2685 if (hisi_hba->intr_coal_ticks == 0 ||
2686 hisi_hba->intr_coal_count == 0) {
2687 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
2688 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
2689 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
2691 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3);
2692 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME,
2693 hisi_hba->intr_coal_ticks);
2694 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT,
2695 hisi_hba->intr_coal_count);
2697 phys_init_v3_hw(hisi_hba);
2700 static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev,
2701 struct device_attribute *attr,
2704 struct Scsi_Host *shost = class_to_shost(dev);
2705 struct hisi_hba *hisi_hba = shost_priv(shost);
2707 return scnprintf(buf, PAGE_SIZE, "%u\n",
2708 hisi_hba->intr_coal_ticks);
2711 static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev,
2712 struct device_attribute *attr,
2713 const char *buf, size_t count)
2715 struct Scsi_Host *shost = class_to_shost(dev);
2716 struct hisi_hba *hisi_hba = shost_priv(shost);
2717 u32 intr_coal_ticks;
2720 ret = kstrtou32(buf, 10, &intr_coal_ticks);
2722 dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2726 if (intr_coal_ticks >= BIT(24)) {
2727 dev_err(dev, "intr_coal_ticks must be less than 2^24!\n");
2731 hisi_hba->intr_coal_ticks = intr_coal_ticks;
2733 config_intr_coal_v3_hw(hisi_hba);
2737 static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw);
2739 static ssize_t intr_coal_count_v3_hw_show(struct device *dev,
2740 struct device_attribute
2743 struct Scsi_Host *shost = class_to_shost(dev);
2744 struct hisi_hba *hisi_hba = shost_priv(shost);
2746 return scnprintf(buf, PAGE_SIZE, "%u\n",
2747 hisi_hba->intr_coal_count);
2750 static ssize_t intr_coal_count_v3_hw_store(struct device *dev,
2751 struct device_attribute
2752 *attr, const char *buf, size_t count)
2754 struct Scsi_Host *shost = class_to_shost(dev);
2755 struct hisi_hba *hisi_hba = shost_priv(shost);
2756 u32 intr_coal_count;
2759 ret = kstrtou32(buf, 10, &intr_coal_count);
2761 dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2765 if (intr_coal_count >= BIT(8)) {
2766 dev_err(dev, "intr_coal_count must be less than 2^8!\n");
2770 hisi_hba->intr_coal_count = intr_coal_count;
2772 config_intr_coal_v3_hw(hisi_hba);
2776 static DEVICE_ATTR_RW(intr_coal_count_v3_hw);
2778 static int slave_configure_v3_hw(struct scsi_device *sdev)
2780 struct Scsi_Host *shost = dev_to_shost(&sdev->sdev_gendev);
2781 struct domain_device *ddev = sdev_to_domain_dev(sdev);
2782 struct hisi_hba *hisi_hba = shost_priv(shost);
2783 struct device *dev = hisi_hba->dev;
2784 int ret = sas_slave_configure(sdev);
2785 unsigned int max_sectors;
2789 if (!dev_is_sata(ddev))
2790 sas_change_queue_depth(sdev, 64);
2792 if (sdev->type == TYPE_ENCLOSURE)
2795 if (!device_link_add(&sdev->sdev_gendev, dev,
2796 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE)) {
2797 if (pm_runtime_enabled(dev)) {
2798 dev_info(dev, "add device link failed, disable runtime PM for the host\n");
2799 pm_runtime_disable(dev);
2803 /* Set according to IOMMU IOVA caching limit */
2804 max_sectors = min_t(size_t, queue_max_hw_sectors(sdev->request_queue),
2805 (PAGE_SIZE * 32) >> SECTOR_SHIFT);
2807 blk_queue_max_hw_sectors(sdev->request_queue, max_sectors);
2812 static struct attribute *host_v3_hw_attrs[] = {
2813 &dev_attr_phy_event_threshold.attr,
2814 &dev_attr_intr_conv_v3_hw.attr,
2815 &dev_attr_intr_coal_ticks_v3_hw.attr,
2816 &dev_attr_intr_coal_count_v3_hw.attr,
2820 ATTRIBUTE_GROUPS(host_v3_hw);
2822 #define HISI_SAS_DEBUGFS_REG(x) {#x, x}
2824 struct hisi_sas_debugfs_reg_lu {
2829 struct hisi_sas_debugfs_reg {
2830 const struct hisi_sas_debugfs_reg_lu *lu;
2835 static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = {
2836 HISI_SAS_DEBUGFS_REG(PHY_CFG),
2837 HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE),
2838 HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE),
2839 HISI_SAS_DEBUGFS_REG(PHY_CTRL),
2840 HISI_SAS_DEBUGFS_REG(SL_CFG),
2841 HISI_SAS_DEBUGFS_REG(AIP_LIMIT),
2842 HISI_SAS_DEBUGFS_REG(SL_CONTROL),
2843 HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS),
2844 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0),
2845 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1),
2846 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2),
2847 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3),
2848 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4),
2849 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5),
2850 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6),
2851 HISI_SAS_DEBUGFS_REG(TXID_AUTO),
2852 HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0),
2853 HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H),
2854 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER),
2855 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE),
2856 HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER),
2857 HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG),
2858 HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG),
2859 HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG),
2860 HISI_SAS_DEBUGFS_REG(CHL_INT0),
2861 HISI_SAS_DEBUGFS_REG(CHL_INT1),
2862 HISI_SAS_DEBUGFS_REG(CHL_INT2),
2863 HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK),
2864 HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK),
2865 HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK),
2866 HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME),
2867 HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN),
2868 HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER),
2869 HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK),
2870 HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK),
2871 HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK),
2872 HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK),
2873 HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK),
2874 HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK),
2875 HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS),
2876 HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS),
2877 HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME),
2878 HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST),
2879 HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB),
2880 HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW),
2881 HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR),
2882 HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR),
2886 static const struct hisi_sas_debugfs_reg debugfs_port_reg = {
2887 .lu = debugfs_port_reg_lu,
2889 .base_off = PORT_BASE,
2892 static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = {
2893 HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE),
2894 HISI_SAS_DEBUGFS_REG(PHY_CONTEXT),
2895 HISI_SAS_DEBUGFS_REG(PHY_STATE),
2896 HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA),
2897 HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE),
2898 HISI_SAS_DEBUGFS_REG(ITCT_CLR),
2899 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO),
2900 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI),
2901 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO),
2902 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI),
2903 HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG),
2904 HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL),
2905 HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL),
2906 HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME),
2907 HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE),
2908 HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME),
2909 HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME),
2910 HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME),
2911 HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME),
2912 HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME),
2913 HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN),
2914 HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME),
2915 HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2),
2916 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT),
2917 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE),
2918 HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS),
2919 HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS),
2920 HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO),
2921 HISI_SAS_DEBUGFS_REG(INT_COAL_EN),
2922 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME),
2923 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT),
2924 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME),
2925 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT),
2926 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC),
2927 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK),
2928 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1),
2929 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2),
2930 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3),
2931 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1),
2932 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2),
2933 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3),
2934 HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK),
2935 HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK),
2936 HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK),
2937 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR),
2938 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK),
2939 HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN),
2940 HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT),
2941 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH),
2942 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR),
2943 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR),
2944 HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG),
2945 HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK),
2946 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH),
2947 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR),
2948 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR),
2949 HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG),
2950 HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG),
2951 HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX),
2952 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0),
2953 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1),
2954 HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1),
2955 HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD),
2959 static const struct hisi_sas_debugfs_reg debugfs_global_reg = {
2960 .lu = debugfs_global_reg_lu,
2964 static const struct hisi_sas_debugfs_reg_lu debugfs_axi_reg_lu[] = {
2965 HISI_SAS_DEBUGFS_REG(AM_CFG_MAX_TRANS),
2966 HISI_SAS_DEBUGFS_REG(AM_CFG_SINGLE_PORT_MAX_TRANS),
2967 HISI_SAS_DEBUGFS_REG(AXI_CFG),
2968 HISI_SAS_DEBUGFS_REG(AM_ROB_ECC_ERR_ADDR),
2972 static const struct hisi_sas_debugfs_reg debugfs_axi_reg = {
2973 .lu = debugfs_axi_reg_lu,
2975 .base_off = AXI_MASTER_CFG_BASE,
2978 static const struct hisi_sas_debugfs_reg_lu debugfs_ras_reg_lu[] = {
2979 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0),
2980 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1),
2981 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0_MASK),
2982 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1_MASK),
2983 HISI_SAS_DEBUGFS_REG(CFG_SAS_RAS_INTR_MASK),
2984 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2),
2985 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2_MASK),
2989 static const struct hisi_sas_debugfs_reg debugfs_ras_reg = {
2990 .lu = debugfs_ras_reg_lu,
2992 .base_off = RAS_BASE,
2995 static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba)
2997 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2999 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
3001 wait_cmds_complete_timeout_v3_hw(hisi_hba, 100, 5000);
3003 hisi_sas_sync_irqs(hisi_hba);
3006 static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba)
3008 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
3009 (u32)((1ULL << hisi_hba->queue_count) - 1));
3011 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
3014 static void read_iost_itct_cache_v3_hw(struct hisi_hba *hisi_hba,
3015 enum hisi_sas_debugfs_cache_type type,
3018 u32 cache_dw_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ *
3019 HISI_SAS_IOST_ITCT_CACHE_NUM;
3020 struct device *dev = hisi_hba->dev;
3024 hisi_sas_write32(hisi_hba, TAB_RD_TYPE, type);
3026 for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_DW_SZ; i++) {
3027 val = hisi_sas_read32(hisi_hba, TAB_DFX);
3028 if (val == 0xffffffff)
3032 if (val != 0xffffffff) {
3033 dev_err(dev, "Issue occurred in reading IOST/ITCT cache!\n");
3037 memset(buf, 0, cache_dw_size * 4);
3040 for (i = 1; i < cache_dw_size; i++)
3041 buf[i] = hisi_sas_read32(hisi_hba, TAB_DFX);
3044 static void hisi_sas_bist_test_prep_v3_hw(struct hisi_hba *hisi_hba)
3047 int phy_no = hisi_hba->debugfs_bist_phy_no;
3051 hisi_sas_phy_enable(hisi_hba, phy_no, 0);
3054 for (i = 0; i < FFE_CFG_MAX; i++)
3055 hisi_sas_phy_write32(hisi_hba, phy_no, TXDEEMPH_G1 + (i * 0x4),
3056 hisi_hba->debugfs_bist_ffe[phy_no][i]);
3059 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
3060 reg_val |= CFG_ALOS_CHK_DISABLE_MSK;
3061 hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
3064 static void hisi_sas_bist_test_restore_v3_hw(struct hisi_hba *hisi_hba)
3067 int phy_no = hisi_hba->debugfs_bist_phy_no;
3069 /* disable loopback */
3070 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL);
3071 reg_val &= ~(CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
3073 hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL, reg_val);
3076 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
3077 reg_val &= ~CFG_ALOS_CHK_DISABLE_MSK;
3078 hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
3080 /* restore the linkrate */
3081 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
3082 /* init OOB link rate as 1.5 Gbits */
3083 reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
3084 reg_val |= (0x8 << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
3085 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, reg_val);
3088 hisi_sas_phy_enable(hisi_hba, phy_no, 1);
3091 #define SAS_PHY_BIST_CODE_INIT 0x1
3092 #define SAS_PHY_BIST_CODE1_INIT 0X80
3093 static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
3095 u32 reg_val, mode_tmp;
3096 u32 linkrate = hisi_hba->debugfs_bist_linkrate;
3097 u32 phy_no = hisi_hba->debugfs_bist_phy_no;
3098 u32 *ffe = hisi_hba->debugfs_bist_ffe[phy_no];
3099 u32 code_mode = hisi_hba->debugfs_bist_code_mode;
3100 u32 path_mode = hisi_hba->debugfs_bist_mode;
3101 u32 *fix_code = &hisi_hba->debugfs_bist_fixed_code[0];
3102 struct device *dev = hisi_hba->dev;
3104 dev_info(dev, "BIST info:phy%d link_rate=%d code_mode=%d path_mode=%d ffe={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x} fixed_code={0x%x, 0x%x}\n",
3105 phy_no, linkrate, code_mode, path_mode,
3106 ffe[FFE_SAS_1_5_GBPS], ffe[FFE_SAS_3_0_GBPS],
3107 ffe[FFE_SAS_6_0_GBPS], ffe[FFE_SAS_12_0_GBPS],
3108 ffe[FFE_SATA_1_5_GBPS], ffe[FFE_SATA_3_0_GBPS],
3109 ffe[FFE_SATA_6_0_GBPS], fix_code[FIXED_CODE],
3110 fix_code[FIXED_CODE_1]);
3111 mode_tmp = path_mode ? 2 : 1;
3113 /* some preparations before bist test */
3114 hisi_sas_bist_test_prep_v3_hw(hisi_hba);
3116 /* set linkrate of bit test*/
3117 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
3118 PROG_PHY_LINK_RATE);
3119 reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
3120 reg_val |= (linkrate << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
3121 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
3124 /* set code mode of bit test */
3125 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
3127 reg_val &= ~(CFG_BIST_MODE_SEL_MSK | CFG_LOOP_TEST_MODE_MSK |
3128 CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
3130 reg_val |= ((code_mode << CFG_BIST_MODE_SEL_OFF) |
3131 (mode_tmp << CFG_LOOP_TEST_MODE_OFF) |
3133 hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
3136 /* set the bist init value */
3137 if (code_mode == HISI_SAS_BIST_CODE_MODE_FIXED_DATA) {
3138 reg_val = hisi_hba->debugfs_bist_fixed_code[0];
3139 hisi_sas_phy_write32(hisi_hba, phy_no,
3140 SAS_PHY_BIST_CODE, reg_val);
3142 reg_val = hisi_hba->debugfs_bist_fixed_code[1];
3143 hisi_sas_phy_write32(hisi_hba, phy_no,
3144 SAS_PHY_BIST_CODE1, reg_val);
3146 hisi_sas_phy_write32(hisi_hba, phy_no,
3148 SAS_PHY_BIST_CODE_INIT);
3149 hisi_sas_phy_write32(hisi_hba, phy_no,
3151 SAS_PHY_BIST_CODE1_INIT);
3155 reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK);
3156 hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
3159 /* clear error bit */
3161 hisi_sas_phy_read32(hisi_hba, phy_no, SAS_BIST_ERR_CNT);
3163 /* disable bist test and recover it */
3164 hisi_hba->debugfs_bist_cnt += hisi_sas_phy_read32(hisi_hba,
3165 phy_no, SAS_BIST_ERR_CNT);
3166 hisi_sas_bist_test_restore_v3_hw(hisi_hba);
3172 static int hisi_sas_map_queues(struct Scsi_Host *shost)
3174 struct hisi_hba *hisi_hba = shost_priv(shost);
3175 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
3177 return blk_mq_pci_map_queues(qmap, hisi_hba->pci_dev,
3178 BASE_VECTORS_V3_HW);
3181 static struct scsi_host_template sht_v3_hw = {
3183 .proc_name = DRV_NAME,
3184 .module = THIS_MODULE,
3185 .queuecommand = sas_queuecommand,
3186 .dma_need_drain = ata_scsi_dma_need_drain,
3187 .target_alloc = sas_target_alloc,
3188 .slave_configure = slave_configure_v3_hw,
3189 .scan_finished = hisi_sas_scan_finished,
3190 .scan_start = hisi_sas_scan_start,
3191 .map_queues = hisi_sas_map_queues,
3192 .change_queue_depth = sas_change_queue_depth,
3193 .bios_param = sas_bios_param,
3195 .sg_tablesize = HISI_SAS_SGE_PAGE_CNT,
3196 .sg_prot_tablesize = HISI_SAS_SGE_PAGE_CNT,
3197 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
3198 .eh_device_reset_handler = sas_eh_device_reset_handler,
3199 .eh_target_reset_handler = sas_eh_target_reset_handler,
3200 .slave_alloc = hisi_sas_slave_alloc,
3201 .target_destroy = sas_target_destroy,
3203 #ifdef CONFIG_COMPAT
3204 .compat_ioctl = sas_ioctl,
3206 .shost_groups = host_v3_hw_groups,
3207 .tag_alloc_policy = BLK_TAG_ALLOC_RR,
3208 .host_reset = hisi_sas_host_reset,
3212 static const struct hisi_sas_hw hisi_sas_v3_hw = {
3213 .setup_itct = setup_itct_v3_hw,
3214 .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
3215 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
3216 .clear_itct = clear_itct_v3_hw,
3217 .sl_notify_ssp = sl_notify_ssp_v3_hw,
3218 .prep_ssp = prep_ssp_v3_hw,
3219 .prep_smp = prep_smp_v3_hw,
3220 .prep_stp = prep_ata_v3_hw,
3221 .prep_abort = prep_abort_v3_hw,
3222 .start_delivery = start_delivery_v3_hw,
3223 .phys_init = phys_init_v3_hw,
3224 .phy_start = start_phy_v3_hw,
3225 .phy_disable = disable_phy_v3_hw,
3226 .phy_hard_reset = phy_hard_reset_v3_hw,
3227 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
3228 .phy_set_linkrate = phy_set_linkrate_v3_hw,
3229 .dereg_device = dereg_device_v3_hw,
3230 .soft_reset = soft_reset_v3_hw,
3231 .get_phys_state = get_phys_state_v3_hw,
3232 .get_events = phy_get_events_v3_hw,
3233 .write_gpio = write_gpio_v3_hw,
3234 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw,
3235 .debugfs_snapshot_regs = debugfs_snapshot_regs_v3_hw,
3238 static struct Scsi_Host *
3239 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
3241 struct Scsi_Host *shost;
3242 struct hisi_hba *hisi_hba;
3243 struct device *dev = &pdev->dev;
3245 shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba));
3247 dev_err(dev, "shost alloc failed\n");
3250 hisi_hba = shost_priv(shost);
3252 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
3253 INIT_WORK(&hisi_hba->debugfs_work, debugfs_work_handler_v3_hw);
3254 hisi_hba->hw = &hisi_sas_v3_hw;
3255 hisi_hba->pci_dev = pdev;
3256 hisi_hba->dev = dev;
3257 hisi_hba->shost = shost;
3258 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
3260 if (prot_mask & ~HISI_SAS_PROT_MASK)
3261 dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n",
3264 hisi_hba->prot_mask = prot_mask;
3266 if (hisi_sas_get_fw_info(hisi_hba) < 0)
3269 if (hisi_sas_alloc(hisi_hba)) {
3270 hisi_sas_free(hisi_hba);
3276 scsi_host_put(shost);
3277 dev_err(dev, "shost alloc failed\n");
3281 static void debugfs_snapshot_cq_reg_v3_hw(struct hisi_hba *hisi_hba)
3283 int queue_entry_size = hisi_hba->hw->complete_hdr_size;
3284 int dump_index = hisi_hba->debugfs_dump_index;
3287 for (i = 0; i < hisi_hba->queue_count; i++)
3288 memcpy(hisi_hba->debugfs_cq[dump_index][i].complete_hdr,
3289 hisi_hba->complete_hdr[i],
3290 HISI_SAS_QUEUE_SLOTS * queue_entry_size);
3293 static void debugfs_snapshot_dq_reg_v3_hw(struct hisi_hba *hisi_hba)
3295 int queue_entry_size = sizeof(struct hisi_sas_cmd_hdr);
3296 int dump_index = hisi_hba->debugfs_dump_index;
3299 for (i = 0; i < hisi_hba->queue_count; i++) {
3300 struct hisi_sas_cmd_hdr *debugfs_cmd_hdr, *cmd_hdr;
3303 debugfs_cmd_hdr = hisi_hba->debugfs_dq[dump_index][i].hdr;
3304 cmd_hdr = hisi_hba->cmd_hdr[i];
3306 for (j = 0; j < HISI_SAS_QUEUE_SLOTS; j++)
3307 memcpy(&debugfs_cmd_hdr[j], &cmd_hdr[j],
3312 static void debugfs_snapshot_port_reg_v3_hw(struct hisi_hba *hisi_hba)
3314 int dump_index = hisi_hba->debugfs_dump_index;
3315 const struct hisi_sas_debugfs_reg *port = &debugfs_port_reg;
3320 for (phy_cnt = 0; phy_cnt < hisi_hba->n_phy; phy_cnt++) {
3321 databuf = hisi_hba->debugfs_port_reg[dump_index][phy_cnt].data;
3322 for (i = 0; i < port->count; i++, databuf++) {
3323 offset = port->base_off + 4 * i;
3324 *databuf = hisi_sas_phy_read32(hisi_hba, phy_cnt,
3330 static void debugfs_snapshot_global_reg_v3_hw(struct hisi_hba *hisi_hba)
3332 int dump_index = hisi_hba->debugfs_dump_index;
3333 u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_GLOBAL].data;
3336 for (i = 0; i < debugfs_axi_reg.count; i++, databuf++)
3337 *databuf = hisi_sas_read32(hisi_hba, 4 * i);
3340 static void debugfs_snapshot_axi_reg_v3_hw(struct hisi_hba *hisi_hba)
3342 int dump_index = hisi_hba->debugfs_dump_index;
3343 u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_AXI].data;
3344 const struct hisi_sas_debugfs_reg *axi = &debugfs_axi_reg;
3347 for (i = 0; i < axi->count; i++, databuf++)
3348 *databuf = hisi_sas_read32(hisi_hba, 4 * i + axi->base_off);
3351 static void debugfs_snapshot_ras_reg_v3_hw(struct hisi_hba *hisi_hba)
3353 int dump_index = hisi_hba->debugfs_dump_index;
3354 u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_RAS].data;
3355 const struct hisi_sas_debugfs_reg *ras = &debugfs_ras_reg;
3358 for (i = 0; i < ras->count; i++, databuf++)
3359 *databuf = hisi_sas_read32(hisi_hba, 4 * i + ras->base_off);
3362 static void debugfs_snapshot_itct_reg_v3_hw(struct hisi_hba *hisi_hba)
3364 int dump_index = hisi_hba->debugfs_dump_index;
3365 void *cachebuf = hisi_hba->debugfs_itct_cache[dump_index].cache;
3366 void *databuf = hisi_hba->debugfs_itct[dump_index].itct;
3367 struct hisi_sas_itct *itct;
3370 read_iost_itct_cache_v3_hw(hisi_hba, HISI_SAS_ITCT_CACHE, cachebuf);
3372 itct = hisi_hba->itct;
3374 for (i = 0; i < HISI_SAS_MAX_ITCT_ENTRIES; i++, itct++) {
3375 memcpy(databuf, itct, sizeof(struct hisi_sas_itct));
3376 databuf += sizeof(struct hisi_sas_itct);
3380 static void debugfs_snapshot_iost_reg_v3_hw(struct hisi_hba *hisi_hba)
3382 int dump_index = hisi_hba->debugfs_dump_index;
3383 int max_command_entries = HISI_SAS_MAX_COMMANDS;
3384 void *cachebuf = hisi_hba->debugfs_iost_cache[dump_index].cache;
3385 void *databuf = hisi_hba->debugfs_iost[dump_index].iost;
3386 struct hisi_sas_iost *iost;
3389 read_iost_itct_cache_v3_hw(hisi_hba, HISI_SAS_IOST_CACHE, cachebuf);
3391 iost = hisi_hba->iost;
3393 for (i = 0; i < max_command_entries; i++, iost++) {
3394 memcpy(databuf, iost, sizeof(struct hisi_sas_iost));
3395 databuf += sizeof(struct hisi_sas_iost);
3400 debugfs_to_reg_name_v3_hw(int off, int base_off,
3401 const struct hisi_sas_debugfs_reg_lu *lu)
3403 for (; lu->name; lu++) {
3404 if (off == lu->off - base_off)
3411 static void debugfs_print_reg_v3_hw(u32 *regs_val, struct seq_file *s,
3412 const struct hisi_sas_debugfs_reg *reg)
3416 for (i = 0; i < reg->count; i++) {
3420 name = debugfs_to_reg_name_v3_hw(off, reg->base_off,
3424 seq_printf(s, "0x%08x 0x%08x %s\n", off,
3427 seq_printf(s, "0x%08x 0x%08x\n", off,
3432 static int debugfs_global_v3_hw_show(struct seq_file *s, void *p)
3434 struct hisi_sas_debugfs_regs *global = s->private;
3436 debugfs_print_reg_v3_hw(global->data, s,
3437 &debugfs_global_reg);
3441 DEFINE_SHOW_ATTRIBUTE(debugfs_global_v3_hw);
3443 static int debugfs_axi_v3_hw_show(struct seq_file *s, void *p)
3445 struct hisi_sas_debugfs_regs *axi = s->private;
3447 debugfs_print_reg_v3_hw(axi->data, s,
3452 DEFINE_SHOW_ATTRIBUTE(debugfs_axi_v3_hw);
3454 static int debugfs_ras_v3_hw_show(struct seq_file *s, void *p)
3456 struct hisi_sas_debugfs_regs *ras = s->private;
3458 debugfs_print_reg_v3_hw(ras->data, s,
3463 DEFINE_SHOW_ATTRIBUTE(debugfs_ras_v3_hw);
3465 static int debugfs_port_v3_hw_show(struct seq_file *s, void *p)
3467 struct hisi_sas_debugfs_port *port = s->private;
3468 const struct hisi_sas_debugfs_reg *reg_port = &debugfs_port_reg;
3470 debugfs_print_reg_v3_hw(port->data, s, reg_port);
3474 DEFINE_SHOW_ATTRIBUTE(debugfs_port_v3_hw);
3476 static void debugfs_show_row_64_v3_hw(struct seq_file *s, int index,
3477 int sz, __le64 *ptr)
3481 /* completion header size not fixed per HW version */
3482 seq_printf(s, "index %04d:\n\t", index);
3483 for (i = 1; i <= sz / 8; i++, ptr++) {
3484 seq_printf(s, " 0x%016llx", le64_to_cpu(*ptr));
3486 seq_puts(s, "\n\t");
3492 static void debugfs_show_row_32_v3_hw(struct seq_file *s, int index,
3493 int sz, __le32 *ptr)
3497 /* completion header size not fixed per HW version */
3498 seq_printf(s, "index %04d:\n\t", index);
3499 for (i = 1; i <= sz / 4; i++, ptr++) {
3500 seq_printf(s, " 0x%08x", le32_to_cpu(*ptr));
3502 seq_puts(s, "\n\t");
3507 static void debugfs_cq_show_slot_v3_hw(struct seq_file *s, int slot,
3508 struct hisi_sas_debugfs_cq *debugfs_cq)
3510 struct hisi_sas_cq *cq = debugfs_cq->cq;
3511 struct hisi_hba *hisi_hba = cq->hisi_hba;
3512 __le32 *complete_hdr = debugfs_cq->complete_hdr +
3513 (hisi_hba->hw->complete_hdr_size * slot);
3515 debugfs_show_row_32_v3_hw(s, slot,
3516 hisi_hba->hw->complete_hdr_size,
3520 static int debugfs_cq_v3_hw_show(struct seq_file *s, void *p)
3522 struct hisi_sas_debugfs_cq *debugfs_cq = s->private;
3525 for (slot = 0; slot < HISI_SAS_QUEUE_SLOTS; slot++)
3526 debugfs_cq_show_slot_v3_hw(s, slot, debugfs_cq);
3530 DEFINE_SHOW_ATTRIBUTE(debugfs_cq_v3_hw);
3532 static void debugfs_dq_show_slot_v3_hw(struct seq_file *s, int slot,
3535 struct hisi_sas_debugfs_dq *debugfs_dq = dq_ptr;
3536 void *cmd_queue = debugfs_dq->hdr;
3537 __le32 *cmd_hdr = cmd_queue +
3538 sizeof(struct hisi_sas_cmd_hdr) * slot;
3540 debugfs_show_row_32_v3_hw(s, slot, sizeof(struct hisi_sas_cmd_hdr),
3544 static int debugfs_dq_v3_hw_show(struct seq_file *s, void *p)
3548 for (slot = 0; slot < HISI_SAS_QUEUE_SLOTS; slot++)
3549 debugfs_dq_show_slot_v3_hw(s, slot, s->private);
3553 DEFINE_SHOW_ATTRIBUTE(debugfs_dq_v3_hw);
3555 static int debugfs_iost_v3_hw_show(struct seq_file *s, void *p)
3557 struct hisi_sas_debugfs_iost *debugfs_iost = s->private;
3558 struct hisi_sas_iost *iost = debugfs_iost->iost;
3559 int i, max_command_entries = HISI_SAS_MAX_COMMANDS;
3561 for (i = 0; i < max_command_entries; i++, iost++) {
3562 __le64 *data = &iost->qw0;
3564 debugfs_show_row_64_v3_hw(s, i, sizeof(*iost), data);
3569 DEFINE_SHOW_ATTRIBUTE(debugfs_iost_v3_hw);
3571 static int debugfs_iost_cache_v3_hw_show(struct seq_file *s, void *p)
3573 struct hisi_sas_debugfs_iost_cache *debugfs_iost_cache = s->private;
3574 struct hisi_sas_iost_itct_cache *iost_cache =
3575 debugfs_iost_cache->cache;
3576 u32 cache_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * 4;
3580 for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_NUM; i++, iost_cache++) {
3582 * Data struct of IOST cache:
3583 * Data[1]: BIT0~15: Table index
3585 * Data[2]~[9]: IOST table
3587 tab_idx = (iost_cache->data[1] & 0xffff);
3588 iost = (__le64 *)iost_cache;
3590 debugfs_show_row_64_v3_hw(s, tab_idx, cache_size, iost);
3595 DEFINE_SHOW_ATTRIBUTE(debugfs_iost_cache_v3_hw);
3597 static int debugfs_itct_v3_hw_show(struct seq_file *s, void *p)
3600 struct hisi_sas_debugfs_itct *debugfs_itct = s->private;
3601 struct hisi_sas_itct *itct = debugfs_itct->itct;
3603 for (i = 0; i < HISI_SAS_MAX_ITCT_ENTRIES; i++, itct++) {
3604 __le64 *data = &itct->qw0;
3606 debugfs_show_row_64_v3_hw(s, i, sizeof(*itct), data);
3611 DEFINE_SHOW_ATTRIBUTE(debugfs_itct_v3_hw);
3613 static int debugfs_itct_cache_v3_hw_show(struct seq_file *s, void *p)
3615 struct hisi_sas_debugfs_itct_cache *debugfs_itct_cache = s->private;
3616 struct hisi_sas_iost_itct_cache *itct_cache =
3617 debugfs_itct_cache->cache;
3618 u32 cache_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * 4;
3622 for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_NUM; i++, itct_cache++) {
3624 * Data struct of ITCT cache:
3625 * Data[1]: BIT0~15: Table index
3627 * Data[2]~[9]: ITCT table
3629 tab_idx = itct_cache->data[1] & 0xffff;
3630 itct = (__le64 *)itct_cache;
3632 debugfs_show_row_64_v3_hw(s, tab_idx, cache_size, itct);
3637 DEFINE_SHOW_ATTRIBUTE(debugfs_itct_cache_v3_hw);
3639 static void debugfs_create_files_v3_hw(struct hisi_hba *hisi_hba)
3641 u64 *debugfs_timestamp;
3642 int dump_index = hisi_hba->debugfs_dump_index;
3643 struct dentry *dump_dentry;
3644 struct dentry *dentry;
3650 snprintf(name, 256, "%d", dump_index);
3652 dump_dentry = debugfs_create_dir(name, hisi_hba->debugfs_dump_dentry);
3654 debugfs_timestamp = &hisi_hba->debugfs_timestamp[dump_index];
3656 debugfs_create_u64("timestamp", 0400, dump_dentry,
3659 debugfs_create_file("global", 0400, dump_dentry,
3660 &hisi_hba->debugfs_regs[dump_index][DEBUGFS_GLOBAL],
3661 &debugfs_global_v3_hw_fops);
3663 /* Create port dir and files */
3664 dentry = debugfs_create_dir("port", dump_dentry);
3665 for (p = 0; p < hisi_hba->n_phy; p++) {
3666 snprintf(name, 256, "%d", p);
3668 debugfs_create_file(name, 0400, dentry,
3669 &hisi_hba->debugfs_port_reg[dump_index][p],
3670 &debugfs_port_v3_hw_fops);
3673 /* Create CQ dir and files */
3674 dentry = debugfs_create_dir("cq", dump_dentry);
3675 for (c = 0; c < hisi_hba->queue_count; c++) {
3676 snprintf(name, 256, "%d", c);
3678 debugfs_create_file(name, 0400, dentry,
3679 &hisi_hba->debugfs_cq[dump_index][c],
3680 &debugfs_cq_v3_hw_fops);
3683 /* Create DQ dir and files */
3684 dentry = debugfs_create_dir("dq", dump_dentry);
3685 for (d = 0; d < hisi_hba->queue_count; d++) {
3686 snprintf(name, 256, "%d", d);
3688 debugfs_create_file(name, 0400, dentry,
3689 &hisi_hba->debugfs_dq[dump_index][d],
3690 &debugfs_dq_v3_hw_fops);
3693 debugfs_create_file("iost", 0400, dump_dentry,
3694 &hisi_hba->debugfs_iost[dump_index],
3695 &debugfs_iost_v3_hw_fops);
3697 debugfs_create_file("iost_cache", 0400, dump_dentry,
3698 &hisi_hba->debugfs_iost_cache[dump_index],
3699 &debugfs_iost_cache_v3_hw_fops);
3701 debugfs_create_file("itct", 0400, dump_dentry,
3702 &hisi_hba->debugfs_itct[dump_index],
3703 &debugfs_itct_v3_hw_fops);
3705 debugfs_create_file("itct_cache", 0400, dump_dentry,
3706 &hisi_hba->debugfs_itct_cache[dump_index],
3707 &debugfs_itct_cache_v3_hw_fops);
3709 debugfs_create_file("axi", 0400, dump_dentry,
3710 &hisi_hba->debugfs_regs[dump_index][DEBUGFS_AXI],
3711 &debugfs_axi_v3_hw_fops);
3713 debugfs_create_file("ras", 0400, dump_dentry,
3714 &hisi_hba->debugfs_regs[dump_index][DEBUGFS_RAS],
3715 &debugfs_ras_v3_hw_fops);
3718 static void debugfs_snapshot_regs_v3_hw(struct hisi_hba *hisi_hba)
3720 int debugfs_dump_index = hisi_hba->debugfs_dump_index;
3721 struct device *dev = hisi_hba->dev;
3722 u64 timestamp = local_clock();
3724 if (debugfs_dump_index >= hisi_sas_debugfs_dump_count) {
3725 dev_warn(dev, "dump count exceeded!\n");
3729 do_div(timestamp, NSEC_PER_MSEC);
3730 hisi_hba->debugfs_timestamp[debugfs_dump_index] = timestamp;
3732 debugfs_snapshot_prepare_v3_hw(hisi_hba);
3734 debugfs_snapshot_global_reg_v3_hw(hisi_hba);
3735 debugfs_snapshot_port_reg_v3_hw(hisi_hba);
3736 debugfs_snapshot_axi_reg_v3_hw(hisi_hba);
3737 debugfs_snapshot_ras_reg_v3_hw(hisi_hba);
3738 debugfs_snapshot_cq_reg_v3_hw(hisi_hba);
3739 debugfs_snapshot_dq_reg_v3_hw(hisi_hba);
3740 debugfs_snapshot_itct_reg_v3_hw(hisi_hba);
3741 debugfs_snapshot_iost_reg_v3_hw(hisi_hba);
3743 debugfs_create_files_v3_hw(hisi_hba);
3745 debugfs_snapshot_restore_v3_hw(hisi_hba);
3746 hisi_hba->debugfs_dump_index++;
3749 static ssize_t debugfs_trigger_dump_v3_hw_write(struct file *file,
3750 const char __user *user_buf,
3751 size_t count, loff_t *ppos)
3753 struct hisi_hba *hisi_hba = file->f_inode->i_private;
3756 if (hisi_hba->debugfs_dump_index >= hisi_sas_debugfs_dump_count)
3762 if (copy_from_user(buf, user_buf, count))
3768 queue_work(hisi_hba->wq, &hisi_hba->debugfs_work);
3773 static const struct file_operations debugfs_trigger_dump_v3_hw_fops = {
3774 .write = &debugfs_trigger_dump_v3_hw_write,
3775 .owner = THIS_MODULE,
3779 HISI_SAS_BIST_LOOPBACK_MODE_DIGITAL = 0,
3780 HISI_SAS_BIST_LOOPBACK_MODE_SERDES,
3781 HISI_SAS_BIST_LOOPBACK_MODE_REMOTE,
3784 static const struct {
3787 } debugfs_loop_linkrate_v3_hw[] = {
3788 { SAS_LINK_RATE_1_5_GBPS, "1.5 Gbit" },
3789 { SAS_LINK_RATE_3_0_GBPS, "3.0 Gbit" },
3790 { SAS_LINK_RATE_6_0_GBPS, "6.0 Gbit" },
3791 { SAS_LINK_RATE_12_0_GBPS, "12.0 Gbit" },
3794 static int debugfs_bist_linkrate_v3_hw_show(struct seq_file *s, void *p)
3796 struct hisi_hba *hisi_hba = s->private;
3799 for (i = 0; i < ARRAY_SIZE(debugfs_loop_linkrate_v3_hw); i++) {
3800 int match = (hisi_hba->debugfs_bist_linkrate ==
3801 debugfs_loop_linkrate_v3_hw[i].value);
3803 seq_printf(s, "%s%s%s ", match ? "[" : "",
3804 debugfs_loop_linkrate_v3_hw[i].name,
3812 static ssize_t debugfs_bist_linkrate_v3_hw_write(struct file *filp,
3813 const char __user *buf,
3814 size_t count, loff_t *ppos)
3816 struct seq_file *m = filp->private_data;
3817 struct hisi_hba *hisi_hba = m->private;
3818 char kbuf[16] = {}, *pkbuf;
3822 if (hisi_hba->debugfs_bist_enable)
3825 if (count >= sizeof(kbuf))
3828 if (copy_from_user(kbuf, buf, count))
3831 pkbuf = strstrip(kbuf);
3833 for (i = 0; i < ARRAY_SIZE(debugfs_loop_linkrate_v3_hw); i++) {
3834 if (!strncmp(debugfs_loop_linkrate_v3_hw[i].name,
3836 hisi_hba->debugfs_bist_linkrate =
3837 debugfs_loop_linkrate_v3_hw[i].value;
3849 static int debugfs_bist_linkrate_v3_hw_open(struct inode *inode,
3852 return single_open(filp, debugfs_bist_linkrate_v3_hw_show,
3856 static const struct file_operations debugfs_bist_linkrate_v3_hw_fops = {
3857 .open = debugfs_bist_linkrate_v3_hw_open,
3859 .write = debugfs_bist_linkrate_v3_hw_write,
3860 .llseek = seq_lseek,
3861 .release = single_release,
3862 .owner = THIS_MODULE,
3865 static const struct {
3868 } debugfs_loop_code_mode_v3_hw[] = {
3869 { HISI_SAS_BIST_CODE_MODE_PRBS7, "PRBS7" },
3870 { HISI_SAS_BIST_CODE_MODE_PRBS23, "PRBS23" },
3871 { HISI_SAS_BIST_CODE_MODE_PRBS31, "PRBS31" },
3872 { HISI_SAS_BIST_CODE_MODE_JTPAT, "JTPAT" },
3873 { HISI_SAS_BIST_CODE_MODE_CJTPAT, "CJTPAT" },
3874 { HISI_SAS_BIST_CODE_MODE_SCRAMBED_0, "SCRAMBED_0" },
3875 { HISI_SAS_BIST_CODE_MODE_TRAIN, "TRAIN" },
3876 { HISI_SAS_BIST_CODE_MODE_TRAIN_DONE, "TRAIN_DONE" },
3877 { HISI_SAS_BIST_CODE_MODE_HFTP, "HFTP" },
3878 { HISI_SAS_BIST_CODE_MODE_MFTP, "MFTP" },
3879 { HISI_SAS_BIST_CODE_MODE_LFTP, "LFTP" },
3880 { HISI_SAS_BIST_CODE_MODE_FIXED_DATA, "FIXED_DATA" },
3883 static int debugfs_bist_code_mode_v3_hw_show(struct seq_file *s, void *p)
3885 struct hisi_hba *hisi_hba = s->private;
3888 for (i = 0; i < ARRAY_SIZE(debugfs_loop_code_mode_v3_hw); i++) {
3889 int match = (hisi_hba->debugfs_bist_code_mode ==
3890 debugfs_loop_code_mode_v3_hw[i].value);
3892 seq_printf(s, "%s%s%s ", match ? "[" : "",
3893 debugfs_loop_code_mode_v3_hw[i].name,
3901 static ssize_t debugfs_bist_code_mode_v3_hw_write(struct file *filp,
3902 const char __user *buf,
3906 struct seq_file *m = filp->private_data;
3907 struct hisi_hba *hisi_hba = m->private;
3908 char kbuf[16] = {}, *pkbuf;
3912 if (hisi_hba->debugfs_bist_enable)
3915 if (count >= sizeof(kbuf))
3918 if (copy_from_user(kbuf, buf, count))
3921 pkbuf = strstrip(kbuf);
3923 for (i = 0; i < ARRAY_SIZE(debugfs_loop_code_mode_v3_hw); i++) {
3924 if (!strncmp(debugfs_loop_code_mode_v3_hw[i].name,
3926 hisi_hba->debugfs_bist_code_mode =
3927 debugfs_loop_code_mode_v3_hw[i].value;
3939 static int debugfs_bist_code_mode_v3_hw_open(struct inode *inode,
3942 return single_open(filp, debugfs_bist_code_mode_v3_hw_show,
3946 static const struct file_operations debugfs_bist_code_mode_v3_hw_fops = {
3947 .open = debugfs_bist_code_mode_v3_hw_open,
3949 .write = debugfs_bist_code_mode_v3_hw_write,
3950 .llseek = seq_lseek,
3951 .release = single_release,
3952 .owner = THIS_MODULE,
3955 static ssize_t debugfs_bist_phy_v3_hw_write(struct file *filp,
3956 const char __user *buf,
3957 size_t count, loff_t *ppos)
3959 struct seq_file *m = filp->private_data;
3960 struct hisi_hba *hisi_hba = m->private;
3961 unsigned int phy_no;
3964 if (hisi_hba->debugfs_bist_enable)
3967 val = kstrtouint_from_user(buf, count, 0, &phy_no);
3971 if (phy_no >= hisi_hba->n_phy)
3974 hisi_hba->debugfs_bist_phy_no = phy_no;
3979 static int debugfs_bist_phy_v3_hw_show(struct seq_file *s, void *p)
3981 struct hisi_hba *hisi_hba = s->private;
3983 seq_printf(s, "%d\n", hisi_hba->debugfs_bist_phy_no);
3988 static int debugfs_bist_phy_v3_hw_open(struct inode *inode,
3991 return single_open(filp, debugfs_bist_phy_v3_hw_show,
3995 static const struct file_operations debugfs_bist_phy_v3_hw_fops = {
3996 .open = debugfs_bist_phy_v3_hw_open,
3998 .write = debugfs_bist_phy_v3_hw_write,
3999 .llseek = seq_lseek,
4000 .release = single_release,
4001 .owner = THIS_MODULE,
4004 static ssize_t debugfs_bist_cnt_v3_hw_write(struct file *filp,
4005 const char __user *buf,
4006 size_t count, loff_t *ppos)
4008 struct seq_file *m = filp->private_data;
4009 struct hisi_hba *hisi_hba = m->private;
4013 if (hisi_hba->debugfs_bist_enable)
4016 val = kstrtouint_from_user(buf, count, 0, &cnt);
4023 hisi_hba->debugfs_bist_cnt = 0;
4027 static int debugfs_bist_cnt_v3_hw_show(struct seq_file *s, void *p)
4029 struct hisi_hba *hisi_hba = s->private;
4031 seq_printf(s, "%u\n", hisi_hba->debugfs_bist_cnt);
4036 static int debugfs_bist_cnt_v3_hw_open(struct inode *inode,
4039 return single_open(filp, debugfs_bist_cnt_v3_hw_show,
4043 static const struct file_operations debugfs_bist_cnt_v3_hw_ops = {
4044 .open = debugfs_bist_cnt_v3_hw_open,
4046 .write = debugfs_bist_cnt_v3_hw_write,
4047 .llseek = seq_lseek,
4048 .release = single_release,
4049 .owner = THIS_MODULE,
4052 static const struct {
4055 } debugfs_loop_modes_v3_hw[] = {
4056 { HISI_SAS_BIST_LOOPBACK_MODE_DIGITAL, "digital" },
4057 { HISI_SAS_BIST_LOOPBACK_MODE_SERDES, "serdes" },
4058 { HISI_SAS_BIST_LOOPBACK_MODE_REMOTE, "remote" },
4061 static int debugfs_bist_mode_v3_hw_show(struct seq_file *s, void *p)
4063 struct hisi_hba *hisi_hba = s->private;
4066 for (i = 0; i < ARRAY_SIZE(debugfs_loop_modes_v3_hw); i++) {
4067 int match = (hisi_hba->debugfs_bist_mode ==
4068 debugfs_loop_modes_v3_hw[i].value);
4070 seq_printf(s, "%s%s%s ", match ? "[" : "",
4071 debugfs_loop_modes_v3_hw[i].name,
4079 static ssize_t debugfs_bist_mode_v3_hw_write(struct file *filp,
4080 const char __user *buf,
4081 size_t count, loff_t *ppos)
4083 struct seq_file *m = filp->private_data;
4084 struct hisi_hba *hisi_hba = m->private;
4085 char kbuf[16] = {}, *pkbuf;
4089 if (hisi_hba->debugfs_bist_enable)
4092 if (count >= sizeof(kbuf))
4095 if (copy_from_user(kbuf, buf, count))
4098 pkbuf = strstrip(kbuf);
4100 for (i = 0; i < ARRAY_SIZE(debugfs_loop_modes_v3_hw); i++) {
4101 if (!strncmp(debugfs_loop_modes_v3_hw[i].name, pkbuf, 16)) {
4102 hisi_hba->debugfs_bist_mode =
4103 debugfs_loop_modes_v3_hw[i].value;
4115 static int debugfs_bist_mode_v3_hw_open(struct inode *inode,
4118 return single_open(filp, debugfs_bist_mode_v3_hw_show,
4122 static const struct file_operations debugfs_bist_mode_v3_hw_fops = {
4123 .open = debugfs_bist_mode_v3_hw_open,
4125 .write = debugfs_bist_mode_v3_hw_write,
4126 .llseek = seq_lseek,
4127 .release = single_release,
4128 .owner = THIS_MODULE,
4131 static ssize_t debugfs_bist_enable_v3_hw_write(struct file *filp,
4132 const char __user *buf,
4133 size_t count, loff_t *ppos)
4135 struct seq_file *m = filp->private_data;
4136 struct hisi_hba *hisi_hba = m->private;
4137 unsigned int enable;
4140 val = kstrtouint_from_user(buf, count, 0, &enable);
4147 if (enable == hisi_hba->debugfs_bist_enable)
4150 val = debugfs_set_bist_v3_hw(hisi_hba, enable);
4154 hisi_hba->debugfs_bist_enable = enable;
4159 static int debugfs_bist_enable_v3_hw_show(struct seq_file *s, void *p)
4161 struct hisi_hba *hisi_hba = s->private;
4163 seq_printf(s, "%d\n", hisi_hba->debugfs_bist_enable);
4168 static int debugfs_bist_enable_v3_hw_open(struct inode *inode,
4171 return single_open(filp, debugfs_bist_enable_v3_hw_show,
4175 static const struct file_operations debugfs_bist_enable_v3_hw_fops = {
4176 .open = debugfs_bist_enable_v3_hw_open,
4178 .write = debugfs_bist_enable_v3_hw_write,
4179 .llseek = seq_lseek,
4180 .release = single_release,
4181 .owner = THIS_MODULE,
4184 static const struct {
4186 } debugfs_ffe_name_v3_hw[FFE_CFG_MAX] = {
4190 { "SAS_12_0_GBPS" },
4192 { "SATA_1_5_GBPS" },
4193 { "SATA_3_0_GBPS" },
4194 { "SATA_6_0_GBPS" },
4197 static ssize_t debugfs_v3_hw_write(struct file *filp,
4198 const char __user *buf,
4199 size_t count, loff_t *ppos)
4201 struct seq_file *m = filp->private_data;
4202 u32 *val = m->private;
4205 res = kstrtouint_from_user(buf, count, 0, val);
4212 static int debugfs_v3_hw_show(struct seq_file *s, void *p)
4214 u32 *val = s->private;
4216 seq_printf(s, "0x%x\n", *val);
4221 static int debugfs_v3_hw_open(struct inode *inode, struct file *filp)
4223 return single_open(filp, debugfs_v3_hw_show,
4227 static const struct file_operations debugfs_v3_hw_fops = {
4228 .open = debugfs_v3_hw_open,
4230 .write = debugfs_v3_hw_write,
4231 .llseek = seq_lseek,
4232 .release = single_release,
4233 .owner = THIS_MODULE,
4236 static ssize_t debugfs_phy_down_cnt_v3_hw_write(struct file *filp,
4237 const char __user *buf,
4238 size_t count, loff_t *ppos)
4240 struct seq_file *s = filp->private_data;
4241 struct hisi_sas_phy *phy = s->private;
4242 unsigned int set_val;
4245 res = kstrtouint_from_user(buf, count, 0, &set_val);
4252 atomic_set(&phy->down_cnt, 0);
4257 static int debugfs_phy_down_cnt_v3_hw_show(struct seq_file *s, void *p)
4259 struct hisi_sas_phy *phy = s->private;
4261 seq_printf(s, "%d\n", atomic_read(&phy->down_cnt));
4266 static int debugfs_phy_down_cnt_v3_hw_open(struct inode *inode,
4269 return single_open(filp, debugfs_phy_down_cnt_v3_hw_show,
4273 static const struct file_operations debugfs_phy_down_cnt_v3_hw_fops = {
4274 .open = debugfs_phy_down_cnt_v3_hw_open,
4276 .write = debugfs_phy_down_cnt_v3_hw_write,
4277 .llseek = seq_lseek,
4278 .release = single_release,
4279 .owner = THIS_MODULE,
4282 enum fifo_dump_mode_v3_hw {
4283 FIFO_DUMP_FORVER = (1U << 0),
4284 FIFO_DUMP_AFTER_TRIGGER = (1U << 1),
4285 FIFO_DUMP_UNTILL_TRIGGER = (1U << 2),
4288 enum fifo_trigger_mode_v3_hw {
4289 FIFO_TRIGGER_EDGE = (1U << 0),
4290 FIFO_TRIGGER_SAME_LEVEL = (1U << 1),
4291 FIFO_TRIGGER_DIFF_LEVEL = (1U << 2),
4294 static int debugfs_is_fifo_config_valid_v3_hw(struct hisi_sas_phy *phy)
4296 struct hisi_hba *hisi_hba = phy->hisi_hba;
4298 if (phy->fifo.signal_sel > 0xf) {
4299 dev_info(hisi_hba->dev, "Invalid signal select: %u\n",
4300 phy->fifo.signal_sel);
4304 switch (phy->fifo.dump_mode) {
4305 case FIFO_DUMP_FORVER:
4306 case FIFO_DUMP_AFTER_TRIGGER:
4307 case FIFO_DUMP_UNTILL_TRIGGER:
4310 dev_info(hisi_hba->dev, "Invalid dump mode: %u\n",
4311 phy->fifo.dump_mode);
4315 /* when FIFO_DUMP_FORVER, no need to check trigger_mode */
4316 if (phy->fifo.dump_mode == FIFO_DUMP_FORVER)
4319 switch (phy->fifo.trigger_mode) {
4320 case FIFO_TRIGGER_EDGE:
4321 case FIFO_TRIGGER_SAME_LEVEL:
4322 case FIFO_TRIGGER_DIFF_LEVEL:
4325 dev_info(hisi_hba->dev, "Invalid trigger mode: %u\n",
4326 phy->fifo.trigger_mode);
4332 static int debugfs_update_fifo_config_v3_hw(struct hisi_sas_phy *phy)
4334 u32 trigger_mode = phy->fifo.trigger_mode;
4335 u32 signal_sel = phy->fifo.signal_sel;
4336 u32 dump_mode = phy->fifo.dump_mode;
4337 struct hisi_hba *hisi_hba = phy->hisi_hba;
4338 int phy_no = phy->sas_phy.id;
4342 /* Check the validity of trace FIFO configuration */
4343 res = debugfs_is_fifo_config_valid_v3_hw(phy);
4347 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4348 /* Disable trace FIFO before update configuration */
4349 reg_val |= DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4351 /* Update trace FIFO configuration */
4352 reg_val &= ~(DFX_FIFO_CTRL_DUMP_MODE_MSK |
4353 DFX_FIFO_CTRL_SIGNAL_SEL_MSK |
4354 DFX_FIFO_CTRL_TRIGGER_MODE_MSK);
4356 reg_val |= ((trigger_mode << DFX_FIFO_CTRL_TRIGGER_MODE_OFF) |
4357 (dump_mode << DFX_FIFO_CTRL_DUMP_MODE_OFF) |
4358 (signal_sel << DFX_FIFO_CTRL_SIGNAL_SEL_OFF));
4359 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, reg_val);
4361 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_DUMP_MSK,
4362 phy->fifo.dump_msk);
4364 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_TRIGGER,
4367 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_TRIGGER_MSK,
4368 phy->fifo.trigger_msk);
4370 /* Enable trace FIFO after updated configuration */
4371 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4372 reg_val &= ~DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4373 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, reg_val);
4378 static ssize_t debugfs_fifo_update_cfg_v3_hw_write(struct file *filp,
4379 const char __user *buf,
4380 size_t count, loff_t *ppos)
4382 struct hisi_sas_phy *phy = filp->private_data;
4386 val = kstrtobool_from_user(buf, count, &update);
4393 val = debugfs_update_fifo_config_v3_hw(phy);
4400 static const struct file_operations debugfs_fifo_update_cfg_v3_hw_fops = {
4401 .open = simple_open,
4402 .write = debugfs_fifo_update_cfg_v3_hw_write,
4403 .owner = THIS_MODULE,
4406 static void debugfs_read_fifo_data_v3_hw(struct hisi_sas_phy *phy)
4408 struct hisi_hba *hisi_hba = phy->hisi_hba;
4409 u32 *buf = phy->fifo.rd_data;
4410 int phy_no = phy->sas_phy.id;
4414 memset(buf, 0, sizeof(phy->fifo.rd_data));
4416 /* Disable trace FIFO before read data */
4417 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4418 val |= DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4419 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, val);
4421 for (i = 0; i < HISI_SAS_FIFO_DATA_DW_SIZE; i++) {
4422 val = hisi_sas_phy_read32(hisi_hba, phy_no,
4427 /* Enable trace FIFO after read data */
4428 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4429 val &= ~DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4430 hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, val);
4433 static int debugfs_fifo_data_v3_hw_show(struct seq_file *s, void *p)
4435 struct hisi_sas_phy *phy = s->private;
4437 debugfs_read_fifo_data_v3_hw(phy);
4439 debugfs_show_row_32_v3_hw(s, 0, HISI_SAS_FIFO_DATA_DW_SIZE * 4,
4444 DEFINE_SHOW_ATTRIBUTE(debugfs_fifo_data_v3_hw);
4446 static void debugfs_fifo_init_v3_hw(struct hisi_hba *hisi_hba)
4450 hisi_hba->debugfs_fifo_dentry =
4451 debugfs_create_dir("fifo", hisi_hba->debugfs_dir);
4453 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4454 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
4455 struct dentry *port_dentry;
4459 /* get default configuration for trace FIFO */
4460 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4461 val &= DFX_FIFO_CTRL_DUMP_MODE_MSK;
4462 val >>= DFX_FIFO_CTRL_DUMP_MODE_OFF;
4463 phy->fifo.dump_mode = val;
4465 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4466 val &= DFX_FIFO_CTRL_TRIGGER_MODE_MSK;
4467 val >>= DFX_FIFO_CTRL_TRIGGER_MODE_OFF;
4468 phy->fifo.trigger_mode = val;
4470 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4471 val &= DFX_FIFO_CTRL_SIGNAL_SEL_MSK;
4472 val >>= DFX_FIFO_CTRL_SIGNAL_SEL_OFF;
4473 phy->fifo.signal_sel = val;
4475 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_DUMP_MSK);
4476 phy->fifo.dump_msk = val;
4478 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_TRIGGER);
4479 phy->fifo.trigger = val;
4480 val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_TRIGGER_MSK);
4481 phy->fifo.trigger_msk = val;
4483 snprintf(name, 256, "%d", phy_no);
4484 port_dentry = debugfs_create_dir(name,
4485 hisi_hba->debugfs_fifo_dentry);
4487 debugfs_create_file("update_config", 0200, port_dentry, phy,
4488 &debugfs_fifo_update_cfg_v3_hw_fops);
4490 debugfs_create_file("signal_sel", 0600, port_dentry,
4491 &phy->fifo.signal_sel,
4492 &debugfs_v3_hw_fops);
4494 debugfs_create_file("dump_msk", 0600, port_dentry,
4495 &phy->fifo.dump_msk,
4496 &debugfs_v3_hw_fops);
4498 debugfs_create_file("dump_mode", 0600, port_dentry,
4499 &phy->fifo.dump_mode,
4500 &debugfs_v3_hw_fops);
4502 debugfs_create_file("trigger_mode", 0600, port_dentry,
4503 &phy->fifo.trigger_mode,
4504 &debugfs_v3_hw_fops);
4506 debugfs_create_file("trigger", 0600, port_dentry,
4508 &debugfs_v3_hw_fops);
4510 debugfs_create_file("trigger_msk", 0600, port_dentry,
4511 &phy->fifo.trigger_msk,
4512 &debugfs_v3_hw_fops);
4514 debugfs_create_file("fifo_data", 0400, port_dentry, phy,
4515 &debugfs_fifo_data_v3_hw_fops);
4519 static void debugfs_work_handler_v3_hw(struct work_struct *work)
4521 struct hisi_hba *hisi_hba =
4522 container_of(work, struct hisi_hba, debugfs_work);
4524 debugfs_snapshot_regs_v3_hw(hisi_hba);
4527 static void debugfs_release_v3_hw(struct hisi_hba *hisi_hba, int dump_index)
4529 struct device *dev = hisi_hba->dev;
4532 devm_kfree(dev, hisi_hba->debugfs_iost_cache[dump_index].cache);
4533 devm_kfree(dev, hisi_hba->debugfs_itct_cache[dump_index].cache);
4534 devm_kfree(dev, hisi_hba->debugfs_iost[dump_index].iost);
4535 devm_kfree(dev, hisi_hba->debugfs_itct[dump_index].itct);
4537 for (i = 0; i < hisi_hba->queue_count; i++)
4538 devm_kfree(dev, hisi_hba->debugfs_dq[dump_index][i].hdr);
4540 for (i = 0; i < hisi_hba->queue_count; i++)
4542 hisi_hba->debugfs_cq[dump_index][i].complete_hdr);
4544 for (i = 0; i < DEBUGFS_REGS_NUM; i++)
4545 devm_kfree(dev, hisi_hba->debugfs_regs[dump_index][i].data);
4547 for (i = 0; i < hisi_hba->n_phy; i++)
4548 devm_kfree(dev, hisi_hba->debugfs_port_reg[dump_index][i].data);
4551 static const struct hisi_sas_debugfs_reg *debugfs_reg_array_v3_hw[DEBUGFS_REGS_NUM] = {
4552 [DEBUGFS_GLOBAL] = &debugfs_global_reg,
4553 [DEBUGFS_AXI] = &debugfs_axi_reg,
4554 [DEBUGFS_RAS] = &debugfs_ras_reg,
4557 static int debugfs_alloc_v3_hw(struct hisi_hba *hisi_hba, int dump_index)
4559 const struct hisi_sas_hw *hw = hisi_hba->hw;
4560 struct device *dev = hisi_hba->dev;
4564 for (r = 0; r < DEBUGFS_REGS_NUM; r++) {
4565 struct hisi_sas_debugfs_regs *regs =
4566 &hisi_hba->debugfs_regs[dump_index][r];
4568 sz = debugfs_reg_array_v3_hw[r]->count * 4;
4569 regs->data = devm_kmalloc(dev, sz, GFP_KERNEL);
4572 regs->hisi_hba = hisi_hba;
4575 sz = debugfs_port_reg.count * 4;
4576 for (p = 0; p < hisi_hba->n_phy; p++) {
4577 struct hisi_sas_debugfs_port *port =
4578 &hisi_hba->debugfs_port_reg[dump_index][p];
4580 port->data = devm_kmalloc(dev, sz, GFP_KERNEL);
4583 port->phy = &hisi_hba->phy[p];
4586 sz = hw->complete_hdr_size * HISI_SAS_QUEUE_SLOTS;
4587 for (c = 0; c < hisi_hba->queue_count; c++) {
4588 struct hisi_sas_debugfs_cq *cq =
4589 &hisi_hba->debugfs_cq[dump_index][c];
4591 cq->complete_hdr = devm_kmalloc(dev, sz, GFP_KERNEL);
4592 if (!cq->complete_hdr)
4594 cq->cq = &hisi_hba->cq[c];
4597 sz = sizeof(struct hisi_sas_cmd_hdr) * HISI_SAS_QUEUE_SLOTS;
4598 for (d = 0; d < hisi_hba->queue_count; d++) {
4599 struct hisi_sas_debugfs_dq *dq =
4600 &hisi_hba->debugfs_dq[dump_index][d];
4602 dq->hdr = devm_kmalloc(dev, sz, GFP_KERNEL);
4605 dq->dq = &hisi_hba->dq[d];
4608 sz = HISI_SAS_MAX_COMMANDS * sizeof(struct hisi_sas_iost);
4610 hisi_hba->debugfs_iost[dump_index].iost =
4611 devm_kmalloc(dev, sz, GFP_KERNEL);
4612 if (!hisi_hba->debugfs_iost[dump_index].iost)
4615 sz = HISI_SAS_IOST_ITCT_CACHE_NUM *
4616 sizeof(struct hisi_sas_iost_itct_cache);
4618 hisi_hba->debugfs_iost_cache[dump_index].cache =
4619 devm_kmalloc(dev, sz, GFP_KERNEL);
4620 if (!hisi_hba->debugfs_iost_cache[dump_index].cache)
4623 sz = HISI_SAS_IOST_ITCT_CACHE_NUM *
4624 sizeof(struct hisi_sas_iost_itct_cache);
4626 hisi_hba->debugfs_itct_cache[dump_index].cache =
4627 devm_kmalloc(dev, sz, GFP_KERNEL);
4628 if (!hisi_hba->debugfs_itct_cache[dump_index].cache)
4631 /* New memory allocation must be locate before itct */
4632 sz = HISI_SAS_MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_itct);
4634 hisi_hba->debugfs_itct[dump_index].itct =
4635 devm_kmalloc(dev, sz, GFP_KERNEL);
4636 if (!hisi_hba->debugfs_itct[dump_index].itct)
4641 for (i = 0; i < hisi_sas_debugfs_dump_count; i++)
4642 debugfs_release_v3_hw(hisi_hba, i);
4646 static void debugfs_phy_down_cnt_init_v3_hw(struct hisi_hba *hisi_hba)
4648 struct dentry *dir = debugfs_create_dir("phy_down_cnt",
4649 hisi_hba->debugfs_dir);
4653 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4654 snprintf(name, 16, "%d", phy_no);
4655 debugfs_create_file(name, 0600, dir,
4656 &hisi_hba->phy[phy_no],
4657 &debugfs_phy_down_cnt_v3_hw_fops);
4661 static void debugfs_bist_init_v3_hw(struct hisi_hba *hisi_hba)
4663 struct dentry *ports_dentry;
4666 hisi_hba->debugfs_bist_dentry =
4667 debugfs_create_dir("bist", hisi_hba->debugfs_dir);
4668 debugfs_create_file("link_rate", 0600,
4669 hisi_hba->debugfs_bist_dentry, hisi_hba,
4670 &debugfs_bist_linkrate_v3_hw_fops);
4672 debugfs_create_file("code_mode", 0600,
4673 hisi_hba->debugfs_bist_dentry, hisi_hba,
4674 &debugfs_bist_code_mode_v3_hw_fops);
4676 debugfs_create_file("fixed_code", 0600,
4677 hisi_hba->debugfs_bist_dentry,
4678 &hisi_hba->debugfs_bist_fixed_code[0],
4679 &debugfs_v3_hw_fops);
4681 debugfs_create_file("fixed_code_1", 0600,
4682 hisi_hba->debugfs_bist_dentry,
4683 &hisi_hba->debugfs_bist_fixed_code[1],
4684 &debugfs_v3_hw_fops);
4686 debugfs_create_file("phy_id", 0600, hisi_hba->debugfs_bist_dentry,
4687 hisi_hba, &debugfs_bist_phy_v3_hw_fops);
4689 debugfs_create_file("cnt", 0600, hisi_hba->debugfs_bist_dentry,
4690 hisi_hba, &debugfs_bist_cnt_v3_hw_ops);
4692 debugfs_create_file("loopback_mode", 0600,
4693 hisi_hba->debugfs_bist_dentry,
4694 hisi_hba, &debugfs_bist_mode_v3_hw_fops);
4696 debugfs_create_file("enable", 0600, hisi_hba->debugfs_bist_dentry,
4697 hisi_hba, &debugfs_bist_enable_v3_hw_fops);
4699 ports_dentry = debugfs_create_dir("port", hisi_hba->debugfs_bist_dentry);
4701 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4702 struct dentry *port_dentry;
4703 struct dentry *ffe_dentry;
4707 snprintf(name, 256, "%d", phy_no);
4708 port_dentry = debugfs_create_dir(name, ports_dentry);
4709 ffe_dentry = debugfs_create_dir("ffe", port_dentry);
4710 for (i = 0; i < FFE_CFG_MAX; i++) {
4713 debugfs_create_file(debugfs_ffe_name_v3_hw[i].name,
4715 &hisi_hba->debugfs_bist_ffe[phy_no][i],
4716 &debugfs_v3_hw_fops);
4720 hisi_hba->debugfs_bist_linkrate = SAS_LINK_RATE_1_5_GBPS;
4723 static void debugfs_init_v3_hw(struct hisi_hba *hisi_hba)
4725 struct device *dev = hisi_hba->dev;
4728 hisi_hba->debugfs_dir = debugfs_create_dir(dev_name(dev),
4729 hisi_sas_debugfs_dir);
4730 debugfs_create_file("trigger_dump", 0200,
4731 hisi_hba->debugfs_dir,
4733 &debugfs_trigger_dump_v3_hw_fops);
4735 /* create bist structures */
4736 debugfs_bist_init_v3_hw(hisi_hba);
4738 hisi_hba->debugfs_dump_dentry =
4739 debugfs_create_dir("dump", hisi_hba->debugfs_dir);
4741 debugfs_phy_down_cnt_init_v3_hw(hisi_hba);
4742 debugfs_fifo_init_v3_hw(hisi_hba);
4744 for (i = 0; i < hisi_sas_debugfs_dump_count; i++) {
4745 if (debugfs_alloc_v3_hw(hisi_hba, i)) {
4746 debugfs_remove_recursive(hisi_hba->debugfs_dir);
4747 dev_dbg(dev, "failed to init debugfs!\n");
4753 static void debugfs_exit_v3_hw(struct hisi_hba *hisi_hba)
4755 debugfs_remove_recursive(hisi_hba->debugfs_dir);
4759 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
4761 struct Scsi_Host *shost;
4762 struct hisi_hba *hisi_hba;
4763 struct device *dev = &pdev->dev;
4764 struct asd_sas_phy **arr_phy;
4765 struct asd_sas_port **arr_port;
4766 struct sas_ha_struct *sha;
4767 int rc, phy_nr, port_nr, i;
4769 rc = pcim_enable_device(pdev);
4773 pci_set_master(pdev);
4775 rc = pcim_iomap_regions(pdev, 1 << BAR_NO_V3_HW, DRV_NAME);
4779 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4781 dev_err(dev, "No usable DMA addressing method\n");
4786 shost = hisi_sas_shost_alloc_pci(pdev);
4792 sha = SHOST_TO_SAS_HA(shost);
4793 hisi_hba = shost_priv(shost);
4794 dev_set_drvdata(dev, sha);
4796 hisi_hba->regs = pcim_iomap_table(pdev)[BAR_NO_V3_HW];
4797 if (!hisi_hba->regs) {
4798 dev_err(dev, "cannot map register\n");
4800 goto err_out_free_host;
4803 phy_nr = port_nr = hisi_hba->n_phy;
4805 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
4806 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
4807 if (!arr_phy || !arr_port) {
4809 goto err_out_free_host;
4812 sha->sas_phy = arr_phy;
4813 sha->sas_port = arr_port;
4814 sha->core.shost = shost;
4815 sha->lldd_ha = hisi_hba;
4817 shost->transportt = hisi_sas_stt;
4818 shost->max_id = HISI_SAS_MAX_DEVICES;
4819 shost->max_lun = ~0;
4820 shost->max_channel = 1;
4821 shost->max_cmd_len = 16;
4822 shost->can_queue = HISI_SAS_UNRESERVED_IPTT;
4823 shost->cmd_per_lun = HISI_SAS_UNRESERVED_IPTT;
4825 sha->sas_ha_name = DRV_NAME;
4827 sha->lldd_module = THIS_MODULE;
4828 sha->sas_addr = &hisi_hba->sas_addr[0];
4829 sha->num_phys = hisi_hba->n_phy;
4831 for (i = 0; i < hisi_hba->n_phy; i++) {
4832 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
4833 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
4836 if (hisi_hba->prot_mask) {
4837 dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n",
4839 scsi_host_set_prot(hisi_hba->shost, prot_mask);
4840 if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK)
4841 scsi_host_set_guard(hisi_hba->shost,
4842 SHOST_DIX_GUARD_CRC);
4845 if (hisi_sas_debugfs_enable)
4846 debugfs_init_v3_hw(hisi_hba);
4848 rc = interrupt_preinit_v3_hw(hisi_hba);
4850 goto err_out_undo_debugfs;
4852 rc = scsi_add_host(shost, dev);
4854 goto err_out_undo_debugfs;
4856 rc = sas_register_ha(sha);
4858 goto err_out_remove_host;
4860 rc = hisi_sas_v3_init(hisi_hba);
4862 goto err_out_unregister_ha;
4864 scsi_scan_host(shost);
4866 pm_runtime_set_autosuspend_delay(dev, 5000);
4867 pm_runtime_use_autosuspend(dev);
4869 * For the situation that there are ATA disks connected with SAS
4870 * controller, it additionally creates ata_port which will affect the
4871 * child_count of hisi_hba->dev. Even if suspended all the disks,
4872 * ata_port is still and the child_count of hisi_hba->dev is not 0.
4873 * So use pm_suspend_ignore_children() to ignore the effect to
4876 pm_suspend_ignore_children(dev, true);
4877 pm_runtime_put_noidle(&pdev->dev);
4881 err_out_unregister_ha:
4882 sas_unregister_ha(sha);
4883 err_out_remove_host:
4884 scsi_remove_host(shost);
4885 err_out_undo_debugfs:
4886 debugfs_exit_v3_hw(hisi_hba);
4888 hisi_sas_free(hisi_hba);
4889 scsi_host_put(shost);
4895 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
4899 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 1), hisi_hba);
4900 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 2), hisi_hba);
4901 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 11), hisi_hba);
4902 for (i = 0; i < hisi_hba->cq_nvecs; i++) {
4903 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
4904 int nr = hisi_sas_intr_conv ? 16 : 16 + i;
4906 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, nr), cq);
4910 static void hisi_sas_v3_remove(struct pci_dev *pdev)
4912 struct device *dev = &pdev->dev;
4913 struct sas_ha_struct *sha = dev_get_drvdata(dev);
4914 struct hisi_hba *hisi_hba = sha->lldd_ha;
4915 struct Scsi_Host *shost = sha->core.shost;
4917 pm_runtime_get_noresume(dev);
4918 del_timer_sync(&hisi_hba->timer);
4920 sas_unregister_ha(sha);
4921 flush_workqueue(hisi_hba->wq);
4922 sas_remove_host(sha->core.shost);
4924 hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
4925 hisi_sas_free(hisi_hba);
4926 debugfs_exit_v3_hw(hisi_hba);
4927 scsi_host_put(shost);
4930 static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev)
4932 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
4933 struct hisi_hba *hisi_hba = sha->lldd_ha;
4934 struct device *dev = hisi_hba->dev;
4937 dev_info(dev, "FLR prepare\n");
4938 down(&hisi_hba->sem);
4939 set_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
4940 hisi_sas_controller_reset_prepare(hisi_hba);
4942 rc = disable_host_v3_hw(hisi_hba);
4944 dev_err(dev, "FLR: disable host failed rc=%d\n", rc);
4947 static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev)
4949 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
4950 struct hisi_hba *hisi_hba = sha->lldd_ha;
4951 struct device *dev = hisi_hba->dev;
4954 hisi_sas_init_mem(hisi_hba);
4956 rc = hw_init_v3_hw(hisi_hba);
4958 dev_err(dev, "FLR: hw init failed rc=%d\n", rc);
4962 hisi_sas_controller_reset_done(hisi_hba);
4963 dev_info(dev, "FLR done\n");
4967 /* instances of the controller */
4971 static int _suspend_v3_hw(struct device *device)
4973 struct pci_dev *pdev = to_pci_dev(device);
4974 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
4975 struct hisi_hba *hisi_hba = sha->lldd_ha;
4976 struct device *dev = hisi_hba->dev;
4977 struct Scsi_Host *shost = hisi_hba->shost;
4980 if (!pdev->pm_cap) {
4981 dev_err(dev, "PCI PM not supported\n");
4985 if (test_and_set_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags))
4988 dev_warn(dev, "entering suspend state\n");
4990 scsi_block_requests(shost);
4991 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
4992 flush_workqueue(hisi_hba->wq);
4994 rc = disable_host_v3_hw(hisi_hba);
4996 dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc);
4997 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
4998 clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
4999 scsi_unblock_requests(shost);
5003 hisi_sas_init_mem(hisi_hba);
5005 hisi_sas_release_tasks(hisi_hba);
5007 sas_suspend_ha(sha);
5009 dev_warn(dev, "end of suspending controller\n");
5013 static int _resume_v3_hw(struct device *device)
5015 struct pci_dev *pdev = to_pci_dev(device);
5016 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5017 struct hisi_hba *hisi_hba = sha->lldd_ha;
5018 struct Scsi_Host *shost = hisi_hba->shost;
5019 struct device *dev = hisi_hba->dev;
5021 pci_power_t device_state = pdev->current_state;
5023 dev_warn(dev, "resuming from operating state [D%d]\n",
5026 scsi_unblock_requests(shost);
5027 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
5029 sas_prep_resume_ha(sha);
5030 rc = hw_init_v3_hw(hisi_hba);
5032 scsi_remove_host(shost);
5035 phys_init_v3_hw(hisi_hba);
5038 * If a directly-attached disk is removed during suspend, a deadlock
5039 * may occur, as the PHYE_RESUME_TIMEOUT processing will require the
5040 * hisi_hba->device to be active, which can only happen when resume
5041 * completes. So don't wait for the HA event workqueue to drain upon
5044 sas_resume_ha_no_sync(sha);
5045 clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
5047 dev_warn(dev, "end of resuming controller\n");
5052 static int __maybe_unused suspend_v3_hw(struct device *device)
5054 struct pci_dev *pdev = to_pci_dev(device);
5055 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5056 struct hisi_hba *hisi_hba = sha->lldd_ha;
5059 set_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
5061 rc = _suspend_v3_hw(device);
5063 clear_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
5068 static int __maybe_unused resume_v3_hw(struct device *device)
5070 struct pci_dev *pdev = to_pci_dev(device);
5071 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5072 struct hisi_hba *hisi_hba = sha->lldd_ha;
5073 int rc = _resume_v3_hw(device);
5075 clear_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
5080 static const struct pci_device_id sas_v3_pci_table[] = {
5081 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
5084 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
5086 static const struct pci_error_handlers hisi_sas_err_handler = {
5087 .reset_prepare = hisi_sas_reset_prepare_v3_hw,
5088 .reset_done = hisi_sas_reset_done_v3_hw,
5091 static UNIVERSAL_DEV_PM_OPS(hisi_sas_v3_pm_ops,
5096 static struct pci_driver sas_v3_pci_driver = {
5098 .id_table = sas_v3_pci_table,
5099 .probe = hisi_sas_v3_probe,
5100 .remove = hisi_sas_v3_remove,
5101 .err_handler = &hisi_sas_err_handler,
5102 .driver.pm = &hisi_sas_v3_pm_ops,
5105 module_pci_driver(sas_v3_pci_driver);
5106 module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444);
5108 MODULE_LICENSE("GPL");
5109 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
5110 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
5111 MODULE_ALIAS("pci:" DRV_NAME);