1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2017 Hisilicon Limited.
7 #define DRV_NAME "hisi_sas_v3_hw"
9 /* global registers need init */
10 #define DLVRY_QUEUE_ENABLE 0x0
11 #define IOST_BASE_ADDR_LO 0x8
12 #define IOST_BASE_ADDR_HI 0xc
13 #define ITCT_BASE_ADDR_LO 0x10
14 #define ITCT_BASE_ADDR_HI 0x14
15 #define IO_BROKEN_MSG_ADDR_LO 0x18
16 #define IO_BROKEN_MSG_ADDR_HI 0x1c
17 #define PHY_CONTEXT 0x20
18 #define PHY_STATE 0x24
19 #define PHY_PORT_NUM_MA 0x28
20 #define PHY_CONN_RATE 0x30
22 #define ITCT_CLR_EN_OFF 16
23 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
24 #define ITCT_DEV_OFF 0
25 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
26 #define SAS_AXI_USER3 0x50
27 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
28 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
29 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
30 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
31 #define CFG_MAX_TAG 0x68
32 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
33 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
34 #define HGC_GET_ITV_TIME 0x90
35 #define DEVICE_MSG_WORK_MODE 0x94
36 #define OPENA_WT_CONTI_TIME 0x9c
37 #define I_T_NEXUS_LOSS_TIME 0xa0
38 #define MAX_CON_TIME_LIMIT_TIME 0xa4
39 #define BUS_INACTIVE_LIMIT_TIME 0xa8
40 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
41 #define CQ_INT_CONVERGE_EN 0xb0
42 #define CFG_AGING_TIME 0xbc
43 #define HGC_DFX_CFG2 0xc0
44 #define CFG_ABT_SET_QUERY_IPTT 0xd4
45 #define CFG_SET_ABORTED_IPTT_OFF 0
46 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
47 #define CFG_SET_ABORTED_EN_OFF 12
48 #define CFG_ABT_SET_IPTT_DONE 0xd8
49 #define CFG_ABT_SET_IPTT_DONE_OFF 0
50 #define HGC_IOMB_PROC1_STATUS 0x104
51 #define HGC_LM_DFX_STATUS2 0x128
52 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
53 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
54 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
55 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
56 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
57 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
58 #define HGC_CQE_ECC_ADDR 0x13c
59 #define HGC_CQE_ECC_1B_ADDR_OFF 0
60 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
61 #define HGC_CQE_ECC_MB_ADDR_OFF 8
62 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
63 #define HGC_IOST_ECC_ADDR 0x140
64 #define HGC_IOST_ECC_1B_ADDR_OFF 0
65 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
66 #define HGC_IOST_ECC_MB_ADDR_OFF 16
67 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
68 #define HGC_DQE_ECC_ADDR 0x144
69 #define HGC_DQE_ECC_1B_ADDR_OFF 0
70 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
71 #define HGC_DQE_ECC_MB_ADDR_OFF 16
72 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
73 #define CHNL_INT_STATUS 0x148
75 #define HGC_ITCT_ECC_ADDR 0x150
76 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
77 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
78 HGC_ITCT_ECC_1B_ADDR_OFF)
79 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
80 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
81 HGC_ITCT_ECC_MB_ADDR_OFF)
82 #define HGC_AXI_FIFO_ERR_INFO 0x154
83 #define AXI_ERR_INFO_OFF 0
84 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
85 #define FIFO_ERR_INFO_OFF 8
86 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
87 #define TAB_RD_TYPE 0x15c
88 #define INT_COAL_EN 0x19c
89 #define OQ_INT_COAL_TIME 0x1a0
90 #define OQ_INT_COAL_CNT 0x1a4
91 #define ENT_INT_COAL_TIME 0x1a8
92 #define ENT_INT_COAL_CNT 0x1ac
93 #define OQ_INT_SRC 0x1b0
94 #define OQ_INT_SRC_MSK 0x1b4
95 #define ENT_INT_SRC1 0x1b8
96 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
97 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
98 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
99 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
100 #define ENT_INT_SRC2 0x1bc
101 #define ENT_INT_SRC3 0x1c0
102 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
103 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
104 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
105 #define ENT_INT_SRC3_AXI_OFF 11
106 #define ENT_INT_SRC3_FIFO_OFF 12
107 #define ENT_INT_SRC3_LM_OFF 14
108 #define ENT_INT_SRC3_ITC_INT_OFF 15
109 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
110 #define ENT_INT_SRC3_ABT_OFF 16
111 #define ENT_INT_SRC3_DQE_POISON_OFF 18
112 #define ENT_INT_SRC3_IOST_POISON_OFF 19
113 #define ENT_INT_SRC3_ITCT_POISON_OFF 20
114 #define ENT_INT_SRC3_ITCT_NCQ_POISON_OFF 21
115 #define ENT_INT_SRC_MSK1 0x1c4
116 #define ENT_INT_SRC_MSK2 0x1c8
117 #define ENT_INT_SRC_MSK3 0x1cc
118 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
119 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
120 #define CHNL_ENT_INT_MSK 0x1d4
121 #define HGC_COM_INT_MSK 0x1d8
122 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
123 #define SAS_ECC_INTR 0x1e8
124 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
125 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
126 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
127 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
128 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 4
129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 5
130 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 6
131 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 7
132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 8
133 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 9
134 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
135 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
136 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 12
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 13
138 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 14
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 15
140 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 16
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 17
142 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 18
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 19
144 #define SAS_ECC_INTR_OOO_RAM_ECC_1B_OFF 20
145 #define SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF 21
146 #define SAS_ECC_INTR_MSK 0x1ec
147 #define HGC_ERR_STAT_EN 0x238
148 #define CQE_SEND_CNT 0x248
149 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
150 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
151 #define DLVRY_Q_0_DEPTH 0x268
152 #define DLVRY_Q_0_WR_PTR 0x26c
153 #define DLVRY_Q_0_RD_PTR 0x270
154 #define HYPER_STREAM_ID_EN_CFG 0xc80
155 #define OQ0_INT_SRC_MSK 0xc90
156 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
157 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
158 #define COMPL_Q_0_DEPTH 0x4e8
159 #define COMPL_Q_0_WR_PTR 0x4ec
160 #define COMPL_Q_0_RD_PTR 0x4f0
161 #define HGC_RXM_DFX_STATUS14 0xae8
162 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
163 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
164 HGC_RXM_DFX_STATUS14_MEM0_OFF)
165 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
166 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
167 HGC_RXM_DFX_STATUS14_MEM1_OFF)
168 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
169 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
170 HGC_RXM_DFX_STATUS14_MEM2_OFF)
171 #define HGC_RXM_DFX_STATUS15 0xaec
172 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
173 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
174 HGC_RXM_DFX_STATUS15_MEM3_OFF)
175 #define AWQOS_AWCACHE_CFG 0xc84
176 #define ARQOS_ARCACHE_CFG 0xc88
177 #define HILINK_ERR_DFX 0xe04
178 #define SAS_GPIO_CFG_0 0x1000
179 #define SAS_GPIO_CFG_1 0x1004
180 #define SAS_GPIO_TX_0_1 0x1040
181 #define SAS_CFG_DRIVE_VLD 0x1070
183 /* phy registers requiring init */
184 #define PORT_BASE (0x2000)
185 #define PHY_CFG (PORT_BASE + 0x0)
186 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
187 #define PHY_CFG_ENA_OFF 0
188 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
189 #define PHY_CFG_DC_OPT_OFF 2
190 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
191 #define PHY_CFG_PHY_RST_OFF 3
192 #define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF)
193 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
194 #define CFG_PROG_PHY_LINK_RATE_OFF 0
195 #define CFG_PROG_PHY_LINK_RATE_MSK (0xff << CFG_PROG_PHY_LINK_RATE_OFF)
196 #define CFG_PROG_OOB_PHY_LINK_RATE_OFF 8
197 #define CFG_PROG_OOB_PHY_LINK_RATE_MSK (0xf << CFG_PROG_OOB_PHY_LINK_RATE_OFF)
198 #define PHY_CTRL (PORT_BASE + 0x14)
199 #define PHY_CTRL_RESET_OFF 0
200 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
201 #define CMD_HDR_PIR_OFF 8
202 #define CMD_HDR_PIR_MSK (0x1 << CMD_HDR_PIR_OFF)
203 #define SERDES_CFG (PORT_BASE + 0x1c)
204 #define CFG_ALOS_CHK_DISABLE_OFF 9
205 #define CFG_ALOS_CHK_DISABLE_MSK (0x1 << CFG_ALOS_CHK_DISABLE_OFF)
206 #define SAS_PHY_BIST_CTRL (PORT_BASE + 0x2c)
207 #define CFG_BIST_MODE_SEL_OFF 0
208 #define CFG_BIST_MODE_SEL_MSK (0xf << CFG_BIST_MODE_SEL_OFF)
209 #define CFG_LOOP_TEST_MODE_OFF 14
210 #define CFG_LOOP_TEST_MODE_MSK (0x3 << CFG_LOOP_TEST_MODE_OFF)
211 #define CFG_RX_BIST_EN_OFF 16
212 #define CFG_RX_BIST_EN_MSK (0x1 << CFG_RX_BIST_EN_OFF)
213 #define CFG_TX_BIST_EN_OFF 17
214 #define CFG_TX_BIST_EN_MSK (0x1 << CFG_TX_BIST_EN_OFF)
215 #define CFG_BIST_TEST_OFF 18
216 #define CFG_BIST_TEST_MSK (0x1 << CFG_BIST_TEST_OFF)
217 #define SAS_PHY_BIST_CODE (PORT_BASE + 0x30)
218 #define SAS_PHY_BIST_CODE1 (PORT_BASE + 0x34)
219 #define SAS_BIST_ERR_CNT (PORT_BASE + 0x38)
220 #define SL_CFG (PORT_BASE + 0x84)
221 #define AIP_LIMIT (PORT_BASE + 0x90)
222 #define SL_CONTROL (PORT_BASE + 0x94)
223 #define SL_CONTROL_NOTIFY_EN_OFF 0
224 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
225 #define SL_CTA_OFF 17
226 #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
227 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
228 #define RX_BCAST_CHG_OFF 1
229 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
230 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
231 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
232 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
233 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
234 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
235 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
236 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
237 #define TXID_AUTO (PORT_BASE + 0xb8)
239 #define CT3_MSK (0x1 << CT3_OFF)
240 #define TX_HARDRST_OFF 2
241 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
242 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
243 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
244 #define STP_LINK_TIMER (PORT_BASE + 0x120)
245 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124)
246 #define CON_CFG_DRIVER (PORT_BASE + 0x130)
247 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
248 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
249 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
250 #define CHL_INT0 (PORT_BASE + 0x1b4)
251 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
252 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
253 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
254 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
255 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
256 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
257 #define CHL_INT0_NOT_RDY_OFF 4
258 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
259 #define CHL_INT0_PHY_RDY_OFF 5
260 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
261 #define CHL_INT1 (PORT_BASE + 0x1b8)
262 #define CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF 15
263 #define CHL_INT1_DMAC_TX_ECC_1B_ERR_OFF 16
264 #define CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF 17
265 #define CHL_INT1_DMAC_RX_ECC_1B_ERR_OFF 18
266 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
267 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
268 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
269 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
270 #define CHL_INT1_DMAC_TX_FIFO_ERR_OFF 23
271 #define CHL_INT1_DMAC_RX_FIFO_ERR_OFF 24
272 #define CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF 26
273 #define CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF 27
274 #define CHL_INT2 (PORT_BASE + 0x1bc)
275 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
276 #define CHL_INT2_RX_DISP_ERR_OFF 28
277 #define CHL_INT2_RX_CODE_ERR_OFF 29
278 #define CHL_INT2_RX_INVLD_DW_OFF 30
279 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31
280 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
281 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
282 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
283 #define SAS_EC_INT_COAL_TIME (PORT_BASE + 0x1cc)
284 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
285 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4)
286 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
287 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
288 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
289 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
290 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
291 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
292 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
293 #define DMA_TX_STATUS_BUSY_OFF 0
294 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
295 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
296 #define DMA_RX_STATUS_BUSY_OFF 0
297 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
299 #define COARSETUNE_TIME (PORT_BASE + 0x304)
300 #define TXDEEMPH_G1 (PORT_BASE + 0x350)
301 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
302 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
303 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
304 #define ERR_CNT_CODE_ERR (PORT_BASE + 0x394)
305 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
307 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
308 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
309 #error Max ITCT exceeded
312 #define AXI_MASTER_CFG_BASE (0x5000)
313 #define AM_CTRL_GLOBAL (0x0)
314 #define AM_CTRL_SHUTDOWN_REQ_OFF 0
315 #define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF)
316 #define AM_CURR_TRANS_RETURN (0x150)
318 #define AM_CFG_MAX_TRANS (0x5010)
319 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
320 #define AXI_CFG (0x5100)
321 #define AM_ROB_ECC_ERR_ADDR (0x510c)
322 #define AM_ROB_ECC_ERR_ADDR_OFF 0
323 #define AM_ROB_ECC_ERR_ADDR_MSK 0xffffffff
325 /* RAS registers need init */
326 #define RAS_BASE (0x6000)
327 #define SAS_RAS_INTR0 (RAS_BASE)
328 #define SAS_RAS_INTR1 (RAS_BASE + 0x04)
329 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08)
330 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c)
331 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c)
332 #define SAS_RAS_INTR2 (RAS_BASE + 0x20)
333 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24)
335 /* HW dma structures */
336 /* Delivery queue header */
338 #define CMD_HDR_ABORT_FLAG_OFF 0
339 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
340 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
341 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
342 #define CMD_HDR_RESP_REPORT_OFF 5
343 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
344 #define CMD_HDR_TLR_CTRL_OFF 6
345 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
346 #define CMD_HDR_PORT_OFF 18
347 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
348 #define CMD_HDR_PRIORITY_OFF 27
349 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
350 #define CMD_HDR_CMD_OFF 29
351 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
353 #define CMD_HDR_UNCON_CMD_OFF 3
354 #define CMD_HDR_DIR_OFF 5
355 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
356 #define CMD_HDR_RESET_OFF 7
357 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
358 #define CMD_HDR_VDTL_OFF 10
359 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
360 #define CMD_HDR_FRAME_TYPE_OFF 11
361 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
362 #define CMD_HDR_DEV_ID_OFF 16
363 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
365 #define CMD_HDR_CFL_OFF 0
366 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
367 #define CMD_HDR_NCQ_TAG_OFF 10
368 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
369 #define CMD_HDR_MRFL_OFF 15
370 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
371 #define CMD_HDR_SG_MOD_OFF 24
372 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
374 #define CMD_HDR_IPTT_OFF 0
375 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
377 #define CMD_HDR_DIF_SGL_LEN_OFF 0
378 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
379 #define CMD_HDR_DATA_SGL_LEN_OFF 16
380 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
382 #define CMD_HDR_ADDR_MODE_SEL_OFF 15
383 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
384 #define CMD_HDR_ABORT_IPTT_OFF 16
385 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
387 /* Completion header */
389 #define CMPLT_HDR_CMPLT_OFF 0
390 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
391 #define CMPLT_HDR_ERROR_PHASE_OFF 2
392 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
393 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
394 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
395 #define CMPLT_HDR_ERX_OFF 12
396 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
397 #define CMPLT_HDR_ABORT_STAT_OFF 13
398 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
400 #define STAT_IO_NOT_VALID 0x1
401 #define STAT_IO_NO_DEVICE 0x2
402 #define STAT_IO_COMPLETE 0x3
403 #define STAT_IO_ABORTED 0x4
405 #define CMPLT_HDR_IPTT_OFF 0
406 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
407 #define CMPLT_HDR_DEV_ID_OFF 16
408 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
410 #define CMPLT_HDR_IO_IN_TARGET_OFF 17
411 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
415 #define ITCT_HDR_DEV_TYPE_OFF 0
416 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
417 #define ITCT_HDR_VALID_OFF 2
418 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
419 #define ITCT_HDR_MCR_OFF 5
420 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
421 #define ITCT_HDR_VLN_OFF 9
422 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
423 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
424 #define ITCT_HDR_AWT_CONTINUE_OFF 25
425 #define ITCT_HDR_PORT_ID_OFF 28
426 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
428 #define ITCT_HDR_INLT_OFF 0
429 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
430 #define ITCT_HDR_RTOLT_OFF 48
431 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
433 struct hisi_sas_protect_iu_v3_hw {
443 struct hisi_sas_complete_v3_hdr {
450 struct hisi_sas_err_record_v3 {
452 __le32 trans_tx_fail_type;
455 __le32 trans_rx_fail_type;
458 __le16 dma_tx_err_type;
459 __le16 sipc_rx_err_type;
462 __le32 dma_rx_err_type;
465 #define RX_DATA_LEN_UNDERFLOW_OFF 6
466 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
468 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
469 #define HISI_SAS_MSI_COUNT_V3_HW 32
471 #define DIR_NO_DATA 0
473 #define DIR_TO_DEVICE 2
474 #define DIR_RESERVED 3
476 #define FIS_CMD_IS_UNCONSTRAINED(fis) \
477 ((fis.command == ATA_CMD_READ_LOG_EXT) || \
478 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
479 ((fis.command == ATA_CMD_DEV_RESET) && \
480 ((fis.control & ATA_SRST) != 0)))
482 #define T10_INSRT_EN_OFF 0
483 #define T10_INSRT_EN_MSK (1 << T10_INSRT_EN_OFF)
484 #define T10_RMV_EN_OFF 1
485 #define T10_RMV_EN_MSK (1 << T10_RMV_EN_OFF)
486 #define T10_RPLC_EN_OFF 2
487 #define T10_RPLC_EN_MSK (1 << T10_RPLC_EN_OFF)
488 #define T10_CHK_EN_OFF 3
489 #define T10_CHK_EN_MSK (1 << T10_CHK_EN_OFF)
490 #define INCR_LBRT_OFF 5
491 #define INCR_LBRT_MSK (1 << INCR_LBRT_OFF)
492 #define USR_DATA_BLOCK_SZ_OFF 20
493 #define USR_DATA_BLOCK_SZ_MSK (0x3 << USR_DATA_BLOCK_SZ_OFF)
494 #define T10_CHK_MSK_OFF 16
495 #define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF)
496 #define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF)
498 #define BASE_VECTORS_V3_HW 16
499 #define MIN_AFFINE_VECTORS_V3_HW (BASE_VECTORS_V3_HW + 1)
501 #define CHNL_INT_STS_MSK 0xeeeeeeee
502 #define CHNL_INT_STS_PHY_MSK 0xe
503 #define CHNL_INT_STS_INT0_MSK BIT(1)
504 #define CHNL_INT_STS_INT1_MSK BIT(2)
505 #define CHNL_INT_STS_INT2_MSK BIT(3)
509 DSM_FUNC_ERR_HANDLE_MSI = 0,
512 static bool hisi_sas_intr_conv;
513 MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)");
515 /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */
516 static int prot_mask;
517 module_param(prot_mask, int, 0);
518 MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 ");
520 static bool auto_affine_msi_experimental;
521 module_param(auto_affine_msi_experimental, bool, 0444);
522 MODULE_PARM_DESC(auto_affine_msi_experimental, "Enable auto-affinity of MSI IRQs as experimental:\n"
525 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
527 void __iomem *regs = hisi_hba->regs + off;
532 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
534 void __iomem *regs = hisi_hba->regs + off;
539 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
542 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
547 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
550 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
555 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \
558 void __iomem *regs = hisi_hba->regs + off; \
559 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \
562 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \
565 void __iomem *regs = hisi_hba->regs + off; \
566 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\
569 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
573 /* Global registers init */
574 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
575 (u32)((1ULL << hisi_hba->queue_count) - 1));
576 hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0);
577 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
578 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
579 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
580 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
581 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
582 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
583 hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN,
585 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
586 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
587 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
588 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
589 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
590 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
591 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffc220ff);
592 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
593 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
594 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
595 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x155555);
596 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
597 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
598 for (i = 0; i < hisi_hba->queue_count; i++)
599 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0);
601 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
603 for (i = 0; i < hisi_hba->n_phy; i++) {
604 enum sas_linkrate max;
605 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
606 struct asd_sas_phy *sas_phy = &phy->sas_phy;
607 u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, i,
610 prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
611 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
612 SAS_LINK_RATE_1_5_GBPS))
613 max = SAS_LINK_RATE_12_0_GBPS;
615 max = sas_phy->phy->maximum_linkrate;
616 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
617 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
619 hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00);
620 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
621 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
622 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
623 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
624 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
625 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xf2057fff);
626 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
627 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
628 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
629 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
630 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
631 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
632 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
633 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
634 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01);
635 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32);
636 hisi_sas_phy_write32(hisi_hba, i, SAS_EC_INT_COAL_TIME,
638 /* used for 12G negotiate */
639 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
640 hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff);
642 /* get default FFE configuration for BIST */
643 for (j = 0; j < FFE_CFG_MAX; j++) {
644 u32 val = hisi_sas_phy_read32(hisi_hba, i,
645 TXDEEMPH_G1 + (j * 0x4));
646 hisi_hba->debugfs_bist_ffe[i][j] = val;
650 for (i = 0; i < hisi_hba->queue_count; i++) {
652 hisi_sas_write32(hisi_hba,
653 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
654 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
656 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
657 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
659 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
660 HISI_SAS_QUEUE_SLOTS);
662 /* Completion queue */
663 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
664 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
666 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
667 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
669 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
670 HISI_SAS_QUEUE_SLOTS);
674 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
675 lower_32_bits(hisi_hba->itct_dma));
677 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
678 upper_32_bits(hisi_hba->itct_dma));
681 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
682 lower_32_bits(hisi_hba->iost_dma));
684 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
685 upper_32_bits(hisi_hba->iost_dma));
688 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
689 lower_32_bits(hisi_hba->breakpoint_dma));
691 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
692 upper_32_bits(hisi_hba->breakpoint_dma));
694 /* SATA broken msg */
695 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
696 lower_32_bits(hisi_hba->sata_breakpoint_dma));
698 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
699 upper_32_bits(hisi_hba->sata_breakpoint_dma));
701 /* SATA initial fis */
702 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
703 lower_32_bits(hisi_hba->initial_fis_dma));
705 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
706 upper_32_bits(hisi_hba->initial_fis_dma));
708 /* RAS registers init */
709 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
710 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
711 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0);
712 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0);
714 /* LED registers init */
715 hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff);
716 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080);
717 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080);
718 /* Configure blink generator rate A to 1Hz and B to 4Hz */
719 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700);
720 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000);
723 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
725 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
727 cfg &= ~PHY_CFG_DC_OPT_MSK;
728 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
729 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
732 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
734 struct sas_identify_frame identify_frame;
735 u32 *identify_buffer;
737 memset(&identify_frame, 0, sizeof(identify_frame));
738 identify_frame.dev_type = SAS_END_DEVICE;
739 identify_frame.frame_type = 0;
740 identify_frame._un1 = 1;
741 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
742 identify_frame.target_bits = SAS_PROTOCOL_NONE;
743 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
744 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
745 identify_frame.phy_id = phy_no;
746 identify_buffer = (u32 *)(&identify_frame);
748 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
749 __swab32(identify_buffer[0]));
750 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
751 __swab32(identify_buffer[1]));
752 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
753 __swab32(identify_buffer[2]));
754 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
755 __swab32(identify_buffer[3]));
756 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
757 __swab32(identify_buffer[4]));
758 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
759 __swab32(identify_buffer[5]));
762 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
763 struct hisi_sas_device *sas_dev)
765 struct domain_device *device = sas_dev->sas_device;
766 struct device *dev = hisi_hba->dev;
767 u64 qw0, device_id = sas_dev->device_id;
768 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
769 struct domain_device *parent_dev = device->parent;
770 struct asd_sas_port *sas_port = device->port;
771 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
774 memset(itct, 0, sizeof(*itct));
778 switch (sas_dev->dev_type) {
780 case SAS_EDGE_EXPANDER_DEVICE:
781 case SAS_FANOUT_EXPANDER_DEVICE:
782 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
785 case SAS_SATA_PENDING:
786 if (parent_dev && dev_is_expander(parent_dev->dev_type))
787 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
789 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
792 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
796 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
797 (device->linkrate << ITCT_HDR_MCR_OFF) |
798 (1 << ITCT_HDR_VLN_OFF) |
799 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
800 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
801 (port->id << ITCT_HDR_PORT_ID_OFF));
802 itct->qw0 = cpu_to_le64(qw0);
805 memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
806 itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
809 if (!dev_is_sata(device))
810 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
811 (0x1ULL << ITCT_HDR_RTOLT_OFF));
814 static int clear_itct_v3_hw(struct hisi_hba *hisi_hba,
815 struct hisi_sas_device *sas_dev)
817 DECLARE_COMPLETION_ONSTACK(completion);
818 u64 dev_id = sas_dev->device_id;
819 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
820 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
821 struct device *dev = hisi_hba->dev;
823 sas_dev->completion = &completion;
825 /* clear the itct interrupt state */
826 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
827 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
828 ENT_INT_SRC3_ITC_INT_MSK);
830 /* clear the itct table */
831 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
832 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
834 if (!wait_for_completion_timeout(sas_dev->completion,
835 CLEAR_ITCT_TIMEOUT * HZ)) {
836 dev_warn(dev, "failed to clear ITCT\n");
840 memset(itct, 0, sizeof(struct hisi_sas_itct));
844 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
845 struct domain_device *device)
847 struct hisi_sas_slot *slot, *slot2;
848 struct hisi_sas_device *sas_dev = device->lldd_dev;
849 u32 cfg_abt_set_query_iptt;
851 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
852 CFG_ABT_SET_QUERY_IPTT);
853 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
854 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
855 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
856 (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
857 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
858 cfg_abt_set_query_iptt);
860 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
861 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
862 cfg_abt_set_query_iptt);
863 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
864 1 << CFG_ABT_SET_IPTT_DONE_OFF);
867 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
869 struct device *dev = hisi_hba->dev;
873 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
875 /* Disable all of the PHYs */
876 hisi_sas_stop_phys(hisi_hba);
879 /* Ensure axi bus idle */
880 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
883 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
887 if (ACPI_HANDLE(dev)) {
890 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
891 if (ACPI_FAILURE(s)) {
892 dev_err(dev, "Reset failed\n");
896 dev_err(dev, "no reset method!\n");
903 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
905 struct device *dev = hisi_hba->dev;
906 union acpi_object *obj;
910 rc = reset_hw_v3_hw(hisi_hba);
912 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d\n", rc);
917 init_reg_v3_hw(hisi_hba);
919 if (guid_parse("D5918B4B-37AE-4E10-A99F-E5E8A6EF4C1F", &guid)) {
920 dev_err(dev, "Parse GUID failed\n");
925 * This DSM handles some hardware-related configurations:
926 * 1. Switch over to MSI error handling in kernel
927 * 2. BIOS *may* reset some register values through this method
929 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 0,
930 DSM_FUNC_ERR_HANDLE_MSI, NULL);
932 dev_warn(dev, "can not find DSM method, ignore\n");
939 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
941 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
943 cfg |= PHY_CFG_ENA_MSK;
944 cfg &= ~PHY_CFG_PHY_RST_MSK;
945 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
948 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
950 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
951 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
952 static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
953 BIT(CHL_INT2_RX_CODE_ERR_OFF) |
954 BIT(CHL_INT2_RX_INVLD_DW_OFF);
957 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk);
959 cfg &= ~PHY_CFG_ENA_MSK;
960 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
964 state = hisi_sas_read32(hisi_hba, PHY_STATE);
965 if (state & BIT(phy_no)) {
966 cfg |= PHY_CFG_PHY_RST_MSK;
967 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
972 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
973 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
974 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
976 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk);
977 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk);
980 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
982 config_id_frame_v3_hw(hisi_hba, phy_no);
983 config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
984 enable_phy_v3_hw(hisi_hba, phy_no);
987 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
989 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
992 hisi_sas_phy_enable(hisi_hba, phy_no, 0);
993 if (phy->identify.device_type == SAS_END_DEVICE) {
994 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
995 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
996 txid_auto | TX_HARDRST_MSK);
999 hisi_sas_phy_enable(hisi_hba, phy_no, 1);
1002 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
1004 return SAS_LINK_RATE_12_0_GBPS;
1007 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
1011 for (i = 0; i < hisi_hba->n_phy; i++) {
1012 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1013 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1015 if (!sas_phy->phy->enabled)
1018 hisi_sas_phy_enable(hisi_hba, i, 1);
1022 static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1026 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1027 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1028 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1030 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1031 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1032 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1035 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
1038 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1039 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1041 for (i = 0; i < hisi_hba->n_phy; i++)
1042 if (phy_state & BIT(i))
1043 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1049 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
1051 struct hisi_hba *hisi_hba = dq->hisi_hba;
1052 struct hisi_sas_slot *s, *s1, *s2 = NULL;
1053 int dlvry_queue = dq->id;
1056 list_for_each_entry_safe(s, s1, &dq->list, delivery) {
1060 list_del(&s->delivery);
1067 * Ensure that memories for slots built on other CPUs is observed.
1070 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
1072 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
1075 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
1076 struct hisi_sas_slot *slot,
1077 struct hisi_sas_cmd_hdr *hdr,
1078 struct scatterlist *scatter,
1081 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1082 struct scatterlist *sg;
1085 for_each_sg(scatter, sg, n_elem, i) {
1086 struct hisi_sas_sge *entry = &sge_page->sge[i];
1088 entry->addr = cpu_to_le64(sg_dma_address(sg));
1089 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1090 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1091 entry->data_off = 0;
1094 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1096 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1099 static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba,
1100 struct hisi_sas_slot *slot,
1101 struct hisi_sas_cmd_hdr *hdr,
1102 struct scatterlist *scatter,
1105 struct hisi_sas_sge_dif_page *sge_dif_page;
1106 struct scatterlist *sg;
1109 sge_dif_page = hisi_sas_sge_dif_addr_mem(slot);
1111 for_each_sg(scatter, sg, n_elem, i) {
1112 struct hisi_sas_sge *entry = &sge_dif_page->sge[i];
1114 entry->addr = cpu_to_le64(sg_dma_address(sg));
1115 entry->page_ctrl_0 = 0;
1116 entry->page_ctrl_1 = 0;
1117 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1118 entry->data_off = 0;
1121 hdr->dif_prd_table_addr =
1122 cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot));
1124 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF);
1127 static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd)
1129 unsigned char prot_flags = scsi_cmnd->prot_flags;
1131 if (prot_flags & SCSI_PROT_REF_CHECK)
1132 return T10_CHK_APP_TAG_MSK;
1133 return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK;
1136 static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd,
1137 struct hisi_sas_protect_iu_v3_hw *prot)
1139 unsigned char prot_op = scsi_get_prot_op(scsi_cmnd);
1140 unsigned int interval = scsi_prot_interval(scsi_cmnd);
1141 u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmnd->request);
1144 case SCSI_PROT_READ_INSERT:
1145 prot->dw0 |= T10_INSRT_EN_MSK;
1146 prot->lbrtgv = lbrt_chk_val;
1148 case SCSI_PROT_READ_STRIP:
1149 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1150 prot->lbrtcv = lbrt_chk_val;
1151 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1153 case SCSI_PROT_READ_PASS:
1154 prot->dw0 |= T10_CHK_EN_MSK;
1155 prot->lbrtcv = lbrt_chk_val;
1156 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1158 case SCSI_PROT_WRITE_INSERT:
1159 prot->dw0 |= T10_INSRT_EN_MSK;
1160 prot->lbrtgv = lbrt_chk_val;
1162 case SCSI_PROT_WRITE_STRIP:
1163 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1164 prot->lbrtcv = lbrt_chk_val;
1166 case SCSI_PROT_WRITE_PASS:
1167 prot->dw0 |= T10_CHK_EN_MSK;
1168 prot->lbrtcv = lbrt_chk_val;
1169 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1172 WARN(1, "prot_op(0x%x) is not valid\n", prot_op);
1180 prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF);
1183 prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF);
1186 WARN(1, "protection interval (0x%x) invalid\n",
1191 prot->dw0 |= INCR_LBRT_MSK;
1194 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
1195 struct hisi_sas_slot *slot)
1197 struct sas_task *task = slot->task;
1198 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1199 struct domain_device *device = task->dev;
1200 struct hisi_sas_device *sas_dev = device->lldd_dev;
1201 struct hisi_sas_port *port = slot->port;
1202 struct sas_ssp_task *ssp_task = &task->ssp_task;
1203 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1204 struct hisi_sas_tmf_task *tmf = slot->tmf;
1205 int has_data = 0, priority = !!tmf;
1206 unsigned char prot_op;
1208 u32 dw1 = 0, dw2 = 0, len = 0;
1210 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1211 (2 << CMD_HDR_TLR_CTRL_OFF) |
1212 (port->id << CMD_HDR_PORT_OFF) |
1213 (priority << CMD_HDR_PRIORITY_OFF) |
1214 (1 << CMD_HDR_CMD_OFF)); /* ssp */
1216 dw1 = 1 << CMD_HDR_VDTL_OFF;
1218 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1219 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1221 prot_op = scsi_get_prot_op(scsi_cmnd);
1222 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1223 switch (scsi_cmnd->sc_data_direction) {
1226 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1228 case DMA_FROM_DEVICE:
1230 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1233 dw1 &= ~CMD_HDR_DIR_MSK;
1237 /* map itct entry */
1238 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1240 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1241 + 3) / 4) << CMD_HDR_CFL_OFF) |
1242 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1243 (2 << CMD_HDR_SG_MOD_OFF);
1244 hdr->dw2 = cpu_to_le32(dw2);
1245 hdr->transfer_tags = cpu_to_le32(slot->idx);
1248 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1251 if (scsi_prot_sg_count(scsi_cmnd))
1252 prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr,
1253 scsi_prot_sglist(scsi_cmnd),
1257 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1258 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1260 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1261 sizeof(struct ssp_frame_hdr);
1263 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1265 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
1266 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
1268 buf_cmd[10] = tmf->tmf;
1270 case TMF_ABORT_TASK:
1271 case TMF_QUERY_TASK:
1273 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1275 tmf->tag_of_task_to_be_managed & 0xff;
1282 if (has_data && (prot_op != SCSI_PROT_NORMAL)) {
1283 struct hisi_sas_protect_iu_v3_hw prot;
1286 hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF);
1287 dw1 |= CMD_HDR_PIR_MSK;
1288 buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) +
1289 sizeof(struct ssp_frame_hdr) +
1290 sizeof(struct ssp_command_iu);
1292 memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw));
1293 fill_prot_v3_hw(scsi_cmnd, &prot);
1294 memcpy(buf_cmd_prot, &prot,
1295 sizeof(struct hisi_sas_protect_iu_v3_hw));
1297 * For READ, we need length of info read to memory, while for
1298 * WRITE we need length of data written to the disk.
1300 if (prot_op == SCSI_PROT_WRITE_INSERT ||
1301 prot_op == SCSI_PROT_READ_INSERT ||
1302 prot_op == SCSI_PROT_WRITE_PASS ||
1303 prot_op == SCSI_PROT_READ_PASS) {
1304 unsigned int interval = scsi_prot_interval(scsi_cmnd);
1305 unsigned int ilog2_interval = ilog2(interval);
1307 len = (task->total_xfer_len >> ilog2_interval) * 8;
1311 hdr->dw1 = cpu_to_le32(dw1);
1313 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len);
1316 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
1317 struct hisi_sas_slot *slot)
1319 struct sas_task *task = slot->task;
1320 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1321 struct domain_device *device = task->dev;
1322 struct hisi_sas_port *port = slot->port;
1323 struct scatterlist *sg_req;
1324 struct hisi_sas_device *sas_dev = device->lldd_dev;
1325 dma_addr_t req_dma_addr;
1326 unsigned int req_len;
1329 sg_req = &task->smp_task.smp_req;
1330 req_len = sg_dma_len(sg_req);
1331 req_dma_addr = sg_dma_address(sg_req);
1335 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1336 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1337 (2 << CMD_HDR_CMD_OFF)); /* smp */
1339 /* map itct entry */
1340 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1341 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1342 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1345 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1346 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1349 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1351 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1352 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1355 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1356 struct hisi_sas_slot *slot)
1358 struct sas_task *task = slot->task;
1359 struct domain_device *device = task->dev;
1360 struct domain_device *parent_dev = device->parent;
1361 struct hisi_sas_device *sas_dev = device->lldd_dev;
1362 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1363 struct asd_sas_port *sas_port = device->port;
1364 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1366 int has_data = 0, hdr_tag = 0;
1367 u32 dw1 = 0, dw2 = 0;
1369 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1370 if (parent_dev && dev_is_expander(parent_dev->dev_type))
1371 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1373 hdr->dw0 |= cpu_to_le32(4U << CMD_HDR_CMD_OFF);
1375 switch (task->data_dir) {
1378 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1380 case DMA_FROM_DEVICE:
1382 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1385 dw1 &= ~CMD_HDR_DIR_MSK;
1388 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1389 (task->ata_task.fis.control & ATA_SRST))
1390 dw1 |= 1 << CMD_HDR_RESET_OFF;
1392 dw1 |= (hisi_sas_get_ata_protocol(
1393 &task->ata_task.fis, task->data_dir))
1394 << CMD_HDR_FRAME_TYPE_OFF;
1395 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1397 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
1398 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1400 hdr->dw1 = cpu_to_le32(dw1);
1403 if (task->ata_task.use_ncq) {
1404 struct ata_queued_cmd *qc = task->uldd_task;
1407 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1408 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1411 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1412 2 << CMD_HDR_SG_MOD_OFF;
1413 hdr->dw2 = cpu_to_le32(dw2);
1416 hdr->transfer_tags = cpu_to_le32(slot->idx);
1419 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1422 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1423 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1424 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1426 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1428 if (likely(!task->ata_task.device_control_reg_update))
1429 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1430 /* fill in command FIS */
1431 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1434 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1435 struct hisi_sas_slot *slot,
1436 int device_id, int abort_flag, int tag_to_abort)
1438 struct sas_task *task = slot->task;
1439 struct domain_device *dev = task->dev;
1440 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1441 struct hisi_sas_port *port = slot->port;
1444 hdr->dw0 = cpu_to_le32((5U << CMD_HDR_CMD_OFF) | /*abort*/
1445 (port->id << CMD_HDR_PORT_OFF) |
1447 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1449 << CMD_HDR_ABORT_FLAG_OFF));
1452 hdr->dw1 = cpu_to_le32(device_id
1453 << CMD_HDR_DEV_ID_OFF);
1456 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1457 hdr->transfer_tags = cpu_to_le32(slot->idx);
1460 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1464 u32 context, port_id, link_rate;
1465 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1466 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1467 struct device *dev = hisi_hba->dev;
1468 unsigned long flags;
1470 del_timer(&phy->timer);
1471 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1473 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1474 port_id = (port_id >> (4 * phy_no)) & 0xf;
1475 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1476 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1478 if (port_id == 0xf) {
1479 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1483 sas_phy->linkrate = link_rate;
1484 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1486 /* Check for SATA dev */
1487 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1488 if (context & (1 << phy_no)) {
1489 struct hisi_sas_initial_fis *initial_fis;
1490 struct dev_to_host_fis *fis;
1491 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1492 struct Scsi_Host *shost = hisi_hba->shost;
1494 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1495 initial_fis = &hisi_hba->initial_fis[phy_no];
1496 fis = &initial_fis->fis;
1498 /* check ERR bit of Status Register */
1499 if (fis->status & ATA_ERR) {
1500 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n",
1501 phy_no, fis->status);
1502 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1507 sas_phy->oob_mode = SATA_OOB_MODE;
1508 attached_sas_addr[0] = 0x50;
1509 attached_sas_addr[6] = shost->host_no;
1510 attached_sas_addr[7] = phy_no;
1511 memcpy(sas_phy->attached_sas_addr,
1514 memcpy(sas_phy->frame_rcvd, fis,
1515 sizeof(struct dev_to_host_fis));
1516 phy->phy_type |= PORT_TYPE_SATA;
1517 phy->identify.device_type = SAS_SATA_DEV;
1518 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1519 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1521 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1522 struct sas_identify_frame *id =
1523 (struct sas_identify_frame *)frame_rcvd;
1525 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1526 for (i = 0; i < 6; i++) {
1527 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1528 RX_IDAF_DWORD0 + (i * 4));
1529 frame_rcvd[i] = __swab32(idaf);
1531 sas_phy->oob_mode = SAS_OOB_MODE;
1532 memcpy(sas_phy->attached_sas_addr,
1535 phy->phy_type |= PORT_TYPE_SAS;
1536 phy->identify.device_type = id->dev_type;
1537 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1538 if (phy->identify.device_type == SAS_END_DEVICE)
1539 phy->identify.target_port_protocols =
1541 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1542 phy->identify.target_port_protocols =
1546 phy->port_id = port_id;
1547 phy->phy_attached = 1;
1548 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
1550 spin_lock_irqsave(&phy->lock, flags);
1551 if (phy->reset_completion) {
1553 complete(phy->reset_completion);
1555 spin_unlock_irqrestore(&phy->lock, flags);
1557 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1558 CHL_INT0_SL_PHY_ENABLE_MSK);
1559 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1564 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1566 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1567 u32 phy_state, sl_ctrl, txid_auto;
1568 struct device *dev = hisi_hba->dev;
1570 atomic_inc(&phy->down_cnt);
1572 del_timer(&phy->timer);
1573 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1575 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1576 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1577 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1579 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1580 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1581 sl_ctrl&(~SL_CTA_MSK));
1583 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1584 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1585 txid_auto | CT3_MSK);
1587 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1588 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1593 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1595 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1596 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1597 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1600 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1601 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
1602 if ((bcast_status & RX_BCAST_CHG_MSK) &&
1603 !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
1604 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1605 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1606 CHL_INT0_SL_RX_BCST_ACK_MSK);
1607 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1612 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1614 struct hisi_hba *hisi_hba = p;
1617 irqreturn_t res = IRQ_NONE;
1619 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1623 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1625 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1626 int rdy = phy_state & (1 << phy_no);
1629 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1631 if (phy_up_v3_hw(phy_no, hisi_hba)
1634 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1636 if (phy_bcast_v3_hw(phy_no, hisi_hba)
1640 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1642 if (phy_down_v3_hw(phy_no, hisi_hba)
1654 static const struct hisi_sas_hw_error port_axi_error[] = {
1656 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF),
1657 .msg = "dmac_tx_ecc_bad_err",
1660 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF),
1661 .msg = "dmac_rx_ecc_bad_err",
1664 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1665 .msg = "dma_tx_axi_wr_err",
1668 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1669 .msg = "dma_tx_axi_rd_err",
1672 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1673 .msg = "dma_rx_axi_wr_err",
1676 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1677 .msg = "dma_rx_axi_rd_err",
1680 .irq_msk = BIT(CHL_INT1_DMAC_TX_FIFO_ERR_OFF),
1681 .msg = "dma_tx_fifo_err",
1684 .irq_msk = BIT(CHL_INT1_DMAC_RX_FIFO_ERR_OFF),
1685 .msg = "dma_rx_fifo_err",
1688 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF),
1689 .msg = "dma_tx_axi_ruser_err",
1692 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF),
1693 .msg = "dma_rx_axi_ruser_err",
1697 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1699 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1);
1700 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK);
1701 struct device *dev = hisi_hba->dev;
1704 irq_value &= ~irq_msk;
1708 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1709 const struct hisi_sas_hw_error *error = &port_axi_error[i];
1711 if (!(irq_value & error->irq_msk))
1714 dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1715 error->msg, phy_no, irq_value);
1716 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1719 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value);
1722 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1724 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1725 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1726 struct sas_phy *sphy = sas_phy->phy;
1727 unsigned long flags;
1730 spin_lock_irqsave(&phy->lock, flags);
1732 /* loss dword sync */
1733 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1734 sphy->loss_of_dword_sync_count += reg_value;
1736 /* phy reset problem */
1737 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1738 sphy->phy_reset_problem_count += reg_value;
1741 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1742 sphy->invalid_dword_count += reg_value;
1745 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1746 sphy->running_disparity_error_count += reg_value;
1748 /* code violation error */
1749 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
1750 phy->code_violation_err_count += reg_value;
1752 spin_unlock_irqrestore(&phy->lock, flags);
1755 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1757 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
1758 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1759 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1760 struct pci_dev *pci_dev = hisi_hba->pci_dev;
1761 struct device *dev = hisi_hba->dev;
1762 static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
1763 BIT(CHL_INT2_RX_CODE_ERR_OFF) |
1764 BIT(CHL_INT2_RX_INVLD_DW_OFF);
1766 irq_value &= ~irq_msk;
1770 if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1771 dev_warn(dev, "phy%d identify timeout\n", phy_no);
1772 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1775 if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1776 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1777 STP_LINK_TIMEOUT_STATE);
1779 dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1781 if (reg_value & BIT(4))
1782 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1785 if (pci_dev->revision > 0x20 && (irq_value & msk)) {
1786 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1787 struct sas_phy *sphy = sas_phy->phy;
1789 phy_get_events_v3_hw(hisi_hba, phy_no);
1791 if (irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF))
1792 dev_info(dev, "phy%d invalid dword cnt: %u\n", phy_no,
1793 sphy->invalid_dword_count);
1795 if (irq_value & BIT(CHL_INT2_RX_CODE_ERR_OFF))
1796 dev_info(dev, "phy%d code violation cnt: %u\n", phy_no,
1797 phy->code_violation_err_count);
1799 if (irq_value & BIT(CHL_INT2_RX_DISP_ERR_OFF))
1800 dev_info(dev, "phy%d disparity error cnt: %u\n", phy_no,
1801 sphy->running_disparity_error_count);
1804 if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) &&
1805 (pci_dev->revision == 0x20)) {
1809 rc = hisi_sas_read32_poll_timeout_atomic(
1810 HILINK_ERR_DFX, reg_value,
1811 !((reg_value >> 8) & BIT(phy_no)),
1814 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1817 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value);
1820 static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1822 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1824 if (irq_value0 & CHL_INT0_PHY_RDY_MSK)
1825 hisi_sas_phy_oob_ready(hisi_hba, phy_no);
1827 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1828 irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1829 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1830 & (~CHL_INT0_NOT_RDY_MSK));
1833 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1835 struct hisi_hba *hisi_hba = p;
1839 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1843 if (irq_msk & (CHNL_INT_STS_INT0_MSK << (phy_no * CHNL_WIDTH)))
1844 handle_chl_int0_v3_hw(hisi_hba, phy_no);
1846 if (irq_msk & (CHNL_INT_STS_INT1_MSK << (phy_no * CHNL_WIDTH)))
1847 handle_chl_int1_v3_hw(hisi_hba, phy_no);
1849 if (irq_msk & (CHNL_INT_STS_INT2_MSK << (phy_no * CHNL_WIDTH)))
1850 handle_chl_int2_v3_hw(hisi_hba, phy_no);
1852 irq_msk &= ~(CHNL_INT_STS_PHY_MSK << (phy_no * CHNL_WIDTH));
1859 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
1861 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
1862 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
1863 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
1864 .msg = "hgc_dqe_eccbad_intr",
1865 .reg = HGC_DQE_ECC_ADDR,
1868 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
1869 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
1870 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
1871 .msg = "hgc_iost_eccbad_intr",
1872 .reg = HGC_IOST_ECC_ADDR,
1875 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
1876 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
1877 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
1878 .msg = "hgc_itct_eccbad_intr",
1879 .reg = HGC_ITCT_ECC_ADDR,
1882 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
1883 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
1884 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
1885 .msg = "hgc_iostl_eccbad_intr",
1886 .reg = HGC_LM_DFX_STATUS2,
1889 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
1890 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
1891 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
1892 .msg = "hgc_itctl_eccbad_intr",
1893 .reg = HGC_LM_DFX_STATUS2,
1896 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
1897 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
1898 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
1899 .msg = "hgc_cqe_eccbad_intr",
1900 .reg = HGC_CQE_ECC_ADDR,
1903 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
1904 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
1905 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
1906 .msg = "rxm_mem0_eccbad_intr",
1907 .reg = HGC_RXM_DFX_STATUS14,
1910 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
1911 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
1912 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
1913 .msg = "rxm_mem1_eccbad_intr",
1914 .reg = HGC_RXM_DFX_STATUS14,
1917 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
1918 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
1919 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
1920 .msg = "rxm_mem2_eccbad_intr",
1921 .reg = HGC_RXM_DFX_STATUS14,
1924 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
1925 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
1926 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
1927 .msg = "rxm_mem3_eccbad_intr",
1928 .reg = HGC_RXM_DFX_STATUS15,
1931 .irq_msk = BIT(SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF),
1932 .msk = AM_ROB_ECC_ERR_ADDR_MSK,
1933 .shift = AM_ROB_ECC_ERR_ADDR_OFF,
1934 .msg = "ooo_ram_eccbad_intr",
1935 .reg = AM_ROB_ECC_ERR_ADDR,
1939 static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba,
1942 struct device *dev = hisi_hba->dev;
1943 const struct hisi_sas_hw_error *ecc_error;
1947 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
1948 ecc_error = &multi_bit_ecc_errors[i];
1949 if (irq_value & ecc_error->irq_msk) {
1950 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
1951 val &= ecc_error->msk;
1952 val >>= ecc_error->shift;
1953 dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n",
1954 ecc_error->msg, irq_value, val);
1955 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1960 static void fatal_ecc_int_v3_hw(struct hisi_hba *hisi_hba)
1962 u32 irq_value, irq_msk;
1964 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
1965 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
1967 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
1969 multi_bit_ecc_error_process_v3_hw(hisi_hba, irq_value);
1971 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
1972 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
1975 static const struct hisi_sas_hw_error axi_error[] = {
1976 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
1977 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
1978 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
1979 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
1980 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
1981 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
1982 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
1983 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
1987 static const struct hisi_sas_hw_error fifo_error[] = {
1988 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
1989 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
1990 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
1991 { .msk = BIT(11), .msg = "CMDP_FIFO" },
1992 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
1996 static const struct hisi_sas_hw_error fatal_axi_error[] = {
1998 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
1999 .msg = "write pointer and depth",
2002 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
2003 .msg = "iptt no match slot",
2006 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
2007 .msg = "read pointer and depth",
2010 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
2011 .reg = HGC_AXI_FIFO_ERR_INFO,
2015 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
2016 .reg = HGC_AXI_FIFO_ERR_INFO,
2020 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
2021 .msg = "LM add/fetch list",
2024 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
2025 .msg = "SAS_HGC_ABT fetch LM list",
2028 .irq_msk = BIT(ENT_INT_SRC3_DQE_POISON_OFF),
2029 .msg = "read dqe poison",
2032 .irq_msk = BIT(ENT_INT_SRC3_IOST_POISON_OFF),
2033 .msg = "read iost poison",
2036 .irq_msk = BIT(ENT_INT_SRC3_ITCT_POISON_OFF),
2037 .msg = "read itct poison",
2040 .irq_msk = BIT(ENT_INT_SRC3_ITCT_NCQ_POISON_OFF),
2041 .msg = "read itct ncq poison",
2046 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
2048 u32 irq_value, irq_msk;
2049 struct hisi_hba *hisi_hba = p;
2050 struct device *dev = hisi_hba->dev;
2051 struct pci_dev *pdev = hisi_hba->pci_dev;
2054 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2055 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
2057 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
2058 irq_value &= ~irq_msk;
2060 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
2061 const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
2063 if (!(irq_value & error->irq_msk))
2067 const struct hisi_sas_hw_error *sub = error->sub;
2068 u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
2070 for (; sub->msk || sub->msg; sub++) {
2071 if (!(err_value & sub->msk))
2074 dev_err(dev, "%s error (0x%x) found!\n",
2075 sub->msg, irq_value);
2076 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2079 dev_err(dev, "%s error (0x%x) found!\n",
2080 error->msg, irq_value);
2081 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2084 if (pdev->revision < 0x21) {
2087 reg_val = hisi_sas_read32(hisi_hba,
2088 AXI_MASTER_CFG_BASE +
2090 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2091 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2092 AM_CTRL_GLOBAL, reg_val);
2096 fatal_ecc_int_v3_hw(hisi_hba);
2098 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
2099 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
2100 u32 dev_id = reg_val & ITCT_DEV_MSK;
2101 struct hisi_sas_device *sas_dev =
2102 &hisi_hba->devices[dev_id];
2104 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
2105 dev_dbg(dev, "clear ITCT ok\n");
2106 complete(sas_dev->completion);
2109 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
2110 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
2116 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
2117 struct hisi_sas_slot *slot)
2119 struct task_status_struct *ts = &task->task_status;
2120 struct hisi_sas_complete_v3_hdr *complete_queue =
2121 hisi_hba->complete_hdr[slot->cmplt_queue];
2122 struct hisi_sas_complete_v3_hdr *complete_hdr =
2123 &complete_queue[slot->cmplt_queue_slot];
2124 struct hisi_sas_err_record_v3 *record =
2125 hisi_sas_status_buf_addr_mem(slot);
2126 u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type);
2127 u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type);
2128 u32 dw3 = le32_to_cpu(complete_hdr->dw3);
2130 switch (task->task_proto) {
2131 case SAS_PROTOCOL_SSP:
2132 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
2133 ts->residual = trans_tx_fail_type;
2134 ts->stat = SAS_DATA_UNDERRUN;
2135 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
2136 ts->stat = SAS_QUEUE_FULL;
2139 ts->stat = SAS_OPEN_REJECT;
2140 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2143 case SAS_PROTOCOL_SATA:
2144 case SAS_PROTOCOL_STP:
2145 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2146 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
2147 ts->residual = trans_tx_fail_type;
2148 ts->stat = SAS_DATA_UNDERRUN;
2149 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
2150 ts->stat = SAS_PHY_DOWN;
2153 ts->stat = SAS_OPEN_REJECT;
2154 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2156 hisi_sas_sata_done(task, slot);
2158 case SAS_PROTOCOL_SMP:
2159 ts->stat = SAM_STAT_CHECK_CONDITION;
2166 static void slot_complete_v3_hw(struct hisi_hba *hisi_hba,
2167 struct hisi_sas_slot *slot)
2169 struct sas_task *task = slot->task;
2170 struct hisi_sas_device *sas_dev;
2171 struct device *dev = hisi_hba->dev;
2172 struct task_status_struct *ts;
2173 struct domain_device *device;
2174 struct sas_ha_struct *ha;
2175 struct hisi_sas_complete_v3_hdr *complete_queue =
2176 hisi_hba->complete_hdr[slot->cmplt_queue];
2177 struct hisi_sas_complete_v3_hdr *complete_hdr =
2178 &complete_queue[slot->cmplt_queue_slot];
2179 unsigned long flags;
2180 bool is_internal = slot->is_internal;
2183 if (unlikely(!task || !task->lldd_task || !task->dev))
2186 ts = &task->task_status;
2188 ha = device->port->ha;
2189 sas_dev = device->lldd_dev;
2191 spin_lock_irqsave(&task->task_state_lock, flags);
2192 task->task_state_flags &=
2193 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2194 spin_unlock_irqrestore(&task->task_state_lock, flags);
2196 memset(ts, 0, sizeof(*ts));
2197 ts->resp = SAS_TASK_COMPLETE;
2199 if (unlikely(!sas_dev)) {
2200 dev_dbg(dev, "slot complete: port has not device\n");
2201 ts->stat = SAS_PHY_DOWN;
2205 dw0 = le32_to_cpu(complete_hdr->dw0);
2206 dw1 = le32_to_cpu(complete_hdr->dw1);
2207 dw3 = le32_to_cpu(complete_hdr->dw3);
2210 * Use SAS+TMF status codes
2212 switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) {
2213 case STAT_IO_ABORTED:
2214 /* this IO has been aborted by abort command */
2215 ts->stat = SAS_ABORTED_TASK;
2217 case STAT_IO_COMPLETE:
2218 /* internal abort command complete */
2219 ts->stat = TMF_RESP_FUNC_SUCC;
2221 case STAT_IO_NO_DEVICE:
2222 ts->stat = TMF_RESP_FUNC_COMPLETE;
2224 case STAT_IO_NOT_VALID:
2226 * abort single IO, the controller can't find the IO
2228 ts->stat = TMF_RESP_FUNC_FAILED;
2234 /* check for erroneous completion */
2235 if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
2236 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2238 slot_err_v3_hw(hisi_hba, task, slot);
2239 if (ts->stat != SAS_DATA_UNDERRUN)
2240 dev_info(dev, "erroneous completion iptt=%d task=%pK dev id=%d CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n",
2241 slot->idx, task, sas_dev->device_id,
2242 dw0, dw1, complete_hdr->act, dw3,
2243 error_info[0], error_info[1],
2244 error_info[2], error_info[3]);
2245 if (unlikely(slot->abort)) {
2246 sas_task_abort(task);
2252 switch (task->task_proto) {
2253 case SAS_PROTOCOL_SSP: {
2254 struct ssp_response_iu *iu =
2255 hisi_sas_status_buf_addr_mem(slot) +
2256 sizeof(struct hisi_sas_err_record);
2258 sas_ssp_task_response(dev, task, iu);
2261 case SAS_PROTOCOL_SMP: {
2262 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2263 void *to = page_address(sg_page(sg_resp));
2265 ts->stat = SAM_STAT_GOOD;
2267 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2269 memcpy(to + sg_resp->offset,
2270 hisi_sas_status_buf_addr_mem(slot) +
2271 sizeof(struct hisi_sas_err_record),
2275 case SAS_PROTOCOL_SATA:
2276 case SAS_PROTOCOL_STP:
2277 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2278 ts->stat = SAM_STAT_GOOD;
2279 hisi_sas_sata_done(task, slot);
2282 ts->stat = SAM_STAT_CHECK_CONDITION;
2286 if (!slot->port->port_attached) {
2287 dev_warn(dev, "slot complete: port %d has removed\n",
2288 slot->port->sas_port.id);
2289 ts->stat = SAS_PHY_DOWN;
2293 spin_lock_irqsave(&task->task_state_lock, flags);
2294 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
2295 spin_unlock_irqrestore(&task->task_state_lock, flags);
2296 dev_info(dev, "slot complete: task(%pK) aborted\n", task);
2299 task->task_state_flags |= SAS_TASK_STATE_DONE;
2300 spin_unlock_irqrestore(&task->task_state_lock, flags);
2301 hisi_sas_slot_task_free(hisi_hba, task, slot);
2303 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
2304 spin_lock_irqsave(&device->done_lock, flags);
2305 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
2306 spin_unlock_irqrestore(&device->done_lock, flags);
2307 dev_info(dev, "slot complete: task(%pK) ignored\n ",
2311 spin_unlock_irqrestore(&device->done_lock, flags);
2314 if (task->task_done)
2315 task->task_done(task);
2318 static irqreturn_t cq_thread_v3_hw(int irq_no, void *p)
2320 struct hisi_sas_cq *cq = p;
2321 struct hisi_hba *hisi_hba = cq->hisi_hba;
2322 struct hisi_sas_slot *slot;
2323 struct hisi_sas_complete_v3_hdr *complete_queue;
2324 u32 rd_point = cq->rd_point, wr_point;
2327 complete_queue = hisi_hba->complete_hdr[queue];
2329 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
2332 while (rd_point != wr_point) {
2333 struct hisi_sas_complete_v3_hdr *complete_hdr;
2334 struct device *dev = hisi_hba->dev;
2338 complete_hdr = &complete_queue[rd_point];
2339 dw1 = le32_to_cpu(complete_hdr->dw1);
2341 iptt = dw1 & CMPLT_HDR_IPTT_MSK;
2342 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
2343 slot = &hisi_hba->slot_info[iptt];
2344 slot->cmplt_queue_slot = rd_point;
2345 slot->cmplt_queue = queue;
2346 slot_complete_v3_hw(hisi_hba, slot);
2348 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt);
2350 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
2354 /* update rd_point */
2355 cq->rd_point = rd_point;
2356 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
2361 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
2363 struct hisi_sas_cq *cq = p;
2364 struct hisi_hba *hisi_hba = cq->hisi_hba;
2367 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
2369 return IRQ_WAKE_THREAD;
2372 static void setup_reply_map_v3_hw(struct hisi_hba *hisi_hba, int nvecs)
2374 const struct cpumask *mask;
2377 for (queue = 0; queue < nvecs; queue++) {
2378 struct hisi_sas_cq *cq = &hisi_hba->cq[queue];
2380 mask = pci_irq_get_affinity(hisi_hba->pci_dev, queue +
2381 BASE_VECTORS_V3_HW);
2384 cq->irq_mask = mask;
2385 for_each_cpu(cpu, mask)
2386 hisi_hba->reply_map[cpu] = queue;
2391 for_each_possible_cpu(cpu)
2392 hisi_hba->reply_map[cpu] = cpu % hisi_hba->queue_count;
2393 /* Don't clean all CQ masks */
2396 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
2398 struct device *dev = hisi_hba->dev;
2399 struct pci_dev *pdev = hisi_hba->pci_dev;
2401 int max_msi = HISI_SAS_MSI_COUNT_V3_HW, min_msi;
2403 if (auto_affine_msi_experimental) {
2404 struct irq_affinity desc = {
2405 .pre_vectors = BASE_VECTORS_V3_HW,
2408 dev_info(dev, "Enable MSI auto-affinity\n");
2410 min_msi = MIN_AFFINE_VECTORS_V3_HW;
2412 hisi_hba->reply_map = devm_kcalloc(dev, nr_cpu_ids,
2413 sizeof(unsigned int),
2415 if (!hisi_hba->reply_map)
2417 vectors = pci_alloc_irq_vectors_affinity(hisi_hba->pci_dev,
2424 setup_reply_map_v3_hw(hisi_hba, vectors - BASE_VECTORS_V3_HW);
2427 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, min_msi,
2428 max_msi, PCI_IRQ_MSI);
2433 hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW;
2435 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
2436 int_phy_up_down_bcast_v3_hw, 0,
2437 DRV_NAME " phy", hisi_hba);
2439 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
2441 goto free_irq_vectors;
2444 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
2445 int_chnl_int_v3_hw, 0,
2446 DRV_NAME " channel", hisi_hba);
2448 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
2450 goto free_irq_vectors;
2453 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
2454 fatal_axi_int_v3_hw, 0,
2455 DRV_NAME " fatal", hisi_hba);
2457 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
2459 goto free_irq_vectors;
2462 if (hisi_sas_intr_conv)
2463 dev_info(dev, "Enable interrupt converge\n");
2465 for (i = 0; i < hisi_hba->cq_nvecs; i++) {
2466 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2467 int nr = hisi_sas_intr_conv ? 16 : 16 + i;
2468 unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED :
2471 cq->irq_no = pci_irq_vector(pdev, nr);
2472 rc = devm_request_threaded_irq(dev, cq->irq_no,
2476 DRV_NAME " cq", cq);
2478 dev_err(dev, "could not request cq%d interrupt, rc=%d\n",
2481 goto free_irq_vectors;
2488 pci_free_irq_vectors(pdev);
2492 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
2496 rc = hw_init_v3_hw(hisi_hba);
2500 rc = interrupt_init_v3_hw(hisi_hba);
2507 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
2508 struct sas_phy_linkrates *r)
2510 enum sas_linkrate max = r->maximum_linkrate;
2511 u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, phy_no,
2512 PROG_PHY_LINK_RATE);
2514 prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
2515 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
2516 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
2517 prog_phy_link_rate);
2520 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
2522 struct pci_dev *pdev = hisi_hba->pci_dev;
2525 synchronize_irq(pci_irq_vector(pdev, 1));
2526 synchronize_irq(pci_irq_vector(pdev, 2));
2527 synchronize_irq(pci_irq_vector(pdev, 11));
2528 for (i = 0; i < hisi_hba->queue_count; i++) {
2529 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
2530 synchronize_irq(pci_irq_vector(pdev, i + 16));
2533 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
2534 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
2535 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
2536 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
2538 for (i = 0; i < hisi_hba->n_phy; i++) {
2539 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
2540 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
2541 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
2542 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
2543 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
2547 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
2549 return hisi_sas_read32(hisi_hba, PHY_STATE);
2552 static int disable_host_v3_hw(struct hisi_hba *hisi_hba)
2554 struct device *dev = hisi_hba->dev;
2555 u32 status, reg_val;
2558 interrupt_disable_v3_hw(hisi_hba);
2559 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2561 hisi_sas_stop_phys(hisi_hba);
2565 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2567 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2568 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2569 AM_CTRL_GLOBAL, reg_val);
2571 /* wait until bus idle */
2572 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
2573 AM_CURR_TRANS_RETURN, status,
2574 status == 0x3, 10, 100);
2576 dev_err(dev, "axi bus is not idle, rc=%d\n", rc);
2583 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
2585 struct device *dev = hisi_hba->dev;
2588 rc = disable_host_v3_hw(hisi_hba);
2590 dev_err(dev, "soft reset: disable host failed rc=%d\n", rc);
2594 hisi_sas_init_mem(hisi_hba);
2596 return hw_init_v3_hw(hisi_hba);
2599 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type,
2600 u8 reg_index, u8 reg_count, u8 *write_data)
2602 struct device *dev = hisi_hba->dev;
2603 u32 *data = (u32 *)write_data;
2607 case SAS_GPIO_REG_TX:
2608 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) {
2609 dev_err(dev, "write gpio: invalid reg range[%d, %d]\n",
2610 reg_index, reg_index + reg_count - 1);
2614 for (i = 0; i < reg_count; i++)
2615 hisi_sas_write32(hisi_hba,
2616 SAS_GPIO_TX_0_1 + (reg_index + i) * 4,
2620 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
2628 static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
2629 int delay_ms, int timeout_ms)
2631 struct device *dev = hisi_hba->dev;
2632 int entries, entries_old = 0, time;
2634 for (time = 0; time < timeout_ms; time += delay_ms) {
2635 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
2636 if (entries == entries_old)
2639 entries_old = entries;
2643 if (time >= timeout_ms) {
2644 dev_dbg(dev, "Wait commands complete timeout!\n");
2648 dev_dbg(dev, "wait commands complete %dms\n", time);
2651 static ssize_t intr_conv_v3_hw_show(struct device *dev,
2652 struct device_attribute *attr, char *buf)
2654 return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv);
2656 static DEVICE_ATTR_RO(intr_conv_v3_hw);
2658 static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba)
2660 /* config those registers between enable and disable PHYs */
2661 hisi_sas_stop_phys(hisi_hba);
2663 if (hisi_hba->intr_coal_ticks == 0 ||
2664 hisi_hba->intr_coal_count == 0) {
2665 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
2666 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
2667 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
2669 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3);
2670 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME,
2671 hisi_hba->intr_coal_ticks);
2672 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT,
2673 hisi_hba->intr_coal_count);
2675 phys_init_v3_hw(hisi_hba);
2678 static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev,
2679 struct device_attribute *attr,
2682 struct Scsi_Host *shost = class_to_shost(dev);
2683 struct hisi_hba *hisi_hba = shost_priv(shost);
2685 return scnprintf(buf, PAGE_SIZE, "%u\n",
2686 hisi_hba->intr_coal_ticks);
2689 static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev,
2690 struct device_attribute *attr,
2691 const char *buf, size_t count)
2693 struct Scsi_Host *shost = class_to_shost(dev);
2694 struct hisi_hba *hisi_hba = shost_priv(shost);
2695 u32 intr_coal_ticks;
2698 ret = kstrtou32(buf, 10, &intr_coal_ticks);
2700 dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2704 if (intr_coal_ticks >= BIT(24)) {
2705 dev_err(dev, "intr_coal_ticks must be less than 2^24!\n");
2709 hisi_hba->intr_coal_ticks = intr_coal_ticks;
2711 config_intr_coal_v3_hw(hisi_hba);
2715 static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw);
2717 static ssize_t intr_coal_count_v3_hw_show(struct device *dev,
2718 struct device_attribute
2721 struct Scsi_Host *shost = class_to_shost(dev);
2722 struct hisi_hba *hisi_hba = shost_priv(shost);
2724 return scnprintf(buf, PAGE_SIZE, "%u\n",
2725 hisi_hba->intr_coal_count);
2728 static ssize_t intr_coal_count_v3_hw_store(struct device *dev,
2729 struct device_attribute
2730 *attr, const char *buf, size_t count)
2732 struct Scsi_Host *shost = class_to_shost(dev);
2733 struct hisi_hba *hisi_hba = shost_priv(shost);
2734 u32 intr_coal_count;
2737 ret = kstrtou32(buf, 10, &intr_coal_count);
2739 dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2743 if (intr_coal_count >= BIT(8)) {
2744 dev_err(dev, "intr_coal_count must be less than 2^8!\n");
2748 hisi_hba->intr_coal_count = intr_coal_count;
2750 config_intr_coal_v3_hw(hisi_hba);
2754 static DEVICE_ATTR_RW(intr_coal_count_v3_hw);
2756 static struct device_attribute *host_attrs_v3_hw[] = {
2757 &dev_attr_phy_event_threshold,
2758 &dev_attr_intr_conv_v3_hw,
2759 &dev_attr_intr_coal_ticks_v3_hw,
2760 &dev_attr_intr_coal_count_v3_hw,
2764 static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = {
2765 HISI_SAS_DEBUGFS_REG(PHY_CFG),
2766 HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE),
2767 HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE),
2768 HISI_SAS_DEBUGFS_REG(PHY_CTRL),
2769 HISI_SAS_DEBUGFS_REG(SL_CFG),
2770 HISI_SAS_DEBUGFS_REG(AIP_LIMIT),
2771 HISI_SAS_DEBUGFS_REG(SL_CONTROL),
2772 HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS),
2773 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0),
2774 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1),
2775 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2),
2776 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3),
2777 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4),
2778 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5),
2779 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6),
2780 HISI_SAS_DEBUGFS_REG(TXID_AUTO),
2781 HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0),
2782 HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H),
2783 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER),
2784 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE),
2785 HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER),
2786 HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG),
2787 HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG),
2788 HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG),
2789 HISI_SAS_DEBUGFS_REG(CHL_INT0),
2790 HISI_SAS_DEBUGFS_REG(CHL_INT1),
2791 HISI_SAS_DEBUGFS_REG(CHL_INT2),
2792 HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK),
2793 HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK),
2794 HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK),
2795 HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME),
2796 HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN),
2797 HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER),
2798 HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK),
2799 HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK),
2800 HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK),
2801 HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK),
2802 HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK),
2803 HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK),
2804 HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS),
2805 HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS),
2806 HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME),
2807 HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST),
2808 HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB),
2809 HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW),
2810 HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR),
2811 HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR),
2815 static const struct hisi_sas_debugfs_reg debugfs_port_reg = {
2816 .lu = debugfs_port_reg_lu,
2818 .base_off = PORT_BASE,
2819 .read_port_reg = hisi_sas_phy_read32,
2822 static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = {
2823 HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE),
2824 HISI_SAS_DEBUGFS_REG(PHY_CONTEXT),
2825 HISI_SAS_DEBUGFS_REG(PHY_STATE),
2826 HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA),
2827 HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE),
2828 HISI_SAS_DEBUGFS_REG(ITCT_CLR),
2829 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO),
2830 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI),
2831 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO),
2832 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI),
2833 HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG),
2834 HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL),
2835 HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL),
2836 HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME),
2837 HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE),
2838 HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME),
2839 HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME),
2840 HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME),
2841 HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME),
2842 HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME),
2843 HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN),
2844 HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME),
2845 HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2),
2846 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT),
2847 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE),
2848 HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS),
2849 HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS),
2850 HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO),
2851 HISI_SAS_DEBUGFS_REG(INT_COAL_EN),
2852 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME),
2853 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT),
2854 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME),
2855 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT),
2856 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC),
2857 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK),
2858 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1),
2859 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2),
2860 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3),
2861 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1),
2862 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2),
2863 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3),
2864 HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK),
2865 HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK),
2866 HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK),
2867 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR),
2868 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK),
2869 HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN),
2870 HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT),
2871 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH),
2872 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR),
2873 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR),
2874 HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG),
2875 HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK),
2876 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH),
2877 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR),
2878 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR),
2879 HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG),
2880 HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG),
2881 HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX),
2882 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0),
2883 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1),
2884 HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1),
2885 HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD),
2889 static const struct hisi_sas_debugfs_reg debugfs_global_reg = {
2890 .lu = debugfs_global_reg_lu,
2892 .read_global_reg = hisi_sas_read32,
2895 static const struct hisi_sas_debugfs_reg_lu debugfs_axi_reg_lu[] = {
2896 HISI_SAS_DEBUGFS_REG(AM_CFG_MAX_TRANS),
2897 HISI_SAS_DEBUGFS_REG(AM_CFG_SINGLE_PORT_MAX_TRANS),
2898 HISI_SAS_DEBUGFS_REG(AXI_CFG),
2899 HISI_SAS_DEBUGFS_REG(AM_ROB_ECC_ERR_ADDR),
2903 static const struct hisi_sas_debugfs_reg debugfs_axi_reg = {
2904 .lu = debugfs_axi_reg_lu,
2906 .base_off = AXI_MASTER_CFG_BASE,
2907 .read_global_reg = hisi_sas_read32,
2910 static const struct hisi_sas_debugfs_reg_lu debugfs_ras_reg_lu[] = {
2911 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0),
2912 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1),
2913 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0_MASK),
2914 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1_MASK),
2915 HISI_SAS_DEBUGFS_REG(CFG_SAS_RAS_INTR_MASK),
2916 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2),
2917 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2_MASK),
2921 static const struct hisi_sas_debugfs_reg debugfs_ras_reg = {
2922 .lu = debugfs_ras_reg_lu,
2924 .base_off = RAS_BASE,
2925 .read_global_reg = hisi_sas_read32,
2928 static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba)
2930 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2932 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
2934 wait_cmds_complete_timeout_v3_hw(hisi_hba, 100, 5000);
2936 hisi_sas_sync_irqs(hisi_hba);
2939 static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba)
2941 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
2942 (u32)((1ULL << hisi_hba->queue_count) - 1));
2944 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2947 static void read_iost_itct_cache_v3_hw(struct hisi_hba *hisi_hba,
2948 enum hisi_sas_debugfs_cache_type type,
2951 u32 cache_dw_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ *
2952 HISI_SAS_IOST_ITCT_CACHE_NUM;
2953 struct device *dev = hisi_hba->dev;
2957 hisi_sas_write32(hisi_hba, TAB_RD_TYPE, type);
2959 for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_DW_SZ; i++) {
2960 val = hisi_sas_read32(hisi_hba, TAB_DFX);
2961 if (val == 0xffffffff)
2965 if (val != 0xffffffff) {
2966 dev_err(dev, "Issue occurred in reading IOST/ITCT cache!\n");
2970 memset(buf, 0, cache_dw_size * 4);
2973 for (i = 1; i < cache_dw_size; i++)
2974 buf[i] = hisi_sas_read32(hisi_hba, TAB_DFX);
2977 static void hisi_sas_bist_test_prep_v3_hw(struct hisi_hba *hisi_hba)
2980 int phy_no = hisi_hba->debugfs_bist_phy_no;
2984 hisi_sas_phy_enable(hisi_hba, phy_no, 0);
2987 for (i = 0; i < FFE_CFG_MAX; i++)
2988 hisi_sas_phy_write32(hisi_hba, phy_no, TXDEEMPH_G1 + (i * 0x4),
2989 hisi_hba->debugfs_bist_ffe[phy_no][i]);
2992 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
2993 reg_val |= CFG_ALOS_CHK_DISABLE_MSK;
2994 hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
2997 static void hisi_sas_bist_test_restore_v3_hw(struct hisi_hba *hisi_hba)
3000 int phy_no = hisi_hba->debugfs_bist_phy_no;
3002 /* disable loopback */
3003 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL);
3004 reg_val &= ~(CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
3006 hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL, reg_val);
3009 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
3010 reg_val &= ~CFG_ALOS_CHK_DISABLE_MSK;
3011 hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
3013 /* restore the linkrate */
3014 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
3015 /* init OOB link rate as 1.5 Gbits */
3016 reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
3017 reg_val |= (0x8 << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
3018 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, reg_val);
3021 hisi_sas_phy_enable(hisi_hba, phy_no, 1);
3024 #define SAS_PHY_BIST_CODE_INIT 0x1
3025 #define SAS_PHY_BIST_CODE1_INIT 0X80
3026 static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
3028 u32 reg_val, mode_tmp;
3029 u32 linkrate = hisi_hba->debugfs_bist_linkrate;
3030 u32 phy_no = hisi_hba->debugfs_bist_phy_no;
3031 u32 *ffe = hisi_hba->debugfs_bist_ffe[phy_no];
3032 u32 code_mode = hisi_hba->debugfs_bist_code_mode;
3033 u32 path_mode = hisi_hba->debugfs_bist_mode;
3034 u32 *fix_code = &hisi_hba->debugfs_bist_fixed_code[0];
3035 struct device *dev = hisi_hba->dev;
3037 dev_info(dev, "BIST info:phy%d link_rate=%d code_mode=%d path_mode=%d ffe={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x} fixed_code={0x%x, 0x%x}\n",
3038 phy_no, linkrate, code_mode, path_mode,
3039 ffe[FFE_SAS_1_5_GBPS], ffe[FFE_SAS_3_0_GBPS],
3040 ffe[FFE_SAS_6_0_GBPS], ffe[FFE_SAS_12_0_GBPS],
3041 ffe[FFE_SATA_1_5_GBPS], ffe[FFE_SATA_3_0_GBPS],
3042 ffe[FFE_SATA_6_0_GBPS], fix_code[FIXED_CODE],
3043 fix_code[FIXED_CODE_1]);
3044 mode_tmp = path_mode ? 2 : 1;
3046 /* some preparations before bist test */
3047 hisi_sas_bist_test_prep_v3_hw(hisi_hba);
3049 /* set linkrate of bit test*/
3050 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
3051 PROG_PHY_LINK_RATE);
3052 reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
3053 reg_val |= (linkrate << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
3054 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
3057 /* set code mode of bit test */
3058 reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
3060 reg_val &= ~(CFG_BIST_MODE_SEL_MSK | CFG_LOOP_TEST_MODE_MSK |
3061 CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
3063 reg_val |= ((code_mode << CFG_BIST_MODE_SEL_OFF) |
3064 (mode_tmp << CFG_LOOP_TEST_MODE_OFF) |
3066 hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
3069 /* set the bist init value */
3070 if (code_mode == HISI_SAS_BIST_CODE_MODE_FIXED_DATA) {
3071 reg_val = hisi_hba->debugfs_bist_fixed_code[0];
3072 hisi_sas_phy_write32(hisi_hba, phy_no,
3073 SAS_PHY_BIST_CODE, reg_val);
3075 reg_val = hisi_hba->debugfs_bist_fixed_code[1];
3076 hisi_sas_phy_write32(hisi_hba, phy_no,
3077 SAS_PHY_BIST_CODE1, reg_val);
3079 hisi_sas_phy_write32(hisi_hba, phy_no,
3081 SAS_PHY_BIST_CODE_INIT);
3082 hisi_sas_phy_write32(hisi_hba, phy_no,
3084 SAS_PHY_BIST_CODE1_INIT);
3088 reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK);
3089 hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
3092 /* clear error bit */
3094 hisi_sas_phy_read32(hisi_hba, phy_no, SAS_BIST_ERR_CNT);
3096 /* disable bist test and recover it */
3097 hisi_hba->debugfs_bist_cnt += hisi_sas_phy_read32(hisi_hba,
3098 phy_no, SAS_BIST_ERR_CNT);
3099 hisi_sas_bist_test_restore_v3_hw(hisi_hba);
3105 static struct scsi_host_template sht_v3_hw = {
3107 .proc_name = DRV_NAME,
3108 .module = THIS_MODULE,
3109 .queuecommand = sas_queuecommand,
3110 .dma_need_drain = ata_scsi_dma_need_drain,
3111 .target_alloc = sas_target_alloc,
3112 .slave_configure = hisi_sas_slave_configure,
3113 .scan_finished = hisi_sas_scan_finished,
3114 .scan_start = hisi_sas_scan_start,
3115 .change_queue_depth = sas_change_queue_depth,
3116 .bios_param = sas_bios_param,
3118 .sg_tablesize = HISI_SAS_SGE_PAGE_CNT,
3119 .sg_prot_tablesize = HISI_SAS_SGE_PAGE_CNT,
3120 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
3121 .eh_device_reset_handler = sas_eh_device_reset_handler,
3122 .eh_target_reset_handler = sas_eh_target_reset_handler,
3123 .target_destroy = sas_target_destroy,
3125 #ifdef CONFIG_COMPAT
3126 .compat_ioctl = sas_ioctl,
3128 .shost_attrs = host_attrs_v3_hw,
3129 .tag_alloc_policy = BLK_TAG_ALLOC_RR,
3130 .host_reset = hisi_sas_host_reset,
3133 static const struct hisi_sas_hw hisi_sas_v3_hw = {
3134 .hw_init = hisi_sas_v3_init,
3135 .setup_itct = setup_itct_v3_hw,
3136 .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
3137 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
3138 .clear_itct = clear_itct_v3_hw,
3139 .sl_notify_ssp = sl_notify_ssp_v3_hw,
3140 .prep_ssp = prep_ssp_v3_hw,
3141 .prep_smp = prep_smp_v3_hw,
3142 .prep_stp = prep_ata_v3_hw,
3143 .prep_abort = prep_abort_v3_hw,
3144 .start_delivery = start_delivery_v3_hw,
3145 .phys_init = phys_init_v3_hw,
3146 .phy_start = start_phy_v3_hw,
3147 .phy_disable = disable_phy_v3_hw,
3148 .phy_hard_reset = phy_hard_reset_v3_hw,
3149 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
3150 .phy_set_linkrate = phy_set_linkrate_v3_hw,
3151 .dereg_device = dereg_device_v3_hw,
3152 .soft_reset = soft_reset_v3_hw,
3153 .get_phys_state = get_phys_state_v3_hw,
3154 .get_events = phy_get_events_v3_hw,
3155 .write_gpio = write_gpio_v3_hw,
3156 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw,
3157 .debugfs_reg_array[DEBUGFS_GLOBAL] = &debugfs_global_reg,
3158 .debugfs_reg_array[DEBUGFS_AXI] = &debugfs_axi_reg,
3159 .debugfs_reg_array[DEBUGFS_RAS] = &debugfs_ras_reg,
3160 .debugfs_reg_port = &debugfs_port_reg,
3161 .snapshot_prepare = debugfs_snapshot_prepare_v3_hw,
3162 .snapshot_restore = debugfs_snapshot_restore_v3_hw,
3163 .read_iost_itct_cache = read_iost_itct_cache_v3_hw,
3164 .set_bist = debugfs_set_bist_v3_hw,
3167 static struct Scsi_Host *
3168 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
3170 struct Scsi_Host *shost;
3171 struct hisi_hba *hisi_hba;
3172 struct device *dev = &pdev->dev;
3174 shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba));
3176 dev_err(dev, "shost alloc failed\n");
3179 hisi_hba = shost_priv(shost);
3181 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
3182 INIT_WORK(&hisi_hba->debugfs_work, hisi_sas_debugfs_work_handler);
3183 hisi_hba->hw = &hisi_sas_v3_hw;
3184 hisi_hba->pci_dev = pdev;
3185 hisi_hba->dev = dev;
3186 hisi_hba->shost = shost;
3187 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
3189 if (prot_mask & ~HISI_SAS_PROT_MASK)
3190 dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n",
3193 hisi_hba->prot_mask = prot_mask;
3195 if (hisi_sas_get_fw_info(hisi_hba) < 0)
3198 if (hisi_sas_alloc(hisi_hba)) {
3199 hisi_sas_free(hisi_hba);
3205 scsi_host_put(shost);
3206 dev_err(dev, "shost alloc failed\n");
3211 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3213 struct Scsi_Host *shost;
3214 struct hisi_hba *hisi_hba;
3215 struct device *dev = &pdev->dev;
3216 struct asd_sas_phy **arr_phy;
3217 struct asd_sas_port **arr_port;
3218 struct sas_ha_struct *sha;
3219 int rc, phy_nr, port_nr, i;
3221 rc = pci_enable_device(pdev);
3225 pci_set_master(pdev);
3227 rc = pci_request_regions(pdev, DRV_NAME);
3229 goto err_out_disable_device;
3231 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3233 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3235 dev_err(dev, "No usable DMA addressing method\n");
3237 goto err_out_regions;
3240 shost = hisi_sas_shost_alloc_pci(pdev);
3243 goto err_out_regions;
3246 sha = SHOST_TO_SAS_HA(shost);
3247 hisi_hba = shost_priv(shost);
3248 dev_set_drvdata(dev, sha);
3250 hisi_hba->regs = pcim_iomap(pdev, 5, 0);
3251 if (!hisi_hba->regs) {
3252 dev_err(dev, "cannot map register\n");
3257 phy_nr = port_nr = hisi_hba->n_phy;
3259 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
3260 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
3261 if (!arr_phy || !arr_port) {
3266 sha->sas_phy = arr_phy;
3267 sha->sas_port = arr_port;
3268 sha->core.shost = shost;
3269 sha->lldd_ha = hisi_hba;
3271 shost->transportt = hisi_sas_stt;
3272 shost->max_id = HISI_SAS_MAX_DEVICES;
3273 shost->max_lun = ~0;
3274 shost->max_channel = 1;
3275 shost->max_cmd_len = 16;
3276 shost->can_queue = HISI_SAS_UNRESERVED_IPTT;
3277 shost->cmd_per_lun = HISI_SAS_UNRESERVED_IPTT;
3279 sha->sas_ha_name = DRV_NAME;
3281 sha->lldd_module = THIS_MODULE;
3282 sha->sas_addr = &hisi_hba->sas_addr[0];
3283 sha->num_phys = hisi_hba->n_phy;
3285 for (i = 0; i < hisi_hba->n_phy; i++) {
3286 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
3287 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
3290 if (hisi_hba->prot_mask) {
3291 dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n",
3293 scsi_host_set_prot(hisi_hba->shost, prot_mask);
3294 if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK)
3295 scsi_host_set_guard(hisi_hba->shost,
3296 SHOST_DIX_GUARD_CRC);
3299 if (hisi_sas_debugfs_enable)
3300 hisi_sas_debugfs_init(hisi_hba);
3302 rc = scsi_add_host(shost, dev);
3306 rc = sas_register_ha(sha);
3308 goto err_out_register_ha;
3310 rc = hisi_hba->hw->hw_init(hisi_hba);
3312 goto err_out_register_ha;
3314 scsi_scan_host(shost);
3318 err_out_register_ha:
3319 scsi_remove_host(shost);
3321 hisi_sas_debugfs_exit(hisi_hba);
3322 scsi_host_put(shost);
3324 pci_release_regions(pdev);
3325 err_out_disable_device:
3326 pci_disable_device(pdev);
3332 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
3336 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
3337 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
3338 free_irq(pci_irq_vector(pdev, 11), hisi_hba);
3339 for (i = 0; i < hisi_hba->cq_nvecs; i++) {
3340 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
3341 int nr = hisi_sas_intr_conv ? 16 : 16 + i;
3343 free_irq(pci_irq_vector(pdev, nr), cq);
3345 pci_free_irq_vectors(pdev);
3348 static void hisi_sas_v3_remove(struct pci_dev *pdev)
3350 struct device *dev = &pdev->dev;
3351 struct sas_ha_struct *sha = dev_get_drvdata(dev);
3352 struct hisi_hba *hisi_hba = sha->lldd_ha;
3353 struct Scsi_Host *shost = sha->core.shost;
3355 if (timer_pending(&hisi_hba->timer))
3356 del_timer(&hisi_hba->timer);
3358 sas_unregister_ha(sha);
3359 sas_remove_host(sha->core.shost);
3361 hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
3362 pci_release_regions(pdev);
3363 pci_disable_device(pdev);
3364 hisi_sas_free(hisi_hba);
3365 hisi_sas_debugfs_exit(hisi_hba);
3366 scsi_host_put(shost);
3369 static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev)
3371 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
3372 struct hisi_hba *hisi_hba = sha->lldd_ha;
3373 struct device *dev = hisi_hba->dev;
3376 dev_info(dev, "FLR prepare\n");
3377 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
3378 hisi_sas_controller_reset_prepare(hisi_hba);
3380 rc = disable_host_v3_hw(hisi_hba);
3382 dev_err(dev, "FLR: disable host failed rc=%d\n", rc);
3385 static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev)
3387 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
3388 struct hisi_hba *hisi_hba = sha->lldd_ha;
3389 struct device *dev = hisi_hba->dev;
3392 hisi_sas_init_mem(hisi_hba);
3394 rc = hw_init_v3_hw(hisi_hba);
3396 dev_err(dev, "FLR: hw init failed rc=%d\n", rc);
3400 hisi_sas_controller_reset_done(hisi_hba);
3401 dev_info(dev, "FLR done\n");
3405 /* instances of the controller */
3409 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state)
3411 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
3412 struct hisi_hba *hisi_hba = sha->lldd_ha;
3413 struct device *dev = hisi_hba->dev;
3414 struct Scsi_Host *shost = hisi_hba->shost;
3415 pci_power_t device_state;
3418 if (!pdev->pm_cap) {
3419 dev_err(dev, "PCI PM not supported\n");
3423 if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
3426 scsi_block_requests(shost);
3427 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
3428 flush_workqueue(hisi_hba->wq);
3430 rc = disable_host_v3_hw(hisi_hba);
3432 dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc);
3433 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
3434 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
3435 scsi_unblock_requests(shost);
3439 hisi_sas_init_mem(hisi_hba);
3441 device_state = pci_choose_state(pdev, state);
3442 dev_warn(dev, "entering operating state [D%d]\n",
3444 pci_save_state(pdev);
3445 pci_disable_device(pdev);
3446 pci_set_power_state(pdev, device_state);
3448 hisi_sas_release_tasks(hisi_hba);
3450 sas_suspend_ha(sha);
3454 static int hisi_sas_v3_resume(struct pci_dev *pdev)
3456 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
3457 struct hisi_hba *hisi_hba = sha->lldd_ha;
3458 struct Scsi_Host *shost = hisi_hba->shost;
3459 struct device *dev = hisi_hba->dev;
3461 pci_power_t device_state = pdev->current_state;
3463 dev_warn(dev, "resuming from operating state [D%d]\n",
3465 pci_set_power_state(pdev, PCI_D0);
3466 pci_enable_wake(pdev, PCI_D0, 0);
3467 pci_restore_state(pdev);
3468 rc = pci_enable_device(pdev);
3470 dev_err(dev, "enable device failed during resume (%d)\n", rc);
3474 pci_set_master(pdev);
3475 scsi_unblock_requests(shost);
3476 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
3478 sas_prep_resume_ha(sha);
3479 rc = hw_init_v3_hw(hisi_hba);
3481 scsi_remove_host(shost);
3482 pci_disable_device(pdev);
3485 hisi_hba->hw->phys_init(hisi_hba);
3487 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
3492 static const struct pci_device_id sas_v3_pci_table[] = {
3493 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
3496 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
3498 static const struct pci_error_handlers hisi_sas_err_handler = {
3499 .reset_prepare = hisi_sas_reset_prepare_v3_hw,
3500 .reset_done = hisi_sas_reset_done_v3_hw,
3503 static struct pci_driver sas_v3_pci_driver = {
3505 .id_table = sas_v3_pci_table,
3506 .probe = hisi_sas_v3_probe,
3507 .remove = hisi_sas_v3_remove,
3508 .suspend = hisi_sas_v3_suspend,
3509 .resume = hisi_sas_v3_resume,
3510 .err_handler = &hisi_sas_err_handler,
3513 module_pci_driver(sas_v3_pci_driver);
3514 module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444);
3516 MODULE_LICENSE("GPL");
3517 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3518 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
3519 MODULE_ALIAS("pci:" DRV_NAME);