drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

   1 /*
   2  * Copyright (c) 2016 Linaro Ltd.
   3  * Copyright (c) 2016 Hisilicon Limited.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  */
  11
  12 #include "hisi_sas.h"
  13 #define DRV_NAME "hisi_sas_v2_hw"
  14
  15 /* global registers need init*/
  16 #define DLVRY_QUEUE_ENABLE              0x0
  17 #define IOST_BASE_ADDR_LO               0x8
  18 #define IOST_BASE_ADDR_HI               0xc
  19 #define ITCT_BASE_ADDR_LO               0x10
  20 #define ITCT_BASE_ADDR_HI               0x14
  21 #define IO_BROKEN_MSG_ADDR_LO           0x18
  22 #define IO_BROKEN_MSG_ADDR_HI           0x1c
  23 #define PHY_CONTEXT                     0x20
  24 #define PHY_STATE                       0x24
  25 #define PHY_PORT_NUM_MA                 0x28
  26 #define PORT_STATE                      0x2c
  27 #define PORT_STATE_PHY8_PORT_NUM_OFF    16
  28 #define PORT_STATE_PHY8_PORT_NUM_MSK    (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
  29 #define PORT_STATE_PHY8_CONN_RATE_OFF   20
  30 #define PORT_STATE_PHY8_CONN_RATE_MSK   (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
  31 #define PHY_CONN_RATE                   0x30
  32 #define HGC_TRANS_TASK_CNT_LIMIT        0x38
  33 #define AXI_AHB_CLK_CFG                 0x3c
  34 #define ITCT_CLR                        0x44
  35 #define ITCT_CLR_EN_OFF                 16
  36 #define ITCT_CLR_EN_MSK                 (0x1 << ITCT_CLR_EN_OFF)
  37 #define ITCT_DEV_OFF                    0
  38 #define ITCT_DEV_MSK                    (0x7ff << ITCT_DEV_OFF)
  39 #define AXI_USER1                       0x48
  40 #define AXI_USER2                       0x4c
  41 #define IO_SATA_BROKEN_MSG_ADDR_LO      0x58
  42 #define IO_SATA_BROKEN_MSG_ADDR_HI      0x5c
  43 #define SATA_INITI_D2H_STORE_ADDR_LO    0x60
  44 #define SATA_INITI_D2H_STORE_ADDR_HI    0x64
  45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
  46 #define HGC_SAS_TXFAIL_RETRY_CTRL       0x88
  47 #define HGC_GET_ITV_TIME                0x90
  48 #define DEVICE_MSG_WORK_MODE            0x94
  49 #define OPENA_WT_CONTI_TIME             0x9c
  50 #define I_T_NEXUS_LOSS_TIME             0xa0
  51 #define MAX_CON_TIME_LIMIT_TIME         0xa4
  52 #define BUS_INACTIVE_LIMIT_TIME         0xa8
  53 #define REJECT_TO_OPEN_LIMIT_TIME       0xac
  54 #define CFG_AGING_TIME                  0xbc
  55 #define HGC_DFX_CFG2                    0xc0
  56 #define HGC_IOMB_PROC1_STATUS   0x104
  57 #define CFG_1US_TIMER_TRSH              0xcc
  58 #define HGC_LM_DFX_STATUS2              0x128
  59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF         0
  60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
  61                                          HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
  62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF         12
  63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
  64                                          HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
  65 #define HGC_CQE_ECC_ADDR                0x13c
  66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
  67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
  68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
  69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
  70 #define HGC_IOST_ECC_ADDR               0x140
  71 #define HGC_IOST_ECC_1B_ADDR_OFF        0
  72 #define HGC_IOST_ECC_1B_ADDR_MSK        (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
  73 #define HGC_IOST_ECC_MB_ADDR_OFF        16
  74 #define HGC_IOST_ECC_MB_ADDR_MSK        (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
  75 #define HGC_DQE_ECC_ADDR                0x144
  76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
  77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
  78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
  79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
  80 #define HGC_INVLD_DQE_INFO              0x148
  81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF   9
  82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK   (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
  83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF   18
  84 #define HGC_ITCT_ECC_ADDR               0x150
  85 #define HGC_ITCT_ECC_1B_ADDR_OFF                0
  86 #define HGC_ITCT_ECC_1B_ADDR_MSK                (0x3ff << \
  87                                                  HGC_ITCT_ECC_1B_ADDR_OFF)
  88 #define HGC_ITCT_ECC_MB_ADDR_OFF                16
  89 #define HGC_ITCT_ECC_MB_ADDR_MSK                (0x3ff << \
  90                                                  HGC_ITCT_ECC_MB_ADDR_OFF)
  91 #define HGC_AXI_FIFO_ERR_INFO   0x154
  92 #define AXI_ERR_INFO_OFF                0
  93 #define AXI_ERR_INFO_MSK                (0xff << AXI_ERR_INFO_OFF)
  94 #define FIFO_ERR_INFO_OFF               8
  95 #define FIFO_ERR_INFO_MSK               (0xff << FIFO_ERR_INFO_OFF)
  96 #define INT_COAL_EN                     0x19c
  97 #define OQ_INT_COAL_TIME                0x1a0
  98 #define OQ_INT_COAL_CNT                 0x1a4
  99 #define ENT_INT_COAL_TIME               0x1a8
 100 #define ENT_INT_COAL_CNT                0x1ac
 101 #define OQ_INT_SRC                      0x1b0
 102 #define OQ_INT_SRC_MSK                  0x1b4
 103 #define ENT_INT_SRC1                    0x1b8
 104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF    0
 105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
 106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF    8
 107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
 108 #define ENT_INT_SRC2                    0x1bc
 109 #define ENT_INT_SRC3                    0x1c0
 110 #define ENT_INT_SRC3_WP_DEPTH_OFF               8
 111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF      9
 112 #define ENT_INT_SRC3_RP_DEPTH_OFF               10
 113 #define ENT_INT_SRC3_AXI_OFF                    11
 114 #define ENT_INT_SRC3_FIFO_OFF                   12
 115 #define ENT_INT_SRC3_LM_OFF                             14
 116 #define ENT_INT_SRC3_ITC_INT_OFF        15
 117 #define ENT_INT_SRC3_ITC_INT_MSK        (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
 118 #define ENT_INT_SRC3_ABT_OFF            16
 119 #define ENT_INT_SRC_MSK1                0x1c4
 120 #define ENT_INT_SRC_MSK2                0x1c8
 121 #define ENT_INT_SRC_MSK3                0x1cc
 122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF  31
 123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK  (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
 124 #define SAS_ECC_INTR                    0x1e8
 125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF             0
 126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF             1
 127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF    2
 128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF    3
 129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF    4
 130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF    5
 131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF        6
 132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF        7
 133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF        8
 134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF        9
 135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF             10
 136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF             11
 137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF        12
 138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF        13
 139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF        14
 140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF        15
 141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF        16
 142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF        17
 143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF        18
 144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF        19
 145 #define SAS_ECC_INTR_MSK                0x1ec
 146 #define HGC_ERR_STAT_EN                 0x238
 147 #define DLVRY_Q_0_BASE_ADDR_LO          0x260
 148 #define DLVRY_Q_0_BASE_ADDR_HI          0x264
 149 #define DLVRY_Q_0_DEPTH                 0x268
 150 #define DLVRY_Q_0_WR_PTR                0x26c
 151 #define DLVRY_Q_0_RD_PTR                0x270
 152 #define HYPER_STREAM_ID_EN_CFG          0xc80
 153 #define OQ0_INT_SRC_MSK                 0xc90
 154 #define COMPL_Q_0_BASE_ADDR_LO          0x4e0
 155 #define COMPL_Q_0_BASE_ADDR_HI          0x4e4
 156 #define COMPL_Q_0_DEPTH                 0x4e8
 157 #define COMPL_Q_0_WR_PTR                0x4ec
 158 #define COMPL_Q_0_RD_PTR                0x4f0
 159 #define HGC_RXM_DFX_STATUS14    0xae8
 160 #define HGC_RXM_DFX_STATUS14_MEM0_OFF           0
 161 #define HGC_RXM_DFX_STATUS14_MEM0_MSK           (0x1ff << \
 162                                                  HGC_RXM_DFX_STATUS14_MEM0_OFF)
 163 #define HGC_RXM_DFX_STATUS14_MEM1_OFF           9
 164 #define HGC_RXM_DFX_STATUS14_MEM1_MSK           (0x1ff << \
 165                                                  HGC_RXM_DFX_STATUS14_MEM1_OFF)
 166 #define HGC_RXM_DFX_STATUS14_MEM2_OFF           18
 167 #define HGC_RXM_DFX_STATUS14_MEM2_MSK           (0x1ff << \
 168                                                  HGC_RXM_DFX_STATUS14_MEM2_OFF)
 169 #define HGC_RXM_DFX_STATUS15    0xaec
 170 #define HGC_RXM_DFX_STATUS15_MEM3_OFF           0
 171 #define HGC_RXM_DFX_STATUS15_MEM3_MSK           (0x1ff << \
 172                                                  HGC_RXM_DFX_STATUS15_MEM3_OFF)
 173 /* phy registers need init */
 174 #define PORT_BASE                       (0x2000)
 175
 176 #define PHY_CFG                         (PORT_BASE + 0x0)
 177 #define HARD_PHY_LINKRATE               (PORT_BASE + 0x4)
 178 #define PHY_CFG_ENA_OFF                 0
 179 #define PHY_CFG_ENA_MSK                 (0x1 << PHY_CFG_ENA_OFF)
 180 #define PHY_CFG_DC_OPT_OFF              2
 181 #define PHY_CFG_DC_OPT_MSK              (0x1 << PHY_CFG_DC_OPT_OFF)
 182 #define PROG_PHY_LINK_RATE              (PORT_BASE + 0x8)
 183 #define PROG_PHY_LINK_RATE_MAX_OFF      0
 184 #define PROG_PHY_LINK_RATE_MAX_MSK      (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
 185 #define PHY_CTRL                        (PORT_BASE + 0x14)
 186 #define PHY_CTRL_RESET_OFF              0
 187 #define PHY_CTRL_RESET_MSK              (0x1 << PHY_CTRL_RESET_OFF)
 188 #define SAS_PHY_CTRL                    (PORT_BASE + 0x20)
 189 #define SL_CFG                          (PORT_BASE + 0x84)
 190 #define PHY_PCN                         (PORT_BASE + 0x44)
 191 #define SL_TOUT_CFG                     (PORT_BASE + 0x8c)
 192 #define SL_CONTROL                      (PORT_BASE + 0x94)
 193 #define SL_CONTROL_NOTIFY_EN_OFF        0
 194 #define SL_CONTROL_NOTIFY_EN_MSK        (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
 195 #define SL_CONTROL_CTA_OFF              17
 196 #define SL_CONTROL_CTA_MSK              (0x1 << SL_CONTROL_CTA_OFF)
 197 #define RX_PRIMS_STATUS                 (PORT_BASE + 0x98)
 198 #define RX_BCAST_CHG_OFF                1
 199 #define RX_BCAST_CHG_MSK                (0x1 << RX_BCAST_CHG_OFF)
 200 #define TX_ID_DWORD0                    (PORT_BASE + 0x9c)
 201 #define TX_ID_DWORD1                    (PORT_BASE + 0xa0)
 202 #define TX_ID_DWORD2                    (PORT_BASE + 0xa4)
 203 #define TX_ID_DWORD3                    (PORT_BASE + 0xa8)
 204 #define TX_ID_DWORD4                    (PORT_BASE + 0xaC)
 205 #define TX_ID_DWORD5                    (PORT_BASE + 0xb0)
 206 #define TX_ID_DWORD6                    (PORT_BASE + 0xb4)
 207 #define TXID_AUTO                       (PORT_BASE + 0xb8)
 208 #define TXID_AUTO_CT3_OFF               1
 209 #define TXID_AUTO_CT3_MSK               (0x1 << TXID_AUTO_CT3_OFF)
 210 #define TXID_AUTO_CTB_OFF               11
 211 #define TXID_AUTO_CTB_MSK               (0x1 << TXID_AUTO_CTB_OFF)
 212 #define TX_HARDRST_OFF                  2
 213 #define TX_HARDRST_MSK                  (0x1 << TX_HARDRST_OFF)
 214 #define RX_IDAF_DWORD0                  (PORT_BASE + 0xc4)
 215 #define RX_IDAF_DWORD1                  (PORT_BASE + 0xc8)
 216 #define RX_IDAF_DWORD2                  (PORT_BASE + 0xcc)
 217 #define RX_IDAF_DWORD3                  (PORT_BASE + 0xd0)
 218 #define RX_IDAF_DWORD4                  (PORT_BASE + 0xd4)
 219 #define RX_IDAF_DWORD5                  (PORT_BASE + 0xd8)
 220 #define RX_IDAF_DWORD6                  (PORT_BASE + 0xdc)
 221 #define RXOP_CHECK_CFG_H                (PORT_BASE + 0xfc)
 222 #define CON_CONTROL                     (PORT_BASE + 0x118)
 223 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF        0
 224 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK        \
 225                 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
 226 #define DONE_RECEIVED_TIME              (PORT_BASE + 0x11c)
 227 #define CHL_INT0                        (PORT_BASE + 0x1b4)
 228 #define CHL_INT0_HOTPLUG_TOUT_OFF       0
 229 #define CHL_INT0_HOTPLUG_TOUT_MSK       (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
 230 #define CHL_INT0_SL_RX_BCST_ACK_OFF     1
 231 #define CHL_INT0_SL_RX_BCST_ACK_MSK     (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
 232 #define CHL_INT0_SL_PHY_ENABLE_OFF      2
 233 #define CHL_INT0_SL_PHY_ENABLE_MSK      (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
 234 #define CHL_INT0_NOT_RDY_OFF            4
 235 #define CHL_INT0_NOT_RDY_MSK            (0x1 << CHL_INT0_NOT_RDY_OFF)
 236 #define CHL_INT0_PHY_RDY_OFF            5
 237 #define CHL_INT0_PHY_RDY_MSK            (0x1 << CHL_INT0_PHY_RDY_OFF)
 238 #define CHL_INT1                        (PORT_BASE + 0x1b8)
 239 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF    15
 240 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
 241 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF    17
 242 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
 243 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
 244 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
 245 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
 246 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
 247 #define CHL_INT2                        (PORT_BASE + 0x1bc)
 248 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF  0
 249 #define CHL_INT0_MSK                    (PORT_BASE + 0x1c0)
 250 #define CHL_INT1_MSK                    (PORT_BASE + 0x1c4)
 251 #define CHL_INT2_MSK                    (PORT_BASE + 0x1c8)
 252 #define CHL_INT_COAL_EN                 (PORT_BASE + 0x1d0)
 253 #define DMA_TX_DFX0                             (PORT_BASE + 0x200)
 254 #define DMA_TX_DFX1                             (PORT_BASE + 0x204)
 255 #define DMA_TX_DFX1_IPTT_OFF            0
 256 #define DMA_TX_DFX1_IPTT_MSK            (0xffff << DMA_TX_DFX1_IPTT_OFF)
 257 #define DMA_TX_FIFO_DFX0                (PORT_BASE + 0x240)
 258 #define PORT_DFX0                               (PORT_BASE + 0x258)
 259 #define LINK_DFX2                                       (PORT_BASE + 0X264)
 260 #define LINK_DFX2_RCVR_HOLD_STS_OFF     9
 261 #define LINK_DFX2_RCVR_HOLD_STS_MSK     (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
 262 #define LINK_DFX2_SEND_HOLD_STS_OFF     10
 263 #define LINK_DFX2_SEND_HOLD_STS_MSK     (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
 264 #define SAS_ERR_CNT4_REG                (PORT_BASE + 0x290)
 265 #define SAS_ERR_CNT6_REG                (PORT_BASE + 0x298)
 266 #define PHY_CTRL_RDY_MSK                (PORT_BASE + 0x2b0)
 267 #define PHYCTRL_NOT_RDY_MSK             (PORT_BASE + 0x2b4)
 268 #define PHYCTRL_DWS_RESET_MSK           (PORT_BASE + 0x2b8)
 269 #define PHYCTRL_PHY_ENA_MSK             (PORT_BASE + 0x2bc)
 270 #define SL_RX_BCAST_CHK_MSK             (PORT_BASE + 0x2c0)
 271 #define PHYCTRL_OOB_RESTART_MSK         (PORT_BASE + 0x2c4)
 272 #define DMA_TX_STATUS                   (PORT_BASE + 0x2d0)
 273 #define DMA_TX_STATUS_BUSY_OFF          0
 274 #define DMA_TX_STATUS_BUSY_MSK          (0x1 << DMA_TX_STATUS_BUSY_OFF)
 275 #define DMA_RX_STATUS                   (PORT_BASE + 0x2e8)
 276 #define DMA_RX_STATUS_BUSY_OFF          0
 277 #define DMA_RX_STATUS_BUSY_MSK          (0x1 << DMA_RX_STATUS_BUSY_OFF)
 278
 279 #define AXI_CFG                         (0x5100)
 280 #define AM_CFG_MAX_TRANS                (0x5010)
 281 #define AM_CFG_SINGLE_PORT_MAX_TRANS    (0x5014)
 282
 283 #define AXI_MASTER_CFG_BASE             (0x5000)
 284 #define AM_CTRL_GLOBAL                  (0x0)
 285 #define AM_CURR_TRANS_RETURN    (0x150)
 286
 287 /* HW dma structures */
 288 /* Delivery queue header */
 289 /* dw0 */
 290 #define CMD_HDR_ABORT_FLAG_OFF          0
 291 #define CMD_HDR_ABORT_FLAG_MSK          (0x3 << CMD_HDR_ABORT_FLAG_OFF)
 292 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF   2
 293 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK   (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
 294 #define CMD_HDR_RESP_REPORT_OFF         5
 295 #define CMD_HDR_RESP_REPORT_MSK         (0x1 << CMD_HDR_RESP_REPORT_OFF)
 296 #define CMD_HDR_TLR_CTRL_OFF            6
 297 #define CMD_HDR_TLR_CTRL_MSK            (0x3 << CMD_HDR_TLR_CTRL_OFF)
 298 #define CMD_HDR_PORT_OFF                18
 299 #define CMD_HDR_PORT_MSK                (0xf << CMD_HDR_PORT_OFF)
 300 #define CMD_HDR_PRIORITY_OFF            27
 301 #define CMD_HDR_PRIORITY_MSK            (0x1 << CMD_HDR_PRIORITY_OFF)
 302 #define CMD_HDR_CMD_OFF                 29
 303 #define CMD_HDR_CMD_MSK                 (0x7 << CMD_HDR_CMD_OFF)
 304 /* dw1 */
 305 #define CMD_HDR_DIR_OFF                 5
 306 #define CMD_HDR_DIR_MSK                 (0x3 << CMD_HDR_DIR_OFF)
 307 #define CMD_HDR_RESET_OFF               7
 308 #define CMD_HDR_RESET_MSK               (0x1 << CMD_HDR_RESET_OFF)
 309 #define CMD_HDR_VDTL_OFF                10
 310 #define CMD_HDR_VDTL_MSK                (0x1 << CMD_HDR_VDTL_OFF)
 311 #define CMD_HDR_FRAME_TYPE_OFF          11
 312 #define CMD_HDR_FRAME_TYPE_MSK          (0x1f << CMD_HDR_FRAME_TYPE_OFF)
 313 #define CMD_HDR_DEV_ID_OFF              16
 314 #define CMD_HDR_DEV_ID_MSK              (0xffff << CMD_HDR_DEV_ID_OFF)
 315 /* dw2 */
 316 #define CMD_HDR_CFL_OFF                 0
 317 #define CMD_HDR_CFL_MSK                 (0x1ff << CMD_HDR_CFL_OFF)
 318 #define CMD_HDR_NCQ_TAG_OFF             10
 319 #define CMD_HDR_NCQ_TAG_MSK             (0x1f << CMD_HDR_NCQ_TAG_OFF)
 320 #define CMD_HDR_MRFL_OFF                15
 321 #define CMD_HDR_MRFL_MSK                (0x1ff << CMD_HDR_MRFL_OFF)
 322 #define CMD_HDR_SG_MOD_OFF              24
 323 #define CMD_HDR_SG_MOD_MSK              (0x3 << CMD_HDR_SG_MOD_OFF)
 324 #define CMD_HDR_FIRST_BURST_OFF         26
 325 #define CMD_HDR_FIRST_BURST_MSK         (0x1 << CMD_HDR_SG_MOD_OFF)
 326 /* dw3 */
 327 #define CMD_HDR_IPTT_OFF                0
 328 #define CMD_HDR_IPTT_MSK                (0xffff << CMD_HDR_IPTT_OFF)
 329 /* dw6 */
 330 #define CMD_HDR_DIF_SGL_LEN_OFF         0
 331 #define CMD_HDR_DIF_SGL_LEN_MSK         (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
 332 #define CMD_HDR_DATA_SGL_LEN_OFF        16
 333 #define CMD_HDR_DATA_SGL_LEN_MSK        (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
 334 #define CMD_HDR_ABORT_IPTT_OFF          16
 335 #define CMD_HDR_ABORT_IPTT_MSK          (0xffff << CMD_HDR_ABORT_IPTT_OFF)
 336
 337 /* Completion header */
 338 /* dw0 */
 339 #define CMPLT_HDR_ERR_PHASE_OFF 2
 340 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
 341 #define CMPLT_HDR_RSPNS_XFRD_OFF        10
 342 #define CMPLT_HDR_RSPNS_XFRD_MSK        (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
 343 #define CMPLT_HDR_ERX_OFF               12
 344 #define CMPLT_HDR_ERX_MSK               (0x1 << CMPLT_HDR_ERX_OFF)
 345 #define CMPLT_HDR_ABORT_STAT_OFF        13
 346 #define CMPLT_HDR_ABORT_STAT_MSK        (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
 347 /* abort_stat */
 348 #define STAT_IO_NOT_VALID               0x1
 349 #define STAT_IO_NO_DEVICE               0x2
 350 #define STAT_IO_COMPLETE                0x3
 351 #define STAT_IO_ABORTED                 0x4
 352 /* dw1 */
 353 #define CMPLT_HDR_IPTT_OFF              0
 354 #define CMPLT_HDR_IPTT_MSK              (0xffff << CMPLT_HDR_IPTT_OFF)
 355 #define CMPLT_HDR_DEV_ID_OFF            16
 356 #define CMPLT_HDR_DEV_ID_MSK            (0xffff << CMPLT_HDR_DEV_ID_OFF)
 357
 358 /* ITCT header */
 359 /* qw0 */
 360 #define ITCT_HDR_DEV_TYPE_OFF           0
 361 #define ITCT_HDR_DEV_TYPE_MSK           (0x3 << ITCT_HDR_DEV_TYPE_OFF)
 362 #define ITCT_HDR_VALID_OFF              2
 363 #define ITCT_HDR_VALID_MSK              (0x1 << ITCT_HDR_VALID_OFF)
 364 #define ITCT_HDR_MCR_OFF                5
 365 #define ITCT_HDR_MCR_MSK                (0xf << ITCT_HDR_MCR_OFF)
 366 #define ITCT_HDR_VLN_OFF                9
 367 #define ITCT_HDR_VLN_MSK                (0xf << ITCT_HDR_VLN_OFF)
 368 #define ITCT_HDR_SMP_TIMEOUT_OFF        16
 369 #define ITCT_HDR_SMP_TIMEOUT_8US        1
 370 #define ITCT_HDR_SMP_TIMEOUT            (ITCT_HDR_SMP_TIMEOUT_8US * \
 371                                          250) /* 2ms */
 372 #define ITCT_HDR_AWT_CONTINUE_OFF       25
 373 #define ITCT_HDR_PORT_ID_OFF            28
 374 #define ITCT_HDR_PORT_ID_MSK            (0xf << ITCT_HDR_PORT_ID_OFF)
 375 /* qw2 */
 376 #define ITCT_HDR_INLT_OFF               0
 377 #define ITCT_HDR_INLT_MSK               (0xffffULL << ITCT_HDR_INLT_OFF)
 378 #define ITCT_HDR_BITLT_OFF              16
 379 #define ITCT_HDR_BITLT_MSK              (0xffffULL << ITCT_HDR_BITLT_OFF)
 380 #define ITCT_HDR_MCTLT_OFF              32
 381 #define ITCT_HDR_MCTLT_MSK              (0xffffULL << ITCT_HDR_MCTLT_OFF)
 382 #define ITCT_HDR_RTOLT_OFF              48
 383 #define ITCT_HDR_RTOLT_MSK              (0xffffULL << ITCT_HDR_RTOLT_OFF)
 384
 385 #define HISI_SAS_FATAL_INT_NR   2
 386
 387 struct hisi_sas_complete_v2_hdr {
 388         __le32 dw0;
 389         __le32 dw1;
 390         __le32 act;
 391         __le32 dw3;
 392 };
 393
 394 struct hisi_sas_err_record_v2 {
 395         /* dw0 */
 396         __le32 trans_tx_fail_type;
 397
 398         /* dw1 */
 399         __le32 trans_rx_fail_type;
 400
 401         /* dw2 */
 402         __le16 dma_tx_err_type;
 403         __le16 sipc_rx_err_type;
 404
 405         /* dw3 */
 406         __le32 dma_rx_err_type;
 407 };
 408
 409 struct signal_attenuation_s {
 410         u32 de_emphasis;
 411         u32 preshoot;
 412         u32 boost;
 413 };
 414
 415 struct sig_atten_lu_s {
 416         const struct signal_attenuation_s *att;
 417         u32 sas_phy_ctrl;
 418 };
 419
 420 static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
 421         {
 422                 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
 423                 .msk = HGC_DQE_ECC_1B_ADDR_MSK,
 424                 .shift = HGC_DQE_ECC_1B_ADDR_OFF,
 425                 .msg = "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n",
 426                 .reg = HGC_DQE_ECC_ADDR,
 427         },
 428         {
 429                 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
 430                 .msk = HGC_IOST_ECC_1B_ADDR_MSK,
 431                 .shift = HGC_IOST_ECC_1B_ADDR_OFF,
 432                 .msg = "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n",
 433                 .reg = HGC_IOST_ECC_ADDR,
 434         },
 435         {
 436                 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
 437                 .msk = HGC_ITCT_ECC_1B_ADDR_MSK,
 438                 .shift = HGC_ITCT_ECC_1B_ADDR_OFF,
 439                 .msg = "hgc_itct_acc1b_intr found: am address is 0x%08X\n",
 440                 .reg = HGC_ITCT_ECC_ADDR,
 441         },
 442         {
 443                 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
 444                 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
 445                 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
 446                 .msg = "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n",
 447                 .reg = HGC_LM_DFX_STATUS2,
 448         },
 449         {
 450                 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
 451                 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
 452                 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
 453                 .msg = "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n",
 454                 .reg = HGC_LM_DFX_STATUS2,
 455         },
 456         {
 457                 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
 458                 .msk = HGC_CQE_ECC_1B_ADDR_MSK,
 459                 .shift = HGC_CQE_ECC_1B_ADDR_OFF,
 460                 .msg = "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n",
 461                 .reg = HGC_CQE_ECC_ADDR,
 462         },
 463         {
 464                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
 465                 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
 466                 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
 467                 .msg = "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n",
 468                 .reg = HGC_RXM_DFX_STATUS14,
 469         },
 470         {
 471                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
 472                 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
 473                 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
 474                 .msg = "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n",
 475                 .reg = HGC_RXM_DFX_STATUS14,
 476         },
 477         {
 478                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
 479                 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
 480                 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
 481                 .msg = "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n",
 482                 .reg = HGC_RXM_DFX_STATUS14,
 483         },
 484         {
 485                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
 486                 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
 487                 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
 488                 .msg = "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n",
 489                 .reg = HGC_RXM_DFX_STATUS15,
 490         },
 491 };
 492
 493 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
 494         {
 495                 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
 496                 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
 497                 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
 498                 .msg = "hgc_dqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
 499                 .reg = HGC_DQE_ECC_ADDR,
 500         },
 501         {
 502                 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
 503                 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
 504                 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
 505                 .msg = "hgc_iost_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
 506                 .reg = HGC_IOST_ECC_ADDR,
 507         },
 508         {
 509                 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
 510                 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
 511                 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
 512                 .msg = "hgc_itct_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
 513                 .reg = HGC_ITCT_ECC_ADDR,
 514         },
 515         {
 516                 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
 517                 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
 518                 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
 519                 .msg = "hgc_iostl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 520                 .reg = HGC_LM_DFX_STATUS2,
 521         },
 522         {
 523                 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
 524                 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
 525                 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
 526                 .msg = "hgc_itctl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 527                 .reg = HGC_LM_DFX_STATUS2,
 528         },
 529         {
 530                 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
 531                 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
 532                 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
 533                 .msg = "hgc_cqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
 534                 .reg = HGC_CQE_ECC_ADDR,
 535         },
 536         {
 537                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
 538                 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
 539                 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
 540                 .msg = "rxm_mem0_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 541                 .reg = HGC_RXM_DFX_STATUS14,
 542         },
 543         {
 544                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
 545                 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
 546                 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
 547                 .msg = "rxm_mem1_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 548                 .reg = HGC_RXM_DFX_STATUS14,
 549         },
 550         {
 551                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
 552                 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
 553                 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
 554                 .msg = "rxm_mem2_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 555                 .reg = HGC_RXM_DFX_STATUS14,
 556         },
 557         {
 558                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
 559                 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
 560                 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
 561                 .msg = "rxm_mem3_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 562                 .reg = HGC_RXM_DFX_STATUS15,
 563         },
 564 };
 565
 566 enum {
 567         HISI_SAS_PHY_PHY_UPDOWN,
 568         HISI_SAS_PHY_CHNL_INT,
 569         HISI_SAS_PHY_INT_NR
 570 };
 571
 572 enum {
 573         TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
 574         TRANS_RX_FAIL_BASE = 0x20, /* dw1 */
 575         DMA_TX_ERR_BASE = 0x40, /* dw2 bit 15-0 */
 576         SIPC_RX_ERR_BASE = 0x50, /* dw2 bit 31-16*/
 577         DMA_RX_ERR_BASE = 0x60, /* dw3 */
 578
 579         /* trans tx*/
 580         TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
 581         TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
 582         TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
 583         TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
 584         TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
 585         RESERVED0, /* 0x5 */
 586         TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
 587         TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
 588         TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
 589         TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
 590         TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
 591         TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
 592         TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
 593         TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
 594         TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
 595         TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
 596         TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
 597         TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
 598         TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
 599         TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
 600         TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
 601         TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
 602         TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
 603         TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
 604         TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
 605         TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
 606         TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
 607         TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
 608         /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
 609         TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
 610         /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
 611         TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
 612         TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
 613         /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
 614         TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
 615
 616         /* trans rx */
 617         TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x20 */
 618         TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x21 for sata/stp */
 619         TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x22 for ssp/smp */
 620         /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
 621         TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x23 for sata/stp */
 622         TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x24 for sata/stp */
 623         TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x25 for smp */
 624         /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
 625         TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x26 for sata/stp*/
 626         TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x27 */
 627         TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x28 */
 628         TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x29 */
 629         TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x2a */
 630         RESERVED1, /* 0x2b */
 631         TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x2c */
 632         TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x2d */
 633         TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x2e */
 634         TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x2f */
 635         TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x30 for ssp/smp */
 636         TRANS_RX_ERR_WITH_BAD_HASH, /* 0x31 for ssp */
 637         /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
 638         TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x32 for ssp*/
 639         /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
 640         TRANS_RX_SSP_FRM_LEN_ERR, /* 0x33 for ssp */
 641         /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
 642         RESERVED2, /* 0x34 */
 643         RESERVED3, /* 0x35 */
 644         RESERVED4, /* 0x36 */
 645         RESERVED5, /* 0x37 */
 646         TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x38 */
 647         TRANS_RX_SMP_FRM_LEN_ERR, /* 0x39 */
 648         TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x3a */
 649         RESERVED6, /* 0x3b */
 650         RESERVED7, /* 0x3c */
 651         RESERVED8, /* 0x3d */
 652         RESERVED9, /* 0x3e */
 653         TRANS_RX_R_ERR, /* 0x3f */
 654
 655         /* dma tx */
 656         DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x40 */
 657         DMA_TX_DIF_APP_ERR, /* 0x41 */
 658         DMA_TX_DIF_RPP_ERR, /* 0x42 */
 659         DMA_TX_DATA_SGL_OVERFLOW, /* 0x43 */
 660         DMA_TX_DIF_SGL_OVERFLOW, /* 0x44 */
 661         DMA_TX_UNEXP_XFER_ERR, /* 0x45 */
 662         DMA_TX_UNEXP_RETRANS_ERR, /* 0x46 */
 663         DMA_TX_XFER_LEN_OVERFLOW, /* 0x47 */
 664         DMA_TX_XFER_OFFSET_ERR, /* 0x48 */
 665         DMA_TX_RAM_ECC_ERR, /* 0x49 */
 666         DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x4a */
 667         DMA_TX_MAX_ERR_CODE,
 668
 669         /* sipc rx */
 670         SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x50 */
 671         SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x51 */
 672         SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x52 */
 673         SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x53 */
 674         SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x54 */
 675         SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x55 */
 676         SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x56 */
 677         SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x57 */
 678         SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x58 */
 679         SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x59 */
 680         SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x5a */
 681         SIPC_RX_MAX_ERR_CODE,
 682
 683         /* dma rx */
 684         DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x60 */
 685         DMA_RX_DIF_APP_ERR, /* 0x61 */
 686         DMA_RX_DIF_RPP_ERR, /* 0x62 */
 687         DMA_RX_DATA_SGL_OVERFLOW, /* 0x63 */
 688         DMA_RX_DIF_SGL_OVERFLOW, /* 0x64 */
 689         DMA_RX_DATA_LEN_OVERFLOW, /* 0x65 */
 690         DMA_RX_DATA_LEN_UNDERFLOW, /* 0x66 */
 691         DMA_RX_DATA_OFFSET_ERR, /* 0x67 */
 692         RESERVED10, /* 0x68 */
 693         DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x69 */
 694         DMA_RX_RESP_BUF_OVERFLOW, /* 0x6a */
 695         DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x6b */
 696         DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x6c */
 697         DMA_RX_UNEXP_RDFRAME_ERR, /* 0x6d */
 698         DMA_RX_PIO_DATA_LEN_ERR, /* 0x6e */
 699         DMA_RX_RDSETUP_STATUS_ERR, /* 0x6f */
 700         DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x70 */
 701         DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x71 */
 702         DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x72 */
 703         DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x73 */
 704         DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x74 */
 705         DMA_RX_RDSETUP_OFFSET_ERR, /* 0x75 */
 706         DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x76 */
 707         DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x77 */
 708         DMA_RX_RAM_ECC_ERR, /* 0x78 */
 709         DMA_RX_UNKNOWN_FRM_ERR, /* 0x79 */
 710         DMA_RX_MAX_ERR_CODE,
 711 };
 712
 713 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
 714 #define HISI_MAX_SATA_SUPPORT_V2_HW     (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
 715
 716 #define DIR_NO_DATA 0
 717 #define DIR_TO_INI 1
 718 #define DIR_TO_DEVICE 2
 719 #define DIR_RESERVED 3
 720
 721 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
 722                 err_phase == 0x4 || err_phase == 0x8 ||\
 723                 err_phase == 0x6 || err_phase == 0xa)
 724 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
 725                 err_phase == 0x20 || err_phase == 0x40)
 726
 727 static void link_timeout_disable_link(struct timer_list *t);
 728
 729 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
 730 {
 731         void __iomem *regs = hisi_hba->regs + off;
 732
 733         return readl(regs);
 734 }
 735
 736 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
 737 {
 738         void __iomem *regs = hisi_hba->regs + off;
 739
 740         return readl_relaxed(regs);
 741 }
 742
 743 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
 744 {
 745         void __iomem *regs = hisi_hba->regs + off;
 746
 747         writel(val, regs);
 748 }
 749
 750 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
 751                                  u32 off, u32 val)
 752 {
 753         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 754
 755         writel(val, regs);
 756 }
 757
 758 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
 759                                       int phy_no, u32 off)
 760 {
 761         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 762
 763         return readl(regs);
 764 }
 765
 766 /* This function needs to be protected from pre-emption. */
 767 static int
 768 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
 769                              struct domain_device *device)
 770 {
 771         int sata_dev = dev_is_sata(device);
 772         void *bitmap = hisi_hba->slot_index_tags;
 773         struct hisi_sas_device *sas_dev = device->lldd_dev;
 774         int sata_idx = sas_dev->sata_idx;
 775         int start, end;
 776
 777         if (!sata_dev) {
 778                 /*
 779                  * STP link SoC bug workaround: index starts from 1.
 780                  * additionally, we can only allocate odd IPTT(1~4095)
 781                  * for SAS/SMP device.
 782                  */
 783                 start = 1;
 784                 end = hisi_hba->slot_index_count;
 785         } else {
 786                 if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
 787                         return -EINVAL;
 788
 789                 /*
 790                  * For SATA device: allocate even IPTT in this interval
 791                  * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
 792                  * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
 793                  * SoC bug workaround. So we ignore the first 32 even IPTTs.
 794                  */
 795                 start = 64 * (sata_idx + 1);
 796                 end = 64 * (sata_idx + 2);
 797         }
 798
 799         while (1) {
 800                 start = find_next_zero_bit(bitmap,
 801                                         hisi_hba->slot_index_count, start);
 802                 if (start >= end)
 803                         return -SAS_QUEUE_FULL;
 804                 /*
 805                   * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
 806                   */
 807                 if (sata_dev ^ (start & 1))
 808                         break;
 809                 start++;
 810         }
 811
 812         set_bit(start, bitmap);
 813         *slot_idx = start;
 814         return 0;
 815 }
 816
 817 static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
 818 {
 819         unsigned int index;
 820         struct device *dev = hisi_hba->dev;
 821         void *bitmap = hisi_hba->sata_dev_bitmap;
 822
 823         index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
 824         if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
 825                 dev_warn(dev, "alloc sata index failed, index=%d\n", index);
 826                 return false;
 827         }
 828
 829         set_bit(index, bitmap);
 830         *idx = index;
 831         return true;
 832 }
 833
 834
 835 static struct
 836 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
 837 {
 838         struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
 839         struct hisi_sas_device *sas_dev = NULL;
 840         int i, sata_dev = dev_is_sata(device);
 841         int sata_idx = -1;
 842         unsigned long flags;
 843
 844         spin_lock_irqsave(&hisi_hba->lock, flags);
 845
 846         if (sata_dev)
 847                 if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
 848                         goto out;
 849
 850         for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
 851                 /*
 852                  * SATA device id bit0 should be 0
 853                  */
 854                 if (sata_dev && (i & 1))
 855                         continue;
 856                 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
 857                         int queue = i % hisi_hba->queue_count;
 858                         struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
 859
 860                         hisi_hba->devices[i].device_id = i;
 861                         sas_dev = &hisi_hba->devices[i];
 862                         sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
 863                         sas_dev->dev_type = device->dev_type;
 864                         sas_dev->hisi_hba = hisi_hba;
 865                         sas_dev->sas_device = device;
 866                         sas_dev->sata_idx = sata_idx;
 867                         sas_dev->dq = dq;
 868                         INIT_LIST_HEAD(&hisi_hba->devices[i].list);
 869                         break;
 870                 }
 871         }
 872
 873 out:
 874         spin_unlock_irqrestore(&hisi_hba->lock, flags);
 875
 876         return sas_dev;
 877 }
 878
 879 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 880 {
 881         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 882
 883         cfg &= ~PHY_CFG_DC_OPT_MSK;
 884         cfg |= 1 << PHY_CFG_DC_OPT_OFF;
 885         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 886 }
 887
 888 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 889 {
 890         struct sas_identify_frame identify_frame;
 891         u32 *identify_buffer;
 892
 893         memset(&identify_frame, 0, sizeof(identify_frame));
 894         identify_frame.dev_type = SAS_END_DEVICE;
 895         identify_frame.frame_type = 0;
 896         identify_frame._un1 = 1;
 897         identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
 898         identify_frame.target_bits = SAS_PROTOCOL_NONE;
 899         memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 900         memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 901         identify_frame.phy_id = phy_no;
 902         identify_buffer = (u32 *)(&identify_frame);
 903
 904         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
 905                         __swab32(identify_buffer[0]));
 906         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
 907                         __swab32(identify_buffer[1]));
 908         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
 909                         __swab32(identify_buffer[2]));
 910         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
 911                         __swab32(identify_buffer[3]));
 912         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
 913                         __swab32(identify_buffer[4]));
 914         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
 915                         __swab32(identify_buffer[5]));
 916 }
 917
 918 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
 919                              struct hisi_sas_device *sas_dev)
 920 {
 921         struct domain_device *device = sas_dev->sas_device;
 922         struct device *dev = hisi_hba->dev;
 923         u64 qw0, device_id = sas_dev->device_id;
 924         struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
 925         struct domain_device *parent_dev = device->parent;
 926         struct asd_sas_port *sas_port = device->port;
 927         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
 928
 929         memset(itct, 0, sizeof(*itct));
 930
 931         /* qw0 */
 932         qw0 = 0;
 933         switch (sas_dev->dev_type) {
 934         case SAS_END_DEVICE:
 935         case SAS_EDGE_EXPANDER_DEVICE:
 936         case SAS_FANOUT_EXPANDER_DEVICE:
 937                 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
 938                 break;
 939         case SAS_SATA_DEV:
 940         case SAS_SATA_PENDING:
 941                 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
 942                         qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
 943                 else
 944                         qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
 945                 break;
 946         default:
 947                 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
 948                          sas_dev->dev_type);
 949         }
 950
 951         qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
 952                 (device->linkrate << ITCT_HDR_MCR_OFF) |
 953                 (1 << ITCT_HDR_VLN_OFF) |
 954                 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
 955                 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
 956                 (port->id << ITCT_HDR_PORT_ID_OFF));
 957         itct->qw0 = cpu_to_le64(qw0);
 958
 959         /* qw1 */
 960         memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
 961         itct->sas_addr = __swab64(itct->sas_addr);
 962
 963         /* qw2 */
 964         if (!dev_is_sata(device))
 965                 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
 966                                         (0x1ULL << ITCT_HDR_BITLT_OFF) |
 967                                         (0x32ULL << ITCT_HDR_MCTLT_OFF) |
 968                                         (0x1ULL << ITCT_HDR_RTOLT_OFF));
 969 }
 970
 971 static void clear_itct_v2_hw(struct hisi_hba *hisi_hba,
 972                               struct hisi_sas_device *sas_dev)
 973 {
 974         DECLARE_COMPLETION_ONSTACK(completion);
 975         u64 dev_id = sas_dev->device_id;
 976         struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
 977         u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
 978         int i;
 979
 980         sas_dev->completion = &completion;
 981
 982         /* clear the itct interrupt state */
 983         if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
 984                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
 985                                  ENT_INT_SRC3_ITC_INT_MSK);
 986
 987         for (i = 0; i < 2; i++) {
 988                 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
 989                 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
 990                 wait_for_completion(sas_dev->completion);
 991
 992                 memset(itct, 0, sizeof(struct hisi_sas_itct));
 993         }
 994 }
 995
 996 static void free_device_v2_hw(struct hisi_sas_device *sas_dev)
 997 {
 998         struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
 999
1000         /* SoC bug workaround */
1001         if (dev_is_sata(sas_dev->sas_device))
1002                 clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
1003 }
1004
1005 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
1006 {
1007         int i, reset_val;
1008         u32 val;
1009         unsigned long end_time;
1010         struct device *dev = hisi_hba->dev;
1011
1012         /* The mask needs to be set depending on the number of phys */
1013         if (hisi_hba->n_phy == 9)
1014                 reset_val = 0x1fffff;
1015         else
1016                 reset_val = 0x7ffff;
1017
1018         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
1019
1020         /* Disable all of the PHYs */
1021         for (i = 0; i < hisi_hba->n_phy; i++) {
1022                 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
1023
1024                 phy_cfg &= ~PHY_CTRL_RESET_MSK;
1025                 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
1026         }
1027         udelay(50);
1028
1029         /* Ensure DMA tx & rx idle */
1030         for (i = 0; i < hisi_hba->n_phy; i++) {
1031                 u32 dma_tx_status, dma_rx_status;
1032
1033                 end_time = jiffies + msecs_to_jiffies(1000);
1034
1035                 while (1) {
1036                         dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
1037                                                             DMA_TX_STATUS);
1038                         dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
1039                                                             DMA_RX_STATUS);
1040
1041                         if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
1042                                 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
1043                                 break;
1044
1045                         msleep(20);
1046                         if (time_after(jiffies, end_time))
1047                                 return -EIO;
1048                 }
1049         }
1050
1051         /* Ensure axi bus idle */
1052         end_time = jiffies + msecs_to_jiffies(1000);
1053         while (1) {
1054                 u32 axi_status =
1055                         hisi_sas_read32(hisi_hba, AXI_CFG);
1056
1057                 if (axi_status == 0)
1058                         break;
1059
1060                 msleep(20);
1061                 if (time_after(jiffies, end_time))
1062                         return -EIO;
1063         }
1064
1065         if (ACPI_HANDLE(dev)) {
1066                 acpi_status s;
1067
1068                 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
1069                 if (ACPI_FAILURE(s)) {
1070                         dev_err(dev, "Reset failed\n");
1071                         return -EIO;
1072                 }
1073         } else if (hisi_hba->ctrl) {
1074                 /* reset and disable clock*/
1075                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
1076                                 reset_val);
1077                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
1078                                 reset_val);
1079                 msleep(1);
1080                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
1081                 if (reset_val != (val & reset_val)) {
1082                         dev_err(dev, "SAS reset fail.\n");
1083                         return -EIO;
1084                 }
1085
1086                 /* De-reset and enable clock*/
1087                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
1088                                 reset_val);
1089                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
1090                                 reset_val);
1091                 msleep(1);
1092                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
1093                                 &val);
1094                 if (val & reset_val) {
1095                         dev_err(dev, "SAS de-reset fail.\n");
1096                         return -EIO;
1097                 }
1098         } else {
1099                 dev_err(dev, "no reset method\n");
1100                 return -EINVAL;
1101         }
1102
1103         return 0;
1104 }
1105
1106 /* This function needs to be called after resetting SAS controller. */
1107 static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1108 {
1109         u32 cfg;
1110         int phy_no;
1111
1112         hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
1113         for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1114                 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
1115                 if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
1116                         continue;
1117
1118                 cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1119                 hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
1120         }
1121 }
1122
1123 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1124 {
1125         int phy_no;
1126         u32 dma_tx_dfx1;
1127
1128         for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1129                 if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
1130                         continue;
1131
1132                 dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1133                                                 DMA_TX_DFX1);
1134                 if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
1135                         u32 cfg = hisi_sas_phy_read32(hisi_hba,
1136                                 phy_no, CON_CONTROL);
1137
1138                         cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1139                         hisi_sas_phy_write32(hisi_hba, phy_no,
1140                                 CON_CONTROL, cfg);
1141                         clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
1142                 }
1143         }
1144 }
1145
1146 static const struct signal_attenuation_s x6000 = {9200, 0, 10476};
1147 static const struct sig_atten_lu_s sig_atten_lu[] = {
1148         { &x6000, 0x3016a68 },
1149 };
1150
1151 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
1152 {
1153         struct device *dev = hisi_hba->dev;
1154         u32 sas_phy_ctrl = 0x30b9908;
1155         u32 signal[3];
1156         int i;
1157
1158         /* Global registers init */
1159
1160         /* Deal with am-max-transmissions quirk */
1161         if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
1162                 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
1163                 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
1164                                  0x2020);
1165         } /* Else, use defaults -> do nothing */
1166
1167         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
1168                          (u32)((1ULL << hisi_hba->queue_count) - 1));
1169         hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
1170         hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
1171         hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
1172         hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
1173         hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
1174         hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
1175         hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
1176         hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
1177         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
1178         hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
1179         hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
1180         hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
1181         hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
1182         hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
1183         hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
1184         hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
1185         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
1186         hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
1187         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
1188         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
1189         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
1190         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
1191         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
1192         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
1193         for (i = 0; i < hisi_hba->queue_count; i++)
1194                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
1195
1196         hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
1197         hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
1198
1199         /* Get sas_phy_ctrl value to deal with TX FFE issue. */
1200         if (!device_property_read_u32_array(dev, "hisilicon,signal-attenuation",
1201                                             signal, ARRAY_SIZE(signal))) {
1202                 for (i = 0; i < ARRAY_SIZE(sig_atten_lu); i++) {
1203                         const struct sig_atten_lu_s *lookup = &sig_atten_lu[i];
1204                         const struct signal_attenuation_s *att = lookup->att;
1205
1206                         if ((signal[0] == att->de_emphasis) &&
1207                             (signal[1] == att->preshoot) &&
1208                             (signal[2] == att->boost)) {
1209                                 sas_phy_ctrl = lookup->sas_phy_ctrl;
1210                                 break;
1211                         }
1212                 }
1213
1214                 if (i == ARRAY_SIZE(sig_atten_lu))
1215                         dev_warn(dev, "unknown signal attenuation values, using default PHY ctrl config\n");
1216         }
1217
1218         for (i = 0; i < hisi_hba->n_phy; i++) {
1219                 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
1220                 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, sas_phy_ctrl);
1221                 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
1222                 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
1223                 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
1224                 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
1225                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
1226                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
1227                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
1228                 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
1229                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff857fff);
1230                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbfe);
1231                 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
1232                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
1233                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
1234                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
1235                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
1236                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
1237                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
1238                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
1239                 if (hisi_hba->refclk_frequency_mhz == 66)
1240                         hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
1241                 /* else, do nothing -> leave it how you found it */
1242         }
1243
1244         for (i = 0; i < hisi_hba->queue_count; i++) {
1245                 /* Delivery queue */
1246                 hisi_sas_write32(hisi_hba,
1247                                  DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
1248                                  upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
1249
1250                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
1251                                  lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
1252
1253                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
1254                                  HISI_SAS_QUEUE_SLOTS);
1255
1256                 /* Completion queue */
1257                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
1258                                  upper_32_bits(hisi_hba->complete_hdr_dma[i]));
1259
1260                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
1261                                  lower_32_bits(hisi_hba->complete_hdr_dma[i]));
1262
1263                 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
1264                                  HISI_SAS_QUEUE_SLOTS);
1265         }
1266
1267         /* itct */
1268         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
1269                          lower_32_bits(hisi_hba->itct_dma));
1270
1271         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
1272                          upper_32_bits(hisi_hba->itct_dma));
1273
1274         /* iost */
1275         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
1276                          lower_32_bits(hisi_hba->iost_dma));
1277
1278         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
1279                          upper_32_bits(hisi_hba->iost_dma));
1280
1281         /* breakpoint */
1282         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
1283                          lower_32_bits(hisi_hba->breakpoint_dma));
1284
1285         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
1286                          upper_32_bits(hisi_hba->breakpoint_dma));
1287
1288         /* SATA broken msg */
1289         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
1290                          lower_32_bits(hisi_hba->sata_breakpoint_dma));
1291
1292         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
1293                          upper_32_bits(hisi_hba->sata_breakpoint_dma));
1294
1295         /* SATA initial fis */
1296         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
1297                          lower_32_bits(hisi_hba->initial_fis_dma));
1298
1299         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
1300                          upper_32_bits(hisi_hba->initial_fis_dma));
1301 }
1302
1303 static void link_timeout_enable_link(struct timer_list *t)
1304 {
1305         struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1306         int i, reg_val;
1307
1308         for (i = 0; i < hisi_hba->n_phy; i++) {
1309                 if (hisi_hba->reject_stp_links_msk & BIT(i))
1310                         continue;
1311
1312                 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
1313                 if (!(reg_val & BIT(0))) {
1314                         hisi_sas_phy_write32(hisi_hba, i,
1315                                         CON_CONTROL, 0x7);
1316                         break;
1317                 }
1318         }
1319
1320         hisi_hba->timer.function = link_timeout_disable_link;
1321         mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
1322 }
1323
1324 static void link_timeout_disable_link(struct timer_list *t)
1325 {
1326         struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1327         int i, reg_val;
1328
1329         reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
1330         for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
1331                 if (hisi_hba->reject_stp_links_msk & BIT(i))
1332                         continue;
1333
1334                 if (reg_val & BIT(i)) {
1335                         hisi_sas_phy_write32(hisi_hba, i,
1336                                         CON_CONTROL, 0x6);
1337                         break;
1338                 }
1339         }
1340
1341         hisi_hba->timer.function = link_timeout_enable_link;
1342         mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
1343 }
1344
1345 static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
1346 {
1347         hisi_hba->timer.function = link_timeout_disable_link;
1348         hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
1349         add_timer(&hisi_hba->timer);
1350 }
1351
1352 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
1353 {
1354         struct device *dev = hisi_hba->dev;
1355         int rc;
1356
1357         rc = reset_hw_v2_hw(hisi_hba);
1358         if (rc) {
1359                 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1360                 return rc;
1361         }
1362
1363         msleep(100);
1364         init_reg_v2_hw(hisi_hba);
1365
1366         return 0;
1367 }
1368
1369 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1370 {
1371         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1372
1373         cfg |= PHY_CFG_ENA_MSK;
1374         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1375 }
1376
1377 static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1378 {
1379         u32 context;
1380
1381         context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1382         if (context & (1 << phy_no))
1383                 return true;
1384
1385         return false;
1386 }
1387
1388 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1389 {
1390         u32 dfx_val;
1391
1392         dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1393
1394         if (dfx_val & BIT(16))
1395                 return false;
1396
1397         return true;
1398 }
1399
1400 static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1401 {
1402         int i, max_loop = 1000;
1403         struct device *dev = hisi_hba->dev;
1404         u32 status, axi_status, dfx_val, dfx_tx_val;
1405
1406         for (i = 0; i < max_loop; i++) {
1407                 status = hisi_sas_read32_relaxed(hisi_hba,
1408                         AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
1409
1410                 axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
1411                 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1412                 dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
1413                         phy_no, DMA_TX_FIFO_DFX0);
1414
1415                 if ((status == 0x3) && (axi_status == 0x0) &&
1416                     (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
1417                         return true;
1418                 udelay(10);
1419         }
1420         dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1421                         phy_no, status, axi_status,
1422                         dfx_val, dfx_tx_val);
1423         return false;
1424 }
1425
1426 static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1427 {
1428         int i, max_loop = 1000;
1429         struct device *dev = hisi_hba->dev;
1430         u32 status, tx_dfx0;
1431
1432         for (i = 0; i < max_loop; i++) {
1433                 status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
1434                 status = (status & 0x3fc0) >> 6;
1435
1436                 if (status != 0x1)
1437                         return true;
1438
1439                 tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
1440                 if ((tx_dfx0 & 0x1ff) == 0x2)
1441                         return true;
1442                 udelay(10);
1443         }
1444         dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1445                         phy_no, status, tx_dfx0);
1446         return false;
1447 }
1448
1449 static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1450 {
1451         if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
1452                 return true;
1453
1454         if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
1455                 return false;
1456
1457         if (!wait_io_done_v2_hw(hisi_hba, phy_no))
1458                 return false;
1459
1460         return true;
1461 }
1462
1463
1464 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1465 {
1466         u32 cfg, axi_val, dfx0_val, txid_auto;
1467         struct device *dev = hisi_hba->dev;
1468
1469         /* Close axi bus. */
1470         axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
1471                                 AM_CTRL_GLOBAL);
1472         axi_val |= 0x1;
1473         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1474                 AM_CTRL_GLOBAL, axi_val);
1475
1476         if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
1477                 if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
1478                         goto do_disable;
1479
1480                 /* Reset host controller. */
1481                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1482                 return;
1483         }
1484
1485         dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
1486         dfx0_val = (dfx0_val & 0x1fc0) >> 6;
1487         if (dfx0_val != 0x4)
1488                 goto do_disable;
1489
1490         if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
1491                 dev_warn(dev, "phy%d, wait tx fifo need send break\n",
1492                         phy_no);
1493                 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
1494                                         TXID_AUTO);
1495                 txid_auto |= TXID_AUTO_CTB_MSK;
1496                 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1497                                         txid_auto);
1498         }
1499
1500 do_disable:
1501         cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1502         cfg &= ~PHY_CFG_ENA_MSK;
1503         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1504
1505         /* Open axi bus. */
1506         axi_val &= ~0x1;
1507         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1508                 AM_CTRL_GLOBAL, axi_val);
1509 }
1510
1511 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1512 {
1513         config_id_frame_v2_hw(hisi_hba, phy_no);
1514         config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
1515         enable_phy_v2_hw(hisi_hba, phy_no);
1516 }
1517
1518 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1519 {
1520         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1521         u32 txid_auto;
1522
1523         disable_phy_v2_hw(hisi_hba, phy_no);
1524         if (phy->identify.device_type == SAS_END_DEVICE) {
1525                 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1526                 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1527                                         txid_auto | TX_HARDRST_MSK);
1528         }
1529         msleep(100);
1530         start_phy_v2_hw(hisi_hba, phy_no);
1531 }
1532
1533 static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1534 {
1535         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1536         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1537         struct sas_phy *sphy = sas_phy->phy;
1538         u32 err4_reg_val, err6_reg_val;
1539
1540         /* loss dword syn, phy reset problem */
1541         err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
1542
1543         /* disparity err, invalid dword */
1544         err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
1545
1546         sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
1547         sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
1548         sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
1549         sphy->running_disparity_error_count += err6_reg_val & 0xFF;
1550 }
1551
1552 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
1553 {
1554         int i;
1555
1556         for (i = 0; i < hisi_hba->n_phy; i++) {
1557                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1558                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1559
1560                 if (!sas_phy->phy->enabled)
1561                         continue;
1562
1563                 start_phy_v2_hw(hisi_hba, i);
1564         }
1565 }
1566
1567 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1568 {
1569         u32 sl_control;
1570
1571         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1572         sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1573         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1574         msleep(1);
1575         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1576         sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1577         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1578 }
1579
1580 static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
1581 {
1582         return SAS_LINK_RATE_12_0_GBPS;
1583 }
1584
1585 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
1586                 struct sas_phy_linkrates *r)
1587 {
1588         u32 prog_phy_link_rate =
1589                 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
1590         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1591         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1592         int i;
1593         enum sas_linkrate min, max;
1594         u32 rate_mask = 0;
1595
1596         if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1597                 max = sas_phy->phy->maximum_linkrate;
1598                 min = r->minimum_linkrate;
1599         } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1600                 max = r->maximum_linkrate;
1601                 min = sas_phy->phy->minimum_linkrate;
1602         } else
1603                 return;
1604
1605         sas_phy->phy->maximum_linkrate = max;
1606         sas_phy->phy->minimum_linkrate = min;
1607
1608         max -= SAS_LINK_RATE_1_5_GBPS;
1609
1610         for (i = 0; i <= max; i++)
1611                 rate_mask |= 1 << (i * 2);
1612
1613         prog_phy_link_rate &= ~0xff;
1614         prog_phy_link_rate |= rate_mask;
1615
1616         disable_phy_v2_hw(hisi_hba, phy_no);
1617         msleep(100);
1618         hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1619                         prog_phy_link_rate);
1620         start_phy_v2_hw(hisi_hba, phy_no);
1621 }
1622
1623 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
1624 {
1625         int i, bitmap = 0;
1626         u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1627         u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1628
1629         for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
1630                 if (phy_state & 1 << i)
1631                         if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1632                                 bitmap |= 1 << i;
1633
1634         if (hisi_hba->n_phy == 9) {
1635                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1636
1637                 if (phy_state & 1 << 8)
1638                         if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1639                              PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1640                                 bitmap |= 1 << 9;
1641         }
1642
1643         return bitmap;
1644 }
1645
1646 /*
1647  * The callpath to this function and upto writing the write
1648  * queue pointer should be safe from interruption.
1649  */
1650 static int
1651 get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
1652 {
1653         struct device *dev = hisi_hba->dev;
1654         int queue = dq->id;
1655         u32 r, w;
1656
1657         w = dq->wr_point;
1658         r = hisi_sas_read32_relaxed(hisi_hba,
1659                                 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1660         if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1661                 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
1662                                 queue, r, w);
1663                 return -EAGAIN;
1664         }
1665
1666         return 0;
1667 }
1668
1669 static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
1670 {
1671         struct hisi_hba *hisi_hba = dq->hisi_hba;
1672         int dlvry_queue = dq->slot_prep->dlvry_queue;
1673         int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
1674
1675         dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
1676         hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
1677                          dq->wr_point);
1678 }
1679
1680 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1681                               struct hisi_sas_slot *slot,
1682                               struct hisi_sas_cmd_hdr *hdr,
1683                               struct scatterlist *scatter,
1684                               int n_elem)
1685 {
1686         struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1687         struct device *dev = hisi_hba->dev;
1688         struct scatterlist *sg;
1689         int i;
1690
1691         if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
1692                 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1693                         n_elem);
1694                 return -EINVAL;
1695         }
1696
1697         for_each_sg(scatter, sg, n_elem, i) {
1698                 struct hisi_sas_sge *entry = &sge_page->sge[i];
1699
1700                 entry->addr = cpu_to_le64(sg_dma_address(sg));
1701                 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1702                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1703                 entry->data_off = 0;
1704         }
1705
1706         hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1707
1708         hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1709
1710         return 0;
1711 }
1712
1713 static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1714                           struct hisi_sas_slot *slot)
1715 {
1716         struct sas_task *task = slot->task;
1717         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1718         struct domain_device *device = task->dev;
1719         struct device *dev = hisi_hba->dev;
1720         struct hisi_sas_port *port = slot->port;
1721         struct scatterlist *sg_req, *sg_resp;
1722         struct hisi_sas_device *sas_dev = device->lldd_dev;
1723         dma_addr_t req_dma_addr;
1724         unsigned int req_len, resp_len;
1725         int elem, rc;
1726
1727         /*
1728         * DMA-map SMP request, response buffers
1729         */
1730         /* req */
1731         sg_req = &task->smp_task.smp_req;
1732         elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
1733         if (!elem)
1734                 return -ENOMEM;
1735         req_len = sg_dma_len(sg_req);
1736         req_dma_addr = sg_dma_address(sg_req);
1737
1738         /* resp */
1739         sg_resp = &task->smp_task.smp_resp;
1740         elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
1741         if (!elem) {
1742                 rc = -ENOMEM;
1743                 goto err_out_req;
1744         }
1745         resp_len = sg_dma_len(sg_resp);
1746         if ((req_len & 0x3) || (resp_len & 0x3)) {
1747                 rc = -EINVAL;
1748                 goto err_out_resp;
1749         }
1750
1751         /* create header */
1752         /* dw0 */
1753         hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1754                                (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1755                                (2 << CMD_HDR_CMD_OFF)); /* smp */
1756
1757         /* map itct entry */
1758         hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1759                                (1 << CMD_HDR_FRAME_TYPE_OFF) |
1760                                (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1761
1762         /* dw2 */
1763         hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1764                                (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1765                                CMD_HDR_MRFL_OFF));
1766
1767         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1768
1769         hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1770         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1771
1772         return 0;
1773
1774 err_out_resp:
1775         dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1776                      DMA_FROM_DEVICE);
1777 err_out_req:
1778         dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1779                      DMA_TO_DEVICE);
1780         return rc;
1781 }
1782
1783 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1784                           struct hisi_sas_slot *slot, int is_tmf,
1785                           struct hisi_sas_tmf_task *tmf)
1786 {
1787         struct sas_task *task = slot->task;
1788         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1789         struct domain_device *device = task->dev;
1790         struct hisi_sas_device *sas_dev = device->lldd_dev;
1791         struct hisi_sas_port *port = slot->port;
1792         struct sas_ssp_task *ssp_task = &task->ssp_task;
1793         struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1794         int has_data = 0, rc, priority = is_tmf;
1795         u8 *buf_cmd;
1796         u32 dw1 = 0, dw2 = 0;
1797
1798         hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1799                                (2 << CMD_HDR_TLR_CTRL_OFF) |
1800                                (port->id << CMD_HDR_PORT_OFF) |
1801                                (priority << CMD_HDR_PRIORITY_OFF) |
1802                                (1 << CMD_HDR_CMD_OFF)); /* ssp */
1803
1804         dw1 = 1 << CMD_HDR_VDTL_OFF;
1805         if (is_tmf) {
1806                 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1807                 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1808         } else {
1809                 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1810                 switch (scsi_cmnd->sc_data_direction) {
1811                 case DMA_TO_DEVICE:
1812                         has_data = 1;
1813                         dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1814                         break;
1815                 case DMA_FROM_DEVICE:
1816                         has_data = 1;
1817                         dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1818                         break;
1819                 default:
1820                         dw1 &= ~CMD_HDR_DIR_MSK;
1821                 }
1822         }
1823
1824         /* map itct entry */
1825         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1826         hdr->dw1 = cpu_to_le32(dw1);
1827
1828         dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1829               + 3) / 4) << CMD_HDR_CFL_OFF) |
1830               ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1831               (2 << CMD_HDR_SG_MOD_OFF);
1832         hdr->dw2 = cpu_to_le32(dw2);
1833
1834         hdr->transfer_tags = cpu_to_le32(slot->idx);
1835
1836         if (has_data) {
1837                 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1838                                         slot->n_elem);
1839                 if (rc)
1840                         return rc;
1841         }
1842
1843         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1844         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1845         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1846
1847         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1848                 sizeof(struct ssp_frame_hdr);
1849
1850         memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1851         if (!is_tmf) {
1852                 buf_cmd[9] = task->ssp_task.task_attr |
1853                                 (task->ssp_task.task_prio << 3);
1854                 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1855                                 task->ssp_task.cmd->cmd_len);
1856         } else {
1857                 buf_cmd[10] = tmf->tmf;
1858                 switch (tmf->tmf) {
1859                 case TMF_ABORT_TASK:
1860                 case TMF_QUERY_TASK:
1861                         buf_cmd[12] =
1862                                 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1863                         buf_cmd[13] =
1864                                 tmf->tag_of_task_to_be_managed & 0xff;
1865                         break;
1866                 default:
1867                         break;
1868                 }
1869         }
1870
1871         return 0;
1872 }
1873
1874 #define TRANS_TX_ERR    0
1875 #define TRANS_RX_ERR    1
1876 #define DMA_TX_ERR              2
1877 #define SIPC_RX_ERR             3
1878 #define DMA_RX_ERR              4
1879
1880 #define DMA_TX_ERR_OFF  0
1881 #define DMA_TX_ERR_MSK  (0xffff << DMA_TX_ERR_OFF)
1882 #define SIPC_RX_ERR_OFF 16
1883 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1884
1885 static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
1886 {
1887         static const u8 trans_tx_err_code_prio[] = {
1888                 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
1889                 TRANS_TX_ERR_PHY_NOT_ENABLE,
1890                 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
1891                 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
1892                 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
1893                 RESERVED0,
1894                 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
1895                 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
1896                 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
1897                 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
1898                 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
1899                 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
1900                 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
1901                 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
1902                 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
1903                 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
1904                 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
1905                 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
1906                 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1907                 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
1908                 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
1909                 TRANS_TX_ERR_WITH_BREAK_REQUEST,
1910                 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
1911                 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
1912                 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
1913                 TRANS_TX_ERR_WITH_NAK_RECEVIED,
1914                 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
1915                 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
1916                 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
1917                 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
1918                 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
1919         };
1920         int index, i;
1921
1922         for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
1923                 index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
1924                 if (err_msk & (1 << index))
1925                         return trans_tx_err_code_prio[i];
1926         }
1927         return -1;
1928 }
1929
1930 static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
1931 {
1932         static const u8 trans_rx_err_code_prio[] = {
1933                 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
1934                 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
1935                 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
1936                 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
1937                 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
1938                 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
1939                 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
1940                 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
1941                 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
1942                 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1943                 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
1944                 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
1945                 TRANS_RX_ERR_WITH_BREAK_REQUEST,
1946                 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
1947                 RESERVED1,
1948                 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
1949                 TRANS_RX_ERR_WITH_DATA_LEN0,
1950                 TRANS_RX_ERR_WITH_BAD_HASH,
1951                 TRANS_RX_XRDY_WLEN_ZERO_ERR,
1952                 TRANS_RX_SSP_FRM_LEN_ERR,
1953                 RESERVED2,
1954                 RESERVED3,
1955                 RESERVED4,
1956                 RESERVED5,
1957                 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
1958                 TRANS_RX_SMP_FRM_LEN_ERR,
1959                 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
1960                 RESERVED6,
1961                 RESERVED7,
1962                 RESERVED8,
1963                 RESERVED9,
1964                 TRANS_RX_R_ERR,
1965         };
1966         int index, i;
1967
1968         for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
1969                 index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
1970                 if (err_msk & (1 << index))
1971                         return trans_rx_err_code_prio[i];
1972         }
1973         return -1;
1974 }
1975
1976 static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
1977 {
1978         static const u8 dma_tx_err_code_prio[] = {
1979                 DMA_TX_UNEXP_XFER_ERR,
1980                 DMA_TX_UNEXP_RETRANS_ERR,
1981                 DMA_TX_XFER_LEN_OVERFLOW,
1982                 DMA_TX_XFER_OFFSET_ERR,
1983                 DMA_TX_RAM_ECC_ERR,
1984                 DMA_TX_DIF_LEN_ALIGN_ERR,
1985                 DMA_TX_DIF_CRC_ERR,
1986                 DMA_TX_DIF_APP_ERR,
1987                 DMA_TX_DIF_RPP_ERR,
1988                 DMA_TX_DATA_SGL_OVERFLOW,
1989                 DMA_TX_DIF_SGL_OVERFLOW,
1990         };
1991         int index, i;
1992
1993         for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
1994                 index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
1995                 err_msk = err_msk & DMA_TX_ERR_MSK;
1996                 if (err_msk & (1 << index))
1997                         return dma_tx_err_code_prio[i];
1998         }
1999         return -1;
2000 }
2001
2002 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
2003 {
2004         static const u8 sipc_rx_err_code_prio[] = {
2005                 SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
2006                 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
2007                 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
2008                 SIPC_RX_WRSETUP_LEN_ODD_ERR,
2009                 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
2010                 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
2011                 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
2012                 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
2013                 SIPC_RX_SATA_UNEXP_FIS_ERR,
2014                 SIPC_RX_WRSETUP_ESTATUS_ERR,
2015                 SIPC_RX_DATA_UNDERFLOW_ERR,
2016         };
2017         int index, i;
2018
2019         for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
2020                 index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
2021                 err_msk = err_msk & SIPC_RX_ERR_MSK;
2022                 if (err_msk & (1 << (index + 0x10)))
2023                         return sipc_rx_err_code_prio[i];
2024         }
2025         return -1;
2026 }
2027
2028 static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
2029 {
2030         static const u8 dma_rx_err_code_prio[] = {
2031                 DMA_RX_UNKNOWN_FRM_ERR,
2032                 DMA_RX_DATA_LEN_OVERFLOW,
2033                 DMA_RX_DATA_LEN_UNDERFLOW,
2034                 DMA_RX_DATA_OFFSET_ERR,
2035                 RESERVED10,
2036                 DMA_RX_SATA_FRAME_TYPE_ERR,
2037                 DMA_RX_RESP_BUF_OVERFLOW,
2038                 DMA_RX_UNEXP_RETRANS_RESP_ERR,
2039                 DMA_RX_UNEXP_NORM_RESP_ERR,
2040                 DMA_RX_UNEXP_RDFRAME_ERR,
2041                 DMA_RX_PIO_DATA_LEN_ERR,
2042                 DMA_RX_RDSETUP_STATUS_ERR,
2043                 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
2044                 DMA_RX_RDSETUP_STATUS_BSY_ERR,
2045                 DMA_RX_RDSETUP_LEN_ODD_ERR,
2046                 DMA_RX_RDSETUP_LEN_ZERO_ERR,
2047                 DMA_RX_RDSETUP_LEN_OVER_ERR,
2048                 DMA_RX_RDSETUP_OFFSET_ERR,
2049                 DMA_RX_RDSETUP_ACTIVE_ERR,
2050                 DMA_RX_RDSETUP_ESTATUS_ERR,
2051                 DMA_RX_RAM_ECC_ERR,
2052                 DMA_RX_DIF_CRC_ERR,
2053                 DMA_RX_DIF_APP_ERR,
2054                 DMA_RX_DIF_RPP_ERR,
2055                 DMA_RX_DATA_SGL_OVERFLOW,
2056                 DMA_RX_DIF_SGL_OVERFLOW,
2057         };
2058         int index, i;
2059
2060         for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
2061                 index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
2062                 if (err_msk & (1 << index))
2063                         return dma_rx_err_code_prio[i];
2064         }
2065         return -1;
2066 }
2067
2068 /* by default, task resp is complete */
2069 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
2070                            struct sas_task *task,
2071                            struct hisi_sas_slot *slot,
2072                            int err_phase)
2073 {
2074         struct task_status_struct *ts = &task->task_status;
2075         struct hisi_sas_err_record_v2 *err_record =
2076                         hisi_sas_status_buf_addr_mem(slot);
2077         u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
2078         u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
2079         u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
2080         u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
2081         u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
2082         int error = -1;
2083
2084         if (err_phase == 1) {
2085                 /* error in TX phase, the priority of error is: DW2 > DW0 */
2086                 error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
2087                 if (error == -1)
2088                         error = parse_trans_tx_err_code_v2_hw(
2089                                         trans_tx_fail_type);
2090         } else if (err_phase == 2) {
2091                 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
2092                 error = parse_trans_rx_err_code_v2_hw(
2093                                         trans_rx_fail_type);
2094                 if (error == -1) {
2095                         error = parse_dma_rx_err_code_v2_hw(
2096                                         dma_rx_err_type);
2097                         if (error == -1)
2098                                 error = parse_sipc_rx_err_code_v2_hw(
2099                                                 sipc_rx_err_type);
2100                 }
2101         }
2102
2103         switch (task->task_proto) {
2104         case SAS_PROTOCOL_SSP:
2105         {
2106                 switch (error) {
2107                 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2108                 {
2109                         ts->stat = SAS_OPEN_REJECT;
2110                         ts->open_rej_reason = SAS_OREJ_NO_DEST;
2111                         break;
2112                 }
2113                 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2114                 {
2115                         ts->stat = SAS_OPEN_REJECT;
2116                         ts->open_rej_reason = SAS_OREJ_EPROTO;
2117                         break;
2118                 }
2119                 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2120                 {
2121                         ts->stat = SAS_OPEN_REJECT;
2122                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2123                         break;
2124                 }
2125                 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2126                 {
2127                         ts->stat = SAS_OPEN_REJECT;
2128                         ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2129                         break;
2130                 }
2131                 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2132                 {
2133                         ts->stat = SAS_OPEN_REJECT;
2134                         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2135                         break;
2136                 }
2137                 case DMA_RX_UNEXP_NORM_RESP_ERR:
2138                 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2139                 case DMA_RX_RESP_BUF_OVERFLOW:
2140                 {
2141                         ts->stat = SAS_OPEN_REJECT;
2142                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2143                         break;
2144                 }
2145                 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2146                 {
2147                         /* not sure */
2148                         ts->stat = SAS_DEV_NO_RESPONSE;
2149                         break;
2150                 }
2151                 case DMA_RX_DATA_LEN_OVERFLOW:
2152                 {
2153                         ts->stat = SAS_DATA_OVERRUN;
2154                         ts->residual = 0;
2155                         break;
2156                 }
2157                 case DMA_RX_DATA_LEN_UNDERFLOW:
2158                 {
2159                         ts->residual = trans_tx_fail_type;
2160                         ts->stat = SAS_DATA_UNDERRUN;
2161                         break;
2162                 }
2163                 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2164                 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2165                 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2166                 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2167                 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2168                 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2169                 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2170                 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2171                 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2172                 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2173                 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2174                 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2175                 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2176                 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2177                 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2178                 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2179                 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
2180                 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2181                 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2182                 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
2183                 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
2184                 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2185                 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2186                 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2187                 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2188                 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2189                 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2190                 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2191                 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2192                 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2193                 case TRANS_TX_ERR_FRAME_TXED:
2194                 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2195                 case TRANS_RX_ERR_WITH_DATA_LEN0:
2196                 case TRANS_RX_ERR_WITH_BAD_HASH:
2197                 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2198                 case TRANS_RX_SSP_FRM_LEN_ERR:
2199                 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2200                 case DMA_TX_DATA_SGL_OVERFLOW:
2201                 case DMA_TX_UNEXP_XFER_ERR:
2202                 case DMA_TX_UNEXP_RETRANS_ERR:
2203                 case DMA_TX_XFER_LEN_OVERFLOW:
2204                 case DMA_TX_XFER_OFFSET_ERR:
2205                 case SIPC_RX_DATA_UNDERFLOW_ERR:
2206                 case DMA_RX_DATA_SGL_OVERFLOW:
2207                 case DMA_RX_DATA_OFFSET_ERR:
2208                 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2209                 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2210                 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2211                 case DMA_RX_SATA_FRAME_TYPE_ERR:
2212                 case DMA_RX_UNKNOWN_FRM_ERR:
2213                 {
2214                         /* This will request a retry */
2215                         ts->stat = SAS_QUEUE_FULL;
2216                         slot->abort = 1;
2217                         break;
2218                 }
2219                 default:
2220                         break;
2221                 }
2222         }
2223                 break;
2224         case SAS_PROTOCOL_SMP:
2225                 ts->stat = SAM_STAT_CHECK_CONDITION;
2226                 break;
2227
2228         case SAS_PROTOCOL_SATA:
2229         case SAS_PROTOCOL_STP:
2230         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2231         {
2232                 switch (error) {
2233                 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2234                 {
2235                         ts->stat = SAS_OPEN_REJECT;
2236                         ts->open_rej_reason = SAS_OREJ_NO_DEST;
2237                         break;
2238                 }
2239                 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2240                 {
2241                         ts->resp = SAS_TASK_UNDELIVERED;
2242                         ts->stat = SAS_DEV_NO_RESPONSE;
2243                         break;
2244                 }
2245                 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2246                 {
2247                         ts->stat = SAS_OPEN_REJECT;
2248                         ts->open_rej_reason = SAS_OREJ_EPROTO;
2249                         break;
2250                 }
2251                 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2252                 {
2253                         ts->stat = SAS_OPEN_REJECT;
2254                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2255                         break;
2256                 }
2257                 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2258                 {
2259                         ts->stat = SAS_OPEN_REJECT;
2260                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2261                         break;
2262                 }
2263                 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2264                 {
2265                         ts->stat = SAS_OPEN_REJECT;
2266                         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2267                         break;
2268                 }
2269                 case DMA_RX_RESP_BUF_OVERFLOW:
2270                 case DMA_RX_UNEXP_NORM_RESP_ERR:
2271                 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2272                 {
2273                         ts->stat = SAS_OPEN_REJECT;
2274                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2275                         break;
2276                 }
2277                 case DMA_RX_DATA_LEN_OVERFLOW:
2278                 {
2279                         ts->stat = SAS_DATA_OVERRUN;
2280                         ts->residual = 0;
2281                         break;
2282                 }
2283                 case DMA_RX_DATA_LEN_UNDERFLOW:
2284                 {
2285                         ts->residual = trans_tx_fail_type;
2286                         ts->stat = SAS_DATA_UNDERRUN;
2287                         break;
2288                 }
2289                 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2290                 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2291                 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2292                 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2293                 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2294                 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2295                 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2296                 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2297                 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2298                 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2299                 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2300                 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2301                 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2302                 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2303                 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2304                 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2305                 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2306                 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2307                 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
2308                 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
2309                 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2310                 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2311                 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
2312                 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
2313                 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
2314                 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
2315                 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2316                 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2317                 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2318                 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2319                 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2320                 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2321                 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2322                 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2323                 case TRANS_RX_ERR_WITH_DATA_LEN0:
2324                 case TRANS_RX_ERR_WITH_BAD_HASH:
2325                 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2326                 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2327                 case DMA_TX_DATA_SGL_OVERFLOW:
2328                 case DMA_TX_UNEXP_XFER_ERR:
2329                 case DMA_TX_UNEXP_RETRANS_ERR:
2330                 case DMA_TX_XFER_LEN_OVERFLOW:
2331                 case DMA_TX_XFER_OFFSET_ERR:
2332                 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
2333                 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
2334                 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
2335                 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
2336                 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
2337                 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
2338                 case SIPC_RX_SATA_UNEXP_FIS_ERR:
2339                 case DMA_RX_DATA_SGL_OVERFLOW:
2340                 case DMA_RX_DATA_OFFSET_ERR:
2341                 case DMA_RX_SATA_FRAME_TYPE_ERR:
2342                 case DMA_RX_UNEXP_RDFRAME_ERR:
2343                 case DMA_RX_PIO_DATA_LEN_ERR:
2344                 case DMA_RX_RDSETUP_STATUS_ERR:
2345                 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
2346                 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
2347                 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2348                 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2349                 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2350                 case DMA_RX_RDSETUP_OFFSET_ERR:
2351                 case DMA_RX_RDSETUP_ACTIVE_ERR:
2352                 case DMA_RX_RDSETUP_ESTATUS_ERR:
2353                 case DMA_RX_UNKNOWN_FRM_ERR:
2354                 case TRANS_RX_SSP_FRM_LEN_ERR:
2355                 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
2356                 {
2357                         slot->abort = 1;
2358                         ts->stat = SAS_PHY_DOWN;
2359                         break;
2360                 }
2361                 default:
2362                 {
2363                         ts->stat = SAS_PROTO_RESPONSE;
2364                         break;
2365                 }
2366                 }
2367                 hisi_sas_sata_done(task, slot);
2368         }
2369                 break;
2370         default:
2371                 break;
2372         }
2373 }
2374
2375 static int
2376 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
2377 {
2378         struct sas_task *task = slot->task;
2379         struct hisi_sas_device *sas_dev;
2380         struct device *dev = hisi_hba->dev;
2381         struct task_status_struct *ts;
2382         struct domain_device *device;
2383         enum exec_status sts;
2384         struct hisi_sas_complete_v2_hdr *complete_queue =
2385                         hisi_hba->complete_hdr[slot->cmplt_queue];
2386         struct hisi_sas_complete_v2_hdr *complete_hdr =
2387                         &complete_queue[slot->cmplt_queue_slot];
2388         unsigned long flags;
2389         int aborted;
2390
2391         if (unlikely(!task || !task->lldd_task || !task->dev))
2392                 return -EINVAL;
2393
2394         ts = &task->task_status;
2395         device = task->dev;
2396         sas_dev = device->lldd_dev;
2397
2398         spin_lock_irqsave(&task->task_state_lock, flags);
2399         aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
2400         task->task_state_flags &=
2401                 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2402         spin_unlock_irqrestore(&task->task_state_lock, flags);
2403
2404         memset(ts, 0, sizeof(*ts));
2405         ts->resp = SAS_TASK_COMPLETE;
2406
2407         if (unlikely(aborted)) {
2408                 dev_dbg(dev, "slot_complete: task(%p) aborted\n", task);
2409                 ts->stat = SAS_ABORTED_TASK;
2410                 spin_lock_irqsave(&hisi_hba->lock, flags);
2411                 hisi_sas_slot_task_free(hisi_hba, task, slot);
2412                 spin_unlock_irqrestore(&hisi_hba->lock, flags);
2413                 return ts->stat;
2414         }
2415
2416         if (unlikely(!sas_dev)) {
2417                 dev_dbg(dev, "slot complete: port has no device\n");
2418                 ts->stat = SAS_PHY_DOWN;
2419                 goto out;
2420         }
2421
2422         /* Use SAS+TMF status codes */
2423         switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
2424                         >> CMPLT_HDR_ABORT_STAT_OFF) {
2425         case STAT_IO_ABORTED:
2426                 /* this io has been aborted by abort command */
2427                 ts->stat = SAS_ABORTED_TASK;
2428                 goto out;
2429         case STAT_IO_COMPLETE:
2430                 /* internal abort command complete */
2431                 ts->stat = TMF_RESP_FUNC_SUCC;
2432                 del_timer(&slot->internal_abort_timer);
2433                 goto out;
2434         case STAT_IO_NO_DEVICE:
2435                 ts->stat = TMF_RESP_FUNC_COMPLETE;
2436                 del_timer(&slot->internal_abort_timer);
2437                 goto out;
2438         case STAT_IO_NOT_VALID:
2439                 /* abort single io, controller don't find
2440                  * the io need to abort
2441                  */
2442                 ts->stat = TMF_RESP_FUNC_FAILED;
2443                 del_timer(&slot->internal_abort_timer);
2444                 goto out;
2445         default:
2446                 break;
2447         }
2448
2449         if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
2450                 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2451                 u32 err_phase = (complete_hdr->dw0 & CMPLT_HDR_ERR_PHASE_MSK)
2452                                 >> CMPLT_HDR_ERR_PHASE_OFF;
2453                 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2454
2455                 /* Analyse error happens on which phase TX or RX */
2456                 if (ERR_ON_TX_PHASE(err_phase))
2457                         slot_err_v2_hw(hisi_hba, task, slot, 1);
2458                 else if (ERR_ON_RX_PHASE(err_phase))
2459                         slot_err_v2_hw(hisi_hba, task, slot, 2);
2460
2461                 if (ts->stat != SAS_DATA_UNDERRUN)
2462                         dev_info(dev, "erroneous completion iptt=%d task=%p "
2463                                 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
2464                                 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
2465                                 slot->idx, task,
2466                                 complete_hdr->dw0, complete_hdr->dw1,
2467                                 complete_hdr->act, complete_hdr->dw3,
2468                                 error_info[0], error_info[1],
2469                                 error_info[2], error_info[3]);
2470
2471                 if (unlikely(slot->abort))
2472                         return ts->stat;
2473                 goto out;
2474         }
2475
2476         switch (task->task_proto) {
2477         case SAS_PROTOCOL_SSP:
2478         {
2479                 struct hisi_sas_status_buffer *status_buffer =
2480                                 hisi_sas_status_buf_addr_mem(slot);
2481                 struct ssp_response_iu *iu = (struct ssp_response_iu *)
2482                                 &status_buffer->iu[0];
2483
2484                 sas_ssp_task_response(dev, task, iu);
2485                 break;
2486         }
2487         case SAS_PROTOCOL_SMP:
2488         {
2489                 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2490                 void *to;
2491
2492                 ts->stat = SAM_STAT_GOOD;
2493                 to = kmap_atomic(sg_page(sg_resp));
2494
2495                 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
2496                              DMA_FROM_DEVICE);
2497                 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2498                              DMA_TO_DEVICE);
2499                 memcpy(to + sg_resp->offset,
2500                        hisi_sas_status_buf_addr_mem(slot) +
2501                        sizeof(struct hisi_sas_err_record),
2502                        sg_dma_len(sg_resp));
2503                 kunmap_atomic(to);
2504                 break;
2505         }
2506         case SAS_PROTOCOL_SATA:
2507         case SAS_PROTOCOL_STP:
2508         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2509         {
2510                 ts->stat = SAM_STAT_GOOD;
2511                 hisi_sas_sata_done(task, slot);
2512                 break;
2513         }
2514         default:
2515                 ts->stat = SAM_STAT_CHECK_CONDITION;
2516                 break;
2517         }
2518
2519         if (!slot->port->port_attached) {
2520                 dev_warn(dev, "slot complete: port %d has removed\n",
2521                         slot->port->sas_port.id);
2522                 ts->stat = SAS_PHY_DOWN;
2523         }
2524
2525 out:
2526         spin_lock_irqsave(&task->task_state_lock, flags);
2527         task->task_state_flags |= SAS_TASK_STATE_DONE;
2528         spin_unlock_irqrestore(&task->task_state_lock, flags);
2529         spin_lock_irqsave(&hisi_hba->lock, flags);
2530         hisi_sas_slot_task_free(hisi_hba, task, slot);
2531         spin_unlock_irqrestore(&hisi_hba->lock, flags);
2532         sts = ts->stat;
2533
2534         if (task->task_done)
2535                 task->task_done(task);
2536
2537         return sts;
2538 }
2539
2540 static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
2541                           struct hisi_sas_slot *slot)
2542 {
2543         struct sas_task *task = slot->task;
2544         struct domain_device *device = task->dev;
2545         struct domain_device *parent_dev = device->parent;
2546         struct hisi_sas_device *sas_dev = device->lldd_dev;
2547         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2548         struct asd_sas_port *sas_port = device->port;
2549         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
2550         u8 *buf_cmd;
2551         int has_data = 0, rc = 0, hdr_tag = 0;
2552         u32 dw1 = 0, dw2 = 0;
2553
2554         /* create header */
2555         /* dw0 */
2556         hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
2557         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
2558                 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
2559         else
2560                 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
2561
2562         /* dw1 */
2563         switch (task->data_dir) {
2564         case DMA_TO_DEVICE:
2565                 has_data = 1;
2566                 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
2567                 break;
2568         case DMA_FROM_DEVICE:
2569                 has_data = 1;
2570                 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
2571                 break;
2572         default:
2573                 dw1 &= ~CMD_HDR_DIR_MSK;
2574         }
2575
2576         if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
2577                         (task->ata_task.fis.control & ATA_SRST))
2578                 dw1 |= 1 << CMD_HDR_RESET_OFF;
2579
2580         dw1 |= (hisi_sas_get_ata_protocol(
2581                 &task->ata_task.fis, task->data_dir))
2582                 << CMD_HDR_FRAME_TYPE_OFF;
2583         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
2584         hdr->dw1 = cpu_to_le32(dw1);
2585
2586         /* dw2 */
2587         if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
2588                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
2589                 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
2590         }
2591
2592         dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
2593                         2 << CMD_HDR_SG_MOD_OFF;
2594         hdr->dw2 = cpu_to_le32(dw2);
2595
2596         /* dw3 */
2597         hdr->transfer_tags = cpu_to_le32(slot->idx);
2598
2599         if (has_data) {
2600                 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
2601                                         slot->n_elem);
2602                 if (rc)
2603                         return rc;
2604         }
2605
2606         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
2607         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
2608         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
2609
2610         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
2611
2612         if (likely(!task->ata_task.device_control_reg_update))
2613                 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
2614         /* fill in command FIS */
2615         memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
2616
2617         return 0;
2618 }
2619
2620 static void hisi_sas_internal_abort_quirk_timeout(struct timer_list *t)
2621 {
2622         struct hisi_sas_slot *slot = from_timer(slot, t, internal_abort_timer);
2623         struct hisi_sas_port *port = slot->port;
2624         struct asd_sas_port *asd_sas_port;
2625         struct asd_sas_phy *sas_phy;
2626
2627         if (!port)
2628                 return;
2629
2630         asd_sas_port = &port->sas_port;
2631
2632         /* Kick the hardware - send break command */
2633         list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
2634                 struct hisi_sas_phy *phy = sas_phy->lldd_phy;
2635                 struct hisi_hba *hisi_hba = phy->hisi_hba;
2636                 int phy_no = sas_phy->id;
2637                 u32 link_dfx2;
2638
2639                 link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
2640                 if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
2641                     (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
2642                         u32 txid_auto;
2643
2644                         txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
2645                                                         TXID_AUTO);
2646                         txid_auto |= TXID_AUTO_CTB_MSK;
2647                         hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2648                                              txid_auto);
2649                         return;
2650                 }
2651         }
2652 }
2653
2654 static int prep_abort_v2_hw(struct hisi_hba *hisi_hba,
2655                 struct hisi_sas_slot *slot,
2656                 int device_id, int abort_flag, int tag_to_abort)
2657 {
2658         struct sas_task *task = slot->task;
2659         struct domain_device *dev = task->dev;
2660         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2661         struct hisi_sas_port *port = slot->port;
2662         struct timer_list *timer = &slot->internal_abort_timer;
2663
2664         /* setup the quirk timer */
2665         timer_setup(timer, hisi_sas_internal_abort_quirk_timeout, 0);
2666         /* Set the timeout to 10ms less than internal abort timeout */
2667         mod_timer(timer, jiffies + msecs_to_jiffies(100));
2668
2669         /* dw0 */
2670         hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
2671                                (port->id << CMD_HDR_PORT_OFF) |
2672                                (dev_is_sata(dev) <<
2673                                 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
2674                                (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
2675
2676         /* dw1 */
2677         hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
2678
2679         /* dw7 */
2680         hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
2681         hdr->transfer_tags = cpu_to_le32(slot->idx);
2682
2683         return 0;
2684 }
2685
2686 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2687 {
2688         int i, res = IRQ_HANDLED;
2689         u32 port_id, link_rate;
2690         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2691         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2692         struct device *dev = hisi_hba->dev;
2693         u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
2694         struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
2695
2696         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
2697
2698         if (is_sata_phy_v2_hw(hisi_hba, phy_no))
2699                 goto end;
2700
2701         if (phy_no == 8) {
2702                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2703
2704                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2705                           PORT_STATE_PHY8_PORT_NUM_OFF;
2706                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2707                             PORT_STATE_PHY8_CONN_RATE_OFF;
2708         } else {
2709                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2710                 port_id = (port_id >> (4 * phy_no)) & 0xf;
2711                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2712                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2713         }
2714
2715         if (port_id == 0xf) {
2716                 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
2717                 res = IRQ_NONE;
2718                 goto end;
2719         }
2720
2721         for (i = 0; i < 6; i++) {
2722                 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
2723                                                RX_IDAF_DWORD0 + (i * 4));
2724                 frame_rcvd[i] = __swab32(idaf);
2725         }
2726
2727         sas_phy->linkrate = link_rate;
2728         sas_phy->oob_mode = SAS_OOB_MODE;
2729         memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
2730         dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2731         phy->port_id = port_id;
2732         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2733         phy->phy_type |= PORT_TYPE_SAS;
2734         phy->phy_attached = 1;
2735         phy->identify.device_type = id->dev_type;
2736         phy->frame_rcvd_size =  sizeof(struct sas_identify_frame);
2737         if (phy->identify.device_type == SAS_END_DEVICE)
2738                 phy->identify.target_port_protocols =
2739                         SAS_PROTOCOL_SSP;
2740         else if (phy->identify.device_type != SAS_PHY_UNUSED) {
2741                 phy->identify.target_port_protocols =
2742                         SAS_PROTOCOL_SMP;
2743                 if (!timer_pending(&hisi_hba->timer))
2744                         set_link_timer_quirk(hisi_hba);
2745         }
2746         hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
2747
2748 end:
2749         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2750                              CHL_INT0_SL_PHY_ENABLE_MSK);
2751         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
2752
2753         return res;
2754 }
2755
2756 static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
2757 {
2758         u32 port_state;
2759
2760         port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2761         if (port_state & 0x1ff)
2762                 return true;
2763
2764         return false;
2765 }
2766
2767 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2768 {
2769         u32 phy_state, sl_ctrl, txid_auto;
2770         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2771         struct hisi_sas_port *port = phy->port;
2772         struct device *dev = hisi_hba->dev;
2773
2774         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
2775
2776         phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2777         dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
2778         hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
2779
2780         sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
2781         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
2782                              sl_ctrl & ~SL_CONTROL_CTA_MSK);
2783         if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
2784                 if (!check_any_wideports_v2_hw(hisi_hba) &&
2785                                 timer_pending(&hisi_hba->timer))
2786                         del_timer(&hisi_hba->timer);
2787
2788         txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
2789         hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2790                              txid_auto | TXID_AUTO_CT3_MSK);
2791
2792         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
2793         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
2794
2795         return IRQ_HANDLED;
2796 }
2797
2798 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
2799 {
2800         struct hisi_hba *hisi_hba = p;
2801         u32 irq_msk;
2802         int phy_no = 0;
2803         irqreturn_t res = IRQ_NONE;
2804
2805         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
2806                    >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
2807         while (irq_msk) {
2808                 if (irq_msk  & 1) {
2809                         u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
2810                                             CHL_INT0);
2811
2812                         switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
2813                                         CHL_INT0_SL_PHY_ENABLE_MSK)) {
2814
2815                         case CHL_INT0_SL_PHY_ENABLE_MSK:
2816                                 /* phy up */
2817                                 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2818                                     IRQ_HANDLED)
2819                                         res = IRQ_HANDLED;
2820                                 break;
2821
2822                         case CHL_INT0_NOT_RDY_MSK:
2823                                 /* phy down */
2824                                 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2825                                     IRQ_HANDLED)
2826                                         res = IRQ_HANDLED;
2827                                 break;
2828
2829                         case (CHL_INT0_NOT_RDY_MSK |
2830                                         CHL_INT0_SL_PHY_ENABLE_MSK):
2831                                 reg_value = hisi_sas_read32(hisi_hba,
2832                                                 PHY_STATE);
2833                                 if (reg_value & BIT(phy_no)) {
2834                                         /* phy up */
2835                                         if (phy_up_v2_hw(phy_no, hisi_hba) ==
2836                                             IRQ_HANDLED)
2837                                                 res = IRQ_HANDLED;
2838                                 } else {
2839                                         /* phy down */
2840                                         if (phy_down_v2_hw(phy_no, hisi_hba) ==
2841                                             IRQ_HANDLED)
2842                                                 res = IRQ_HANDLED;
2843                                 }
2844                                 break;
2845
2846                         default:
2847                                 break;
2848                         }
2849
2850                 }
2851                 irq_msk >>= 1;
2852                 phy_no++;
2853         }
2854
2855         return res;
2856 }
2857
2858 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2859 {
2860         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2861         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2862         struct sas_ha_struct *sas_ha = &hisi_hba->sha;
2863         u32 bcast_status;
2864
2865         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
2866         bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
2867         if (bcast_status & RX_BCAST_CHG_MSK)
2868                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2869         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2870                              CHL_INT0_SL_RX_BCST_ACK_MSK);
2871         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
2872 }
2873
2874 static const struct hisi_sas_hw_error port_ecc_axi_error[] = {
2875         {
2876                 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_ERR_OFF),
2877                 .msg = "dmac_tx_ecc_bad_err",
2878         },
2879         {
2880                 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_ERR_OFF),
2881                 .msg = "dmac_rx_ecc_bad_err",
2882         },
2883         {
2884                 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
2885                 .msg = "dma_tx_axi_wr_err",
2886         },
2887         {
2888                 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
2889                 .msg = "dma_tx_axi_rd_err",
2890         },
2891         {
2892                 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
2893                 .msg = "dma_rx_axi_wr_err",
2894         },
2895         {
2896                 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
2897                 .msg = "dma_rx_axi_rd_err",
2898         },
2899 };
2900
2901 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
2902 {
2903         struct hisi_hba *hisi_hba = p;
2904         struct device *dev = hisi_hba->dev;
2905         u32 ent_msk, ent_tmp, irq_msk;
2906         int phy_no = 0;
2907
2908         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2909         ent_tmp = ent_msk;
2910         ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
2911         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
2912
2913         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
2914                         HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
2915
2916         while (irq_msk) {
2917                 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2918                                                      CHL_INT0);
2919                 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2920                                                      CHL_INT1);
2921                 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2922                                                      CHL_INT2);
2923
2924                 if ((irq_msk & (1 << phy_no)) && irq_value1) {
2925                         int i;
2926
2927                         for (i = 0; i < ARRAY_SIZE(port_ecc_axi_error); i++) {
2928                                 const struct hisi_sas_hw_error *error =
2929                                                 &port_ecc_axi_error[i];
2930
2931                                 if (!(irq_value1 & error->irq_msk))
2932                                         continue;
2933
2934                                 dev_warn(dev, "%s error (phy%d 0x%x) found!\n",
2935                                         error->msg, phy_no, irq_value1);
2936                                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2937                         }
2938
2939                         hisi_sas_phy_write32(hisi_hba, phy_no,
2940                                              CHL_INT1, irq_value1);
2941                 }
2942
2943                 if ((irq_msk & (1 << phy_no)) && irq_value2) {
2944                         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2945
2946                         if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
2947                                 dev_warn(dev, "phy%d identify timeout\n",
2948                                                 phy_no);
2949                                 hisi_sas_notify_phy_event(phy,
2950                                                 HISI_PHYE_LINK_RESET);
2951                         }
2952
2953                         hisi_sas_phy_write32(hisi_hba, phy_no,
2954                                                  CHL_INT2, irq_value2);
2955                 }
2956
2957                 if ((irq_msk & (1 << phy_no)) && irq_value0) {
2958                         if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2959                                 phy_bcast_v2_hw(phy_no, hisi_hba);
2960
2961                         hisi_sas_phy_write32(hisi_hba, phy_no,
2962                                         CHL_INT0, irq_value0
2963                                         & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2964                                         & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2965                                         & (~CHL_INT0_NOT_RDY_MSK));
2966                 }
2967                 irq_msk &= ~(1 << phy_no);
2968                 phy_no++;
2969         }
2970
2971         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2972
2973         return IRQ_HANDLED;
2974 }
2975
2976 static void
2977 one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
2978 {
2979         struct device *dev = hisi_hba->dev;
2980         const struct hisi_sas_hw_error *ecc_error;
2981         u32 val;
2982         int i;
2983
2984         for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) {
2985                 ecc_error = &one_bit_ecc_errors[i];
2986                 if (irq_value & ecc_error->irq_msk) {
2987                         val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2988                         val &= ecc_error->msk;
2989                         val >>= ecc_error->shift;
2990                         dev_warn(dev, ecc_error->msg, val);
2991                 }
2992         }
2993 }
2994
2995 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
2996                 u32 irq_value)
2997 {
2998         struct device *dev = hisi_hba->dev;
2999         const struct hisi_sas_hw_error *ecc_error;
3000         u32 val;
3001         int i;
3002
3003         for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
3004                 ecc_error = &multi_bit_ecc_errors[i];
3005                 if (irq_value & ecc_error->irq_msk) {
3006                         val = hisi_sas_read32(hisi_hba, ecc_error->reg);
3007                         val &= ecc_error->msk;
3008                         val >>= ecc_error->shift;
3009                         dev_err(dev, ecc_error->msg, irq_value, val);
3010                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3011                 }
3012         }
3013
3014         return;
3015 }
3016
3017 static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
3018 {
3019         struct hisi_hba *hisi_hba = p;
3020         u32 irq_value, irq_msk;
3021
3022         irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
3023         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
3024
3025         irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
3026         if (irq_value) {
3027                 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
3028                 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
3029         }
3030
3031         hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
3032         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
3033
3034         return IRQ_HANDLED;
3035 }
3036
3037 static const struct hisi_sas_hw_error axi_error[] = {
3038         { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
3039         { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
3040         { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
3041         { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
3042         { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
3043         { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
3044         { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
3045         { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
3046         {},
3047 };
3048
3049 static const struct hisi_sas_hw_error fifo_error[] = {
3050         { .msk = BIT(8),  .msg = "CQE_WINFO_FIFO" },
3051         { .msk = BIT(9),  .msg = "CQE_MSG_FIFIO" },
3052         { .msk = BIT(10), .msg = "GETDQE_FIFO" },
3053         { .msk = BIT(11), .msg = "CMDP_FIFO" },
3054         { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
3055         {},
3056 };
3057
3058 static const struct hisi_sas_hw_error fatal_axi_errors[] = {
3059         {
3060                 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
3061                 .msg = "write pointer and depth",
3062         },
3063         {
3064                 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
3065                 .msg = "iptt no match slot",
3066         },
3067         {
3068                 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
3069                 .msg = "read pointer and depth",
3070         },
3071         {
3072                 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
3073                 .reg = HGC_AXI_FIFO_ERR_INFO,
3074                 .sub = axi_error,
3075         },
3076         {
3077                 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
3078                 .reg = HGC_AXI_FIFO_ERR_INFO,
3079                 .sub = fifo_error,
3080         },
3081         {
3082                 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
3083                 .msg = "LM add/fetch list",
3084         },
3085         {
3086                 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
3087                 .msg = "SAS_HGC_ABT fetch LM list",
3088         },
3089 };
3090
3091 static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
3092 {
3093         struct hisi_hba *hisi_hba = p;
3094         u32 irq_value, irq_msk, err_value;
3095         struct device *dev = hisi_hba->dev;
3096         const struct hisi_sas_hw_error *axi_error;
3097         int i;
3098
3099         irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
3100         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
3101
3102         irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
3103
3104         for (i = 0; i < ARRAY_SIZE(fatal_axi_errors); i++) {
3105                 axi_error = &fatal_axi_errors[i];
3106                 if (!(irq_value & axi_error->irq_msk))
3107                         continue;
3108
3109                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3110                                  1 << axi_error->shift);
3111                 if (axi_error->sub) {
3112                         const struct hisi_sas_hw_error *sub = axi_error->sub;
3113
3114                         err_value = hisi_sas_read32(hisi_hba, axi_error->reg);
3115                         for (; sub->msk || sub->msg; sub++) {
3116                                 if (!(err_value & sub->msk))
3117                                         continue;
3118                                 dev_err(dev, "%s (0x%x) found!\n",
3119                                          sub->msg, irq_value);
3120                                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3121                         }
3122                 } else {
3123                         dev_err(dev, "%s (0x%x) found!\n",
3124                                  axi_error->msg, irq_value);
3125                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3126                 }
3127         }
3128
3129         if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
3130                 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
3131                 u32 dev_id = reg_val & ITCT_DEV_MSK;
3132                 struct hisi_sas_device *sas_dev = &hisi_hba->devices[dev_id];
3133
3134                 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
3135                 dev_dbg(dev, "clear ITCT ok\n");
3136                 complete(sas_dev->completion);
3137         }
3138
3139         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value);
3140         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
3141
3142         return IRQ_HANDLED;
3143 }
3144
3145 static void cq_tasklet_v2_hw(unsigned long val)
3146 {
3147         struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
3148         struct hisi_hba *hisi_hba = cq->hisi_hba;
3149         struct hisi_sas_slot *slot;
3150         struct hisi_sas_itct *itct;
3151         struct hisi_sas_complete_v2_hdr *complete_queue;
3152         u32 rd_point = cq->rd_point, wr_point, dev_id;
3153         int queue = cq->id;
3154         struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
3155
3156         if (unlikely(hisi_hba->reject_stp_links_msk))
3157                 phys_try_accept_stp_links_v2_hw(hisi_hba);
3158
3159         complete_queue = hisi_hba->complete_hdr[queue];
3160
3161         spin_lock(&dq->lock);
3162         wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
3163                                    (0x14 * queue));
3164
3165         while (rd_point != wr_point) {
3166                 struct hisi_sas_complete_v2_hdr *complete_hdr;
3167                 int iptt;
3168
3169                 complete_hdr = &complete_queue[rd_point];
3170
3171                 /* Check for NCQ completion */
3172                 if (complete_hdr->act) {
3173                         u32 act_tmp = complete_hdr->act;
3174                         int ncq_tag_count = ffs(act_tmp);
3175
3176                         dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
3177                                  CMPLT_HDR_DEV_ID_OFF;
3178                         itct = &hisi_hba->itct[dev_id];
3179
3180                         /* The NCQ tags are held in the itct header */
3181                         while (ncq_tag_count) {
3182                                 __le64 *ncq_tag = &itct->qw4_15[0];
3183
3184                                 ncq_tag_count -= 1;
3185                                 iptt = (ncq_tag[ncq_tag_count / 5]
3186                                         >> (ncq_tag_count % 5) * 12) & 0xfff;
3187
3188                                 slot = &hisi_hba->slot_info[iptt];
3189                                 slot->cmplt_queue_slot = rd_point;
3190                                 slot->cmplt_queue = queue;
3191                                 slot_complete_v2_hw(hisi_hba, slot);
3192
3193                                 act_tmp &= ~(1 << ncq_tag_count);
3194                                 ncq_tag_count = ffs(act_tmp);
3195                         }
3196                 } else {
3197                         iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
3198                         slot = &hisi_hba->slot_info[iptt];
3199                         slot->cmplt_queue_slot = rd_point;
3200                         slot->cmplt_queue = queue;
3201                         slot_complete_v2_hw(hisi_hba, slot);
3202                 }
3203
3204                 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
3205                         rd_point = 0;
3206         }
3207
3208         /* update rd_point */
3209         cq->rd_point = rd_point;
3210         hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
3211         spin_unlock(&dq->lock);
3212 }
3213
3214 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
3215 {
3216         struct hisi_sas_cq *cq = p;
3217         struct hisi_hba *hisi_hba = cq->hisi_hba;
3218         int queue = cq->id;
3219
3220         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
3221
3222         tasklet_schedule(&cq->tasklet);
3223
3224         return IRQ_HANDLED;
3225 }
3226
3227 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
3228 {
3229         struct hisi_sas_phy *phy = p;
3230         struct hisi_hba *hisi_hba = phy->hisi_hba;
3231         struct asd_sas_phy *sas_phy = &phy->sas_phy;
3232         struct device *dev = hisi_hba->dev;
3233         struct  hisi_sas_initial_fis *initial_fis;
3234         struct dev_to_host_fis *fis;
3235         u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
3236         irqreturn_t res = IRQ_HANDLED;
3237         u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
3238         int phy_no, offset;
3239
3240         phy_no = sas_phy->id;
3241         initial_fis = &hisi_hba->initial_fis[phy_no];
3242         fis = &initial_fis->fis;
3243
3244         offset = 4 * (phy_no / 4);
3245         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
3246         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
3247                          ent_msk | 1 << ((phy_no % 4) * 8));
3248
3249         ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
3250         ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
3251                              (phy_no % 4)));
3252         ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
3253         if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
3254                 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
3255                 res = IRQ_NONE;
3256                 goto end;
3257         }
3258
3259         /* check ERR bit of Status Register */
3260         if (fis->status & ATA_ERR) {
3261                 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
3262                                 fis->status);
3263                 disable_phy_v2_hw(hisi_hba, phy_no);
3264                 enable_phy_v2_hw(hisi_hba, phy_no);
3265                 res = IRQ_NONE;
3266                 goto end;
3267         }
3268
3269         if (unlikely(phy_no == 8)) {
3270                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
3271
3272                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
3273                           PORT_STATE_PHY8_PORT_NUM_OFF;
3274                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
3275                             PORT_STATE_PHY8_CONN_RATE_OFF;
3276         } else {
3277                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
3278                 port_id = (port_id >> (4 * phy_no)) & 0xf;
3279                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
3280                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
3281         }
3282
3283         if (port_id == 0xf) {
3284                 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
3285                 res = IRQ_NONE;
3286                 goto end;
3287         }
3288
3289         sas_phy->linkrate = link_rate;
3290         hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
3291                                                 HARD_PHY_LINKRATE);
3292         phy->maximum_linkrate = hard_phy_linkrate & 0xf;
3293         phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
3294
3295         sas_phy->oob_mode = SATA_OOB_MODE;
3296         /* Make up some unique SAS address */
3297         attached_sas_addr[0] = 0x50;
3298         attached_sas_addr[7] = phy_no;
3299         memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
3300         memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
3301         dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
3302         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
3303         phy->port_id = port_id;
3304         phy->phy_type |= PORT_TYPE_SATA;
3305         phy->phy_attached = 1;
3306         phy->identify.device_type = SAS_SATA_DEV;
3307         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3308         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3309         hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
3310
3311 end:
3312         hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
3313         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
3314
3315         return res;
3316 }
3317
3318 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
3319         int_phy_updown_v2_hw,
3320         int_chnl_int_v2_hw,
3321 };
3322
3323 static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
3324         fatal_ecc_int_v2_hw,
3325         fatal_axi_int_v2_hw
3326 };
3327
3328 /**
3329  * There is a limitation in the hip06 chipset that we need
3330  * to map in all mbigen interrupts, even if they are not used.
3331  */
3332 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
3333 {
3334         struct platform_device *pdev = hisi_hba->platform_dev;
3335         struct device *dev = &pdev->dev;
3336         int irq, rc, irq_map[128];
3337         int i, phy_no, fatal_no, queue_no, k;
3338
3339         for (i = 0; i < 128; i++)
3340                 irq_map[i] = platform_get_irq(pdev, i);
3341
3342         for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
3343                 irq = irq_map[i + 1]; /* Phy up/down is irq1 */
3344                 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
3345                                       DRV_NAME " phy", hisi_hba);
3346                 if (rc) {
3347                         dev_err(dev, "irq init: could not request "
3348                                 "phy interrupt %d, rc=%d\n",
3349                                 irq, rc);
3350                         rc = -ENOENT;
3351                         goto free_phy_int_irqs;
3352                 }
3353         }
3354
3355         for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
3356                 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
3357
3358                 irq = irq_map[phy_no + 72];
3359                 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
3360                                       DRV_NAME " sata", phy);
3361                 if (rc) {
3362                         dev_err(dev, "irq init: could not request "
3363                                 "sata interrupt %d, rc=%d\n",
3364                                 irq, rc);
3365                         rc = -ENOENT;
3366                         goto free_sata_int_irqs;
3367                 }
3368         }
3369
3370         for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
3371                 irq = irq_map[fatal_no + 81];
3372                 rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
3373                                       DRV_NAME " fatal", hisi_hba);
3374                 if (rc) {
3375                         dev_err(dev,
3376                                 "irq init: could not request fatal interrupt %d, rc=%d\n",
3377                                 irq, rc);
3378                         rc = -ENOENT;
3379                         goto free_fatal_int_irqs;
3380                 }
3381         }
3382
3383         for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
3384                 struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
3385                 struct tasklet_struct *t = &cq->tasklet;
3386
3387                 irq = irq_map[queue_no + 96];
3388                 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
3389                                       DRV_NAME " cq", cq);
3390                 if (rc) {
3391                         dev_err(dev,
3392                                 "irq init: could not request cq interrupt %d, rc=%d\n",
3393                                 irq, rc);
3394                         rc = -ENOENT;
3395                         goto free_cq_int_irqs;
3396                 }
3397                 tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq);
3398         }
3399
3400         return 0;
3401
3402 free_cq_int_irqs:
3403         for (k = 0; k < queue_no; k++) {
3404                 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
3405
3406                 free_irq(irq_map[k + 96], cq);
3407                 tasklet_kill(&cq->tasklet);
3408         }
3409 free_fatal_int_irqs:
3410         for (k = 0; k < fatal_no; k++)
3411                 free_irq(irq_map[k + 81], hisi_hba);
3412 free_sata_int_irqs:
3413         for (k = 0; k < phy_no; k++) {
3414                 struct hisi_sas_phy *phy = &hisi_hba->phy[k];
3415
3416                 free_irq(irq_map[k + 72], phy);
3417         }
3418 free_phy_int_irqs:
3419         for (k = 0; k < i; k++)
3420                 free_irq(irq_map[k + 1], hisi_hba);
3421         return rc;
3422 }
3423
3424 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
3425 {
3426         int rc;
3427
3428         memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap));
3429
3430         rc = hw_init_v2_hw(hisi_hba);
3431         if (rc)
3432                 return rc;
3433
3434         rc = interrupt_init_v2_hw(hisi_hba);
3435         if (rc)
3436                 return rc;
3437
3438         return 0;
3439 }
3440
3441 static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
3442 {
3443         struct platform_device *pdev = hisi_hba->platform_dev;
3444         int i;
3445
3446         for (i = 0; i < hisi_hba->queue_count; i++)
3447                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
3448
3449         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
3450         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
3451         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
3452         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
3453
3454         for (i = 0; i < hisi_hba->n_phy; i++) {
3455                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
3456                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
3457         }
3458
3459         for (i = 0; i < 128; i++)
3460                 synchronize_irq(platform_get_irq(pdev, i));
3461 }
3462
3463
3464 static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba)
3465 {
3466         return hisi_sas_read32(hisi_hba, PHY_STATE);
3467 }
3468
3469 static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
3470 {
3471         struct device *dev = hisi_hba->dev;
3472         int rc, cnt;
3473
3474         interrupt_disable_v2_hw(hisi_hba);
3475         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
3476         hisi_sas_kill_tasklets(hisi_hba);
3477
3478         hisi_sas_stop_phys(hisi_hba);
3479
3480         mdelay(10);
3481
3482         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
3483
3484         /* wait until bus idle */
3485         cnt = 0;
3486         while (1) {
3487                 u32 status = hisi_sas_read32_relaxed(hisi_hba,
3488                                 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
3489
3490                 if (status == 0x3)
3491                         break;
3492
3493                 udelay(10);
3494                 if (cnt++ > 10) {
3495                         dev_err(dev, "wait axi bus state to idle timeout!\n");
3496                         return -1;
3497                 }
3498         }
3499
3500         hisi_sas_init_mem(hisi_hba);
3501
3502         rc = hw_init_v2_hw(hisi_hba);
3503         if (rc)
3504                 return rc;
3505
3506         phys_reject_stp_links_v2_hw(hisi_hba);
3507
3508         return 0;
3509 }
3510
3511 static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type,
3512                         u8 reg_index, u8 reg_count, u8 *write_data)
3513 {
3514         struct device *dev = hisi_hba->dev;
3515         int phy_no, count;
3516
3517         if (!hisi_hba->sgpio_regs)
3518                 return -EOPNOTSUPP;
3519
3520         switch (reg_type) {
3521         case SAS_GPIO_REG_TX:
3522                 count = reg_count * 4;
3523                 count = min(count, hisi_hba->n_phy);
3524
3525                 for (phy_no = 0; phy_no < count; phy_no++) {
3526                         /*
3527                          * GPIO_TX[n] register has the highest numbered drive
3528                          * of the four in the first byte and the lowest
3529                          * numbered drive in the fourth byte.
3530                          * See SFF-8485 Rev. 0.7 Table 24.
3531                          */
3532                         void __iomem  *reg_addr = hisi_hba->sgpio_regs +
3533                                         reg_index * 4 + phy_no;
3534                         int data_idx = phy_no + 3 - (phy_no % 4) * 2;
3535
3536                         writeb(write_data[data_idx], reg_addr);
3537                 }
3538
3539                 break;
3540         default:
3541                 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
3542                                 reg_type);
3543                 return -EINVAL;
3544         }
3545
3546         return 0;
3547 }
3548
3549 static const struct hisi_sas_hw hisi_sas_v2_hw = {
3550         .hw_init = hisi_sas_v2_init,
3551         .setup_itct = setup_itct_v2_hw,
3552         .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
3553         .alloc_dev = alloc_dev_quirk_v2_hw,
3554         .sl_notify = sl_notify_v2_hw,
3555         .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
3556         .clear_itct = clear_itct_v2_hw,
3557         .free_device = free_device_v2_hw,
3558         .prep_smp = prep_smp_v2_hw,
3559         .prep_ssp = prep_ssp_v2_hw,
3560         .prep_stp = prep_ata_v2_hw,
3561         .prep_abort = prep_abort_v2_hw,
3562         .get_free_slot = get_free_slot_v2_hw,
3563         .start_delivery = start_delivery_v2_hw,
3564         .slot_complete = slot_complete_v2_hw,
3565         .phys_init = phys_init_v2_hw,
3566         .phy_start = start_phy_v2_hw,
3567         .phy_disable = disable_phy_v2_hw,
3568         .phy_hard_reset = phy_hard_reset_v2_hw,
3569         .get_events = phy_get_events_v2_hw,
3570         .phy_set_linkrate = phy_set_linkrate_v2_hw,
3571         .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
3572         .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
3573         .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3574         .soft_reset = soft_reset_v2_hw,
3575         .get_phys_state = get_phys_state_v2_hw,
3576         .write_gpio = write_gpio_v2_hw,
3577 };
3578
3579 static int hisi_sas_v2_probe(struct platform_device *pdev)
3580 {
3581         /*
3582          * Check if we should defer the probe before we probe the
3583          * upper layer, as it's hard to defer later on.
3584          */
3585         int ret = platform_get_irq(pdev, 0);
3586
3587         if (ret < 0) {
3588                 if (ret != -EPROBE_DEFER)
3589                         dev_err(&pdev->dev, "cannot obtain irq\n");
3590                 return ret;
3591         }
3592
3593         return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
3594 }
3595
3596 static int hisi_sas_v2_remove(struct platform_device *pdev)
3597 {
3598         struct sas_ha_struct *sha = platform_get_drvdata(pdev);
3599         struct hisi_hba *hisi_hba = sha->lldd_ha;
3600
3601         if (timer_pending(&hisi_hba->timer))
3602                 del_timer(&hisi_hba->timer);
3603
3604         hisi_sas_kill_tasklets(hisi_hba);
3605
3606         return hisi_sas_remove(pdev);
3607 }
3608
3609 static const struct of_device_id sas_v2_of_match[] = {
3610         { .compatible = "hisilicon,hip06-sas-v2",},
3611         { .compatible = "hisilicon,hip07-sas-v2",},
3612         {},
3613 };
3614 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
3615
3616 static const struct acpi_device_id sas_v2_acpi_match[] = {
3617         { "HISI0162", 0 },
3618         { }
3619 };
3620
3621 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
3622
3623 static struct platform_driver hisi_sas_v2_driver = {
3624         .probe = hisi_sas_v2_probe,
3625         .remove = hisi_sas_v2_remove,
3626         .driver = {
3627                 .name = DRV_NAME,
3628                 .of_match_table = sas_v2_of_match,
3629                 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
3630         },
3631 };
3632
3633 module_platform_driver(hisi_sas_v2_driver);
3634
3635 MODULE_LICENSE("GPL");
3636 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3637 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3638 MODULE_ALIAS("platform:" DRV_NAME);