drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

   1 /*
   2  * Copyright (c) 2016 Linaro Ltd.
   3  * Copyright (c) 2016 Hisilicon Limited.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  */
  11
  12 #include "hisi_sas.h"
  13 #define DRV_NAME "hisi_sas_v2_hw"
  14
  15 /* global registers need init*/
  16 #define DLVRY_QUEUE_ENABLE              0x0
  17 #define IOST_BASE_ADDR_LO               0x8
  18 #define IOST_BASE_ADDR_HI               0xc
  19 #define ITCT_BASE_ADDR_LO               0x10
  20 #define ITCT_BASE_ADDR_HI               0x14
  21 #define IO_BROKEN_MSG_ADDR_LO           0x18
  22 #define IO_BROKEN_MSG_ADDR_HI           0x1c
  23 #define PHY_CONTEXT                     0x20
  24 #define PHY_STATE                       0x24
  25 #define PHY_PORT_NUM_MA                 0x28
  26 #define PORT_STATE                      0x2c
  27 #define PORT_STATE_PHY8_PORT_NUM_OFF    16
  28 #define PORT_STATE_PHY8_PORT_NUM_MSK    (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
  29 #define PORT_STATE_PHY8_CONN_RATE_OFF   20
  30 #define PORT_STATE_PHY8_CONN_RATE_MSK   (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
  31 #define PHY_CONN_RATE                   0x30
  32 #define HGC_TRANS_TASK_CNT_LIMIT        0x38
  33 #define AXI_AHB_CLK_CFG                 0x3c
  34 #define ITCT_CLR                        0x44
  35 #define ITCT_CLR_EN_OFF                 16
  36 #define ITCT_CLR_EN_MSK                 (0x1 << ITCT_CLR_EN_OFF)
  37 #define ITCT_DEV_OFF                    0
  38 #define ITCT_DEV_MSK                    (0x7ff << ITCT_DEV_OFF)
  39 #define AXI_USER1                       0x48
  40 #define AXI_USER2                       0x4c
  41 #define IO_SATA_BROKEN_MSG_ADDR_LO      0x58
  42 #define IO_SATA_BROKEN_MSG_ADDR_HI      0x5c
  43 #define SATA_INITI_D2H_STORE_ADDR_LO    0x60
  44 #define SATA_INITI_D2H_STORE_ADDR_HI    0x64
  45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
  46 #define HGC_SAS_TXFAIL_RETRY_CTRL       0x88
  47 #define HGC_GET_ITV_TIME                0x90
  48 #define DEVICE_MSG_WORK_MODE            0x94
  49 #define OPENA_WT_CONTI_TIME             0x9c
  50 #define I_T_NEXUS_LOSS_TIME             0xa0
  51 #define MAX_CON_TIME_LIMIT_TIME         0xa4
  52 #define BUS_INACTIVE_LIMIT_TIME         0xa8
  53 #define REJECT_TO_OPEN_LIMIT_TIME       0xac
  54 #define CFG_AGING_TIME                  0xbc
  55 #define HGC_DFX_CFG2                    0xc0
  56 #define HGC_IOMB_PROC1_STATUS   0x104
  57 #define CFG_1US_TIMER_TRSH              0xcc
  58 #define HGC_LM_DFX_STATUS2              0x128
  59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF         0
  60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
  61                                          HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
  62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF         12
  63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
  64                                          HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
  65 #define HGC_CQE_ECC_ADDR                0x13c
  66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
  67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
  68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
  69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
  70 #define HGC_IOST_ECC_ADDR               0x140
  71 #define HGC_IOST_ECC_1B_ADDR_OFF        0
  72 #define HGC_IOST_ECC_1B_ADDR_MSK        (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
  73 #define HGC_IOST_ECC_MB_ADDR_OFF        16
  74 #define HGC_IOST_ECC_MB_ADDR_MSK        (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
  75 #define HGC_DQE_ECC_ADDR                0x144
  76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
  77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
  78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
  79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
  80 #define HGC_INVLD_DQE_INFO              0x148
  81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF   9
  82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK   (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
  83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF   18
  84 #define HGC_ITCT_ECC_ADDR               0x150
  85 #define HGC_ITCT_ECC_1B_ADDR_OFF                0
  86 #define HGC_ITCT_ECC_1B_ADDR_MSK                (0x3ff << \
  87                                                  HGC_ITCT_ECC_1B_ADDR_OFF)
  88 #define HGC_ITCT_ECC_MB_ADDR_OFF                16
  89 #define HGC_ITCT_ECC_MB_ADDR_MSK                (0x3ff << \
  90                                                  HGC_ITCT_ECC_MB_ADDR_OFF)
  91 #define HGC_AXI_FIFO_ERR_INFO   0x154
  92 #define AXI_ERR_INFO_OFF                0
  93 #define AXI_ERR_INFO_MSK                (0xff << AXI_ERR_INFO_OFF)
  94 #define FIFO_ERR_INFO_OFF               8
  95 #define FIFO_ERR_INFO_MSK               (0xff << FIFO_ERR_INFO_OFF)
  96 #define INT_COAL_EN                     0x19c
  97 #define OQ_INT_COAL_TIME                0x1a0
  98 #define OQ_INT_COAL_CNT                 0x1a4
  99 #define ENT_INT_COAL_TIME               0x1a8
 100 #define ENT_INT_COAL_CNT                0x1ac
 101 #define OQ_INT_SRC                      0x1b0
 102 #define OQ_INT_SRC_MSK                  0x1b4
 103 #define ENT_INT_SRC1                    0x1b8
 104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF    0
 105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
 106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF    8
 107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
 108 #define ENT_INT_SRC2                    0x1bc
 109 #define ENT_INT_SRC3                    0x1c0
 110 #define ENT_INT_SRC3_WP_DEPTH_OFF               8
 111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF      9
 112 #define ENT_INT_SRC3_RP_DEPTH_OFF               10
 113 #define ENT_INT_SRC3_AXI_OFF                    11
 114 #define ENT_INT_SRC3_FIFO_OFF                   12
 115 #define ENT_INT_SRC3_LM_OFF                             14
 116 #define ENT_INT_SRC3_ITC_INT_OFF        15
 117 #define ENT_INT_SRC3_ITC_INT_MSK        (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
 118 #define ENT_INT_SRC3_ABT_OFF            16
 119 #define ENT_INT_SRC_MSK1                0x1c4
 120 #define ENT_INT_SRC_MSK2                0x1c8
 121 #define ENT_INT_SRC_MSK3                0x1cc
 122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF  31
 123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK  (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
 124 #define SAS_ECC_INTR                    0x1e8
 125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF             0
 126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF             1
 127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF    2
 128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF    3
 129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF    4
 130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF    5
 131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF        6
 132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF        7
 133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF        8
 134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF        9
 135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF             10
 136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF             11
 137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF        12
 138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF        13
 139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF        14
 140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF        15
 141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF        16
 142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF        17
 143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF        18
 144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF        19
 145 #define SAS_ECC_INTR_MSK                0x1ec
 146 #define HGC_ERR_STAT_EN                 0x238
 147 #define DLVRY_Q_0_BASE_ADDR_LO          0x260
 148 #define DLVRY_Q_0_BASE_ADDR_HI          0x264
 149 #define DLVRY_Q_0_DEPTH                 0x268
 150 #define DLVRY_Q_0_WR_PTR                0x26c
 151 #define DLVRY_Q_0_RD_PTR                0x270
 152 #define HYPER_STREAM_ID_EN_CFG          0xc80
 153 #define OQ0_INT_SRC_MSK                 0xc90
 154 #define COMPL_Q_0_BASE_ADDR_LO          0x4e0
 155 #define COMPL_Q_0_BASE_ADDR_HI          0x4e4
 156 #define COMPL_Q_0_DEPTH                 0x4e8
 157 #define COMPL_Q_0_WR_PTR                0x4ec
 158 #define COMPL_Q_0_RD_PTR                0x4f0
 159 #define HGC_RXM_DFX_STATUS14    0xae8
 160 #define HGC_RXM_DFX_STATUS14_MEM0_OFF           0
 161 #define HGC_RXM_DFX_STATUS14_MEM0_MSK           (0x1ff << \
 162                                                  HGC_RXM_DFX_STATUS14_MEM0_OFF)
 163 #define HGC_RXM_DFX_STATUS14_MEM1_OFF           9
 164 #define HGC_RXM_DFX_STATUS14_MEM1_MSK           (0x1ff << \
 165                                                  HGC_RXM_DFX_STATUS14_MEM1_OFF)
 166 #define HGC_RXM_DFX_STATUS14_MEM2_OFF           18
 167 #define HGC_RXM_DFX_STATUS14_MEM2_MSK           (0x1ff << \
 168                                                  HGC_RXM_DFX_STATUS14_MEM2_OFF)
 169 #define HGC_RXM_DFX_STATUS15    0xaec
 170 #define HGC_RXM_DFX_STATUS15_MEM3_OFF           0
 171 #define HGC_RXM_DFX_STATUS15_MEM3_MSK           (0x1ff << \
 172                                                  HGC_RXM_DFX_STATUS15_MEM3_OFF)
 173 /* phy registers need init */
 174 #define PORT_BASE                       (0x2000)
 175
 176 #define PHY_CFG                         (PORT_BASE + 0x0)
 177 #define HARD_PHY_LINKRATE               (PORT_BASE + 0x4)
 178 #define PHY_CFG_ENA_OFF                 0
 179 #define PHY_CFG_ENA_MSK                 (0x1 << PHY_CFG_ENA_OFF)
 180 #define PHY_CFG_DC_OPT_OFF              2
 181 #define PHY_CFG_DC_OPT_MSK              (0x1 << PHY_CFG_DC_OPT_OFF)
 182 #define PROG_PHY_LINK_RATE              (PORT_BASE + 0x8)
 183 #define PROG_PHY_LINK_RATE_MAX_OFF      0
 184 #define PROG_PHY_LINK_RATE_MAX_MSK      (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
 185 #define PHY_CTRL                        (PORT_BASE + 0x14)
 186 #define PHY_CTRL_RESET_OFF              0
 187 #define PHY_CTRL_RESET_MSK              (0x1 << PHY_CTRL_RESET_OFF)
 188 #define SAS_PHY_CTRL                    (PORT_BASE + 0x20)
 189 #define SL_CFG                          (PORT_BASE + 0x84)
 190 #define PHY_PCN                         (PORT_BASE + 0x44)
 191 #define SL_TOUT_CFG                     (PORT_BASE + 0x8c)
 192 #define SL_CONTROL                      (PORT_BASE + 0x94)
 193 #define SL_CONTROL_NOTIFY_EN_OFF        0
 194 #define SL_CONTROL_NOTIFY_EN_MSK        (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
 195 #define SL_CONTROL_CTA_OFF              17
 196 #define SL_CONTROL_CTA_MSK              (0x1 << SL_CONTROL_CTA_OFF)
 197 #define RX_PRIMS_STATUS                 (PORT_BASE + 0x98)
 198 #define RX_BCAST_CHG_OFF                1
 199 #define RX_BCAST_CHG_MSK                (0x1 << RX_BCAST_CHG_OFF)
 200 #define TX_ID_DWORD0                    (PORT_BASE + 0x9c)
 201 #define TX_ID_DWORD1                    (PORT_BASE + 0xa0)
 202 #define TX_ID_DWORD2                    (PORT_BASE + 0xa4)
 203 #define TX_ID_DWORD3                    (PORT_BASE + 0xa8)
 204 #define TX_ID_DWORD4                    (PORT_BASE + 0xaC)
 205 #define TX_ID_DWORD5                    (PORT_BASE + 0xb0)
 206 #define TX_ID_DWORD6                    (PORT_BASE + 0xb4)
 207 #define TXID_AUTO                       (PORT_BASE + 0xb8)
 208 #define TXID_AUTO_CT3_OFF               1
 209 #define TXID_AUTO_CT3_MSK               (0x1 << TXID_AUTO_CT3_OFF)
 210 #define TXID_AUTO_CTB_OFF               11
 211 #define TXID_AUTO_CTB_MSK               (0x1 << TXID_AUTO_CTB_OFF)
 212 #define TX_HARDRST_OFF                  2
 213 #define TX_HARDRST_MSK                  (0x1 << TX_HARDRST_OFF)
 214 #define RX_IDAF_DWORD0                  (PORT_BASE + 0xc4)
 215 #define RX_IDAF_DWORD1                  (PORT_BASE + 0xc8)
 216 #define RX_IDAF_DWORD2                  (PORT_BASE + 0xcc)
 217 #define RX_IDAF_DWORD3                  (PORT_BASE + 0xd0)
 218 #define RX_IDAF_DWORD4                  (PORT_BASE + 0xd4)
 219 #define RX_IDAF_DWORD5                  (PORT_BASE + 0xd8)
 220 #define RX_IDAF_DWORD6                  (PORT_BASE + 0xdc)
 221 #define RXOP_CHECK_CFG_H                (PORT_BASE + 0xfc)
 222 #define CON_CONTROL                     (PORT_BASE + 0x118)
 223 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF        0
 224 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK        \
 225                 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
 226 #define DONE_RECEIVED_TIME              (PORT_BASE + 0x11c)
 227 #define CHL_INT0                        (PORT_BASE + 0x1b4)
 228 #define CHL_INT0_HOTPLUG_TOUT_OFF       0
 229 #define CHL_INT0_HOTPLUG_TOUT_MSK       (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
 230 #define CHL_INT0_SL_RX_BCST_ACK_OFF     1
 231 #define CHL_INT0_SL_RX_BCST_ACK_MSK     (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
 232 #define CHL_INT0_SL_PHY_ENABLE_OFF      2
 233 #define CHL_INT0_SL_PHY_ENABLE_MSK      (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
 234 #define CHL_INT0_NOT_RDY_OFF            4
 235 #define CHL_INT0_NOT_RDY_MSK            (0x1 << CHL_INT0_NOT_RDY_OFF)
 236 #define CHL_INT0_PHY_RDY_OFF            5
 237 #define CHL_INT0_PHY_RDY_MSK            (0x1 << CHL_INT0_PHY_RDY_OFF)
 238 #define CHL_INT1                        (PORT_BASE + 0x1b8)
 239 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF    15
 240 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
 241 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF    17
 242 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
 243 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
 244 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
 245 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
 246 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
 247 #define CHL_INT2                        (PORT_BASE + 0x1bc)
 248 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF  0
 249 #define CHL_INT0_MSK                    (PORT_BASE + 0x1c0)
 250 #define CHL_INT1_MSK                    (PORT_BASE + 0x1c4)
 251 #define CHL_INT2_MSK                    (PORT_BASE + 0x1c8)
 252 #define CHL_INT_COAL_EN                 (PORT_BASE + 0x1d0)
 253 #define DMA_TX_DFX0                             (PORT_BASE + 0x200)
 254 #define DMA_TX_DFX1                             (PORT_BASE + 0x204)
 255 #define DMA_TX_DFX1_IPTT_OFF            0
 256 #define DMA_TX_DFX1_IPTT_MSK            (0xffff << DMA_TX_DFX1_IPTT_OFF)
 257 #define DMA_TX_FIFO_DFX0                (PORT_BASE + 0x240)
 258 #define PORT_DFX0                               (PORT_BASE + 0x258)
 259 #define LINK_DFX2                                       (PORT_BASE + 0X264)
 260 #define LINK_DFX2_RCVR_HOLD_STS_OFF     9
 261 #define LINK_DFX2_RCVR_HOLD_STS_MSK     (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
 262 #define LINK_DFX2_SEND_HOLD_STS_OFF     10
 263 #define LINK_DFX2_SEND_HOLD_STS_MSK     (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
 264 #define SAS_ERR_CNT4_REG                (PORT_BASE + 0x290)
 265 #define SAS_ERR_CNT6_REG                (PORT_BASE + 0x298)
 266 #define PHY_CTRL_RDY_MSK                (PORT_BASE + 0x2b0)
 267 #define PHYCTRL_NOT_RDY_MSK             (PORT_BASE + 0x2b4)
 268 #define PHYCTRL_DWS_RESET_MSK           (PORT_BASE + 0x2b8)
 269 #define PHYCTRL_PHY_ENA_MSK             (PORT_BASE + 0x2bc)
 270 #define SL_RX_BCAST_CHK_MSK             (PORT_BASE + 0x2c0)
 271 #define PHYCTRL_OOB_RESTART_MSK         (PORT_BASE + 0x2c4)
 272 #define DMA_TX_STATUS                   (PORT_BASE + 0x2d0)
 273 #define DMA_TX_STATUS_BUSY_OFF          0
 274 #define DMA_TX_STATUS_BUSY_MSK          (0x1 << DMA_TX_STATUS_BUSY_OFF)
 275 #define DMA_RX_STATUS                   (PORT_BASE + 0x2e8)
 276 #define DMA_RX_STATUS_BUSY_OFF          0
 277 #define DMA_RX_STATUS_BUSY_MSK          (0x1 << DMA_RX_STATUS_BUSY_OFF)
 278
 279 #define AXI_CFG                         (0x5100)
 280 #define AM_CFG_MAX_TRANS                (0x5010)
 281 #define AM_CFG_SINGLE_PORT_MAX_TRANS    (0x5014)
 282
 283 #define AXI_MASTER_CFG_BASE             (0x5000)
 284 #define AM_CTRL_GLOBAL                  (0x0)
 285 #define AM_CURR_TRANS_RETURN    (0x150)
 286
 287 /* HW dma structures */
 288 /* Delivery queue header */
 289 /* dw0 */
 290 #define CMD_HDR_ABORT_FLAG_OFF          0
 291 #define CMD_HDR_ABORT_FLAG_MSK          (0x3 << CMD_HDR_ABORT_FLAG_OFF)
 292 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF   2
 293 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK   (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
 294 #define CMD_HDR_RESP_REPORT_OFF         5
 295 #define CMD_HDR_RESP_REPORT_MSK         (0x1 << CMD_HDR_RESP_REPORT_OFF)
 296 #define CMD_HDR_TLR_CTRL_OFF            6
 297 #define CMD_HDR_TLR_CTRL_MSK            (0x3 << CMD_HDR_TLR_CTRL_OFF)
 298 #define CMD_HDR_PORT_OFF                18
 299 #define CMD_HDR_PORT_MSK                (0xf << CMD_HDR_PORT_OFF)
 300 #define CMD_HDR_PRIORITY_OFF            27
 301 #define CMD_HDR_PRIORITY_MSK            (0x1 << CMD_HDR_PRIORITY_OFF)
 302 #define CMD_HDR_CMD_OFF                 29
 303 #define CMD_HDR_CMD_MSK                 (0x7 << CMD_HDR_CMD_OFF)
 304 /* dw1 */
 305 #define CMD_HDR_DIR_OFF                 5
 306 #define CMD_HDR_DIR_MSK                 (0x3 << CMD_HDR_DIR_OFF)
 307 #define CMD_HDR_RESET_OFF               7
 308 #define CMD_HDR_RESET_MSK               (0x1 << CMD_HDR_RESET_OFF)
 309 #define CMD_HDR_VDTL_OFF                10
 310 #define CMD_HDR_VDTL_MSK                (0x1 << CMD_HDR_VDTL_OFF)
 311 #define CMD_HDR_FRAME_TYPE_OFF          11
 312 #define CMD_HDR_FRAME_TYPE_MSK          (0x1f << CMD_HDR_FRAME_TYPE_OFF)
 313 #define CMD_HDR_DEV_ID_OFF              16
 314 #define CMD_HDR_DEV_ID_MSK              (0xffff << CMD_HDR_DEV_ID_OFF)
 315 /* dw2 */
 316 #define CMD_HDR_CFL_OFF                 0
 317 #define CMD_HDR_CFL_MSK                 (0x1ff << CMD_HDR_CFL_OFF)
 318 #define CMD_HDR_NCQ_TAG_OFF             10
 319 #define CMD_HDR_NCQ_TAG_MSK             (0x1f << CMD_HDR_NCQ_TAG_OFF)
 320 #define CMD_HDR_MRFL_OFF                15
 321 #define CMD_HDR_MRFL_MSK                (0x1ff << CMD_HDR_MRFL_OFF)
 322 #define CMD_HDR_SG_MOD_OFF              24
 323 #define CMD_HDR_SG_MOD_MSK              (0x3 << CMD_HDR_SG_MOD_OFF)
 324 #define CMD_HDR_FIRST_BURST_OFF         26
 325 #define CMD_HDR_FIRST_BURST_MSK         (0x1 << CMD_HDR_SG_MOD_OFF)
 326 /* dw3 */
 327 #define CMD_HDR_IPTT_OFF                0
 328 #define CMD_HDR_IPTT_MSK                (0xffff << CMD_HDR_IPTT_OFF)
 329 /* dw6 */
 330 #define CMD_HDR_DIF_SGL_LEN_OFF         0
 331 #define CMD_HDR_DIF_SGL_LEN_MSK         (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
 332 #define CMD_HDR_DATA_SGL_LEN_OFF        16
 333 #define CMD_HDR_DATA_SGL_LEN_MSK        (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
 334 #define CMD_HDR_ABORT_IPTT_OFF          16
 335 #define CMD_HDR_ABORT_IPTT_MSK          (0xffff << CMD_HDR_ABORT_IPTT_OFF)
 336
 337 /* Completion header */
 338 /* dw0 */
 339 #define CMPLT_HDR_ERR_PHASE_OFF 2
 340 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
 341 #define CMPLT_HDR_RSPNS_XFRD_OFF        10
 342 #define CMPLT_HDR_RSPNS_XFRD_MSK        (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
 343 #define CMPLT_HDR_ERX_OFF               12
 344 #define CMPLT_HDR_ERX_MSK               (0x1 << CMPLT_HDR_ERX_OFF)
 345 #define CMPLT_HDR_ABORT_STAT_OFF        13
 346 #define CMPLT_HDR_ABORT_STAT_MSK        (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
 347 /* abort_stat */
 348 #define STAT_IO_NOT_VALID               0x1
 349 #define STAT_IO_NO_DEVICE               0x2
 350 #define STAT_IO_COMPLETE                0x3
 351 #define STAT_IO_ABORTED                 0x4
 352 /* dw1 */
 353 #define CMPLT_HDR_IPTT_OFF              0
 354 #define CMPLT_HDR_IPTT_MSK              (0xffff << CMPLT_HDR_IPTT_OFF)
 355 #define CMPLT_HDR_DEV_ID_OFF            16
 356 #define CMPLT_HDR_DEV_ID_MSK            (0xffff << CMPLT_HDR_DEV_ID_OFF)
 357
 358 /* ITCT header */
 359 /* qw0 */
 360 #define ITCT_HDR_DEV_TYPE_OFF           0
 361 #define ITCT_HDR_DEV_TYPE_MSK           (0x3 << ITCT_HDR_DEV_TYPE_OFF)
 362 #define ITCT_HDR_VALID_OFF              2
 363 #define ITCT_HDR_VALID_MSK              (0x1 << ITCT_HDR_VALID_OFF)
 364 #define ITCT_HDR_MCR_OFF                5
 365 #define ITCT_HDR_MCR_MSK                (0xf << ITCT_HDR_MCR_OFF)
 366 #define ITCT_HDR_VLN_OFF                9
 367 #define ITCT_HDR_VLN_MSK                (0xf << ITCT_HDR_VLN_OFF)
 368 #define ITCT_HDR_SMP_TIMEOUT_OFF        16
 369 #define ITCT_HDR_SMP_TIMEOUT_8US        1
 370 #define ITCT_HDR_SMP_TIMEOUT            (ITCT_HDR_SMP_TIMEOUT_8US * \
 371                                          250) /* 2ms */
 372 #define ITCT_HDR_AWT_CONTINUE_OFF       25
 373 #define ITCT_HDR_PORT_ID_OFF            28
 374 #define ITCT_HDR_PORT_ID_MSK            (0xf << ITCT_HDR_PORT_ID_OFF)
 375 /* qw2 */
 376 #define ITCT_HDR_INLT_OFF               0
 377 #define ITCT_HDR_INLT_MSK               (0xffffULL << ITCT_HDR_INLT_OFF)
 378 #define ITCT_HDR_BITLT_OFF              16
 379 #define ITCT_HDR_BITLT_MSK              (0xffffULL << ITCT_HDR_BITLT_OFF)
 380 #define ITCT_HDR_MCTLT_OFF              32
 381 #define ITCT_HDR_MCTLT_MSK              (0xffffULL << ITCT_HDR_MCTLT_OFF)
 382 #define ITCT_HDR_RTOLT_OFF              48
 383 #define ITCT_HDR_RTOLT_MSK              (0xffffULL << ITCT_HDR_RTOLT_OFF)
 384
 385 #define HISI_SAS_FATAL_INT_NR   2
 386
 387 struct hisi_sas_complete_v2_hdr {
 388         __le32 dw0;
 389         __le32 dw1;
 390         __le32 act;
 391         __le32 dw3;
 392 };
 393
 394 struct hisi_sas_err_record_v2 {
 395         /* dw0 */
 396         __le32 trans_tx_fail_type;
 397
 398         /* dw1 */
 399         __le32 trans_rx_fail_type;
 400
 401         /* dw2 */
 402         __le16 dma_tx_err_type;
 403         __le16 sipc_rx_err_type;
 404
 405         /* dw3 */
 406         __le32 dma_rx_err_type;
 407 };
 408
 409 struct signal_attenuation_s {
 410         u32 de_emphasis;
 411         u32 preshoot;
 412         u32 boost;
 413 };
 414
 415 struct sig_atten_lu_s {
 416         const struct signal_attenuation_s *att;
 417         u32 sas_phy_ctrl;
 418 };
 419
 420 static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
 421         {
 422                 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
 423                 .msk = HGC_DQE_ECC_1B_ADDR_MSK,
 424                 .shift = HGC_DQE_ECC_1B_ADDR_OFF,
 425                 .msg = "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n",
 426                 .reg = HGC_DQE_ECC_ADDR,
 427         },
 428         {
 429                 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
 430                 .msk = HGC_IOST_ECC_1B_ADDR_MSK,
 431                 .shift = HGC_IOST_ECC_1B_ADDR_OFF,
 432                 .msg = "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n",
 433                 .reg = HGC_IOST_ECC_ADDR,
 434         },
 435         {
 436                 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
 437                 .msk = HGC_ITCT_ECC_1B_ADDR_MSK,
 438                 .shift = HGC_ITCT_ECC_1B_ADDR_OFF,
 439                 .msg = "hgc_itct_acc1b_intr found: am address is 0x%08X\n",
 440                 .reg = HGC_ITCT_ECC_ADDR,
 441         },
 442         {
 443                 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
 444                 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
 445                 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
 446                 .msg = "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n",
 447                 .reg = HGC_LM_DFX_STATUS2,
 448         },
 449         {
 450                 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
 451                 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
 452                 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
 453                 .msg = "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n",
 454                 .reg = HGC_LM_DFX_STATUS2,
 455         },
 456         {
 457                 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
 458                 .msk = HGC_CQE_ECC_1B_ADDR_MSK,
 459                 .shift = HGC_CQE_ECC_1B_ADDR_OFF,
 460                 .msg = "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n",
 461                 .reg = HGC_CQE_ECC_ADDR,
 462         },
 463         {
 464                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
 465                 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
 466                 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
 467                 .msg = "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n",
 468                 .reg = HGC_RXM_DFX_STATUS14,
 469         },
 470         {
 471                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
 472                 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
 473                 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
 474                 .msg = "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n",
 475                 .reg = HGC_RXM_DFX_STATUS14,
 476         },
 477         {
 478                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
 479                 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
 480                 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
 481                 .msg = "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n",
 482                 .reg = HGC_RXM_DFX_STATUS14,
 483         },
 484         {
 485                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
 486                 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
 487                 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
 488                 .msg = "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n",
 489                 .reg = HGC_RXM_DFX_STATUS15,
 490         },
 491 };
 492
 493 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
 494         {
 495                 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
 496                 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
 497                 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
 498                 .msg = "hgc_dqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
 499                 .reg = HGC_DQE_ECC_ADDR,
 500         },
 501         {
 502                 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
 503                 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
 504                 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
 505                 .msg = "hgc_iost_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
 506                 .reg = HGC_IOST_ECC_ADDR,
 507         },
 508         {
 509                 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
 510                 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
 511                 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
 512                 .msg = "hgc_itct_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
 513                 .reg = HGC_ITCT_ECC_ADDR,
 514         },
 515         {
 516                 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
 517                 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
 518                 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
 519                 .msg = "hgc_iostl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 520                 .reg = HGC_LM_DFX_STATUS2,
 521         },
 522         {
 523                 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
 524                 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
 525                 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
 526                 .msg = "hgc_itctl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 527                 .reg = HGC_LM_DFX_STATUS2,
 528         },
 529         {
 530                 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
 531                 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
 532                 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
 533                 .msg = "hgc_cqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
 534                 .reg = HGC_CQE_ECC_ADDR,
 535         },
 536         {
 537                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
 538                 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
 539                 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
 540                 .msg = "rxm_mem0_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 541                 .reg = HGC_RXM_DFX_STATUS14,
 542         },
 543         {
 544                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
 545                 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
 546                 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
 547                 .msg = "rxm_mem1_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 548                 .reg = HGC_RXM_DFX_STATUS14,
 549         },
 550         {
 551                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
 552                 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
 553                 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
 554                 .msg = "rxm_mem2_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 555                 .reg = HGC_RXM_DFX_STATUS14,
 556         },
 557         {
 558                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
 559                 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
 560                 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
 561                 .msg = "rxm_mem3_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 562                 .reg = HGC_RXM_DFX_STATUS15,
 563         },
 564 };
 565
 566 enum {
 567         HISI_SAS_PHY_PHY_UPDOWN,
 568         HISI_SAS_PHY_CHNL_INT,
 569         HISI_SAS_PHY_INT_NR
 570 };
 571
 572 enum {
 573         TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
 574         TRANS_RX_FAIL_BASE = 0x20, /* dw1 */
 575         DMA_TX_ERR_BASE = 0x40, /* dw2 bit 15-0 */
 576         SIPC_RX_ERR_BASE = 0x50, /* dw2 bit 31-16*/
 577         DMA_RX_ERR_BASE = 0x60, /* dw3 */
 578
 579         /* trans tx*/
 580         TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
 581         TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
 582         TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
 583         TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
 584         TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
 585         RESERVED0, /* 0x5 */
 586         TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
 587         TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
 588         TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
 589         TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
 590         TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
 591         TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
 592         TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
 593         TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
 594         TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
 595         TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
 596         TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
 597         TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
 598         TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
 599         TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
 600         TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
 601         TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
 602         TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
 603         TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
 604         TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
 605         TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
 606         TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
 607         TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
 608         /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
 609         TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
 610         /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
 611         TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
 612         TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
 613         /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
 614         TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
 615
 616         /* trans rx */
 617         TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x20 */
 618         TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x21 for sata/stp */
 619         TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x22 for ssp/smp */
 620         /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
 621         TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x23 for sata/stp */
 622         TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x24 for sata/stp */
 623         TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x25 for smp */
 624         /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
 625         TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x26 for sata/stp*/
 626         TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x27 */
 627         TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x28 */
 628         TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x29 */
 629         TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x2a */
 630         RESERVED1, /* 0x2b */
 631         TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x2c */
 632         TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x2d */
 633         TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x2e */
 634         TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x2f */
 635         TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x30 for ssp/smp */
 636         TRANS_RX_ERR_WITH_BAD_HASH, /* 0x31 for ssp */
 637         /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
 638         TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x32 for ssp*/
 639         /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
 640         TRANS_RX_SSP_FRM_LEN_ERR, /* 0x33 for ssp */
 641         /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
 642         RESERVED2, /* 0x34 */
 643         RESERVED3, /* 0x35 */
 644         RESERVED4, /* 0x36 */
 645         RESERVED5, /* 0x37 */
 646         TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x38 */
 647         TRANS_RX_SMP_FRM_LEN_ERR, /* 0x39 */
 648         TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x3a */
 649         RESERVED6, /* 0x3b */
 650         RESERVED7, /* 0x3c */
 651         RESERVED8, /* 0x3d */
 652         RESERVED9, /* 0x3e */
 653         TRANS_RX_R_ERR, /* 0x3f */
 654
 655         /* dma tx */
 656         DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x40 */
 657         DMA_TX_DIF_APP_ERR, /* 0x41 */
 658         DMA_TX_DIF_RPP_ERR, /* 0x42 */
 659         DMA_TX_DATA_SGL_OVERFLOW, /* 0x43 */
 660         DMA_TX_DIF_SGL_OVERFLOW, /* 0x44 */
 661         DMA_TX_UNEXP_XFER_ERR, /* 0x45 */
 662         DMA_TX_UNEXP_RETRANS_ERR, /* 0x46 */
 663         DMA_TX_XFER_LEN_OVERFLOW, /* 0x47 */
 664         DMA_TX_XFER_OFFSET_ERR, /* 0x48 */
 665         DMA_TX_RAM_ECC_ERR, /* 0x49 */
 666         DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x4a */
 667         DMA_TX_MAX_ERR_CODE,
 668
 669         /* sipc rx */
 670         SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x50 */
 671         SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x51 */
 672         SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x52 */
 673         SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x53 */
 674         SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x54 */
 675         SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x55 */
 676         SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x56 */
 677         SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x57 */
 678         SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x58 */
 679         SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x59 */
 680         SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x5a */
 681         SIPC_RX_MAX_ERR_CODE,
 682
 683         /* dma rx */
 684         DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x60 */
 685         DMA_RX_DIF_APP_ERR, /* 0x61 */
 686         DMA_RX_DIF_RPP_ERR, /* 0x62 */
 687         DMA_RX_DATA_SGL_OVERFLOW, /* 0x63 */
 688         DMA_RX_DIF_SGL_OVERFLOW, /* 0x64 */
 689         DMA_RX_DATA_LEN_OVERFLOW, /* 0x65 */
 690         DMA_RX_DATA_LEN_UNDERFLOW, /* 0x66 */
 691         DMA_RX_DATA_OFFSET_ERR, /* 0x67 */
 692         RESERVED10, /* 0x68 */
 693         DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x69 */
 694         DMA_RX_RESP_BUF_OVERFLOW, /* 0x6a */
 695         DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x6b */
 696         DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x6c */
 697         DMA_RX_UNEXP_RDFRAME_ERR, /* 0x6d */
 698         DMA_RX_PIO_DATA_LEN_ERR, /* 0x6e */
 699         DMA_RX_RDSETUP_STATUS_ERR, /* 0x6f */
 700         DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x70 */
 701         DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x71 */
 702         DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x72 */
 703         DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x73 */
 704         DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x74 */
 705         DMA_RX_RDSETUP_OFFSET_ERR, /* 0x75 */
 706         DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x76 */
 707         DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x77 */
 708         DMA_RX_RAM_ECC_ERR, /* 0x78 */
 709         DMA_RX_UNKNOWN_FRM_ERR, /* 0x79 */
 710         DMA_RX_MAX_ERR_CODE,
 711 };
 712
 713 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
 714 #define HISI_MAX_SATA_SUPPORT_V2_HW     (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
 715
 716 #define DIR_NO_DATA 0
 717 #define DIR_TO_INI 1
 718 #define DIR_TO_DEVICE 2
 719 #define DIR_RESERVED 3
 720
 721 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
 722                 err_phase == 0x4 || err_phase == 0x8 ||\
 723                 err_phase == 0x6 || err_phase == 0xa)
 724 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
 725                 err_phase == 0x20 || err_phase == 0x40)
 726
 727 static void link_timeout_disable_link(struct timer_list *t);
 728
 729 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
 730 {
 731         void __iomem *regs = hisi_hba->regs + off;
 732
 733         return readl(regs);
 734 }
 735
 736 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
 737 {
 738         void __iomem *regs = hisi_hba->regs + off;
 739
 740         return readl_relaxed(regs);
 741 }
 742
 743 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
 744 {
 745         void __iomem *regs = hisi_hba->regs + off;
 746
 747         writel(val, regs);
 748 }
 749
 750 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
 751                                  u32 off, u32 val)
 752 {
 753         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 754
 755         writel(val, regs);
 756 }
 757
 758 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
 759                                       int phy_no, u32 off)
 760 {
 761         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 762
 763         return readl(regs);
 764 }
 765
 766 /* This function needs to be protected from pre-emption. */
 767 static int
 768 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
 769                              struct domain_device *device)
 770 {
 771         int sata_dev = dev_is_sata(device);
 772         void *bitmap = hisi_hba->slot_index_tags;
 773         struct hisi_sas_device *sas_dev = device->lldd_dev;
 774         int sata_idx = sas_dev->sata_idx;
 775         int start, end;
 776
 777         if (!sata_dev) {
 778                 /*
 779                  * STP link SoC bug workaround: index starts from 1.
 780                  * additionally, we can only allocate odd IPTT(1~4095)
 781                  * for SAS/SMP device.
 782                  */
 783                 start = 1;
 784                 end = hisi_hba->slot_index_count;
 785         } else {
 786                 if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
 787                         return -EINVAL;
 788
 789                 /*
 790                  * For SATA device: allocate even IPTT in this interval
 791                  * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
 792                  * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
 793                  * SoC bug workaround. So we ignore the first 32 even IPTTs.
 794                  */
 795                 start = 64 * (sata_idx + 1);
 796                 end = 64 * (sata_idx + 2);
 797         }
 798
 799         while (1) {
 800                 start = find_next_zero_bit(bitmap,
 801                                         hisi_hba->slot_index_count, start);
 802                 if (start >= end)
 803                         return -SAS_QUEUE_FULL;
 804                 /*
 805                   * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
 806                   */
 807                 if (sata_dev ^ (start & 1))
 808                         break;
 809                 start++;
 810         }
 811
 812         set_bit(start, bitmap);
 813         *slot_idx = start;
 814         return 0;
 815 }
 816
 817 static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
 818 {
 819         unsigned int index;
 820         struct device *dev = hisi_hba->dev;
 821         void *bitmap = hisi_hba->sata_dev_bitmap;
 822
 823         index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
 824         if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
 825                 dev_warn(dev, "alloc sata index failed, index=%d\n", index);
 826                 return false;
 827         }
 828
 829         set_bit(index, bitmap);
 830         *idx = index;
 831         return true;
 832 }
 833
 834
 835 static struct
 836 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
 837 {
 838         struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
 839         struct hisi_sas_device *sas_dev = NULL;
 840         int i, sata_dev = dev_is_sata(device);
 841         int sata_idx = -1;
 842         unsigned long flags;
 843
 844         spin_lock_irqsave(&hisi_hba->lock, flags);
 845
 846         if (sata_dev)
 847                 if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
 848                         goto out;
 849
 850         for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
 851                 /*
 852                  * SATA device id bit0 should be 0
 853                  */
 854                 if (sata_dev && (i & 1))
 855                         continue;
 856                 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
 857                         int queue = i % hisi_hba->queue_count;
 858                         struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
 859
 860                         hisi_hba->devices[i].device_id = i;
 861                         sas_dev = &hisi_hba->devices[i];
 862                         sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
 863                         sas_dev->dev_type = device->dev_type;
 864                         sas_dev->hisi_hba = hisi_hba;
 865                         sas_dev->sas_device = device;
 866                         sas_dev->sata_idx = sata_idx;
 867                         sas_dev->dq = dq;
 868                         INIT_LIST_HEAD(&hisi_hba->devices[i].list);
 869                         break;
 870                 }
 871         }
 872
 873 out:
 874         spin_unlock_irqrestore(&hisi_hba->lock, flags);
 875
 876         return sas_dev;
 877 }
 878
 879 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 880 {
 881         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 882
 883         cfg &= ~PHY_CFG_DC_OPT_MSK;
 884         cfg |= 1 << PHY_CFG_DC_OPT_OFF;
 885         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 886 }
 887
 888 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 889 {
 890         struct sas_identify_frame identify_frame;
 891         u32 *identify_buffer;
 892
 893         memset(&identify_frame, 0, sizeof(identify_frame));
 894         identify_frame.dev_type = SAS_END_DEVICE;
 895         identify_frame.frame_type = 0;
 896         identify_frame._un1 = 1;
 897         identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
 898         identify_frame.target_bits = SAS_PROTOCOL_NONE;
 899         memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 900         memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 901         identify_frame.phy_id = phy_no;
 902         identify_buffer = (u32 *)(&identify_frame);
 903
 904         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
 905                         __swab32(identify_buffer[0]));
 906         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
 907                         __swab32(identify_buffer[1]));
 908         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
 909                         __swab32(identify_buffer[2]));
 910         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
 911                         __swab32(identify_buffer[3]));
 912         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
 913                         __swab32(identify_buffer[4]));
 914         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
 915                         __swab32(identify_buffer[5]));
 916 }
 917
 918 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
 919                              struct hisi_sas_device *sas_dev)
 920 {
 921         struct domain_device *device = sas_dev->sas_device;
 922         struct device *dev = hisi_hba->dev;
 923         u64 qw0, device_id = sas_dev->device_id;
 924         struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
 925         struct domain_device *parent_dev = device->parent;
 926         struct asd_sas_port *sas_port = device->port;
 927         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
 928
 929         memset(itct, 0, sizeof(*itct));
 930
 931         /* qw0 */
 932         qw0 = 0;
 933         switch (sas_dev->dev_type) {
 934         case SAS_END_DEVICE:
 935         case SAS_EDGE_EXPANDER_DEVICE:
 936         case SAS_FANOUT_EXPANDER_DEVICE:
 937                 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
 938                 break;
 939         case SAS_SATA_DEV:
 940         case SAS_SATA_PENDING:
 941                 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
 942                         qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
 943                 else
 944                         qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
 945                 break;
 946         default:
 947                 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
 948                          sas_dev->dev_type);
 949         }
 950
 951         qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
 952                 (device->linkrate << ITCT_HDR_MCR_OFF) |
 953                 (1 << ITCT_HDR_VLN_OFF) |
 954                 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
 955                 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
 956                 (port->id << ITCT_HDR_PORT_ID_OFF));
 957         itct->qw0 = cpu_to_le64(qw0);
 958
 959         /* qw1 */
 960         memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
 961         itct->sas_addr = __swab64(itct->sas_addr);
 962
 963         /* qw2 */
 964         if (!dev_is_sata(device))
 965                 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
 966                                         (0x1ULL << ITCT_HDR_BITLT_OFF) |
 967                                         (0x32ULL << ITCT_HDR_MCTLT_OFF) |
 968                                         (0x1ULL << ITCT_HDR_RTOLT_OFF));
 969 }
 970
 971 static void clear_itct_v2_hw(struct hisi_hba *hisi_hba,
 972                               struct hisi_sas_device *sas_dev)
 973 {
 974         DECLARE_COMPLETION_ONSTACK(completion);
 975         u64 dev_id = sas_dev->device_id;
 976         struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
 977         u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
 978         int i;
 979
 980         sas_dev->completion = &completion;
 981
 982         /* clear the itct interrupt state */
 983         if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
 984                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
 985                                  ENT_INT_SRC3_ITC_INT_MSK);
 986
 987         for (i = 0; i < 2; i++) {
 988                 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
 989                 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
 990                 wait_for_completion(sas_dev->completion);
 991
 992                 memset(itct, 0, sizeof(struct hisi_sas_itct));
 993         }
 994 }
 995
 996 static void free_device_v2_hw(struct hisi_sas_device *sas_dev)
 997 {
 998         struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
 999
1000         /* SoC bug workaround */
1001         if (dev_is_sata(sas_dev->sas_device))
1002                 clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
1003 }
1004
1005 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
1006 {
1007         int i, reset_val;
1008         u32 val;
1009         unsigned long end_time;
1010         struct device *dev = hisi_hba->dev;
1011
1012         /* The mask needs to be set depending on the number of phys */
1013         if (hisi_hba->n_phy == 9)
1014                 reset_val = 0x1fffff;
1015         else
1016                 reset_val = 0x7ffff;
1017
1018         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
1019
1020         /* Disable all of the PHYs */
1021         for (i = 0; i < hisi_hba->n_phy; i++) {
1022                 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
1023
1024                 phy_cfg &= ~PHY_CTRL_RESET_MSK;
1025                 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
1026         }
1027         udelay(50);
1028
1029         /* Ensure DMA tx & rx idle */
1030         for (i = 0; i < hisi_hba->n_phy; i++) {
1031                 u32 dma_tx_status, dma_rx_status;
1032
1033                 end_time = jiffies + msecs_to_jiffies(1000);
1034
1035                 while (1) {
1036                         dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
1037                                                             DMA_TX_STATUS);
1038                         dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
1039                                                             DMA_RX_STATUS);
1040
1041                         if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
1042                                 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
1043                                 break;
1044
1045                         msleep(20);
1046                         if (time_after(jiffies, end_time))
1047                                 return -EIO;
1048                 }
1049         }
1050
1051         /* Ensure axi bus idle */
1052         end_time = jiffies + msecs_to_jiffies(1000);
1053         while (1) {
1054                 u32 axi_status =
1055                         hisi_sas_read32(hisi_hba, AXI_CFG);
1056
1057                 if (axi_status == 0)
1058                         break;
1059
1060                 msleep(20);
1061                 if (time_after(jiffies, end_time))
1062                         return -EIO;
1063         }
1064
1065         if (ACPI_HANDLE(dev)) {
1066                 acpi_status s;
1067
1068                 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
1069                 if (ACPI_FAILURE(s)) {
1070                         dev_err(dev, "Reset failed\n");
1071                         return -EIO;
1072                 }
1073         } else if (hisi_hba->ctrl) {
1074                 /* reset and disable clock*/
1075                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
1076                                 reset_val);
1077                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
1078                                 reset_val);
1079                 msleep(1);
1080                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
1081                 if (reset_val != (val & reset_val)) {
1082                         dev_err(dev, "SAS reset fail.\n");
1083                         return -EIO;
1084                 }
1085
1086                 /* De-reset and enable clock*/
1087                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
1088                                 reset_val);
1089                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
1090                                 reset_val);
1091                 msleep(1);
1092                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
1093                                 &val);
1094                 if (val & reset_val) {
1095                         dev_err(dev, "SAS de-reset fail.\n");
1096                         return -EIO;
1097                 }
1098         } else {
1099                 dev_err(dev, "no reset method\n");
1100                 return -EINVAL;
1101         }
1102
1103         return 0;
1104 }
1105
1106 /* This function needs to be called after resetting SAS controller. */
1107 static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1108 {
1109         u32 cfg;
1110         int phy_no;
1111
1112         hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
1113         for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1114                 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
1115                 if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
1116                         continue;
1117
1118                 cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1119                 hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
1120         }
1121 }
1122
1123 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1124 {
1125         int phy_no;
1126         u32 dma_tx_dfx1;
1127
1128         for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1129                 if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
1130                         continue;
1131
1132                 dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1133                                                 DMA_TX_DFX1);
1134                 if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
1135                         u32 cfg = hisi_sas_phy_read32(hisi_hba,
1136                                 phy_no, CON_CONTROL);
1137
1138                         cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1139                         hisi_sas_phy_write32(hisi_hba, phy_no,
1140                                 CON_CONTROL, cfg);
1141                         clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
1142                 }
1143         }
1144 }
1145
1146 static const struct signal_attenuation_s x6000 = {9200, 0, 10476};
1147 static const struct sig_atten_lu_s sig_atten_lu[] = {
1148         { &x6000, 0x3016a68 },
1149 };
1150
1151 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
1152 {
1153         struct device *dev = hisi_hba->dev;
1154         u32 sas_phy_ctrl = 0x30b9908;
1155         u32 signal[3];
1156         int i;
1157
1158         /* Global registers init */
1159
1160         /* Deal with am-max-transmissions quirk */
1161         if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
1162                 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
1163                 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
1164                                  0x2020);
1165         } /* Else, use defaults -> do nothing */
1166
1167         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
1168                          (u32)((1ULL << hisi_hba->queue_count) - 1));
1169         hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
1170         hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
1171         hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
1172         hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
1173         hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
1174         hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
1175         hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
1176         hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
1177         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
1178         hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
1179         hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
1180         hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
1181         hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
1182         hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
1183         hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
1184         hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
1185         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
1186         hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
1187         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
1188         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
1189         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
1190         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
1191         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
1192         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
1193         for (i = 0; i < hisi_hba->queue_count; i++)
1194                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
1195
1196         hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
1197         hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
1198
1199         /* Get sas_phy_ctrl value to deal with TX FFE issue. */
1200         if (!device_property_read_u32_array(dev, "hisilicon,signal-attenuation",
1201                                             signal, ARRAY_SIZE(signal))) {
1202                 for (i = 0; i < ARRAY_SIZE(sig_atten_lu); i++) {
1203                         const struct sig_atten_lu_s *lookup = &sig_atten_lu[i];
1204                         const struct signal_attenuation_s *att = lookup->att;
1205
1206                         if ((signal[0] == att->de_emphasis) &&
1207                             (signal[1] == att->preshoot) &&
1208                             (signal[2] == att->boost)) {
1209                                 sas_phy_ctrl = lookup->sas_phy_ctrl;
1210                                 break;
1211                         }
1212                 }
1213
1214                 if (i == ARRAY_SIZE(sig_atten_lu))
1215                         dev_warn(dev, "unknown signal attenuation values, using default PHY ctrl config\n");
1216         }
1217
1218         for (i = 0; i < hisi_hba->n_phy; i++) {
1219                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1220                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1221                 u32 prog_phy_link_rate = 0x800;
1222
1223                 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
1224                                 SAS_LINK_RATE_1_5_GBPS)) {
1225                         prog_phy_link_rate = 0x855;
1226                 } else {
1227                         enum sas_linkrate max = sas_phy->phy->maximum_linkrate;
1228
1229                         prog_phy_link_rate =
1230                                 hisi_sas_get_prog_phy_linkrate_mask(max) |
1231                                 0x800;
1232                 }
1233                 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
1234                         prog_phy_link_rate);
1235                 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, sas_phy_ctrl);
1236                 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
1237                 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
1238                 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
1239                 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
1240                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
1241                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
1242                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
1243                 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
1244                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff857fff);
1245                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbfe);
1246                 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
1247                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
1248                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
1249                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
1250                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
1251                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
1252                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
1253                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
1254                 if (hisi_hba->refclk_frequency_mhz == 66)
1255                         hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
1256                 /* else, do nothing -> leave it how you found it */
1257         }
1258
1259         for (i = 0; i < hisi_hba->queue_count; i++) {
1260                 /* Delivery queue */
1261                 hisi_sas_write32(hisi_hba,
1262                                  DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
1263                                  upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
1264
1265                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
1266                                  lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
1267
1268                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
1269                                  HISI_SAS_QUEUE_SLOTS);
1270
1271                 /* Completion queue */
1272                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
1273                                  upper_32_bits(hisi_hba->complete_hdr_dma[i]));
1274
1275                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
1276                                  lower_32_bits(hisi_hba->complete_hdr_dma[i]));
1277
1278                 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
1279                                  HISI_SAS_QUEUE_SLOTS);
1280         }
1281
1282         /* itct */
1283         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
1284                          lower_32_bits(hisi_hba->itct_dma));
1285
1286         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
1287                          upper_32_bits(hisi_hba->itct_dma));
1288
1289         /* iost */
1290         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
1291                          lower_32_bits(hisi_hba->iost_dma));
1292
1293         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
1294                          upper_32_bits(hisi_hba->iost_dma));
1295
1296         /* breakpoint */
1297         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
1298                          lower_32_bits(hisi_hba->breakpoint_dma));
1299
1300         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
1301                          upper_32_bits(hisi_hba->breakpoint_dma));
1302
1303         /* SATA broken msg */
1304         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
1305                          lower_32_bits(hisi_hba->sata_breakpoint_dma));
1306
1307         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
1308                          upper_32_bits(hisi_hba->sata_breakpoint_dma));
1309
1310         /* SATA initial fis */
1311         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
1312                          lower_32_bits(hisi_hba->initial_fis_dma));
1313
1314         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
1315                          upper_32_bits(hisi_hba->initial_fis_dma));
1316 }
1317
1318 static void link_timeout_enable_link(struct timer_list *t)
1319 {
1320         struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1321         int i, reg_val;
1322
1323         for (i = 0; i < hisi_hba->n_phy; i++) {
1324                 if (hisi_hba->reject_stp_links_msk & BIT(i))
1325                         continue;
1326
1327                 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
1328                 if (!(reg_val & BIT(0))) {
1329                         hisi_sas_phy_write32(hisi_hba, i,
1330                                         CON_CONTROL, 0x7);
1331                         break;
1332                 }
1333         }
1334
1335         hisi_hba->timer.function = link_timeout_disable_link;
1336         mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
1337 }
1338
1339 static void link_timeout_disable_link(struct timer_list *t)
1340 {
1341         struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1342         int i, reg_val;
1343
1344         reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
1345         for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
1346                 if (hisi_hba->reject_stp_links_msk & BIT(i))
1347                         continue;
1348
1349                 if (reg_val & BIT(i)) {
1350                         hisi_sas_phy_write32(hisi_hba, i,
1351                                         CON_CONTROL, 0x6);
1352                         break;
1353                 }
1354         }
1355
1356         hisi_hba->timer.function = link_timeout_enable_link;
1357         mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
1358 }
1359
1360 static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
1361 {
1362         hisi_hba->timer.function = link_timeout_disable_link;
1363         hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
1364         add_timer(&hisi_hba->timer);
1365 }
1366
1367 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
1368 {
1369         struct device *dev = hisi_hba->dev;
1370         int rc;
1371
1372         rc = reset_hw_v2_hw(hisi_hba);
1373         if (rc) {
1374                 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1375                 return rc;
1376         }
1377
1378         msleep(100);
1379         init_reg_v2_hw(hisi_hba);
1380
1381         return 0;
1382 }
1383
1384 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1385 {
1386         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1387
1388         cfg |= PHY_CFG_ENA_MSK;
1389         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1390 }
1391
1392 static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1393 {
1394         u32 context;
1395
1396         context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1397         if (context & (1 << phy_no))
1398                 return true;
1399
1400         return false;
1401 }
1402
1403 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1404 {
1405         u32 dfx_val;
1406
1407         dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1408
1409         if (dfx_val & BIT(16))
1410                 return false;
1411
1412         return true;
1413 }
1414
1415 static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1416 {
1417         int i, max_loop = 1000;
1418         struct device *dev = hisi_hba->dev;
1419         u32 status, axi_status, dfx_val, dfx_tx_val;
1420
1421         for (i = 0; i < max_loop; i++) {
1422                 status = hisi_sas_read32_relaxed(hisi_hba,
1423                         AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
1424
1425                 axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
1426                 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1427                 dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
1428                         phy_no, DMA_TX_FIFO_DFX0);
1429
1430                 if ((status == 0x3) && (axi_status == 0x0) &&
1431                     (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
1432                         return true;
1433                 udelay(10);
1434         }
1435         dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1436                         phy_no, status, axi_status,
1437                         dfx_val, dfx_tx_val);
1438         return false;
1439 }
1440
1441 static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1442 {
1443         int i, max_loop = 1000;
1444         struct device *dev = hisi_hba->dev;
1445         u32 status, tx_dfx0;
1446
1447         for (i = 0; i < max_loop; i++) {
1448                 status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
1449                 status = (status & 0x3fc0) >> 6;
1450
1451                 if (status != 0x1)
1452                         return true;
1453
1454                 tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
1455                 if ((tx_dfx0 & 0x1ff) == 0x2)
1456                         return true;
1457                 udelay(10);
1458         }
1459         dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1460                         phy_no, status, tx_dfx0);
1461         return false;
1462 }
1463
1464 static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1465 {
1466         if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
1467                 return true;
1468
1469         if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
1470                 return false;
1471
1472         if (!wait_io_done_v2_hw(hisi_hba, phy_no))
1473                 return false;
1474
1475         return true;
1476 }
1477
1478
1479 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1480 {
1481         u32 cfg, axi_val, dfx0_val, txid_auto;
1482         struct device *dev = hisi_hba->dev;
1483
1484         /* Close axi bus. */
1485         axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
1486                                 AM_CTRL_GLOBAL);
1487         axi_val |= 0x1;
1488         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1489                 AM_CTRL_GLOBAL, axi_val);
1490
1491         if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
1492                 if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
1493                         goto do_disable;
1494
1495                 /* Reset host controller. */
1496                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1497                 return;
1498         }
1499
1500         dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
1501         dfx0_val = (dfx0_val & 0x1fc0) >> 6;
1502         if (dfx0_val != 0x4)
1503                 goto do_disable;
1504
1505         if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
1506                 dev_warn(dev, "phy%d, wait tx fifo need send break\n",
1507                         phy_no);
1508                 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
1509                                         TXID_AUTO);
1510                 txid_auto |= TXID_AUTO_CTB_MSK;
1511                 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1512                                         txid_auto);
1513         }
1514
1515 do_disable:
1516         cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1517         cfg &= ~PHY_CFG_ENA_MSK;
1518         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1519
1520         /* Open axi bus. */
1521         axi_val &= ~0x1;
1522         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1523                 AM_CTRL_GLOBAL, axi_val);
1524 }
1525
1526 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1527 {
1528         config_id_frame_v2_hw(hisi_hba, phy_no);
1529         config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
1530         enable_phy_v2_hw(hisi_hba, phy_no);
1531 }
1532
1533 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1534 {
1535         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1536         u32 txid_auto;
1537
1538         disable_phy_v2_hw(hisi_hba, phy_no);
1539         if (phy->identify.device_type == SAS_END_DEVICE) {
1540                 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1541                 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1542                                         txid_auto | TX_HARDRST_MSK);
1543         }
1544         msleep(100);
1545         start_phy_v2_hw(hisi_hba, phy_no);
1546 }
1547
1548 static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1549 {
1550         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1551         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1552         struct sas_phy *sphy = sas_phy->phy;
1553         u32 err4_reg_val, err6_reg_val;
1554
1555         /* loss dword syn, phy reset problem */
1556         err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
1557
1558         /* disparity err, invalid dword */
1559         err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
1560
1561         sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
1562         sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
1563         sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
1564         sphy->running_disparity_error_count += err6_reg_val & 0xFF;
1565 }
1566
1567 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
1568 {
1569         int i;
1570
1571         for (i = 0; i < hisi_hba->n_phy; i++) {
1572                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1573                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1574
1575                 if (!sas_phy->phy->enabled)
1576                         continue;
1577
1578                 start_phy_v2_hw(hisi_hba, i);
1579         }
1580 }
1581
1582 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1583 {
1584         u32 sl_control;
1585
1586         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1587         sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1588         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1589         msleep(1);
1590         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1591         sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1592         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1593 }
1594
1595 static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
1596 {
1597         return SAS_LINK_RATE_12_0_GBPS;
1598 }
1599
1600 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
1601                 struct sas_phy_linkrates *r)
1602 {
1603         enum sas_linkrate max = r->maximum_linkrate;
1604         u32 prog_phy_link_rate = 0x800;
1605
1606         prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
1607         hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1608                              prog_phy_link_rate);
1609 }
1610
1611 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
1612 {
1613         int i, bitmap = 0;
1614         u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1615         u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1616
1617         for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
1618                 if (phy_state & 1 << i)
1619                         if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1620                                 bitmap |= 1 << i;
1621
1622         if (hisi_hba->n_phy == 9) {
1623                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1624
1625                 if (phy_state & 1 << 8)
1626                         if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1627                              PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1628                                 bitmap |= 1 << 9;
1629         }
1630
1631         return bitmap;
1632 }
1633
1634 /*
1635  * The callpath to this function and upto writing the write
1636  * queue pointer should be safe from interruption.
1637  */
1638 static int
1639 get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
1640 {
1641         struct device *dev = hisi_hba->dev;
1642         int queue = dq->id;
1643         u32 r, w;
1644
1645         w = dq->wr_point;
1646         r = hisi_sas_read32_relaxed(hisi_hba,
1647                                 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1648         if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1649                 dev_warn(dev, "full queue=%d r=%d w=%d\n",
1650                                 queue, r, w);
1651                 return -EAGAIN;
1652         }
1653
1654         dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS;
1655
1656         return w;
1657 }
1658
1659 /* DQ lock must be taken here */
1660 static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
1661 {
1662         struct hisi_hba *hisi_hba = dq->hisi_hba;
1663         struct hisi_sas_slot *s, *s1;
1664         struct list_head *dq_list;
1665         int dlvry_queue = dq->id;
1666         int wp, count = 0;
1667
1668         dq_list = &dq->list;
1669         list_for_each_entry_safe(s, s1, &dq->list, delivery) {
1670                 if (!s->ready)
1671                         break;
1672                 count++;
1673                 wp = (s->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
1674                 list_del(&s->delivery);
1675         }
1676
1677         if (!count)
1678                 return;
1679
1680         hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
1681 }
1682
1683 static void prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1684                               struct hisi_sas_slot *slot,
1685                               struct hisi_sas_cmd_hdr *hdr,
1686                               struct scatterlist *scatter,
1687                               int n_elem)
1688 {
1689         struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1690         struct scatterlist *sg;
1691         int i;
1692
1693         for_each_sg(scatter, sg, n_elem, i) {
1694                 struct hisi_sas_sge *entry = &sge_page->sge[i];
1695
1696                 entry->addr = cpu_to_le64(sg_dma_address(sg));
1697                 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1698                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1699                 entry->data_off = 0;
1700         }
1701
1702         hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1703
1704         hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1705 }
1706
1707 static void prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1708                           struct hisi_sas_slot *slot)
1709 {
1710         struct sas_task *task = slot->task;
1711         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1712         struct domain_device *device = task->dev;
1713         struct hisi_sas_port *port = slot->port;
1714         struct scatterlist *sg_req;
1715         struct hisi_sas_device *sas_dev = device->lldd_dev;
1716         dma_addr_t req_dma_addr;
1717         unsigned int req_len;
1718
1719         /* req */
1720         sg_req = &task->smp_task.smp_req;
1721         req_dma_addr = sg_dma_address(sg_req);
1722         req_len = sg_dma_len(&task->smp_task.smp_req);
1723
1724         /* create header */
1725         /* dw0 */
1726         hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1727                                (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1728                                (2 << CMD_HDR_CMD_OFF)); /* smp */
1729
1730         /* map itct entry */
1731         hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1732                                (1 << CMD_HDR_FRAME_TYPE_OFF) |
1733                                (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1734
1735         /* dw2 */
1736         hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1737                                (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1738                                CMD_HDR_MRFL_OFF));
1739
1740         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1741
1742         hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1743         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1744 }
1745
1746 static void prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1747                           struct hisi_sas_slot *slot, int is_tmf,
1748                           struct hisi_sas_tmf_task *tmf)
1749 {
1750         struct sas_task *task = slot->task;
1751         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1752         struct domain_device *device = task->dev;
1753         struct hisi_sas_device *sas_dev = device->lldd_dev;
1754         struct hisi_sas_port *port = slot->port;
1755         struct sas_ssp_task *ssp_task = &task->ssp_task;
1756         struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1757         int has_data = 0, priority = is_tmf;
1758         u8 *buf_cmd;
1759         u32 dw1 = 0, dw2 = 0;
1760
1761         hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1762                                (2 << CMD_HDR_TLR_CTRL_OFF) |
1763                                (port->id << CMD_HDR_PORT_OFF) |
1764                                (priority << CMD_HDR_PRIORITY_OFF) |
1765                                (1 << CMD_HDR_CMD_OFF)); /* ssp */
1766
1767         dw1 = 1 << CMD_HDR_VDTL_OFF;
1768         if (is_tmf) {
1769                 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1770                 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1771         } else {
1772                 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1773                 switch (scsi_cmnd->sc_data_direction) {
1774                 case DMA_TO_DEVICE:
1775                         has_data = 1;
1776                         dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1777                         break;
1778                 case DMA_FROM_DEVICE:
1779                         has_data = 1;
1780                         dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1781                         break;
1782                 default:
1783                         dw1 &= ~CMD_HDR_DIR_MSK;
1784                 }
1785         }
1786
1787         /* map itct entry */
1788         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1789         hdr->dw1 = cpu_to_le32(dw1);
1790
1791         dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1792               + 3) / 4) << CMD_HDR_CFL_OFF) |
1793               ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1794               (2 << CMD_HDR_SG_MOD_OFF);
1795         hdr->dw2 = cpu_to_le32(dw2);
1796
1797         hdr->transfer_tags = cpu_to_le32(slot->idx);
1798
1799         if (has_data)
1800                 prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1801                                         slot->n_elem);
1802
1803         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1804         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1805         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1806
1807         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1808                 sizeof(struct ssp_frame_hdr);
1809
1810         memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1811         if (!is_tmf) {
1812                 buf_cmd[9] = task->ssp_task.task_attr |
1813                                 (task->ssp_task.task_prio << 3);
1814                 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1815                                 task->ssp_task.cmd->cmd_len);
1816         } else {
1817                 buf_cmd[10] = tmf->tmf;
1818                 switch (tmf->tmf) {
1819                 case TMF_ABORT_TASK:
1820                 case TMF_QUERY_TASK:
1821                         buf_cmd[12] =
1822                                 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1823                         buf_cmd[13] =
1824                                 tmf->tag_of_task_to_be_managed & 0xff;
1825                         break;
1826                 default:
1827                         break;
1828                 }
1829         }
1830 }
1831
1832 #define TRANS_TX_ERR    0
1833 #define TRANS_RX_ERR    1
1834 #define DMA_TX_ERR              2
1835 #define SIPC_RX_ERR             3
1836 #define DMA_RX_ERR              4
1837
1838 #define DMA_TX_ERR_OFF  0
1839 #define DMA_TX_ERR_MSK  (0xffff << DMA_TX_ERR_OFF)
1840 #define SIPC_RX_ERR_OFF 16
1841 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1842
1843 static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
1844 {
1845         static const u8 trans_tx_err_code_prio[] = {
1846                 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
1847                 TRANS_TX_ERR_PHY_NOT_ENABLE,
1848                 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
1849                 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
1850                 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
1851                 RESERVED0,
1852                 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
1853                 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
1854                 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
1855                 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
1856                 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
1857                 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
1858                 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
1859                 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
1860                 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
1861                 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
1862                 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
1863                 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
1864                 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1865                 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
1866                 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
1867                 TRANS_TX_ERR_WITH_BREAK_REQUEST,
1868                 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
1869                 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
1870                 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
1871                 TRANS_TX_ERR_WITH_NAK_RECEVIED,
1872                 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
1873                 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
1874                 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
1875                 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
1876                 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
1877         };
1878         int index, i;
1879
1880         for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
1881                 index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
1882                 if (err_msk & (1 << index))
1883                         return trans_tx_err_code_prio[i];
1884         }
1885         return -1;
1886 }
1887
1888 static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
1889 {
1890         static const u8 trans_rx_err_code_prio[] = {
1891                 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
1892                 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
1893                 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
1894                 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
1895                 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
1896                 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
1897                 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
1898                 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
1899                 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
1900                 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1901                 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
1902                 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
1903                 TRANS_RX_ERR_WITH_BREAK_REQUEST,
1904                 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
1905                 RESERVED1,
1906                 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
1907                 TRANS_RX_ERR_WITH_DATA_LEN0,
1908                 TRANS_RX_ERR_WITH_BAD_HASH,
1909                 TRANS_RX_XRDY_WLEN_ZERO_ERR,
1910                 TRANS_RX_SSP_FRM_LEN_ERR,
1911                 RESERVED2,
1912                 RESERVED3,
1913                 RESERVED4,
1914                 RESERVED5,
1915                 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
1916                 TRANS_RX_SMP_FRM_LEN_ERR,
1917                 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
1918                 RESERVED6,
1919                 RESERVED7,
1920                 RESERVED8,
1921                 RESERVED9,
1922                 TRANS_RX_R_ERR,
1923         };
1924         int index, i;
1925
1926         for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
1927                 index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
1928                 if (err_msk & (1 << index))
1929                         return trans_rx_err_code_prio[i];
1930         }
1931         return -1;
1932 }
1933
1934 static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
1935 {
1936         static const u8 dma_tx_err_code_prio[] = {
1937                 DMA_TX_UNEXP_XFER_ERR,
1938                 DMA_TX_UNEXP_RETRANS_ERR,
1939                 DMA_TX_XFER_LEN_OVERFLOW,
1940                 DMA_TX_XFER_OFFSET_ERR,
1941                 DMA_TX_RAM_ECC_ERR,
1942                 DMA_TX_DIF_LEN_ALIGN_ERR,
1943                 DMA_TX_DIF_CRC_ERR,
1944                 DMA_TX_DIF_APP_ERR,
1945                 DMA_TX_DIF_RPP_ERR,
1946                 DMA_TX_DATA_SGL_OVERFLOW,
1947                 DMA_TX_DIF_SGL_OVERFLOW,
1948         };
1949         int index, i;
1950
1951         for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
1952                 index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
1953                 err_msk = err_msk & DMA_TX_ERR_MSK;
1954                 if (err_msk & (1 << index))
1955                         return dma_tx_err_code_prio[i];
1956         }
1957         return -1;
1958 }
1959
1960 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
1961 {
1962         static const u8 sipc_rx_err_code_prio[] = {
1963                 SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
1964                 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
1965                 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
1966                 SIPC_RX_WRSETUP_LEN_ODD_ERR,
1967                 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
1968                 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
1969                 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
1970                 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
1971                 SIPC_RX_SATA_UNEXP_FIS_ERR,
1972                 SIPC_RX_WRSETUP_ESTATUS_ERR,
1973                 SIPC_RX_DATA_UNDERFLOW_ERR,
1974         };
1975         int index, i;
1976
1977         for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
1978                 index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
1979                 err_msk = err_msk & SIPC_RX_ERR_MSK;
1980                 if (err_msk & (1 << (index + 0x10)))
1981                         return sipc_rx_err_code_prio[i];
1982         }
1983         return -1;
1984 }
1985
1986 static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
1987 {
1988         static const u8 dma_rx_err_code_prio[] = {
1989                 DMA_RX_UNKNOWN_FRM_ERR,
1990                 DMA_RX_DATA_LEN_OVERFLOW,
1991                 DMA_RX_DATA_LEN_UNDERFLOW,
1992                 DMA_RX_DATA_OFFSET_ERR,
1993                 RESERVED10,
1994                 DMA_RX_SATA_FRAME_TYPE_ERR,
1995                 DMA_RX_RESP_BUF_OVERFLOW,
1996                 DMA_RX_UNEXP_RETRANS_RESP_ERR,
1997                 DMA_RX_UNEXP_NORM_RESP_ERR,
1998                 DMA_RX_UNEXP_RDFRAME_ERR,
1999                 DMA_RX_PIO_DATA_LEN_ERR,
2000                 DMA_RX_RDSETUP_STATUS_ERR,
2001                 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
2002                 DMA_RX_RDSETUP_STATUS_BSY_ERR,
2003                 DMA_RX_RDSETUP_LEN_ODD_ERR,
2004                 DMA_RX_RDSETUP_LEN_ZERO_ERR,
2005                 DMA_RX_RDSETUP_LEN_OVER_ERR,
2006                 DMA_RX_RDSETUP_OFFSET_ERR,
2007                 DMA_RX_RDSETUP_ACTIVE_ERR,
2008                 DMA_RX_RDSETUP_ESTATUS_ERR,
2009                 DMA_RX_RAM_ECC_ERR,
2010                 DMA_RX_DIF_CRC_ERR,
2011                 DMA_RX_DIF_APP_ERR,
2012                 DMA_RX_DIF_RPP_ERR,
2013                 DMA_RX_DATA_SGL_OVERFLOW,
2014                 DMA_RX_DIF_SGL_OVERFLOW,
2015         };
2016         int index, i;
2017
2018         for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
2019                 index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
2020                 if (err_msk & (1 << index))
2021                         return dma_rx_err_code_prio[i];
2022         }
2023         return -1;
2024 }
2025
2026 /* by default, task resp is complete */
2027 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
2028                            struct sas_task *task,
2029                            struct hisi_sas_slot *slot,
2030                            int err_phase)
2031 {
2032         struct task_status_struct *ts = &task->task_status;
2033         struct hisi_sas_err_record_v2 *err_record =
2034                         hisi_sas_status_buf_addr_mem(slot);
2035         u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
2036         u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
2037         u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
2038         u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
2039         u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
2040         int error = -1;
2041
2042         if (err_phase == 1) {
2043                 /* error in TX phase, the priority of error is: DW2 > DW0 */
2044                 error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
2045                 if (error == -1)
2046                         error = parse_trans_tx_err_code_v2_hw(
2047                                         trans_tx_fail_type);
2048         } else if (err_phase == 2) {
2049                 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
2050                 error = parse_trans_rx_err_code_v2_hw(
2051                                         trans_rx_fail_type);
2052                 if (error == -1) {
2053                         error = parse_dma_rx_err_code_v2_hw(
2054                                         dma_rx_err_type);
2055                         if (error == -1)
2056                                 error = parse_sipc_rx_err_code_v2_hw(
2057                                                 sipc_rx_err_type);
2058                 }
2059         }
2060
2061         switch (task->task_proto) {
2062         case SAS_PROTOCOL_SSP:
2063         {
2064                 switch (error) {
2065                 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2066                 {
2067                         ts->stat = SAS_OPEN_REJECT;
2068                         ts->open_rej_reason = SAS_OREJ_NO_DEST;
2069                         break;
2070                 }
2071                 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2072                 {
2073                         ts->stat = SAS_OPEN_REJECT;
2074                         ts->open_rej_reason = SAS_OREJ_EPROTO;
2075                         break;
2076                 }
2077                 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2078                 {
2079                         ts->stat = SAS_OPEN_REJECT;
2080                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2081                         break;
2082                 }
2083                 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2084                 {
2085                         ts->stat = SAS_OPEN_REJECT;
2086                         ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2087                         break;
2088                 }
2089                 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2090                 {
2091                         ts->stat = SAS_OPEN_REJECT;
2092                         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2093                         break;
2094                 }
2095                 case DMA_RX_UNEXP_NORM_RESP_ERR:
2096                 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2097                 case DMA_RX_RESP_BUF_OVERFLOW:
2098                 {
2099                         ts->stat = SAS_OPEN_REJECT;
2100                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2101                         break;
2102                 }
2103                 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2104                 {
2105                         /* not sure */
2106                         ts->stat = SAS_DEV_NO_RESPONSE;
2107                         break;
2108                 }
2109                 case DMA_RX_DATA_LEN_OVERFLOW:
2110                 {
2111                         ts->stat = SAS_DATA_OVERRUN;
2112                         ts->residual = 0;
2113                         break;
2114                 }
2115                 case DMA_RX_DATA_LEN_UNDERFLOW:
2116                 {
2117                         ts->residual = trans_tx_fail_type;
2118                         ts->stat = SAS_DATA_UNDERRUN;
2119                         break;
2120                 }
2121                 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2122                 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2123                 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2124                 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2125                 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2126                 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2127                 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2128                 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2129                 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2130                 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2131                 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2132                 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2133                 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2134                 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2135                 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2136                 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2137                 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
2138                 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2139                 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2140                 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
2141                 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
2142                 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2143                 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2144                 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2145                 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2146                 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2147                 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2148                 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2149                 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2150                 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2151                 case TRANS_TX_ERR_FRAME_TXED:
2152                 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2153                 case TRANS_RX_ERR_WITH_DATA_LEN0:
2154                 case TRANS_RX_ERR_WITH_BAD_HASH:
2155                 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2156                 case TRANS_RX_SSP_FRM_LEN_ERR:
2157                 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2158                 case DMA_TX_DATA_SGL_OVERFLOW:
2159                 case DMA_TX_UNEXP_XFER_ERR:
2160                 case DMA_TX_UNEXP_RETRANS_ERR:
2161                 case DMA_TX_XFER_LEN_OVERFLOW:
2162                 case DMA_TX_XFER_OFFSET_ERR:
2163                 case SIPC_RX_DATA_UNDERFLOW_ERR:
2164                 case DMA_RX_DATA_SGL_OVERFLOW:
2165                 case DMA_RX_DATA_OFFSET_ERR:
2166                 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2167                 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2168                 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2169                 case DMA_RX_SATA_FRAME_TYPE_ERR:
2170                 case DMA_RX_UNKNOWN_FRM_ERR:
2171                 {
2172                         /* This will request a retry */
2173                         ts->stat = SAS_QUEUE_FULL;
2174                         slot->abort = 1;
2175                         break;
2176                 }
2177                 default:
2178                         break;
2179                 }
2180         }
2181                 break;
2182         case SAS_PROTOCOL_SMP:
2183                 ts->stat = SAM_STAT_CHECK_CONDITION;
2184                 break;
2185
2186         case SAS_PROTOCOL_SATA:
2187         case SAS_PROTOCOL_STP:
2188         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2189         {
2190                 switch (error) {
2191                 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2192                 {
2193                         ts->stat = SAS_OPEN_REJECT;
2194                         ts->open_rej_reason = SAS_OREJ_NO_DEST;
2195                         break;
2196                 }
2197                 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2198                 {
2199                         ts->resp = SAS_TASK_UNDELIVERED;
2200                         ts->stat = SAS_DEV_NO_RESPONSE;
2201                         break;
2202                 }
2203                 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2204                 {
2205                         ts->stat = SAS_OPEN_REJECT;
2206                         ts->open_rej_reason = SAS_OREJ_EPROTO;
2207                         break;
2208                 }
2209                 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2210                 {
2211                         ts->stat = SAS_OPEN_REJECT;
2212                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2213                         break;
2214                 }
2215                 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2216                 {
2217                         ts->stat = SAS_OPEN_REJECT;
2218                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2219                         break;
2220                 }
2221                 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2222                 {
2223                         ts->stat = SAS_OPEN_REJECT;
2224                         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2225                         break;
2226                 }
2227                 case DMA_RX_RESP_BUF_OVERFLOW:
2228                 case DMA_RX_UNEXP_NORM_RESP_ERR:
2229                 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2230                 {
2231                         ts->stat = SAS_OPEN_REJECT;
2232                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2233                         break;
2234                 }
2235                 case DMA_RX_DATA_LEN_OVERFLOW:
2236                 {
2237                         ts->stat = SAS_DATA_OVERRUN;
2238                         ts->residual = 0;
2239                         break;
2240                 }
2241                 case DMA_RX_DATA_LEN_UNDERFLOW:
2242                 {
2243                         ts->residual = trans_tx_fail_type;
2244                         ts->stat = SAS_DATA_UNDERRUN;
2245                         break;
2246                 }
2247                 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2248                 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2249                 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2250                 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2251                 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2252                 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2253                 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2254                 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2255                 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2256                 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2257                 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2258                 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2259                 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2260                 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2261                 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2262                 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2263                 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2264                 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2265                 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
2266                 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
2267                 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2268                 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2269                 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
2270                 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
2271                 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
2272                 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
2273                 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2274                 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2275                 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2276                 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2277                 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2278                 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2279                 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2280                 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2281                 case TRANS_RX_ERR_WITH_DATA_LEN0:
2282                 case TRANS_RX_ERR_WITH_BAD_HASH:
2283                 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2284                 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2285                 case DMA_TX_DATA_SGL_OVERFLOW:
2286                 case DMA_TX_UNEXP_XFER_ERR:
2287                 case DMA_TX_UNEXP_RETRANS_ERR:
2288                 case DMA_TX_XFER_LEN_OVERFLOW:
2289                 case DMA_TX_XFER_OFFSET_ERR:
2290                 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
2291                 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
2292                 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
2293                 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
2294                 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
2295                 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
2296                 case SIPC_RX_SATA_UNEXP_FIS_ERR:
2297                 case DMA_RX_DATA_SGL_OVERFLOW:
2298                 case DMA_RX_DATA_OFFSET_ERR:
2299                 case DMA_RX_SATA_FRAME_TYPE_ERR:
2300                 case DMA_RX_UNEXP_RDFRAME_ERR:
2301                 case DMA_RX_PIO_DATA_LEN_ERR:
2302                 case DMA_RX_RDSETUP_STATUS_ERR:
2303                 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
2304                 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
2305                 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2306                 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2307                 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2308                 case DMA_RX_RDSETUP_OFFSET_ERR:
2309                 case DMA_RX_RDSETUP_ACTIVE_ERR:
2310                 case DMA_RX_RDSETUP_ESTATUS_ERR:
2311                 case DMA_RX_UNKNOWN_FRM_ERR:
2312                 case TRANS_RX_SSP_FRM_LEN_ERR:
2313                 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
2314                 {
2315                         slot->abort = 1;
2316                         ts->stat = SAS_PHY_DOWN;
2317                         break;
2318                 }
2319                 default:
2320                 {
2321                         ts->stat = SAS_PROTO_RESPONSE;
2322                         break;
2323                 }
2324                 }
2325                 hisi_sas_sata_done(task, slot);
2326         }
2327                 break;
2328         default:
2329                 break;
2330         }
2331 }
2332
2333 static int
2334 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
2335 {
2336         struct sas_task *task = slot->task;
2337         struct hisi_sas_device *sas_dev;
2338         struct device *dev = hisi_hba->dev;
2339         struct task_status_struct *ts;
2340         struct domain_device *device;
2341         struct sas_ha_struct *ha;
2342         enum exec_status sts;
2343         struct hisi_sas_complete_v2_hdr *complete_queue =
2344                         hisi_hba->complete_hdr[slot->cmplt_queue];
2345         struct hisi_sas_complete_v2_hdr *complete_hdr =
2346                         &complete_queue[slot->cmplt_queue_slot];
2347         unsigned long flags;
2348         bool is_internal = slot->is_internal;
2349
2350         if (unlikely(!task || !task->lldd_task || !task->dev))
2351                 return -EINVAL;
2352
2353         ts = &task->task_status;
2354         device = task->dev;
2355         ha = device->port->ha;
2356         sas_dev = device->lldd_dev;
2357
2358         spin_lock_irqsave(&task->task_state_lock, flags);
2359         task->task_state_flags &=
2360                 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2361         spin_unlock_irqrestore(&task->task_state_lock, flags);
2362
2363         memset(ts, 0, sizeof(*ts));
2364         ts->resp = SAS_TASK_COMPLETE;
2365
2366         if (unlikely(!sas_dev)) {
2367                 dev_dbg(dev, "slot complete: port has no device\n");
2368                 ts->stat = SAS_PHY_DOWN;
2369                 goto out;
2370         }
2371
2372         /* Use SAS+TMF status codes */
2373         switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
2374                         >> CMPLT_HDR_ABORT_STAT_OFF) {
2375         case STAT_IO_ABORTED:
2376                 /* this io has been aborted by abort command */
2377                 ts->stat = SAS_ABORTED_TASK;
2378                 goto out;
2379         case STAT_IO_COMPLETE:
2380                 /* internal abort command complete */
2381                 ts->stat = TMF_RESP_FUNC_SUCC;
2382                 del_timer(&slot->internal_abort_timer);
2383                 goto out;
2384         case STAT_IO_NO_DEVICE:
2385                 ts->stat = TMF_RESP_FUNC_COMPLETE;
2386                 del_timer(&slot->internal_abort_timer);
2387                 goto out;
2388         case STAT_IO_NOT_VALID:
2389                 /* abort single io, controller don't find
2390                  * the io need to abort
2391                  */
2392                 ts->stat = TMF_RESP_FUNC_FAILED;
2393                 del_timer(&slot->internal_abort_timer);
2394                 goto out;
2395         default:
2396                 break;
2397         }
2398
2399         if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
2400                 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2401                 u32 err_phase = (complete_hdr->dw0 & CMPLT_HDR_ERR_PHASE_MSK)
2402                                 >> CMPLT_HDR_ERR_PHASE_OFF;
2403                 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2404
2405                 /* Analyse error happens on which phase TX or RX */
2406                 if (ERR_ON_TX_PHASE(err_phase))
2407                         slot_err_v2_hw(hisi_hba, task, slot, 1);
2408                 else if (ERR_ON_RX_PHASE(err_phase))
2409                         slot_err_v2_hw(hisi_hba, task, slot, 2);
2410
2411                 if (ts->stat != SAS_DATA_UNDERRUN)
2412                         dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d "
2413                                 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
2414                                 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
2415                                 slot->idx, task, sas_dev->device_id,
2416                                 complete_hdr->dw0, complete_hdr->dw1,
2417                                 complete_hdr->act, complete_hdr->dw3,
2418                                 error_info[0], error_info[1],
2419                                 error_info[2], error_info[3]);
2420
2421                 if (unlikely(slot->abort))
2422                         return ts->stat;
2423                 goto out;
2424         }
2425
2426         switch (task->task_proto) {
2427         case SAS_PROTOCOL_SSP:
2428         {
2429                 struct hisi_sas_status_buffer *status_buffer =
2430                                 hisi_sas_status_buf_addr_mem(slot);
2431                 struct ssp_response_iu *iu = (struct ssp_response_iu *)
2432                                 &status_buffer->iu[0];
2433
2434                 sas_ssp_task_response(dev, task, iu);
2435                 break;
2436         }
2437         case SAS_PROTOCOL_SMP:
2438         {
2439                 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2440                 void *to;
2441
2442                 ts->stat = SAM_STAT_GOOD;
2443                 to = kmap_atomic(sg_page(sg_resp));
2444
2445                 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
2446                              DMA_FROM_DEVICE);
2447                 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2448                              DMA_TO_DEVICE);
2449                 memcpy(to + sg_resp->offset,
2450                        hisi_sas_status_buf_addr_mem(slot) +
2451                        sizeof(struct hisi_sas_err_record),
2452                        sg_dma_len(sg_resp));
2453                 kunmap_atomic(to);
2454                 break;
2455         }
2456         case SAS_PROTOCOL_SATA:
2457         case SAS_PROTOCOL_STP:
2458         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2459         {
2460                 ts->stat = SAM_STAT_GOOD;
2461                 hisi_sas_sata_done(task, slot);
2462                 break;
2463         }
2464         default:
2465                 ts->stat = SAM_STAT_CHECK_CONDITION;
2466                 break;
2467         }
2468
2469         if (!slot->port->port_attached) {
2470                 dev_warn(dev, "slot complete: port %d has removed\n",
2471                         slot->port->sas_port.id);
2472                 ts->stat = SAS_PHY_DOWN;
2473         }
2474
2475 out:
2476         hisi_sas_slot_task_free(hisi_hba, task, slot);
2477         sts = ts->stat;
2478         spin_lock_irqsave(&task->task_state_lock, flags);
2479         if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
2480                 spin_unlock_irqrestore(&task->task_state_lock, flags);
2481                 dev_info(dev, "slot complete: task(%p) aborted\n", task);
2482                 return SAS_ABORTED_TASK;
2483         }
2484         task->task_state_flags |= SAS_TASK_STATE_DONE;
2485         spin_unlock_irqrestore(&task->task_state_lock, flags);
2486
2487         if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
2488                 spin_lock_irqsave(&device->done_lock, flags);
2489                 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
2490                         spin_unlock_irqrestore(&device->done_lock, flags);
2491                         dev_info(dev, "slot complete: task(%p) ignored\n ",
2492                                  task);
2493                         return sts;
2494                 }
2495                 spin_unlock_irqrestore(&device->done_lock, flags);
2496         }
2497
2498         if (task->task_done)
2499                 task->task_done(task);
2500
2501         return sts;
2502 }
2503
2504 static void prep_ata_v2_hw(struct hisi_hba *hisi_hba,
2505                           struct hisi_sas_slot *slot)
2506 {
2507         struct sas_task *task = slot->task;
2508         struct domain_device *device = task->dev;
2509         struct domain_device *parent_dev = device->parent;
2510         struct hisi_sas_device *sas_dev = device->lldd_dev;
2511         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2512         struct asd_sas_port *sas_port = device->port;
2513         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
2514         u8 *buf_cmd;
2515         int has_data = 0, hdr_tag = 0;
2516         u32 dw1 = 0, dw2 = 0;
2517
2518         /* create header */
2519         /* dw0 */
2520         hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
2521         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
2522                 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
2523         else
2524                 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
2525
2526         /* dw1 */
2527         switch (task->data_dir) {
2528         case DMA_TO_DEVICE:
2529                 has_data = 1;
2530                 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
2531                 break;
2532         case DMA_FROM_DEVICE:
2533                 has_data = 1;
2534                 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
2535                 break;
2536         default:
2537                 dw1 &= ~CMD_HDR_DIR_MSK;
2538         }
2539
2540         if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
2541                         (task->ata_task.fis.control & ATA_SRST))
2542                 dw1 |= 1 << CMD_HDR_RESET_OFF;
2543
2544         dw1 |= (hisi_sas_get_ata_protocol(
2545                 &task->ata_task.fis, task->data_dir))
2546                 << CMD_HDR_FRAME_TYPE_OFF;
2547         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
2548         hdr->dw1 = cpu_to_le32(dw1);
2549
2550         /* dw2 */
2551         if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
2552                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
2553                 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
2554         }
2555
2556         dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
2557                         2 << CMD_HDR_SG_MOD_OFF;
2558         hdr->dw2 = cpu_to_le32(dw2);
2559
2560         /* dw3 */
2561         hdr->transfer_tags = cpu_to_le32(slot->idx);
2562
2563         if (has_data)
2564                 prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
2565                                         slot->n_elem);
2566
2567         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
2568         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
2569         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
2570
2571         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
2572
2573         if (likely(!task->ata_task.device_control_reg_update))
2574                 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
2575         /* fill in command FIS */
2576         memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
2577 }
2578
2579 static void hisi_sas_internal_abort_quirk_timeout(struct timer_list *t)
2580 {
2581         struct hisi_sas_slot *slot = from_timer(slot, t, internal_abort_timer);
2582         struct hisi_sas_port *port = slot->port;
2583         struct asd_sas_port *asd_sas_port;
2584         struct asd_sas_phy *sas_phy;
2585
2586         if (!port)
2587                 return;
2588
2589         asd_sas_port = &port->sas_port;
2590
2591         /* Kick the hardware - send break command */
2592         list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
2593                 struct hisi_sas_phy *phy = sas_phy->lldd_phy;
2594                 struct hisi_hba *hisi_hba = phy->hisi_hba;
2595                 int phy_no = sas_phy->id;
2596                 u32 link_dfx2;
2597
2598                 link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
2599                 if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
2600                     (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
2601                         u32 txid_auto;
2602
2603                         txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
2604                                                         TXID_AUTO);
2605                         txid_auto |= TXID_AUTO_CTB_MSK;
2606                         hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2607                                              txid_auto);
2608                         return;
2609                 }
2610         }
2611 }
2612
2613 static void prep_abort_v2_hw(struct hisi_hba *hisi_hba,
2614                 struct hisi_sas_slot *slot,
2615                 int device_id, int abort_flag, int tag_to_abort)
2616 {
2617         struct sas_task *task = slot->task;
2618         struct domain_device *dev = task->dev;
2619         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2620         struct hisi_sas_port *port = slot->port;
2621         struct timer_list *timer = &slot->internal_abort_timer;
2622
2623         /* setup the quirk timer */
2624         timer_setup(timer, hisi_sas_internal_abort_quirk_timeout, 0);
2625         /* Set the timeout to 10ms less than internal abort timeout */
2626         mod_timer(timer, jiffies + msecs_to_jiffies(100));
2627
2628         /* dw0 */
2629         hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
2630                                (port->id << CMD_HDR_PORT_OFF) |
2631                                (dev_is_sata(dev) <<
2632                                 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
2633                                (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
2634
2635         /* dw1 */
2636         hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
2637
2638         /* dw7 */
2639         hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
2640         hdr->transfer_tags = cpu_to_le32(slot->idx);
2641 }
2642
2643 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2644 {
2645         int i, res = IRQ_HANDLED;
2646         u32 port_id, link_rate;
2647         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2648         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2649         struct device *dev = hisi_hba->dev;
2650         u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
2651         struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
2652
2653         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
2654
2655         if (is_sata_phy_v2_hw(hisi_hba, phy_no))
2656                 goto end;
2657
2658         if (phy_no == 8) {
2659                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2660
2661                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2662                           PORT_STATE_PHY8_PORT_NUM_OFF;
2663                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2664                             PORT_STATE_PHY8_CONN_RATE_OFF;
2665         } else {
2666                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2667                 port_id = (port_id >> (4 * phy_no)) & 0xf;
2668                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2669                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2670         }
2671
2672         if (port_id == 0xf) {
2673                 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
2674                 res = IRQ_NONE;
2675                 goto end;
2676         }
2677
2678         for (i = 0; i < 6; i++) {
2679                 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
2680                                                RX_IDAF_DWORD0 + (i * 4));
2681                 frame_rcvd[i] = __swab32(idaf);
2682         }
2683
2684         sas_phy->linkrate = link_rate;
2685         sas_phy->oob_mode = SAS_OOB_MODE;
2686         memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
2687         dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2688         phy->port_id = port_id;
2689         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2690         phy->phy_type |= PORT_TYPE_SAS;
2691         phy->phy_attached = 1;
2692         phy->identify.device_type = id->dev_type;
2693         phy->frame_rcvd_size =  sizeof(struct sas_identify_frame);
2694         if (phy->identify.device_type == SAS_END_DEVICE)
2695                 phy->identify.target_port_protocols =
2696                         SAS_PROTOCOL_SSP;
2697         else if (phy->identify.device_type != SAS_PHY_UNUSED) {
2698                 phy->identify.target_port_protocols =
2699                         SAS_PROTOCOL_SMP;
2700                 if (!timer_pending(&hisi_hba->timer))
2701                         set_link_timer_quirk(hisi_hba);
2702         }
2703         hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
2704
2705 end:
2706         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2707                              CHL_INT0_SL_PHY_ENABLE_MSK);
2708         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
2709
2710         return res;
2711 }
2712
2713 static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
2714 {
2715         u32 port_state;
2716
2717         port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2718         if (port_state & 0x1ff)
2719                 return true;
2720
2721         return false;
2722 }
2723
2724 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2725 {
2726         u32 phy_state, sl_ctrl, txid_auto;
2727         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2728         struct hisi_sas_port *port = phy->port;
2729         struct device *dev = hisi_hba->dev;
2730
2731         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
2732
2733         phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2734         dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
2735         hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
2736
2737         sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
2738         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
2739                              sl_ctrl & ~SL_CONTROL_CTA_MSK);
2740         if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
2741                 if (!check_any_wideports_v2_hw(hisi_hba) &&
2742                                 timer_pending(&hisi_hba->timer))
2743                         del_timer(&hisi_hba->timer);
2744
2745         txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
2746         hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2747                              txid_auto | TXID_AUTO_CT3_MSK);
2748
2749         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
2750         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
2751
2752         return IRQ_HANDLED;
2753 }
2754
2755 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
2756 {
2757         struct hisi_hba *hisi_hba = p;
2758         u32 irq_msk;
2759         int phy_no = 0;
2760         irqreturn_t res = IRQ_NONE;
2761
2762         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
2763                    >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
2764         while (irq_msk) {
2765                 if (irq_msk  & 1) {
2766                         u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
2767                                             CHL_INT0);
2768
2769                         switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
2770                                         CHL_INT0_SL_PHY_ENABLE_MSK)) {
2771
2772                         case CHL_INT0_SL_PHY_ENABLE_MSK:
2773                                 /* phy up */
2774                                 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2775                                     IRQ_HANDLED)
2776                                         res = IRQ_HANDLED;
2777                                 break;
2778
2779                         case CHL_INT0_NOT_RDY_MSK:
2780                                 /* phy down */
2781                                 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2782                                     IRQ_HANDLED)
2783                                         res = IRQ_HANDLED;
2784                                 break;
2785
2786                         case (CHL_INT0_NOT_RDY_MSK |
2787                                         CHL_INT0_SL_PHY_ENABLE_MSK):
2788                                 reg_value = hisi_sas_read32(hisi_hba,
2789                                                 PHY_STATE);
2790                                 if (reg_value & BIT(phy_no)) {
2791                                         /* phy up */
2792                                         if (phy_up_v2_hw(phy_no, hisi_hba) ==
2793                                             IRQ_HANDLED)
2794                                                 res = IRQ_HANDLED;
2795                                 } else {
2796                                         /* phy down */
2797                                         if (phy_down_v2_hw(phy_no, hisi_hba) ==
2798                                             IRQ_HANDLED)
2799                                                 res = IRQ_HANDLED;
2800                                 }
2801                                 break;
2802
2803                         default:
2804                                 break;
2805                         }
2806
2807                 }
2808                 irq_msk >>= 1;
2809                 phy_no++;
2810         }
2811
2812         return res;
2813 }
2814
2815 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2816 {
2817         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2818         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2819         struct sas_ha_struct *sas_ha = &hisi_hba->sha;
2820         u32 bcast_status;
2821
2822         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
2823         bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
2824         if (bcast_status & RX_BCAST_CHG_MSK)
2825                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2826         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2827                              CHL_INT0_SL_RX_BCST_ACK_MSK);
2828         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
2829 }
2830
2831 static const struct hisi_sas_hw_error port_ecc_axi_error[] = {
2832         {
2833                 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_ERR_OFF),
2834                 .msg = "dmac_tx_ecc_bad_err",
2835         },
2836         {
2837                 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_ERR_OFF),
2838                 .msg = "dmac_rx_ecc_bad_err",
2839         },
2840         {
2841                 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
2842                 .msg = "dma_tx_axi_wr_err",
2843         },
2844         {
2845                 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
2846                 .msg = "dma_tx_axi_rd_err",
2847         },
2848         {
2849                 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
2850                 .msg = "dma_rx_axi_wr_err",
2851         },
2852         {
2853                 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
2854                 .msg = "dma_rx_axi_rd_err",
2855         },
2856 };
2857
2858 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
2859 {
2860         struct hisi_hba *hisi_hba = p;
2861         struct device *dev = hisi_hba->dev;
2862         u32 ent_msk, ent_tmp, irq_msk;
2863         int phy_no = 0;
2864
2865         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2866         ent_tmp = ent_msk;
2867         ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
2868         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
2869
2870         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
2871                         HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
2872
2873         while (irq_msk) {
2874                 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2875                                                      CHL_INT0);
2876                 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2877                                                      CHL_INT1);
2878                 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2879                                                      CHL_INT2);
2880
2881                 if ((irq_msk & (1 << phy_no)) && irq_value1) {
2882                         int i;
2883
2884                         for (i = 0; i < ARRAY_SIZE(port_ecc_axi_error); i++) {
2885                                 const struct hisi_sas_hw_error *error =
2886                                                 &port_ecc_axi_error[i];
2887
2888                                 if (!(irq_value1 & error->irq_msk))
2889                                         continue;
2890
2891                                 dev_warn(dev, "%s error (phy%d 0x%x) found!\n",
2892                                         error->msg, phy_no, irq_value1);
2893                                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2894                         }
2895
2896                         hisi_sas_phy_write32(hisi_hba, phy_no,
2897                                              CHL_INT1, irq_value1);
2898                 }
2899
2900                 if ((irq_msk & (1 << phy_no)) && irq_value2) {
2901                         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2902
2903                         if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
2904                                 dev_warn(dev, "phy%d identify timeout\n",
2905                                                 phy_no);
2906                                 hisi_sas_notify_phy_event(phy,
2907                                                 HISI_PHYE_LINK_RESET);
2908                         }
2909
2910                         hisi_sas_phy_write32(hisi_hba, phy_no,
2911                                                  CHL_INT2, irq_value2);
2912                 }
2913
2914                 if ((irq_msk & (1 << phy_no)) && irq_value0) {
2915                         if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2916                                 phy_bcast_v2_hw(phy_no, hisi_hba);
2917
2918                         hisi_sas_phy_write32(hisi_hba, phy_no,
2919                                         CHL_INT0, irq_value0
2920                                         & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2921                                         & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2922                                         & (~CHL_INT0_NOT_RDY_MSK));
2923                 }
2924                 irq_msk &= ~(1 << phy_no);
2925                 phy_no++;
2926         }
2927
2928         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2929
2930         return IRQ_HANDLED;
2931 }
2932
2933 static void
2934 one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
2935 {
2936         struct device *dev = hisi_hba->dev;
2937         const struct hisi_sas_hw_error *ecc_error;
2938         u32 val;
2939         int i;
2940
2941         for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) {
2942                 ecc_error = &one_bit_ecc_errors[i];
2943                 if (irq_value & ecc_error->irq_msk) {
2944                         val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2945                         val &= ecc_error->msk;
2946                         val >>= ecc_error->shift;
2947                         dev_warn(dev, ecc_error->msg, val);
2948                 }
2949         }
2950 }
2951
2952 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
2953                 u32 irq_value)
2954 {
2955         struct device *dev = hisi_hba->dev;
2956         const struct hisi_sas_hw_error *ecc_error;
2957         u32 val;
2958         int i;
2959
2960         for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
2961                 ecc_error = &multi_bit_ecc_errors[i];
2962                 if (irq_value & ecc_error->irq_msk) {
2963                         val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2964                         val &= ecc_error->msk;
2965                         val >>= ecc_error->shift;
2966                         dev_err(dev, ecc_error->msg, irq_value, val);
2967                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2968                 }
2969         }
2970
2971         return;
2972 }
2973
2974 static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
2975 {
2976         struct hisi_hba *hisi_hba = p;
2977         u32 irq_value, irq_msk;
2978
2979         irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
2980         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
2981
2982         irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
2983         if (irq_value) {
2984                 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2985                 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2986         }
2987
2988         hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
2989         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
2990
2991         return IRQ_HANDLED;
2992 }
2993
2994 static const struct hisi_sas_hw_error axi_error[] = {
2995         { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
2996         { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
2997         { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
2998         { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
2999         { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
3000         { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
3001         { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
3002         { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
3003         {},
3004 };
3005
3006 static const struct hisi_sas_hw_error fifo_error[] = {
3007         { .msk = BIT(8),  .msg = "CQE_WINFO_FIFO" },
3008         { .msk = BIT(9),  .msg = "CQE_MSG_FIFIO" },
3009         { .msk = BIT(10), .msg = "GETDQE_FIFO" },
3010         { .msk = BIT(11), .msg = "CMDP_FIFO" },
3011         { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
3012         {},
3013 };
3014
3015 static const struct hisi_sas_hw_error fatal_axi_errors[] = {
3016         {
3017                 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
3018                 .msg = "write pointer and depth",
3019         },
3020         {
3021                 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
3022                 .msg = "iptt no match slot",
3023         },
3024         {
3025                 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
3026                 .msg = "read pointer and depth",
3027         },
3028         {
3029                 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
3030                 .reg = HGC_AXI_FIFO_ERR_INFO,
3031                 .sub = axi_error,
3032         },
3033         {
3034                 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
3035                 .reg = HGC_AXI_FIFO_ERR_INFO,
3036                 .sub = fifo_error,
3037         },
3038         {
3039                 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
3040                 .msg = "LM add/fetch list",
3041         },
3042         {
3043                 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
3044                 .msg = "SAS_HGC_ABT fetch LM list",
3045         },
3046 };
3047
3048 static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
3049 {
3050         struct hisi_hba *hisi_hba = p;
3051         u32 irq_value, irq_msk, err_value;
3052         struct device *dev = hisi_hba->dev;
3053         const struct hisi_sas_hw_error *axi_error;
3054         int i;
3055
3056         irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
3057         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
3058
3059         irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
3060
3061         for (i = 0; i < ARRAY_SIZE(fatal_axi_errors); i++) {
3062                 axi_error = &fatal_axi_errors[i];
3063                 if (!(irq_value & axi_error->irq_msk))
3064                         continue;
3065
3066                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3067                                  1 << axi_error->shift);
3068                 if (axi_error->sub) {
3069                         const struct hisi_sas_hw_error *sub = axi_error->sub;
3070
3071                         err_value = hisi_sas_read32(hisi_hba, axi_error->reg);
3072                         for (; sub->msk || sub->msg; sub++) {
3073                                 if (!(err_value & sub->msk))
3074                                         continue;
3075                                 dev_err(dev, "%s (0x%x) found!\n",
3076                                          sub->msg, irq_value);
3077                                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3078                         }
3079                 } else {
3080                         dev_err(dev, "%s (0x%x) found!\n",
3081                                  axi_error->msg, irq_value);
3082                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3083                 }
3084         }
3085
3086         if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
3087                 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
3088                 u32 dev_id = reg_val & ITCT_DEV_MSK;
3089                 struct hisi_sas_device *sas_dev = &hisi_hba->devices[dev_id];
3090
3091                 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
3092                 dev_dbg(dev, "clear ITCT ok\n");
3093                 complete(sas_dev->completion);
3094         }
3095
3096         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value);
3097         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
3098
3099         return IRQ_HANDLED;
3100 }
3101
3102 static void cq_tasklet_v2_hw(unsigned long val)
3103 {
3104         struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
3105         struct hisi_hba *hisi_hba = cq->hisi_hba;
3106         struct hisi_sas_slot *slot;
3107         struct hisi_sas_itct *itct;
3108         struct hisi_sas_complete_v2_hdr *complete_queue;
3109         u32 rd_point = cq->rd_point, wr_point, dev_id;
3110         int queue = cq->id;
3111
3112         if (unlikely(hisi_hba->reject_stp_links_msk))
3113                 phys_try_accept_stp_links_v2_hw(hisi_hba);
3114
3115         complete_queue = hisi_hba->complete_hdr[queue];
3116
3117         wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
3118                                    (0x14 * queue));
3119
3120         while (rd_point != wr_point) {
3121                 struct hisi_sas_complete_v2_hdr *complete_hdr;
3122                 int iptt;
3123
3124                 complete_hdr = &complete_queue[rd_point];
3125
3126                 /* Check for NCQ completion */
3127                 if (complete_hdr->act) {
3128                         u32 act_tmp = complete_hdr->act;
3129                         int ncq_tag_count = ffs(act_tmp);
3130
3131                         dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
3132                                  CMPLT_HDR_DEV_ID_OFF;
3133                         itct = &hisi_hba->itct[dev_id];
3134
3135                         /* The NCQ tags are held in the itct header */
3136                         while (ncq_tag_count) {
3137                                 __le64 *ncq_tag = &itct->qw4_15[0];
3138
3139                                 ncq_tag_count -= 1;
3140                                 iptt = (ncq_tag[ncq_tag_count / 5]
3141                                         >> (ncq_tag_count % 5) * 12) & 0xfff;
3142
3143                                 slot = &hisi_hba->slot_info[iptt];
3144                                 slot->cmplt_queue_slot = rd_point;
3145                                 slot->cmplt_queue = queue;
3146                                 slot_complete_v2_hw(hisi_hba, slot);
3147
3148                                 act_tmp &= ~(1 << ncq_tag_count);
3149                                 ncq_tag_count = ffs(act_tmp);
3150                         }
3151                 } else {
3152                         iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
3153                         slot = &hisi_hba->slot_info[iptt];
3154                         slot->cmplt_queue_slot = rd_point;
3155                         slot->cmplt_queue = queue;
3156                         slot_complete_v2_hw(hisi_hba, slot);
3157                 }
3158
3159                 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
3160                         rd_point = 0;
3161         }
3162
3163         /* update rd_point */
3164         cq->rd_point = rd_point;
3165         hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
3166 }
3167
3168 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
3169 {
3170         struct hisi_sas_cq *cq = p;
3171         struct hisi_hba *hisi_hba = cq->hisi_hba;
3172         int queue = cq->id;
3173
3174         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
3175
3176         tasklet_schedule(&cq->tasklet);
3177
3178         return IRQ_HANDLED;
3179 }
3180
3181 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
3182 {
3183         struct hisi_sas_phy *phy = p;
3184         struct hisi_hba *hisi_hba = phy->hisi_hba;
3185         struct asd_sas_phy *sas_phy = &phy->sas_phy;
3186         struct device *dev = hisi_hba->dev;
3187         struct  hisi_sas_initial_fis *initial_fis;
3188         struct dev_to_host_fis *fis;
3189         u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
3190         irqreturn_t res = IRQ_HANDLED;
3191         u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
3192         int phy_no, offset;
3193
3194         phy_no = sas_phy->id;
3195         initial_fis = &hisi_hba->initial_fis[phy_no];
3196         fis = &initial_fis->fis;
3197
3198         offset = 4 * (phy_no / 4);
3199         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
3200         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
3201                          ent_msk | 1 << ((phy_no % 4) * 8));
3202
3203         ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
3204         ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
3205                              (phy_no % 4)));
3206         ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
3207         if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
3208                 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
3209                 res = IRQ_NONE;
3210                 goto end;
3211         }
3212
3213         /* check ERR bit of Status Register */
3214         if (fis->status & ATA_ERR) {
3215                 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
3216                                 fis->status);
3217                 disable_phy_v2_hw(hisi_hba, phy_no);
3218                 enable_phy_v2_hw(hisi_hba, phy_no);
3219                 res = IRQ_NONE;
3220                 goto end;
3221         }
3222
3223         if (unlikely(phy_no == 8)) {
3224                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
3225
3226                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
3227                           PORT_STATE_PHY8_PORT_NUM_OFF;
3228                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
3229                             PORT_STATE_PHY8_CONN_RATE_OFF;
3230         } else {
3231                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
3232                 port_id = (port_id >> (4 * phy_no)) & 0xf;
3233                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
3234                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
3235         }
3236
3237         if (port_id == 0xf) {
3238                 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
3239                 res = IRQ_NONE;
3240                 goto end;
3241         }
3242
3243         sas_phy->linkrate = link_rate;
3244         hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
3245                                                 HARD_PHY_LINKRATE);
3246         phy->maximum_linkrate = hard_phy_linkrate & 0xf;
3247         phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
3248
3249         sas_phy->oob_mode = SATA_OOB_MODE;
3250         /* Make up some unique SAS address */
3251         attached_sas_addr[0] = 0x50;
3252         attached_sas_addr[6] = hisi_hba->shost->host_no;
3253         attached_sas_addr[7] = phy_no;
3254         memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
3255         memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
3256         dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
3257         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
3258         phy->port_id = port_id;
3259         phy->phy_type |= PORT_TYPE_SATA;
3260         phy->phy_attached = 1;
3261         phy->identify.device_type = SAS_SATA_DEV;
3262         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3263         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3264         hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
3265
3266 end:
3267         hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
3268         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
3269
3270         return res;
3271 }
3272
3273 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
3274         int_phy_updown_v2_hw,
3275         int_chnl_int_v2_hw,
3276 };
3277
3278 static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
3279         fatal_ecc_int_v2_hw,
3280         fatal_axi_int_v2_hw
3281 };
3282
3283 /**
3284  * There is a limitation in the hip06 chipset that we need
3285  * to map in all mbigen interrupts, even if they are not used.
3286  */
3287 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
3288 {
3289         struct platform_device *pdev = hisi_hba->platform_dev;
3290         struct device *dev = &pdev->dev;
3291         int irq, rc, irq_map[128];
3292         int i, phy_no, fatal_no, queue_no, k;
3293
3294         for (i = 0; i < 128; i++)
3295                 irq_map[i] = platform_get_irq(pdev, i);
3296
3297         for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
3298                 irq = irq_map[i + 1]; /* Phy up/down is irq1 */
3299                 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
3300                                       DRV_NAME " phy", hisi_hba);
3301                 if (rc) {
3302                         dev_err(dev, "irq init: could not request "
3303                                 "phy interrupt %d, rc=%d\n",
3304                                 irq, rc);
3305                         rc = -ENOENT;
3306                         goto free_phy_int_irqs;
3307                 }
3308         }
3309
3310         for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
3311                 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
3312
3313                 irq = irq_map[phy_no + 72];
3314                 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
3315                                       DRV_NAME " sata", phy);
3316                 if (rc) {
3317                         dev_err(dev, "irq init: could not request "
3318                                 "sata interrupt %d, rc=%d\n",
3319                                 irq, rc);
3320                         rc = -ENOENT;
3321                         goto free_sata_int_irqs;
3322                 }
3323         }
3324
3325         for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
3326                 irq = irq_map[fatal_no + 81];
3327                 rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
3328                                       DRV_NAME " fatal", hisi_hba);
3329                 if (rc) {
3330                         dev_err(dev,
3331                                 "irq init: could not request fatal interrupt %d, rc=%d\n",
3332                                 irq, rc);
3333                         rc = -ENOENT;
3334                         goto free_fatal_int_irqs;
3335                 }
3336         }
3337
3338         for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
3339                 struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
3340                 struct tasklet_struct *t = &cq->tasklet;
3341
3342                 irq = irq_map[queue_no + 96];
3343                 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
3344                                       DRV_NAME " cq", cq);
3345                 if (rc) {
3346                         dev_err(dev,
3347                                 "irq init: could not request cq interrupt %d, rc=%d\n",
3348                                 irq, rc);
3349                         rc = -ENOENT;
3350                         goto free_cq_int_irqs;
3351                 }
3352                 tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq);
3353         }
3354
3355         return 0;
3356
3357 free_cq_int_irqs:
3358         for (k = 0; k < queue_no; k++) {
3359                 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
3360
3361                 free_irq(irq_map[k + 96], cq);
3362                 tasklet_kill(&cq->tasklet);
3363         }
3364 free_fatal_int_irqs:
3365         for (k = 0; k < fatal_no; k++)
3366                 free_irq(irq_map[k + 81], hisi_hba);
3367 free_sata_int_irqs:
3368         for (k = 0; k < phy_no; k++) {
3369                 struct hisi_sas_phy *phy = &hisi_hba->phy[k];
3370
3371                 free_irq(irq_map[k + 72], phy);
3372         }
3373 free_phy_int_irqs:
3374         for (k = 0; k < i; k++)
3375                 free_irq(irq_map[k + 1], hisi_hba);
3376         return rc;
3377 }
3378
3379 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
3380 {
3381         int rc;
3382
3383         memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap));
3384
3385         rc = hw_init_v2_hw(hisi_hba);
3386         if (rc)
3387                 return rc;
3388
3389         rc = interrupt_init_v2_hw(hisi_hba);
3390         if (rc)
3391                 return rc;
3392
3393         return 0;
3394 }
3395
3396 static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
3397 {
3398         struct platform_device *pdev = hisi_hba->platform_dev;
3399         int i;
3400
3401         for (i = 0; i < hisi_hba->queue_count; i++)
3402                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
3403
3404         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
3405         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
3406         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
3407         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
3408
3409         for (i = 0; i < hisi_hba->n_phy; i++) {
3410                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
3411                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
3412         }
3413
3414         for (i = 0; i < 128; i++)
3415                 synchronize_irq(platform_get_irq(pdev, i));
3416 }
3417
3418
3419 static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba)
3420 {
3421         return hisi_sas_read32(hisi_hba, PHY_STATE);
3422 }
3423
3424 static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
3425 {
3426         struct device *dev = hisi_hba->dev;
3427         int rc, cnt;
3428
3429         interrupt_disable_v2_hw(hisi_hba);
3430         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
3431         hisi_sas_kill_tasklets(hisi_hba);
3432
3433         hisi_sas_stop_phys(hisi_hba);
3434
3435         mdelay(10);
3436
3437         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
3438
3439         /* wait until bus idle */
3440         cnt = 0;
3441         while (1) {
3442                 u32 status = hisi_sas_read32_relaxed(hisi_hba,
3443                                 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
3444
3445                 if (status == 0x3)
3446                         break;
3447
3448                 udelay(10);
3449                 if (cnt++ > 10) {
3450                         dev_err(dev, "wait axi bus state to idle timeout!\n");
3451                         return -1;
3452                 }
3453         }
3454
3455         hisi_sas_init_mem(hisi_hba);
3456
3457         rc = hw_init_v2_hw(hisi_hba);
3458         if (rc)
3459                 return rc;
3460
3461         phys_reject_stp_links_v2_hw(hisi_hba);
3462
3463         return 0;
3464 }
3465
3466 static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type,
3467                         u8 reg_index, u8 reg_count, u8 *write_data)
3468 {
3469         struct device *dev = hisi_hba->dev;
3470         int phy_no, count;
3471
3472         if (!hisi_hba->sgpio_regs)
3473                 return -EOPNOTSUPP;
3474
3475         switch (reg_type) {
3476         case SAS_GPIO_REG_TX:
3477                 count = reg_count * 4;
3478                 count = min(count, hisi_hba->n_phy);
3479
3480                 for (phy_no = 0; phy_no < count; phy_no++) {
3481                         /*
3482                          * GPIO_TX[n] register has the highest numbered drive
3483                          * of the four in the first byte and the lowest
3484                          * numbered drive in the fourth byte.
3485                          * See SFF-8485 Rev. 0.7 Table 24.
3486                          */
3487                         void __iomem  *reg_addr = hisi_hba->sgpio_regs +
3488                                         reg_index * 4 + phy_no;
3489                         int data_idx = phy_no + 3 - (phy_no % 4) * 2;
3490
3491                         writeb(write_data[data_idx], reg_addr);
3492                 }
3493
3494                 break;
3495         default:
3496                 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
3497                                 reg_type);
3498                 return -EINVAL;
3499         }
3500
3501         return 0;
3502 }
3503
3504 static const struct hisi_sas_hw hisi_sas_v2_hw = {
3505         .hw_init = hisi_sas_v2_init,
3506         .setup_itct = setup_itct_v2_hw,
3507         .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
3508         .alloc_dev = alloc_dev_quirk_v2_hw,
3509         .sl_notify = sl_notify_v2_hw,
3510         .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
3511         .clear_itct = clear_itct_v2_hw,
3512         .free_device = free_device_v2_hw,
3513         .prep_smp = prep_smp_v2_hw,
3514         .prep_ssp = prep_ssp_v2_hw,
3515         .prep_stp = prep_ata_v2_hw,
3516         .prep_abort = prep_abort_v2_hw,
3517         .get_free_slot = get_free_slot_v2_hw,
3518         .start_delivery = start_delivery_v2_hw,
3519         .slot_complete = slot_complete_v2_hw,
3520         .phys_init = phys_init_v2_hw,
3521         .phy_start = start_phy_v2_hw,
3522         .phy_disable = disable_phy_v2_hw,
3523         .phy_hard_reset = phy_hard_reset_v2_hw,
3524         .get_events = phy_get_events_v2_hw,
3525         .phy_set_linkrate = phy_set_linkrate_v2_hw,
3526         .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
3527         .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
3528         .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3529         .soft_reset = soft_reset_v2_hw,
3530         .get_phys_state = get_phys_state_v2_hw,
3531         .write_gpio = write_gpio_v2_hw,
3532 };
3533
3534 static int hisi_sas_v2_probe(struct platform_device *pdev)
3535 {
3536         /*
3537          * Check if we should defer the probe before we probe the
3538          * upper layer, as it's hard to defer later on.
3539          */
3540         int ret = platform_get_irq(pdev, 0);
3541
3542         if (ret < 0) {
3543                 if (ret != -EPROBE_DEFER)
3544                         dev_err(&pdev->dev, "cannot obtain irq\n");
3545                 return ret;
3546         }
3547
3548         return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
3549 }
3550
3551 static int hisi_sas_v2_remove(struct platform_device *pdev)
3552 {
3553         struct sas_ha_struct *sha = platform_get_drvdata(pdev);
3554         struct hisi_hba *hisi_hba = sha->lldd_ha;
3555
3556         hisi_sas_kill_tasklets(hisi_hba);
3557
3558         return hisi_sas_remove(pdev);
3559 }
3560
3561 static const struct of_device_id sas_v2_of_match[] = {
3562         { .compatible = "hisilicon,hip06-sas-v2",},
3563         { .compatible = "hisilicon,hip07-sas-v2",},
3564         {},
3565 };
3566 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
3567
3568 static const struct acpi_device_id sas_v2_acpi_match[] = {
3569         { "HISI0162", 0 },
3570         { }
3571 };
3572
3573 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
3574
3575 static struct platform_driver hisi_sas_v2_driver = {
3576         .probe = hisi_sas_v2_probe,
3577         .remove = hisi_sas_v2_remove,
3578         .driver = {
3579                 .name = DRV_NAME,
3580                 .of_match_table = sas_v2_of_match,
3581                 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
3582         },
3583 };
3584
3585 module_platform_driver(hisi_sas_v2_driver);
3586
3587 MODULE_LICENSE("GPL");
3588 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3589 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3590 MODULE_ALIAS("platform:" DRV_NAME);