drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

   1 /*
   2  * Copyright (c) 2016 Linaro Ltd.
   3  * Copyright (c) 2016 Hisilicon Limited.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  */
  11
  12 #include "hisi_sas.h"
  13 #define DRV_NAME "hisi_sas_v2_hw"
  14
  15 /* global registers need init*/
  16 #define DLVRY_QUEUE_ENABLE              0x0
  17 #define IOST_BASE_ADDR_LO               0x8
  18 #define IOST_BASE_ADDR_HI               0xc
  19 #define ITCT_BASE_ADDR_LO               0x10
  20 #define ITCT_BASE_ADDR_HI               0x14
  21 #define IO_BROKEN_MSG_ADDR_LO           0x18
  22 #define IO_BROKEN_MSG_ADDR_HI           0x1c
  23 #define PHY_CONTEXT                     0x20
  24 #define PHY_STATE                       0x24
  25 #define PHY_PORT_NUM_MA                 0x28
  26 #define PORT_STATE                      0x2c
  27 #define PORT_STATE_PHY8_PORT_NUM_OFF    16
  28 #define PORT_STATE_PHY8_PORT_NUM_MSK    (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
  29 #define PORT_STATE_PHY8_CONN_RATE_OFF   20
  30 #define PORT_STATE_PHY8_CONN_RATE_MSK   (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
  31 #define PHY_CONN_RATE                   0x30
  32 #define HGC_TRANS_TASK_CNT_LIMIT        0x38
  33 #define AXI_AHB_CLK_CFG                 0x3c
  34 #define ITCT_CLR                        0x44
  35 #define ITCT_CLR_EN_OFF                 16
  36 #define ITCT_CLR_EN_MSK                 (0x1 << ITCT_CLR_EN_OFF)
  37 #define ITCT_DEV_OFF                    0
  38 #define ITCT_DEV_MSK                    (0x7ff << ITCT_DEV_OFF)
  39 #define AXI_USER1                       0x48
  40 #define AXI_USER2                       0x4c
  41 #define IO_SATA_BROKEN_MSG_ADDR_LO      0x58
  42 #define IO_SATA_BROKEN_MSG_ADDR_HI      0x5c
  43 #define SATA_INITI_D2H_STORE_ADDR_LO    0x60
  44 #define SATA_INITI_D2H_STORE_ADDR_HI    0x64
  45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
  46 #define HGC_SAS_TXFAIL_RETRY_CTRL       0x88
  47 #define HGC_GET_ITV_TIME                0x90
  48 #define DEVICE_MSG_WORK_MODE            0x94
  49 #define OPENA_WT_CONTI_TIME             0x9c
  50 #define I_T_NEXUS_LOSS_TIME             0xa0
  51 #define MAX_CON_TIME_LIMIT_TIME         0xa4
  52 #define BUS_INACTIVE_LIMIT_TIME         0xa8
  53 #define REJECT_TO_OPEN_LIMIT_TIME       0xac
  54 #define CFG_AGING_TIME                  0xbc
  55 #define HGC_DFX_CFG2                    0xc0
  56 #define HGC_IOMB_PROC1_STATUS   0x104
  57 #define CFG_1US_TIMER_TRSH              0xcc
  58 #define HGC_LM_DFX_STATUS2              0x128
  59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF         0
  60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
  61                                          HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
  62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF         12
  63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
  64                                          HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
  65 #define HGC_CQE_ECC_ADDR                0x13c
  66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
  67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
  68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
  69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
  70 #define HGC_IOST_ECC_ADDR               0x140
  71 #define HGC_IOST_ECC_1B_ADDR_OFF        0
  72 #define HGC_IOST_ECC_1B_ADDR_MSK        (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
  73 #define HGC_IOST_ECC_MB_ADDR_OFF        16
  74 #define HGC_IOST_ECC_MB_ADDR_MSK        (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
  75 #define HGC_DQE_ECC_ADDR                0x144
  76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
  77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
  78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
  79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
  80 #define HGC_INVLD_DQE_INFO              0x148
  81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF   9
  82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK   (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
  83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF   18
  84 #define HGC_ITCT_ECC_ADDR               0x150
  85 #define HGC_ITCT_ECC_1B_ADDR_OFF                0
  86 #define HGC_ITCT_ECC_1B_ADDR_MSK                (0x3ff << \
  87                                                  HGC_ITCT_ECC_1B_ADDR_OFF)
  88 #define HGC_ITCT_ECC_MB_ADDR_OFF                16
  89 #define HGC_ITCT_ECC_MB_ADDR_MSK                (0x3ff << \
  90                                                  HGC_ITCT_ECC_MB_ADDR_OFF)
  91 #define HGC_AXI_FIFO_ERR_INFO   0x154
  92 #define AXI_ERR_INFO_OFF                0
  93 #define AXI_ERR_INFO_MSK                (0xff << AXI_ERR_INFO_OFF)
  94 #define FIFO_ERR_INFO_OFF               8
  95 #define FIFO_ERR_INFO_MSK               (0xff << FIFO_ERR_INFO_OFF)
  96 #define INT_COAL_EN                     0x19c
  97 #define OQ_INT_COAL_TIME                0x1a0
  98 #define OQ_INT_COAL_CNT                 0x1a4
  99 #define ENT_INT_COAL_TIME               0x1a8
 100 #define ENT_INT_COAL_CNT                0x1ac
 101 #define OQ_INT_SRC                      0x1b0
 102 #define OQ_INT_SRC_MSK                  0x1b4
 103 #define ENT_INT_SRC1                    0x1b8
 104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF    0
 105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
 106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF    8
 107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
 108 #define ENT_INT_SRC2                    0x1bc
 109 #define ENT_INT_SRC3                    0x1c0
 110 #define ENT_INT_SRC3_WP_DEPTH_OFF               8
 111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF      9
 112 #define ENT_INT_SRC3_RP_DEPTH_OFF               10
 113 #define ENT_INT_SRC3_AXI_OFF                    11
 114 #define ENT_INT_SRC3_FIFO_OFF                   12
 115 #define ENT_INT_SRC3_LM_OFF                             14
 116 #define ENT_INT_SRC3_ITC_INT_OFF        15
 117 #define ENT_INT_SRC3_ITC_INT_MSK        (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
 118 #define ENT_INT_SRC3_ABT_OFF            16
 119 #define ENT_INT_SRC_MSK1                0x1c4
 120 #define ENT_INT_SRC_MSK2                0x1c8
 121 #define ENT_INT_SRC_MSK3                0x1cc
 122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF  31
 123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK  (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
 124 #define SAS_ECC_INTR                    0x1e8
 125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF             0
 126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF             1
 127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF    2
 128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF    3
 129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF    4
 130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF    5
 131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF        6
 132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF        7
 133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF        8
 134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF        9
 135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF             10
 136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF             11
 137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF        12
 138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF        13
 139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF        14
 140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF        15
 141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF        16
 142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF        17
 143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF        18
 144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF        19
 145 #define SAS_ECC_INTR_MSK                0x1ec
 146 #define HGC_ERR_STAT_EN                 0x238
 147 #define CQE_SEND_CNT                    0x248
 148 #define DLVRY_Q_0_BASE_ADDR_LO          0x260
 149 #define DLVRY_Q_0_BASE_ADDR_HI          0x264
 150 #define DLVRY_Q_0_DEPTH                 0x268
 151 #define DLVRY_Q_0_WR_PTR                0x26c
 152 #define DLVRY_Q_0_RD_PTR                0x270
 153 #define HYPER_STREAM_ID_EN_CFG          0xc80
 154 #define OQ0_INT_SRC_MSK                 0xc90
 155 #define COMPL_Q_0_BASE_ADDR_LO          0x4e0
 156 #define COMPL_Q_0_BASE_ADDR_HI          0x4e4
 157 #define COMPL_Q_0_DEPTH                 0x4e8
 158 #define COMPL_Q_0_WR_PTR                0x4ec
 159 #define COMPL_Q_0_RD_PTR                0x4f0
 160 #define HGC_RXM_DFX_STATUS14    0xae8
 161 #define HGC_RXM_DFX_STATUS14_MEM0_OFF           0
 162 #define HGC_RXM_DFX_STATUS14_MEM0_MSK           (0x1ff << \
 163                                                  HGC_RXM_DFX_STATUS14_MEM0_OFF)
 164 #define HGC_RXM_DFX_STATUS14_MEM1_OFF           9
 165 #define HGC_RXM_DFX_STATUS14_MEM1_MSK           (0x1ff << \
 166                                                  HGC_RXM_DFX_STATUS14_MEM1_OFF)
 167 #define HGC_RXM_DFX_STATUS14_MEM2_OFF           18
 168 #define HGC_RXM_DFX_STATUS14_MEM2_MSK           (0x1ff << \
 169                                                  HGC_RXM_DFX_STATUS14_MEM2_OFF)
 170 #define HGC_RXM_DFX_STATUS15    0xaec
 171 #define HGC_RXM_DFX_STATUS15_MEM3_OFF           0
 172 #define HGC_RXM_DFX_STATUS15_MEM3_MSK           (0x1ff << \
 173                                                  HGC_RXM_DFX_STATUS15_MEM3_OFF)
 174 /* phy registers need init */
 175 #define PORT_BASE                       (0x2000)
 176
 177 #define PHY_CFG                         (PORT_BASE + 0x0)
 178 #define HARD_PHY_LINKRATE               (PORT_BASE + 0x4)
 179 #define PHY_CFG_ENA_OFF                 0
 180 #define PHY_CFG_ENA_MSK                 (0x1 << PHY_CFG_ENA_OFF)
 181 #define PHY_CFG_DC_OPT_OFF              2
 182 #define PHY_CFG_DC_OPT_MSK              (0x1 << PHY_CFG_DC_OPT_OFF)
 183 #define PROG_PHY_LINK_RATE              (PORT_BASE + 0x8)
 184 #define PROG_PHY_LINK_RATE_MAX_OFF      0
 185 #define PROG_PHY_LINK_RATE_MAX_MSK      (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
 186 #define PHY_CTRL                        (PORT_BASE + 0x14)
 187 #define PHY_CTRL_RESET_OFF              0
 188 #define PHY_CTRL_RESET_MSK              (0x1 << PHY_CTRL_RESET_OFF)
 189 #define SAS_PHY_CTRL                    (PORT_BASE + 0x20)
 190 #define SL_CFG                          (PORT_BASE + 0x84)
 191 #define PHY_PCN                         (PORT_BASE + 0x44)
 192 #define SL_TOUT_CFG                     (PORT_BASE + 0x8c)
 193 #define SL_CONTROL                      (PORT_BASE + 0x94)
 194 #define SL_CONTROL_NOTIFY_EN_OFF        0
 195 #define SL_CONTROL_NOTIFY_EN_MSK        (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
 196 #define SL_CONTROL_CTA_OFF              17
 197 #define SL_CONTROL_CTA_MSK              (0x1 << SL_CONTROL_CTA_OFF)
 198 #define RX_PRIMS_STATUS                 (PORT_BASE + 0x98)
 199 #define RX_BCAST_CHG_OFF                1
 200 #define RX_BCAST_CHG_MSK                (0x1 << RX_BCAST_CHG_OFF)
 201 #define TX_ID_DWORD0                    (PORT_BASE + 0x9c)
 202 #define TX_ID_DWORD1                    (PORT_BASE + 0xa0)
 203 #define TX_ID_DWORD2                    (PORT_BASE + 0xa4)
 204 #define TX_ID_DWORD3                    (PORT_BASE + 0xa8)
 205 #define TX_ID_DWORD4                    (PORT_BASE + 0xaC)
 206 #define TX_ID_DWORD5                    (PORT_BASE + 0xb0)
 207 #define TX_ID_DWORD6                    (PORT_BASE + 0xb4)
 208 #define TXID_AUTO                       (PORT_BASE + 0xb8)
 209 #define TXID_AUTO_CT3_OFF               1
 210 #define TXID_AUTO_CT3_MSK               (0x1 << TXID_AUTO_CT3_OFF)
 211 #define TXID_AUTO_CTB_OFF               11
 212 #define TXID_AUTO_CTB_MSK               (0x1 << TXID_AUTO_CTB_OFF)
 213 #define TX_HARDRST_OFF                  2
 214 #define TX_HARDRST_MSK                  (0x1 << TX_HARDRST_OFF)
 215 #define RX_IDAF_DWORD0                  (PORT_BASE + 0xc4)
 216 #define RX_IDAF_DWORD1                  (PORT_BASE + 0xc8)
 217 #define RX_IDAF_DWORD2                  (PORT_BASE + 0xcc)
 218 #define RX_IDAF_DWORD3                  (PORT_BASE + 0xd0)
 219 #define RX_IDAF_DWORD4                  (PORT_BASE + 0xd4)
 220 #define RX_IDAF_DWORD5                  (PORT_BASE + 0xd8)
 221 #define RX_IDAF_DWORD6                  (PORT_BASE + 0xdc)
 222 #define RXOP_CHECK_CFG_H                (PORT_BASE + 0xfc)
 223 #define CON_CONTROL                     (PORT_BASE + 0x118)
 224 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF        0
 225 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK        \
 226                 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
 227 #define DONE_RECEIVED_TIME              (PORT_BASE + 0x11c)
 228 #define CHL_INT0                        (PORT_BASE + 0x1b4)
 229 #define CHL_INT0_HOTPLUG_TOUT_OFF       0
 230 #define CHL_INT0_HOTPLUG_TOUT_MSK       (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
 231 #define CHL_INT0_SL_RX_BCST_ACK_OFF     1
 232 #define CHL_INT0_SL_RX_BCST_ACK_MSK     (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
 233 #define CHL_INT0_SL_PHY_ENABLE_OFF      2
 234 #define CHL_INT0_SL_PHY_ENABLE_MSK      (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
 235 #define CHL_INT0_NOT_RDY_OFF            4
 236 #define CHL_INT0_NOT_RDY_MSK            (0x1 << CHL_INT0_NOT_RDY_OFF)
 237 #define CHL_INT0_PHY_RDY_OFF            5
 238 #define CHL_INT0_PHY_RDY_MSK            (0x1 << CHL_INT0_PHY_RDY_OFF)
 239 #define CHL_INT1                        (PORT_BASE + 0x1b8)
 240 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF    15
 241 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
 242 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF    17
 243 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
 244 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
 245 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
 246 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
 247 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
 248 #define CHL_INT2                        (PORT_BASE + 0x1bc)
 249 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF  0
 250 #define CHL_INT0_MSK                    (PORT_BASE + 0x1c0)
 251 #define CHL_INT1_MSK                    (PORT_BASE + 0x1c4)
 252 #define CHL_INT2_MSK                    (PORT_BASE + 0x1c8)
 253 #define CHL_INT_COAL_EN                 (PORT_BASE + 0x1d0)
 254 #define DMA_TX_DFX0                             (PORT_BASE + 0x200)
 255 #define DMA_TX_DFX1                             (PORT_BASE + 0x204)
 256 #define DMA_TX_DFX1_IPTT_OFF            0
 257 #define DMA_TX_DFX1_IPTT_MSK            (0xffff << DMA_TX_DFX1_IPTT_OFF)
 258 #define DMA_TX_FIFO_DFX0                (PORT_BASE + 0x240)
 259 #define PORT_DFX0                               (PORT_BASE + 0x258)
 260 #define LINK_DFX2                                       (PORT_BASE + 0X264)
 261 #define LINK_DFX2_RCVR_HOLD_STS_OFF     9
 262 #define LINK_DFX2_RCVR_HOLD_STS_MSK     (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
 263 #define LINK_DFX2_SEND_HOLD_STS_OFF     10
 264 #define LINK_DFX2_SEND_HOLD_STS_MSK     (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
 265 #define SAS_ERR_CNT4_REG                (PORT_BASE + 0x290)
 266 #define SAS_ERR_CNT6_REG                (PORT_BASE + 0x298)
 267 #define PHY_CTRL_RDY_MSK                (PORT_BASE + 0x2b0)
 268 #define PHYCTRL_NOT_RDY_MSK             (PORT_BASE + 0x2b4)
 269 #define PHYCTRL_DWS_RESET_MSK           (PORT_BASE + 0x2b8)
 270 #define PHYCTRL_PHY_ENA_MSK             (PORT_BASE + 0x2bc)
 271 #define SL_RX_BCAST_CHK_MSK             (PORT_BASE + 0x2c0)
 272 #define PHYCTRL_OOB_RESTART_MSK         (PORT_BASE + 0x2c4)
 273 #define DMA_TX_STATUS                   (PORT_BASE + 0x2d0)
 274 #define DMA_TX_STATUS_BUSY_OFF          0
 275 #define DMA_TX_STATUS_BUSY_MSK          (0x1 << DMA_TX_STATUS_BUSY_OFF)
 276 #define DMA_RX_STATUS                   (PORT_BASE + 0x2e8)
 277 #define DMA_RX_STATUS_BUSY_OFF          0
 278 #define DMA_RX_STATUS_BUSY_MSK          (0x1 << DMA_RX_STATUS_BUSY_OFF)
 279
 280 #define AXI_CFG                         (0x5100)
 281 #define AM_CFG_MAX_TRANS                (0x5010)
 282 #define AM_CFG_SINGLE_PORT_MAX_TRANS    (0x5014)
 283
 284 #define AXI_MASTER_CFG_BASE             (0x5000)
 285 #define AM_CTRL_GLOBAL                  (0x0)
 286 #define AM_CURR_TRANS_RETURN    (0x150)
 287
 288 /* HW dma structures */
 289 /* Delivery queue header */
 290 /* dw0 */
 291 #define CMD_HDR_ABORT_FLAG_OFF          0
 292 #define CMD_HDR_ABORT_FLAG_MSK          (0x3 << CMD_HDR_ABORT_FLAG_OFF)
 293 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF   2
 294 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK   (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
 295 #define CMD_HDR_RESP_REPORT_OFF         5
 296 #define CMD_HDR_RESP_REPORT_MSK         (0x1 << CMD_HDR_RESP_REPORT_OFF)
 297 #define CMD_HDR_TLR_CTRL_OFF            6
 298 #define CMD_HDR_TLR_CTRL_MSK            (0x3 << CMD_HDR_TLR_CTRL_OFF)
 299 #define CMD_HDR_PHY_ID_OFF              8
 300 #define CMD_HDR_PHY_ID_MSK              (0x1ff << CMD_HDR_PHY_ID_OFF)
 301 #define CMD_HDR_FORCE_PHY_OFF           17
 302 #define CMD_HDR_FORCE_PHY_MSK           (0x1 << CMD_HDR_FORCE_PHY_OFF)
 303 #define CMD_HDR_PORT_OFF                18
 304 #define CMD_HDR_PORT_MSK                (0xf << CMD_HDR_PORT_OFF)
 305 #define CMD_HDR_PRIORITY_OFF            27
 306 #define CMD_HDR_PRIORITY_MSK            (0x1 << CMD_HDR_PRIORITY_OFF)
 307 #define CMD_HDR_CMD_OFF                 29
 308 #define CMD_HDR_CMD_MSK                 (0x7 << CMD_HDR_CMD_OFF)
 309 /* dw1 */
 310 #define CMD_HDR_DIR_OFF                 5
 311 #define CMD_HDR_DIR_MSK                 (0x3 << CMD_HDR_DIR_OFF)
 312 #define CMD_HDR_RESET_OFF               7
 313 #define CMD_HDR_RESET_MSK               (0x1 << CMD_HDR_RESET_OFF)
 314 #define CMD_HDR_VDTL_OFF                10
 315 #define CMD_HDR_VDTL_MSK                (0x1 << CMD_HDR_VDTL_OFF)
 316 #define CMD_HDR_FRAME_TYPE_OFF          11
 317 #define CMD_HDR_FRAME_TYPE_MSK          (0x1f << CMD_HDR_FRAME_TYPE_OFF)
 318 #define CMD_HDR_DEV_ID_OFF              16
 319 #define CMD_HDR_DEV_ID_MSK              (0xffff << CMD_HDR_DEV_ID_OFF)
 320 /* dw2 */
 321 #define CMD_HDR_CFL_OFF                 0
 322 #define CMD_HDR_CFL_MSK                 (0x1ff << CMD_HDR_CFL_OFF)
 323 #define CMD_HDR_NCQ_TAG_OFF             10
 324 #define CMD_HDR_NCQ_TAG_MSK             (0x1f << CMD_HDR_NCQ_TAG_OFF)
 325 #define CMD_HDR_MRFL_OFF                15
 326 #define CMD_HDR_MRFL_MSK                (0x1ff << CMD_HDR_MRFL_OFF)
 327 #define CMD_HDR_SG_MOD_OFF              24
 328 #define CMD_HDR_SG_MOD_MSK              (0x3 << CMD_HDR_SG_MOD_OFF)
 329 #define CMD_HDR_FIRST_BURST_OFF         26
 330 #define CMD_HDR_FIRST_BURST_MSK         (0x1 << CMD_HDR_SG_MOD_OFF)
 331 /* dw3 */
 332 #define CMD_HDR_IPTT_OFF                0
 333 #define CMD_HDR_IPTT_MSK                (0xffff << CMD_HDR_IPTT_OFF)
 334 /* dw6 */
 335 #define CMD_HDR_DIF_SGL_LEN_OFF         0
 336 #define CMD_HDR_DIF_SGL_LEN_MSK         (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
 337 #define CMD_HDR_DATA_SGL_LEN_OFF        16
 338 #define CMD_HDR_DATA_SGL_LEN_MSK        (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
 339 #define CMD_HDR_ABORT_IPTT_OFF          16
 340 #define CMD_HDR_ABORT_IPTT_MSK          (0xffff << CMD_HDR_ABORT_IPTT_OFF)
 341
 342 /* Completion header */
 343 /* dw0 */
 344 #define CMPLT_HDR_ERR_PHASE_OFF 2
 345 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
 346 #define CMPLT_HDR_RSPNS_XFRD_OFF        10
 347 #define CMPLT_HDR_RSPNS_XFRD_MSK        (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
 348 #define CMPLT_HDR_ERX_OFF               12
 349 #define CMPLT_HDR_ERX_MSK               (0x1 << CMPLT_HDR_ERX_OFF)
 350 #define CMPLT_HDR_ABORT_STAT_OFF        13
 351 #define CMPLT_HDR_ABORT_STAT_MSK        (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
 352 /* abort_stat */
 353 #define STAT_IO_NOT_VALID               0x1
 354 #define STAT_IO_NO_DEVICE               0x2
 355 #define STAT_IO_COMPLETE                0x3
 356 #define STAT_IO_ABORTED                 0x4
 357 /* dw1 */
 358 #define CMPLT_HDR_IPTT_OFF              0
 359 #define CMPLT_HDR_IPTT_MSK              (0xffff << CMPLT_HDR_IPTT_OFF)
 360 #define CMPLT_HDR_DEV_ID_OFF            16
 361 #define CMPLT_HDR_DEV_ID_MSK            (0xffff << CMPLT_HDR_DEV_ID_OFF)
 362
 363 /* ITCT header */
 364 /* qw0 */
 365 #define ITCT_HDR_DEV_TYPE_OFF           0
 366 #define ITCT_HDR_DEV_TYPE_MSK           (0x3 << ITCT_HDR_DEV_TYPE_OFF)
 367 #define ITCT_HDR_VALID_OFF              2
 368 #define ITCT_HDR_VALID_MSK              (0x1 << ITCT_HDR_VALID_OFF)
 369 #define ITCT_HDR_MCR_OFF                5
 370 #define ITCT_HDR_MCR_MSK                (0xf << ITCT_HDR_MCR_OFF)
 371 #define ITCT_HDR_VLN_OFF                9
 372 #define ITCT_HDR_VLN_MSK                (0xf << ITCT_HDR_VLN_OFF)
 373 #define ITCT_HDR_SMP_TIMEOUT_OFF        16
 374 #define ITCT_HDR_SMP_TIMEOUT_8US        1
 375 #define ITCT_HDR_SMP_TIMEOUT            (ITCT_HDR_SMP_TIMEOUT_8US * \
 376                                          250) /* 2ms */
 377 #define ITCT_HDR_AWT_CONTINUE_OFF       25
 378 #define ITCT_HDR_PORT_ID_OFF            28
 379 #define ITCT_HDR_PORT_ID_MSK            (0xf << ITCT_HDR_PORT_ID_OFF)
 380 /* qw2 */
 381 #define ITCT_HDR_INLT_OFF               0
 382 #define ITCT_HDR_INLT_MSK               (0xffffULL << ITCT_HDR_INLT_OFF)
 383 #define ITCT_HDR_BITLT_OFF              16
 384 #define ITCT_HDR_BITLT_MSK              (0xffffULL << ITCT_HDR_BITLT_OFF)
 385 #define ITCT_HDR_MCTLT_OFF              32
 386 #define ITCT_HDR_MCTLT_MSK              (0xffffULL << ITCT_HDR_MCTLT_OFF)
 387 #define ITCT_HDR_RTOLT_OFF              48
 388 #define ITCT_HDR_RTOLT_MSK              (0xffffULL << ITCT_HDR_RTOLT_OFF)
 389
 390 #define HISI_SAS_FATAL_INT_NR   2
 391
 392 struct hisi_sas_complete_v2_hdr {
 393         __le32 dw0;
 394         __le32 dw1;
 395         __le32 act;
 396         __le32 dw3;
 397 };
 398
 399 struct hisi_sas_err_record_v2 {
 400         /* dw0 */
 401         __le32 trans_tx_fail_type;
 402
 403         /* dw1 */
 404         __le32 trans_rx_fail_type;
 405
 406         /* dw2 */
 407         __le16 dma_tx_err_type;
 408         __le16 sipc_rx_err_type;
 409
 410         /* dw3 */
 411         __le32 dma_rx_err_type;
 412 };
 413
 414 struct signal_attenuation_s {
 415         u32 de_emphasis;
 416         u32 preshoot;
 417         u32 boost;
 418 };
 419
 420 struct sig_atten_lu_s {
 421         const struct signal_attenuation_s *att;
 422         u32 sas_phy_ctrl;
 423 };
 424
 425 static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
 426         {
 427                 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
 428                 .msk = HGC_DQE_ECC_1B_ADDR_MSK,
 429                 .shift = HGC_DQE_ECC_1B_ADDR_OFF,
 430                 .msg = "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n",
 431                 .reg = HGC_DQE_ECC_ADDR,
 432         },
 433         {
 434                 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
 435                 .msk = HGC_IOST_ECC_1B_ADDR_MSK,
 436                 .shift = HGC_IOST_ECC_1B_ADDR_OFF,
 437                 .msg = "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n",
 438                 .reg = HGC_IOST_ECC_ADDR,
 439         },
 440         {
 441                 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
 442                 .msk = HGC_ITCT_ECC_1B_ADDR_MSK,
 443                 .shift = HGC_ITCT_ECC_1B_ADDR_OFF,
 444                 .msg = "hgc_itct_acc1b_intr found: am address is 0x%08X\n",
 445                 .reg = HGC_ITCT_ECC_ADDR,
 446         },
 447         {
 448                 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
 449                 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
 450                 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
 451                 .msg = "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n",
 452                 .reg = HGC_LM_DFX_STATUS2,
 453         },
 454         {
 455                 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
 456                 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
 457                 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
 458                 .msg = "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n",
 459                 .reg = HGC_LM_DFX_STATUS2,
 460         },
 461         {
 462                 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
 463                 .msk = HGC_CQE_ECC_1B_ADDR_MSK,
 464                 .shift = HGC_CQE_ECC_1B_ADDR_OFF,
 465                 .msg = "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n",
 466                 .reg = HGC_CQE_ECC_ADDR,
 467         },
 468         {
 469                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
 470                 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
 471                 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
 472                 .msg = "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n",
 473                 .reg = HGC_RXM_DFX_STATUS14,
 474         },
 475         {
 476                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
 477                 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
 478                 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
 479                 .msg = "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n",
 480                 .reg = HGC_RXM_DFX_STATUS14,
 481         },
 482         {
 483                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
 484                 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
 485                 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
 486                 .msg = "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n",
 487                 .reg = HGC_RXM_DFX_STATUS14,
 488         },
 489         {
 490                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
 491                 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
 492                 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
 493                 .msg = "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n",
 494                 .reg = HGC_RXM_DFX_STATUS15,
 495         },
 496 };
 497
 498 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
 499         {
 500                 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
 501                 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
 502                 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
 503                 .msg = "hgc_dqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
 504                 .reg = HGC_DQE_ECC_ADDR,
 505         },
 506         {
 507                 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
 508                 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
 509                 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
 510                 .msg = "hgc_iost_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
 511                 .reg = HGC_IOST_ECC_ADDR,
 512         },
 513         {
 514                 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
 515                 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
 516                 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
 517                 .msg = "hgc_itct_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
 518                 .reg = HGC_ITCT_ECC_ADDR,
 519         },
 520         {
 521                 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
 522                 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
 523                 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
 524                 .msg = "hgc_iostl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 525                 .reg = HGC_LM_DFX_STATUS2,
 526         },
 527         {
 528                 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
 529                 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
 530                 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
 531                 .msg = "hgc_itctl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 532                 .reg = HGC_LM_DFX_STATUS2,
 533         },
 534         {
 535                 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
 536                 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
 537                 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
 538                 .msg = "hgc_cqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
 539                 .reg = HGC_CQE_ECC_ADDR,
 540         },
 541         {
 542                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
 543                 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
 544                 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
 545                 .msg = "rxm_mem0_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 546                 .reg = HGC_RXM_DFX_STATUS14,
 547         },
 548         {
 549                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
 550                 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
 551                 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
 552                 .msg = "rxm_mem1_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 553                 .reg = HGC_RXM_DFX_STATUS14,
 554         },
 555         {
 556                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
 557                 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
 558                 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
 559                 .msg = "rxm_mem2_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 560                 .reg = HGC_RXM_DFX_STATUS14,
 561         },
 562         {
 563                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
 564                 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
 565                 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
 566                 .msg = "rxm_mem3_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 567                 .reg = HGC_RXM_DFX_STATUS15,
 568         },
 569 };
 570
 571 enum {
 572         HISI_SAS_PHY_PHY_UPDOWN,
 573         HISI_SAS_PHY_CHNL_INT,
 574         HISI_SAS_PHY_INT_NR
 575 };
 576
 577 enum {
 578         TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
 579         TRANS_RX_FAIL_BASE = 0x20, /* dw1 */
 580         DMA_TX_ERR_BASE = 0x40, /* dw2 bit 15-0 */
 581         SIPC_RX_ERR_BASE = 0x50, /* dw2 bit 31-16*/
 582         DMA_RX_ERR_BASE = 0x60, /* dw3 */
 583
 584         /* trans tx*/
 585         TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
 586         TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
 587         TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
 588         TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
 589         TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
 590         RESERVED0, /* 0x5 */
 591         TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
 592         TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
 593         TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
 594         TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
 595         TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
 596         TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
 597         TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
 598         TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
 599         TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
 600         TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
 601         TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
 602         TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
 603         TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
 604         TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
 605         TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
 606         TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
 607         TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
 608         TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
 609         TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
 610         TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
 611         TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
 612         TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
 613         /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
 614         TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
 615         /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
 616         TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
 617         TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
 618         /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
 619         TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
 620
 621         /* trans rx */
 622         TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x20 */
 623         TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x21 for sata/stp */
 624         TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x22 for ssp/smp */
 625         /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
 626         TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x23 for sata/stp */
 627         TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x24 for sata/stp */
 628         TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x25 for smp */
 629         /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
 630         TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x26 for sata/stp*/
 631         TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x27 */
 632         TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x28 */
 633         TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x29 */
 634         TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x2a */
 635         RESERVED1, /* 0x2b */
 636         TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x2c */
 637         TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x2d */
 638         TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x2e */
 639         TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x2f */
 640         TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x30 for ssp/smp */
 641         TRANS_RX_ERR_WITH_BAD_HASH, /* 0x31 for ssp */
 642         /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
 643         TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x32 for ssp*/
 644         /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
 645         TRANS_RX_SSP_FRM_LEN_ERR, /* 0x33 for ssp */
 646         /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
 647         RESERVED2, /* 0x34 */
 648         RESERVED3, /* 0x35 */
 649         RESERVED4, /* 0x36 */
 650         RESERVED5, /* 0x37 */
 651         TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x38 */
 652         TRANS_RX_SMP_FRM_LEN_ERR, /* 0x39 */
 653         TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x3a */
 654         RESERVED6, /* 0x3b */
 655         RESERVED7, /* 0x3c */
 656         RESERVED8, /* 0x3d */
 657         RESERVED9, /* 0x3e */
 658         TRANS_RX_R_ERR, /* 0x3f */
 659
 660         /* dma tx */
 661         DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x40 */
 662         DMA_TX_DIF_APP_ERR, /* 0x41 */
 663         DMA_TX_DIF_RPP_ERR, /* 0x42 */
 664         DMA_TX_DATA_SGL_OVERFLOW, /* 0x43 */
 665         DMA_TX_DIF_SGL_OVERFLOW, /* 0x44 */
 666         DMA_TX_UNEXP_XFER_ERR, /* 0x45 */
 667         DMA_TX_UNEXP_RETRANS_ERR, /* 0x46 */
 668         DMA_TX_XFER_LEN_OVERFLOW, /* 0x47 */
 669         DMA_TX_XFER_OFFSET_ERR, /* 0x48 */
 670         DMA_TX_RAM_ECC_ERR, /* 0x49 */
 671         DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x4a */
 672         DMA_TX_MAX_ERR_CODE,
 673
 674         /* sipc rx */
 675         SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x50 */
 676         SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x51 */
 677         SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x52 */
 678         SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x53 */
 679         SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x54 */
 680         SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x55 */
 681         SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x56 */
 682         SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x57 */
 683         SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x58 */
 684         SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x59 */
 685         SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x5a */
 686         SIPC_RX_MAX_ERR_CODE,
 687
 688         /* dma rx */
 689         DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x60 */
 690         DMA_RX_DIF_APP_ERR, /* 0x61 */
 691         DMA_RX_DIF_RPP_ERR, /* 0x62 */
 692         DMA_RX_DATA_SGL_OVERFLOW, /* 0x63 */
 693         DMA_RX_DIF_SGL_OVERFLOW, /* 0x64 */
 694         DMA_RX_DATA_LEN_OVERFLOW, /* 0x65 */
 695         DMA_RX_DATA_LEN_UNDERFLOW, /* 0x66 */
 696         DMA_RX_DATA_OFFSET_ERR, /* 0x67 */
 697         RESERVED10, /* 0x68 */
 698         DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x69 */
 699         DMA_RX_RESP_BUF_OVERFLOW, /* 0x6a */
 700         DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x6b */
 701         DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x6c */
 702         DMA_RX_UNEXP_RDFRAME_ERR, /* 0x6d */
 703         DMA_RX_PIO_DATA_LEN_ERR, /* 0x6e */
 704         DMA_RX_RDSETUP_STATUS_ERR, /* 0x6f */
 705         DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x70 */
 706         DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x71 */
 707         DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x72 */
 708         DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x73 */
 709         DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x74 */
 710         DMA_RX_RDSETUP_OFFSET_ERR, /* 0x75 */
 711         DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x76 */
 712         DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x77 */
 713         DMA_RX_RAM_ECC_ERR, /* 0x78 */
 714         DMA_RX_UNKNOWN_FRM_ERR, /* 0x79 */
 715         DMA_RX_MAX_ERR_CODE,
 716 };
 717
 718 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
 719 #define HISI_MAX_SATA_SUPPORT_V2_HW     (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
 720
 721 #define DIR_NO_DATA 0
 722 #define DIR_TO_INI 1
 723 #define DIR_TO_DEVICE 2
 724 #define DIR_RESERVED 3
 725
 726 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
 727                 err_phase == 0x4 || err_phase == 0x8 ||\
 728                 err_phase == 0x6 || err_phase == 0xa)
 729 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
 730                 err_phase == 0x20 || err_phase == 0x40)
 731
 732 static void link_timeout_disable_link(struct timer_list *t);
 733
 734 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
 735 {
 736         void __iomem *regs = hisi_hba->regs + off;
 737
 738         return readl(regs);
 739 }
 740
 741 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
 742 {
 743         void __iomem *regs = hisi_hba->regs + off;
 744
 745         return readl_relaxed(regs);
 746 }
 747
 748 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
 749 {
 750         void __iomem *regs = hisi_hba->regs + off;
 751
 752         writel(val, regs);
 753 }
 754
 755 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
 756                                  u32 off, u32 val)
 757 {
 758         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 759
 760         writel(val, regs);
 761 }
 762
 763 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
 764                                       int phy_no, u32 off)
 765 {
 766         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 767
 768         return readl(regs);
 769 }
 770
 771 /* This function needs to be protected from pre-emption. */
 772 static int
 773 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba,
 774                              struct domain_device *device)
 775 {
 776         int sata_dev = dev_is_sata(device);
 777         void *bitmap = hisi_hba->slot_index_tags;
 778         struct hisi_sas_device *sas_dev = device->lldd_dev;
 779         int sata_idx = sas_dev->sata_idx;
 780         int start, end;
 781         unsigned long flags;
 782
 783         if (!sata_dev) {
 784                 /*
 785                  * STP link SoC bug workaround: index starts from 1.
 786                  * additionally, we can only allocate odd IPTT(1~4095)
 787                  * for SAS/SMP device.
 788                  */
 789                 start = 1;
 790                 end = hisi_hba->slot_index_count;
 791         } else {
 792                 if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
 793                         return -EINVAL;
 794
 795                 /*
 796                  * For SATA device: allocate even IPTT in this interval
 797                  * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
 798                  * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
 799                  * SoC bug workaround. So we ignore the first 32 even IPTTs.
 800                  */
 801                 start = 64 * (sata_idx + 1);
 802                 end = 64 * (sata_idx + 2);
 803         }
 804
 805         spin_lock_irqsave(&hisi_hba->lock, flags);
 806         while (1) {
 807                 start = find_next_zero_bit(bitmap,
 808                                         hisi_hba->slot_index_count, start);
 809                 if (start >= end) {
 810                         spin_unlock_irqrestore(&hisi_hba->lock, flags);
 811                         return -SAS_QUEUE_FULL;
 812                 }
 813                 /*
 814                   * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
 815                   */
 816                 if (sata_dev ^ (start & 1))
 817                         break;
 818                 start++;
 819         }
 820
 821         set_bit(start, bitmap);
 822         spin_unlock_irqrestore(&hisi_hba->lock, flags);
 823         return start;
 824 }
 825
 826 static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
 827 {
 828         unsigned int index;
 829         struct device *dev = hisi_hba->dev;
 830         void *bitmap = hisi_hba->sata_dev_bitmap;
 831
 832         index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
 833         if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
 834                 dev_warn(dev, "alloc sata index failed, index=%d\n", index);
 835                 return false;
 836         }
 837
 838         set_bit(index, bitmap);
 839         *idx = index;
 840         return true;
 841 }
 842
 843
 844 static struct
 845 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
 846 {
 847         struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
 848         struct hisi_sas_device *sas_dev = NULL;
 849         int i, sata_dev = dev_is_sata(device);
 850         int sata_idx = -1;
 851         unsigned long flags;
 852
 853         spin_lock_irqsave(&hisi_hba->lock, flags);
 854
 855         if (sata_dev)
 856                 if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
 857                         goto out;
 858
 859         for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
 860                 /*
 861                  * SATA device id bit0 should be 0
 862                  */
 863                 if (sata_dev && (i & 1))
 864                         continue;
 865                 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
 866                         int queue = i % hisi_hba->queue_count;
 867                         struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
 868
 869                         hisi_hba->devices[i].device_id = i;
 870                         sas_dev = &hisi_hba->devices[i];
 871                         sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
 872                         sas_dev->dev_type = device->dev_type;
 873                         sas_dev->hisi_hba = hisi_hba;
 874                         sas_dev->sas_device = device;
 875                         sas_dev->sata_idx = sata_idx;
 876                         sas_dev->dq = dq;
 877                         INIT_LIST_HEAD(&hisi_hba->devices[i].list);
 878                         break;
 879                 }
 880         }
 881
 882 out:
 883         spin_unlock_irqrestore(&hisi_hba->lock, flags);
 884
 885         return sas_dev;
 886 }
 887
 888 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 889 {
 890         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 891
 892         cfg &= ~PHY_CFG_DC_OPT_MSK;
 893         cfg |= 1 << PHY_CFG_DC_OPT_OFF;
 894         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 895 }
 896
 897 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 898 {
 899         struct sas_identify_frame identify_frame;
 900         u32 *identify_buffer;
 901
 902         memset(&identify_frame, 0, sizeof(identify_frame));
 903         identify_frame.dev_type = SAS_END_DEVICE;
 904         identify_frame.frame_type = 0;
 905         identify_frame._un1 = 1;
 906         identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
 907         identify_frame.target_bits = SAS_PROTOCOL_NONE;
 908         memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 909         memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 910         identify_frame.phy_id = phy_no;
 911         identify_buffer = (u32 *)(&identify_frame);
 912
 913         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
 914                         __swab32(identify_buffer[0]));
 915         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
 916                         __swab32(identify_buffer[1]));
 917         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
 918                         __swab32(identify_buffer[2]));
 919         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
 920                         __swab32(identify_buffer[3]));
 921         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
 922                         __swab32(identify_buffer[4]));
 923         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
 924                         __swab32(identify_buffer[5]));
 925 }
 926
 927 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
 928                              struct hisi_sas_device *sas_dev)
 929 {
 930         struct domain_device *device = sas_dev->sas_device;
 931         struct device *dev = hisi_hba->dev;
 932         u64 qw0, device_id = sas_dev->device_id;
 933         struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
 934         struct domain_device *parent_dev = device->parent;
 935         struct asd_sas_port *sas_port = device->port;
 936         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
 937
 938         memset(itct, 0, sizeof(*itct));
 939
 940         /* qw0 */
 941         qw0 = 0;
 942         switch (sas_dev->dev_type) {
 943         case SAS_END_DEVICE:
 944         case SAS_EDGE_EXPANDER_DEVICE:
 945         case SAS_FANOUT_EXPANDER_DEVICE:
 946                 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
 947                 break;
 948         case SAS_SATA_DEV:
 949         case SAS_SATA_PENDING:
 950                 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
 951                         qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
 952                 else
 953                         qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
 954                 break;
 955         default:
 956                 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
 957                          sas_dev->dev_type);
 958         }
 959
 960         qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
 961                 (device->linkrate << ITCT_HDR_MCR_OFF) |
 962                 (1 << ITCT_HDR_VLN_OFF) |
 963                 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
 964                 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
 965                 (port->id << ITCT_HDR_PORT_ID_OFF));
 966         itct->qw0 = cpu_to_le64(qw0);
 967
 968         /* qw1 */
 969         memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
 970         itct->sas_addr = __swab64(itct->sas_addr);
 971
 972         /* qw2 */
 973         if (!dev_is_sata(device))
 974                 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
 975                                         (0x1ULL << ITCT_HDR_BITLT_OFF) |
 976                                         (0x32ULL << ITCT_HDR_MCTLT_OFF) |
 977                                         (0x1ULL << ITCT_HDR_RTOLT_OFF));
 978 }
 979
 980 static void clear_itct_v2_hw(struct hisi_hba *hisi_hba,
 981                               struct hisi_sas_device *sas_dev)
 982 {
 983         DECLARE_COMPLETION_ONSTACK(completion);
 984         u64 dev_id = sas_dev->device_id;
 985         struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
 986         u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
 987         int i;
 988
 989         sas_dev->completion = &completion;
 990
 991         /* clear the itct interrupt state */
 992         if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
 993                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
 994                                  ENT_INT_SRC3_ITC_INT_MSK);
 995
 996         for (i = 0; i < 2; i++) {
 997                 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
 998                 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
 999                 wait_for_completion(sas_dev->completion);
1000
1001                 memset(itct, 0, sizeof(struct hisi_sas_itct));
1002         }
1003 }
1004
1005 static void free_device_v2_hw(struct hisi_sas_device *sas_dev)
1006 {
1007         struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
1008
1009         /* SoC bug workaround */
1010         if (dev_is_sata(sas_dev->sas_device))
1011                 clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
1012 }
1013
1014 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
1015 {
1016         int i, reset_val;
1017         u32 val;
1018         unsigned long end_time;
1019         struct device *dev = hisi_hba->dev;
1020
1021         /* The mask needs to be set depending on the number of phys */
1022         if (hisi_hba->n_phy == 9)
1023                 reset_val = 0x1fffff;
1024         else
1025                 reset_val = 0x7ffff;
1026
1027         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
1028
1029         /* Disable all of the PHYs */
1030         for (i = 0; i < hisi_hba->n_phy; i++) {
1031                 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
1032
1033                 phy_cfg &= ~PHY_CTRL_RESET_MSK;
1034                 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
1035         }
1036         udelay(50);
1037
1038         /* Ensure DMA tx & rx idle */
1039         for (i = 0; i < hisi_hba->n_phy; i++) {
1040                 u32 dma_tx_status, dma_rx_status;
1041
1042                 end_time = jiffies + msecs_to_jiffies(1000);
1043
1044                 while (1) {
1045                         dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
1046                                                             DMA_TX_STATUS);
1047                         dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
1048                                                             DMA_RX_STATUS);
1049
1050                         if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
1051                                 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
1052                                 break;
1053
1054                         msleep(20);
1055                         if (time_after(jiffies, end_time))
1056                                 return -EIO;
1057                 }
1058         }
1059
1060         /* Ensure axi bus idle */
1061         end_time = jiffies + msecs_to_jiffies(1000);
1062         while (1) {
1063                 u32 axi_status =
1064                         hisi_sas_read32(hisi_hba, AXI_CFG);
1065
1066                 if (axi_status == 0)
1067                         break;
1068
1069                 msleep(20);
1070                 if (time_after(jiffies, end_time))
1071                         return -EIO;
1072         }
1073
1074         if (ACPI_HANDLE(dev)) {
1075                 acpi_status s;
1076
1077                 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
1078                 if (ACPI_FAILURE(s)) {
1079                         dev_err(dev, "Reset failed\n");
1080                         return -EIO;
1081                 }
1082         } else if (hisi_hba->ctrl) {
1083                 /* reset and disable clock*/
1084                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
1085                                 reset_val);
1086                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
1087                                 reset_val);
1088                 msleep(1);
1089                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
1090                 if (reset_val != (val & reset_val)) {
1091                         dev_err(dev, "SAS reset fail.\n");
1092                         return -EIO;
1093                 }
1094
1095                 /* De-reset and enable clock*/
1096                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
1097                                 reset_val);
1098                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
1099                                 reset_val);
1100                 msleep(1);
1101                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
1102                                 &val);
1103                 if (val & reset_val) {
1104                         dev_err(dev, "SAS de-reset fail.\n");
1105                         return -EIO;
1106                 }
1107         } else {
1108                 dev_err(dev, "no reset method\n");
1109                 return -EINVAL;
1110         }
1111
1112         return 0;
1113 }
1114
1115 /* This function needs to be called after resetting SAS controller. */
1116 static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1117 {
1118         u32 cfg;
1119         int phy_no;
1120
1121         hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
1122         for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1123                 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
1124                 if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
1125                         continue;
1126
1127                 cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1128                 hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
1129         }
1130 }
1131
1132 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1133 {
1134         int phy_no;
1135         u32 dma_tx_dfx1;
1136
1137         for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1138                 if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
1139                         continue;
1140
1141                 dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1142                                                 DMA_TX_DFX1);
1143                 if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
1144                         u32 cfg = hisi_sas_phy_read32(hisi_hba,
1145                                 phy_no, CON_CONTROL);
1146
1147                         cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1148                         hisi_sas_phy_write32(hisi_hba, phy_no,
1149                                 CON_CONTROL, cfg);
1150                         clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
1151                 }
1152         }
1153 }
1154
1155 static const struct signal_attenuation_s x6000 = {9200, 0, 10476};
1156 static const struct sig_atten_lu_s sig_atten_lu[] = {
1157         { &x6000, 0x3016a68 },
1158 };
1159
1160 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
1161 {
1162         struct device *dev = hisi_hba->dev;
1163         u32 sas_phy_ctrl = 0x30b9908;
1164         u32 signal[3];
1165         int i;
1166
1167         /* Global registers init */
1168
1169         /* Deal with am-max-transmissions quirk */
1170         if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
1171                 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
1172                 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
1173                                  0x2020);
1174         } /* Else, use defaults -> do nothing */
1175
1176         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
1177                          (u32)((1ULL << hisi_hba->queue_count) - 1));
1178         hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
1179         hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
1180         hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
1181         hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
1182         hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
1183         hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
1184         hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
1185         hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
1186         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
1187         hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
1188         hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
1189         hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
1190         hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
1191         hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
1192         hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
1193         hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
1194         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
1195         hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
1196         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
1197         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
1198         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
1199         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
1200         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
1201         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
1202         for (i = 0; i < hisi_hba->queue_count; i++)
1203                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
1204
1205         hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
1206         hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
1207
1208         /* Get sas_phy_ctrl value to deal with TX FFE issue. */
1209         if (!device_property_read_u32_array(dev, "hisilicon,signal-attenuation",
1210                                             signal, ARRAY_SIZE(signal))) {
1211                 for (i = 0; i < ARRAY_SIZE(sig_atten_lu); i++) {
1212                         const struct sig_atten_lu_s *lookup = &sig_atten_lu[i];
1213                         const struct signal_attenuation_s *att = lookup->att;
1214
1215                         if ((signal[0] == att->de_emphasis) &&
1216                             (signal[1] == att->preshoot) &&
1217                             (signal[2] == att->boost)) {
1218                                 sas_phy_ctrl = lookup->sas_phy_ctrl;
1219                                 break;
1220                         }
1221                 }
1222
1223                 if (i == ARRAY_SIZE(sig_atten_lu))
1224                         dev_warn(dev, "unknown signal attenuation values, using default PHY ctrl config\n");
1225         }
1226
1227         for (i = 0; i < hisi_hba->n_phy; i++) {
1228                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1229                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1230                 u32 prog_phy_link_rate = 0x800;
1231
1232                 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
1233                                 SAS_LINK_RATE_1_5_GBPS)) {
1234                         prog_phy_link_rate = 0x855;
1235                 } else {
1236                         enum sas_linkrate max = sas_phy->phy->maximum_linkrate;
1237
1238                         prog_phy_link_rate =
1239                                 hisi_sas_get_prog_phy_linkrate_mask(max) |
1240                                 0x800;
1241                 }
1242                 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
1243                         prog_phy_link_rate);
1244                 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, sas_phy_ctrl);
1245                 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
1246                 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
1247                 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
1248                 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
1249                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
1250                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
1251                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
1252                 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
1253                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff857fff);
1254                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbfe);
1255                 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
1256                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
1257                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
1258                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
1259                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
1260                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
1261                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
1262                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
1263                 if (hisi_hba->refclk_frequency_mhz == 66)
1264                         hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
1265                 /* else, do nothing -> leave it how you found it */
1266         }
1267
1268         for (i = 0; i < hisi_hba->queue_count; i++) {
1269                 /* Delivery queue */
1270                 hisi_sas_write32(hisi_hba,
1271                                  DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
1272                                  upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
1273
1274                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
1275                                  lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
1276
1277                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
1278                                  HISI_SAS_QUEUE_SLOTS);
1279
1280                 /* Completion queue */
1281                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
1282                                  upper_32_bits(hisi_hba->complete_hdr_dma[i]));
1283
1284                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
1285                                  lower_32_bits(hisi_hba->complete_hdr_dma[i]));
1286
1287                 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
1288                                  HISI_SAS_QUEUE_SLOTS);
1289         }
1290
1291         /* itct */
1292         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
1293                          lower_32_bits(hisi_hba->itct_dma));
1294
1295         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
1296                          upper_32_bits(hisi_hba->itct_dma));
1297
1298         /* iost */
1299         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
1300                          lower_32_bits(hisi_hba->iost_dma));
1301
1302         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
1303                          upper_32_bits(hisi_hba->iost_dma));
1304
1305         /* breakpoint */
1306         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
1307                          lower_32_bits(hisi_hba->breakpoint_dma));
1308
1309         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
1310                          upper_32_bits(hisi_hba->breakpoint_dma));
1311
1312         /* SATA broken msg */
1313         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
1314                          lower_32_bits(hisi_hba->sata_breakpoint_dma));
1315
1316         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
1317                          upper_32_bits(hisi_hba->sata_breakpoint_dma));
1318
1319         /* SATA initial fis */
1320         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
1321                          lower_32_bits(hisi_hba->initial_fis_dma));
1322
1323         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
1324                          upper_32_bits(hisi_hba->initial_fis_dma));
1325 }
1326
1327 static void link_timeout_enable_link(struct timer_list *t)
1328 {
1329         struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1330         int i, reg_val;
1331
1332         for (i = 0; i < hisi_hba->n_phy; i++) {
1333                 if (hisi_hba->reject_stp_links_msk & BIT(i))
1334                         continue;
1335
1336                 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
1337                 if (!(reg_val & BIT(0))) {
1338                         hisi_sas_phy_write32(hisi_hba, i,
1339                                         CON_CONTROL, 0x7);
1340                         break;
1341                 }
1342         }
1343
1344         hisi_hba->timer.function = link_timeout_disable_link;
1345         mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
1346 }
1347
1348 static void link_timeout_disable_link(struct timer_list *t)
1349 {
1350         struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1351         int i, reg_val;
1352
1353         reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
1354         for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
1355                 if (hisi_hba->reject_stp_links_msk & BIT(i))
1356                         continue;
1357
1358                 if (reg_val & BIT(i)) {
1359                         hisi_sas_phy_write32(hisi_hba, i,
1360                                         CON_CONTROL, 0x6);
1361                         break;
1362                 }
1363         }
1364
1365         hisi_hba->timer.function = link_timeout_enable_link;
1366         mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
1367 }
1368
1369 static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
1370 {
1371         hisi_hba->timer.function = link_timeout_disable_link;
1372         hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
1373         add_timer(&hisi_hba->timer);
1374 }
1375
1376 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
1377 {
1378         struct device *dev = hisi_hba->dev;
1379         int rc;
1380
1381         rc = reset_hw_v2_hw(hisi_hba);
1382         if (rc) {
1383                 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1384                 return rc;
1385         }
1386
1387         msleep(100);
1388         init_reg_v2_hw(hisi_hba);
1389
1390         return 0;
1391 }
1392
1393 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1394 {
1395         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1396
1397         cfg |= PHY_CFG_ENA_MSK;
1398         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1399 }
1400
1401 static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1402 {
1403         u32 context;
1404
1405         context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1406         if (context & (1 << phy_no))
1407                 return true;
1408
1409         return false;
1410 }
1411
1412 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1413 {
1414         u32 dfx_val;
1415
1416         dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1417
1418         if (dfx_val & BIT(16))
1419                 return false;
1420
1421         return true;
1422 }
1423
1424 static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1425 {
1426         int i, max_loop = 1000;
1427         struct device *dev = hisi_hba->dev;
1428         u32 status, axi_status, dfx_val, dfx_tx_val;
1429
1430         for (i = 0; i < max_loop; i++) {
1431                 status = hisi_sas_read32_relaxed(hisi_hba,
1432                         AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
1433
1434                 axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
1435                 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1436                 dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
1437                         phy_no, DMA_TX_FIFO_DFX0);
1438
1439                 if ((status == 0x3) && (axi_status == 0x0) &&
1440                     (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
1441                         return true;
1442                 udelay(10);
1443         }
1444         dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1445                         phy_no, status, axi_status,
1446                         dfx_val, dfx_tx_val);
1447         return false;
1448 }
1449
1450 static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1451 {
1452         int i, max_loop = 1000;
1453         struct device *dev = hisi_hba->dev;
1454         u32 status, tx_dfx0;
1455
1456         for (i = 0; i < max_loop; i++) {
1457                 status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
1458                 status = (status & 0x3fc0) >> 6;
1459
1460                 if (status != 0x1)
1461                         return true;
1462
1463                 tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
1464                 if ((tx_dfx0 & 0x1ff) == 0x2)
1465                         return true;
1466                 udelay(10);
1467         }
1468         dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1469                         phy_no, status, tx_dfx0);
1470         return false;
1471 }
1472
1473 static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1474 {
1475         if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
1476                 return true;
1477
1478         if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
1479                 return false;
1480
1481         if (!wait_io_done_v2_hw(hisi_hba, phy_no))
1482                 return false;
1483
1484         return true;
1485 }
1486
1487
1488 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1489 {
1490         u32 cfg, axi_val, dfx0_val, txid_auto;
1491         struct device *dev = hisi_hba->dev;
1492
1493         /* Close axi bus. */
1494         axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
1495                                 AM_CTRL_GLOBAL);
1496         axi_val |= 0x1;
1497         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1498                 AM_CTRL_GLOBAL, axi_val);
1499
1500         if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
1501                 if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
1502                         goto do_disable;
1503
1504                 /* Reset host controller. */
1505                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1506                 return;
1507         }
1508
1509         dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
1510         dfx0_val = (dfx0_val & 0x1fc0) >> 6;
1511         if (dfx0_val != 0x4)
1512                 goto do_disable;
1513
1514         if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
1515                 dev_warn(dev, "phy%d, wait tx fifo need send break\n",
1516                         phy_no);
1517                 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
1518                                         TXID_AUTO);
1519                 txid_auto |= TXID_AUTO_CTB_MSK;
1520                 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1521                                         txid_auto);
1522         }
1523
1524 do_disable:
1525         cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1526         cfg &= ~PHY_CFG_ENA_MSK;
1527         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1528
1529         /* Open axi bus. */
1530         axi_val &= ~0x1;
1531         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1532                 AM_CTRL_GLOBAL, axi_val);
1533 }
1534
1535 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1536 {
1537         config_id_frame_v2_hw(hisi_hba, phy_no);
1538         config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
1539         enable_phy_v2_hw(hisi_hba, phy_no);
1540 }
1541
1542 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1543 {
1544         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1545         u32 txid_auto;
1546
1547         disable_phy_v2_hw(hisi_hba, phy_no);
1548         if (phy->identify.device_type == SAS_END_DEVICE) {
1549                 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1550                 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1551                                         txid_auto | TX_HARDRST_MSK);
1552         }
1553         msleep(100);
1554         start_phy_v2_hw(hisi_hba, phy_no);
1555 }
1556
1557 static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1558 {
1559         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1560         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1561         struct sas_phy *sphy = sas_phy->phy;
1562         u32 err4_reg_val, err6_reg_val;
1563
1564         /* loss dword syn, phy reset problem */
1565         err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
1566
1567         /* disparity err, invalid dword */
1568         err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
1569
1570         sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
1571         sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
1572         sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
1573         sphy->running_disparity_error_count += err6_reg_val & 0xFF;
1574 }
1575
1576 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
1577 {
1578         int i;
1579
1580         for (i = 0; i < hisi_hba->n_phy; i++) {
1581                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1582                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1583
1584                 if (!sas_phy->phy->enabled)
1585                         continue;
1586
1587                 start_phy_v2_hw(hisi_hba, i);
1588         }
1589 }
1590
1591 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1592 {
1593         u32 sl_control;
1594
1595         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1596         sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1597         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1598         msleep(1);
1599         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1600         sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1601         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1602 }
1603
1604 static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
1605 {
1606         return SAS_LINK_RATE_12_0_GBPS;
1607 }
1608
1609 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
1610                 struct sas_phy_linkrates *r)
1611 {
1612         enum sas_linkrate max = r->maximum_linkrate;
1613         u32 prog_phy_link_rate = 0x800;
1614
1615         prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
1616         hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1617                              prog_phy_link_rate);
1618 }
1619
1620 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
1621 {
1622         int i, bitmap = 0;
1623         u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1624         u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1625
1626         for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
1627                 if (phy_state & 1 << i)
1628                         if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1629                                 bitmap |= 1 << i;
1630
1631         if (hisi_hba->n_phy == 9) {
1632                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1633
1634                 if (phy_state & 1 << 8)
1635                         if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1636                              PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1637                                 bitmap |= 1 << 9;
1638         }
1639
1640         return bitmap;
1641 }
1642
1643 /*
1644  * The callpath to this function and upto writing the write
1645  * queue pointer should be safe from interruption.
1646  */
1647 static int
1648 get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
1649 {
1650         struct device *dev = hisi_hba->dev;
1651         int queue = dq->id;
1652         u32 r, w;
1653
1654         w = dq->wr_point;
1655         r = hisi_sas_read32_relaxed(hisi_hba,
1656                                 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1657         if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1658                 dev_warn(dev, "full queue=%d r=%d w=%d\n",
1659                                 queue, r, w);
1660                 return -EAGAIN;
1661         }
1662
1663         dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS;
1664
1665         return w;
1666 }
1667
1668 /* DQ lock must be taken here */
1669 static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
1670 {
1671         struct hisi_hba *hisi_hba = dq->hisi_hba;
1672         struct hisi_sas_slot *s, *s1, *s2 = NULL;
1673         struct list_head *dq_list;
1674         int dlvry_queue = dq->id;
1675         int wp;
1676
1677         dq_list = &dq->list;
1678         list_for_each_entry_safe(s, s1, &dq->list, delivery) {
1679                 if (!s->ready)
1680                         break;
1681                 s2 = s;
1682                 list_del(&s->delivery);
1683         }
1684
1685         if (!s2)
1686                 return;
1687
1688         /*
1689          * Ensure that memories for slots built on other CPUs is observed.
1690          */
1691         smp_rmb();
1692         wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
1693
1694         hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
1695 }
1696
1697 static void prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1698                               struct hisi_sas_slot *slot,
1699                               struct hisi_sas_cmd_hdr *hdr,
1700                               struct scatterlist *scatter,
1701                               int n_elem)
1702 {
1703         struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1704         struct scatterlist *sg;
1705         int i;
1706
1707         for_each_sg(scatter, sg, n_elem, i) {
1708                 struct hisi_sas_sge *entry = &sge_page->sge[i];
1709
1710                 entry->addr = cpu_to_le64(sg_dma_address(sg));
1711                 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1712                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1713                 entry->data_off = 0;
1714         }
1715
1716         hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1717
1718         hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1719 }
1720
1721 static void prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1722                           struct hisi_sas_slot *slot)
1723 {
1724         struct sas_task *task = slot->task;
1725         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1726         struct domain_device *device = task->dev;
1727         struct hisi_sas_port *port = slot->port;
1728         struct scatterlist *sg_req;
1729         struct hisi_sas_device *sas_dev = device->lldd_dev;
1730         dma_addr_t req_dma_addr;
1731         unsigned int req_len;
1732
1733         /* req */
1734         sg_req = &task->smp_task.smp_req;
1735         req_dma_addr = sg_dma_address(sg_req);
1736         req_len = sg_dma_len(&task->smp_task.smp_req);
1737
1738         /* create header */
1739         /* dw0 */
1740         hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1741                                (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1742                                (2 << CMD_HDR_CMD_OFF)); /* smp */
1743
1744         /* map itct entry */
1745         hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1746                                (1 << CMD_HDR_FRAME_TYPE_OFF) |
1747                                (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1748
1749         /* dw2 */
1750         hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1751                                (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1752                                CMD_HDR_MRFL_OFF));
1753
1754         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1755
1756         hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1757         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1758 }
1759
1760 static void prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1761                           struct hisi_sas_slot *slot)
1762 {
1763         struct sas_task *task = slot->task;
1764         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1765         struct domain_device *device = task->dev;
1766         struct hisi_sas_device *sas_dev = device->lldd_dev;
1767         struct hisi_sas_port *port = slot->port;
1768         struct sas_ssp_task *ssp_task = &task->ssp_task;
1769         struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1770         struct hisi_sas_tmf_task *tmf = slot->tmf;
1771         int has_data = 0, priority = !!tmf;
1772         u8 *buf_cmd;
1773         u32 dw1 = 0, dw2 = 0;
1774
1775         hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1776                                (2 << CMD_HDR_TLR_CTRL_OFF) |
1777                                (port->id << CMD_HDR_PORT_OFF) |
1778                                (priority << CMD_HDR_PRIORITY_OFF) |
1779                                (1 << CMD_HDR_CMD_OFF)); /* ssp */
1780
1781         dw1 = 1 << CMD_HDR_VDTL_OFF;
1782         if (tmf) {
1783                 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1784                 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1785         } else {
1786                 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1787                 switch (scsi_cmnd->sc_data_direction) {
1788                 case DMA_TO_DEVICE:
1789                         has_data = 1;
1790                         dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1791                         break;
1792                 case DMA_FROM_DEVICE:
1793                         has_data = 1;
1794                         dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1795                         break;
1796                 default:
1797                         dw1 &= ~CMD_HDR_DIR_MSK;
1798                 }
1799         }
1800
1801         /* map itct entry */
1802         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1803         hdr->dw1 = cpu_to_le32(dw1);
1804
1805         dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1806               + 3) / 4) << CMD_HDR_CFL_OFF) |
1807               ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1808               (2 << CMD_HDR_SG_MOD_OFF);
1809         hdr->dw2 = cpu_to_le32(dw2);
1810
1811         hdr->transfer_tags = cpu_to_le32(slot->idx);
1812
1813         if (has_data)
1814                 prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1815                                         slot->n_elem);
1816
1817         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1818         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1819         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1820
1821         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1822                 sizeof(struct ssp_frame_hdr);
1823
1824         memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1825         if (!tmf) {
1826                 buf_cmd[9] = task->ssp_task.task_attr |
1827                                 (task->ssp_task.task_prio << 3);
1828                 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1829                                 task->ssp_task.cmd->cmd_len);
1830         } else {
1831                 buf_cmd[10] = tmf->tmf;
1832                 switch (tmf->tmf) {
1833                 case TMF_ABORT_TASK:
1834                 case TMF_QUERY_TASK:
1835                         buf_cmd[12] =
1836                                 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1837                         buf_cmd[13] =
1838                                 tmf->tag_of_task_to_be_managed & 0xff;
1839                         break;
1840                 default:
1841                         break;
1842                 }
1843         }
1844 }
1845
1846 #define TRANS_TX_ERR    0
1847 #define TRANS_RX_ERR    1
1848 #define DMA_TX_ERR              2
1849 #define SIPC_RX_ERR             3
1850 #define DMA_RX_ERR              4
1851
1852 #define DMA_TX_ERR_OFF  0
1853 #define DMA_TX_ERR_MSK  (0xffff << DMA_TX_ERR_OFF)
1854 #define SIPC_RX_ERR_OFF 16
1855 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1856
1857 static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
1858 {
1859         static const u8 trans_tx_err_code_prio[] = {
1860                 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
1861                 TRANS_TX_ERR_PHY_NOT_ENABLE,
1862                 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
1863                 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
1864                 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
1865                 RESERVED0,
1866                 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
1867                 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
1868                 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
1869                 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
1870                 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
1871                 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
1872                 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
1873                 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
1874                 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
1875                 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
1876                 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
1877                 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
1878                 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1879                 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
1880                 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
1881                 TRANS_TX_ERR_WITH_BREAK_REQUEST,
1882                 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
1883                 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
1884                 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
1885                 TRANS_TX_ERR_WITH_NAK_RECEVIED,
1886                 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
1887                 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
1888                 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
1889                 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
1890                 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
1891         };
1892         int index, i;
1893
1894         for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
1895                 index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
1896                 if (err_msk & (1 << index))
1897                         return trans_tx_err_code_prio[i];
1898         }
1899         return -1;
1900 }
1901
1902 static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
1903 {
1904         static const u8 trans_rx_err_code_prio[] = {
1905                 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
1906                 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
1907                 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
1908                 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
1909                 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
1910                 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
1911                 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
1912                 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
1913                 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
1914                 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1915                 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
1916                 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
1917                 TRANS_RX_ERR_WITH_BREAK_REQUEST,
1918                 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
1919                 RESERVED1,
1920                 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
1921                 TRANS_RX_ERR_WITH_DATA_LEN0,
1922                 TRANS_RX_ERR_WITH_BAD_HASH,
1923                 TRANS_RX_XRDY_WLEN_ZERO_ERR,
1924                 TRANS_RX_SSP_FRM_LEN_ERR,
1925                 RESERVED2,
1926                 RESERVED3,
1927                 RESERVED4,
1928                 RESERVED5,
1929                 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
1930                 TRANS_RX_SMP_FRM_LEN_ERR,
1931                 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
1932                 RESERVED6,
1933                 RESERVED7,
1934                 RESERVED8,
1935                 RESERVED9,
1936                 TRANS_RX_R_ERR,
1937         };
1938         int index, i;
1939
1940         for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
1941                 index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
1942                 if (err_msk & (1 << index))
1943                         return trans_rx_err_code_prio[i];
1944         }
1945         return -1;
1946 }
1947
1948 static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
1949 {
1950         static const u8 dma_tx_err_code_prio[] = {
1951                 DMA_TX_UNEXP_XFER_ERR,
1952                 DMA_TX_UNEXP_RETRANS_ERR,
1953                 DMA_TX_XFER_LEN_OVERFLOW,
1954                 DMA_TX_XFER_OFFSET_ERR,
1955                 DMA_TX_RAM_ECC_ERR,
1956                 DMA_TX_DIF_LEN_ALIGN_ERR,
1957                 DMA_TX_DIF_CRC_ERR,
1958                 DMA_TX_DIF_APP_ERR,
1959                 DMA_TX_DIF_RPP_ERR,
1960                 DMA_TX_DATA_SGL_OVERFLOW,
1961                 DMA_TX_DIF_SGL_OVERFLOW,
1962         };
1963         int index, i;
1964
1965         for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
1966                 index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
1967                 err_msk = err_msk & DMA_TX_ERR_MSK;
1968                 if (err_msk & (1 << index))
1969                         return dma_tx_err_code_prio[i];
1970         }
1971         return -1;
1972 }
1973
1974 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
1975 {
1976         static const u8 sipc_rx_err_code_prio[] = {
1977                 SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
1978                 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
1979                 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
1980                 SIPC_RX_WRSETUP_LEN_ODD_ERR,
1981                 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
1982                 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
1983                 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
1984                 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
1985                 SIPC_RX_SATA_UNEXP_FIS_ERR,
1986                 SIPC_RX_WRSETUP_ESTATUS_ERR,
1987                 SIPC_RX_DATA_UNDERFLOW_ERR,
1988         };
1989         int index, i;
1990
1991         for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
1992                 index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
1993                 err_msk = err_msk & SIPC_RX_ERR_MSK;
1994                 if (err_msk & (1 << (index + 0x10)))
1995                         return sipc_rx_err_code_prio[i];
1996         }
1997         return -1;
1998 }
1999
2000 static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
2001 {
2002         static const u8 dma_rx_err_code_prio[] = {
2003                 DMA_RX_UNKNOWN_FRM_ERR,
2004                 DMA_RX_DATA_LEN_OVERFLOW,
2005                 DMA_RX_DATA_LEN_UNDERFLOW,
2006                 DMA_RX_DATA_OFFSET_ERR,
2007                 RESERVED10,
2008                 DMA_RX_SATA_FRAME_TYPE_ERR,
2009                 DMA_RX_RESP_BUF_OVERFLOW,
2010                 DMA_RX_UNEXP_RETRANS_RESP_ERR,
2011                 DMA_RX_UNEXP_NORM_RESP_ERR,
2012                 DMA_RX_UNEXP_RDFRAME_ERR,
2013                 DMA_RX_PIO_DATA_LEN_ERR,
2014                 DMA_RX_RDSETUP_STATUS_ERR,
2015                 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
2016                 DMA_RX_RDSETUP_STATUS_BSY_ERR,
2017                 DMA_RX_RDSETUP_LEN_ODD_ERR,
2018                 DMA_RX_RDSETUP_LEN_ZERO_ERR,
2019                 DMA_RX_RDSETUP_LEN_OVER_ERR,
2020                 DMA_RX_RDSETUP_OFFSET_ERR,
2021                 DMA_RX_RDSETUP_ACTIVE_ERR,
2022                 DMA_RX_RDSETUP_ESTATUS_ERR,
2023                 DMA_RX_RAM_ECC_ERR,
2024                 DMA_RX_DIF_CRC_ERR,
2025                 DMA_RX_DIF_APP_ERR,
2026                 DMA_RX_DIF_RPP_ERR,
2027                 DMA_RX_DATA_SGL_OVERFLOW,
2028                 DMA_RX_DIF_SGL_OVERFLOW,
2029         };
2030         int index, i;
2031
2032         for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
2033                 index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
2034                 if (err_msk & (1 << index))
2035                         return dma_rx_err_code_prio[i];
2036         }
2037         return -1;
2038 }
2039
2040 /* by default, task resp is complete */
2041 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
2042                            struct sas_task *task,
2043                            struct hisi_sas_slot *slot,
2044                            int err_phase)
2045 {
2046         struct task_status_struct *ts = &task->task_status;
2047         struct hisi_sas_err_record_v2 *err_record =
2048                         hisi_sas_status_buf_addr_mem(slot);
2049         u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
2050         u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
2051         u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
2052         u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
2053         u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
2054         int error = -1;
2055
2056         if (err_phase == 1) {
2057                 /* error in TX phase, the priority of error is: DW2 > DW0 */
2058                 error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
2059                 if (error == -1)
2060                         error = parse_trans_tx_err_code_v2_hw(
2061                                         trans_tx_fail_type);
2062         } else if (err_phase == 2) {
2063                 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
2064                 error = parse_trans_rx_err_code_v2_hw(
2065                                         trans_rx_fail_type);
2066                 if (error == -1) {
2067                         error = parse_dma_rx_err_code_v2_hw(
2068                                         dma_rx_err_type);
2069                         if (error == -1)
2070                                 error = parse_sipc_rx_err_code_v2_hw(
2071                                                 sipc_rx_err_type);
2072                 }
2073         }
2074
2075         switch (task->task_proto) {
2076         case SAS_PROTOCOL_SSP:
2077         {
2078                 switch (error) {
2079                 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2080                 {
2081                         ts->stat = SAS_OPEN_REJECT;
2082                         ts->open_rej_reason = SAS_OREJ_NO_DEST;
2083                         break;
2084                 }
2085                 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2086                 {
2087                         ts->stat = SAS_OPEN_REJECT;
2088                         ts->open_rej_reason = SAS_OREJ_EPROTO;
2089                         break;
2090                 }
2091                 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2092                 {
2093                         ts->stat = SAS_OPEN_REJECT;
2094                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2095                         break;
2096                 }
2097                 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2098                 {
2099                         ts->stat = SAS_OPEN_REJECT;
2100                         ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2101                         break;
2102                 }
2103                 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2104                 {
2105                         ts->stat = SAS_OPEN_REJECT;
2106                         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2107                         break;
2108                 }
2109                 case DMA_RX_UNEXP_NORM_RESP_ERR:
2110                 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2111                 case DMA_RX_RESP_BUF_OVERFLOW:
2112                 {
2113                         ts->stat = SAS_OPEN_REJECT;
2114                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2115                         break;
2116                 }
2117                 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2118                 {
2119                         /* not sure */
2120                         ts->stat = SAS_DEV_NO_RESPONSE;
2121                         break;
2122                 }
2123                 case DMA_RX_DATA_LEN_OVERFLOW:
2124                 {
2125                         ts->stat = SAS_DATA_OVERRUN;
2126                         ts->residual = 0;
2127                         break;
2128                 }
2129                 case DMA_RX_DATA_LEN_UNDERFLOW:
2130                 {
2131                         ts->residual = trans_tx_fail_type;
2132                         ts->stat = SAS_DATA_UNDERRUN;
2133                         break;
2134                 }
2135                 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2136                 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2137                 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2138                 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2139                 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2140                 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2141                 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2142                 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2143                 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2144                 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2145                 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2146                 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2147                 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2148                 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2149                 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2150                 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2151                 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
2152                 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2153                 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2154                 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
2155                 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
2156                 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2157                 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2158                 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2159                 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2160                 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2161                 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2162                 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2163                 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2164                 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2165                 case TRANS_TX_ERR_FRAME_TXED:
2166                 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2167                 case TRANS_RX_ERR_WITH_DATA_LEN0:
2168                 case TRANS_RX_ERR_WITH_BAD_HASH:
2169                 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2170                 case TRANS_RX_SSP_FRM_LEN_ERR:
2171                 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2172                 case DMA_TX_DATA_SGL_OVERFLOW:
2173                 case DMA_TX_UNEXP_XFER_ERR:
2174                 case DMA_TX_UNEXP_RETRANS_ERR:
2175                 case DMA_TX_XFER_LEN_OVERFLOW:
2176                 case DMA_TX_XFER_OFFSET_ERR:
2177                 case SIPC_RX_DATA_UNDERFLOW_ERR:
2178                 case DMA_RX_DATA_SGL_OVERFLOW:
2179                 case DMA_RX_DATA_OFFSET_ERR:
2180                 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2181                 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2182                 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2183                 case DMA_RX_SATA_FRAME_TYPE_ERR:
2184                 case DMA_RX_UNKNOWN_FRM_ERR:
2185                 {
2186                         /* This will request a retry */
2187                         ts->stat = SAS_QUEUE_FULL;
2188                         slot->abort = 1;
2189                         break;
2190                 }
2191                 default:
2192                         break;
2193                 }
2194         }
2195                 break;
2196         case SAS_PROTOCOL_SMP:
2197                 ts->stat = SAM_STAT_CHECK_CONDITION;
2198                 break;
2199
2200         case SAS_PROTOCOL_SATA:
2201         case SAS_PROTOCOL_STP:
2202         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2203         {
2204                 switch (error) {
2205                 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2206                 {
2207                         ts->stat = SAS_OPEN_REJECT;
2208                         ts->open_rej_reason = SAS_OREJ_NO_DEST;
2209                         break;
2210                 }
2211                 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2212                 {
2213                         ts->resp = SAS_TASK_UNDELIVERED;
2214                         ts->stat = SAS_DEV_NO_RESPONSE;
2215                         break;
2216                 }
2217                 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2218                 {
2219                         ts->stat = SAS_OPEN_REJECT;
2220                         ts->open_rej_reason = SAS_OREJ_EPROTO;
2221                         break;
2222                 }
2223                 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2224                 {
2225                         ts->stat = SAS_OPEN_REJECT;
2226                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2227                         break;
2228                 }
2229                 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2230                 {
2231                         ts->stat = SAS_OPEN_REJECT;
2232                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2233                         break;
2234                 }
2235                 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2236                 {
2237                         ts->stat = SAS_OPEN_REJECT;
2238                         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2239                         break;
2240                 }
2241                 case DMA_RX_RESP_BUF_OVERFLOW:
2242                 case DMA_RX_UNEXP_NORM_RESP_ERR:
2243                 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2244                 {
2245                         ts->stat = SAS_OPEN_REJECT;
2246                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2247                         break;
2248                 }
2249                 case DMA_RX_DATA_LEN_OVERFLOW:
2250                 {
2251                         ts->stat = SAS_DATA_OVERRUN;
2252                         ts->residual = 0;
2253                         break;
2254                 }
2255                 case DMA_RX_DATA_LEN_UNDERFLOW:
2256                 {
2257                         ts->residual = trans_tx_fail_type;
2258                         ts->stat = SAS_DATA_UNDERRUN;
2259                         break;
2260                 }
2261                 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2262                 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2263                 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2264                 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2265                 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2266                 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2267                 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2268                 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2269                 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2270                 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2271                 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2272                 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2273                 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2274                 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2275                 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2276                 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2277                 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2278                 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2279                 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
2280                 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
2281                 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2282                 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2283                 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
2284                 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
2285                 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
2286                 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
2287                 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2288                 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2289                 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2290                 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2291                 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2292                 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2293                 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2294                 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2295                 case TRANS_RX_ERR_WITH_DATA_LEN0:
2296                 case TRANS_RX_ERR_WITH_BAD_HASH:
2297                 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2298                 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2299                 case DMA_TX_DATA_SGL_OVERFLOW:
2300                 case DMA_TX_UNEXP_XFER_ERR:
2301                 case DMA_TX_UNEXP_RETRANS_ERR:
2302                 case DMA_TX_XFER_LEN_OVERFLOW:
2303                 case DMA_TX_XFER_OFFSET_ERR:
2304                 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
2305                 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
2306                 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
2307                 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
2308                 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
2309                 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
2310                 case SIPC_RX_SATA_UNEXP_FIS_ERR:
2311                 case DMA_RX_DATA_SGL_OVERFLOW:
2312                 case DMA_RX_DATA_OFFSET_ERR:
2313                 case DMA_RX_SATA_FRAME_TYPE_ERR:
2314                 case DMA_RX_UNEXP_RDFRAME_ERR:
2315                 case DMA_RX_PIO_DATA_LEN_ERR:
2316                 case DMA_RX_RDSETUP_STATUS_ERR:
2317                 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
2318                 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
2319                 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2320                 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2321                 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2322                 case DMA_RX_RDSETUP_OFFSET_ERR:
2323                 case DMA_RX_RDSETUP_ACTIVE_ERR:
2324                 case DMA_RX_RDSETUP_ESTATUS_ERR:
2325                 case DMA_RX_UNKNOWN_FRM_ERR:
2326                 case TRANS_RX_SSP_FRM_LEN_ERR:
2327                 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
2328                 {
2329                         slot->abort = 1;
2330                         ts->stat = SAS_PHY_DOWN;
2331                         break;
2332                 }
2333                 default:
2334                 {
2335                         ts->stat = SAS_PROTO_RESPONSE;
2336                         break;
2337                 }
2338                 }
2339                 hisi_sas_sata_done(task, slot);
2340         }
2341                 break;
2342         default:
2343                 break;
2344         }
2345 }
2346
2347 static int
2348 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
2349 {
2350         struct sas_task *task = slot->task;
2351         struct hisi_sas_device *sas_dev;
2352         struct device *dev = hisi_hba->dev;
2353         struct task_status_struct *ts;
2354         struct domain_device *device;
2355         struct sas_ha_struct *ha;
2356         enum exec_status sts;
2357         struct hisi_sas_complete_v2_hdr *complete_queue =
2358                         hisi_hba->complete_hdr[slot->cmplt_queue];
2359         struct hisi_sas_complete_v2_hdr *complete_hdr =
2360                         &complete_queue[slot->cmplt_queue_slot];
2361         unsigned long flags;
2362         bool is_internal = slot->is_internal;
2363
2364         if (unlikely(!task || !task->lldd_task || !task->dev))
2365                 return -EINVAL;
2366
2367         ts = &task->task_status;
2368         device = task->dev;
2369         ha = device->port->ha;
2370         sas_dev = device->lldd_dev;
2371
2372         spin_lock_irqsave(&task->task_state_lock, flags);
2373         task->task_state_flags &=
2374                 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2375         spin_unlock_irqrestore(&task->task_state_lock, flags);
2376
2377         memset(ts, 0, sizeof(*ts));
2378         ts->resp = SAS_TASK_COMPLETE;
2379
2380         if (unlikely(!sas_dev)) {
2381                 dev_dbg(dev, "slot complete: port has no device\n");
2382                 ts->stat = SAS_PHY_DOWN;
2383                 goto out;
2384         }
2385
2386         /* Use SAS+TMF status codes */
2387         switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
2388                         >> CMPLT_HDR_ABORT_STAT_OFF) {
2389         case STAT_IO_ABORTED:
2390                 /* this io has been aborted by abort command */
2391                 ts->stat = SAS_ABORTED_TASK;
2392                 goto out;
2393         case STAT_IO_COMPLETE:
2394                 /* internal abort command complete */
2395                 ts->stat = TMF_RESP_FUNC_SUCC;
2396                 del_timer(&slot->internal_abort_timer);
2397                 goto out;
2398         case STAT_IO_NO_DEVICE:
2399                 ts->stat = TMF_RESP_FUNC_COMPLETE;
2400                 del_timer(&slot->internal_abort_timer);
2401                 goto out;
2402         case STAT_IO_NOT_VALID:
2403                 /* abort single io, controller don't find
2404                  * the io need to abort
2405                  */
2406                 ts->stat = TMF_RESP_FUNC_FAILED;
2407                 del_timer(&slot->internal_abort_timer);
2408                 goto out;
2409         default:
2410                 break;
2411         }
2412
2413         if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
2414                 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2415                 u32 err_phase = (complete_hdr->dw0 & CMPLT_HDR_ERR_PHASE_MSK)
2416                                 >> CMPLT_HDR_ERR_PHASE_OFF;
2417                 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2418
2419                 /* Analyse error happens on which phase TX or RX */
2420                 if (ERR_ON_TX_PHASE(err_phase))
2421                         slot_err_v2_hw(hisi_hba, task, slot, 1);
2422                 else if (ERR_ON_RX_PHASE(err_phase))
2423                         slot_err_v2_hw(hisi_hba, task, slot, 2);
2424
2425                 if (ts->stat != SAS_DATA_UNDERRUN)
2426                         dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d "
2427                                 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
2428                                 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
2429                                 slot->idx, task, sas_dev->device_id,
2430                                 complete_hdr->dw0, complete_hdr->dw1,
2431                                 complete_hdr->act, complete_hdr->dw3,
2432                                 error_info[0], error_info[1],
2433                                 error_info[2], error_info[3]);
2434
2435                 if (unlikely(slot->abort))
2436                         return ts->stat;
2437                 goto out;
2438         }
2439
2440         switch (task->task_proto) {
2441         case SAS_PROTOCOL_SSP:
2442         {
2443                 struct hisi_sas_status_buffer *status_buffer =
2444                                 hisi_sas_status_buf_addr_mem(slot);
2445                 struct ssp_response_iu *iu = (struct ssp_response_iu *)
2446                                 &status_buffer->iu[0];
2447
2448                 sas_ssp_task_response(dev, task, iu);
2449                 break;
2450         }
2451         case SAS_PROTOCOL_SMP:
2452         {
2453                 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2454                 void *to;
2455
2456                 ts->stat = SAM_STAT_GOOD;
2457                 to = kmap_atomic(sg_page(sg_resp));
2458
2459                 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
2460                              DMA_FROM_DEVICE);
2461                 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2462                              DMA_TO_DEVICE);
2463                 memcpy(to + sg_resp->offset,
2464                        hisi_sas_status_buf_addr_mem(slot) +
2465                        sizeof(struct hisi_sas_err_record),
2466                        sg_dma_len(sg_resp));
2467                 kunmap_atomic(to);
2468                 break;
2469         }
2470         case SAS_PROTOCOL_SATA:
2471         case SAS_PROTOCOL_STP:
2472         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2473         {
2474                 ts->stat = SAM_STAT_GOOD;
2475                 hisi_sas_sata_done(task, slot);
2476                 break;
2477         }
2478         default:
2479                 ts->stat = SAM_STAT_CHECK_CONDITION;
2480                 break;
2481         }
2482
2483         if (!slot->port->port_attached) {
2484                 dev_warn(dev, "slot complete: port %d has removed\n",
2485                         slot->port->sas_port.id);
2486                 ts->stat = SAS_PHY_DOWN;
2487         }
2488
2489 out:
2490         sts = ts->stat;
2491         spin_lock_irqsave(&task->task_state_lock, flags);
2492         if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
2493                 spin_unlock_irqrestore(&task->task_state_lock, flags);
2494                 dev_info(dev, "slot complete: task(%p) aborted\n", task);
2495                 return SAS_ABORTED_TASK;
2496         }
2497         task->task_state_flags |= SAS_TASK_STATE_DONE;
2498         spin_unlock_irqrestore(&task->task_state_lock, flags);
2499         hisi_sas_slot_task_free(hisi_hba, task, slot);
2500
2501         if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
2502                 spin_lock_irqsave(&device->done_lock, flags);
2503                 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
2504                         spin_unlock_irqrestore(&device->done_lock, flags);
2505                         dev_info(dev, "slot complete: task(%p) ignored\n ",
2506                                  task);
2507                         return sts;
2508                 }
2509                 spin_unlock_irqrestore(&device->done_lock, flags);
2510         }
2511
2512         if (task->task_done)
2513                 task->task_done(task);
2514
2515         return sts;
2516 }
2517
2518 static void prep_ata_v2_hw(struct hisi_hba *hisi_hba,
2519                           struct hisi_sas_slot *slot)
2520 {
2521         struct sas_task *task = slot->task;
2522         struct domain_device *device = task->dev;
2523         struct domain_device *parent_dev = device->parent;
2524         struct hisi_sas_device *sas_dev = device->lldd_dev;
2525         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2526         struct asd_sas_port *sas_port = device->port;
2527         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
2528         struct hisi_sas_tmf_task *tmf = slot->tmf;
2529         u8 *buf_cmd;
2530         int has_data = 0, hdr_tag = 0;
2531         u32 dw1 = 0, dw2 = 0;
2532
2533         /* create header */
2534         /* dw0 */
2535         hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
2536         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
2537                 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
2538         else
2539                 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
2540
2541         if (tmf && tmf->force_phy) {
2542                 hdr->dw0 |= CMD_HDR_FORCE_PHY_MSK;
2543                 hdr->dw0 |= cpu_to_le32((1 << tmf->phy_id)
2544                                 << CMD_HDR_PHY_ID_OFF);
2545         }
2546
2547         /* dw1 */
2548         switch (task->data_dir) {
2549         case DMA_TO_DEVICE:
2550                 has_data = 1;
2551                 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
2552                 break;
2553         case DMA_FROM_DEVICE:
2554                 has_data = 1;
2555                 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
2556                 break;
2557         default:
2558                 dw1 &= ~CMD_HDR_DIR_MSK;
2559         }
2560
2561         if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
2562                         (task->ata_task.fis.control & ATA_SRST))
2563                 dw1 |= 1 << CMD_HDR_RESET_OFF;
2564
2565         dw1 |= (hisi_sas_get_ata_protocol(
2566                 &task->ata_task.fis, task->data_dir))
2567                 << CMD_HDR_FRAME_TYPE_OFF;
2568         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
2569         hdr->dw1 = cpu_to_le32(dw1);
2570
2571         /* dw2 */
2572         if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
2573                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
2574                 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
2575         }
2576
2577         dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
2578                         2 << CMD_HDR_SG_MOD_OFF;
2579         hdr->dw2 = cpu_to_le32(dw2);
2580
2581         /* dw3 */
2582         hdr->transfer_tags = cpu_to_le32(slot->idx);
2583
2584         if (has_data)
2585                 prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
2586                                         slot->n_elem);
2587
2588         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
2589         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
2590         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
2591
2592         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
2593
2594         if (likely(!task->ata_task.device_control_reg_update))
2595                 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
2596         /* fill in command FIS */
2597         memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
2598 }
2599
2600 static void hisi_sas_internal_abort_quirk_timeout(struct timer_list *t)
2601 {
2602         struct hisi_sas_slot *slot = from_timer(slot, t, internal_abort_timer);
2603         struct hisi_sas_port *port = slot->port;
2604         struct asd_sas_port *asd_sas_port;
2605         struct asd_sas_phy *sas_phy;
2606
2607         if (!port)
2608                 return;
2609
2610         asd_sas_port = &port->sas_port;
2611
2612         /* Kick the hardware - send break command */
2613         list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
2614                 struct hisi_sas_phy *phy = sas_phy->lldd_phy;
2615                 struct hisi_hba *hisi_hba = phy->hisi_hba;
2616                 int phy_no = sas_phy->id;
2617                 u32 link_dfx2;
2618
2619                 link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
2620                 if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
2621                     (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
2622                         u32 txid_auto;
2623
2624                         txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
2625                                                         TXID_AUTO);
2626                         txid_auto |= TXID_AUTO_CTB_MSK;
2627                         hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2628                                              txid_auto);
2629                         return;
2630                 }
2631         }
2632 }
2633
2634 static void prep_abort_v2_hw(struct hisi_hba *hisi_hba,
2635                 struct hisi_sas_slot *slot,
2636                 int device_id, int abort_flag, int tag_to_abort)
2637 {
2638         struct sas_task *task = slot->task;
2639         struct domain_device *dev = task->dev;
2640         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2641         struct hisi_sas_port *port = slot->port;
2642         struct timer_list *timer = &slot->internal_abort_timer;
2643
2644         /* setup the quirk timer */
2645         timer_setup(timer, hisi_sas_internal_abort_quirk_timeout, 0);
2646         /* Set the timeout to 10ms less than internal abort timeout */
2647         mod_timer(timer, jiffies + msecs_to_jiffies(100));
2648
2649         /* dw0 */
2650         hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
2651                                (port->id << CMD_HDR_PORT_OFF) |
2652                                (dev_is_sata(dev) <<
2653                                 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
2654                                (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
2655
2656         /* dw1 */
2657         hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
2658
2659         /* dw7 */
2660         hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
2661         hdr->transfer_tags = cpu_to_le32(slot->idx);
2662 }
2663
2664 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2665 {
2666         int i, res = IRQ_HANDLED;
2667         u32 port_id, link_rate;
2668         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2669         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2670         struct device *dev = hisi_hba->dev;
2671         u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
2672         struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
2673         unsigned long flags;
2674
2675         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
2676
2677         if (is_sata_phy_v2_hw(hisi_hba, phy_no))
2678                 goto end;
2679
2680         if (phy_no == 8) {
2681                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2682
2683                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2684                           PORT_STATE_PHY8_PORT_NUM_OFF;
2685                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2686                             PORT_STATE_PHY8_CONN_RATE_OFF;
2687         } else {
2688                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2689                 port_id = (port_id >> (4 * phy_no)) & 0xf;
2690                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2691                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2692         }
2693
2694         if (port_id == 0xf) {
2695                 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
2696                 res = IRQ_NONE;
2697                 goto end;
2698         }
2699
2700         for (i = 0; i < 6; i++) {
2701                 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
2702                                                RX_IDAF_DWORD0 + (i * 4));
2703                 frame_rcvd[i] = __swab32(idaf);
2704         }
2705
2706         sas_phy->linkrate = link_rate;
2707         sas_phy->oob_mode = SAS_OOB_MODE;
2708         memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
2709         dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2710         phy->port_id = port_id;
2711         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2712         phy->phy_type |= PORT_TYPE_SAS;
2713         phy->phy_attached = 1;
2714         phy->identify.device_type = id->dev_type;
2715         phy->frame_rcvd_size =  sizeof(struct sas_identify_frame);
2716         if (phy->identify.device_type == SAS_END_DEVICE)
2717                 phy->identify.target_port_protocols =
2718                         SAS_PROTOCOL_SSP;
2719         else if (phy->identify.device_type != SAS_PHY_UNUSED) {
2720                 phy->identify.target_port_protocols =
2721                         SAS_PROTOCOL_SMP;
2722                 if (!timer_pending(&hisi_hba->timer))
2723                         set_link_timer_quirk(hisi_hba);
2724         }
2725         hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
2726         spin_lock_irqsave(&phy->lock, flags);
2727         if (phy->reset_completion) {
2728                 phy->in_reset = 0;
2729                 complete(phy->reset_completion);
2730         }
2731         spin_unlock_irqrestore(&phy->lock, flags);
2732
2733 end:
2734         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2735                              CHL_INT0_SL_PHY_ENABLE_MSK);
2736         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
2737
2738         return res;
2739 }
2740
2741 static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
2742 {
2743         u32 port_state;
2744
2745         port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2746         if (port_state & 0x1ff)
2747                 return true;
2748
2749         return false;
2750 }
2751
2752 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2753 {
2754         u32 phy_state, sl_ctrl, txid_auto;
2755         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2756         struct hisi_sas_port *port = phy->port;
2757         struct device *dev = hisi_hba->dev;
2758
2759         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
2760
2761         phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2762         dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
2763         hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
2764
2765         sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
2766         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
2767                              sl_ctrl & ~SL_CONTROL_CTA_MSK);
2768         if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
2769                 if (!check_any_wideports_v2_hw(hisi_hba) &&
2770                                 timer_pending(&hisi_hba->timer))
2771                         del_timer(&hisi_hba->timer);
2772
2773         txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
2774         hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2775                              txid_auto | TXID_AUTO_CT3_MSK);
2776
2777         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
2778         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
2779
2780         return IRQ_HANDLED;
2781 }
2782
2783 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
2784 {
2785         struct hisi_hba *hisi_hba = p;
2786         u32 irq_msk;
2787         int phy_no = 0;
2788         irqreturn_t res = IRQ_NONE;
2789
2790         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
2791                    >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
2792         while (irq_msk) {
2793                 if (irq_msk  & 1) {
2794                         u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
2795                                             CHL_INT0);
2796
2797                         switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
2798                                         CHL_INT0_SL_PHY_ENABLE_MSK)) {
2799
2800                         case CHL_INT0_SL_PHY_ENABLE_MSK:
2801                                 /* phy up */
2802                                 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2803                                     IRQ_HANDLED)
2804                                         res = IRQ_HANDLED;
2805                                 break;
2806
2807                         case CHL_INT0_NOT_RDY_MSK:
2808                                 /* phy down */
2809                                 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2810                                     IRQ_HANDLED)
2811                                         res = IRQ_HANDLED;
2812                                 break;
2813
2814                         case (CHL_INT0_NOT_RDY_MSK |
2815                                         CHL_INT0_SL_PHY_ENABLE_MSK):
2816                                 reg_value = hisi_sas_read32(hisi_hba,
2817                                                 PHY_STATE);
2818                                 if (reg_value & BIT(phy_no)) {
2819                                         /* phy up */
2820                                         if (phy_up_v2_hw(phy_no, hisi_hba) ==
2821                                             IRQ_HANDLED)
2822                                                 res = IRQ_HANDLED;
2823                                 } else {
2824                                         /* phy down */
2825                                         if (phy_down_v2_hw(phy_no, hisi_hba) ==
2826                                             IRQ_HANDLED)
2827                                                 res = IRQ_HANDLED;
2828                                 }
2829                                 break;
2830
2831                         default:
2832                                 break;
2833                         }
2834
2835                 }
2836                 irq_msk >>= 1;
2837                 phy_no++;
2838         }
2839
2840         return res;
2841 }
2842
2843 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2844 {
2845         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2846         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2847         struct sas_ha_struct *sas_ha = &hisi_hba->sha;
2848         u32 bcast_status;
2849
2850         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
2851         bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
2852         if ((bcast_status & RX_BCAST_CHG_MSK) &&
2853             !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
2854                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2855         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2856                              CHL_INT0_SL_RX_BCST_ACK_MSK);
2857         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
2858 }
2859
2860 static const struct hisi_sas_hw_error port_ecc_axi_error[] = {
2861         {
2862                 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_ERR_OFF),
2863                 .msg = "dmac_tx_ecc_bad_err",
2864         },
2865         {
2866                 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_ERR_OFF),
2867                 .msg = "dmac_rx_ecc_bad_err",
2868         },
2869         {
2870                 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
2871                 .msg = "dma_tx_axi_wr_err",
2872         },
2873         {
2874                 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
2875                 .msg = "dma_tx_axi_rd_err",
2876         },
2877         {
2878                 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
2879                 .msg = "dma_rx_axi_wr_err",
2880         },
2881         {
2882                 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
2883                 .msg = "dma_rx_axi_rd_err",
2884         },
2885 };
2886
2887 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
2888 {
2889         struct hisi_hba *hisi_hba = p;
2890         struct device *dev = hisi_hba->dev;
2891         u32 ent_msk, ent_tmp, irq_msk;
2892         int phy_no = 0;
2893
2894         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2895         ent_tmp = ent_msk;
2896         ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
2897         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
2898
2899         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
2900                         HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
2901
2902         while (irq_msk) {
2903                 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2904                                                      CHL_INT0);
2905                 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2906                                                      CHL_INT1);
2907                 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2908                                                      CHL_INT2);
2909
2910                 if ((irq_msk & (1 << phy_no)) && irq_value1) {
2911                         int i;
2912
2913                         for (i = 0; i < ARRAY_SIZE(port_ecc_axi_error); i++) {
2914                                 const struct hisi_sas_hw_error *error =
2915                                                 &port_ecc_axi_error[i];
2916
2917                                 if (!(irq_value1 & error->irq_msk))
2918                                         continue;
2919
2920                                 dev_warn(dev, "%s error (phy%d 0x%x) found!\n",
2921                                         error->msg, phy_no, irq_value1);
2922                                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2923                         }
2924
2925                         hisi_sas_phy_write32(hisi_hba, phy_no,
2926                                              CHL_INT1, irq_value1);
2927                 }
2928
2929                 if ((irq_msk & (1 << phy_no)) && irq_value2) {
2930                         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2931
2932                         if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
2933                                 dev_warn(dev, "phy%d identify timeout\n",
2934                                                 phy_no);
2935                                 hisi_sas_notify_phy_event(phy,
2936                                                 HISI_PHYE_LINK_RESET);
2937                         }
2938
2939                         hisi_sas_phy_write32(hisi_hba, phy_no,
2940                                                  CHL_INT2, irq_value2);
2941                 }
2942
2943                 if ((irq_msk & (1 << phy_no)) && irq_value0) {
2944                         if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2945                                 phy_bcast_v2_hw(phy_no, hisi_hba);
2946
2947                         hisi_sas_phy_write32(hisi_hba, phy_no,
2948                                         CHL_INT0, irq_value0
2949                                         & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2950                                         & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2951                                         & (~CHL_INT0_NOT_RDY_MSK));
2952                 }
2953                 irq_msk &= ~(1 << phy_no);
2954                 phy_no++;
2955         }
2956
2957         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2958
2959         return IRQ_HANDLED;
2960 }
2961
2962 static void
2963 one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
2964 {
2965         struct device *dev = hisi_hba->dev;
2966         const struct hisi_sas_hw_error *ecc_error;
2967         u32 val;
2968         int i;
2969
2970         for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) {
2971                 ecc_error = &one_bit_ecc_errors[i];
2972                 if (irq_value & ecc_error->irq_msk) {
2973                         val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2974                         val &= ecc_error->msk;
2975                         val >>= ecc_error->shift;
2976                         dev_warn(dev, ecc_error->msg, val);
2977                 }
2978         }
2979 }
2980
2981 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
2982                 u32 irq_value)
2983 {
2984         struct device *dev = hisi_hba->dev;
2985         const struct hisi_sas_hw_error *ecc_error;
2986         u32 val;
2987         int i;
2988
2989         for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
2990                 ecc_error = &multi_bit_ecc_errors[i];
2991                 if (irq_value & ecc_error->irq_msk) {
2992                         val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2993                         val &= ecc_error->msk;
2994                         val >>= ecc_error->shift;
2995                         dev_err(dev, ecc_error->msg, irq_value, val);
2996                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2997                 }
2998         }
2999
3000         return;
3001 }
3002
3003 static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
3004 {
3005         struct hisi_hba *hisi_hba = p;
3006         u32 irq_value, irq_msk;
3007
3008         irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
3009         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
3010
3011         irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
3012         if (irq_value) {
3013                 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
3014                 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
3015         }
3016
3017         hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
3018         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
3019
3020         return IRQ_HANDLED;
3021 }
3022
3023 static const struct hisi_sas_hw_error axi_error[] = {
3024         { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
3025         { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
3026         { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
3027         { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
3028         { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
3029         { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
3030         { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
3031         { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
3032         {},
3033 };
3034
3035 static const struct hisi_sas_hw_error fifo_error[] = {
3036         { .msk = BIT(8),  .msg = "CQE_WINFO_FIFO" },
3037         { .msk = BIT(9),  .msg = "CQE_MSG_FIFIO" },
3038         { .msk = BIT(10), .msg = "GETDQE_FIFO" },
3039         { .msk = BIT(11), .msg = "CMDP_FIFO" },
3040         { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
3041         {},
3042 };
3043
3044 static const struct hisi_sas_hw_error fatal_axi_errors[] = {
3045         {
3046                 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
3047                 .msg = "write pointer and depth",
3048         },
3049         {
3050                 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
3051                 .msg = "iptt no match slot",
3052         },
3053         {
3054                 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
3055                 .msg = "read pointer and depth",
3056         },
3057         {
3058                 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
3059                 .reg = HGC_AXI_FIFO_ERR_INFO,
3060                 .sub = axi_error,
3061         },
3062         {
3063                 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
3064                 .reg = HGC_AXI_FIFO_ERR_INFO,
3065                 .sub = fifo_error,
3066         },
3067         {
3068                 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
3069                 .msg = "LM add/fetch list",
3070         },
3071         {
3072                 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
3073                 .msg = "SAS_HGC_ABT fetch LM list",
3074         },
3075 };
3076
3077 static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
3078 {
3079         struct hisi_hba *hisi_hba = p;
3080         u32 irq_value, irq_msk, err_value;
3081         struct device *dev = hisi_hba->dev;
3082         const struct hisi_sas_hw_error *axi_error;
3083         int i;
3084
3085         irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
3086         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
3087
3088         irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
3089
3090         for (i = 0; i < ARRAY_SIZE(fatal_axi_errors); i++) {
3091                 axi_error = &fatal_axi_errors[i];
3092                 if (!(irq_value & axi_error->irq_msk))
3093                         continue;
3094
3095                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3096                                  1 << axi_error->shift);
3097                 if (axi_error->sub) {
3098                         const struct hisi_sas_hw_error *sub = axi_error->sub;
3099
3100                         err_value = hisi_sas_read32(hisi_hba, axi_error->reg);
3101                         for (; sub->msk || sub->msg; sub++) {
3102                                 if (!(err_value & sub->msk))
3103                                         continue;
3104                                 dev_err(dev, "%s (0x%x) found!\n",
3105                                          sub->msg, irq_value);
3106                                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3107                         }
3108                 } else {
3109                         dev_err(dev, "%s (0x%x) found!\n",
3110                                  axi_error->msg, irq_value);
3111                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3112                 }
3113         }
3114
3115         if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
3116                 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
3117                 u32 dev_id = reg_val & ITCT_DEV_MSK;
3118                 struct hisi_sas_device *sas_dev = &hisi_hba->devices[dev_id];
3119
3120                 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
3121                 dev_dbg(dev, "clear ITCT ok\n");
3122                 complete(sas_dev->completion);
3123         }
3124
3125         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value);
3126         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
3127
3128         return IRQ_HANDLED;
3129 }
3130
3131 static void cq_tasklet_v2_hw(unsigned long val)
3132 {
3133         struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
3134         struct hisi_hba *hisi_hba = cq->hisi_hba;
3135         struct hisi_sas_slot *slot;
3136         struct hisi_sas_itct *itct;
3137         struct hisi_sas_complete_v2_hdr *complete_queue;
3138         u32 rd_point = cq->rd_point, wr_point, dev_id;
3139         int queue = cq->id;
3140
3141         if (unlikely(hisi_hba->reject_stp_links_msk))
3142                 phys_try_accept_stp_links_v2_hw(hisi_hba);
3143
3144         complete_queue = hisi_hba->complete_hdr[queue];
3145
3146         wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
3147                                    (0x14 * queue));
3148
3149         while (rd_point != wr_point) {
3150                 struct hisi_sas_complete_v2_hdr *complete_hdr;
3151                 int iptt;
3152
3153                 complete_hdr = &complete_queue[rd_point];
3154
3155                 /* Check for NCQ completion */
3156                 if (complete_hdr->act) {
3157                         u32 act_tmp = complete_hdr->act;
3158                         int ncq_tag_count = ffs(act_tmp);
3159
3160                         dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
3161                                  CMPLT_HDR_DEV_ID_OFF;
3162                         itct = &hisi_hba->itct[dev_id];
3163
3164                         /* The NCQ tags are held in the itct header */
3165                         while (ncq_tag_count) {
3166                                 __le64 *ncq_tag = &itct->qw4_15[0];
3167
3168                                 ncq_tag_count -= 1;
3169                                 iptt = (ncq_tag[ncq_tag_count / 5]
3170                                         >> (ncq_tag_count % 5) * 12) & 0xfff;
3171
3172                                 slot = &hisi_hba->slot_info[iptt];
3173                                 slot->cmplt_queue_slot = rd_point;
3174                                 slot->cmplt_queue = queue;
3175                                 slot_complete_v2_hw(hisi_hba, slot);
3176
3177                                 act_tmp &= ~(1 << ncq_tag_count);
3178                                 ncq_tag_count = ffs(act_tmp);
3179                         }
3180                 } else {
3181                         iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
3182                         slot = &hisi_hba->slot_info[iptt];
3183                         slot->cmplt_queue_slot = rd_point;
3184                         slot->cmplt_queue = queue;
3185                         slot_complete_v2_hw(hisi_hba, slot);
3186                 }
3187
3188                 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
3189                         rd_point = 0;
3190         }
3191
3192         /* update rd_point */
3193         cq->rd_point = rd_point;
3194         hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
3195 }
3196
3197 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
3198 {
3199         struct hisi_sas_cq *cq = p;
3200         struct hisi_hba *hisi_hba = cq->hisi_hba;
3201         int queue = cq->id;
3202
3203         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
3204
3205         tasklet_schedule(&cq->tasklet);
3206
3207         return IRQ_HANDLED;
3208 }
3209
3210 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
3211 {
3212         struct hisi_sas_phy *phy = p;
3213         struct hisi_hba *hisi_hba = phy->hisi_hba;
3214         struct asd_sas_phy *sas_phy = &phy->sas_phy;
3215         struct device *dev = hisi_hba->dev;
3216         struct  hisi_sas_initial_fis *initial_fis;
3217         struct dev_to_host_fis *fis;
3218         u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
3219         irqreturn_t res = IRQ_HANDLED;
3220         u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
3221         unsigned long flags;
3222         int phy_no, offset;
3223
3224         phy_no = sas_phy->id;
3225         initial_fis = &hisi_hba->initial_fis[phy_no];
3226         fis = &initial_fis->fis;
3227
3228         offset = 4 * (phy_no / 4);
3229         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
3230         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
3231                          ent_msk | 1 << ((phy_no % 4) * 8));
3232
3233         ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
3234         ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
3235                              (phy_no % 4)));
3236         ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
3237         if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
3238                 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
3239                 res = IRQ_NONE;
3240                 goto end;
3241         }
3242
3243         /* check ERR bit of Status Register */
3244         if (fis->status & ATA_ERR) {
3245                 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
3246                                 fis->status);
3247                 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
3248                 res = IRQ_NONE;
3249                 goto end;
3250         }
3251
3252         if (unlikely(phy_no == 8)) {
3253                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
3254
3255                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
3256                           PORT_STATE_PHY8_PORT_NUM_OFF;
3257                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
3258                             PORT_STATE_PHY8_CONN_RATE_OFF;
3259         } else {
3260                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
3261                 port_id = (port_id >> (4 * phy_no)) & 0xf;
3262                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
3263                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
3264         }
3265
3266         if (port_id == 0xf) {
3267                 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
3268                 res = IRQ_NONE;
3269                 goto end;
3270         }
3271
3272         sas_phy->linkrate = link_rate;
3273         hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
3274                                                 HARD_PHY_LINKRATE);
3275         phy->maximum_linkrate = hard_phy_linkrate & 0xf;
3276         phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
3277
3278         sas_phy->oob_mode = SATA_OOB_MODE;
3279         /* Make up some unique SAS address */
3280         attached_sas_addr[0] = 0x50;
3281         attached_sas_addr[6] = hisi_hba->shost->host_no;
3282         attached_sas_addr[7] = phy_no;
3283         memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
3284         memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
3285         dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
3286         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
3287         phy->port_id = port_id;
3288         phy->phy_type |= PORT_TYPE_SATA;
3289         phy->phy_attached = 1;
3290         phy->identify.device_type = SAS_SATA_DEV;
3291         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3292         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3293         hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
3294
3295         spin_lock_irqsave(&phy->lock, flags);
3296         if (phy->reset_completion) {
3297                 phy->in_reset = 0;
3298                 complete(phy->reset_completion);
3299         }
3300         spin_unlock_irqrestore(&phy->lock, flags);
3301 end:
3302         hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
3303         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
3304
3305         return res;
3306 }
3307
3308 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
3309         int_phy_updown_v2_hw,
3310         int_chnl_int_v2_hw,
3311 };
3312
3313 static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
3314         fatal_ecc_int_v2_hw,
3315         fatal_axi_int_v2_hw
3316 };
3317
3318 /**
3319  * There is a limitation in the hip06 chipset that we need
3320  * to map in all mbigen interrupts, even if they are not used.
3321  */
3322 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
3323 {
3324         struct platform_device *pdev = hisi_hba->platform_dev;
3325         struct device *dev = &pdev->dev;
3326         int irq, rc, irq_map[128];
3327         int i, phy_no, fatal_no, queue_no, k;
3328
3329         for (i = 0; i < 128; i++)
3330                 irq_map[i] = platform_get_irq(pdev, i);
3331
3332         for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
3333                 irq = irq_map[i + 1]; /* Phy up/down is irq1 */
3334                 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
3335                                       DRV_NAME " phy", hisi_hba);
3336                 if (rc) {
3337                         dev_err(dev, "irq init: could not request "
3338                                 "phy interrupt %d, rc=%d\n",
3339                                 irq, rc);
3340                         rc = -ENOENT;
3341                         goto free_phy_int_irqs;
3342                 }
3343         }
3344
3345         for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
3346                 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
3347
3348                 irq = irq_map[phy_no + 72];
3349                 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
3350                                       DRV_NAME " sata", phy);
3351                 if (rc) {
3352                         dev_err(dev, "irq init: could not request "
3353                                 "sata interrupt %d, rc=%d\n",
3354                                 irq, rc);
3355                         rc = -ENOENT;
3356                         goto free_sata_int_irqs;
3357                 }
3358         }
3359
3360         for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
3361                 irq = irq_map[fatal_no + 81];
3362                 rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
3363                                       DRV_NAME " fatal", hisi_hba);
3364                 if (rc) {
3365                         dev_err(dev,
3366                                 "irq init: could not request fatal interrupt %d, rc=%d\n",
3367                                 irq, rc);
3368                         rc = -ENOENT;
3369                         goto free_fatal_int_irqs;
3370                 }
3371         }
3372
3373         for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
3374                 struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
3375                 struct tasklet_struct *t = &cq->tasklet;
3376
3377                 irq = irq_map[queue_no + 96];
3378                 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
3379                                       DRV_NAME " cq", cq);
3380                 if (rc) {
3381                         dev_err(dev,
3382                                 "irq init: could not request cq interrupt %d, rc=%d\n",
3383                                 irq, rc);
3384                         rc = -ENOENT;
3385                         goto free_cq_int_irqs;
3386                 }
3387                 tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq);
3388         }
3389
3390         return 0;
3391
3392 free_cq_int_irqs:
3393         for (k = 0; k < queue_no; k++) {
3394                 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
3395
3396                 free_irq(irq_map[k + 96], cq);
3397                 tasklet_kill(&cq->tasklet);
3398         }
3399 free_fatal_int_irqs:
3400         for (k = 0; k < fatal_no; k++)
3401                 free_irq(irq_map[k + 81], hisi_hba);
3402 free_sata_int_irqs:
3403         for (k = 0; k < phy_no; k++) {
3404                 struct hisi_sas_phy *phy = &hisi_hba->phy[k];
3405
3406                 free_irq(irq_map[k + 72], phy);
3407         }
3408 free_phy_int_irqs:
3409         for (k = 0; k < i; k++)
3410                 free_irq(irq_map[k + 1], hisi_hba);
3411         return rc;
3412 }
3413
3414 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
3415 {
3416         int rc;
3417
3418         memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap));
3419
3420         rc = hw_init_v2_hw(hisi_hba);
3421         if (rc)
3422                 return rc;
3423
3424         rc = interrupt_init_v2_hw(hisi_hba);
3425         if (rc)
3426                 return rc;
3427
3428         return 0;
3429 }
3430
3431 static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
3432 {
3433         struct platform_device *pdev = hisi_hba->platform_dev;
3434         int i;
3435
3436         for (i = 0; i < hisi_hba->queue_count; i++)
3437                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
3438
3439         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
3440         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
3441         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
3442         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
3443
3444         for (i = 0; i < hisi_hba->n_phy; i++) {
3445                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
3446                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
3447         }
3448
3449         for (i = 0; i < 128; i++)
3450                 synchronize_irq(platform_get_irq(pdev, i));
3451 }
3452
3453
3454 static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba)
3455 {
3456         return hisi_sas_read32(hisi_hba, PHY_STATE);
3457 }
3458
3459 static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
3460 {
3461         struct device *dev = hisi_hba->dev;
3462         int rc, cnt;
3463
3464         interrupt_disable_v2_hw(hisi_hba);
3465         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
3466         hisi_sas_kill_tasklets(hisi_hba);
3467
3468         hisi_sas_stop_phys(hisi_hba);
3469
3470         mdelay(10);
3471
3472         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
3473
3474         /* wait until bus idle */
3475         cnt = 0;
3476         while (1) {
3477                 u32 status = hisi_sas_read32_relaxed(hisi_hba,
3478                                 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
3479
3480                 if (status == 0x3)
3481                         break;
3482
3483                 udelay(10);
3484                 if (cnt++ > 10) {
3485                         dev_err(dev, "wait axi bus state to idle timeout!\n");
3486                         return -1;
3487                 }
3488         }
3489
3490         hisi_sas_init_mem(hisi_hba);
3491
3492         rc = hw_init_v2_hw(hisi_hba);
3493         if (rc)
3494                 return rc;
3495
3496         phys_reject_stp_links_v2_hw(hisi_hba);
3497
3498         return 0;
3499 }
3500
3501 static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type,
3502                         u8 reg_index, u8 reg_count, u8 *write_data)
3503 {
3504         struct device *dev = hisi_hba->dev;
3505         int phy_no, count;
3506
3507         if (!hisi_hba->sgpio_regs)
3508                 return -EOPNOTSUPP;
3509
3510         switch (reg_type) {
3511         case SAS_GPIO_REG_TX:
3512                 count = reg_count * 4;
3513                 count = min(count, hisi_hba->n_phy);
3514
3515                 for (phy_no = 0; phy_no < count; phy_no++) {
3516                         /*
3517                          * GPIO_TX[n] register has the highest numbered drive
3518                          * of the four in the first byte and the lowest
3519                          * numbered drive in the fourth byte.
3520                          * See SFF-8485 Rev. 0.7 Table 24.
3521                          */
3522                         void __iomem  *reg_addr = hisi_hba->sgpio_regs +
3523                                         reg_index * 4 + phy_no;
3524                         int data_idx = phy_no + 3 - (phy_no % 4) * 2;
3525
3526                         writeb(write_data[data_idx], reg_addr);
3527                 }
3528
3529                 break;
3530         default:
3531                 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
3532                                 reg_type);
3533                 return -EINVAL;
3534         }
3535
3536         return 0;
3537 }
3538
3539 static void wait_cmds_complete_timeout_v2_hw(struct hisi_hba *hisi_hba,
3540                                              int delay_ms, int timeout_ms)
3541 {
3542         struct device *dev = hisi_hba->dev;
3543         int entries, entries_old = 0, time;
3544
3545         for (time = 0; time < timeout_ms; time += delay_ms) {
3546                 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
3547                 if (entries == entries_old)
3548                         break;
3549
3550                 entries_old = entries;
3551                 msleep(delay_ms);
3552         }
3553
3554         dev_dbg(dev, "wait commands complete %dms\n", time);
3555 }
3556
3557 static struct scsi_host_template sht_v2_hw = {
3558         .name                   = DRV_NAME,
3559         .module                 = THIS_MODULE,
3560         .queuecommand           = sas_queuecommand,
3561         .target_alloc           = sas_target_alloc,
3562         .slave_configure        = hisi_sas_slave_configure,
3563         .scan_finished          = hisi_sas_scan_finished,
3564         .scan_start             = hisi_sas_scan_start,
3565         .change_queue_depth     = sas_change_queue_depth,
3566         .bios_param             = sas_bios_param,
3567         .this_id                = -1,
3568         .sg_tablesize           = SG_ALL,
3569         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
3570         .use_clustering         = ENABLE_CLUSTERING,
3571         .eh_device_reset_handler = sas_eh_device_reset_handler,
3572         .eh_target_reset_handler = sas_eh_target_reset_handler,
3573         .target_destroy         = sas_target_destroy,
3574         .ioctl                  = sas_ioctl,
3575         .shost_attrs            = host_attrs,
3576 };
3577
3578 static const struct hisi_sas_hw hisi_sas_v2_hw = {
3579         .hw_init = hisi_sas_v2_init,
3580         .setup_itct = setup_itct_v2_hw,
3581         .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
3582         .alloc_dev = alloc_dev_quirk_v2_hw,
3583         .sl_notify = sl_notify_v2_hw,
3584         .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
3585         .clear_itct = clear_itct_v2_hw,
3586         .free_device = free_device_v2_hw,
3587         .prep_smp = prep_smp_v2_hw,
3588         .prep_ssp = prep_ssp_v2_hw,
3589         .prep_stp = prep_ata_v2_hw,
3590         .prep_abort = prep_abort_v2_hw,
3591         .get_free_slot = get_free_slot_v2_hw,
3592         .start_delivery = start_delivery_v2_hw,
3593         .slot_complete = slot_complete_v2_hw,
3594         .phys_init = phys_init_v2_hw,
3595         .phy_start = start_phy_v2_hw,
3596         .phy_disable = disable_phy_v2_hw,
3597         .phy_hard_reset = phy_hard_reset_v2_hw,
3598         .get_events = phy_get_events_v2_hw,
3599         .phy_set_linkrate = phy_set_linkrate_v2_hw,
3600         .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
3601         .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
3602         .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3603         .soft_reset = soft_reset_v2_hw,
3604         .get_phys_state = get_phys_state_v2_hw,
3605         .write_gpio = write_gpio_v2_hw,
3606         .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v2_hw,
3607         .sht = &sht_v2_hw,
3608 };
3609
3610 static int hisi_sas_v2_probe(struct platform_device *pdev)
3611 {
3612         /*
3613          * Check if we should defer the probe before we probe the
3614          * upper layer, as it's hard to defer later on.
3615          */
3616         int ret = platform_get_irq(pdev, 0);
3617
3618         if (ret < 0) {
3619                 if (ret != -EPROBE_DEFER)
3620                         dev_err(&pdev->dev, "cannot obtain irq\n");
3621                 return ret;
3622         }
3623
3624         return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
3625 }
3626
3627 static int hisi_sas_v2_remove(struct platform_device *pdev)
3628 {
3629         struct sas_ha_struct *sha = platform_get_drvdata(pdev);
3630         struct hisi_hba *hisi_hba = sha->lldd_ha;
3631
3632         hisi_sas_kill_tasklets(hisi_hba);
3633
3634         return hisi_sas_remove(pdev);
3635 }
3636
3637 static const struct of_device_id sas_v2_of_match[] = {
3638         { .compatible = "hisilicon,hip06-sas-v2",},
3639         { .compatible = "hisilicon,hip07-sas-v2",},
3640         {},
3641 };
3642 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
3643
3644 static const struct acpi_device_id sas_v2_acpi_match[] = {
3645         { "HISI0162", 0 },
3646         { }
3647 };
3648
3649 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
3650
3651 static struct platform_driver hisi_sas_v2_driver = {
3652         .probe = hisi_sas_v2_probe,
3653         .remove = hisi_sas_v2_remove,
3654         .driver = {
3655                 .name = DRV_NAME,
3656                 .of_match_table = sas_v2_of_match,
3657                 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
3658         },
3659 };
3660
3661 module_platform_driver(hisi_sas_v2_driver);
3662
3663 MODULE_LICENSE("GPL");
3664 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3665 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3666 MODULE_ALIAS("platform:" DRV_NAME);