drivers/scsi/aic7xxx/aic7xxx_pci.c

   1 /*
   2  * Product specific probe and attach routines for:
   3  *      3940, 2940, aic7895, aic7890, aic7880,
   4  *      aic7870, aic7860 and aic7850 SCSI controllers
   5  *
   6  * Copyright (c) 1994-2001 Justin T. Gibbs.
   7  * Copyright (c) 2000-2001 Adaptec Inc.
   8  * All rights reserved.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions, and the following disclaimer,
  15  *    without modification.
  16  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  17  *    substantially similar to the "NO WARRANTY" disclaimer below
  18  *    ("Disclaimer") and any redistribution must be conditioned upon
  19  *    including a substantially similar Disclaimer requirement for further
  20  *    binary redistribution.
  21  * 3. Neither the names of the above-listed copyright holders nor the names
  22  *    of any contributors may be used to endorse or promote products derived
  23  *    from this software without specific prior written permission.
  24  *
  25  * Alternatively, this software may be distributed under the terms of the
  26  * GNU General Public License ("GPL") version 2 as published by the Free
  27  * Software Foundation.
  28  *
  29  * NO WARRANTY
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  31  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  32  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  33  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  34  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  35  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  36  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  37  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  38  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  39  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  40  * POSSIBILITY OF SUCH DAMAGES.
  41  *
  42  * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#79 $
  43  */
  44
  45 #include "aic7xxx_osm.h"
  46 #include "aic7xxx_inline.h"
  47 #include "aic7xxx_93cx6.h"
  48 #include "aic7xxx_pci.h"
  49
  50 static inline uint64_t
  51 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
  52 {
  53         uint64_t id;
  54
  55         id = subvendor
  56            | (subdevice << 16)
  57            | ((uint64_t)vendor << 32)
  58            | ((uint64_t)device << 48);
  59
  60         return (id);
  61 }
  62
  63 #define AHC_PCI_IOADDR  PCIR_MAPS       /* I/O Address */
  64 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */
  65
  66 #define DEVID_9005_TYPE(id) ((id) & 0xF)
  67 #define         DEVID_9005_TYPE_HBA             0x0     /* Standard Card */
  68 #define         DEVID_9005_TYPE_AAA             0x3     /* RAID Card */
  69 #define         DEVID_9005_TYPE_SISL            0x5     /* Container ROMB */
  70 #define         DEVID_9005_TYPE_MB              0xF     /* On Motherboard */
  71
  72 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
  73 #define         DEVID_9005_MAXRATE_U160         0x0
  74 #define         DEVID_9005_MAXRATE_ULTRA2       0x1
  75 #define         DEVID_9005_MAXRATE_ULTRA        0x2
  76 #define         DEVID_9005_MAXRATE_FAST         0x3
  77
  78 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
  79
  80 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
  81 #define         DEVID_9005_CLASS_SPI            0x0     /* Parallel SCSI */
  82
  83 #define SUBID_9005_TYPE(id) ((id) & 0xF)
  84 #define         SUBID_9005_TYPE_MB              0xF     /* On Motherboard */
  85 #define         SUBID_9005_TYPE_CARD            0x0     /* Standard Card */
  86 #define         SUBID_9005_TYPE_LCCARD          0x1     /* Low Cost Card */
  87 #define         SUBID_9005_TYPE_RAID            0x3     /* Combined with Raid */
  88
  89 #define SUBID_9005_TYPE_KNOWN(id)                       \
  90           ((((id) & 0xF) == SUBID_9005_TYPE_MB)         \
  91         || (((id) & 0xF) == SUBID_9005_TYPE_CARD)       \
  92         || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD)     \
  93         || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
  94
  95 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
  96 #define         SUBID_9005_MAXRATE_ULTRA2       0x0
  97 #define         SUBID_9005_MAXRATE_ULTRA        0x1
  98 #define         SUBID_9005_MAXRATE_U160         0x2
  99 #define         SUBID_9005_MAXRATE_RESERVED     0x3
 100
 101 #define SUBID_9005_SEEPTYPE(id)                                         \
 102         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
 103          ? ((id) & 0xC0) >> 6                                           \
 104          : ((id) & 0x300) >> 8)
 105 #define         SUBID_9005_SEEPTYPE_NONE        0x0
 106 #define         SUBID_9005_SEEPTYPE_1K          0x1
 107 #define         SUBID_9005_SEEPTYPE_2K_4K       0x2
 108 #define         SUBID_9005_SEEPTYPE_RESERVED    0x3
 109 #define SUBID_9005_AUTOTERM(id)                                         \
 110         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
 111          ? (((id) & 0x400) >> 10) == 0                                  \
 112          : (((id) & 0x40) >> 6) == 0)
 113
 114 #define SUBID_9005_NUMCHAN(id)                                          \
 115         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
 116          ? ((id) & 0x300) >> 8                                          \
 117          : ((id) & 0xC00) >> 10)
 118
 119 #define SUBID_9005_LEGACYCONN(id)                                       \
 120         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
 121          ? 0                                                            \
 122          : ((id) & 0x80) >> 7)
 123
 124 #define SUBID_9005_MFUNCENB(id)                                         \
 125         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
 126          ? ((id) & 0x800) >> 11                                         \
 127          : ((id) & 0x1000) >> 12)
 128 /*
 129  * Informational only. Should use chip register to be
 130  * certain, but may be use in identification strings.
 131  */
 132 #define SUBID_9005_CARD_SCSIWIDTH_MASK  0x2000
 133 #define SUBID_9005_CARD_PCIWIDTH_MASK   0x4000
 134 #define SUBID_9005_CARD_SEDIFF_MASK     0x8000
 135
 136 static ahc_device_setup_t ahc_aic785X_setup;
 137 static ahc_device_setup_t ahc_aic7860_setup;
 138 static ahc_device_setup_t ahc_apa1480_setup;
 139 static ahc_device_setup_t ahc_aic7870_setup;
 140 static ahc_device_setup_t ahc_aic7870h_setup;
 141 static ahc_device_setup_t ahc_aha394X_setup;
 142 static ahc_device_setup_t ahc_aha394Xh_setup;
 143 static ahc_device_setup_t ahc_aha494X_setup;
 144 static ahc_device_setup_t ahc_aha494Xh_setup;
 145 static ahc_device_setup_t ahc_aha398X_setup;
 146 static ahc_device_setup_t ahc_aic7880_setup;
 147 static ahc_device_setup_t ahc_aic7880h_setup;
 148 static ahc_device_setup_t ahc_aha2940Pro_setup;
 149 static ahc_device_setup_t ahc_aha394XU_setup;
 150 static ahc_device_setup_t ahc_aha394XUh_setup;
 151 static ahc_device_setup_t ahc_aha398XU_setup;
 152 static ahc_device_setup_t ahc_aic7890_setup;
 153 static ahc_device_setup_t ahc_aic7892_setup;
 154 static ahc_device_setup_t ahc_aic7895_setup;
 155 static ahc_device_setup_t ahc_aic7895h_setup;
 156 static ahc_device_setup_t ahc_aic7896_setup;
 157 static ahc_device_setup_t ahc_aic7899_setup;
 158 static ahc_device_setup_t ahc_aha29160C_setup;
 159 static ahc_device_setup_t ahc_raid_setup;
 160 static ahc_device_setup_t ahc_aha394XX_setup;
 161 static ahc_device_setup_t ahc_aha494XX_setup;
 162 static ahc_device_setup_t ahc_aha398XX_setup;
 163
 164 static const struct ahc_pci_identity ahc_pci_ident_table[] = {
 165         /* aic7850 based controllers */
 166         {
 167                 ID_AHA_2902_04_10_15_20C_30C,
 168                 ID_ALL_MASK,
 169                 "Adaptec 2902/04/10/15/20C/30C SCSI adapter",
 170                 ahc_aic785X_setup
 171         },
 172         /* aic7860 based controllers */
 173         {
 174                 ID_AHA_2930CU,
 175                 ID_ALL_MASK,
 176                 "Adaptec 2930CU SCSI adapter",
 177                 ahc_aic7860_setup
 178         },
 179         {
 180                 ID_AHA_1480A & ID_DEV_VENDOR_MASK,
 181                 ID_DEV_VENDOR_MASK,
 182                 "Adaptec 1480A Ultra SCSI adapter",
 183                 ahc_apa1480_setup
 184         },
 185         {
 186                 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
 187                 ID_DEV_VENDOR_MASK,
 188                 "Adaptec 2940A Ultra SCSI adapter",
 189                 ahc_aic7860_setup
 190         },
 191         {
 192                 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
 193                 ID_DEV_VENDOR_MASK,
 194                 "Adaptec 2940A/CN Ultra SCSI adapter",
 195                 ahc_aic7860_setup
 196         },
 197         {
 198                 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
 199                 ID_DEV_VENDOR_MASK,
 200                 "Adaptec 2930C Ultra SCSI adapter (VAR)",
 201                 ahc_aic7860_setup
 202         },
 203         /* aic7870 based controllers */
 204         {
 205                 ID_AHA_2940,
 206                 ID_ALL_MASK,
 207                 "Adaptec 2940 SCSI adapter",
 208                 ahc_aic7870_setup
 209         },
 210         {
 211                 ID_AHA_3940,
 212                 ID_ALL_MASK,
 213                 "Adaptec 3940 SCSI adapter",
 214                 ahc_aha394X_setup
 215         },
 216         {
 217                 ID_AHA_398X,
 218                 ID_ALL_MASK,
 219                 "Adaptec 398X SCSI RAID adapter",
 220                 ahc_aha398X_setup
 221         },
 222         {
 223                 ID_AHA_2944,
 224                 ID_ALL_MASK,
 225                 "Adaptec 2944 SCSI adapter",
 226                 ahc_aic7870h_setup
 227         },
 228         {
 229                 ID_AHA_3944,
 230                 ID_ALL_MASK,
 231                 "Adaptec 3944 SCSI adapter",
 232                 ahc_aha394Xh_setup
 233         },
 234         {
 235                 ID_AHA_4944,
 236                 ID_ALL_MASK,
 237                 "Adaptec 4944 SCSI adapter",
 238                 ahc_aha494Xh_setup
 239         },
 240         /* aic7880 based controllers */
 241         {
 242                 ID_AHA_2940U & ID_DEV_VENDOR_MASK,
 243                 ID_DEV_VENDOR_MASK,
 244                 "Adaptec 2940 Ultra SCSI adapter",
 245                 ahc_aic7880_setup
 246         },
 247         {
 248                 ID_AHA_3940U & ID_DEV_VENDOR_MASK,
 249                 ID_DEV_VENDOR_MASK,
 250                 "Adaptec 3940 Ultra SCSI adapter",
 251                 ahc_aha394XU_setup
 252         },
 253         {
 254                 ID_AHA_2944U & ID_DEV_VENDOR_MASK,
 255                 ID_DEV_VENDOR_MASK,
 256                 "Adaptec 2944 Ultra SCSI adapter",
 257                 ahc_aic7880h_setup
 258         },
 259         {
 260                 ID_AHA_3944U & ID_DEV_VENDOR_MASK,
 261                 ID_DEV_VENDOR_MASK,
 262                 "Adaptec 3944 Ultra SCSI adapter",
 263                 ahc_aha394XUh_setup
 264         },
 265         {
 266                 ID_AHA_398XU & ID_DEV_VENDOR_MASK,
 267                 ID_DEV_VENDOR_MASK,
 268                 "Adaptec 398X Ultra SCSI RAID adapter",
 269                 ahc_aha398XU_setup
 270         },
 271         {
 272                 /*
 273                  * XXX Don't know the slot numbers
 274                  * so we can't identify channels
 275                  */
 276                 ID_AHA_4944U & ID_DEV_VENDOR_MASK,
 277                 ID_DEV_VENDOR_MASK,
 278                 "Adaptec 4944 Ultra SCSI adapter",
 279                 ahc_aic7880h_setup
 280         },
 281         {
 282                 ID_AHA_2930U & ID_DEV_VENDOR_MASK,
 283                 ID_DEV_VENDOR_MASK,
 284                 "Adaptec 2930 Ultra SCSI adapter",
 285                 ahc_aic7880_setup
 286         },
 287         {
 288                 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
 289                 ID_DEV_VENDOR_MASK,
 290                 "Adaptec 2940 Pro Ultra SCSI adapter",
 291                 ahc_aha2940Pro_setup
 292         },
 293         {
 294                 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
 295                 ID_DEV_VENDOR_MASK,
 296                 "Adaptec 2940/CN Ultra SCSI adapter",
 297                 ahc_aic7880_setup
 298         },
 299         /* Ignore all SISL (AAC on MB) based controllers. */
 300         {
 301                 ID_9005_SISL_ID,
 302                 ID_9005_SISL_MASK,
 303                 NULL,
 304                 NULL
 305         },
 306         /* aic7890 based controllers */
 307         {
 308                 ID_AHA_2930U2,
 309                 ID_ALL_MASK,
 310                 "Adaptec 2930 Ultra2 SCSI adapter",
 311                 ahc_aic7890_setup
 312         },
 313         {
 314                 ID_AHA_2940U2B,
 315                 ID_ALL_MASK,
 316                 "Adaptec 2940B Ultra2 SCSI adapter",
 317                 ahc_aic7890_setup
 318         },
 319         {
 320                 ID_AHA_2940U2_OEM,
 321                 ID_ALL_MASK,
 322                 "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
 323                 ahc_aic7890_setup
 324         },
 325         {
 326                 ID_AHA_2940U2,
 327                 ID_ALL_MASK,
 328                 "Adaptec 2940 Ultra2 SCSI adapter",
 329                 ahc_aic7890_setup
 330         },
 331         {
 332                 ID_AHA_2950U2B,
 333                 ID_ALL_MASK,
 334                 "Adaptec 2950 Ultra2 SCSI adapter",
 335                 ahc_aic7890_setup
 336         },
 337         {
 338                 ID_AIC7890_ARO,
 339                 ID_ALL_MASK,
 340                 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
 341                 ahc_aic7890_setup
 342         },
 343         {
 344                 ID_AAA_131U2,
 345                 ID_ALL_MASK,
 346                 "Adaptec AAA-131 Ultra2 RAID adapter",
 347                 ahc_aic7890_setup
 348         },
 349         /* aic7892 based controllers */
 350         {
 351                 ID_AHA_29160,
 352                 ID_ALL_MASK,
 353                 "Adaptec 29160 Ultra160 SCSI adapter",
 354                 ahc_aic7892_setup
 355         },
 356         {
 357                 ID_AHA_29160_CPQ,
 358                 ID_ALL_MASK,
 359                 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
 360                 ahc_aic7892_setup
 361         },
 362         {
 363                 ID_AHA_29160N,
 364                 ID_ALL_MASK,
 365                 "Adaptec 29160N Ultra160 SCSI adapter",
 366                 ahc_aic7892_setup
 367         },
 368         {
 369                 ID_AHA_29160C,
 370                 ID_ALL_MASK,
 371                 "Adaptec 29160C Ultra160 SCSI adapter",
 372                 ahc_aha29160C_setup
 373         },
 374         {
 375                 ID_AHA_29160B,
 376                 ID_ALL_MASK,
 377                 "Adaptec 29160B Ultra160 SCSI adapter",
 378                 ahc_aic7892_setup
 379         },
 380         {
 381                 ID_AHA_19160B,
 382                 ID_ALL_MASK,
 383                 "Adaptec 19160B Ultra160 SCSI adapter",
 384                 ahc_aic7892_setup
 385         },
 386         {
 387                 ID_AIC7892_ARO,
 388                 ID_ALL_MASK,
 389                 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
 390                 ahc_aic7892_setup
 391         },
 392         {
 393                 ID_AHA_2915_30LP,
 394                 ID_ALL_MASK,
 395                 "Adaptec 2915/30LP Ultra160 SCSI adapter",
 396                 ahc_aic7892_setup
 397         },
 398         /* aic7895 based controllers */
 399         {
 400                 ID_AHA_2940U_DUAL,
 401                 ID_ALL_MASK,
 402                 "Adaptec 2940/DUAL Ultra SCSI adapter",
 403                 ahc_aic7895_setup
 404         },
 405         {
 406                 ID_AHA_3940AU,
 407                 ID_ALL_MASK,
 408                 "Adaptec 3940A Ultra SCSI adapter",
 409                 ahc_aic7895_setup
 410         },
 411         {
 412                 ID_AHA_3944AU,
 413                 ID_ALL_MASK,
 414                 "Adaptec 3944A Ultra SCSI adapter",
 415                 ahc_aic7895h_setup
 416         },
 417         {
 418                 ID_AIC7895_ARO,
 419                 ID_AIC7895_ARO_MASK,
 420                 "Adaptec aic7895 Ultra SCSI adapter (ARO)",
 421                 ahc_aic7895_setup
 422         },
 423         /* aic7896/97 based controllers */
 424         {
 425                 ID_AHA_3950U2B_0,
 426                 ID_ALL_MASK,
 427                 "Adaptec 3950B Ultra2 SCSI adapter",
 428                 ahc_aic7896_setup
 429         },
 430         {
 431                 ID_AHA_3950U2B_1,
 432                 ID_ALL_MASK,
 433                 "Adaptec 3950B Ultra2 SCSI adapter",
 434                 ahc_aic7896_setup
 435         },
 436         {
 437                 ID_AHA_3950U2D_0,
 438                 ID_ALL_MASK,
 439                 "Adaptec 3950D Ultra2 SCSI adapter",
 440                 ahc_aic7896_setup
 441         },
 442         {
 443                 ID_AHA_3950U2D_1,
 444                 ID_ALL_MASK,
 445                 "Adaptec 3950D Ultra2 SCSI adapter",
 446                 ahc_aic7896_setup
 447         },
 448         {
 449                 ID_AIC7896_ARO,
 450                 ID_ALL_MASK,
 451                 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
 452                 ahc_aic7896_setup
 453         },
 454         /* aic7899 based controllers */
 455         {
 456                 ID_AHA_3960D,
 457                 ID_ALL_MASK,
 458                 "Adaptec 3960D Ultra160 SCSI adapter",
 459                 ahc_aic7899_setup
 460         },
 461         {
 462                 ID_AHA_3960D_CPQ,
 463                 ID_ALL_MASK,
 464                 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
 465                 ahc_aic7899_setup
 466         },
 467         {
 468                 ID_AIC7899_ARO,
 469                 ID_ALL_MASK,
 470                 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
 471                 ahc_aic7899_setup
 472         },
 473         /* Generic chip probes for devices we don't know 'exactly' */
 474         {
 475                 ID_AIC7850 & ID_DEV_VENDOR_MASK,
 476                 ID_DEV_VENDOR_MASK,
 477                 "Adaptec aic7850 SCSI adapter",
 478                 ahc_aic785X_setup
 479         },
 480         {
 481                 ID_AIC7855 & ID_DEV_VENDOR_MASK,
 482                 ID_DEV_VENDOR_MASK,
 483                 "Adaptec aic7855 SCSI adapter",
 484                 ahc_aic785X_setup
 485         },
 486         {
 487                 ID_AIC7859 & ID_DEV_VENDOR_MASK,
 488                 ID_DEV_VENDOR_MASK,
 489                 "Adaptec aic7859 SCSI adapter",
 490                 ahc_aic7860_setup
 491         },
 492         {
 493                 ID_AIC7860 & ID_DEV_VENDOR_MASK,
 494                 ID_DEV_VENDOR_MASK,
 495                 "Adaptec aic7860 Ultra SCSI adapter",
 496                 ahc_aic7860_setup
 497         },
 498         {
 499                 ID_AIC7870 & ID_DEV_VENDOR_MASK,
 500                 ID_DEV_VENDOR_MASK,
 501                 "Adaptec aic7870 SCSI adapter",
 502                 ahc_aic7870_setup
 503         },
 504         {
 505                 ID_AIC7880 & ID_DEV_VENDOR_MASK,
 506                 ID_DEV_VENDOR_MASK,
 507                 "Adaptec aic7880 Ultra SCSI adapter",
 508                 ahc_aic7880_setup
 509         },
 510         {
 511                 ID_AIC7890 & ID_9005_GENERIC_MASK,
 512                 ID_9005_GENERIC_MASK,
 513                 "Adaptec aic7890/91 Ultra2 SCSI adapter",
 514                 ahc_aic7890_setup
 515         },
 516         {
 517                 ID_AIC7892 & ID_9005_GENERIC_MASK,
 518                 ID_9005_GENERIC_MASK,
 519                 "Adaptec aic7892 Ultra160 SCSI adapter",
 520                 ahc_aic7892_setup
 521         },
 522         {
 523                 ID_AIC7895 & ID_DEV_VENDOR_MASK,
 524                 ID_DEV_VENDOR_MASK,
 525                 "Adaptec aic7895 Ultra SCSI adapter",
 526                 ahc_aic7895_setup
 527         },
 528         {
 529                 ID_AIC7896 & ID_9005_GENERIC_MASK,
 530                 ID_9005_GENERIC_MASK,
 531                 "Adaptec aic7896/97 Ultra2 SCSI adapter",
 532                 ahc_aic7896_setup
 533         },
 534         {
 535                 ID_AIC7899 & ID_9005_GENERIC_MASK,
 536                 ID_9005_GENERIC_MASK,
 537                 "Adaptec aic7899 Ultra160 SCSI adapter",
 538                 ahc_aic7899_setup
 539         },
 540         {
 541                 ID_AIC7810 & ID_DEV_VENDOR_MASK,
 542                 ID_DEV_VENDOR_MASK,
 543                 "Adaptec aic7810 RAID memory controller",
 544                 ahc_raid_setup
 545         },
 546         {
 547                 ID_AIC7815 & ID_DEV_VENDOR_MASK,
 548                 ID_DEV_VENDOR_MASK,
 549                 "Adaptec aic7815 RAID memory controller",
 550                 ahc_raid_setup
 551         }
 552 };
 553
 554 static const u_int ahc_num_pci_devs = ARRAY_SIZE(ahc_pci_ident_table);
 555
 556 #define AHC_394X_SLOT_CHANNEL_A 4
 557 #define AHC_394X_SLOT_CHANNEL_B 5
 558
 559 #define AHC_398X_SLOT_CHANNEL_A 4
 560 #define AHC_398X_SLOT_CHANNEL_B 8
 561 #define AHC_398X_SLOT_CHANNEL_C 12
 562
 563 #define AHC_494X_SLOT_CHANNEL_A 4
 564 #define AHC_494X_SLOT_CHANNEL_B 5
 565 #define AHC_494X_SLOT_CHANNEL_C 6
 566 #define AHC_494X_SLOT_CHANNEL_D 7
 567
 568 #define DEVCONFIG               0x40
 569 #define         PCIERRGENDIS    0x80000000ul
 570 #define         SCBSIZE32       0x00010000ul    /* aic789X only */
 571 #define         REXTVALID       0x00001000ul    /* ultra cards only */
 572 #define         MPORTMODE       0x00000400ul    /* aic7870+ only */
 573 #define         RAMPSM          0x00000200ul    /* aic7870+ only */
 574 #define         VOLSENSE        0x00000100ul
 575 #define         PCI64BIT        0x00000080ul    /* 64Bit PCI bus (Ultra2 Only)*/
 576 #define         SCBRAMSEL       0x00000080ul
 577 #define         MRDCEN          0x00000040ul
 578 #define         EXTSCBTIME      0x00000020ul    /* aic7870 only */
 579 #define         EXTSCBPEN       0x00000010ul    /* aic7870 only */
 580 #define         BERREN          0x00000008ul
 581 #define         DACEN           0x00000004ul
 582 #define         STPWLEVEL       0x00000002ul
 583 #define         DIFACTNEGEN     0x00000001ul    /* aic7870 only */
 584
 585 #define CSIZE_LATTIME           0x0c
 586 #define         CACHESIZE       0x0000003ful    /* only 5 bits */
 587 #define         LATTIME         0x0000ff00ul
 588
 589 /* PCI STATUS definitions */
 590 #define DPE     0x80
 591 #define SSE     0x40
 592 #define RMA     0x20
 593 #define RTA     0x10
 594 #define STA     0x08
 595 #define DPR     0x01
 596
 597 static int ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
 598                                      uint16_t subdevice, uint16_t subvendor);
 599 static int ahc_ext_scbram_present(struct ahc_softc *ahc);
 600 static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
 601                                   int pcheck, int fast, int large);
 602 static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
 603 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
 604 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc,
 605                                  struct seeprom_config *sc);
 606 static void configure_termination(struct ahc_softc *ahc,
 607                                   struct seeprom_descriptor *sd,
 608                                   u_int adapter_control,
 609                                   u_int *sxfrctl1);
 610
 611 static void ahc_new_term_detect(struct ahc_softc *ahc,
 612                                 int *enableSEC_low,
 613                                 int *enableSEC_high,
 614                                 int *enablePRI_low,
 615                                 int *enablePRI_high,
 616                                 int *eeprom_present);
 617 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
 618                                  int *internal68_present,
 619                                  int *externalcable_present,
 620                                  int *eeprom_present);
 621 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
 622                                  int *externalcable_present,
 623                                  int *eeprom_present);
 624 static void    write_brdctl(struct ahc_softc *ahc, uint8_t value);
 625 static uint8_t read_brdctl(struct ahc_softc *ahc);
 626 static void ahc_pci_intr(struct ahc_softc *ahc);
 627 static int  ahc_pci_chip_init(struct ahc_softc *ahc);
 628
 629 static int
 630 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
 631                           uint16_t subdevice, uint16_t subvendor)
 632 {
 633         int result;
 634
 635         /* Default to invalid. */
 636         result = 0;
 637         if (vendor == 0x9005
 638          && subvendor == 0x9005
 639          && subdevice != device
 640          && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
 641
 642                 switch (SUBID_9005_TYPE(subdevice)) {
 643                 case SUBID_9005_TYPE_MB:
 644                         break;
 645                 case SUBID_9005_TYPE_CARD:
 646                 case SUBID_9005_TYPE_LCCARD:
 647                         /*
 648                          * Currently only trust Adaptec cards to
 649                          * get the sub device info correct.
 650                          */
 651                         if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
 652                                 result = 1;
 653                         break;
 654                 case SUBID_9005_TYPE_RAID:
 655                         break;
 656                 default:
 657                         break;
 658                 }
 659         }
 660         return (result);
 661 }
 662
 663 const struct ahc_pci_identity *
 664 ahc_find_pci_device(ahc_dev_softc_t pci)
 665 {
 666         uint64_t  full_id;
 667         uint16_t  device;
 668         uint16_t  vendor;
 669         uint16_t  subdevice;
 670         uint16_t  subvendor;
 671         const struct ahc_pci_identity *entry;
 672         u_int     i;
 673
 674         vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
 675         device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
 676         subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
 677         subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
 678         full_id = ahc_compose_id(device, vendor, subdevice, subvendor);
 679
 680         /*
 681          * If the second function is not hooked up, ignore it.
 682          * Unfortunately, not all MB vendors implement the
 683          * subdevice ID as per the Adaptec spec, so do our best
 684          * to sanity check it prior to accepting the subdevice
 685          * ID as valid.
 686          */
 687         if (ahc_get_pci_function(pci) > 0
 688          && ahc_9005_subdevinfo_valid(device, vendor, subdevice, subvendor)
 689          && SUBID_9005_MFUNCENB(subdevice) == 0)
 690                 return (NULL);
 691
 692         for (i = 0; i < ahc_num_pci_devs; i++) {
 693                 entry = &ahc_pci_ident_table[i];
 694                 if (entry->full_id == (full_id & entry->id_mask)) {
 695                         /* Honor exclusion entries. */
 696                         if (entry->name == NULL)
 697                                 return (NULL);
 698                         return (entry);
 699                 }
 700         }
 701         return (NULL);
 702 }
 703
 704 int
 705 ahc_pci_config(struct ahc_softc *ahc, const struct ahc_pci_identity *entry)
 706 {
 707         u_int    command;
 708         u_int    our_id;
 709         u_int    sxfrctl1;
 710         u_int    scsiseq;
 711         u_int    dscommand0;
 712         uint32_t devconfig;
 713         int      error;
 714         uint8_t  sblkctl;
 715
 716         our_id = 0;
 717         error = entry->setup(ahc);
 718         if (error != 0)
 719                 return (error);
 720         ahc->chip |= AHC_PCI;
 721         ahc->description = entry->name;
 722
 723         pci_set_power_state(ahc->dev_softc, AHC_POWER_STATE_D0);
 724
 725         error = ahc_pci_map_registers(ahc);
 726         if (error != 0)
 727                 return (error);
 728
 729         /*
 730          * Before we continue probing the card, ensure that
 731          * its interrupts are *disabled*.  We don't want
 732          * a misstep to hang the machine in an interrupt
 733          * storm.
 734          */
 735         ahc_intr_enable(ahc, FALSE);
 736
 737         devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
 738
 739         /*
 740          * If we need to support high memory, enable dual
 741          * address cycles.  This bit must be set to enable
 742          * high address bit generation even if we are on a
 743          * 64bit bus (PCI64BIT set in devconfig).
 744          */
 745         if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
 746
 747                 if (bootverbose)
 748                         printk("%s: Enabling 39Bit Addressing\n",
 749                                ahc_name(ahc));
 750                 devconfig |= DACEN;
 751         }
 752
 753         /* Ensure that pci error generation, a test feature, is disabled. */
 754         devconfig |= PCIERRGENDIS;
 755
 756         ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
 757
 758         /* Ensure busmastering is enabled */
 759         command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
 760         command |= PCIM_CMD_BUSMASTEREN;
 761
 762         ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
 763
 764         /* On all PCI adapters, we allow SCB paging */
 765         ahc->flags |= AHC_PAGESCBS;
 766
 767         error = ahc_softc_init(ahc);
 768         if (error != 0)
 769                 return (error);
 770
 771         /*
 772          * Disable PCI parity error checking.  Users typically
 773          * do this to work around broken PCI chipsets that get
 774          * the parity timing wrong and thus generate lots of spurious
 775          * errors.  The chip only allows us to disable *all* parity
 776          * error reporting when doing this, so CIO bus, scb ram, and
 777          * scratch ram parity errors will be ignored too.
 778          */
 779         if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0)
 780                 ahc->seqctl |= FAILDIS;
 781
 782         ahc->bus_intr = ahc_pci_intr;
 783         ahc->bus_chip_init = ahc_pci_chip_init;
 784
 785         /* Remember how the card was setup in case there is no SEEPROM */
 786         if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
 787                 ahc_pause(ahc);
 788                 if ((ahc->features & AHC_ULTRA2) != 0)
 789                         our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
 790                 else
 791                         our_id = ahc_inb(ahc, SCSIID) & OID;
 792                 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
 793                 scsiseq = ahc_inb(ahc, SCSISEQ);
 794         } else {
 795                 sxfrctl1 = STPWEN;
 796                 our_id = 7;
 797                 scsiseq = 0;
 798         }
 799
 800         error = ahc_reset(ahc, /*reinit*/FALSE);
 801         if (error != 0)
 802                 return (ENXIO);
 803
 804         if ((ahc->features & AHC_DT) != 0) {
 805                 u_int sfunct;
 806
 807                 /* Perform ALT-Mode Setup */
 808                 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
 809                 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
 810                 ahc_outb(ahc, OPTIONMODE,
 811                          OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
 812                 ahc_outb(ahc, SFUNCT, sfunct);
 813
 814                 /* Normal mode setup */
 815                 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
 816                                           |TARGCRCENDEN);
 817         }
 818
 819         dscommand0 = ahc_inb(ahc, DSCOMMAND0);
 820         dscommand0 |= MPARCKEN|CACHETHEN;
 821         if ((ahc->features & AHC_ULTRA2) != 0) {
 822
 823                 /*
 824                  * DPARCKEN doesn't work correctly on
 825                  * some MBs so don't use it.
 826                  */
 827                 dscommand0 &= ~DPARCKEN;
 828         }
 829
 830         /*
 831          * Handle chips that must have cache line
 832          * streaming (dis/en)abled.
 833          */
 834         if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
 835                 dscommand0 |= CACHETHEN;
 836
 837         if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
 838                 dscommand0 &= ~CACHETHEN;
 839
 840         ahc_outb(ahc, DSCOMMAND0, dscommand0);
 841
 842         ahc->pci_cachesize =
 843             ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME,
 844                                 /*bytes*/1) & CACHESIZE;
 845         ahc->pci_cachesize *= 4;
 846
 847         if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
 848          && ahc->pci_cachesize == 4) {
 849
 850                 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
 851                                      0, /*bytes*/1);
 852                 ahc->pci_cachesize = 0;
 853         }
 854
 855         /*
 856          * We cannot perform ULTRA speeds without the presence
 857          * of the external precision resistor.
 858          */
 859         if ((ahc->features & AHC_ULTRA) != 0) {
 860                 uint32_t devconfig;
 861
 862                 devconfig = ahc_pci_read_config(ahc->dev_softc,
 863                                                 DEVCONFIG, /*bytes*/4);
 864                 if ((devconfig & REXTVALID) == 0)
 865                         ahc->features &= ~AHC_ULTRA;
 866         }
 867
 868         /* See if we have a SEEPROM and perform auto-term */
 869         check_extport(ahc, &sxfrctl1);
 870
 871         /*
 872          * Take the LED out of diagnostic mode
 873          */
 874         sblkctl = ahc_inb(ahc, SBLKCTL);
 875         ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
 876
 877         if ((ahc->features & AHC_ULTRA2) != 0) {
 878                 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
 879         } else {
 880                 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
 881         }
 882
 883         if (ahc->flags & AHC_USEDEFAULTS) {
 884                 /*
 885                  * PCI Adapter default setup
 886                  * Should only be used if the adapter does not have
 887                  * a SEEPROM.
 888                  */
 889                 /* See if someone else set us up already */
 890                 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
 891                  && scsiseq != 0) {
 892                         printk("%s: Using left over BIOS settings\n",
 893                                 ahc_name(ahc));
 894                         ahc->flags &= ~AHC_USEDEFAULTS;
 895                         ahc->flags |= AHC_BIOS_ENABLED;
 896                 } else {
 897                         /*
 898                          * Assume only one connector and always turn
 899                          * on termination.
 900                          */
 901                         our_id = 0x07;
 902                         sxfrctl1 = STPWEN;
 903                 }
 904                 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
 905
 906                 ahc->our_id = our_id;
 907         }
 908
 909         /*
 910          * Take a look to see if we have external SRAM.
 911          * We currently do not attempt to use SRAM that is
 912          * shared among multiple controllers.
 913          */
 914         ahc_probe_ext_scbram(ahc);
 915
 916         /*
 917          * Record our termination setting for the
 918          * generic initialization routine.
 919          */
 920         if ((sxfrctl1 & STPWEN) != 0)
 921                 ahc->flags |= AHC_TERM_ENB_A;
 922
 923         /*
 924          * Save chip register configuration data for chip resets
 925          * that occur during runtime and resume events.
 926          */
 927         ahc->bus_softc.pci_softc.devconfig =
 928             ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
 929         ahc->bus_softc.pci_softc.command =
 930             ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
 931         ahc->bus_softc.pci_softc.csize_lattime =
 932             ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1);
 933         ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
 934         ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
 935         if ((ahc->features & AHC_DT) != 0) {
 936                 u_int sfunct;
 937
 938                 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
 939                 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
 940                 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
 941                 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
 942                 ahc_outb(ahc, SFUNCT, sfunct);
 943                 ahc->bus_softc.pci_softc.crccontrol1 =
 944                     ahc_inb(ahc, CRCCONTROL1);
 945         }
 946         if ((ahc->features & AHC_MULTI_FUNC) != 0)
 947                 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
 948
 949         if ((ahc->features & AHC_ULTRA2) != 0)
 950                 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
 951
 952         /* Core initialization */
 953         error = ahc_init(ahc);
 954         if (error != 0)
 955                 return (error);
 956         ahc->init_level++;
 957
 958         /*
 959          * Allow interrupts now that we are completely setup.
 960          */
 961         return ahc_pci_map_int(ahc);
 962 }
 963
 964 /*
 965  * Test for the presence of external sram in an
 966  * "unshared" configuration.
 967  */
 968 static int
 969 ahc_ext_scbram_present(struct ahc_softc *ahc)
 970 {
 971         u_int chip;
 972         int ramps;
 973         int single_user;
 974         uint32_t devconfig;
 975
 976         chip = ahc->chip & AHC_CHIPID_MASK;
 977         devconfig = ahc_pci_read_config(ahc->dev_softc,
 978                                         DEVCONFIG, /*bytes*/4);
 979         single_user = (devconfig & MPORTMODE) != 0;
 980
 981         if ((ahc->features & AHC_ULTRA2) != 0)
 982                 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
 983         else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
 984                 /*
 985                  * External SCBRAM arbitration is flakey
 986                  * on these chips.  Unfortunately this means
 987                  * we don't use the extra SCB ram space on the
 988                  * 3940AUW.
 989                  */
 990                 ramps = 0;
 991         else if (chip >= AHC_AIC7870)
 992                 ramps = (devconfig & RAMPSM) != 0;
 993         else
 994                 ramps = 0;
 995
 996         if (ramps && single_user)
 997                 return (1);
 998         return (0);
 999 }
1000
1001 /*
1002  * Enable external scbram.
1003  */
1004 static void
1005 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
1006                   int fast, int large)
1007 {
1008         uint32_t devconfig;
1009
1010         if (ahc->features & AHC_MULTI_FUNC) {
1011                 /*
1012                  * Set the SCB Base addr (highest address bit)
1013                  * depending on which channel we are.
1014                  */
1015                 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc));
1016         }
1017
1018         ahc->flags &= ~AHC_LSCBS_ENABLED;
1019         if (large)
1020                 ahc->flags |= AHC_LSCBS_ENABLED;
1021         devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1022         if ((ahc->features & AHC_ULTRA2) != 0) {
1023                 u_int dscommand0;
1024
1025                 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1026                 if (enable)
1027                         dscommand0 &= ~INTSCBRAMSEL;
1028                 else
1029                         dscommand0 |= INTSCBRAMSEL;
1030                 if (large)
1031                         dscommand0 &= ~USCBSIZE32;
1032                 else
1033                         dscommand0 |= USCBSIZE32;
1034                 ahc_outb(ahc, DSCOMMAND0, dscommand0);
1035         } else {
1036                 if (fast)
1037                         devconfig &= ~EXTSCBTIME;
1038                 else
1039                         devconfig |= EXTSCBTIME;
1040                 if (enable)
1041                         devconfig &= ~SCBRAMSEL;
1042                 else
1043                         devconfig |= SCBRAMSEL;
1044                 if (large)
1045                         devconfig &= ~SCBSIZE32;
1046                 else
1047                         devconfig |= SCBSIZE32;
1048         }
1049         if (pcheck)
1050                 devconfig |= EXTSCBPEN;
1051         else
1052                 devconfig &= ~EXTSCBPEN;
1053
1054         ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
1055 }
1056
1057 /*
1058  * Take a look to see if we have external SRAM.
1059  * We currently do not attempt to use SRAM that is
1060  * shared among multiple controllers.
1061  */
1062 static void
1063 ahc_probe_ext_scbram(struct ahc_softc *ahc)
1064 {
1065         int num_scbs;
1066         int test_num_scbs;
1067         int enable;
1068         int pcheck;
1069         int fast;
1070         int large;
1071
1072         enable = FALSE;
1073         pcheck = FALSE;
1074         fast = FALSE;
1075         large = FALSE;
1076         num_scbs = 0;
1077
1078         if (ahc_ext_scbram_present(ahc) == 0)
1079                 goto done;
1080
1081         /*
1082          * Probe for the best parameters to use.
1083          */
1084         ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
1085         num_scbs = ahc_probe_scbs(ahc);
1086         if (num_scbs == 0) {
1087                 /* The SRAM wasn't really present. */
1088                 goto done;
1089         }
1090         enable = TRUE;
1091
1092         /*
1093          * Clear any outstanding parity error
1094          * and ensure that parity error reporting
1095          * is enabled.
1096          */
1097         ahc_outb(ahc, SEQCTL, 0);
1098         ahc_outb(ahc, CLRINT, CLRPARERR);
1099         ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1100
1101         /* Now see if we can do parity */
1102         ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
1103         num_scbs = ahc_probe_scbs(ahc);
1104         if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1105          || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
1106                 pcheck = TRUE;
1107
1108         /* Clear any resulting parity error */
1109         ahc_outb(ahc, CLRINT, CLRPARERR);
1110         ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1111
1112         /* Now see if we can do fast timing */
1113         ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
1114         test_num_scbs = ahc_probe_scbs(ahc);
1115         if (test_num_scbs == num_scbs
1116          && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1117           || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
1118                 fast = TRUE;
1119
1120         /*
1121          * See if we can use large SCBs and still maintain
1122          * the same overall count of SCBs.
1123          */
1124         if ((ahc->features & AHC_LARGE_SCBS) != 0) {
1125                 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
1126                 test_num_scbs = ahc_probe_scbs(ahc);
1127                 if (test_num_scbs >= num_scbs) {
1128                         large = TRUE;
1129                         num_scbs = test_num_scbs;
1130                         if (num_scbs >= 64) {
1131                                 /*
1132                                  * We have enough space to move the
1133                                  * "busy targets table" into SCB space
1134                                  * and make it qualify all the way to the
1135                                  * lun level.
1136                                  */
1137                                 ahc->flags |= AHC_SCB_BTT;
1138                         }
1139                 }
1140         }
1141 done:
1142         /*
1143          * Disable parity error reporting until we
1144          * can load instruction ram.
1145          */
1146         ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1147         /* Clear any latched parity error */
1148         ahc_outb(ahc, CLRINT, CLRPARERR);
1149         ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1150         if (bootverbose && enable) {
1151                 printk("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1152                        ahc_name(ahc), fast ? "fast" : "slow",
1153                        pcheck ? ", parity checking enabled" : "",
1154                        large ? 64 : 32);
1155         }
1156         ahc_scbram_config(ahc, enable, pcheck, fast, large);
1157 }
1158
1159 /*
1160  * Perform some simple tests that should catch situations where
1161  * our registers are invalidly mapped.
1162  */
1163 int
1164 ahc_pci_test_register_access(struct ahc_softc *ahc)
1165 {
1166         int      error;
1167         u_int    status1;
1168         uint32_t cmd;
1169         uint8_t  hcntrl;
1170
1171         error = EIO;
1172
1173         /*
1174          * Enable PCI error interrupt status, but suppress NMIs
1175          * generated by SERR raised due to target aborts.
1176          */
1177         cmd = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
1178         ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
1179                              cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
1180
1181         /*
1182          * First a simple test to see if any
1183          * registers can be read.  Reading
1184          * HCNTRL has no side effects and has
1185          * at least one bit that is guaranteed to
1186          * be zero so it is a good register to
1187          * use for this test.
1188          */
1189         hcntrl = ahc_inb(ahc, HCNTRL);
1190
1191         if (hcntrl == 0xFF)
1192                 goto fail;
1193
1194         if ((hcntrl & CHIPRST) != 0) {
1195                 /*
1196                  * The chip has not been initialized since
1197                  * PCI/EISA/VLB bus reset.  Don't trust
1198                  * "left over BIOS data".
1199                  */
1200                 ahc->flags |= AHC_NO_BIOS_INIT;
1201         }
1202
1203         /*
1204          * Next create a situation where write combining
1205          * or read prefetching could be initiated by the
1206          * CPU or host bridge.  Our device does not support
1207          * either, so look for data corruption and/or flagged
1208          * PCI errors.  First pause without causing another
1209          * chip reset.
1210          */
1211         hcntrl &= ~CHIPRST;
1212         ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
1213         while (ahc_is_paused(ahc) == 0)
1214                 ;
1215
1216         /* Clear any PCI errors that occurred before our driver attached. */
1217         status1 = ahc_pci_read_config(ahc->dev_softc,
1218                                       PCIR_STATUS + 1, /*bytes*/1);
1219         ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1220                              status1, /*bytes*/1);
1221         ahc_outb(ahc, CLRINT, CLRPARERR);
1222
1223         ahc_outb(ahc, SEQCTL, PERRORDIS);
1224         ahc_outb(ahc, SCBPTR, 0);
1225         ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
1226         if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
1227                 goto fail;
1228
1229         status1 = ahc_pci_read_config(ahc->dev_softc,
1230                                       PCIR_STATUS + 1, /*bytes*/1);
1231         if ((status1 & STA) != 0)
1232                 goto fail;
1233
1234         error = 0;
1235
1236 fail:
1237         /* Silently clear any latched errors. */
1238         status1 = ahc_pci_read_config(ahc->dev_softc,
1239                                       PCIR_STATUS + 1, /*bytes*/1);
1240         ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1241                              status1, /*bytes*/1);
1242         ahc_outb(ahc, CLRINT, CLRPARERR);
1243         ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1244         ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
1245         return (error);
1246 }
1247
1248 /*
1249  * Check the external port logic for a serial eeprom
1250  * and termination/cable detection contrls.
1251  */
1252 static void
1253 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
1254 {
1255         struct  seeprom_descriptor sd;
1256         struct  seeprom_config *sc;
1257         int     have_seeprom;
1258         int     have_autoterm;
1259
1260         sd.sd_ahc = ahc;
1261         sd.sd_control_offset = SEECTL;
1262         sd.sd_status_offset = SEECTL;
1263         sd.sd_dataout_offset = SEECTL;
1264         sc = ahc->seep_config;
1265
1266         /*
1267          * For some multi-channel devices, the c46 is simply too
1268          * small to work.  For the other controller types, we can
1269          * get our information from either SEEPROM type.  Set the
1270          * type to start our probe with accordingly.
1271          */
1272         if (ahc->flags & AHC_LARGE_SEEPROM)
1273                 sd.sd_chip = C56_66;
1274         else
1275                 sd.sd_chip = C46;
1276
1277         sd.sd_MS = SEEMS;
1278         sd.sd_RDY = SEERDY;
1279         sd.sd_CS = SEECS;
1280         sd.sd_CK = SEECK;
1281         sd.sd_DO = SEEDO;
1282         sd.sd_DI = SEEDI;
1283
1284         have_seeprom = ahc_acquire_seeprom(ahc, &sd);
1285         if (have_seeprom) {
1286
1287                 if (bootverbose)
1288                         printk("%s: Reading SEEPROM...", ahc_name(ahc));
1289
1290                 for (;;) {
1291                         u_int start_addr;
1292
1293                         start_addr = 32 * (ahc->channel - 'A');
1294
1295                         have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
1296                                                         start_addr,
1297                                                         sizeof(*sc)/2);
1298
1299                         if (have_seeprom)
1300                                 have_seeprom = ahc_verify_cksum(sc);
1301
1302                         if (have_seeprom != 0 || sd.sd_chip == C56_66) {
1303                                 if (bootverbose) {
1304                                         if (have_seeprom == 0)
1305                                                 printk ("checksum error\n");
1306                                         else
1307                                                 printk ("done.\n");
1308                                 }
1309                                 break;
1310                         }
1311                         sd.sd_chip = C56_66;
1312                 }
1313                 ahc_release_seeprom(&sd);
1314
1315                 /* Remember the SEEPROM type for later */
1316                 if (sd.sd_chip == C56_66)
1317                         ahc->flags |= AHC_LARGE_SEEPROM;
1318         }
1319
1320         if (!have_seeprom) {
1321                 /*
1322                  * Pull scratch ram settings and treat them as
1323                  * if they are the contents of an seeprom if
1324                  * the 'ADPT' signature is found in SCB2.
1325                  * We manually compose the data as 16bit values
1326                  * to avoid endian issues.
1327                  */
1328                 ahc_outb(ahc, SCBPTR, 2);
1329                 if (ahc_inb(ahc, SCB_BASE) == 'A'
1330                  && ahc_inb(ahc, SCB_BASE + 1) == 'D'
1331                  && ahc_inb(ahc, SCB_BASE + 2) == 'P'
1332                  && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
1333                         uint16_t *sc_data;
1334                         int       i;
1335
1336                         sc_data = (uint16_t *)sc;
1337                         for (i = 0; i < 32; i++, sc_data++) {
1338                                 int     j;
1339
1340                                 j = i * 2;
1341                                 *sc_data = ahc_inb(ahc, SRAM_BASE + j)
1342                                          | ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
1343                         }
1344                         have_seeprom = ahc_verify_cksum(sc);
1345                         if (have_seeprom)
1346                                 ahc->flags |= AHC_SCB_CONFIG_USED;
1347                 }
1348                 /*
1349                  * Clear any SCB parity errors in case this data and
1350                  * its associated parity was not initialized by the BIOS
1351                  */
1352                 ahc_outb(ahc, CLRINT, CLRPARERR);
1353                 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1354         }
1355
1356         if (!have_seeprom) {
1357                 if (bootverbose)
1358                         printk("%s: No SEEPROM available.\n", ahc_name(ahc));
1359                 ahc->flags |= AHC_USEDEFAULTS;
1360                 kfree(ahc->seep_config);
1361                 ahc->seep_config = NULL;
1362                 sc = NULL;
1363         } else {
1364                 ahc_parse_pci_eeprom(ahc, sc);
1365         }
1366
1367         /*
1368          * Cards that have the external logic necessary to talk to
1369          * a SEEPROM, are almost certain to have the remaining logic
1370          * necessary for auto-termination control.  This assumption
1371          * hasn't failed yet...
1372          */
1373         have_autoterm = have_seeprom;
1374
1375         /*
1376          * Some low-cost chips have SEEPROM and auto-term control built
1377          * in, instead of using a GAL.  They can tell us directly
1378          * if the termination logic is enabled.
1379          */
1380         if ((ahc->features & AHC_SPIOCAP) != 0) {
1381                 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0)
1382                         have_autoterm = FALSE;
1383         }
1384
1385         if (have_autoterm) {
1386                 ahc->flags |= AHC_HAS_TERM_LOGIC;
1387                 ahc_acquire_seeprom(ahc, &sd);
1388                 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1);
1389                 ahc_release_seeprom(&sd);
1390         } else if (have_seeprom) {
1391                 *sxfrctl1 &= ~STPWEN;
1392                 if ((sc->adapter_control & CFSTERM) != 0)
1393                         *sxfrctl1 |= STPWEN;
1394                 if (bootverbose)
1395                         printk("%s: Low byte termination %sabled\n",
1396                                ahc_name(ahc),
1397                                (*sxfrctl1 & STPWEN) ? "en" : "dis");
1398         }
1399 }
1400
1401 static void
1402 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc)
1403 {
1404         /*
1405          * Put the data we've collected down into SRAM
1406          * where ahc_init will find it.
1407          */
1408         int      i;
1409         int      max_targ = sc->max_targets & CFMAXTARG;
1410         u_int    scsi_conf;
1411         uint16_t discenable;
1412         uint16_t ultraenb;
1413
1414         discenable = 0;
1415         ultraenb = 0;
1416         if ((sc->adapter_control & CFULTRAEN) != 0) {
1417                 /*
1418                  * Determine if this adapter has a "newstyle"
1419                  * SEEPROM format.
1420                  */
1421                 for (i = 0; i < max_targ; i++) {
1422                         if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) {
1423                                 ahc->flags |= AHC_NEWEEPROM_FMT;
1424                                 break;
1425                         }
1426                 }
1427         }
1428
1429         for (i = 0; i < max_targ; i++) {
1430                 u_int     scsirate;
1431                 uint16_t target_mask;
1432
1433                 target_mask = 0x01 << i;
1434                 if (sc->device_flags[i] & CFDISC)
1435                         discenable |= target_mask;
1436                 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
1437                         if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0)
1438                                 ultraenb |= target_mask;
1439                 } else if ((sc->adapter_control & CFULTRAEN) != 0) {
1440                         ultraenb |= target_mask;
1441                 }
1442                 if ((sc->device_flags[i] & CFXFER) == 0x04
1443                  && (ultraenb & target_mask) != 0) {
1444                         /* Treat 10MHz as a non-ultra speed */
1445                         sc->device_flags[i] &= ~CFXFER;
1446                         ultraenb &= ~target_mask;
1447                 }
1448                 if ((ahc->features & AHC_ULTRA2) != 0) {
1449                         u_int offset;
1450
1451                         if (sc->device_flags[i] & CFSYNCH)
1452                                 offset = MAX_OFFSET_ULTRA2;
1453                         else
1454                                 offset = 0;
1455                         ahc_outb(ahc, TARG_OFFSET + i, offset);
1456
1457                         /*
1458                          * The ultra enable bits contain the
1459                          * high bit of the ultra2 sync rate
1460                          * field.
1461                          */
1462                         scsirate = (sc->device_flags[i] & CFXFER)
1463                                  | ((ultraenb & target_mask) ? 0x8 : 0x0);
1464                         if (sc->device_flags[i] & CFWIDEB)
1465                                 scsirate |= WIDEXFER;
1466                 } else {
1467                         scsirate = (sc->device_flags[i] & CFXFER) << 4;
1468                         if (sc->device_flags[i] & CFSYNCH)
1469                                 scsirate |= SOFS;
1470                         if (sc->device_flags[i] & CFWIDEB)
1471                                 scsirate |= WIDEXFER;
1472                 }
1473                 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
1474         }
1475         ahc->our_id = sc->brtime_id & CFSCSIID;
1476
1477         scsi_conf = (ahc->our_id & 0x7);
1478         if (sc->adapter_control & CFSPARITY)
1479                 scsi_conf |= ENSPCHK;
1480         if (sc->adapter_control & CFRESETB)
1481                 scsi_conf |= RESET_SCSI;
1482
1483         ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
1484
1485         if (sc->bios_control & CFEXTEND)
1486                 ahc->flags |= AHC_EXTENDED_TRANS_A;
1487
1488         if (sc->bios_control & CFBIOSEN)
1489                 ahc->flags |= AHC_BIOS_ENABLED;
1490         if (ahc->features & AHC_ULTRA
1491          && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
1492                 /* Should we enable Ultra mode? */
1493                 if (!(sc->adapter_control & CFULTRAEN))
1494                         /* Treat us as a non-ultra card */
1495                         ultraenb = 0;
1496         }
1497
1498         if (sc->signature == CFSIGNATURE
1499          || sc->signature == CFSIGNATURE2) {
1500                 uint32_t devconfig;
1501
1502                 /* Honor the STPWLEVEL settings */
1503                 devconfig = ahc_pci_read_config(ahc->dev_softc,
1504                                                 DEVCONFIG, /*bytes*/4);
1505                 devconfig &= ~STPWLEVEL;
1506                 if ((sc->bios_control & CFSTPWLEVEL) != 0)
1507                         devconfig |= STPWLEVEL;
1508                 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG,
1509                                      devconfig, /*bytes*/4);
1510         }
1511         /* Set SCSICONF info */
1512         ahc_outb(ahc, SCSICONF, scsi_conf);
1513         ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
1514         ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
1515         ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
1516         ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
1517 }
1518
1519 static void
1520 configure_termination(struct ahc_softc *ahc,
1521                       struct seeprom_descriptor *sd,
1522                       u_int adapter_control,
1523                       u_int *sxfrctl1)
1524 {
1525         uint8_t brddat;
1526
1527         brddat = 0;
1528
1529         /*
1530          * Update the settings in sxfrctl1 to match the
1531          * termination settings
1532          */
1533         *sxfrctl1 = 0;
1534
1535         /*
1536          * SEECS must be on for the GALS to latch
1537          * the data properly.  Be sure to leave MS
1538          * on or we will release the seeprom.
1539          */
1540         SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS);
1541         if ((adapter_control & CFAUTOTERM) != 0
1542          || (ahc->features & AHC_NEW_TERMCTL) != 0) {
1543                 int internal50_present;
1544                 int internal68_present;
1545                 int externalcable_present;
1546                 int eeprom_present;
1547                 int enableSEC_low;
1548                 int enableSEC_high;
1549                 int enablePRI_low;
1550                 int enablePRI_high;
1551                 int sum;
1552
1553                 enableSEC_low = 0;
1554                 enableSEC_high = 0;
1555                 enablePRI_low = 0;
1556                 enablePRI_high = 0;
1557                 if ((ahc->features & AHC_NEW_TERMCTL) != 0) {
1558                         ahc_new_term_detect(ahc, &enableSEC_low,
1559                                             &enableSEC_high,
1560                                             &enablePRI_low,
1561                                             &enablePRI_high,
1562                                             &eeprom_present);
1563                         if ((adapter_control & CFSEAUTOTERM) == 0) {
1564                                 if (bootverbose)
1565                                         printk("%s: Manual SE Termination\n",
1566                                                ahc_name(ahc));
1567                                 enableSEC_low = (adapter_control & CFSELOWTERM);
1568                                 enableSEC_high =
1569                                     (adapter_control & CFSEHIGHTERM);
1570                         }
1571                         if ((adapter_control & CFAUTOTERM) == 0) {
1572                                 if (bootverbose)
1573                                         printk("%s: Manual LVD Termination\n",
1574                                                ahc_name(ahc));
1575                                 enablePRI_low = (adapter_control & CFSTERM);
1576                                 enablePRI_high = (adapter_control & CFWSTERM);
1577                         }
1578                         /* Make the table calculations below happy */
1579                         internal50_present = 0;
1580                         internal68_present = 1;
1581                         externalcable_present = 1;
1582                 } else if ((ahc->features & AHC_SPIOCAP) != 0) {
1583                         aic785X_cable_detect(ahc, &internal50_present,
1584                                              &externalcable_present,
1585                                              &eeprom_present);
1586                         /* Can never support a wide connector. */
1587                         internal68_present = 0;
1588                 } else {
1589                         aic787X_cable_detect(ahc, &internal50_present,
1590                                              &internal68_present,
1591                                              &externalcable_present,
1592                                              &eeprom_present);
1593                 }
1594
1595                 if ((ahc->features & AHC_WIDE) == 0)
1596                         internal68_present = 0;
1597
1598                 if (bootverbose
1599                  && (ahc->features & AHC_ULTRA2) == 0) {
1600                         printk("%s: internal 50 cable %s present",
1601                                ahc_name(ahc),
1602                                internal50_present ? "is":"not");
1603
1604                         if ((ahc->features & AHC_WIDE) != 0)
1605                                 printk(", internal 68 cable %s present",
1606                                        internal68_present ? "is":"not");
1607                         printk("\n%s: external cable %s present\n",
1608                                ahc_name(ahc),
1609                                externalcable_present ? "is":"not");
1610                 }
1611                 if (bootverbose)
1612                         printk("%s: BIOS eeprom %s present\n",
1613                                ahc_name(ahc), eeprom_present ? "is" : "not");
1614
1615                 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) {
1616                         /*
1617                          * The 50 pin connector is a separate bus,
1618                          * so force it to always be terminated.
1619                          * In the future, perform current sensing
1620                          * to determine if we are in the middle of
1621                          * a properly terminated bus.
1622                          */
1623                         internal50_present = 0;
1624                 }
1625
1626                 /*
1627                  * Now set the termination based on what
1628                  * we found.
1629                  * Flash Enable = BRDDAT7
1630                  * Secondary High Term Enable = BRDDAT6
1631                  * Secondary Low Term Enable = BRDDAT5 (7890)
1632                  * Primary High Term Enable = BRDDAT4 (7890)
1633                  */
1634                 if ((ahc->features & AHC_ULTRA2) == 0
1635                  && (internal50_present != 0)
1636                  && (internal68_present != 0)
1637                  && (externalcable_present != 0)) {
1638                         printk("%s: Illegal cable configuration!!. "
1639                                "Only two connectors on the "
1640                                "adapter may be used at a "
1641                                "time!\n", ahc_name(ahc));
1642
1643                         /*
1644                          * Pretend there are no cables in the hope
1645                          * that having all of the termination on
1646                          * gives us a more stable bus.
1647                          */
1648                         internal50_present = 0;
1649                         internal68_present = 0;
1650                         externalcable_present = 0;
1651                 }
1652
1653                 if ((ahc->features & AHC_WIDE) != 0
1654                  && ((externalcable_present == 0)
1655                   || (internal68_present == 0)
1656                   || (enableSEC_high != 0))) {
1657                         brddat |= BRDDAT6;
1658                         if (bootverbose) {
1659                                 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1660                                         printk("%s: 68 pin termination "
1661                                                "Enabled\n", ahc_name(ahc));
1662                                 else
1663                                         printk("%s: %sHigh byte termination "
1664                                                "Enabled\n", ahc_name(ahc),
1665                                                enableSEC_high ? "Secondary "
1666                                                               : "");
1667                         }
1668                 }
1669
1670                 sum = internal50_present + internal68_present
1671                     + externalcable_present;
1672                 if (sum < 2 || (enableSEC_low != 0)) {
1673                         if ((ahc->features & AHC_ULTRA2) != 0)
1674                                 brddat |= BRDDAT5;
1675                         else
1676                                 *sxfrctl1 |= STPWEN;
1677                         if (bootverbose) {
1678                                 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1679                                         printk("%s: 50 pin termination "
1680                                                "Enabled\n", ahc_name(ahc));
1681                                 else
1682                                         printk("%s: %sLow byte termination "
1683                                                "Enabled\n", ahc_name(ahc),
1684                                                enableSEC_low ? "Secondary "
1685                                                              : "");
1686                         }
1687                 }
1688
1689                 if (enablePRI_low != 0) {
1690                         *sxfrctl1 |= STPWEN;
1691                         if (bootverbose)
1692                                 printk("%s: Primary Low Byte termination "
1693                                        "Enabled\n", ahc_name(ahc));
1694                 }
1695
1696                 /*
1697                  * Setup STPWEN before setting up the rest of
1698                  * the termination per the tech note on the U160 cards.
1699                  */
1700                 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1701
1702                 if (enablePRI_high != 0) {
1703                         brddat |= BRDDAT4;
1704                         if (bootverbose)
1705                                 printk("%s: Primary High Byte "
1706                                        "termination Enabled\n",
1707                                        ahc_name(ahc));
1708                 }
1709
1710                 write_brdctl(ahc, brddat);
1711
1712         } else {
1713                 if ((adapter_control & CFSTERM) != 0) {
1714                         *sxfrctl1 |= STPWEN;
1715
1716                         if (bootverbose)
1717                                 printk("%s: %sLow byte termination Enabled\n",
1718                                        ahc_name(ahc),
1719                                        (ahc->features & AHC_ULTRA2) ? "Primary "
1720                                                                     : "");
1721                 }
1722
1723                 if ((adapter_control & CFWSTERM) != 0
1724                  && (ahc->features & AHC_WIDE) != 0) {
1725                         brddat |= BRDDAT6;
1726                         if (bootverbose)
1727                                 printk("%s: %sHigh byte termination Enabled\n",
1728                                        ahc_name(ahc),
1729                                        (ahc->features & AHC_ULTRA2)
1730                                      ? "Secondary " : "");
1731                 }
1732
1733                 /*
1734                  * Setup STPWEN before setting up the rest of
1735                  * the termination per the tech note on the U160 cards.
1736                  */
1737                 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1738
1739                 if ((ahc->features & AHC_WIDE) != 0)
1740                         write_brdctl(ahc, brddat);
1741         }
1742         SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */
1743 }
1744
1745 static void
1746 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low,
1747                     int *enableSEC_high, int *enablePRI_low,
1748                     int *enablePRI_high, int *eeprom_present)
1749 {
1750         uint8_t brdctl;
1751
1752         /*
1753          * BRDDAT7 = Eeprom
1754          * BRDDAT6 = Enable Secondary High Byte termination
1755          * BRDDAT5 = Enable Secondary Low Byte termination
1756          * BRDDAT4 = Enable Primary high byte termination
1757          * BRDDAT3 = Enable Primary low byte termination
1758          */
1759         brdctl = read_brdctl(ahc);
1760         *eeprom_present = brdctl & BRDDAT7;
1761         *enableSEC_high = (brdctl & BRDDAT6);
1762         *enableSEC_low = (brdctl & BRDDAT5);
1763         *enablePRI_high = (brdctl & BRDDAT4);
1764         *enablePRI_low = (brdctl & BRDDAT3);
1765 }
1766
1767 static void
1768 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1769                      int *internal68_present, int *externalcable_present,
1770                      int *eeprom_present)
1771 {
1772         uint8_t brdctl;
1773
1774         /*
1775          * First read the status of our cables.
1776          * Set the rom bank to 0 since the
1777          * bank setting serves as a multiplexor
1778          * for the cable detection logic.
1779          * BRDDAT5 controls the bank switch.
1780          */
1781         write_brdctl(ahc, 0);
1782
1783         /*
1784          * Now read the state of the internal
1785          * connectors.  BRDDAT6 is INT50 and
1786          * BRDDAT7 is INT68.
1787          */
1788         brdctl = read_brdctl(ahc);
1789         *internal50_present = (brdctl & BRDDAT6) ? 0 : 1;
1790         *internal68_present = (brdctl & BRDDAT7) ? 0 : 1;
1791
1792         /*
1793          * Set the rom bank to 1 and determine
1794          * the other signals.
1795          */
1796         write_brdctl(ahc, BRDDAT5);
1797
1798         /*
1799          * Now read the state of the external
1800          * connectors.  BRDDAT6 is EXT68 and
1801          * BRDDAT7 is EPROMPS.
1802          */
1803         brdctl = read_brdctl(ahc);
1804         *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1805         *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0;
1806 }
1807
1808 static void
1809 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1810                      int *externalcable_present, int *eeprom_present)
1811 {
1812         uint8_t brdctl;
1813         uint8_t spiocap;
1814
1815         spiocap = ahc_inb(ahc, SPIOCAP);
1816         spiocap &= ~SOFTCMDEN;
1817         spiocap |= EXT_BRDCTL;
1818         ahc_outb(ahc, SPIOCAP, spiocap);
1819         ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
1820         ahc_flush_device_writes(ahc);
1821         ahc_delay(500);
1822         ahc_outb(ahc, BRDCTL, 0);
1823         ahc_flush_device_writes(ahc);
1824         ahc_delay(500);
1825         brdctl = ahc_inb(ahc, BRDCTL);
1826         *internal50_present = (brdctl & BRDDAT5) ? 0 : 1;
1827         *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1828         *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0;
1829 }
1830
1831 int
1832 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd)
1833 {
1834         int wait;
1835
1836         if ((ahc->features & AHC_SPIOCAP) != 0
1837          && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0)
1838                 return (0);
1839
1840         /*
1841          * Request access of the memory port.  When access is
1842          * granted, SEERDY will go high.  We use a 1 second
1843          * timeout which should be near 1 second more than
1844          * is needed.  Reason: after the chip reset, there
1845          * should be no contention.
1846          */
1847         SEEPROM_OUTB(sd, sd->sd_MS);
1848         wait = 1000;  /* 1 second timeout in msec */
1849         while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) {
1850                 ahc_delay(1000);  /* delay 1 msec */
1851         }
1852         if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) {
1853                 SEEPROM_OUTB(sd, 0);
1854                 return (0);
1855         }
1856         return(1);
1857 }
1858
1859 void
1860 ahc_release_seeprom(struct seeprom_descriptor *sd)
1861 {
1862         /* Release access to the memory port and the serial EEPROM. */
1863         SEEPROM_OUTB(sd, 0);
1864 }
1865
1866 static void
1867 write_brdctl(struct ahc_softc *ahc, uint8_t value)
1868 {
1869         uint8_t brdctl;
1870
1871         if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1872                 brdctl = BRDSTB;
1873                 if (ahc->channel == 'B')
1874                         brdctl |= BRDCS;
1875         } else if ((ahc->features & AHC_ULTRA2) != 0) {
1876                 brdctl = 0;
1877         } else {
1878                 brdctl = BRDSTB|BRDCS;
1879         }
1880         ahc_outb(ahc, BRDCTL, brdctl);
1881         ahc_flush_device_writes(ahc);
1882         brdctl |= value;
1883         ahc_outb(ahc, BRDCTL, brdctl);
1884         ahc_flush_device_writes(ahc);
1885         if ((ahc->features & AHC_ULTRA2) != 0)
1886                 brdctl |= BRDSTB_ULTRA2;
1887         else
1888                 brdctl &= ~BRDSTB;
1889         ahc_outb(ahc, BRDCTL, brdctl);
1890         ahc_flush_device_writes(ahc);
1891         if ((ahc->features & AHC_ULTRA2) != 0)
1892                 brdctl = 0;
1893         else
1894                 brdctl &= ~BRDCS;
1895         ahc_outb(ahc, BRDCTL, brdctl);
1896 }
1897
1898 static uint8_t
1899 read_brdctl(struct ahc_softc *ahc)
1900 {
1901         uint8_t brdctl;
1902         uint8_t value;
1903
1904         if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1905                 brdctl = BRDRW;
1906                 if (ahc->channel == 'B')
1907                         brdctl |= BRDCS;
1908         } else if ((ahc->features & AHC_ULTRA2) != 0) {
1909                 brdctl = BRDRW_ULTRA2;
1910         } else {
1911                 brdctl = BRDRW|BRDCS;
1912         }
1913         ahc_outb(ahc, BRDCTL, brdctl);
1914         ahc_flush_device_writes(ahc);
1915         value = ahc_inb(ahc, BRDCTL);
1916         ahc_outb(ahc, BRDCTL, 0);
1917         return (value);
1918 }
1919
1920 static void
1921 ahc_pci_intr(struct ahc_softc *ahc)
1922 {
1923         u_int error;
1924         u_int status1;
1925
1926         error = ahc_inb(ahc, ERROR);
1927         if ((error & PCIERRSTAT) == 0)
1928                 return;
1929
1930         status1 = ahc_pci_read_config(ahc->dev_softc,
1931                                       PCIR_STATUS + 1, /*bytes*/1);
1932
1933         printk("%s: PCI error Interrupt at seqaddr = 0x%x\n",
1934               ahc_name(ahc),
1935               ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
1936
1937         if (status1 & DPE) {
1938                 ahc->pci_target_perr_count++;
1939                 printk("%s: Data Parity Error Detected during address "
1940                        "or write data phase\n", ahc_name(ahc));
1941         }
1942         if (status1 & SSE) {
1943                 printk("%s: Signal System Error Detected\n", ahc_name(ahc));
1944         }
1945         if (status1 & RMA) {
1946                 printk("%s: Received a Master Abort\n", ahc_name(ahc));
1947         }
1948         if (status1 & RTA) {
1949                 printk("%s: Received a Target Abort\n", ahc_name(ahc));
1950         }
1951         if (status1 & STA) {
1952                 printk("%s: Signaled a Target Abort\n", ahc_name(ahc));
1953         }
1954         if (status1 & DPR) {
1955                 printk("%s: Data Parity Error has been reported via PERR#\n",
1956                        ahc_name(ahc));
1957         }
1958
1959         /* Clear latched errors. */
1960         ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1961                              status1, /*bytes*/1);
1962
1963         if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
1964                 printk("%s: Latched PCIERR interrupt with "
1965                        "no status bits set\n", ahc_name(ahc));
1966         } else {
1967                 ahc_outb(ahc, CLRINT, CLRPARERR);
1968         }
1969
1970         if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH) {
1971                 printk(
1972 "%s: WARNING WARNING WARNING WARNING\n"
1973 "%s: Too many PCI parity errors observed as a target.\n"
1974 "%s: Some device on this bus is generating bad parity.\n"
1975 "%s: This is an error *observed by*, not *generated by*, this controller.\n"
1976 "%s: PCI parity error checking has been disabled.\n"
1977 "%s: WARNING WARNING WARNING WARNING\n",
1978                        ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
1979                        ahc_name(ahc), ahc_name(ahc), ahc_name(ahc));
1980                 ahc->seqctl |= FAILDIS;
1981                 ahc_outb(ahc, SEQCTL, ahc->seqctl);
1982         }
1983         ahc_unpause(ahc);
1984 }
1985
1986 static int
1987 ahc_pci_chip_init(struct ahc_softc *ahc)
1988 {
1989         ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
1990         ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
1991         if ((ahc->features & AHC_DT) != 0) {
1992                 u_int sfunct;
1993
1994                 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
1995                 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
1996                 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
1997                 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
1998                 ahc_outb(ahc, SFUNCT, sfunct);
1999                 ahc_outb(ahc, CRCCONTROL1,
2000                          ahc->bus_softc.pci_softc.crccontrol1);
2001         }
2002         if ((ahc->features & AHC_MULTI_FUNC) != 0)
2003                 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
2004
2005         if ((ahc->features & AHC_ULTRA2) != 0)
2006                 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
2007
2008         return (ahc_chip_init(ahc));
2009 }
2010
2011 void __maybe_unused
2012 ahc_pci_resume(struct ahc_softc *ahc)
2013 {
2014         /*
2015          * We assume that the OS has restored our register
2016          * mappings, etc.  Just update the config space registers
2017          * that the OS doesn't know about and rely on our chip
2018          * reset handler to handle the rest.
2019          */
2020         ahc_pci_write_config(ahc->dev_softc, DEVCONFIG,
2021                              ahc->bus_softc.pci_softc.devconfig, /*bytes*/4);
2022         ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
2023                              ahc->bus_softc.pci_softc.command, /*bytes*/1);
2024         ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
2025                              ahc->bus_softc.pci_softc.csize_lattime, /*bytes*/1);
2026         if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) {
2027                 struct  seeprom_descriptor sd;
2028                 u_int   sxfrctl1;
2029
2030                 sd.sd_ahc = ahc;
2031                 sd.sd_control_offset = SEECTL;
2032                 sd.sd_status_offset = SEECTL;
2033                 sd.sd_dataout_offset = SEECTL;
2034
2035                 ahc_acquire_seeprom(ahc, &sd);
2036                 configure_termination(ahc, &sd,
2037                                       ahc->seep_config->adapter_control,
2038                                       &sxfrctl1);
2039                 ahc_release_seeprom(&sd);
2040         }
2041 }
2042
2043 static int
2044 ahc_aic785X_setup(struct ahc_softc *ahc)
2045 {
2046         ahc_dev_softc_t pci;
2047         uint8_t rev;
2048
2049         pci = ahc->dev_softc;
2050         ahc->channel = 'A';
2051         ahc->chip = AHC_AIC7850;
2052         ahc->features = AHC_AIC7850_FE;
2053         ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2054         rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2055         if (rev >= 1)
2056                 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2057         ahc->instruction_ram_size = 512;
2058         return (0);
2059 }
2060
2061 static int
2062 ahc_aic7860_setup(struct ahc_softc *ahc)
2063 {
2064         ahc_dev_softc_t pci;
2065         uint8_t rev;
2066
2067         pci = ahc->dev_softc;
2068         ahc->channel = 'A';
2069         ahc->chip = AHC_AIC7860;
2070         ahc->features = AHC_AIC7860_FE;
2071         ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2072         rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2073         if (rev >= 1)
2074                 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2075         ahc->instruction_ram_size = 512;
2076         return (0);
2077 }
2078
2079 static int
2080 ahc_apa1480_setup(struct ahc_softc *ahc)
2081 {
2082         int error;
2083
2084         error = ahc_aic7860_setup(ahc);
2085         if (error != 0)
2086                 return (error);
2087         ahc->features |= AHC_REMOVABLE;
2088         return (0);
2089 }
2090
2091 static int
2092 ahc_aic7870_setup(struct ahc_softc *ahc)
2093 {
2094
2095         ahc->channel = 'A';
2096         ahc->chip = AHC_AIC7870;
2097         ahc->features = AHC_AIC7870_FE;
2098         ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2099         ahc->instruction_ram_size = 512;
2100         return (0);
2101 }
2102
2103 static int
2104 ahc_aic7870h_setup(struct ahc_softc *ahc)
2105 {
2106         int error = ahc_aic7870_setup(ahc);
2107
2108         ahc->features |= AHC_HVD;
2109
2110         return error;
2111 }
2112
2113 static int
2114 ahc_aha394X_setup(struct ahc_softc *ahc)
2115 {
2116         int error;
2117
2118         error = ahc_aic7870_setup(ahc);
2119         if (error == 0)
2120                 error = ahc_aha394XX_setup(ahc);
2121         return (error);
2122 }
2123
2124 static int
2125 ahc_aha394Xh_setup(struct ahc_softc *ahc)
2126 {
2127         int error = ahc_aha394X_setup(ahc);
2128
2129         ahc->features |= AHC_HVD;
2130
2131         return error;
2132 }
2133
2134 static int
2135 ahc_aha398X_setup(struct ahc_softc *ahc)
2136 {
2137         int error;
2138
2139         error = ahc_aic7870_setup(ahc);
2140         if (error == 0)
2141                 error = ahc_aha398XX_setup(ahc);
2142         return (error);
2143 }
2144
2145 static int
2146 ahc_aha494X_setup(struct ahc_softc *ahc)
2147 {
2148         int error;
2149
2150         error = ahc_aic7870_setup(ahc);
2151         if (error == 0)
2152                 error = ahc_aha494XX_setup(ahc);
2153         return (error);
2154 }
2155
2156 static int
2157 ahc_aha494Xh_setup(struct ahc_softc *ahc)
2158 {
2159         int error = ahc_aha494X_setup(ahc);
2160
2161         ahc->features |= AHC_HVD;
2162
2163         return error;
2164 }
2165
2166 static int
2167 ahc_aic7880_setup(struct ahc_softc *ahc)
2168 {
2169         ahc_dev_softc_t pci;
2170         uint8_t rev;
2171
2172         pci = ahc->dev_softc;
2173         ahc->channel = 'A';
2174         ahc->chip = AHC_AIC7880;
2175         ahc->features = AHC_AIC7880_FE;
2176         ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
2177         rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2178         if (rev >= 1) {
2179                 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2180         } else {
2181                 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2182         }
2183         ahc->instruction_ram_size = 512;
2184         return (0);
2185 }
2186
2187 static int
2188 ahc_aic7880h_setup(struct ahc_softc *ahc)
2189 {
2190         int error = ahc_aic7880_setup(ahc);
2191
2192         ahc->features |= AHC_HVD;
2193
2194         return error;
2195 }
2196
2197
2198 static int
2199 ahc_aha2940Pro_setup(struct ahc_softc *ahc)
2200 {
2201
2202         ahc->flags |= AHC_INT50_SPEEDFLEX;
2203         return (ahc_aic7880_setup(ahc));
2204 }
2205
2206 static int
2207 ahc_aha394XU_setup(struct ahc_softc *ahc)
2208 {
2209         int error;
2210
2211         error = ahc_aic7880_setup(ahc);
2212         if (error == 0)
2213                 error = ahc_aha394XX_setup(ahc);
2214         return (error);
2215 }
2216
2217 static int
2218 ahc_aha394XUh_setup(struct ahc_softc *ahc)
2219 {
2220         int error = ahc_aha394XU_setup(ahc);
2221
2222         ahc->features |= AHC_HVD;
2223
2224         return error;
2225 }
2226
2227 static int
2228 ahc_aha398XU_setup(struct ahc_softc *ahc)
2229 {
2230         int error;
2231
2232         error = ahc_aic7880_setup(ahc);
2233         if (error == 0)
2234                 error = ahc_aha398XX_setup(ahc);
2235         return (error);
2236 }
2237
2238 static int
2239 ahc_aic7890_setup(struct ahc_softc *ahc)
2240 {
2241         ahc_dev_softc_t pci;
2242         uint8_t rev;
2243
2244         pci = ahc->dev_softc;
2245         ahc->channel = 'A';
2246         ahc->chip = AHC_AIC7890;
2247         ahc->features = AHC_AIC7890_FE;
2248         ahc->flags |= AHC_NEWEEPROM_FMT;
2249         rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2250         if (rev == 0)
2251                 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
2252         ahc->instruction_ram_size = 768;
2253         return (0);
2254 }
2255
2256 static int
2257 ahc_aic7892_setup(struct ahc_softc *ahc)
2258 {
2259
2260         ahc->channel = 'A';
2261         ahc->chip = AHC_AIC7892;
2262         ahc->features = AHC_AIC7892_FE;
2263         ahc->flags |= AHC_NEWEEPROM_FMT;
2264         ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2265         ahc->instruction_ram_size = 1024;
2266         return (0);
2267 }
2268
2269 static int
2270 ahc_aic7895_setup(struct ahc_softc *ahc)
2271 {
2272         ahc_dev_softc_t pci;
2273         uint8_t rev;
2274
2275         pci = ahc->dev_softc;
2276         ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2277         /*
2278          * The 'C' revision of the aic7895 has a few additional features.
2279          */
2280         rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2281         if (rev >= 4) {
2282                 ahc->chip = AHC_AIC7895C;
2283                 ahc->features = AHC_AIC7895C_FE;
2284         } else  {
2285                 u_int command;
2286
2287                 ahc->chip = AHC_AIC7895;
2288                 ahc->features = AHC_AIC7895_FE;
2289
2290                 /*
2291                  * The BIOS disables the use of MWI transactions
2292                  * since it does not have the MWI bug work around
2293                  * we have.  Disabling MWI reduces performance, so
2294                  * turn it on again.
2295                  */
2296                 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1);
2297                 command |= PCIM_CMD_MWRICEN;
2298                 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1);
2299                 ahc->bugs |= AHC_PCI_MWI_BUG;
2300         }
2301         /*
2302          * XXX Does CACHETHEN really not work???  What about PCI retry?
2303          * on C level chips.  Need to test, but for now, play it safe.
2304          */
2305         ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
2306                   |  AHC_CACHETHEN_BUG;
2307
2308 #if 0
2309         uint32_t devconfig;
2310
2311         /*
2312          * Cachesize must also be zero due to stray DAC
2313          * problem when sitting behind some bridges.
2314          */
2315         ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1);
2316         devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1);
2317         devconfig |= MRDCEN;
2318         ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1);
2319 #endif
2320         ahc->flags |= AHC_NEWEEPROM_FMT;
2321         ahc->instruction_ram_size = 512;
2322         return (0);
2323 }
2324
2325 static int
2326 ahc_aic7895h_setup(struct ahc_softc *ahc)
2327 {
2328         int error = ahc_aic7895_setup(ahc);
2329
2330         ahc->features |= AHC_HVD;
2331
2332         return error;
2333 }
2334
2335 static int
2336 ahc_aic7896_setup(struct ahc_softc *ahc)
2337 {
2338         ahc_dev_softc_t pci;
2339
2340         pci = ahc->dev_softc;
2341         ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2342         ahc->chip = AHC_AIC7896;
2343         ahc->features = AHC_AIC7896_FE;
2344         ahc->flags |= AHC_NEWEEPROM_FMT;
2345         ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
2346         ahc->instruction_ram_size = 768;
2347         return (0);
2348 }
2349
2350 static int
2351 ahc_aic7899_setup(struct ahc_softc *ahc)
2352 {
2353         ahc_dev_softc_t pci;
2354
2355         pci = ahc->dev_softc;
2356         ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2357         ahc->chip = AHC_AIC7899;
2358         ahc->features = AHC_AIC7899_FE;
2359         ahc->flags |= AHC_NEWEEPROM_FMT;
2360         ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2361         ahc->instruction_ram_size = 1024;
2362         return (0);
2363 }
2364
2365 static int
2366 ahc_aha29160C_setup(struct ahc_softc *ahc)
2367 {
2368         int error;
2369
2370         error = ahc_aic7899_setup(ahc);
2371         if (error != 0)
2372                 return (error);
2373         ahc->features |= AHC_REMOVABLE;
2374         return (0);
2375 }
2376
2377 static int
2378 ahc_raid_setup(struct ahc_softc *ahc)
2379 {
2380         printk("RAID functionality unsupported\n");
2381         return (ENXIO);
2382 }
2383
2384 static int
2385 ahc_aha394XX_setup(struct ahc_softc *ahc)
2386 {
2387         ahc_dev_softc_t pci;
2388
2389         pci = ahc->dev_softc;
2390         switch (ahc_get_pci_slot(pci)) {
2391         case AHC_394X_SLOT_CHANNEL_A:
2392                 ahc->channel = 'A';
2393                 break;
2394         case AHC_394X_SLOT_CHANNEL_B:
2395                 ahc->channel = 'B';
2396                 break;
2397         default:
2398                 printk("adapter at unexpected slot %d\n"
2399                        "unable to map to a channel\n",
2400                        ahc_get_pci_slot(pci));
2401                 ahc->channel = 'A';
2402         }
2403         return (0);
2404 }
2405
2406 static int
2407 ahc_aha398XX_setup(struct ahc_softc *ahc)
2408 {
2409         ahc_dev_softc_t pci;
2410
2411         pci = ahc->dev_softc;
2412         switch (ahc_get_pci_slot(pci)) {
2413         case AHC_398X_SLOT_CHANNEL_A:
2414                 ahc->channel = 'A';
2415                 break;
2416         case AHC_398X_SLOT_CHANNEL_B:
2417                 ahc->channel = 'B';
2418                 break;
2419         case AHC_398X_SLOT_CHANNEL_C:
2420                 ahc->channel = 'C';
2421                 break;
2422         default:
2423                 printk("adapter at unexpected slot %d\n"
2424                        "unable to map to a channel\n",
2425                        ahc_get_pci_slot(pci));
2426                 ahc->channel = 'A';
2427                 break;
2428         }
2429         ahc->flags |= AHC_LARGE_SEEPROM;
2430         return (0);
2431 }
2432
2433 static int
2434 ahc_aha494XX_setup(struct ahc_softc *ahc)
2435 {
2436         ahc_dev_softc_t pci;
2437
2438         pci = ahc->dev_softc;
2439         switch (ahc_get_pci_slot(pci)) {
2440         case AHC_494X_SLOT_CHANNEL_A:
2441                 ahc->channel = 'A';
2442                 break;
2443         case AHC_494X_SLOT_CHANNEL_B:
2444                 ahc->channel = 'B';
2445                 break;
2446         case AHC_494X_SLOT_CHANNEL_C:
2447                 ahc->channel = 'C';
2448                 break;
2449         case AHC_494X_SLOT_CHANNEL_D:
2450                 ahc->channel = 'D';
2451                 break;
2452         default:
2453                 printk("adapter at unexpected slot %d\n"
2454                        "unable to map to a channel\n",
2455                        ahc_get_pci_slot(pci));
2456                 ahc->channel = 'A';
2457         }
2458         ahc->flags |= AHC_LARGE_SEEPROM;
2459         return (0);
2460 }