2 * Product specific probe and attach routines for:
3 * aic7901 and aic7902 SCSI controllers
5 * Copyright (c) 1994-2001 Justin T. Gibbs.
6 * Copyright (c) 2000-2002 Adaptec Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
16 * substantially similar to the "NO WARRANTY" disclaimer below
17 * ("Disclaimer") and any redistribution must be conditioned upon
18 * including a substantially similar Disclaimer requirement for further
19 * binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGES.
41 * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#92 $
44 #include "aic79xx_osm.h"
45 #include "aic79xx_inline.h"
46 #include "aic79xx_pci.h"
48 static inline uint64_t
49 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
55 | ((uint64_t)vendor << 32)
56 | ((uint64_t)device << 48);
61 #define ID_AIC7902_PCI_REV_A4 0x3
62 #define ID_AIC7902_PCI_REV_B0 0x10
63 #define SUBID_HP 0x0E11
65 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80)
67 #define DEVID_9005_TYPE(id) ((id) & 0xF)
68 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
69 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */
70 #define DEVID_9005_TYPE_IROC 0x8 /* Raid(0,1,10) Card */
71 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
73 #define DEVID_9005_MFUNC(id) ((id) & 0x10)
75 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000)
77 #define SUBID_9005_TYPE(id) ((id) & 0xF)
78 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */
79 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
81 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0)
83 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20)
85 #define SUBID_9005_SEEPTYPE(id) (((id) & 0x0C0) >> 6)
86 #define SUBID_9005_SEEPTYPE_NONE 0x0
87 #define SUBID_9005_SEEPTYPE_4K 0x1
89 static ahd_device_setup_t ahd_aic7901_setup;
90 static ahd_device_setup_t ahd_aic7901A_setup;
91 static ahd_device_setup_t ahd_aic7902_setup;
92 static ahd_device_setup_t ahd_aic790X_setup;
94 static const struct ahd_pci_identity ahd_pci_ident_table[] =
96 /* aic7901 based controllers */
100 "Adaptec 29320A Ultra320 SCSI adapter",
106 "Adaptec 29320ALP PCIx Ultra320 SCSI adapter",
112 "Adaptec 29320LPE PCIe Ultra320 SCSI adapter",
115 /* aic7901A based controllers */
119 "Adaptec 29320LP Ultra320 SCSI adapter",
122 /* aic7902 based controllers */
126 "Adaptec 29320 Ultra320 SCSI adapter",
132 "Adaptec 29320B Ultra320 SCSI adapter",
138 "Adaptec 39320 Ultra320 SCSI adapter",
144 "Adaptec 39320 Ultra320 SCSI adapter",
150 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter",
156 "Adaptec 39320A Ultra320 SCSI adapter",
162 "Adaptec 39320D Ultra320 SCSI adapter",
168 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
174 "Adaptec 39320D Ultra320 SCSI adapter",
180 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
183 /* Generic chip probes for devices we don't know 'exactly' */
185 ID_AIC7901 & ID_9005_GENERIC_MASK,
186 ID_9005_GENERIC_MASK,
187 "Adaptec AIC7901 Ultra320 SCSI adapter",
191 ID_AIC7901A & ID_DEV_VENDOR_MASK,
193 "Adaptec AIC7901A Ultra320 SCSI adapter",
197 ID_AIC7902 & ID_9005_GENERIC_MASK,
198 ID_9005_GENERIC_MASK,
199 "Adaptec AIC7902 Ultra320 SCSI adapter",
204 static const u_int ahd_num_pci_devs = ARRAY_SIZE(ahd_pci_ident_table);
206 #define DEVCONFIG 0x40
207 #define PCIXINITPAT 0x0000E000ul
208 #define PCIXINIT_PCI33_66 0x0000E000ul
209 #define PCIXINIT_PCIX50_66 0x0000C000ul
210 #define PCIXINIT_PCIX66_100 0x0000A000ul
211 #define PCIXINIT_PCIX100_133 0x00008000ul
212 #define PCI_BUS_MODES_INDEX(devconfig) \
213 (((devconfig) & PCIXINITPAT) >> 13)
214 static const char *pci_bus_modes[] =
216 "PCI bus mode unknown",
217 "PCI bus mode unknown",
218 "PCI bus mode unknown",
219 "PCI bus mode unknown",
226 #define TESTMODE 0x00000800ul
227 #define IRDY_RST 0x00000200ul
228 #define FRAME_RST 0x00000100ul
229 #define PCI64BIT 0x00000080ul
230 #define MRDCEN 0x00000040ul
231 #define ENDIANSEL 0x00000020ul
232 #define MIXQWENDIANEN 0x00000008ul
233 #define DACEN 0x00000004ul
234 #define STPWLEVEL 0x00000002ul
235 #define QWENDIANSEL 0x00000001ul
237 #define DEVCONFIG1 0x44
240 #define CSIZE_LATTIME 0x0c
241 #define CACHESIZE 0x000000fful
242 #define LATTIME 0x0000ff00ul
244 static int ahd_check_extport(struct ahd_softc *ahd);
245 static void ahd_configure_termination(struct ahd_softc *ahd,
246 u_int adapter_control);
247 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat);
248 static void ahd_pci_intr(struct ahd_softc *ahd);
250 const struct ahd_pci_identity *
251 ahd_find_pci_device(ahd_dev_softc_t pci)
258 const struct ahd_pci_identity *entry;
261 vendor = ahd_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
262 device = ahd_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
263 subvendor = ahd_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
264 subdevice = ahd_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
265 full_id = ahd_compose_id(device,
271 * Controllers, mask out the IROC/HostRAID bit
274 full_id &= ID_ALL_IROC_MASK;
276 for (i = 0; i < ahd_num_pci_devs; i++) {
277 entry = &ahd_pci_ident_table[i];
278 if (entry->full_id == (full_id & entry->id_mask)) {
279 /* Honor exclusion entries. */
280 if (entry->name == NULL)
289 ahd_pci_config(struct ahd_softc *ahd, const struct ahd_pci_identity *entry)
291 struct scb_data *shared_scb_data;
297 shared_scb_data = NULL;
298 ahd->description = entry->name;
300 * Record if this is an HP board.
302 subvendor = ahd_pci_read_config(ahd->dev_softc,
303 PCIR_SUBVEND_0, /*bytes*/2);
304 if (subvendor == SUBID_HP)
305 ahd->flags |= AHD_HP_BOARD;
307 error = entry->setup(ahd);
311 devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
312 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
313 ahd->chip |= AHD_PCI;
314 /* Disable PCIX workarounds when running in PCI mode. */
315 ahd->bugs &= ~AHD_PCIX_BUG_MASK;
317 ahd->chip |= AHD_PCIX;
319 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
321 ahd_power_state_change(ahd, AHD_POWER_STATE_D0);
323 error = ahd_pci_map_registers(ahd);
328 * If we need to support high memory, enable dual
329 * address cycles. This bit must be set to enable
330 * high address bit generation even if we are on a
331 * 64bit bus (PCI64BIT set in devconfig).
333 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
335 printk("%s: Enabling 39Bit Addressing\n",
337 devconfig = ahd_pci_read_config(ahd->dev_softc,
338 DEVCONFIG, /*bytes*/4);
340 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG,
341 devconfig, /*bytes*/4);
344 /* Ensure busmastering is enabled */
345 command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
346 command |= PCIM_CMD_BUSMASTEREN;
347 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
349 error = ahd_softc_init(ahd);
353 ahd->bus_intr = ahd_pci_intr;
355 error = ahd_reset(ahd, /*reinit*/FALSE);
360 ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME,
361 /*bytes*/1) & CACHESIZE;
362 ahd->pci_cachesize *= 4;
364 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
365 /* See if we have a SEEPROM and perform auto-term */
366 error = ahd_check_extport(ahd);
370 /* Core initialization */
371 error = ahd_init(ahd);
377 * Allow interrupts now that we are completely setup.
379 return ahd_pci_map_int(ahd);
384 ahd_pci_suspend(struct ahd_softc *ahd)
387 * Save chip register configuration data for chip resets
388 * that occur during runtime and resume events.
390 ahd->suspend_state.pci_state.devconfig =
391 ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
392 ahd->suspend_state.pci_state.command =
393 ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/1);
394 ahd->suspend_state.pci_state.csize_lattime =
395 ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, /*bytes*/1);
400 ahd_pci_resume(struct ahd_softc *ahd)
402 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG,
403 ahd->suspend_state.pci_state.devconfig, /*bytes*/4);
404 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
405 ahd->suspend_state.pci_state.command, /*bytes*/1);
406 ahd_pci_write_config(ahd->dev_softc, CSIZE_LATTIME,
407 ahd->suspend_state.pci_state.csize_lattime, /*bytes*/1);
412 * Perform some simple tests that should catch situations where
413 * our registers are invalidly mapped.
416 ahd_pci_test_register_access(struct ahd_softc *ahd)
427 * Enable PCI error interrupt status, but suppress NMIs
428 * generated by SERR raised due to target aborts.
430 cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
431 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
432 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
435 * First a simple test to see if any
436 * registers can be read. Reading
437 * HCNTRL has no side effects and has
438 * at least one bit that is guaranteed to
439 * be zero so it is a good register to
442 hcntrl = ahd_inb(ahd, HCNTRL);
447 * Next create a situation where write combining
448 * or read prefetching could be initiated by the
449 * CPU or host bridge. Our device does not support
450 * either, so look for data corruption and/or flaged
451 * PCI errors. First pause without causing another
455 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE);
456 while (ahd_is_paused(ahd) == 0)
459 /* Clear any PCI errors that occurred before our driver attached. */
460 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
461 targpcistat = ahd_inb(ahd, TARGPCISTAT);
462 ahd_outb(ahd, TARGPCISTAT, targpcistat);
463 pci_status1 = ahd_pci_read_config(ahd->dev_softc,
464 PCIR_STATUS + 1, /*bytes*/1);
465 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
466 pci_status1, /*bytes*/1);
467 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
468 ahd_outb(ahd, CLRINT, CLRPCIINT);
470 ahd_outb(ahd, SEQCTL0, PERRORDIS);
471 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa);
472 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa)
475 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
476 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
477 targpcistat = ahd_inb(ahd, TARGPCISTAT);
478 if ((targpcistat & STA) != 0)
485 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
487 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
488 targpcistat = ahd_inb(ahd, TARGPCISTAT);
490 /* Silently clear any latched errors. */
491 ahd_outb(ahd, TARGPCISTAT, targpcistat);
492 pci_status1 = ahd_pci_read_config(ahd->dev_softc,
493 PCIR_STATUS + 1, /*bytes*/1);
494 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
495 pci_status1, /*bytes*/1);
496 ahd_outb(ahd, CLRINT, CLRPCIINT);
498 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS);
499 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
504 * Check the external port logic for a serial eeprom
505 * and termination/cable detection contrls.
508 ahd_check_extport(struct ahd_softc *ahd)
510 struct vpd_config vpd;
511 struct seeprom_config *sc;
512 u_int adapter_control;
516 sc = ahd->seep_config;
517 have_seeprom = ahd_acquire_seeprom(ahd);
522 * Fetch VPD for this function and parse it.
525 printk("%s: Reading VPD from SEEPROM...",
528 /* Address is always in units of 16bit words */
529 start_addr = ((2 * sizeof(*sc))
530 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2;
532 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd,
533 start_addr, sizeof(vpd)/2,
536 error = ahd_parse_vpddata(ahd, &vpd);
538 printk("%s: VPD parsing %s\n",
540 error == 0 ? "successful" : "failed");
543 printk("%s: Reading SEEPROM...", ahd_name(ahd));
545 /* Address is always in units of 16bit words */
546 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A');
548 error = ahd_read_seeprom(ahd, (uint16_t *)sc,
549 start_addr, sizeof(*sc)/2,
550 /*bytestream*/FALSE);
553 printk("Unable to read SEEPROM\n");
556 have_seeprom = ahd_verify_cksum(sc);
559 if (have_seeprom == 0)
560 printk ("checksum error\n");
565 ahd_release_seeprom(ahd);
572 * Pull scratch ram settings and treat them as
573 * if they are the contents of an seeprom if
574 * the 'ADPT', 'BIOS', or 'ASPI' signature is found
575 * in SCB 0xFF. We manually compose the data as 16bit
576 * values to avoid endian issues.
578 ahd_set_scbptr(ahd, 0xFF);
579 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET);
580 if (nvram_scb != 0xFF
581 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
582 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D'
583 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
584 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T')
585 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B'
586 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I'
587 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O'
588 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S')
589 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
590 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S'
591 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
592 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) {
596 ahd_set_scbptr(ahd, nvram_scb);
597 sc_data = (uint16_t *)sc;
598 for (i = 0; i < 64; i += 2)
599 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i);
600 have_seeprom = ahd_verify_cksum(sc);
602 ahd->flags |= AHD_SCB_CONFIG_USED;
607 if (have_seeprom != 0
608 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) {
612 printk("%s: Seeprom Contents:", ahd_name(ahd));
613 sc_data = (uint16_t *)sc;
614 for (i = 0; i < (sizeof(*sc)); i += 2)
615 printk("\n\t0x%.4x", sc_data[i]);
622 printk("%s: No SEEPROM available.\n", ahd_name(ahd));
623 ahd->flags |= AHD_USEDEFAULTS;
624 error = ahd_default_config(ahd);
625 adapter_control = CFAUTOTERM|CFSEAUTOTERM;
626 kfree(ahd->seep_config);
627 ahd->seep_config = NULL;
629 error = ahd_parse_cfgdata(ahd, sc);
630 adapter_control = sc->adapter_control;
635 ahd_configure_termination(ahd, adapter_control);
641 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control)
648 devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
649 devconfig &= ~STPWLEVEL;
650 if ((ahd->flags & AHD_STPWLEVEL_A) != 0)
651 devconfig |= STPWLEVEL;
653 printk("%s: STPWLEVEL is %s\n",
654 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off");
655 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
657 /* Make sure current sensing is off. */
658 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) {
659 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
663 * Read to sense. Write to set.
665 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl);
666 if ((adapter_control & CFAUTOTERM) == 0) {
668 printk("%s: Manual Primary Termination\n",
670 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH);
671 if ((adapter_control & CFSTERM) != 0)
672 termctl |= FLX_TERMCTL_ENPRILOW;
673 if ((adapter_control & CFWSTERM) != 0)
674 termctl |= FLX_TERMCTL_ENPRIHIGH;
675 } else if (error != 0) {
676 printk("%s: Primary Auto-Term Sensing failed! "
677 "Using Defaults.\n", ahd_name(ahd));
678 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH;
681 if ((adapter_control & CFSEAUTOTERM) == 0) {
683 printk("%s: Manual Secondary Termination\n",
685 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH);
686 if ((adapter_control & CFSELOWTERM) != 0)
687 termctl |= FLX_TERMCTL_ENSECLOW;
688 if ((adapter_control & CFSEHIGHTERM) != 0)
689 termctl |= FLX_TERMCTL_ENSECHIGH;
690 } else if (error != 0) {
691 printk("%s: Secondary Auto-Term Sensing failed! "
692 "Using Defaults.\n", ahd_name(ahd));
693 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH;
697 * Now set the termination based on what we found.
699 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN;
700 ahd->flags &= ~AHD_TERM_ENB_A;
701 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) {
702 ahd->flags |= AHD_TERM_ENB_A;
705 /* Must set the latch once in order to be effective. */
706 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
707 ahd_outb(ahd, SXFRCTL1, sxfrctl1);
709 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl);
711 printk("%s: Unable to set termination settings!\n",
713 } else if (bootverbose) {
714 printk("%s: Primary High byte termination %sabled\n",
716 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis");
718 printk("%s: Primary Low byte termination %sabled\n",
720 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis");
722 printk("%s: Secondary High byte termination %sabled\n",
724 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis");
726 printk("%s: Secondary Low byte termination %sabled\n",
728 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis");
740 static const char *split_status_source[] =
748 static const char *pci_status_source[] =
760 static const char *split_status_strings[] =
762 "%s: Received split response in %s.\n",
763 "%s: Received split completion error message in %s\n",
764 "%s: Receive overrun in %s\n",
765 "%s: Count not complete in %s\n",
766 "%s: Split completion data bucket in %s\n",
767 "%s: Split completion address error in %s\n",
768 "%s: Split completion byte count error in %s\n",
769 "%s: Signaled Target-abort to early terminate a split in %s\n"
772 static const char *pci_status_strings[] =
774 "%s: Data Parity Error has been reported via PERR# in %s\n",
775 "%s: Target initial wait state error in %s\n",
776 "%s: Split completion read data parity error in %s\n",
777 "%s: Split completion address attribute parity error in %s\n",
778 "%s: Received a Target Abort in %s\n",
779 "%s: Received a Master Abort in %s\n",
780 "%s: Signal System Error Detected in %s\n",
781 "%s: Address or Write Phase Parity Error Detected in %s.\n"
785 ahd_pci_intr(struct ahd_softc *ahd)
787 uint8_t pci_status[8];
788 ahd_mode_state saved_modes;
794 intstat = ahd_inb(ahd, INTSTAT);
796 if ((intstat & SPLTINT) != 0)
797 ahd_pci_split_intr(ahd, intstat);
799 if ((intstat & PCIINT) == 0)
802 printk("%s: PCI error Interrupt\n", ahd_name(ahd));
803 saved_modes = ahd_save_modes(ahd);
804 ahd_dump_card_state(ahd);
805 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
806 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
810 pci_status[i] = ahd_inb(ahd, reg);
811 /* Clear latched errors. So our interrupt deasserts. */
812 ahd_outb(ahd, reg, pci_status[i]);
815 for (i = 0; i < 8; i++) {
821 for (bit = 0; bit < 8; bit++) {
823 if ((pci_status[i] & (0x1 << bit)) != 0) {
826 s = pci_status_strings[bit];
827 if (i == 7/*TARG*/ && bit == 3)
828 s = "%s: Signaled Target Abort\n";
829 printk(s, ahd_name(ahd), pci_status_source[i]);
833 pci_status1 = ahd_pci_read_config(ahd->dev_softc,
834 PCIR_STATUS + 1, /*bytes*/1);
835 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
836 pci_status1, /*bytes*/1);
837 ahd_restore_modes(ahd, saved_modes);
838 ahd_outb(ahd, CLRINT, CLRPCIINT);
843 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
845 uint8_t split_status[4];
846 uint8_t split_status1[4];
847 uint8_t sg_split_status[2];
848 uint8_t sg_split_status1[2];
849 ahd_mode_state saved_modes;
851 uint16_t pcix_status;
854 * Check for splits in all modes. Modes 0 and 1
855 * additionally have SG engine splits to look at.
857 pcix_status = ahd_pci_read_config(ahd->dev_softc, PCIXR_STATUS,
859 printk("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
860 ahd_name(ahd), pcix_status);
861 saved_modes = ahd_save_modes(ahd);
862 for (i = 0; i < 4; i++) {
863 ahd_set_modes(ahd, i, i);
865 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0);
866 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1);
867 /* Clear latched errors. So our interrupt deasserts. */
868 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]);
869 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]);
872 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0);
873 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1);
874 /* Clear latched errors. So our interrupt deasserts. */
875 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]);
876 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]);
879 for (i = 0; i < 4; i++) {
882 for (bit = 0; bit < 8; bit++) {
884 if ((split_status[i] & (0x1 << bit)) != 0)
885 printk(split_status_strings[bit], ahd_name(ahd),
886 split_status_source[i]);
891 if ((sg_split_status[i] & (0x1 << bit)) != 0)
892 printk(split_status_strings[bit], ahd_name(ahd), "SG");
896 * Clear PCI-X status bits.
898 ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS,
899 pcix_status, /*bytes*/2);
900 ahd_outb(ahd, CLRINT, CLRSPLTINT);
901 ahd_restore_modes(ahd, saved_modes);
905 ahd_aic7901_setup(struct ahd_softc *ahd)
908 ahd->chip = AHD_AIC7901;
909 ahd->features = AHD_AIC7901_FE;
910 return (ahd_aic790X_setup(ahd));
914 ahd_aic7901A_setup(struct ahd_softc *ahd)
917 ahd->chip = AHD_AIC7901A;
918 ahd->features = AHD_AIC7901A_FE;
919 return (ahd_aic790X_setup(ahd));
923 ahd_aic7902_setup(struct ahd_softc *ahd)
925 ahd->chip = AHD_AIC7902;
926 ahd->features = AHD_AIC7902_FE;
927 return (ahd_aic790X_setup(ahd));
931 ahd_aic790X_setup(struct ahd_softc *ahd)
936 pci = ahd->dev_softc;
937 rev = ahd_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
938 if (rev < ID_AIC7902_PCI_REV_A4) {
939 printk("%s: Unable to attach to unsupported chip revision %d\n",
941 ahd_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2);
944 ahd->channel = ahd_get_pci_function(pci) + 'A';
945 if (rev < ID_AIC7902_PCI_REV_B0) {
947 * Enable A series workarounds.
949 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
950 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
951 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
952 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
953 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
954 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG
955 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG
956 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG
957 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG
958 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG
962 * IO Cell parameter setup.
964 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
966 if ((ahd->flags & AHD_HP_BOARD) == 0)
967 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA);
969 /* This is revision B and newer. */
970 extern uint32_t aic79xx_slowcrc;
973 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS
974 | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY
975 | AHD_BUSFREEREV_BUG;
976 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG;
978 /* If the user requested that the SLOWCRC bit to be set. */
980 ahd->features |= AHD_AIC79XXB_SLOWCRC;
983 * Some issues have been resolved in the 7901B.
985 if ((ahd->features & AHD_MULTI_FUNC) != 0)
986 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG;
989 * IO Cell parameter setup.
991 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
992 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
993 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF);
996 * Set the PREQDIS bit for H2B which disables some workaround
997 * that doesn't work on regular PCI busses.
998 * XXX - Find out exactly what this does from the hardware
1001 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
1002 ahd_pci_write_config(pci, DEVCONFIG1,
1003 devconfig1|PREQDIS, /*bytes*/1);
1004 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);