drivers/scsi/aacraid/aacraid.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  *      Adaptec AAC series RAID controller driver
   4  *      (c) Copyright 2001 Red Hat Inc. <alan@redhat.com>
   5  *
   6  * based on the old aacraid driver that is..
   7  * Adaptec aacraid device driver for Linux.
   8  *
   9  * Copyright (c) 2000-2010 Adaptec, Inc.
  10  *               2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
  11  *               2016-2017 Microsemi Corp. (aacraid@microsemi.com)
  12  *
  13  * Module Name:
  14  *  aacraid.h
  15  *
  16  * Abstract: Contains all routines for control of the aacraid driver
  17  */
  18
  19 #ifndef _AACRAID_H_
  20 #define _AACRAID_H_
  21 #ifndef dprintk
  22 # define dprintk(x)
  23 #endif
  24 /* eg: if (nblank(dprintk(x))) */
  25 #define _nblank(x) #x
  26 #define nblank(x) _nblank(x)[0]
  27
  28 #include <linux/interrupt.h>
  29 #include <linux/completion.h>
  30 #include <linux/pci.h>
  31 #include <scsi/scsi_host.h>
  32
  33 /*------------------------------------------------------------------------------
  34  *              D E F I N E S
  35  *----------------------------------------------------------------------------*/
  36
  37 #define AAC_MAX_MSIX            32      /* vectors */
  38 #define AAC_PCI_MSI_ENABLE      0x8000
  39
  40 enum {
  41         AAC_ENABLE_INTERRUPT    = 0x0,
  42         AAC_DISABLE_INTERRUPT,
  43         AAC_ENABLE_MSIX,
  44         AAC_DISABLE_MSIX,
  45         AAC_CLEAR_AIF_BIT,
  46         AAC_CLEAR_SYNC_BIT,
  47         AAC_ENABLE_INTX
  48 };
  49
  50 #define AAC_INT_MODE_INTX               (1<<0)
  51 #define AAC_INT_MODE_MSI                (1<<1)
  52 #define AAC_INT_MODE_AIF                (1<<2)
  53 #define AAC_INT_MODE_SYNC               (1<<3)
  54 #define AAC_INT_MODE_MSIX               (1<<16)
  55
  56 #define AAC_INT_ENABLE_TYPE1_INTX       0xfffffffb
  57 #define AAC_INT_ENABLE_TYPE1_MSIX       0xfffffffa
  58 #define AAC_INT_DISABLE_ALL             0xffffffff
  59
  60 /* Bit definitions in IOA->Host Interrupt Register */
  61 #define PMC_TRANSITION_TO_OPERATIONAL   (1<<31)
  62 #define PMC_IOARCB_TRANSFER_FAILED      (1<<28)
  63 #define PMC_IOA_UNIT_CHECK              (1<<27)
  64 #define PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE (1<<26)
  65 #define PMC_CRITICAL_IOA_OP_IN_PROGRESS (1<<25)
  66 #define PMC_IOARRIN_LOST                (1<<4)
  67 #define PMC_SYSTEM_BUS_MMIO_ERROR       (1<<3)
  68 #define PMC_IOA_PROCESSOR_IN_ERROR_STATE (1<<2)
  69 #define PMC_HOST_RRQ_VALID              (1<<1)
  70 #define PMC_OPERATIONAL_STATUS          (1<<31)
  71 #define PMC_ALLOW_MSIX_VECTOR0          (1<<0)
  72
  73 #define PMC_IOA_ERROR_INTERRUPTS        (PMC_IOARCB_TRANSFER_FAILED | \
  74                                          PMC_IOA_UNIT_CHECK | \
  75                                          PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE | \
  76                                          PMC_IOARRIN_LOST | \
  77                                          PMC_SYSTEM_BUS_MMIO_ERROR | \
  78                                          PMC_IOA_PROCESSOR_IN_ERROR_STATE)
  79
  80 #define PMC_ALL_INTERRUPT_BITS          (PMC_IOA_ERROR_INTERRUPTS | \
  81                                          PMC_HOST_RRQ_VALID | \
  82                                          PMC_TRANSITION_TO_OPERATIONAL | \
  83                                          PMC_ALLOW_MSIX_VECTOR0)
  84 #define PMC_GLOBAL_INT_BIT2             0x00000004
  85 #define PMC_GLOBAL_INT_BIT0             0x00000001
  86
  87 #ifndef AAC_DRIVER_BUILD
  88 # define AAC_DRIVER_BUILD 50983
  89 # define AAC_DRIVER_BRANCH "-custom"
  90 #endif
  91 #define MAXIMUM_NUM_CONTAINERS  32
  92
  93 #define AAC_NUM_MGT_FIB         8
  94 #define AAC_NUM_IO_FIB          (1024 - AAC_NUM_MGT_FIB)
  95 #define AAC_NUM_FIB             (AAC_NUM_IO_FIB + AAC_NUM_MGT_FIB)
  96
  97 #define AAC_MAX_LUN             256
  98
  99 #define AAC_MAX_HOSTPHYSMEMPAGES (0xfffff)
 100 #define AAC_MAX_32BIT_SGBCOUNT  ((unsigned short)256)
 101
 102 #define AAC_DEBUG_INSTRUMENT_AIF_DELETE
 103
 104 #define AAC_MAX_NATIVE_TARGETS          1024
 105 /* Thor: 5 phys. buses: #0: empty, 1-4: 256 targets each */
 106 #define AAC_MAX_BUSES                   5
 107 #define AAC_MAX_TARGETS         256
 108 #define AAC_BUS_TARGET_LOOP             (AAC_MAX_BUSES * AAC_MAX_TARGETS)
 109 #define AAC_MAX_NATIVE_SIZE             2048
 110 #define FW_ERROR_BUFFER_SIZE            512
 111 #define AAC_SA_TIMEOUT                  180
 112 #define AAC_ARC_TIMEOUT                 60
 113
 114 #define get_bus_number(x)       (x/AAC_MAX_TARGETS)
 115 #define get_target_number(x)    (x%AAC_MAX_TARGETS)
 116
 117 /* Thor AIF events */
 118 #define SA_AIF_HOTPLUG                  (1<<1)
 119 #define SA_AIF_HARDWARE         (1<<2)
 120 #define SA_AIF_PDEV_CHANGE              (1<<4)
 121 #define SA_AIF_LDEV_CHANGE              (1<<5)
 122 #define SA_AIF_BPSTAT_CHANGE            (1<<30)
 123 #define SA_AIF_BPCFG_CHANGE             (1<<31)
 124
 125 #define HBA_MAX_SG_EMBEDDED             28
 126 #define HBA_MAX_SG_SEPARATE             90
 127 #define HBA_SENSE_DATA_LEN_MAX          32
 128 #define HBA_REQUEST_TAG_ERROR_FLAG      0x00000002
 129 #define HBA_SGL_FLAGS_EXT               0x80000000UL
 130
 131 struct aac_hba_sgl {
 132         u32             addr_lo; /* Lower 32-bits of SGL element address */
 133         u32             addr_hi; /* Upper 32-bits of SGL element address */
 134         u32             len;    /* Length of SGL element in bytes */
 135         u32             flags;  /* SGL element flags */
 136 };
 137
 138 enum {
 139         HBA_IU_TYPE_SCSI_CMD_REQ                = 0x40,
 140         HBA_IU_TYPE_SCSI_TM_REQ                 = 0x41,
 141         HBA_IU_TYPE_SATA_REQ                    = 0x42,
 142         HBA_IU_TYPE_RESP                        = 0x60,
 143         HBA_IU_TYPE_COALESCED_RESP              = 0x61,
 144         HBA_IU_TYPE_INT_COALESCING_CFG_REQ      = 0x70
 145 };
 146
 147 enum {
 148         HBA_CMD_BYTE1_DATA_DIR_IN               = 0x1,
 149         HBA_CMD_BYTE1_DATA_DIR_OUT              = 0x2,
 150         HBA_CMD_BYTE1_DATA_TYPE_DDR             = 0x4,
 151         HBA_CMD_BYTE1_CRYPTO_ENABLE             = 0x8
 152 };
 153
 154 enum {
 155         HBA_CMD_BYTE1_BITOFF_DATA_DIR_IN        = 0x0,
 156         HBA_CMD_BYTE1_BITOFF_DATA_DIR_OUT,
 157         HBA_CMD_BYTE1_BITOFF_DATA_TYPE_DDR,
 158         HBA_CMD_BYTE1_BITOFF_CRYPTO_ENABLE
 159 };
 160
 161 enum {
 162         HBA_RESP_DATAPRES_NO_DATA               = 0x0,
 163         HBA_RESP_DATAPRES_RESPONSE_DATA,
 164         HBA_RESP_DATAPRES_SENSE_DATA
 165 };
 166
 167 enum {
 168         HBA_RESP_SVCRES_TASK_COMPLETE           = 0x0,
 169         HBA_RESP_SVCRES_FAILURE,
 170         HBA_RESP_SVCRES_TMF_COMPLETE,
 171         HBA_RESP_SVCRES_TMF_SUCCEEDED,
 172         HBA_RESP_SVCRES_TMF_REJECTED,
 173         HBA_RESP_SVCRES_TMF_LUN_INVALID
 174 };
 175
 176 enum {
 177         HBA_RESP_STAT_IO_ERROR                  = 0x1,
 178         HBA_RESP_STAT_IO_ABORTED,
 179         HBA_RESP_STAT_NO_PATH_TO_DEVICE,
 180         HBA_RESP_STAT_INVALID_DEVICE,
 181         HBA_RESP_STAT_HBAMODE_DISABLED          = 0xE,
 182         HBA_RESP_STAT_UNDERRUN                  = 0x51,
 183         HBA_RESP_STAT_OVERRUN                   = 0x75
 184 };
 185
 186 struct aac_hba_cmd_req {
 187         u8      iu_type;        /* HBA information unit type */
 188         /*
 189          * byte1:
 190          * [1:0] DIR - 0=No data, 0x1 = IN, 0x2 = OUT
 191          * [2]   TYPE - 0=PCI, 1=DDR
 192          * [3]   CRYPTO_ENABLE - 0=Crypto disabled, 1=Crypto enabled
 193          */
 194         u8      byte1;
 195         u8      reply_qid;      /* Host reply queue to post response to */
 196         u8      reserved1;
 197         __le32  it_nexus;       /* Device handle for the request */
 198         __le32  request_id;     /* Sender context */
 199         /* Lower 32-bits of tweak value for crypto enabled IOs */
 200         __le32  tweak_value_lo;
 201         u8      cdb[16];        /* SCSI CDB of the command */
 202         u8      lun[8];         /* SCSI LUN of the command */
 203
 204         /* Total data length in bytes to be read/written (if any) */
 205         __le32  data_length;
 206
 207         /* [2:0] Task Attribute, [6:3] Command Priority */
 208         u8      attr_prio;
 209
 210         /* Number of SGL elements embedded in the HBA req */
 211         u8      emb_data_desc_count;
 212
 213         __le16  dek_index;      /* DEK index for crypto enabled IOs */
 214
 215         /* Lower 32-bits of reserved error data target location on the host */
 216         __le32  error_ptr_lo;
 217
 218         /* Upper 32-bits of reserved error data target location on the host */
 219         __le32  error_ptr_hi;
 220
 221         /* Length of reserved error data area on the host in bytes */
 222         __le32  error_length;
 223
 224         /* Upper 32-bits of tweak value for crypto enabled IOs */
 225         __le32  tweak_value_hi;
 226
 227         struct aac_hba_sgl sge[HBA_MAX_SG_SEPARATE+2]; /* SG list space */
 228
 229         /*
 230          * structure must not exceed
 231          * AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE
 232          */
 233 };
 234
 235 /* Task Management Functions (TMF) */
 236 #define HBA_TMF_ABORT_TASK      0x01
 237 #define HBA_TMF_LUN_RESET       0x08
 238
 239 struct aac_hba_tm_req {
 240         u8      iu_type;        /* HBA information unit type */
 241         u8      reply_qid;      /* Host reply queue to post response to */
 242         u8      tmf;            /* Task management function */
 243         u8      reserved1;
 244
 245         __le32  it_nexus;       /* Device handle for the command */
 246
 247         u8      lun[8];         /* SCSI LUN */
 248
 249         /* Used to hold sender context. */
 250         __le32  request_id;     /* Sender context */
 251         __le32  reserved2;
 252
 253         /* Request identifier of managed task */
 254         __le32  managed_request_id;     /* Sender context being managed */
 255         __le32  reserved3;
 256
 257         /* Lower 32-bits of reserved error data target location on the host */
 258         __le32  error_ptr_lo;
 259         /* Upper 32-bits of reserved error data target location on the host */
 260         __le32  error_ptr_hi;
 261         /* Length of reserved error data area on the host in bytes */
 262         __le32  error_length;
 263 };
 264
 265 struct aac_hba_reset_req {
 266         u8      iu_type;        /* HBA information unit type */
 267         /* 0 - reset specified device, 1 - reset all devices */
 268         u8      reset_type;
 269         u8      reply_qid;      /* Host reply queue to post response to */
 270         u8      reserved1;
 271
 272         __le32  it_nexus;       /* Device handle for the command */
 273         __le32  request_id;     /* Sender context */
 274         /* Lower 32-bits of reserved error data target location on the host */
 275         __le32  error_ptr_lo;
 276         /* Upper 32-bits of reserved error data target location on the host */
 277         __le32  error_ptr_hi;
 278         /* Length of reserved error data area on the host in bytes */
 279         __le32  error_length;
 280 };
 281
 282 struct aac_hba_resp {
 283         u8      iu_type;                /* HBA information unit type */
 284         u8      reserved1[3];
 285         __le32  request_identifier;     /* sender context */
 286         __le32  reserved2;
 287         u8      service_response;       /* SCSI service response */
 288         u8      status;                 /* SCSI status */
 289         u8      datapres;       /* [1:0] - data present, [7:2] - reserved */
 290         u8      sense_response_data_len;        /* Sense/response data length */
 291         __le32  residual_count;         /* Residual data length in bytes */
 292         /* Sense/response data */
 293         u8      sense_response_buf[HBA_SENSE_DATA_LEN_MAX];
 294 };
 295
 296 struct aac_native_hba {
 297         union {
 298                 struct aac_hba_cmd_req cmd;
 299                 struct aac_hba_tm_req tmr;
 300                 u8 cmd_bytes[AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE];
 301         } cmd;
 302         union {
 303                 struct aac_hba_resp err;
 304                 u8 resp_bytes[FW_ERROR_BUFFER_SIZE];
 305         } resp;
 306 };
 307
 308 #define CISS_REPORT_PHYSICAL_LUNS       0xc3
 309 #define WRITE_HOST_WELLNESS             0xa5
 310 #define CISS_IDENTIFY_PHYSICAL_DEVICE   0x15
 311 #define BMIC_IN                 0x26
 312 #define BMIC_OUT                        0x27
 313
 314 struct aac_ciss_phys_luns_resp {
 315         u8      list_length[4];         /* LUN list length (N-7, big endian) */
 316         u8      resp_flag;              /* extended response_flag */
 317         u8      reserved[3];
 318         struct _ciss_lun {
 319                 u8      tid[3];         /* Target ID */
 320                 u8      bus;            /* Bus, flag (bits 6,7) */
 321                 u8      level3[2];
 322                 u8      level2[2];
 323                 u8      node_ident[16]; /* phys. node identifier */
 324         } lun[1];                       /* List of phys. devices */
 325 };
 326
 327 /*
 328  * Interrupts
 329  */
 330 #define AAC_MAX_HRRQ            64
 331
 332 struct aac_ciss_identify_pd {
 333         u8 scsi_bus;                    /* SCSI Bus number on controller */
 334         u8 scsi_id;                     /* SCSI ID on this bus */
 335         u16 block_size;                 /* sector size in bytes */
 336         u32 total_blocks;               /* number for sectors on drive */
 337         u32 reserved_blocks;            /* controller reserved (RIS) */
 338         u8 model[40];                   /* Physical Drive Model */
 339         u8 serial_number[40];           /* Drive Serial Number */
 340         u8 firmware_revision[8];        /* drive firmware revision */
 341         u8 scsi_inquiry_bits;           /* inquiry byte 7 bits */
 342         u8 compaq_drive_stamp;          /* 0 means drive not stamped */
 343         u8 last_failure_reason;
 344
 345         u8  flags;
 346         u8  more_flags;
 347         u8  scsi_lun;                   /* SCSI LUN for phys drive */
 348         u8  yet_more_flags;
 349         u8  even_more_flags;
 350         u32 spi_speed_rules;            /* SPI Speed :Ultra disable diagnose */
 351         u8  phys_connector[2];          /* connector number on controller */
 352         u8  phys_box_on_bus;            /* phys enclosure this drive resides */
 353         u8  phys_bay_in_box;            /* phys drv bay this drive resides */
 354         u32 rpm;                        /* Drive rotational speed in rpm */
 355         u8  device_type;                /* type of drive */
 356         u8  sata_version;               /* only valid when drive_type is SATA */
 357         u64 big_total_block_count;
 358         u64 ris_starting_lba;
 359         u32 ris_size;
 360         u8  wwid[20];
 361         u8  controller_phy_map[32];
 362         u16 phy_count;
 363         u8  phy_connected_dev_type[256];
 364         u8  phy_to_drive_bay_num[256];
 365         u16 phy_to_attached_dev_index[256];
 366         u8  box_index;
 367         u8  spitfire_support;
 368         u16 extra_physical_drive_flags;
 369         u8  negotiated_link_rate[256];
 370         u8  phy_to_phy_map[256];
 371         u8  redundant_path_present_map;
 372         u8  redundant_path_failure_map;
 373         u8  active_path_number;
 374         u16 alternate_paths_phys_connector[8];
 375         u8  alternate_paths_phys_box_on_port[8];
 376         u8  multi_lun_device_lun_count;
 377         u8  minimum_good_fw_revision[8];
 378         u8  unique_inquiry_bytes[20];
 379         u8  current_temperature_degreesC;
 380         u8  temperature_threshold_degreesC;
 381         u8  max_temperature_degreesC;
 382         u8  logical_blocks_per_phys_block_exp;  /* phyblocksize = 512 * 2^exp */
 383         u16 current_queue_depth_limit;
 384         u8  switch_name[10];
 385         u16 switch_port;
 386         u8  alternate_paths_switch_name[40];
 387         u8  alternate_paths_switch_port[8];
 388         u16 power_on_hours;             /* valid only if gas gauge supported */
 389         u16 percent_endurance_used;     /* valid only if gas gauge supported. */
 390         u8  drive_authentication;
 391         u8  smart_carrier_authentication;
 392         u8  smart_carrier_app_fw_version;
 393         u8  smart_carrier_bootloader_fw_version;
 394         u8  SanitizeSecureEraseSupport;
 395         u8  DriveKeyFlags;
 396         u8  encryption_key_name[64];
 397         u32 misc_drive_flags;
 398         u16 dek_index;
 399         u16 drive_encryption_flags;
 400         u8  sanitize_maximum_time[6];
 401         u8  connector_info_mode;
 402         u8  connector_info_number[4];
 403         u8  long_connector_name[64];
 404         u8  device_unique_identifier[16];
 405         u8  padto_2K[17];
 406 } __packed;
 407
 408 /*
 409  * These macros convert from physical channels to virtual channels
 410  */
 411 #define CONTAINER_CHANNEL               (0)
 412 #define NATIVE_CHANNEL                  (1)
 413 #define CONTAINER_TO_CHANNEL(cont)      (CONTAINER_CHANNEL)
 414 #define CONTAINER_TO_ID(cont)           (cont)
 415 #define CONTAINER_TO_LUN(cont)          (0)
 416 #define ENCLOSURE_CHANNEL               (3)
 417
 418 #define PMC_DEVICE_S6   0x28b
 419 #define PMC_DEVICE_S7   0x28c
 420 #define PMC_DEVICE_S8   0x28d
 421
 422 #define aac_phys_to_logical(x)  ((x)+1)
 423 #define aac_logical_to_phys(x)  ((x)?(x)-1:0)
 424
 425 /*
 426  * These macros are for keeping track of
 427  * character device state.
 428  */
 429 #define AAC_CHARDEV_UNREGISTERED        (-1)
 430 #define AAC_CHARDEV_NEEDS_REINIT        (-2)
 431
 432 /* #define AAC_DETAILED_STATUS_INFO */
 433
 434 struct diskparm
 435 {
 436         int heads;
 437         int sectors;
 438         int cylinders;
 439 };
 440
 441
 442 /*
 443  *      Firmware constants
 444  */
 445
 446 #define         CT_NONE                 0
 447 #define         CT_OK                   218
 448 #define         FT_FILESYS      8       /* ADAPTEC's "FSA"(tm) filesystem */
 449 #define         FT_DRIVE        9       /* physical disk - addressable in scsi by bus/id/lun */
 450
 451 /*
 452  *      Host side memory scatter gather list
 453  *      Used by the adapter for read, write, and readdirplus operations
 454  *      We have separate 32 and 64 bit version because even
 455  *      on 64 bit systems not all cards support the 64 bit version
 456  */
 457 struct sgentry {
 458         __le32  addr;   /* 32-bit address. */
 459         __le32  count;  /* Length. */
 460 };
 461
 462 struct user_sgentry {
 463         u32     addr;   /* 32-bit address. */
 464         u32     count;  /* Length. */
 465 };
 466
 467 struct sgentry64 {
 468         __le32  addr[2];        /* 64-bit addr. 2 pieces for data alignment */
 469         __le32  count;  /* Length. */
 470 };
 471
 472 struct user_sgentry64 {
 473         u32     addr[2];        /* 64-bit addr. 2 pieces for data alignment */
 474         u32     count;  /* Length. */
 475 };
 476
 477 struct sgentryraw {
 478         __le32          next;   /* reserved for F/W use */
 479         __le32          prev;   /* reserved for F/W use */
 480         __le32          addr[2];
 481         __le32          count;
 482         __le32          flags;  /* reserved for F/W use */
 483 };
 484
 485 struct user_sgentryraw {
 486         u32             next;   /* reserved for F/W use */
 487         u32             prev;   /* reserved for F/W use */
 488         u32             addr[2];
 489         u32             count;
 490         u32             flags;  /* reserved for F/W use */
 491 };
 492
 493 struct sge_ieee1212 {
 494         u32     addrLow;
 495         u32     addrHigh;
 496         u32     length;
 497         u32     flags;
 498 };
 499
 500 /*
 501  *      SGMAP
 502  *
 503  *      This is the SGMAP structure for all commands that use
 504  *      32-bit addressing.
 505  */
 506
 507 struct sgmap {
 508         __le32          count;
 509         struct sgentry  sg[1];
 510 };
 511
 512 struct user_sgmap {
 513         u32             count;
 514         struct user_sgentry     sg[1];
 515 };
 516
 517 struct sgmap64 {
 518         __le32          count;
 519         struct sgentry64 sg[1];
 520 };
 521
 522 struct user_sgmap64 {
 523         u32             count;
 524         struct user_sgentry64 sg[1];
 525 };
 526
 527 struct sgmapraw {
 528         __le32            count;
 529         struct sgentryraw sg[1];
 530 };
 531
 532 struct user_sgmapraw {
 533         u32               count;
 534         struct user_sgentryraw sg[1];
 535 };
 536
 537 struct creation_info
 538 {
 539         u8              buildnum;               /* e.g., 588 */
 540         u8              usec;                   /* e.g., 588 */
 541         u8              via;                    /* e.g., 1 = FSU,
 542                                                  *       2 = API
 543                                                  */
 544         u8              year;                   /* e.g., 1997 = 97 */
 545         __le32          date;                   /*
 546                                                  * unsigned     Month           :4;     // 1 - 12
 547                                                  * unsigned     Day             :6;     // 1 - 32
 548                                                  * unsigned     Hour            :6;     // 0 - 23
 549                                                  * unsigned     Minute          :6;     // 0 - 60
 550                                                  * unsigned     Second          :6;     // 0 - 60
 551                                                  */
 552         __le32          serial[2];                      /* e.g., 0x1DEADB0BFAFAF001 */
 553 };
 554
 555
 556 /*
 557  *      Define all the constants needed for the communication interface
 558  */
 559
 560 /*
 561  *      Define how many queue entries each queue will have and the total
 562  *      number of entries for the entire communication interface. Also define
 563  *      how many queues we support.
 564  *
 565  *      This has to match the controller
 566  */
 567
 568 #define NUMBER_OF_COMM_QUEUES  8   // 4 command; 4 response
 569 #define HOST_HIGH_CMD_ENTRIES  4
 570 #define HOST_NORM_CMD_ENTRIES  8
 571 #define ADAP_HIGH_CMD_ENTRIES  4
 572 #define ADAP_NORM_CMD_ENTRIES  512
 573 #define HOST_HIGH_RESP_ENTRIES 4
 574 #define HOST_NORM_RESP_ENTRIES 512
 575 #define ADAP_HIGH_RESP_ENTRIES 4
 576 #define ADAP_NORM_RESP_ENTRIES 8
 577
 578 #define TOTAL_QUEUE_ENTRIES  \
 579     (HOST_NORM_CMD_ENTRIES + HOST_HIGH_CMD_ENTRIES + ADAP_NORM_CMD_ENTRIES + ADAP_HIGH_CMD_ENTRIES + \
 580             HOST_NORM_RESP_ENTRIES + HOST_HIGH_RESP_ENTRIES + ADAP_NORM_RESP_ENTRIES + ADAP_HIGH_RESP_ENTRIES)
 581
 582
 583 /*
 584  *      Set the queues on a 16 byte alignment
 585  */
 586
 587 #define QUEUE_ALIGNMENT         16
 588
 589 /*
 590  *      The queue headers define the Communication Region queues. These
 591  *      are physically contiguous and accessible by both the adapter and the
 592  *      host. Even though all queue headers are in the same contiguous block
 593  *      they will be represented as individual units in the data structures.
 594  */
 595
 596 struct aac_entry {
 597         __le32 size; /* Size in bytes of Fib which this QE points to */
 598         __le32 addr; /* Receiver address of the FIB */
 599 };
 600
 601 /*
 602  *      The adapter assumes the ProducerIndex and ConsumerIndex are grouped
 603  *      adjacently and in that order.
 604  */
 605
 606 struct aac_qhdr {
 607         __le64 header_addr;/* Address to hand the adapter to access
 608                               to this queue head */
 609         __le32 *producer; /* The producer index for this queue (host address) */
 610         __le32 *consumer; /* The consumer index for this queue (host address) */
 611 };
 612
 613 /*
 614  *      Define all the events which the adapter would like to notify
 615  *      the host of.
 616  */
 617
 618 #define         HostNormCmdQue          1       /* Change in host normal priority command queue */
 619 #define         HostHighCmdQue          2       /* Change in host high priority command queue */
 620 #define         HostNormRespQue         3       /* Change in host normal priority response queue */
 621 #define         HostHighRespQue         4       /* Change in host high priority response queue */
 622 #define         AdapNormRespNotFull     5
 623 #define         AdapHighRespNotFull     6
 624 #define         AdapNormCmdNotFull      7
 625 #define         AdapHighCmdNotFull      8
 626 #define         SynchCommandComplete    9
 627 #define         AdapInternalError       0xfe    /* The adapter detected an internal error shutting down */
 628
 629 /*
 630  *      Define all the events the host wishes to notify the
 631  *      adapter of. The first four values much match the Qid the
 632  *      corresponding queue.
 633  */
 634
 635 #define         AdapNormCmdQue          2
 636 #define         AdapHighCmdQue          3
 637 #define         AdapNormRespQue         6
 638 #define         AdapHighRespQue         7
 639 #define         HostShutdown            8
 640 #define         HostPowerFail           9
 641 #define         FatalCommError          10
 642 #define         HostNormRespNotFull     11
 643 #define         HostHighRespNotFull     12
 644 #define         HostNormCmdNotFull      13
 645 #define         HostHighCmdNotFull      14
 646 #define         FastIo                  15
 647 #define         AdapPrintfDone          16
 648
 649 /*
 650  *      Define all the queues that the adapter and host use to communicate
 651  *      Number them to match the physical queue layout.
 652  */
 653
 654 enum aac_queue_types {
 655         HostNormCmdQueue = 0,   /* Adapter to host normal priority command traffic */
 656         HostHighCmdQueue,       /* Adapter to host high priority command traffic */
 657         AdapNormCmdQueue,       /* Host to adapter normal priority command traffic */
 658         AdapHighCmdQueue,       /* Host to adapter high priority command traffic */
 659         HostNormRespQueue,      /* Adapter to host normal priority response traffic */
 660         HostHighRespQueue,      /* Adapter to host high priority response traffic */
 661         AdapNormRespQueue,      /* Host to adapter normal priority response traffic */
 662         AdapHighRespQueue       /* Host to adapter high priority response traffic */
 663 };
 664
 665 /*
 666  *      Assign type values to the FSA communication data structures
 667  */
 668
 669 #define         FIB_MAGIC       0x0001
 670 #define         FIB_MAGIC2      0x0004
 671 #define         FIB_MAGIC2_64   0x0005
 672
 673 /*
 674  *      Define the priority levels the FSA communication routines support.
 675  */
 676
 677 #define         FsaNormal       1
 678
 679 /* transport FIB header (PMC) */
 680 struct aac_fib_xporthdr {
 681         __le64  HostAddress;    /* FIB host address w/o xport header */
 682         __le32  Size;           /* FIB size excluding xport header */
 683         __le32  Handle;         /* driver handle to reference the FIB */
 684         __le64  Reserved[2];
 685 };
 686
 687 #define         ALIGN32         32
 688
 689 /*
 690  * Define the FIB. The FIB is the where all the requested data and
 691  * command information are put to the application on the FSA adapter.
 692  */
 693
 694 struct aac_fibhdr {
 695         __le32 XferState;       /* Current transfer state for this CCB */
 696         __le16 Command;         /* Routing information for the destination */
 697         u8 StructType;          /* Type FIB */
 698         u8 Unused;              /* Unused */
 699         __le16 Size;            /* Size of this FIB in bytes */
 700         __le16 SenderSize;      /* Size of the FIB in the sender
 701                                    (for response sizing) */
 702         __le32 SenderFibAddress;  /* Host defined data in the FIB */
 703         union {
 704                 __le32 ReceiverFibAddress;/* Logical address of this FIB for
 705                                      the adapter (old) */
 706                 __le32 SenderFibAddressHigh;/* upper 32bit of phys. FIB address */
 707                 __le32 TimeStamp;       /* otherwise timestamp for FW internal use */
 708         } u;
 709         __le32 Handle;          /* FIB handle used for MSGU commnunication */
 710         u32 Previous;           /* FW internal use */
 711         u32 Next;               /* FW internal use */
 712 };
 713
 714 struct hw_fib {
 715         struct aac_fibhdr header;
 716         u8 data[512-sizeof(struct aac_fibhdr)]; // Command specific data
 717 };
 718
 719 /*
 720  *      FIB commands
 721  */
 722
 723 #define         TestCommandResponse             1
 724 #define         TestAdapterCommand              2
 725 /*
 726  *      Lowlevel and comm commands
 727  */
 728 #define         LastTestCommand                 100
 729 #define         ReinitHostNormCommandQueue      101
 730 #define         ReinitHostHighCommandQueue      102
 731 #define         ReinitHostHighRespQueue         103
 732 #define         ReinitHostNormRespQueue         104
 733 #define         ReinitAdapNormCommandQueue      105
 734 #define         ReinitAdapHighCommandQueue      107
 735 #define         ReinitAdapHighRespQueue         108
 736 #define         ReinitAdapNormRespQueue         109
 737 #define         InterfaceShutdown               110
 738 #define         DmaCommandFib                   120
 739 #define         StartProfile                    121
 740 #define         TermProfile                     122
 741 #define         SpeedTest                       123
 742 #define         TakeABreakPt                    124
 743 #define         RequestPerfData                 125
 744 #define         SetInterruptDefTimer            126
 745 #define         SetInterruptDefCount            127
 746 #define         GetInterruptDefStatus           128
 747 #define         LastCommCommand                 129
 748 /*
 749  *      Filesystem commands
 750  */
 751 #define         NuFileSystem                    300
 752 #define         UFS                             301
 753 #define         HostFileSystem                  302
 754 #define         LastFileSystemCommand           303
 755 /*
 756  *      Container Commands
 757  */
 758 #define         ContainerCommand                500
 759 #define         ContainerCommand64              501
 760 #define         ContainerRawIo                  502
 761 #define         ContainerRawIo2                 503
 762 /*
 763  *      Scsi Port commands (scsi passthrough)
 764  */
 765 #define         ScsiPortCommand                 600
 766 #define         ScsiPortCommand64               601
 767 /*
 768  *      Misc house keeping and generic adapter initiated commands
 769  */
 770 #define         AifRequest                      700
 771 #define         CheckRevision                   701
 772 #define         FsaHostShutdown                 702
 773 #define         RequestAdapterInfo              703
 774 #define         IsAdapterPaused                 704
 775 #define         SendHostTime                    705
 776 #define         RequestSupplementAdapterInfo    706
 777 #define         LastMiscCommand                 707
 778
 779 /*
 780  * Commands that will target the failover level on the FSA adapter
 781  */
 782
 783 enum fib_xfer_state {
 784         HostOwned                       = (1<<0),
 785         AdapterOwned                    = (1<<1),
 786         FibInitialized                  = (1<<2),
 787         FibEmpty                        = (1<<3),
 788         AllocatedFromPool               = (1<<4),
 789         SentFromHost                    = (1<<5),
 790         SentFromAdapter                 = (1<<6),
 791         ResponseExpected                = (1<<7),
 792         NoResponseExpected              = (1<<8),
 793         AdapterProcessed                = (1<<9),
 794         HostProcessed                   = (1<<10),
 795         HighPriority                    = (1<<11),
 796         NormalPriority                  = (1<<12),
 797         Async                           = (1<<13),
 798         AsyncIo                         = (1<<13),      // rpbfix: remove with new regime
 799         PageFileIo                      = (1<<14),      // rpbfix: remove with new regime
 800         ShutdownRequest                 = (1<<15),
 801         LazyWrite                       = (1<<16),      // rpbfix: remove with new regime
 802         AdapterMicroFib                 = (1<<17),
 803         BIOSFibPath                     = (1<<18),
 804         FastResponseCapable             = (1<<19),
 805         ApiFib                          = (1<<20),      /* Its an API Fib */
 806         /* PMC NEW COMM: There is no more AIF data pending */
 807         NoMoreAifDataAvailable          = (1<<21)
 808 };
 809
 810 /*
 811  *      The following defines needs to be updated any time there is an
 812  *      incompatible change made to the aac_init structure.
 813  */
 814
 815 #define ADAPTER_INIT_STRUCT_REVISION            3
 816 #define ADAPTER_INIT_STRUCT_REVISION_4          4 // rocket science
 817 #define ADAPTER_INIT_STRUCT_REVISION_6          6 /* PMC src */
 818 #define ADAPTER_INIT_STRUCT_REVISION_7          7 /* Denali */
 819 #define ADAPTER_INIT_STRUCT_REVISION_8          8 // Thor
 820
 821 union aac_init
 822 {
 823         struct _r7 {
 824                 __le32  init_struct_revision;
 825                 __le32  no_of_msix_vectors;
 826                 __le32  fsrev;
 827                 __le32  comm_header_address;
 828                 __le32  fast_io_comm_area_address;
 829                 __le32  adapter_fibs_physical_address;
 830                 __le32  adapter_fibs_virtual_address;
 831                 __le32  adapter_fibs_size;
 832                 __le32  adapter_fib_align;
 833                 __le32  printfbuf;
 834                 __le32  printfbufsiz;
 835                 /* number of 4k pages of host phys. mem. */
 836                 __le32  host_phys_mem_pages;
 837                 /* number of seconds since 1970. */
 838                 __le32  host_elapsed_seconds;
 839                 /* ADAPTER_INIT_STRUCT_REVISION_4 begins here */
 840                 __le32  init_flags;     /* flags for supported features */
 841 #define INITFLAGS_NEW_COMM_SUPPORTED    0x00000001
 842 #define INITFLAGS_DRIVER_USES_UTC_TIME  0x00000010
 843 #define INITFLAGS_DRIVER_SUPPORTS_PM    0x00000020
 844 #define INITFLAGS_NEW_COMM_TYPE1_SUPPORTED      0x00000040
 845 #define INITFLAGS_FAST_JBOD_SUPPORTED   0x00000080
 846 #define INITFLAGS_NEW_COMM_TYPE2_SUPPORTED      0x00000100
 847 #define INITFLAGS_DRIVER_SUPPORTS_HBA_MODE  0x00000400
 848                 __le32  max_io_commands;        /* max outstanding commands */
 849                 __le32  max_io_size;    /* largest I/O command */
 850                 __le32  max_fib_size;   /* largest FIB to adapter */
 851                 /* ADAPTER_INIT_STRUCT_REVISION_5 begins here */
 852                 __le32  max_num_aif;    /* max number of aif */
 853                 /* ADAPTER_INIT_STRUCT_REVISION_6 begins here */
 854                 /* Host RRQ (response queue) for SRC */
 855                 __le32  host_rrq_addr_low;
 856                 __le32  host_rrq_addr_high;
 857         } r7;
 858         struct _r8 {
 859                 /* ADAPTER_INIT_STRUCT_REVISION_8 */
 860                 __le32  init_struct_revision;
 861                 __le32  rr_queue_count;
 862                 __le32  host_elapsed_seconds; /* number of secs since 1970. */
 863                 __le32  init_flags;
 864                 __le32  max_io_size;    /* largest I/O command */
 865                 __le32  max_num_aif;    /* max number of aif */
 866                 __le32  reserved1;
 867                 __le32  reserved2;
 868                 struct _rrq {
 869                         __le32  host_addr_low;
 870                         __le32  host_addr_high;
 871                         __le16  msix_id;
 872                         __le16  element_count;
 873                         __le16  comp_thresh;
 874                         __le16  unused;
 875                 } rrq[1];               /* up to 64 RRQ addresses */
 876         } r8;
 877 };
 878
 879 enum aac_log_level {
 880         LOG_AAC_INIT                    = 10,
 881         LOG_AAC_INFORMATIONAL           = 20,
 882         LOG_AAC_WARNING                 = 30,
 883         LOG_AAC_LOW_ERROR               = 40,
 884         LOG_AAC_MEDIUM_ERROR            = 50,
 885         LOG_AAC_HIGH_ERROR              = 60,
 886         LOG_AAC_PANIC                   = 70,
 887         LOG_AAC_DEBUG                   = 80,
 888         LOG_AAC_WINDBG_PRINT            = 90
 889 };
 890
 891 #define FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT       0x030b
 892 #define FSAFS_NTC_FIB_CONTEXT                   0x030c
 893
 894 struct aac_dev;
 895 struct fib;
 896 struct scsi_cmnd;
 897
 898 struct adapter_ops
 899 {
 900         /* Low level operations */
 901         void (*adapter_interrupt)(struct aac_dev *dev);
 902         void (*adapter_notify)(struct aac_dev *dev, u32 event);
 903         void (*adapter_disable_int)(struct aac_dev *dev);
 904         void (*adapter_enable_int)(struct aac_dev *dev);
 905         int  (*adapter_sync_cmd)(struct aac_dev *dev, u32 command, u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, u32 *status, u32 *r1, u32 *r2, u32 *r3, u32 *r4);
 906         int  (*adapter_check_health)(struct aac_dev *dev);
 907         int  (*adapter_restart)(struct aac_dev *dev, int bled, u8 reset_type);
 908         void (*adapter_start)(struct aac_dev *dev);
 909         /* Transport operations */
 910         int  (*adapter_ioremap)(struct aac_dev * dev, u32 size);
 911         irq_handler_t adapter_intr;
 912         /* Packet operations */
 913         int  (*adapter_deliver)(struct fib * fib);
 914         int  (*adapter_bounds)(struct aac_dev * dev, struct scsi_cmnd * cmd, u64 lba);
 915         int  (*adapter_read)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count);
 916         int  (*adapter_write)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count, int fua);
 917         int  (*adapter_scsi)(struct fib * fib, struct scsi_cmnd * cmd);
 918         /* Administrative operations */
 919         int  (*adapter_comm)(struct aac_dev * dev, int comm);
 920 };
 921
 922 /*
 923  *      Define which interrupt handler needs to be installed
 924  */
 925
 926 struct aac_driver_ident
 927 {
 928         int     (*init)(struct aac_dev *dev);
 929         char *  name;
 930         char *  vname;
 931         char *  model;
 932         u16     channels;
 933         int     quirks;
 934 };
 935 /*
 936  * Some adapter firmware needs communication memory
 937  * below 2gig. This tells the init function to set the
 938  * dma mask such that fib memory will be allocated where the
 939  * adapter firmware can get to it.
 940  */
 941 #define AAC_QUIRK_31BIT 0x0001
 942
 943 /*
 944  * Some adapter firmware, when the raid card's cache is turned off, can not
 945  * split up scatter gathers in order to deal with the limits of the
 946  * underlying CHIM. This limit is 34 scatter gather elements.
 947  */
 948 #define AAC_QUIRK_34SG  0x0002
 949
 950 /*
 951  * This adapter is a slave (no Firmware)
 952  */
 953 #define AAC_QUIRK_SLAVE 0x0004
 954
 955 /*
 956  * This adapter is a master.
 957  */
 958 #define AAC_QUIRK_MASTER 0x0008
 959
 960 /*
 961  * Some adapter firmware perform poorly when it must split up scatter gathers
 962  * in order to deal with the limits of the underlying CHIM. This limit in this
 963  * class of adapters is 17 scatter gather elements.
 964  */
 965 #define AAC_QUIRK_17SG  0x0010
 966
 967 /*
 968  *      Some adapter firmware does not support 64 bit scsi passthrough
 969  * commands.
 970  */
 971 #define AAC_QUIRK_SCSI_32       0x0020
 972
 973 /*
 974  * SRC based adapters support the AifReqEvent functions
 975  */
 976 #define AAC_QUIRK_SRC 0x0040
 977
 978 /*
 979  *      The adapter interface specs all queues to be located in the same
 980  *      physically contiguous block. The host structure that defines the
 981  *      commuication queues will assume they are each a separate physically
 982  *      contiguous memory region that will support them all being one big
 983  *      contiguous block.
 984  *      There is a command and response queue for each level and direction of
 985  *      commuication. These regions are accessed by both the host and adapter.
 986  */
 987
 988 struct aac_queue {
 989         u64                     logical;        /*address we give the adapter */
 990         struct aac_entry        *base;          /*system virtual address */
 991         struct aac_qhdr         headers;        /*producer,consumer q headers*/
 992         u32                     entries;        /*Number of queue entries */
 993         wait_queue_head_t       qfull;          /*Event to wait on if q full */
 994         wait_queue_head_t       cmdready;       /*Cmd ready from the adapter */
 995                 /* This is only valid for adapter to host command queues. */
 996         spinlock_t              *lock;          /* Spinlock for this queue must take this lock before accessing the lock */
 997         spinlock_t              lockdata;       /* Actual lock (used only on one side of the lock) */
 998         struct list_head        cmdq;           /* A queue of FIBs which need to be prcessed by the FS thread. This is */
 999                                                 /* only valid for command queues which receive entries from the adapter. */
1000         /* Number of entries on outstanding queue. */
1001         atomic_t                numpending;
1002         struct aac_dev *        dev;            /* Back pointer to adapter structure */
1003 };
1004
1005 /*
1006  *      Message queues. The order here is important, see also the
1007  *      queue type ordering
1008  */
1009
1010 struct aac_queue_block
1011 {
1012         struct aac_queue queue[8];
1013 };
1014
1015 /*
1016  *      SaP1 Message Unit Registers
1017  */
1018
1019 struct sa_drawbridge_CSR {
1020                                 /*      Offset  |  Name */
1021         __le32  reserved[10];   /*      00h-27h |  Reserved */
1022         u8      LUT_Offset;     /*      28h     |  Lookup Table Offset */
1023         u8      reserved1[3];   /*      29h-2bh |  Reserved */
1024         __le32  LUT_Data;       /*      2ch     |  Looup Table Data */
1025         __le32  reserved2[26];  /*      30h-97h |  Reserved */
1026         __le16  PRICLEARIRQ;    /*      98h     |  Primary Clear Irq */
1027         __le16  SECCLEARIRQ;    /*      9ah     |  Secondary Clear Irq */
1028         __le16  PRISETIRQ;      /*      9ch     |  Primary Set Irq */
1029         __le16  SECSETIRQ;      /*      9eh     |  Secondary Set Irq */
1030         __le16  PRICLEARIRQMASK;/*      a0h     |  Primary Clear Irq Mask */
1031         __le16  SECCLEARIRQMASK;/*      a2h     |  Secondary Clear Irq Mask */
1032         __le16  PRISETIRQMASK;  /*      a4h     |  Primary Set Irq Mask */
1033         __le16  SECSETIRQMASK;  /*      a6h     |  Secondary Set Irq Mask */
1034         __le32  MAILBOX0;       /*      a8h     |  Scratchpad 0 */
1035         __le32  MAILBOX1;       /*      ach     |  Scratchpad 1 */
1036         __le32  MAILBOX2;       /*      b0h     |  Scratchpad 2 */
1037         __le32  MAILBOX3;       /*      b4h     |  Scratchpad 3 */
1038         __le32  MAILBOX4;       /*      b8h     |  Scratchpad 4 */
1039         __le32  MAILBOX5;       /*      bch     |  Scratchpad 5 */
1040         __le32  MAILBOX6;       /*      c0h     |  Scratchpad 6 */
1041         __le32  MAILBOX7;       /*      c4h     |  Scratchpad 7 */
1042         __le32  ROM_Setup_Data; /*      c8h     |  Rom Setup and Data */
1043         __le32  ROM_Control_Addr;/*     cch     |  Rom Control and Address */
1044         __le32  reserved3[12];  /*      d0h-ffh |  reserved */
1045         __le32  LUT[64];        /*    100h-1ffh |  Lookup Table Entries */
1046 };
1047
1048 #define Mailbox0        SaDbCSR.MAILBOX0
1049 #define Mailbox1        SaDbCSR.MAILBOX1
1050 #define Mailbox2        SaDbCSR.MAILBOX2
1051 #define Mailbox3        SaDbCSR.MAILBOX3
1052 #define Mailbox4        SaDbCSR.MAILBOX4
1053 #define Mailbox5        SaDbCSR.MAILBOX5
1054 #define Mailbox6        SaDbCSR.MAILBOX6
1055 #define Mailbox7        SaDbCSR.MAILBOX7
1056
1057 #define DoorbellReg_p SaDbCSR.PRISETIRQ
1058 #define DoorbellReg_s SaDbCSR.SECSETIRQ
1059 #define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ
1060
1061
1062 #define DOORBELL_0      0x0001
1063 #define DOORBELL_1      0x0002
1064 #define DOORBELL_2      0x0004
1065 #define DOORBELL_3      0x0008
1066 #define DOORBELL_4      0x0010
1067 #define DOORBELL_5      0x0020
1068 #define DOORBELL_6      0x0040
1069
1070
1071 #define PrintfReady     DOORBELL_5
1072 #define PrintfDone      DOORBELL_5
1073
1074 struct sa_registers {
1075         struct sa_drawbridge_CSR        SaDbCSR;                        /* 98h - c4h */
1076 };
1077
1078
1079 #define SA_INIT_NUM_MSIXVECTORS         1
1080 #define SA_MINIPORT_REVISION            SA_INIT_NUM_MSIXVECTORS
1081
1082 #define sa_readw(AEP, CSR)              readl(&((AEP)->regs.sa->CSR))
1083 #define sa_readl(AEP, CSR)              readl(&((AEP)->regs.sa->CSR))
1084 #define sa_writew(AEP, CSR, value)      writew(value, &((AEP)->regs.sa->CSR))
1085 #define sa_writel(AEP, CSR, value)      writel(value, &((AEP)->regs.sa->CSR))
1086
1087 /*
1088  *      Rx Message Unit Registers
1089  */
1090
1091 struct rx_mu_registers {
1092                             /*  Local  | PCI*| Name */
1093         __le32  ARSR;       /*  1300h  | 00h | APIC Register Select Register */
1094         __le32  reserved0;  /*  1304h  | 04h | Reserved */
1095         __le32  AWR;        /*  1308h  | 08h | APIC Window Register */
1096         __le32  reserved1;  /*  130Ch  | 0Ch | Reserved */
1097         __le32  IMRx[2];    /*  1310h  | 10h | Inbound Message Registers */
1098         __le32  OMRx[2];    /*  1318h  | 18h | Outbound Message Registers */
1099         __le32  IDR;        /*  1320h  | 20h | Inbound Doorbell Register */
1100         __le32  IISR;       /*  1324h  | 24h | Inbound Interrupt
1101                                                 Status Register */
1102         __le32  IIMR;       /*  1328h  | 28h | Inbound Interrupt
1103                                                 Mask Register */
1104         __le32  ODR;        /*  132Ch  | 2Ch | Outbound Doorbell Register */
1105         __le32  OISR;       /*  1330h  | 30h | Outbound Interrupt
1106                                                 Status Register */
1107         __le32  OIMR;       /*  1334h  | 34h | Outbound Interrupt
1108                                                 Mask Register */
1109         __le32  reserved2;  /*  1338h  | 38h | Reserved */
1110         __le32  reserved3;  /*  133Ch  | 3Ch | Reserved */
1111         __le32  InboundQueue;/* 1340h  | 40h | Inbound Queue Port relative to firmware */
1112         __le32  OutboundQueue;/*1344h  | 44h | Outbound Queue Port relative to firmware */
1113                             /* * Must access through ATU Inbound
1114                                  Translation Window */
1115 };
1116
1117 struct rx_inbound {
1118         __le32  Mailbox[8];
1119 };
1120
1121 #define INBOUNDDOORBELL_0       0x00000001
1122 #define INBOUNDDOORBELL_1       0x00000002
1123 #define INBOUNDDOORBELL_2       0x00000004
1124 #define INBOUNDDOORBELL_3       0x00000008
1125 #define INBOUNDDOORBELL_4       0x00000010
1126 #define INBOUNDDOORBELL_5       0x00000020
1127 #define INBOUNDDOORBELL_6       0x00000040
1128
1129 #define OUTBOUNDDOORBELL_0      0x00000001
1130 #define OUTBOUNDDOORBELL_1      0x00000002
1131 #define OUTBOUNDDOORBELL_2      0x00000004
1132 #define OUTBOUNDDOORBELL_3      0x00000008
1133 #define OUTBOUNDDOORBELL_4      0x00000010
1134
1135 #define InboundDoorbellReg      MUnit.IDR
1136 #define OutboundDoorbellReg     MUnit.ODR
1137
1138 struct rx_registers {
1139         struct rx_mu_registers          MUnit;          /* 1300h - 1347h */
1140         __le32                          reserved1[2];   /* 1348h - 134ch */
1141         struct rx_inbound               IndexRegs;
1142 };
1143
1144 #define rx_readb(AEP, CSR)              readb(&((AEP)->regs.rx->CSR))
1145 #define rx_readl(AEP, CSR)              readl(&((AEP)->regs.rx->CSR))
1146 #define rx_writeb(AEP, CSR, value)      writeb(value, &((AEP)->regs.rx->CSR))
1147 #define rx_writel(AEP, CSR, value)      writel(value, &((AEP)->regs.rx->CSR))
1148
1149 /*
1150  *      Rkt Message Unit Registers (same as Rx, except a larger reserve region)
1151  */
1152
1153 #define rkt_mu_registers rx_mu_registers
1154 #define rkt_inbound rx_inbound
1155
1156 struct rkt_registers {
1157         struct rkt_mu_registers         MUnit;           /* 1300h - 1347h */
1158         __le32                          reserved1[1006]; /* 1348h - 22fch */
1159         struct rkt_inbound              IndexRegs;       /* 2300h - */
1160 };
1161
1162 #define rkt_readb(AEP, CSR)             readb(&((AEP)->regs.rkt->CSR))
1163 #define rkt_readl(AEP, CSR)             readl(&((AEP)->regs.rkt->CSR))
1164 #define rkt_writeb(AEP, CSR, value)     writeb(value, &((AEP)->regs.rkt->CSR))
1165 #define rkt_writel(AEP, CSR, value)     writel(value, &((AEP)->regs.rkt->CSR))
1166
1167 /*
1168  * PMC SRC message unit registers
1169  */
1170
1171 #define src_inbound rx_inbound
1172
1173 struct src_mu_registers {
1174                                 /*  PCI*| Name */
1175         __le32  reserved0[6];   /*  00h | Reserved */
1176         __le32  IOAR[2];        /*  18h | IOA->host interrupt register */
1177         __le32  IDR;            /*  20h | Inbound Doorbell Register */
1178         __le32  IISR;           /*  24h | Inbound Int. Status Register */
1179         __le32  reserved1[3];   /*  28h | Reserved */
1180         __le32  OIMR;           /*  34h | Outbound Int. Mask Register */
1181         __le32  reserved2[25];  /*  38h | Reserved */
1182         __le32  ODR_R;          /*  9ch | Outbound Doorbell Read */
1183         __le32  ODR_C;          /*  a0h | Outbound Doorbell Clear */
1184         __le32  reserved3[3];   /*  a4h | Reserved */
1185         __le32  SCR0;           /*  b0h | Scratchpad 0 */
1186         __le32  reserved4[2];   /*  b4h | Reserved */
1187         __le32  OMR;            /*  bch | Outbound Message Register */
1188         __le32  IQ_L;           /*  c0h | Inbound Queue (Low address) */
1189         __le32  IQ_H;           /*  c4h | Inbound Queue (High address) */
1190         __le32  ODR_MSI;        /*  c8h | MSI register for sync./AIF */
1191         __le32  reserved5;      /*  cch | Reserved */
1192         __le32  IQN_L;          /*  d0h | Inbound (native cmd) low  */
1193         __le32  IQN_H;          /*  d4h | Inbound (native cmd) high */
1194 };
1195
1196 struct src_registers {
1197         struct src_mu_registers MUnit;  /* 00h - cbh */
1198         union {
1199                 struct {
1200                         __le32 reserved1[130786];       /* d8h - 7fc5fh */
1201                         struct src_inbound IndexRegs;   /* 7fc60h */
1202                 } tupelo;
1203                 struct {
1204                         __le32 reserved1[970];          /* d8h - fffh */
1205                         struct src_inbound IndexRegs;   /* 1000h */
1206                 } denali;
1207         } u;
1208 };
1209
1210 #define src_readb(AEP, CSR)             readb(&((AEP)->regs.src.bar0->CSR))
1211 #define src_readl(AEP, CSR)             readl(&((AEP)->regs.src.bar0->CSR))
1212 #define src_writeb(AEP, CSR, value)     writeb(value, \
1213                                                 &((AEP)->regs.src.bar0->CSR))
1214 #define src_writel(AEP, CSR, value)     writel(value, \
1215                                                 &((AEP)->regs.src.bar0->CSR))
1216 #if defined(writeq)
1217 #define src_writeq(AEP, CSR, value)     writeq(value, \
1218                                                 &((AEP)->regs.src.bar0->CSR))
1219 #endif
1220
1221 #define SRC_ODR_SHIFT           12
1222 #define SRC_IDR_SHIFT           9
1223 #define SRC_MSI_READ_MASK       0x1000
1224
1225 typedef void (*fib_callback)(void *ctxt, struct fib *fibctx);
1226
1227 struct aac_fib_context {
1228         s16                     type;           // used for verification of structure
1229         s16                     size;
1230         u32                     unique;         // unique value representing this context
1231         ulong                   jiffies;        // used for cleanup - dmb changed to ulong
1232         struct list_head        next;           // used to link context's into a linked list
1233         struct completion       completion;     // this is used to wait for the next fib to arrive.
1234         int                     wait;           // Set to true when thread is in WaitForSingleObject
1235         unsigned long           count;          // total number of FIBs on FibList
1236         struct list_head        fib_list;       // this holds fibs and their attachd hw_fibs
1237 };
1238
1239 struct sense_data {
1240         u8 error_code;          /* 70h (current errors), 71h(deferred errors) */
1241         u8 valid:1;             /* A valid bit of one indicates that the information  */
1242                                 /* field contains valid information as defined in the
1243                                  * SCSI-2 Standard.
1244                                  */
1245         u8 segment_number;      /* Only used for COPY, COMPARE, or COPY AND VERIFY Commands */
1246         u8 sense_key:4;         /* Sense Key */
1247         u8 reserved:1;
1248         u8 ILI:1;               /* Incorrect Length Indicator */
1249         u8 EOM:1;               /* End Of Medium - reserved for random access devices */
1250         u8 filemark:1;          /* Filemark - reserved for random access devices */
1251
1252         u8 information[4];      /* for direct-access devices, contains the unsigned
1253                                  * logical block address or residue associated with
1254                                  * the sense key
1255                                  */
1256         u8 add_sense_len;       /* number of additional sense bytes to follow this field */
1257         u8 cmnd_info[4];        /* not used */
1258         u8 ASC;                 /* Additional Sense Code */
1259         u8 ASCQ;                /* Additional Sense Code Qualifier */
1260         u8 FRUC;                /* Field Replaceable Unit Code - not used */
1261         u8 bit_ptr:3;           /* indicates which byte of the CDB or parameter data
1262                                  * was in error
1263                                  */
1264         u8 BPV:1;               /* bit pointer valid (BPV): 1- indicates that
1265                                  * the bit_ptr field has valid value
1266                                  */
1267         u8 reserved2:2;
1268         u8 CD:1;                /* command data bit: 1- illegal parameter in CDB.
1269                                  * 0- illegal parameter in data.
1270                                  */
1271         u8 SKSV:1;
1272         u8 field_ptr[2];        /* byte of the CDB or parameter data in error */
1273 };
1274
1275 struct fsa_dev_info {
1276         u64             last;
1277         u64             size;
1278         u32             type;
1279         u32             config_waiting_on;
1280         unsigned long   config_waiting_stamp;
1281         u16             queue_depth;
1282         u8              config_needed;
1283         u8              valid;
1284         u8              ro;
1285         u8              locked;
1286         u8              deleted;
1287         char            devname[8];
1288         struct sense_data sense_data;
1289         u32             block_size;
1290         u8              identifier[16];
1291 };
1292
1293 struct fib {
1294         void                    *next;  /* this is used by the allocator */
1295         s16                     type;
1296         s16                     size;
1297         /*
1298          *      The Adapter that this I/O is destined for.
1299          */
1300         struct aac_dev          *dev;
1301         /*
1302          *      This is the event the sendfib routine will wait on if the
1303          *      caller did not pass one and this is synch io.
1304          */
1305         struct completion       event_wait;
1306         spinlock_t              event_lock;
1307
1308         u32                     done;   /* gets set to 1 when fib is complete */
1309         fib_callback            callback;
1310         void                    *callback_data;
1311         u32                     flags; // u32 dmb was ulong
1312         /*
1313          *      And for the internal issue/reply queues (we may be able
1314          *      to merge these two)
1315          */
1316         struct list_head        fiblink;
1317         void                    *data;
1318         u32                     vector_no;
1319         struct hw_fib           *hw_fib_va;     /* also used for native */
1320         dma_addr_t              hw_fib_pa;      /* physical address of hw_fib*/
1321         dma_addr_t              hw_sgl_pa;      /* extra sgl for native */
1322         dma_addr_t              hw_error_pa;    /* error buffer for native */
1323         u32                     hbacmd_size;    /* cmd size for native */
1324 };
1325
1326 #define AAC_INIT                        0
1327 #define AAC_RESCAN                      1
1328
1329 #define AAC_DEVTYPE_RAID_MEMBER 1
1330 #define AAC_DEVTYPE_ARC_RAW             2
1331 #define AAC_DEVTYPE_NATIVE_RAW          3
1332
1333 #define AAC_RESCAN_DELAY                (10 * HZ)
1334
1335 struct aac_hba_map_info {
1336         __le32  rmw_nexus;              /* nexus for native HBA devices */
1337         u8              devtype;        /* device type */
1338         s8              reset_state;    /* 0 - no reset, 1..x - */
1339                                         /* after xth TM LUN reset */
1340         u16             qd_limit;
1341         u32             scan_counter;
1342         struct aac_ciss_identify_pd  *safw_identify_resp;
1343 };
1344
1345 /*
1346  *      Adapter Information Block
1347  *
1348  *      This is returned by the RequestAdapterInfo block
1349  */
1350
1351 struct aac_adapter_info
1352 {
1353         __le32  platform;
1354         __le32  cpu;
1355         __le32  subcpu;
1356         __le32  clock;
1357         __le32  execmem;
1358         __le32  buffermem;
1359         __le32  totalmem;
1360         __le32  kernelrev;
1361         __le32  kernelbuild;
1362         __le32  monitorrev;
1363         __le32  monitorbuild;
1364         __le32  hwrev;
1365         __le32  hwbuild;
1366         __le32  biosrev;
1367         __le32  biosbuild;
1368         __le32  cluster;
1369         __le32  clusterchannelmask;
1370         __le32  serial[2];
1371         __le32  battery;
1372         __le32  options;
1373         __le32  OEM;
1374 };
1375
1376 struct aac_supplement_adapter_info
1377 {
1378         u8      adapter_type_text[17+1];
1379         u8      pad[2];
1380         __le32  flash_memory_byte_size;
1381         __le32  flash_image_id;
1382         __le32  max_number_ports;
1383         __le32  version;
1384         __le32  feature_bits;
1385         u8      slot_number;
1386         u8      reserved_pad0[3];
1387         u8      build_date[12];
1388         __le32  current_number_ports;
1389         struct {
1390                 u8      assembly_pn[8];
1391                 u8      fru_pn[8];
1392                 u8      battery_fru_pn[8];
1393                 u8      ec_version_string[8];
1394                 u8      tsid[12];
1395         }       vpd_info;
1396         __le32  flash_firmware_revision;
1397         __le32  flash_firmware_build;
1398         __le32  raid_type_morph_options;
1399         __le32  flash_firmware_boot_revision;
1400         __le32  flash_firmware_boot_build;
1401         u8      mfg_pcba_serial_no[12];
1402         u8      mfg_wwn_name[8];
1403         __le32  supported_options2;
1404         __le32  struct_expansion;
1405         /* StructExpansion == 1 */
1406         __le32  feature_bits3;
1407         __le32  supported_performance_modes;
1408         u8      host_bus_type;          /* uses HOST_BUS_TYPE_xxx defines */
1409         u8      host_bus_width;         /* actual width in bits or links */
1410         u16     host_bus_speed;         /* actual bus speed/link rate in MHz */
1411         u8      max_rrc_drives;         /* max. number of ITP-RRC drives/pool */
1412         u8      max_disk_xtasks;        /* max. possible num of DiskX Tasks */
1413
1414         u8      cpld_ver_loaded;
1415         u8      cpld_ver_in_flash;
1416
1417         __le64  max_rrc_capacity;
1418         __le32  compiled_max_hist_log_level;
1419         u8      custom_board_name[12];
1420         u16     supported_cntlr_mode;   /* identify supported controller mode */
1421         u16     reserved_for_future16;
1422         __le32  supported_options3;     /* reserved for future options */
1423
1424         __le16  virt_device_bus;                /* virt. SCSI device for Thor */
1425         __le16  virt_device_target;
1426         __le16  virt_device_lun;
1427         __le16  unused;
1428         __le32  reserved_for_future_growth[68];
1429
1430 };
1431 #define AAC_FEATURE_FALCON      cpu_to_le32(0x00000010)
1432 #define AAC_FEATURE_JBOD        cpu_to_le32(0x08000000)
1433 /* SupportedOptions2 */
1434 #define AAC_OPTION_MU_RESET             cpu_to_le32(0x00000001)
1435 #define AAC_OPTION_IGNORE_RESET         cpu_to_le32(0x00000002)
1436 #define AAC_OPTION_POWER_MANAGEMENT     cpu_to_le32(0x00000004)
1437 #define AAC_OPTION_DOORBELL_RESET       cpu_to_le32(0x00004000)
1438 /* 4KB sector size */
1439 #define AAC_OPTION_VARIABLE_BLOCK_SIZE  cpu_to_le32(0x00040000)
1440 /* 240 simple volume support */
1441 #define AAC_OPTION_SUPPORTED_240_VOLUMES cpu_to_le32(0x10000000)
1442 /*
1443  * Supports FIB dump sync command send prior to IOP_RESET
1444  */
1445 #define AAC_OPTION_SUPPORTED3_IOP_RESET_FIB_DUMP        cpu_to_le32(0x00004000)
1446 #define AAC_SIS_VERSION_V3      3
1447 #define AAC_SIS_SLOT_UNKNOWN    0xFF
1448
1449 #define GetBusInfo 0x00000009
1450 struct aac_bus_info {
1451         __le32  Command;        /* VM_Ioctl */
1452         __le32  ObjType;        /* FT_DRIVE */
1453         __le32  MethodId;       /* 1 = SCSI Layer */
1454         __le32  ObjectId;       /* Handle */
1455         __le32  CtlCmd;         /* GetBusInfo */
1456 };
1457
1458 struct aac_bus_info_response {
1459         __le32  Status;         /* ST_OK */
1460         __le32  ObjType;
1461         __le32  MethodId;       /* unused */
1462         __le32  ObjectId;       /* unused */
1463         __le32  CtlCmd;         /* unused */
1464         __le32  ProbeComplete;
1465         __le32  BusCount;
1466         __le32  TargetsPerBus;
1467         u8      InitiatorBusId[10];
1468         u8      BusValid[10];
1469 };
1470
1471 /*
1472  * Battery platforms
1473  */
1474 #define AAC_BAT_REQ_PRESENT     (1)
1475 #define AAC_BAT_REQ_NOTPRESENT  (2)
1476 #define AAC_BAT_OPT_PRESENT     (3)
1477 #define AAC_BAT_OPT_NOTPRESENT  (4)
1478 #define AAC_BAT_NOT_SUPPORTED   (5)
1479 /*
1480  * cpu types
1481  */
1482 #define AAC_CPU_SIMULATOR       (1)
1483 #define AAC_CPU_I960            (2)
1484 #define AAC_CPU_STRONGARM       (3)
1485
1486 /*
1487  * Supported Options
1488  */
1489 #define AAC_OPT_SNAPSHOT                cpu_to_le32(1)
1490 #define AAC_OPT_CLUSTERS                cpu_to_le32(1<<1)
1491 #define AAC_OPT_WRITE_CACHE             cpu_to_le32(1<<2)
1492 #define AAC_OPT_64BIT_DATA              cpu_to_le32(1<<3)
1493 #define AAC_OPT_HOST_TIME_FIB           cpu_to_le32(1<<4)
1494 #define AAC_OPT_RAID50                  cpu_to_le32(1<<5)
1495 #define AAC_OPT_4GB_WINDOW              cpu_to_le32(1<<6)
1496 #define AAC_OPT_SCSI_UPGRADEABLE        cpu_to_le32(1<<7)
1497 #define AAC_OPT_SOFT_ERR_REPORT         cpu_to_le32(1<<8)
1498 #define AAC_OPT_SUPPORTED_RECONDITION   cpu_to_le32(1<<9)
1499 #define AAC_OPT_SGMAP_HOST64            cpu_to_le32(1<<10)
1500 #define AAC_OPT_ALARM                   cpu_to_le32(1<<11)
1501 #define AAC_OPT_NONDASD                 cpu_to_le32(1<<12)
1502 #define AAC_OPT_SCSI_MANAGED            cpu_to_le32(1<<13)
1503 #define AAC_OPT_RAID_SCSI_MODE          cpu_to_le32(1<<14)
1504 #define AAC_OPT_SUPPLEMENT_ADAPTER_INFO cpu_to_le32(1<<16)
1505 #define AAC_OPT_NEW_COMM                cpu_to_le32(1<<17)
1506 #define AAC_OPT_NEW_COMM_64             cpu_to_le32(1<<18)
1507 #define AAC_OPT_EXTENDED                cpu_to_le32(1<<23)
1508 #define AAC_OPT_NATIVE_HBA              cpu_to_le32(1<<25)
1509 #define AAC_OPT_NEW_COMM_TYPE1          cpu_to_le32(1<<28)
1510 #define AAC_OPT_NEW_COMM_TYPE2          cpu_to_le32(1<<29)
1511 #define AAC_OPT_NEW_COMM_TYPE3          cpu_to_le32(1<<30)
1512 #define AAC_OPT_NEW_COMM_TYPE4          cpu_to_le32(1<<31)
1513
1514 #define AAC_COMM_PRODUCER               0
1515 #define AAC_COMM_MESSAGE                1
1516 #define AAC_COMM_MESSAGE_TYPE1          3
1517 #define AAC_COMM_MESSAGE_TYPE2          4
1518 #define AAC_COMM_MESSAGE_TYPE3          5
1519
1520 #define AAC_EXTOPT_SA_FIRMWARE          cpu_to_le32(1<<1)
1521 #define AAC_EXTOPT_SOFT_RESET           cpu_to_le32(1<<16)
1522
1523 /* MSIX context */
1524 struct aac_msix_ctx {
1525         int             vector_no;
1526         struct aac_dev  *dev;
1527 };
1528
1529 struct aac_dev
1530 {
1531         struct list_head        entry;
1532         const char              *name;
1533         int                     id;
1534
1535         /*
1536          *      negotiated FIB settings
1537          */
1538         unsigned int            max_fib_size;
1539         unsigned int            sg_tablesize;
1540         unsigned int            max_num_aif;
1541
1542         unsigned int            max_cmd_size;   /* max_fib_size or MAX_NATIVE */
1543
1544         /*
1545          *      Map for 128 fib objects (64k)
1546          */
1547         dma_addr_t              hw_fib_pa;      /* also used for native cmd */
1548         struct hw_fib           *hw_fib_va;     /* also used for native cmd */
1549         struct hw_fib           *aif_base_va;
1550         /*
1551          *      Fib Headers
1552          */
1553         struct fib              *fibs;
1554
1555         struct fib              *free_fib;
1556         spinlock_t              fib_lock;
1557
1558         struct mutex            ioctl_mutex;
1559         struct mutex            scan_mutex;
1560         struct aac_queue_block *queues;
1561         /*
1562          *      The user API will use an IOCTL to register itself to receive
1563          *      FIBs from the adapter.  The following list is used to keep
1564          *      track of all the threads that have requested these FIBs.  The
1565          *      mutex is used to synchronize access to all data associated
1566          *      with the adapter fibs.
1567          */
1568         struct list_head        fib_list;
1569
1570         struct adapter_ops      a_ops;
1571         unsigned long           fsrev;          /* Main driver's revision number */
1572
1573         resource_size_t         base_start;     /* main IO base */
1574         resource_size_t         dbg_base;       /* address of UART
1575                                                  * debug buffer */
1576
1577         resource_size_t         base_size, dbg_size;    /* Size of
1578                                                          *  mapped in region */
1579         /*
1580          * Holds initialization info
1581          * to communicate with adapter
1582          */
1583         union aac_init          *init;
1584         dma_addr_t              init_pa;        /* Holds physical address of the init struct */
1585         /* response queue (if AAC_COMM_MESSAGE_TYPE1) */
1586         __le32                  *host_rrq;
1587         dma_addr_t              host_rrq_pa;    /* phys. address */
1588         /* index into rrq buffer */
1589         u32                     host_rrq_idx[AAC_MAX_MSIX];
1590         atomic_t                rrq_outstanding[AAC_MAX_MSIX];
1591         u32                     fibs_pushed_no;
1592         struct pci_dev          *pdev;          /* Our PCI interface */
1593         /* pointer to buffer used for printf's from the adapter */
1594         void                    *printfbuf;
1595         void                    *comm_addr;     /* Base address of Comm area */
1596         dma_addr_t              comm_phys;      /* Physical Address of Comm area */
1597         size_t                  comm_size;
1598
1599         struct Scsi_Host        *scsi_host_ptr;
1600         int                     maximum_num_containers;
1601         int                     maximum_num_physicals;
1602         int                     maximum_num_channels;
1603         struct fsa_dev_info     *fsa_dev;
1604         struct task_struct      *thread;
1605         struct delayed_work     safw_rescan_work;
1606         struct delayed_work     src_reinit_aif_worker;
1607         int                     cardtype;
1608         /*
1609          *This lock will protect the two 32-bit
1610          *writes to the Inbound Queue
1611          */
1612         spinlock_t              iq_lock;
1613
1614         /*
1615          *      The following is the device specific extension.
1616          */
1617 #ifndef AAC_MIN_FOOTPRINT_SIZE
1618 #       define AAC_MIN_FOOTPRINT_SIZE 8192
1619 #       define AAC_MIN_SRC_BAR0_SIZE 0x400000
1620 #       define AAC_MIN_SRC_BAR1_SIZE 0x800
1621 #       define AAC_MIN_SRCV_BAR0_SIZE 0x100000
1622 #       define AAC_MIN_SRCV_BAR1_SIZE 0x400
1623 #endif
1624         union
1625         {
1626                 struct sa_registers __iomem *sa;
1627                 struct rx_registers __iomem *rx;
1628                 struct rkt_registers __iomem *rkt;
1629                 struct {
1630                         struct src_registers __iomem *bar0;
1631                         char __iomem *bar1;
1632                 } src;
1633         } regs;
1634         volatile void __iomem *base, *dbg_base_mapped;
1635         volatile struct rx_inbound __iomem *IndexRegs;
1636         u32                     OIMR; /* Mask Register Cache */
1637         /*
1638          *      AIF thread states
1639          */
1640         u32                     aif_thread;
1641         struct aac_adapter_info adapter_info;
1642         struct aac_supplement_adapter_info supplement_adapter_info;
1643         /* These are in adapter info but they are in the io flow so
1644          * lets break them out so we don't have to do an AND to check them
1645          */
1646         u8                      nondasd_support;
1647         u8                      jbod;
1648         u8                      cache_protected;
1649         u8                      dac_support;
1650         u8                      needs_dac;
1651         u8                      raid_scsi_mode;
1652         u8                      comm_interface;
1653         u8                      raw_io_interface;
1654         u8                      raw_io_64;
1655         u8                      printf_enabled;
1656         u8                      in_reset;
1657         u8                      in_soft_reset;
1658         u8                      msi;
1659         u8                      sa_firmware;
1660         int                     management_fib_count;
1661         spinlock_t              manage_lock;
1662         spinlock_t              sync_lock;
1663         int                     sync_mode;
1664         struct fib              *sync_fib;
1665         struct list_head        sync_fib_list;
1666         u32                     doorbell_mask;
1667         u32                     max_msix;       /* max. MSI-X vectors */
1668         u32                     vector_cap;     /* MSI-X vector capab.*/
1669         int                     msi_enabled;    /* MSI/MSI-X enabled */
1670         atomic_t                msix_counter;
1671         u32                     scan_counter;
1672         struct msix_entry       msixentry[AAC_MAX_MSIX];
1673         struct aac_msix_ctx     aac_msix[AAC_MAX_MSIX]; /* context */
1674         struct aac_hba_map_info hba_map[AAC_MAX_BUSES][AAC_MAX_TARGETS];
1675         struct aac_ciss_phys_luns_resp *safw_phys_luns;
1676         u8                      adapter_shutdown;
1677         u32                     handle_pci_error;
1678         bool                    init_reset;
1679         u8                      soft_reset_support;
1680 };
1681
1682 #define aac_adapter_interrupt(dev) \
1683         (dev)->a_ops.adapter_interrupt(dev)
1684
1685 #define aac_adapter_notify(dev, event) \
1686         (dev)->a_ops.adapter_notify(dev, event)
1687
1688 #define aac_adapter_disable_int(dev) \
1689         (dev)->a_ops.adapter_disable_int(dev)
1690
1691 #define aac_adapter_enable_int(dev) \
1692         (dev)->a_ops.adapter_enable_int(dev)
1693
1694 #define aac_adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) \
1695         (dev)->a_ops.adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4)
1696
1697 #define aac_adapter_restart(dev, bled, reset_type) \
1698         ((dev)->a_ops.adapter_restart(dev, bled, reset_type))
1699
1700 #define aac_adapter_start(dev) \
1701         ((dev)->a_ops.adapter_start(dev))
1702
1703 #define aac_adapter_ioremap(dev, size) \
1704         (dev)->a_ops.adapter_ioremap(dev, size)
1705
1706 #define aac_adapter_deliver(fib) \
1707         ((fib)->dev)->a_ops.adapter_deliver(fib)
1708
1709 #define aac_adapter_bounds(dev,cmd,lba) \
1710         dev->a_ops.adapter_bounds(dev,cmd,lba)
1711
1712 #define aac_adapter_read(fib,cmd,lba,count) \
1713         ((fib)->dev)->a_ops.adapter_read(fib,cmd,lba,count)
1714
1715 #define aac_adapter_write(fib,cmd,lba,count,fua) \
1716         ((fib)->dev)->a_ops.adapter_write(fib,cmd,lba,count,fua)
1717
1718 #define aac_adapter_scsi(fib,cmd) \
1719         ((fib)->dev)->a_ops.adapter_scsi(fib,cmd)
1720
1721 #define aac_adapter_comm(dev,comm) \
1722         (dev)->a_ops.adapter_comm(dev, comm)
1723
1724 #define FIB_CONTEXT_FLAG_TIMED_OUT              (0x00000001)
1725 #define FIB_CONTEXT_FLAG                        (0x00000002)
1726 #define FIB_CONTEXT_FLAG_WAIT                   (0x00000004)
1727 #define FIB_CONTEXT_FLAG_FASTRESP               (0x00000008)
1728 #define FIB_CONTEXT_FLAG_NATIVE_HBA             (0x00000010)
1729 #define FIB_CONTEXT_FLAG_NATIVE_HBA_TMF (0x00000020)
1730 #define FIB_CONTEXT_FLAG_SCSI_CMD       (0x00000040)
1731 #define FIB_CONTEXT_FLAG_EH_RESET       (0x00000080)
1732
1733 /*
1734  *      Define the command values
1735  */
1736
1737 #define         Null                    0
1738 #define         GetAttributes           1
1739 #define         SetAttributes           2
1740 #define         Lookup                  3
1741 #define         ReadLink                4
1742 #define         Read                    5
1743 #define         Write                   6
1744 #define         Create                  7
1745 #define         MakeDirectory           8
1746 #define         SymbolicLink            9
1747 #define         MakeNode                10
1748 #define         Removex                 11
1749 #define         RemoveDirectoryx        12
1750 #define         Rename                  13
1751 #define         Link                    14
1752 #define         ReadDirectory           15
1753 #define         ReadDirectoryPlus       16
1754 #define         FileSystemStatus        17
1755 #define         FileSystemInfo          18
1756 #define         PathConfigure           19
1757 #define         Commit                  20
1758 #define         Mount                   21
1759 #define         UnMount                 22
1760 #define         Newfs                   23
1761 #define         FsCheck                 24
1762 #define         FsSync                  25
1763 #define         SimReadWrite            26
1764 #define         SetFileSystemStatus     27
1765 #define         BlockRead               28
1766 #define         BlockWrite              29
1767 #define         NvramIoctl              30
1768 #define         FsSyncWait              31
1769 #define         ClearArchiveBit         32
1770 #define         SetAcl                  33
1771 #define         GetAcl                  34
1772 #define         AssignAcl               35
1773 #define         FaultInsertion          36      /* Fault Insertion Command */
1774 #define         CrazyCache              37      /* Crazycache */
1775
1776 #define         MAX_FSACOMMAND_NUM      38
1777
1778
1779 /*
1780  *      Define the status returns. These are very unixlike although
1781  *      most are not in fact used
1782  */
1783
1784 #define         ST_OK           0
1785 #define         ST_PERM         1
1786 #define         ST_NOENT        2
1787 #define         ST_IO           5
1788 #define         ST_NXIO         6
1789 #define         ST_E2BIG        7
1790 #define         ST_MEDERR       8
1791 #define         ST_ACCES        13
1792 #define         ST_EXIST        17
1793 #define         ST_XDEV         18
1794 #define         ST_NODEV        19
1795 #define         ST_NOTDIR       20
1796 #define         ST_ISDIR        21
1797 #define         ST_INVAL        22
1798 #define         ST_FBIG         27
1799 #define         ST_NOSPC        28
1800 #define         ST_ROFS         30
1801 #define         ST_MLINK        31
1802 #define         ST_WOULDBLOCK   35
1803 #define         ST_NAMETOOLONG  63
1804 #define         ST_NOTEMPTY     66
1805 #define         ST_DQUOT        69
1806 #define         ST_STALE        70
1807 #define         ST_REMOTE       71
1808 #define         ST_NOT_READY    72
1809 #define         ST_BADHANDLE    10001
1810 #define         ST_NOT_SYNC     10002
1811 #define         ST_BAD_COOKIE   10003
1812 #define         ST_NOTSUPP      10004
1813 #define         ST_TOOSMALL     10005
1814 #define         ST_SERVERFAULT  10006
1815 #define         ST_BADTYPE      10007
1816 #define         ST_JUKEBOX      10008
1817 #define         ST_NOTMOUNTED   10009
1818 #define         ST_MAINTMODE    10010
1819 #define         ST_STALEACL     10011
1820
1821 /*
1822  *      On writes how does the client want the data written.
1823  */
1824
1825 #define CACHE_CSTABLE           1
1826 #define CACHE_UNSTABLE          2
1827
1828 /*
1829  *      Lets the client know at which level the data was committed on
1830  *      a write request
1831  */
1832
1833 #define CMFILE_SYNCH_NVRAM      1
1834 #define CMDATA_SYNCH_NVRAM      2
1835 #define CMFILE_SYNCH            3
1836 #define CMDATA_SYNCH            4
1837 #define CMUNSTABLE              5
1838
1839 #define RIO_TYPE_WRITE                  0x0000
1840 #define RIO_TYPE_READ                   0x0001
1841 #define RIO_SUREWRITE                   0x0008
1842
1843 #define RIO2_IO_TYPE                    0x0003
1844 #define RIO2_IO_TYPE_WRITE              0x0000
1845 #define RIO2_IO_TYPE_READ               0x0001
1846 #define RIO2_IO_TYPE_VERIFY             0x0002
1847 #define RIO2_IO_ERROR                   0x0004
1848 #define RIO2_IO_SUREWRITE               0x0008
1849 #define RIO2_SGL_CONFORMANT             0x0010
1850 #define RIO2_SG_FORMAT                  0xF000
1851 #define RIO2_SG_FORMAT_ARC              0x0000
1852 #define RIO2_SG_FORMAT_SRL              0x1000
1853 #define RIO2_SG_FORMAT_IEEE1212         0x2000
1854
1855 struct aac_read
1856 {
1857         __le32          command;
1858         __le32          cid;
1859         __le32          block;
1860         __le32          count;
1861         struct sgmap    sg;     // Must be last in struct because it is variable
1862 };
1863
1864 struct aac_read64
1865 {
1866         __le32          command;
1867         __le16          cid;
1868         __le16          sector_count;
1869         __le32          block;
1870         __le16          pad;
1871         __le16          flags;
1872         struct sgmap64  sg;     // Must be last in struct because it is variable
1873 };
1874
1875 struct aac_read_reply
1876 {
1877         __le32          status;
1878         __le32          count;
1879 };
1880
1881 struct aac_write
1882 {
1883         __le32          command;
1884         __le32          cid;
1885         __le32          block;
1886         __le32          count;
1887         __le32          stable; // Not used
1888         struct sgmap    sg;     // Must be last in struct because it is variable
1889 };
1890
1891 struct aac_write64
1892 {
1893         __le32          command;
1894         __le16          cid;
1895         __le16          sector_count;
1896         __le32          block;
1897         __le16          pad;
1898         __le16          flags;
1899         struct sgmap64  sg;     // Must be last in struct because it is variable
1900 };
1901 struct aac_write_reply
1902 {
1903         __le32          status;
1904         __le32          count;
1905         __le32          committed;
1906 };
1907
1908 struct aac_raw_io
1909 {
1910         __le32          block[2];
1911         __le32          count;
1912         __le16          cid;
1913         __le16          flags;          /* 00 W, 01 R */
1914         __le16          bpTotal;        /* reserved for F/W use */
1915         __le16          bpComplete;     /* reserved for F/W use */
1916         struct sgmapraw sg;
1917 };
1918
1919 struct aac_raw_io2 {
1920         __le32          blockLow;
1921         __le32          blockHigh;
1922         __le32          byteCount;
1923         __le16          cid;
1924         __le16          flags;          /* RIO2 flags */
1925         __le32          sgeFirstSize;   /* size of first sge el. */
1926         __le32          sgeNominalSize; /* size of 2nd sge el. (if conformant) */
1927         u8              sgeCnt;         /* only 8 bits required */
1928         u8              bpTotal;        /* reserved for F/W use */
1929         u8              bpComplete;     /* reserved for F/W use */
1930         u8              sgeFirstIndex;  /* reserved for F/W use */
1931         u8              unused[4];
1932         struct sge_ieee1212     sge[1];
1933 };
1934
1935 #define CT_FLUSH_CACHE 129
1936 struct aac_synchronize {
1937         __le32          command;        /* VM_ContainerConfig */
1938         __le32          type;           /* CT_FLUSH_CACHE */
1939         __le32          cid;
1940         __le32          parm1;
1941         __le32          parm2;
1942         __le32          parm3;
1943         __le32          parm4;
1944         __le32          count;  /* sizeof(((struct aac_synchronize_reply *)NULL)->data) */
1945 };
1946
1947 struct aac_synchronize_reply {
1948         __le32          dummy0;
1949         __le32          dummy1;
1950         __le32          status; /* CT_OK */
1951         __le32          parm1;
1952         __le32          parm2;
1953         __le32          parm3;
1954         __le32          parm4;
1955         __le32          parm5;
1956         u8              data[16];
1957 };
1958
1959 #define CT_POWER_MANAGEMENT     245
1960 #define CT_PM_START_UNIT        2
1961 #define CT_PM_STOP_UNIT         3
1962 #define CT_PM_UNIT_IMMEDIATE    1
1963 struct aac_power_management {
1964         __le32          command;        /* VM_ContainerConfig */
1965         __le32          type;           /* CT_POWER_MANAGEMENT */
1966         __le32          sub;            /* CT_PM_* */
1967         __le32          cid;
1968         __le32          parm;           /* CT_PM_sub_* */
1969 };
1970
1971 #define CT_PAUSE_IO    65
1972 #define CT_RELEASE_IO  66
1973 struct aac_pause {
1974         __le32          command;        /* VM_ContainerConfig */
1975         __le32          type;           /* CT_PAUSE_IO */
1976         __le32          timeout;        /* 10ms ticks */
1977         __le32          min;
1978         __le32          noRescan;
1979         __le32          parm3;
1980         __le32          parm4;
1981         __le32          count;  /* sizeof(((struct aac_pause_reply *)NULL)->data) */
1982 };
1983
1984 struct aac_srb
1985 {
1986         __le32          function;
1987         __le32          channel;
1988         __le32          id;
1989         __le32          lun;
1990         __le32          timeout;
1991         __le32          flags;
1992         __le32          count;          // Data xfer size
1993         __le32          retry_limit;
1994         __le32          cdb_size;
1995         u8              cdb[16];
1996         struct  sgmap   sg;
1997 };
1998
1999 /*
2000  * This and associated data structs are used by the
2001  * ioctl caller and are in cpu order.
2002  */
2003 struct user_aac_srb
2004 {
2005         u32             function;
2006         u32             channel;
2007         u32             id;
2008         u32             lun;
2009         u32             timeout;
2010         u32             flags;
2011         u32             count;          // Data xfer size
2012         u32             retry_limit;
2013         u32             cdb_size;
2014         u8              cdb[16];
2015         struct  user_sgmap      sg;
2016 };
2017
2018 #define         AAC_SENSE_BUFFERSIZE     30
2019
2020 struct aac_srb_reply
2021 {
2022         __le32          status;
2023         __le32          srb_status;
2024         __le32          scsi_status;
2025         __le32          data_xfer_length;
2026         __le32          sense_data_size;
2027         u8              sense_data[AAC_SENSE_BUFFERSIZE]; // Can this be SCSI_SENSE_BUFFERSIZE
2028 };
2029
2030 struct aac_srb_unit {
2031         struct aac_srb          srb;
2032         struct aac_srb_reply    srb_reply;
2033 };
2034
2035 /*
2036  * SRB Flags
2037  */
2038 #define         SRB_NoDataXfer           0x0000
2039 #define         SRB_DisableDisconnect    0x0004
2040 #define         SRB_DisableSynchTransfer 0x0008
2041 #define         SRB_BypassFrozenQueue    0x0010
2042 #define         SRB_DisableAutosense     0x0020
2043 #define         SRB_DataIn               0x0040
2044 #define         SRB_DataOut              0x0080
2045
2046 /*
2047  * SRB Functions - set in aac_srb->function
2048  */
2049 #define SRBF_ExecuteScsi        0x0000
2050 #define SRBF_ClaimDevice        0x0001
2051 #define SRBF_IO_Control         0x0002
2052 #define SRBF_ReceiveEvent       0x0003
2053 #define SRBF_ReleaseQueue       0x0004
2054 #define SRBF_AttachDevice       0x0005
2055 #define SRBF_ReleaseDevice      0x0006
2056 #define SRBF_Shutdown           0x0007
2057 #define SRBF_Flush              0x0008
2058 #define SRBF_AbortCommand       0x0010
2059 #define SRBF_ReleaseRecovery    0x0011
2060 #define SRBF_ResetBus           0x0012
2061 #define SRBF_ResetDevice        0x0013
2062 #define SRBF_TerminateIO        0x0014
2063 #define SRBF_FlushQueue         0x0015
2064 #define SRBF_RemoveDevice       0x0016
2065 #define SRBF_DomainValidation   0x0017
2066
2067 /*
2068  * SRB SCSI Status - set in aac_srb->scsi_status
2069  */
2070 #define SRB_STATUS_PENDING                  0x00
2071 #define SRB_STATUS_SUCCESS                  0x01
2072 #define SRB_STATUS_ABORTED                  0x02
2073 #define SRB_STATUS_ABORT_FAILED             0x03
2074 #define SRB_STATUS_ERROR                    0x04
2075 #define SRB_STATUS_BUSY                     0x05
2076 #define SRB_STATUS_INVALID_REQUEST          0x06
2077 #define SRB_STATUS_INVALID_PATH_ID          0x07
2078 #define SRB_STATUS_NO_DEVICE                0x08
2079 #define SRB_STATUS_TIMEOUT                  0x09
2080 #define SRB_STATUS_SELECTION_TIMEOUT        0x0A
2081 #define SRB_STATUS_COMMAND_TIMEOUT          0x0B
2082 #define SRB_STATUS_MESSAGE_REJECTED         0x0D
2083 #define SRB_STATUS_BUS_RESET                0x0E
2084 #define SRB_STATUS_PARITY_ERROR             0x0F
2085 #define SRB_STATUS_REQUEST_SENSE_FAILED     0x10
2086 #define SRB_STATUS_NO_HBA                   0x11
2087 #define SRB_STATUS_DATA_OVERRUN             0x12
2088 #define SRB_STATUS_UNEXPECTED_BUS_FREE      0x13
2089 #define SRB_STATUS_PHASE_SEQUENCE_FAILURE   0x14
2090 #define SRB_STATUS_BAD_SRB_BLOCK_LENGTH     0x15
2091 #define SRB_STATUS_REQUEST_FLUSHED          0x16
2092 #define SRB_STATUS_DELAYED_RETRY            0x17
2093 #define SRB_STATUS_INVALID_LUN              0x20
2094 #define SRB_STATUS_INVALID_TARGET_ID        0x21
2095 #define SRB_STATUS_BAD_FUNCTION             0x22
2096 #define SRB_STATUS_ERROR_RECOVERY           0x23
2097 #define SRB_STATUS_NOT_STARTED              0x24
2098 #define SRB_STATUS_NOT_IN_USE               0x30
2099 #define SRB_STATUS_FORCE_ABORT              0x31
2100 #define SRB_STATUS_DOMAIN_VALIDATION_FAIL   0x32
2101
2102 /*
2103  * Object-Server / Volume-Manager Dispatch Classes
2104  */
2105
2106 #define         VM_Null                 0
2107 #define         VM_NameServe            1
2108 #define         VM_ContainerConfig      2
2109 #define         VM_Ioctl                3
2110 #define         VM_FilesystemIoctl      4
2111 #define         VM_CloseAll             5
2112 #define         VM_CtBlockRead          6
2113 #define         VM_CtBlockWrite         7
2114 #define         VM_SliceBlockRead       8       /* raw access to configured "storage objects" */
2115 #define         VM_SliceBlockWrite      9
2116 #define         VM_DriveBlockRead       10      /* raw access to physical devices */
2117 #define         VM_DriveBlockWrite      11
2118 #define         VM_EnclosureMgt         12      /* enclosure management */
2119 #define         VM_Unused               13      /* used to be diskset management */
2120 #define         VM_CtBlockVerify        14
2121 #define         VM_CtPerf               15      /* performance test */
2122 #define         VM_CtBlockRead64        16
2123 #define         VM_CtBlockWrite64       17
2124 #define         VM_CtBlockVerify64      18
2125 #define         VM_CtHostRead64         19
2126 #define         VM_CtHostWrite64        20
2127 #define         VM_DrvErrTblLog         21
2128 #define         VM_NameServe64          22
2129 #define         VM_NameServeAllBlk      30
2130
2131 #define         MAX_VMCOMMAND_NUM       23      /* used for sizing stats array - leave last */
2132
2133 /*
2134  *      Descriptive information (eg, vital stats)
2135  *      that a content manager might report.  The
2136  *      FileArray filesystem component is one example
2137  *      of a content manager.  Raw mode might be
2138  *      another.
2139  */
2140
2141 struct aac_fsinfo {
2142         __le32  fsTotalSize;    /* Consumed by fs, incl. metadata */
2143         __le32  fsBlockSize;
2144         __le32  fsFragSize;
2145         __le32  fsMaxExtendSize;
2146         __le32  fsSpaceUnits;
2147         __le32  fsMaxNumFiles;
2148         __le32  fsNumFreeFiles;
2149         __le32  fsInodeDensity;
2150 };      /* valid iff ObjType == FT_FILESYS && !(ContentState & FSCS_NOTCLEAN) */
2151
2152 struct  aac_blockdevinfo {
2153         __le32  block_size;
2154         __le32  logical_phys_map;
2155         u8      identifier[16];
2156 };
2157
2158 union aac_contentinfo {
2159         struct  aac_fsinfo              filesys;
2160         struct  aac_blockdevinfo        bdevinfo;
2161 };
2162
2163 /*
2164  *      Query for Container Configuration Status
2165  */
2166
2167 #define CT_GET_CONFIG_STATUS 147
2168 struct aac_get_config_status {
2169         __le32          command;        /* VM_ContainerConfig */
2170         __le32          type;           /* CT_GET_CONFIG_STATUS */
2171         __le32          parm1;
2172         __le32          parm2;
2173         __le32          parm3;
2174         __le32          parm4;
2175         __le32          parm5;
2176         __le32          count;  /* sizeof(((struct aac_get_config_status_resp *)NULL)->data) */
2177 };
2178
2179 #define CFACT_CONTINUE 0
2180 #define CFACT_PAUSE    1
2181 #define CFACT_ABORT    2
2182 struct aac_get_config_status_resp {
2183         __le32          response; /* ST_OK */
2184         __le32          dummy0;
2185         __le32          status; /* CT_OK */
2186         __le32          parm1;
2187         __le32          parm2;
2188         __le32          parm3;
2189         __le32          parm4;
2190         __le32          parm5;
2191         struct {
2192                 __le32  action; /* CFACT_CONTINUE, CFACT_PAUSE or CFACT_ABORT */
2193                 __le16  flags;
2194                 __le16  count;
2195         }               data;
2196 };
2197
2198 /*
2199  *      Accept the configuration as-is
2200  */
2201
2202 #define CT_COMMIT_CONFIG 152
2203
2204 struct aac_commit_config {
2205         __le32          command;        /* VM_ContainerConfig */
2206         __le32          type;           /* CT_COMMIT_CONFIG */
2207 };
2208
2209 /*
2210  *      Query for Container Configuration Status
2211  */
2212
2213 #define CT_GET_CONTAINER_COUNT 4
2214 struct aac_get_container_count {
2215         __le32          command;        /* VM_ContainerConfig */
2216         __le32          type;           /* CT_GET_CONTAINER_COUNT */
2217 };
2218
2219 struct aac_get_container_count_resp {
2220         __le32          response; /* ST_OK */
2221         __le32          dummy0;
2222         __le32          MaxContainers;
2223         __le32          ContainerSwitchEntries;
2224         __le32          MaxPartitions;
2225         __le32          MaxSimpleVolumes;
2226 };
2227
2228
2229 /*
2230  *      Query for "mountable" objects, ie, objects that are typically
2231  *      associated with a drive letter on the client (host) side.
2232  */
2233
2234 struct aac_mntent {
2235         __le32                  oid;
2236         u8                      name[16];       /* if applicable */
2237         struct creation_info    create_info;    /* if applicable */
2238         __le32                  capacity;
2239         __le32                  vol;            /* substrate structure */
2240         __le32                  obj;            /* FT_FILESYS, etc. */
2241         __le32                  state;          /* unready for mounting,
2242                                                    readonly, etc. */
2243         union aac_contentinfo   fileinfo;       /* Info specific to content
2244                                                    manager (eg, filesystem) */
2245         __le32                  altoid;         /* != oid <==> snapshot or
2246                                                    broken mirror exists */
2247         __le32                  capacityhigh;
2248 };
2249
2250 #define FSCS_NOTCLEAN   0x0001  /* fsck is necessary before mounting */
2251 #define FSCS_READONLY   0x0002  /* possible result of broken mirror */
2252 #define FSCS_HIDDEN     0x0004  /* should be ignored - set during a clear */
2253 #define FSCS_NOT_READY  0x0008  /* Array spinning up to fulfil request */
2254
2255 struct aac_query_mount {
2256         __le32          command;
2257         __le32          type;
2258         __le32          count;
2259 };
2260
2261 struct aac_mount {
2262         __le32          status;
2263         __le32          type;           /* should be same as that requested */
2264         __le32          count;
2265         struct aac_mntent mnt[1];
2266 };
2267
2268 #define CT_READ_NAME 130
2269 struct aac_get_name {
2270         __le32          command;        /* VM_ContainerConfig */
2271         __le32          type;           /* CT_READ_NAME */
2272         __le32          cid;
2273         __le32          parm1;
2274         __le32          parm2;
2275         __le32          parm3;
2276         __le32          parm4;
2277         __le32          count;  /* sizeof(((struct aac_get_name_resp *)NULL)->data) */
2278 };
2279
2280 struct aac_get_name_resp {
2281         __le32          dummy0;
2282         __le32          dummy1;
2283         __le32          status; /* CT_OK */
2284         __le32          parm1;
2285         __le32          parm2;
2286         __le32          parm3;
2287         __le32          parm4;
2288         __le32          parm5;
2289         u8              data[17];
2290 };
2291
2292 #define CT_CID_TO_32BITS_UID 165
2293 struct aac_get_serial {
2294         __le32          command;        /* VM_ContainerConfig */
2295         __le32          type;           /* CT_CID_TO_32BITS_UID */
2296         __le32          cid;
2297 };
2298
2299 struct aac_get_serial_resp {
2300         __le32          dummy0;
2301         __le32          dummy1;
2302         __le32          status; /* CT_OK */
2303         __le32          uid;
2304 };
2305
2306 /*
2307  * The following command is sent to shut down each container.
2308  */
2309
2310 struct aac_close {
2311         __le32  command;
2312         __le32  cid;
2313 };
2314
2315 struct aac_query_disk
2316 {
2317         s32     cnum;
2318         s32     bus;
2319         s32     id;
2320         s32     lun;
2321         u32     valid;
2322         u32     locked;
2323         u32     deleted;
2324         s32     instance;
2325         s8      name[10];
2326         u32     unmapped;
2327 };
2328
2329 struct aac_delete_disk {
2330         u32     disknum;
2331         u32     cnum;
2332 };
2333
2334 struct fib_ioctl
2335 {
2336         u32     fibctx;
2337         s32     wait;
2338         char    __user *fib;
2339 };
2340
2341 struct revision
2342 {
2343         u32 compat;
2344         __le32 version;
2345         __le32 build;
2346 };
2347
2348
2349 /*
2350  *      Ugly - non Linux like ioctl coding for back compat.
2351  */
2352
2353 #define CTL_CODE(function, method) (                 \
2354     (4<< 16) | ((function) << 2) | (method) \
2355 )
2356
2357 /*
2358  *      Define the method codes for how buffers are passed for I/O and FS
2359  *      controls
2360  */
2361
2362 #define METHOD_BUFFERED                 0
2363 #define METHOD_NEITHER                  3
2364
2365 /*
2366  *      Filesystem ioctls
2367  */
2368
2369 #define FSACTL_SENDFIB                          CTL_CODE(2050, METHOD_BUFFERED)
2370 #define FSACTL_SEND_RAW_SRB                     CTL_CODE(2067, METHOD_BUFFERED)
2371 #define FSACTL_DELETE_DISK                      0x163
2372 #define FSACTL_QUERY_DISK                       0x173
2373 #define FSACTL_OPEN_GET_ADAPTER_FIB             CTL_CODE(2100, METHOD_BUFFERED)
2374 #define FSACTL_GET_NEXT_ADAPTER_FIB             CTL_CODE(2101, METHOD_BUFFERED)
2375 #define FSACTL_CLOSE_GET_ADAPTER_FIB            CTL_CODE(2102, METHOD_BUFFERED)
2376 #define FSACTL_MINIPORT_REV_CHECK               CTL_CODE(2107, METHOD_BUFFERED)
2377 #define FSACTL_GET_PCI_INFO                     CTL_CODE(2119, METHOD_BUFFERED)
2378 #define FSACTL_FORCE_DELETE_DISK                CTL_CODE(2120, METHOD_NEITHER)
2379 #define FSACTL_GET_CONTAINERS                   2131
2380 #define FSACTL_SEND_LARGE_FIB                   CTL_CODE(2138, METHOD_BUFFERED)
2381 #define FSACTL_RESET_IOP                        CTL_CODE(2140, METHOD_BUFFERED)
2382 #define FSACTL_GET_HBA_INFO                     CTL_CODE(2150, METHOD_BUFFERED)
2383 /* flags defined for IOP & HW SOFT RESET */
2384 #define HW_IOP_RESET                            0x01
2385 #define HW_SOFT_RESET                           0x02
2386 #define IOP_HWSOFT_RESET                        (HW_IOP_RESET | HW_SOFT_RESET)
2387 /* HW Soft Reset register offset */
2388 #define IBW_SWR_OFFSET                          0x4000
2389 #define SOFT_RESET_TIME                 60
2390
2391
2392
2393 struct aac_common
2394 {
2395         /*
2396          *      If this value is set to 1 then interrupt moderation will occur
2397          *      in the base commuication support.
2398          */
2399         u32 irq_mod;
2400         u32 peak_fibs;
2401         u32 zero_fibs;
2402         u32 fib_timeouts;
2403         /*
2404          *      Statistical counters in debug mode
2405          */
2406 #ifdef DBG
2407         u32 FibsSent;
2408         u32 FibRecved;
2409         u32 NativeSent;
2410         u32 NativeRecved;
2411         u32 NoResponseSent;
2412         u32 NoResponseRecved;
2413         u32 AsyncSent;
2414         u32 AsyncRecved;
2415         u32 NormalSent;
2416         u32 NormalRecved;
2417 #endif
2418 };
2419
2420 extern struct aac_common aac_config;
2421
2422 /*
2423  * This is for management ioctl purpose only.
2424  */
2425 struct aac_hba_info {
2426
2427         u8      driver_name[50];
2428         u8      adapter_number;
2429         u8      system_io_bus_number;
2430         u8      device_number;
2431         u32     function_number;
2432         u32     vendor_id;
2433         u32     device_id;
2434         u32     sub_vendor_id;
2435         u32     sub_system_id;
2436         u32     mapped_base_address_size;
2437         u32     base_physical_address_high_part;
2438         u32     base_physical_address_low_part;
2439
2440         u32     max_command_size;
2441         u32     max_fib_size;
2442         u32     max_scatter_gather_from_os;
2443         u32     max_scatter_gather_to_fw;
2444         u32     max_outstanding_fibs;
2445
2446         u32     queue_start_threshold;
2447         u32     queue_dump_threshold;
2448         u32     max_io_size_queued;
2449         u32     outstanding_io;
2450
2451         u32     firmware_build_number;
2452         u32     bios_build_number;
2453         u32     driver_build_number;
2454         u32     serial_number_high_part;
2455         u32     serial_number_low_part;
2456         u32     supported_options;
2457         u32     feature_bits;
2458         u32     currentnumber_ports;
2459
2460         u8      new_comm_interface:1;
2461         u8      new_commands_supported:1;
2462         u8      disable_passthrough:1;
2463         u8      expose_non_dasd:1;
2464         u8      queue_allowed:1;
2465         u8      bled_check_enabled:1;
2466         u8      reserved1:1;
2467         u8      reserted2:1;
2468
2469         u32     reserved3[10];
2470
2471 };
2472
2473 /*
2474  *      The following macro is used when sending and receiving FIBs. It is
2475  *      only used for debugging.
2476  */
2477
2478 #ifdef DBG
2479 #define FIB_COUNTER_INCREMENT(counter)          (counter)++
2480 #else
2481 #define FIB_COUNTER_INCREMENT(counter)
2482 #endif
2483
2484 /*
2485  *      Adapter direct commands
2486  *      Monitor/Kernel API
2487  */
2488
2489 #define BREAKPOINT_REQUEST              0x00000004
2490 #define INIT_STRUCT_BASE_ADDRESS        0x00000005
2491 #define READ_PERMANENT_PARAMETERS       0x0000000a
2492 #define WRITE_PERMANENT_PARAMETERS      0x0000000b
2493 #define HOST_CRASHING                   0x0000000d
2494 #define SEND_SYNCHRONOUS_FIB            0x0000000c
2495 #define COMMAND_POST_RESULTS            0x00000014
2496 #define GET_ADAPTER_PROPERTIES          0x00000019
2497 #define GET_DRIVER_BUFFER_PROPERTIES    0x00000023
2498 #define RCV_TEMP_READINGS               0x00000025
2499 #define GET_COMM_PREFERRED_SETTINGS     0x00000026
2500 #define IOP_RESET_FW_FIB_DUMP           0x00000034
2501 #define DROP_IO                 0x00000035
2502 #define IOP_RESET                       0x00001000
2503 #define IOP_RESET_ALWAYS                0x00001001
2504 #define RE_INIT_ADAPTER         0x000000ee
2505
2506 #define IOP_SRC_RESET_MASK              0x00000100
2507
2508 /*
2509  *      Adapter Status Register
2510  *
2511  *  Phase Staus mailbox is 32bits:
2512  *      <31:16> = Phase Status
2513  *      <15:0>  = Phase
2514  *
2515  *      The adapter reports is present state through the phase.  Only
2516  *      a single phase should be ever be set.  Each phase can have multiple
2517  *      phase status bits to provide more detailed information about the
2518  *      state of the board.  Care should be taken to ensure that any phase
2519  *      status bits that are set when changing the phase are also valid
2520  *      for the new phase or be cleared out.  Adapter software (monitor,
2521  *      iflash, kernel) is responsible for properly maintining the phase
2522  *      status mailbox when it is running.
2523  *
2524  *      MONKER_API Phases
2525  *
2526  *      Phases are bit oriented.  It is NOT valid  to have multiple bits set
2527  */
2528
2529 #define SELF_TEST_FAILED                0x00000004
2530 #define MONITOR_PANIC                   0x00000020
2531 #define KERNEL_BOOTING                  0x00000040
2532 #define KERNEL_UP_AND_RUNNING           0x00000080
2533 #define KERNEL_PANIC                    0x00000100
2534 #define FLASH_UPD_PENDING               0x00002000
2535 #define FLASH_UPD_SUCCESS               0x00004000
2536 #define FLASH_UPD_FAILED                0x00008000
2537 #define INVALID_OMR                     0xffffffff
2538 #define FWUPD_TIMEOUT                   (5 * 60)
2539
2540 /*
2541  *      Doorbell bit defines
2542  */
2543
2544 #define DoorBellSyncCmdAvailable        (1<<0)  /* Host -> Adapter */
2545 #define DoorBellPrintfDone              (1<<5)  /* Host -> Adapter */
2546 #define DoorBellAdapterNormCmdReady     (1<<1)  /* Adapter -> Host */
2547 #define DoorBellAdapterNormRespReady    (1<<2)  /* Adapter -> Host */
2548 #define DoorBellAdapterNormCmdNotFull   (1<<3)  /* Adapter -> Host */
2549 #define DoorBellAdapterNormRespNotFull  (1<<4)  /* Adapter -> Host */
2550 #define DoorBellPrintfReady             (1<<5)  /* Adapter -> Host */
2551 #define DoorBellAifPending              (1<<6)  /* Adapter -> Host */
2552
2553 /* PMC specific outbound doorbell bits */
2554 #define PmDoorBellResponseSent          (1<<1)  /* Adapter -> Host */
2555
2556 /*
2557  *      For FIB communication, we need all of the following things
2558  *      to send back to the user.
2559  */
2560
2561 #define         AifCmdEventNotify       1       /* Notify of event */
2562 #define                 AifEnConfigChange       3       /* Adapter configuration change */
2563 #define                 AifEnContainerChange    4       /* Container configuration change */
2564 #define                 AifEnDeviceFailure      5       /* SCSI device failed */
2565 #define                 AifEnEnclosureManagement 13     /* EM_DRIVE_* */
2566 #define                         EM_DRIVE_INSERTION      31
2567 #define                         EM_DRIVE_REMOVAL        32
2568 #define                 EM_SES_DRIVE_INSERTION  33
2569 #define                 EM_SES_DRIVE_REMOVAL    26
2570 #define                 AifEnBatteryEvent       14      /* Change in Battery State */
2571 #define                 AifEnAddContainer       15      /* A new array was created */
2572 #define                 AifEnDeleteContainer    16      /* A container was deleted */
2573 #define                 AifEnExpEvent           23      /* Firmware Event Log */
2574 #define                 AifExeFirmwarePanic     3       /* Firmware Event Panic */
2575 #define                 AifHighPriority         3       /* Highest Priority Event */
2576 #define                 AifEnAddJBOD            30      /* JBOD created */
2577 #define                 AifEnDeleteJBOD         31      /* JBOD deleted */
2578
2579 #define                 AifBuManagerEvent               42 /* Bu management*/
2580 #define                 AifBuCacheDataLoss              10
2581 #define                 AifBuCacheDataRecover   11
2582
2583 #define         AifCmdJobProgress       2       /* Progress report */
2584 #define                 AifJobCtrZero   101     /* Array Zero progress */
2585 #define                 AifJobStsSuccess 1      /* Job completes */
2586 #define                 AifJobStsRunning 102    /* Job running */
2587 #define         AifCmdAPIReport         3       /* Report from other user of API */
2588 #define         AifCmdDriverNotify      4       /* Notify host driver of event */
2589 #define                 AifDenMorphComplete 200 /* A morph operation completed */
2590 #define                 AifDenVolumeExtendComplete 201 /* A volume extend completed */
2591 #define         AifReqJobList           100     /* Gets back complete job list */
2592 #define         AifReqJobsForCtr        101     /* Gets back jobs for specific container */
2593 #define         AifReqJobsForScsi       102     /* Gets back jobs for specific SCSI device */
2594 #define         AifReqJobReport         103     /* Gets back a specific job report or list of them */
2595 #define         AifReqTerminateJob      104     /* Terminates job */
2596 #define         AifReqSuspendJob        105     /* Suspends a job */
2597 #define         AifReqResumeJob         106     /* Resumes a job */
2598 #define         AifReqSendAPIReport     107     /* API generic report requests */
2599 #define         AifReqAPIJobStart       108     /* Start a job from the API */
2600 #define         AifReqAPIJobUpdate      109     /* Update a job report from the API */
2601 #define         AifReqAPIJobFinish      110     /* Finish a job from the API */
2602
2603 /* PMC NEW COMM: Request the event data */
2604 #define         AifReqEvent             200
2605 #define         AifRawDeviceRemove      203     /* RAW device deleted */
2606 #define         AifNativeDeviceAdd      204     /* native HBA device added */
2607 #define         AifNativeDeviceRemove   205     /* native HBA device removed */
2608
2609
2610 /*
2611  *      Adapter Initiated FIB command structures. Start with the adapter
2612  *      initiated FIBs that really come from the adapter, and get responded
2613  *      to by the host.
2614  */
2615
2616 struct aac_aifcmd {
2617         __le32 command;         /* Tell host what type of notify this is */
2618         __le32 seqnum;          /* To allow ordering of reports (if necessary) */
2619         u8 data[1];             /* Undefined length (from kernel viewpoint) */
2620 };
2621
2622 /**
2623  *      Convert capacity to cylinders
2624  *      accounting for the fact capacity could be a 64 bit value
2625  *
2626  */
2627 static inline unsigned int cap_to_cyls(sector_t capacity, unsigned divisor)
2628 {
2629         sector_div(capacity, divisor);
2630         return capacity;
2631 }
2632
2633 static inline int aac_pci_offline(struct aac_dev *dev)
2634 {
2635         return pci_channel_offline(dev->pdev) || dev->handle_pci_error;
2636 }
2637
2638 static inline int aac_adapter_check_health(struct aac_dev *dev)
2639 {
2640         if (unlikely(aac_pci_offline(dev)))
2641                 return -1;
2642
2643         return (dev)->a_ops.adapter_check_health(dev);
2644 }
2645
2646
2647 int aac_scan_host(struct aac_dev *dev);
2648
2649 static inline void aac_schedule_safw_scan_worker(struct aac_dev *dev)
2650 {
2651         schedule_delayed_work(&dev->safw_rescan_work, AAC_RESCAN_DELAY);
2652 }
2653
2654 static inline void aac_schedule_src_reinit_aif_worker(struct aac_dev *dev)
2655 {
2656         schedule_delayed_work(&dev->src_reinit_aif_worker, AAC_RESCAN_DELAY);
2657 }
2658
2659 static inline void aac_safw_rescan_worker(struct work_struct *work)
2660 {
2661         struct aac_dev *dev = container_of(to_delayed_work(work),
2662                 struct aac_dev, safw_rescan_work);
2663
2664         wait_event(dev->scsi_host_ptr->host_wait,
2665                 !scsi_host_in_recovery(dev->scsi_host_ptr));
2666
2667         aac_scan_host(dev);
2668 }
2669
2670 static inline void aac_cancel_rescan_worker(struct aac_dev *dev)
2671 {
2672         cancel_delayed_work_sync(&dev->safw_rescan_work);
2673         cancel_delayed_work_sync(&dev->src_reinit_aif_worker);
2674 }
2675
2676 /* SCp.phase values */
2677 #define AAC_OWNER_MIDLEVEL      0x101
2678 #define AAC_OWNER_LOWLEVEL      0x102
2679 #define AAC_OWNER_ERROR_HANDLER 0x103
2680 #define AAC_OWNER_FIRMWARE      0x106
2681
2682 void aac_safw_rescan_worker(struct work_struct *work);
2683 void aac_src_reinit_aif_worker(struct work_struct *work);
2684 int aac_acquire_irq(struct aac_dev *dev);
2685 void aac_free_irq(struct aac_dev *dev);
2686 int aac_setup_safw_adapter(struct aac_dev *dev);
2687 const char *aac_driverinfo(struct Scsi_Host *);
2688 void aac_fib_vector_assign(struct aac_dev *dev);
2689 struct fib *aac_fib_alloc(struct aac_dev *dev);
2690 struct fib *aac_fib_alloc_tag(struct aac_dev *dev, struct scsi_cmnd *scmd);
2691 int aac_fib_setup(struct aac_dev *dev);
2692 void aac_fib_map_free(struct aac_dev *dev);
2693 void aac_fib_free(struct fib * context);
2694 void aac_fib_init(struct fib * context);
2695 void aac_printf(struct aac_dev *dev, u32 val);
2696 int aac_fib_send(u16 command, struct fib * context, unsigned long size, int priority, int wait, int reply, fib_callback callback, void *ctxt);
2697 int aac_hba_send(u8 command, struct fib *context,
2698                 fib_callback callback, void *ctxt);
2699 int aac_consumer_get(struct aac_dev * dev, struct aac_queue * q, struct aac_entry **entry);
2700 void aac_consumer_free(struct aac_dev * dev, struct aac_queue * q, u32 qnum);
2701 int aac_fib_complete(struct fib * context);
2702 void aac_hba_callback(void *context, struct fib *fibptr);
2703 #define fib_data(fibctx) ((void *)(fibctx)->hw_fib_va->data)
2704 struct aac_dev *aac_init_adapter(struct aac_dev *dev);
2705 void aac_src_access_devreg(struct aac_dev *dev, int mode);
2706 void aac_set_intx_mode(struct aac_dev *dev);
2707 int aac_get_config_status(struct aac_dev *dev, int commit_flag);
2708 int aac_get_containers(struct aac_dev *dev);
2709 int aac_scsi_cmd(struct scsi_cmnd *cmd);
2710 int aac_dev_ioctl(struct aac_dev *dev, unsigned int cmd, void __user *arg);
2711 #ifndef shost_to_class
2712 #define shost_to_class(shost) &shost->shost_dev
2713 #endif
2714 ssize_t aac_get_serial_number(struct device *dev, char *buf);
2715 int aac_do_ioctl(struct aac_dev *dev, unsigned int cmd, void __user *arg);
2716 int aac_rx_init(struct aac_dev *dev);
2717 int aac_rkt_init(struct aac_dev *dev);
2718 int aac_nark_init(struct aac_dev *dev);
2719 int aac_sa_init(struct aac_dev *dev);
2720 int aac_src_init(struct aac_dev *dev);
2721 int aac_srcv_init(struct aac_dev *dev);
2722 int aac_queue_get(struct aac_dev * dev, u32 * index, u32 qid, struct hw_fib * hw_fib, int wait, struct fib * fibptr, unsigned long *nonotify);
2723 void aac_define_int_mode(struct aac_dev *dev);
2724 unsigned int aac_response_normal(struct aac_queue * q);
2725 unsigned int aac_command_normal(struct aac_queue * q);
2726 unsigned int aac_intr_normal(struct aac_dev *dev, u32 Index,
2727                         int isAif, int isFastResponse,
2728                         struct hw_fib *aif_fib);
2729 int aac_reset_adapter(struct aac_dev *dev, int forced, u8 reset_type);
2730 int aac_check_health(struct aac_dev * dev);
2731 int aac_command_thread(void *data);
2732 int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context *fibctx);
2733 int aac_fib_adapter_complete(struct fib * fibptr, unsigned short size);
2734 struct aac_driver_ident* aac_get_driver_ident(int devtype);
2735 int aac_get_adapter_info(struct aac_dev* dev);
2736 int aac_send_shutdown(struct aac_dev *dev);
2737 int aac_probe_container(struct aac_dev *dev, int cid);
2738 int _aac_rx_init(struct aac_dev *dev);
2739 int aac_rx_select_comm(struct aac_dev *dev, int comm);
2740 int aac_rx_deliver_producer(struct fib * fib);
2741 void aac_reinit_aif(struct aac_dev *aac, unsigned int index);
2742
2743 static inline int aac_is_src(struct aac_dev *dev)
2744 {
2745         u16 device = dev->pdev->device;
2746
2747         if (device == PMC_DEVICE_S6 ||
2748                 device == PMC_DEVICE_S7 ||
2749                 device == PMC_DEVICE_S8)
2750                 return 1;
2751         return 0;
2752 }
2753
2754 static inline int aac_supports_2T(struct aac_dev *dev)
2755 {
2756         return (dev->adapter_info.options & AAC_OPT_NEW_COMM_64);
2757 }
2758
2759 char * get_container_type(unsigned type);
2760 extern int numacb;
2761 extern char aac_driver_version[];
2762 extern int startup_timeout;
2763 extern int aif_timeout;
2764 extern int expose_physicals;
2765 extern int aac_reset_devices;
2766 extern int aac_msi;
2767 extern int aac_commit;
2768 extern int update_interval;
2769 extern int check_interval;
2770 extern int aac_check_reset;
2771 extern int aac_fib_dump;
2772 #endif