drivers/rtc/rtc-sun6i.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * An RTC driver for Allwinner A31/A23
   4  *
   5  * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org>
   6  *
   7  * based on rtc-sunxi.c
   8  *
   9  * An RTC driver for Allwinner A10/A20
  10  *
  11  * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/delay.h>
  17 #include <linux/err.h>
  18 #include <linux/fs.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/of.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/rtc.h>
  29 #include <linux/slab.h>
  30 #include <linux/types.h>
  31
  32 /* Control register */
  33 #define SUN6I_LOSC_CTRL                         0x0000
  34 #define SUN6I_LOSC_CTRL_KEY                     (0x16aa << 16)
  35 #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS         BIT(15)
  36 #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC            BIT(9)
  37 #define SUN6I_LOSC_CTRL_RTC_HMS_ACC             BIT(8)
  38 #define SUN6I_LOSC_CTRL_RTC_YMD_ACC             BIT(7)
  39 #define SUN6I_LOSC_CTRL_EXT_LOSC_EN             BIT(4)
  40 #define SUN6I_LOSC_CTRL_EXT_OSC                 BIT(0)
  41 #define SUN6I_LOSC_CTRL_ACC_MASK                GENMASK(9, 7)
  42
  43 #define SUN6I_LOSC_CLK_PRESCAL                  0x0008
  44
  45 /* RTC */
  46 #define SUN6I_RTC_YMD                           0x0010
  47 #define SUN6I_RTC_HMS                           0x0014
  48
  49 /* Alarm 0 (counter) */
  50 #define SUN6I_ALRM_COUNTER                      0x0020
  51 #define SUN6I_ALRM_CUR_VAL                      0x0024
  52 #define SUN6I_ALRM_EN                           0x0028
  53 #define SUN6I_ALRM_EN_CNT_EN                    BIT(0)
  54 #define SUN6I_ALRM_IRQ_EN                       0x002c
  55 #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN            BIT(0)
  56 #define SUN6I_ALRM_IRQ_STA                      0x0030
  57 #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND         BIT(0)
  58
  59 /* Alarm 1 (wall clock) */
  60 #define SUN6I_ALRM1_EN                          0x0044
  61 #define SUN6I_ALRM1_IRQ_EN                      0x0048
  62 #define SUN6I_ALRM1_IRQ_STA                     0x004c
  63 #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND       BIT(0)
  64
  65 /* Alarm config */
  66 #define SUN6I_ALARM_CONFIG                      0x0050
  67 #define SUN6I_ALARM_CONFIG_WAKEUP               BIT(0)
  68
  69 #define SUN6I_LOSC_OUT_GATING                   0x0060
  70 #define SUN6I_LOSC_OUT_GATING_EN_OFFSET         0
  71
  72 /*
  73  * Get date values
  74  */
  75 #define SUN6I_DATE_GET_DAY_VALUE(x)             ((x)  & 0x0000001f)
  76 #define SUN6I_DATE_GET_MON_VALUE(x)             (((x) & 0x00000f00) >> 8)
  77 #define SUN6I_DATE_GET_YEAR_VALUE(x)            (((x) & 0x003f0000) >> 16)
  78 #define SUN6I_LEAP_GET_VALUE(x)                 (((x) & 0x00400000) >> 22)
  79
  80 /*
  81  * Get time values
  82  */
  83 #define SUN6I_TIME_GET_SEC_VALUE(x)             ((x)  & 0x0000003f)
  84 #define SUN6I_TIME_GET_MIN_VALUE(x)             (((x) & 0x00003f00) >> 8)
  85 #define SUN6I_TIME_GET_HOUR_VALUE(x)            (((x) & 0x001f0000) >> 16)
  86
  87 /*
  88  * Set date values
  89  */
  90 #define SUN6I_DATE_SET_DAY_VALUE(x)             ((x)       & 0x0000001f)
  91 #define SUN6I_DATE_SET_MON_VALUE(x)             ((x) <<  8 & 0x00000f00)
  92 #define SUN6I_DATE_SET_YEAR_VALUE(x)            ((x) << 16 & 0x003f0000)
  93 #define SUN6I_LEAP_SET_VALUE(x)                 ((x) << 22 & 0x00400000)
  94
  95 /*
  96  * Set time values
  97  */
  98 #define SUN6I_TIME_SET_SEC_VALUE(x)             ((x)       & 0x0000003f)
  99 #define SUN6I_TIME_SET_MIN_VALUE(x)             ((x) <<  8 & 0x00003f00)
 100 #define SUN6I_TIME_SET_HOUR_VALUE(x)            ((x) << 16 & 0x001f0000)
 101
 102 /*
 103  * The year parameter passed to the driver is usually an offset relative to
 104  * the year 1900. This macro is used to convert this offset to another one
 105  * relative to the minimum year allowed by the hardware.
 106  *
 107  * The year range is 1970 - 2033. This range is selected to match Allwinner's
 108  * driver, even though it is somewhat limited.
 109  */
 110 #define SUN6I_YEAR_MIN                          1970
 111 #define SUN6I_YEAR_OFF                          (SUN6I_YEAR_MIN - 1900)
 112
 113 /*
 114  * There are other differences between models, including:
 115  *
 116  *   - number of GPIO pins that can be configured to hold a certain level
 117  *   - crypto-key related registers (H5, H6)
 118  *   - boot process related (super standby, secondary processor entry address)
 119  *     registers (R40, H6)
 120  *   - SYS power domain controls (R40)
 121  *   - DCXO controls (H6)
 122  *   - RC oscillator calibration (H6)
 123  *
 124  * These functions are not covered by this driver.
 125  */
 126 struct sun6i_rtc_clk_data {
 127         unsigned long rc_osc_rate;
 128         unsigned int fixed_prescaler : 16;
 129         unsigned int has_prescaler : 1;
 130         unsigned int has_out_clk : 1;
 131         unsigned int export_iosc : 1;
 132         unsigned int has_losc_en : 1;
 133         unsigned int has_auto_swt : 1;
 134 };
 135
 136 struct sun6i_rtc_dev {
 137         struct rtc_device *rtc;
 138         const struct sun6i_rtc_clk_data *data;
 139         void __iomem *base;
 140         int irq;
 141         unsigned long alarm;
 142
 143         struct clk_hw hw;
 144         struct clk_hw *int_osc;
 145         struct clk *losc;
 146         struct clk *ext_losc;
 147
 148         spinlock_t lock;
 149 };
 150
 151 static struct sun6i_rtc_dev *sun6i_rtc;
 152
 153 static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw,
 154                                                unsigned long parent_rate)
 155 {
 156         struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
 157         u32 val = 0;
 158
 159         val = readl(rtc->base + SUN6I_LOSC_CTRL);
 160         if (val & SUN6I_LOSC_CTRL_EXT_OSC)
 161                 return parent_rate;
 162
 163         if (rtc->data->fixed_prescaler)
 164                 parent_rate /= rtc->data->fixed_prescaler;
 165
 166         if (rtc->data->has_prescaler) {
 167                 val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL);
 168                 val &= GENMASK(4, 0);
 169         }
 170
 171         return parent_rate / (val + 1);
 172 }
 173
 174 static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw)
 175 {
 176         struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
 177
 178         return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC;
 179 }
 180
 181 static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index)
 182 {
 183         struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
 184         unsigned long flags;
 185         u32 val;
 186
 187         if (index > 1)
 188                 return -EINVAL;
 189
 190         spin_lock_irqsave(&rtc->lock, flags);
 191         val = readl(rtc->base + SUN6I_LOSC_CTRL);
 192         val &= ~SUN6I_LOSC_CTRL_EXT_OSC;
 193         val |= SUN6I_LOSC_CTRL_KEY;
 194         val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0;
 195         if (rtc->data->has_losc_en) {
 196                 val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN;
 197                 val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0;
 198         }
 199         writel(val, rtc->base + SUN6I_LOSC_CTRL);
 200         spin_unlock_irqrestore(&rtc->lock, flags);
 201
 202         return 0;
 203 }
 204
 205 static const struct clk_ops sun6i_rtc_osc_ops = {
 206         .recalc_rate    = sun6i_rtc_osc_recalc_rate,
 207
 208         .get_parent     = sun6i_rtc_osc_get_parent,
 209         .set_parent     = sun6i_rtc_osc_set_parent,
 210 };
 211
 212 static void __init sun6i_rtc_clk_init(struct device_node *node,
 213                                       const struct sun6i_rtc_clk_data *data)
 214 {
 215         struct clk_hw_onecell_data *clk_data;
 216         struct sun6i_rtc_dev *rtc;
 217         struct clk_init_data init = {
 218                 .ops            = &sun6i_rtc_osc_ops,
 219                 .name           = "losc",
 220         };
 221         const char *iosc_name = "rtc-int-osc";
 222         const char *clkout_name = "osc32k-out";
 223         const char *parents[2];
 224         u32 reg;
 225
 226         rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
 227         if (!rtc)
 228                 return;
 229
 230         rtc->data = data;
 231         clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL);
 232         if (!clk_data) {
 233                 kfree(rtc);
 234                 return;
 235         }
 236
 237         spin_lock_init(&rtc->lock);
 238
 239         rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node));
 240         if (IS_ERR(rtc->base)) {
 241                 pr_crit("Can't map RTC registers");
 242                 goto err;
 243         }
 244
 245         reg = SUN6I_LOSC_CTRL_KEY;
 246         if (rtc->data->has_auto_swt) {
 247                 /* Bypass auto-switch to int osc, on ext losc failure */
 248                 reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS;
 249                 writel(reg, rtc->base + SUN6I_LOSC_CTRL);
 250         }
 251
 252         /* Switch to the external, more precise, oscillator, if present */
 253         if (of_get_property(node, "clocks", NULL)) {
 254                 reg |= SUN6I_LOSC_CTRL_EXT_OSC;
 255                 if (rtc->data->has_losc_en)
 256                         reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN;
 257         }
 258         writel(reg, rtc->base + SUN6I_LOSC_CTRL);
 259
 260         /* Yes, I know, this is ugly. */
 261         sun6i_rtc = rtc;
 262
 263         /* Only read IOSC name from device tree if it is exported */
 264         if (rtc->data->export_iosc)
 265                 of_property_read_string_index(node, "clock-output-names", 2,
 266                                               &iosc_name);
 267
 268         rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL,
 269                                                                 iosc_name,
 270                                                                 NULL, 0,
 271                                                                 rtc->data->rc_osc_rate,
 272                                                                 300000000);
 273         if (IS_ERR(rtc->int_osc)) {
 274                 pr_crit("Couldn't register the internal oscillator\n");
 275                 return;
 276         }
 277
 278         parents[0] = clk_hw_get_name(rtc->int_osc);
 279         /* If there is no external oscillator, this will be NULL and ... */
 280         parents[1] = of_clk_get_parent_name(node, 0);
 281
 282         rtc->hw.init = &init;
 283
 284         init.parent_names = parents;
 285         /* ... number of clock parents will be 1. */
 286         init.num_parents = of_clk_get_parent_count(node) + 1;
 287         of_property_read_string_index(node, "clock-output-names", 0,
 288                                       &init.name);
 289
 290         rtc->losc = clk_register(NULL, &rtc->hw);
 291         if (IS_ERR(rtc->losc)) {
 292                 pr_crit("Couldn't register the LOSC clock\n");
 293                 return;
 294         }
 295
 296         of_property_read_string_index(node, "clock-output-names", 1,
 297                                       &clkout_name);
 298         rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name,
 299                                           0, rtc->base + SUN6I_LOSC_OUT_GATING,
 300                                           SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0,
 301                                           &rtc->lock);
 302         if (IS_ERR(rtc->ext_losc)) {
 303                 pr_crit("Couldn't register the LOSC external gate\n");
 304                 return;
 305         }
 306
 307         clk_data->num = 2;
 308         clk_data->hws[0] = &rtc->hw;
 309         clk_data->hws[1] = __clk_get_hw(rtc->ext_losc);
 310         if (rtc->data->export_iosc) {
 311                 clk_data->hws[2] = rtc->int_osc;
 312                 clk_data->num = 3;
 313         }
 314         of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 315         return;
 316
 317 err:
 318         kfree(clk_data);
 319 }
 320
 321 static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = {
 322         .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
 323         .has_prescaler = 1,
 324 };
 325
 326 static void __init sun6i_a31_rtc_clk_init(struct device_node *node)
 327 {
 328         sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data);
 329 }
 330 CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc",
 331                       sun6i_a31_rtc_clk_init);
 332
 333 static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = {
 334         .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
 335         .has_prescaler = 1,
 336         .has_out_clk = 1,
 337 };
 338
 339 static void __init sun8i_a23_rtc_clk_init(struct device_node *node)
 340 {
 341         sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data);
 342 }
 343 CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc",
 344                       sun8i_a23_rtc_clk_init);
 345
 346 static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = {
 347         .rc_osc_rate = 16000000,
 348         .fixed_prescaler = 32,
 349         .has_prescaler = 1,
 350         .has_out_clk = 1,
 351         .export_iosc = 1,
 352 };
 353
 354 static void __init sun8i_h3_rtc_clk_init(struct device_node *node)
 355 {
 356         sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data);
 357 }
 358 CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc",
 359                       sun8i_h3_rtc_clk_init);
 360 /* As far as we are concerned, clocks for H5 are the same as H3 */
 361 CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc",
 362                       sun8i_h3_rtc_clk_init);
 363
 364 static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = {
 365         .rc_osc_rate = 16000000,
 366         .fixed_prescaler = 32,
 367         .has_prescaler = 1,
 368         .has_out_clk = 1,
 369         .export_iosc = 1,
 370         .has_losc_en = 1,
 371         .has_auto_swt = 1,
 372 };
 373
 374 static void __init sun50i_h6_rtc_clk_init(struct device_node *node)
 375 {
 376         sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data);
 377 }
 378 CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc",
 379                       sun50i_h6_rtc_clk_init);
 380
 381 /*
 382  * The R40 user manual is self-conflicting on whether the prescaler is
 383  * fixed or configurable. The clock diagram shows it as fixed, but there
 384  * is also a configurable divider in the RTC block.
 385  */
 386 static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = {
 387         .rc_osc_rate = 16000000,
 388         .fixed_prescaler = 512,
 389 };
 390 static void __init sun8i_r40_rtc_clk_init(struct device_node *node)
 391 {
 392         sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data);
 393 }
 394 CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc",
 395                       sun8i_r40_rtc_clk_init);
 396
 397 static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = {
 398         .rc_osc_rate = 32000,
 399         .has_out_clk = 1,
 400 };
 401
 402 static void __init sun8i_v3_rtc_clk_init(struct device_node *node)
 403 {
 404         sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data);
 405 }
 406 CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc",
 407                       sun8i_v3_rtc_clk_init);
 408
 409 static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id)
 410 {
 411         struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id;
 412         irqreturn_t ret = IRQ_NONE;
 413         u32 val;
 414
 415         spin_lock(&chip->lock);
 416         val = readl(chip->base + SUN6I_ALRM_IRQ_STA);
 417
 418         if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) {
 419                 val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND;
 420                 writel(val, chip->base + SUN6I_ALRM_IRQ_STA);
 421
 422                 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
 423
 424                 ret = IRQ_HANDLED;
 425         }
 426         spin_unlock(&chip->lock);
 427
 428         return ret;
 429 }
 430
 431 static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip)
 432 {
 433         u32 alrm_val = 0;
 434         u32 alrm_irq_val = 0;
 435         u32 alrm_wake_val = 0;
 436         unsigned long flags;
 437
 438         if (to) {
 439                 alrm_val = SUN6I_ALRM_EN_CNT_EN;
 440                 alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN;
 441                 alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP;
 442         } else {
 443                 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
 444                        chip->base + SUN6I_ALRM_IRQ_STA);
 445         }
 446
 447         spin_lock_irqsave(&chip->lock, flags);
 448         writel(alrm_val, chip->base + SUN6I_ALRM_EN);
 449         writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN);
 450         writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG);
 451         spin_unlock_irqrestore(&chip->lock, flags);
 452 }
 453
 454 static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
 455 {
 456         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 457         u32 date, time;
 458
 459         /*
 460          * read again in case it changes
 461          */
 462         do {
 463                 date = readl(chip->base + SUN6I_RTC_YMD);
 464                 time = readl(chip->base + SUN6I_RTC_HMS);
 465         } while ((date != readl(chip->base + SUN6I_RTC_YMD)) ||
 466                  (time != readl(chip->base + SUN6I_RTC_HMS)));
 467
 468         rtc_tm->tm_sec  = SUN6I_TIME_GET_SEC_VALUE(time);
 469         rtc_tm->tm_min  = SUN6I_TIME_GET_MIN_VALUE(time);
 470         rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time);
 471
 472         rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);
 473         rtc_tm->tm_mon  = SUN6I_DATE_GET_MON_VALUE(date);
 474         rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date);
 475
 476         rtc_tm->tm_mon  -= 1;
 477
 478         /*
 479          * switch from (data_year->min)-relative offset to
 480          * a (1900)-relative one
 481          */
 482         rtc_tm->tm_year += SUN6I_YEAR_OFF;
 483
 484         return 0;
 485 }
 486
 487 static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
 488 {
 489         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 490         unsigned long flags;
 491         u32 alrm_st;
 492         u32 alrm_en;
 493
 494         spin_lock_irqsave(&chip->lock, flags);
 495         alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN);
 496         alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA);
 497         spin_unlock_irqrestore(&chip->lock, flags);
 498
 499         wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN);
 500         wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN);
 501         rtc_time64_to_tm(chip->alarm, &wkalrm->time);
 502
 503         return 0;
 504 }
 505
 506 static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
 507 {
 508         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 509         struct rtc_time *alrm_tm = &wkalrm->time;
 510         struct rtc_time tm_now;
 511         unsigned long time_now = 0;
 512         unsigned long time_set = 0;
 513         unsigned long time_gap = 0;
 514         int ret = 0;
 515
 516         ret = sun6i_rtc_gettime(dev, &tm_now);
 517         if (ret < 0) {
 518                 dev_err(dev, "Error in getting time\n");
 519                 return -EINVAL;
 520         }
 521
 522         time_set = rtc_tm_to_time64(alrm_tm);
 523         time_now = rtc_tm_to_time64(&tm_now);
 524         if (time_set <= time_now) {
 525                 dev_err(dev, "Date to set in the past\n");
 526                 return -EINVAL;
 527         }
 528
 529         time_gap = time_set - time_now;
 530
 531         if (time_gap > U32_MAX) {
 532                 dev_err(dev, "Date too far in the future\n");
 533                 return -EINVAL;
 534         }
 535
 536         sun6i_rtc_setaie(0, chip);
 537         writel(0, chip->base + SUN6I_ALRM_COUNTER);
 538         usleep_range(100, 300);
 539
 540         writel(time_gap, chip->base + SUN6I_ALRM_COUNTER);
 541         chip->alarm = time_set;
 542
 543         sun6i_rtc_setaie(wkalrm->enabled, chip);
 544
 545         return 0;
 546 }
 547
 548 static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset,
 549                           unsigned int mask, unsigned int ms_timeout)
 550 {
 551         const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
 552         u32 reg;
 553
 554         do {
 555                 reg = readl(chip->base + offset);
 556                 reg &= mask;
 557
 558                 if (!reg)
 559                         return 0;
 560
 561         } while (time_before(jiffies, timeout));
 562
 563         return -ETIMEDOUT;
 564 }
 565
 566 static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
 567 {
 568         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 569         u32 date = 0;
 570         u32 time = 0;
 571
 572         rtc_tm->tm_year -= SUN6I_YEAR_OFF;
 573         rtc_tm->tm_mon += 1;
 574
 575         date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
 576                 SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon)  |
 577                 SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);
 578
 579         if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN))
 580                 date |= SUN6I_LEAP_SET_VALUE(1);
 581
 582         time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec)  |
 583                 SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min)  |
 584                 SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
 585
 586         /* Check whether registers are writable */
 587         if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
 588                            SUN6I_LOSC_CTRL_ACC_MASK, 50)) {
 589                 dev_err(dev, "rtc is still busy.\n");
 590                 return -EBUSY;
 591         }
 592
 593         writel(time, chip->base + SUN6I_RTC_HMS);
 594
 595         /*
 596          * After writing the RTC HH-MM-SS register, the
 597          * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
 598          * be cleared until the real writing operation is finished
 599          */
 600
 601         if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
 602                            SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) {
 603                 dev_err(dev, "Failed to set rtc time.\n");
 604                 return -ETIMEDOUT;
 605         }
 606
 607         writel(date, chip->base + SUN6I_RTC_YMD);
 608
 609         /*
 610          * After writing the RTC YY-MM-DD register, the
 611          * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
 612          * be cleared until the real writing operation is finished
 613          */
 614
 615         if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
 616                            SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) {
 617                 dev_err(dev, "Failed to set rtc time.\n");
 618                 return -ETIMEDOUT;
 619         }
 620
 621         return 0;
 622 }
 623
 624 static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 625 {
 626         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 627
 628         if (!enabled)
 629                 sun6i_rtc_setaie(enabled, chip);
 630
 631         return 0;
 632 }
 633
 634 static const struct rtc_class_ops sun6i_rtc_ops = {
 635         .read_time              = sun6i_rtc_gettime,
 636         .set_time               = sun6i_rtc_settime,
 637         .read_alarm             = sun6i_rtc_getalarm,
 638         .set_alarm              = sun6i_rtc_setalarm,
 639         .alarm_irq_enable       = sun6i_rtc_alarm_irq_enable
 640 };
 641
 642 #ifdef CONFIG_PM_SLEEP
 643 /* Enable IRQ wake on suspend, to wake up from RTC. */
 644 static int sun6i_rtc_suspend(struct device *dev)
 645 {
 646         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 647
 648         if (device_may_wakeup(dev))
 649                 enable_irq_wake(chip->irq);
 650
 651         return 0;
 652 }
 653
 654 /* Disable IRQ wake on resume. */
 655 static int sun6i_rtc_resume(struct device *dev)
 656 {
 657         struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
 658
 659         if (device_may_wakeup(dev))
 660                 disable_irq_wake(chip->irq);
 661
 662         return 0;
 663 }
 664 #endif
 665
 666 static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops,
 667         sun6i_rtc_suspend, sun6i_rtc_resume);
 668
 669 static int sun6i_rtc_probe(struct platform_device *pdev)
 670 {
 671         struct sun6i_rtc_dev *chip = sun6i_rtc;
 672         int ret;
 673
 674         if (!chip)
 675                 return -ENODEV;
 676
 677         platform_set_drvdata(pdev, chip);
 678
 679         chip->irq = platform_get_irq(pdev, 0);
 680         if (chip->irq < 0)
 681                 return chip->irq;
 682
 683         ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq,
 684                                0, dev_name(&pdev->dev), chip);
 685         if (ret) {
 686                 dev_err(&pdev->dev, "Could not request IRQ\n");
 687                 return ret;
 688         }
 689
 690         /* clear the alarm counter value */
 691         writel(0, chip->base + SUN6I_ALRM_COUNTER);
 692
 693         /* disable counter alarm */
 694         writel(0, chip->base + SUN6I_ALRM_EN);
 695
 696         /* disable counter alarm interrupt */
 697         writel(0, chip->base + SUN6I_ALRM_IRQ_EN);
 698
 699         /* disable week alarm */
 700         writel(0, chip->base + SUN6I_ALRM1_EN);
 701
 702         /* disable week alarm interrupt */
 703         writel(0, chip->base + SUN6I_ALRM1_IRQ_EN);
 704
 705         /* clear counter alarm pending interrupts */
 706         writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
 707                chip->base + SUN6I_ALRM_IRQ_STA);
 708
 709         /* clear week alarm pending interrupts */
 710         writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND,
 711                chip->base + SUN6I_ALRM1_IRQ_STA);
 712
 713         /* disable alarm wakeup */
 714         writel(0, chip->base + SUN6I_ALARM_CONFIG);
 715
 716         clk_prepare_enable(chip->losc);
 717
 718         device_init_wakeup(&pdev->dev, 1);
 719
 720         chip->rtc = devm_rtc_allocate_device(&pdev->dev);
 721         if (IS_ERR(chip->rtc))
 722                 return PTR_ERR(chip->rtc);
 723
 724         chip->rtc->ops = &sun6i_rtc_ops;
 725         chip->rtc->range_max = 2019686399LL; /* 2033-12-31 23:59:59 */
 726
 727         ret = rtc_register_device(chip->rtc);
 728         if (ret)
 729                 return ret;
 730
 731         dev_info(&pdev->dev, "RTC enabled\n");
 732
 733         return 0;
 734 }
 735
 736 /*
 737  * As far as RTC functionality goes, all models are the same. The
 738  * datasheets claim that different models have different number of
 739  * registers available for non-volatile storage, but experiments show
 740  * that all SoCs have 16 registers available for this purpose.
 741  */
 742 static const struct of_device_id sun6i_rtc_dt_ids[] = {
 743         { .compatible = "allwinner,sun6i-a31-rtc" },
 744         { .compatible = "allwinner,sun8i-a23-rtc" },
 745         { .compatible = "allwinner,sun8i-h3-rtc" },
 746         { .compatible = "allwinner,sun8i-r40-rtc" },
 747         { .compatible = "allwinner,sun8i-v3-rtc" },
 748         { .compatible = "allwinner,sun50i-h5-rtc" },
 749         { .compatible = "allwinner,sun50i-h6-rtc" },
 750         { /* sentinel */ },
 751 };
 752 MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
 753
 754 static struct platform_driver sun6i_rtc_driver = {
 755         .probe          = sun6i_rtc_probe,
 756         .driver         = {
 757                 .name           = "sun6i-rtc",
 758                 .of_match_table = sun6i_rtc_dt_ids,
 759                 .pm = &sun6i_rtc_pm_ops,
 760         },
 761 };
 762 builtin_platform_driver(sun6i_rtc_driver);