1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale STMP37XX/STMP378X Real Time Clock driver
5 * Copyright (c) 2007 Sigmatel, Inc.
6 * Peter Hartley, <peter.hartley@sigmatel.com>
8 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
9 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
10 * Copyright 2011 Wolfram Sang, Pengutronix e.K.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/platform_device.h>
17 #include <linux/interrupt.h>
18 #include <linux/delay.h>
19 #include <linux/rtc.h>
20 #include <linux/slab.h>
21 #include <linux/of_device.h>
23 #include <linux/stmp_device.h>
24 #include <linux/stmp3xxx_rtc_wdt.h>
26 #define STMP3XXX_RTC_CTRL 0x0
27 #define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN 0x00000001
28 #define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
29 #define STMP3XXX_RTC_CTRL_ALARM_IRQ 0x00000004
30 #define STMP3XXX_RTC_CTRL_WATCHDOGEN 0x00000010
32 #define STMP3XXX_RTC_STAT 0x10
33 #define STMP3XXX_RTC_STAT_STALE_SHIFT 16
34 #define STMP3XXX_RTC_STAT_RTC_PRESENT 0x80000000
35 #define STMP3XXX_RTC_STAT_XTAL32000_PRESENT 0x10000000
36 #define STMP3XXX_RTC_STAT_XTAL32768_PRESENT 0x08000000
38 #define STMP3XXX_RTC_SECONDS 0x30
40 #define STMP3XXX_RTC_ALARM 0x40
42 #define STMP3XXX_RTC_WATCHDOG 0x50
44 #define STMP3XXX_RTC_PERSISTENT0 0x60
45 #define STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE (1 << 0)
46 #define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1)
47 #define STMP3XXX_RTC_PERSISTENT0_ALARM_EN (1 << 2)
48 #define STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP (1 << 4)
49 #define STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5)
50 #define STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ (1 << 6)
51 #define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE (1 << 7)
53 #define STMP3XXX_RTC_PERSISTENT1 0x70
54 /* missing bitmask in headers */
55 #define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER 0x80000000
57 struct stmp3xxx_rtc_data {
58 struct rtc_device *rtc;
63 #if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG)
65 * stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC
66 * @dev: the parent device of the watchdog (= the RTC)
67 * @timeout: the desired value for the timeout register of the watchdog.
68 * 0 disables the watchdog
70 * The watchdog needs one register and two bits which are in the RTC domain.
71 * To handle the resource conflict, the RTC driver will create another
72 * platform_device for the watchdog driver as a child of the RTC device.
73 * The watchdog driver is passed the below accessor function via platform_data
74 * to configure the watchdog. Locking is not needed because accessing SET/CLR
75 * registers is atomic.
78 static void stmp3xxx_wdt_set_timeout(struct device *dev, u32 timeout)
80 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
83 writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG);
84 writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
85 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
86 writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
87 rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET);
89 writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
90 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
91 writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
92 rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
96 static struct stmp3xxx_wdt_pdata wdt_pdata = {
97 .wdt_set_timeout = stmp3xxx_wdt_set_timeout,
100 static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
103 struct platform_device *wdt_pdev =
104 platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id);
107 wdt_pdev->dev.parent = &rtc_pdev->dev;
108 wdt_pdev->dev.platform_data = &wdt_pdata;
109 rc = platform_device_add(wdt_pdev);
113 dev_err(&rtc_pdev->dev,
114 "failed to register stmp3xxx_rtc_wdt\n");
117 static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
120 #endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */
122 static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data)
124 int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */
126 * The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
128 * | The order in which registers are updated is
129 * | Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds.
130 * | (This list is in bitfield order, from LSB to MSB, as they would
131 * | appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT
132 * | register. For example, the Seconds register corresponds to
133 * | STALE_REGS or NEW_REGS containing 0x80.)
136 if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) &
137 (0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)))
140 } while (--timeout > 0);
141 return (readl(rtc_data->io + STMP3XXX_RTC_STAT) &
142 (0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0;
145 /* Time read/write */
146 static int stmp3xxx_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
149 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
151 ret = stmp3xxx_wait_time(rtc_data);
155 rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_SECONDS), rtc_tm);
159 static int stmp3xxx_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
161 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
163 writel(rtc_tm_to_time64(rtc_tm), rtc_data->io + STMP3XXX_RTC_SECONDS);
164 return stmp3xxx_wait_time(rtc_data);
167 /* interrupt(s) handler */
168 static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
170 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev_id);
171 u32 status = readl(rtc_data->io + STMP3XXX_RTC_CTRL);
173 if (status & STMP3XXX_RTC_CTRL_ALARM_IRQ) {
174 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ,
175 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
176 rtc_update_irq(rtc_data->rtc, 1, RTC_AF | RTC_IRQF);
183 static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled)
185 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
188 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
189 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
190 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
191 STMP_OFFSET_REG_SET);
192 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
193 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
195 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
196 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
197 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
198 STMP_OFFSET_REG_CLR);
199 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
200 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
205 static int stmp3xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
207 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
209 rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time);
213 static int stmp3xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
215 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
217 writel(rtc_tm_to_time64(&alm->time), rtc_data->io + STMP3XXX_RTC_ALARM);
219 stmp3xxx_alarm_irq_enable(dev, alm->enabled);
224 static const struct rtc_class_ops stmp3xxx_rtc_ops = {
226 stmp3xxx_alarm_irq_enable,
227 .read_time = stmp3xxx_rtc_gettime,
228 .set_time = stmp3xxx_rtc_settime,
229 .read_alarm = stmp3xxx_rtc_read_alarm,
230 .set_alarm = stmp3xxx_rtc_set_alarm,
233 static int stmp3xxx_rtc_remove(struct platform_device *pdev)
235 struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(pdev);
240 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
241 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
246 static int stmp3xxx_rtc_probe(struct platform_device *pdev)
248 struct stmp3xxx_rtc_data *rtc_data;
251 u32 pers0_set, pers0_clr;
255 rtc_data = devm_kzalloc(&pdev->dev, sizeof(*rtc_data), GFP_KERNEL);
259 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
261 dev_err(&pdev->dev, "failed to get resource\n");
265 rtc_data->io = devm_ioremap(&pdev->dev, r->start, resource_size(r));
267 dev_err(&pdev->dev, "ioremap failed\n");
271 rtc_data->irq_alarm = platform_get_irq(pdev, 0);
273 rtc_stat = readl(rtc_data->io + STMP3XXX_RTC_STAT);
274 if (!(rtc_stat & STMP3XXX_RTC_STAT_RTC_PRESENT)) {
275 dev_err(&pdev->dev, "no device onboard\n");
279 platform_set_drvdata(pdev, rtc_data);
282 * Resetting the rtc stops the watchdog timer that is potentially
283 * running. So (assuming it is running on purpose) don't reset if the
284 * watchdog is enabled.
286 if (readl(rtc_data->io + STMP3XXX_RTC_CTRL) &
287 STMP3XXX_RTC_CTRL_WATCHDOGEN) {
289 "Watchdog is running, skip resetting rtc\n");
291 err = stmp_reset_block(rtc_data->io);
293 dev_err(&pdev->dev, "stmp_reset_block failed: %d\n",
300 * Obviously the rtc needs a clock input to be able to run.
301 * This clock can be provided by an external 32k crystal. If that one is
302 * missing XTAL must not be disabled in suspend which consumes a
303 * lot of power. Normally the presence and exact frequency (supported
304 * are 32000 Hz and 32768 Hz) is detectable from fuses, but as reality
305 * proves these fuses are not blown correctly on all machines, so the
306 * frequency can be overridden in the device tree.
308 if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32000_PRESENT)
310 else if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32768_PRESENT)
313 of_property_read_u32(pdev->dev.of_node, "stmp,crystal-freq",
316 switch (crystalfreq) {
318 /* keep 32kHz crystal running in low-power mode */
319 pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ |
320 STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
321 STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
322 pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
325 /* keep 32.768kHz crystal running in low-power mode */
326 pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
327 STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
328 pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP |
329 STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ;
333 "invalid crystal-freq specified in device-tree. Assuming no crystal\n");
336 /* keep XTAL on in low-power mode */
337 pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
338 pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
339 STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
342 writel(pers0_set, rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
343 STMP_OFFSET_REG_SET);
345 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
346 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
347 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE | pers0_clr,
348 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
350 writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN |
351 STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
352 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
354 rtc_data->rtc = devm_rtc_allocate_device(&pdev->dev);
355 if (IS_ERR(rtc_data->rtc))
356 return PTR_ERR(rtc_data->rtc);
358 err = devm_request_irq(&pdev->dev, rtc_data->irq_alarm,
359 stmp3xxx_rtc_interrupt, 0, "RTC alarm", &pdev->dev);
361 dev_err(&pdev->dev, "Cannot claim IRQ%d\n",
362 rtc_data->irq_alarm);
366 rtc_data->rtc->ops = &stmp3xxx_rtc_ops;
367 rtc_data->rtc->range_max = U32_MAX;
369 err = rtc_register_device(rtc_data->rtc);
373 stmp3xxx_wdt_register(pdev);
377 #ifdef CONFIG_PM_SLEEP
378 static int stmp3xxx_rtc_suspend(struct device *dev)
383 static int stmp3xxx_rtc_resume(struct device *dev)
385 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
387 stmp_reset_block(rtc_data->io);
388 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
389 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
390 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
391 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
396 static SIMPLE_DEV_PM_OPS(stmp3xxx_rtc_pm_ops, stmp3xxx_rtc_suspend,
397 stmp3xxx_rtc_resume);
399 static const struct of_device_id rtc_dt_ids[] = {
400 { .compatible = "fsl,stmp3xxx-rtc", },
403 MODULE_DEVICE_TABLE(of, rtc_dt_ids);
405 static struct platform_driver stmp3xxx_rtcdrv = {
406 .probe = stmp3xxx_rtc_probe,
407 .remove = stmp3xxx_rtc_remove,
409 .name = "stmp3xxx-rtc",
410 .pm = &stmp3xxx_rtc_pm_ops,
411 .of_match_table = rtc_dt_ids,
415 module_platform_driver(stmp3xxx_rtcdrv);
417 MODULE_DESCRIPTION("STMP3xxx RTC Driver");
418 MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com> and "
419 "Wolfram Sang <kernel@pengutronix.de>");
420 MODULE_LICENSE("GPL");