1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
5 #include <linux/module.h>
6 #include <linux/init.h>
8 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
11 #include <linux/slab.h>
12 #include <linux/spinlock.h>
14 /* RTC Register offsets from RTC CTRL REG */
15 #define PM8XXX_ALARM_CTRL_OFFSET 0x01
16 #define PM8XXX_RTC_WRITE_OFFSET 0x02
17 #define PM8XXX_RTC_READ_OFFSET 0x06
18 #define PM8XXX_ALARM_RW_OFFSET 0x0A
20 /* RTC_CTRL register bit fields */
21 #define PM8xxx_RTC_ENABLE BIT(7)
22 #define PM8xxx_RTC_ALARM_CLEAR BIT(0)
24 #define NUM_8_BIT_RTC_REGS 0x4
27 * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
28 * @ctrl: base address of control register
29 * @write: base address of write register
30 * @read: base address of read register
31 * @alarm_ctrl: base address of alarm control register
32 * @alarm_ctrl2: base address of alarm control2 register
33 * @alarm_rw: base address of alarm read-write register
34 * @alarm_en: alarm enable mask
36 struct pm8xxx_rtc_regs {
40 unsigned int alarm_ctrl;
41 unsigned int alarm_ctrl2;
42 unsigned int alarm_rw;
43 unsigned int alarm_en;
47 * struct pm8xxx_rtc - rtc driver internal structure
48 * @rtc: rtc device for this driver.
49 * @regmap: regmap used to access RTC registers
50 * @allow_set_time: indicates whether writing to the RTC is allowed
51 * @rtc_alarm_irq: rtc alarm irq number.
52 * @regs: rtc registers description.
53 * @rtc_dev: device structure.
54 * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
57 struct rtc_device *rtc;
58 struct regmap *regmap;
61 const struct pm8xxx_rtc_regs *regs;
62 struct device *rtc_dev;
63 spinlock_t ctrl_reg_lock;
67 * Steps to write the RTC registers.
68 * 1. Disable alarm if enabled.
69 * 2. Disable rtc if enabled.
70 * 3. Write 0x00 to LSB.
71 * 4. Write Byte[1], Byte[2], Byte[3] then Byte[0].
72 * 5. Enable rtc if disabled in step 2.
73 * 6. Enable alarm if disabled in step 1.
75 static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
78 unsigned long secs, irq_flags;
79 u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, rtc_disabled = 0;
80 unsigned int ctrl_reg, rtc_ctrl_reg;
81 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
82 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
84 if (!rtc_dd->allow_set_time)
87 secs = rtc_tm_to_time64(tm);
89 dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
91 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
92 value[i] = secs & 0xFF;
96 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
98 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
102 if (ctrl_reg & regs->alarm_en) {
104 ctrl_reg &= ~regs->alarm_en;
105 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
107 dev_err(dev, "Write to RTC Alarm control register failed\n");
112 /* Disable RTC H/w before writing on RTC register */
113 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &rtc_ctrl_reg);
117 if (rtc_ctrl_reg & PM8xxx_RTC_ENABLE) {
119 rtc_ctrl_reg &= ~PM8xxx_RTC_ENABLE;
120 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
122 dev_err(dev, "Write to RTC control register failed\n");
127 /* Write 0 to Byte[0] */
128 rc = regmap_write(rtc_dd->regmap, regs->write, 0);
130 dev_err(dev, "Write to RTC write data register failed\n");
134 /* Write Byte[1], Byte[2], Byte[3] */
135 rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
136 &value[1], sizeof(value) - 1);
138 dev_err(dev, "Write to RTC write data register failed\n");
143 rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
145 dev_err(dev, "Write to RTC write data register failed\n");
149 /* Enable RTC H/w after writing on RTC register */
151 rtc_ctrl_reg |= PM8xxx_RTC_ENABLE;
152 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
154 dev_err(dev, "Write to RTC control register failed\n");
160 ctrl_reg |= regs->alarm_en;
161 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
163 dev_err(dev, "Write to RTC Alarm control register failed\n");
169 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
174 static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
177 u8 value[NUM_8_BIT_RTC_REGS];
180 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
181 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
183 rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
185 dev_err(dev, "RTC read data register failed\n");
190 * Read the LSB again and check if there has been a carry over.
191 * If there is, redo the read operation.
193 rc = regmap_read(rtc_dd->regmap, regs->read, ®);
195 dev_err(dev, "RTC read data register failed\n");
199 if (unlikely(reg < value[0])) {
200 rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
201 value, sizeof(value));
203 dev_err(dev, "RTC read data register failed\n");
208 secs = value[0] | (value[1] << 8) | (value[2] << 16) |
209 ((unsigned long)value[3] << 24);
211 rtc_time64_to_tm(secs, tm);
213 dev_dbg(dev, "secs = %lu, h:m:s == %ptRt, y-m-d = %ptRdr\n", secs, tm, tm);
218 static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
221 u8 value[NUM_8_BIT_RTC_REGS];
222 unsigned int ctrl_reg;
223 unsigned long secs, irq_flags;
224 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
225 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
227 secs = rtc_tm_to_time64(&alarm->time);
229 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
230 value[i] = secs & 0xFF;
234 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
236 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
239 dev_err(dev, "Write to RTC ALARM register failed\n");
243 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
248 ctrl_reg |= regs->alarm_en;
250 ctrl_reg &= ~regs->alarm_en;
252 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
254 dev_err(dev, "Write to RTC alarm control register failed\n");
258 dev_dbg(dev, "Alarm Set for h:m:s=%ptRt, y-m-d=%ptRdr\n",
259 &alarm->time, &alarm->time);
261 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
265 static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
268 u8 value[NUM_8_BIT_RTC_REGS];
270 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
271 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
273 rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
276 dev_err(dev, "RTC alarm time read failed\n");
280 secs = value[0] | (value[1] << 8) | (value[2] << 16) |
281 ((unsigned long)value[3] << 24);
283 rtc_time64_to_tm(secs, &alarm->time);
285 dev_dbg(dev, "Alarm set for - h:m:s=%ptRt, y-m-d=%ptRdr\n",
286 &alarm->time, &alarm->time);
291 static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
294 unsigned long irq_flags;
295 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
296 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
297 unsigned int ctrl_reg;
298 u8 value[NUM_8_BIT_RTC_REGS] = {0};
300 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
302 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
307 ctrl_reg |= regs->alarm_en;
309 ctrl_reg &= ~regs->alarm_en;
311 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
313 dev_err(dev, "Write to RTC control register failed\n");
317 /* Clear Alarm register */
319 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
322 dev_err(dev, "Clear RTC ALARM register failed\n");
328 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
332 static const struct rtc_class_ops pm8xxx_rtc_ops = {
333 .read_time = pm8xxx_rtc_read_time,
334 .set_time = pm8xxx_rtc_set_time,
335 .set_alarm = pm8xxx_rtc_set_alarm,
336 .read_alarm = pm8xxx_rtc_read_alarm,
337 .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
340 static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
342 struct pm8xxx_rtc *rtc_dd = dev_id;
343 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
344 unsigned int ctrl_reg;
346 unsigned long irq_flags;
348 rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
350 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
352 /* Clear the alarm enable bit */
353 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
355 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
356 goto rtc_alarm_handled;
359 ctrl_reg &= ~regs->alarm_en;
361 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
363 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
364 dev_err(rtc_dd->rtc_dev,
365 "Write to alarm control register failed\n");
366 goto rtc_alarm_handled;
369 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
371 /* Clear RTC alarm register */
372 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
374 dev_err(rtc_dd->rtc_dev,
375 "RTC Alarm control2 register read failed\n");
376 goto rtc_alarm_handled;
379 ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
380 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
382 dev_err(rtc_dd->rtc_dev,
383 "Write to RTC Alarm control2 register failed\n");
389 static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
391 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
392 unsigned int ctrl_reg;
395 /* Check if the RTC is on, else turn it on */
396 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
400 if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
401 ctrl_reg |= PM8xxx_RTC_ENABLE;
402 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
410 static const struct pm8xxx_rtc_regs pm8921_regs = {
416 .alarm_ctrl2 = 0x11e,
420 static const struct pm8xxx_rtc_regs pm8058_regs = {
426 .alarm_ctrl2 = 0x1e9,
430 static const struct pm8xxx_rtc_regs pm8941_regs = {
435 .alarm_ctrl = 0x6146,
436 .alarm_ctrl2 = 0x6148,
441 * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
443 static const struct of_device_id pm8xxx_id_table[] = {
444 { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
445 { .compatible = "qcom,pm8018-rtc", .data = &pm8921_regs },
446 { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
447 { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
450 MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
452 static int pm8xxx_rtc_probe(struct platform_device *pdev)
455 struct pm8xxx_rtc *rtc_dd;
456 const struct of_device_id *match;
458 match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
462 rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
466 /* Initialise spinlock to protect RTC control register */
467 spin_lock_init(&rtc_dd->ctrl_reg_lock);
469 rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
470 if (!rtc_dd->regmap) {
471 dev_err(&pdev->dev, "Parent regmap unavailable.\n");
475 rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
476 if (rtc_dd->rtc_alarm_irq < 0)
479 rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
482 rtc_dd->regs = match->data;
483 rtc_dd->rtc_dev = &pdev->dev;
485 rc = pm8xxx_rtc_enable(rtc_dd);
489 platform_set_drvdata(pdev, rtc_dd);
491 device_init_wakeup(&pdev->dev, 1);
493 /* Register the RTC device */
494 rtc_dd->rtc = devm_rtc_allocate_device(&pdev->dev);
495 if (IS_ERR(rtc_dd->rtc))
496 return PTR_ERR(rtc_dd->rtc);
498 rtc_dd->rtc->ops = &pm8xxx_rtc_ops;
499 rtc_dd->rtc->range_max = U32_MAX;
501 /* Request the alarm IRQ */
502 rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
503 pm8xxx_alarm_trigger,
505 "pm8xxx_rtc_alarm", rtc_dd);
507 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
511 return rtc_register_device(rtc_dd->rtc);
514 #ifdef CONFIG_PM_SLEEP
515 static int pm8xxx_rtc_resume(struct device *dev)
517 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
519 if (device_may_wakeup(dev))
520 disable_irq_wake(rtc_dd->rtc_alarm_irq);
525 static int pm8xxx_rtc_suspend(struct device *dev)
527 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
529 if (device_may_wakeup(dev))
530 enable_irq_wake(rtc_dd->rtc_alarm_irq);
536 static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops,
540 static struct platform_driver pm8xxx_rtc_driver = {
541 .probe = pm8xxx_rtc_probe,
543 .name = "rtc-pm8xxx",
544 .pm = &pm8xxx_rtc_pm_ops,
545 .of_match_table = pm8xxx_id_table,
549 module_platform_driver(pm8xxx_rtc_driver);
551 MODULE_ALIAS("platform:rtc-pm8xxx");
552 MODULE_DESCRIPTION("PMIC8xxx RTC driver");
553 MODULE_LICENSE("GPL v2");
554 MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");