Merge remote-tracking branch 'origin/chrome-platform-5.7-fixes' into for-kernelci
[linux-2.6-microblaze.git] / drivers / rtc / rtc-omap.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * TI OMAP Real Time Clock interface for Linux
4  *
5  * Copyright (C) 2003 MontaVista Software, Inc.
6  * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
7  *
8  * Copyright (C) 2006 David Brownell (new RTC framework)
9  * Copyright (C) 2014 Johan Hovold <johan@kernel.org>
10  */
11
12 #include <linux/bcd.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/ioport.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/rtc.h>
28
29 /*
30  * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock
31  * with century-range alarm matching, driven by the 32kHz clock.
32  *
33  * The main user-visible ways it differs from PC RTCs are by omitting
34  * "don't care" alarm fields and sub-second periodic IRQs, and having
35  * an autoadjust mechanism to calibrate to the true oscillator rate.
36  *
37  * Board-specific wiring options include using split power mode with
38  * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
39  * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
40  * low power modes) for OMAP1 boards (OMAP-L138 has this built into
41  * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
42  */
43
44 /* RTC registers */
45 #define OMAP_RTC_SECONDS_REG            0x00
46 #define OMAP_RTC_MINUTES_REG            0x04
47 #define OMAP_RTC_HOURS_REG              0x08
48 #define OMAP_RTC_DAYS_REG               0x0C
49 #define OMAP_RTC_MONTHS_REG             0x10
50 #define OMAP_RTC_YEARS_REG              0x14
51 #define OMAP_RTC_WEEKS_REG              0x18
52
53 #define OMAP_RTC_ALARM_SECONDS_REG      0x20
54 #define OMAP_RTC_ALARM_MINUTES_REG      0x24
55 #define OMAP_RTC_ALARM_HOURS_REG        0x28
56 #define OMAP_RTC_ALARM_DAYS_REG         0x2c
57 #define OMAP_RTC_ALARM_MONTHS_REG       0x30
58 #define OMAP_RTC_ALARM_YEARS_REG        0x34
59
60 #define OMAP_RTC_CTRL_REG               0x40
61 #define OMAP_RTC_STATUS_REG             0x44
62 #define OMAP_RTC_INTERRUPTS_REG         0x48
63
64 #define OMAP_RTC_COMP_LSB_REG           0x4c
65 #define OMAP_RTC_COMP_MSB_REG           0x50
66 #define OMAP_RTC_OSC_REG                0x54
67
68 #define OMAP_RTC_SCRATCH0_REG           0x60
69 #define OMAP_RTC_SCRATCH1_REG           0x64
70 #define OMAP_RTC_SCRATCH2_REG           0x68
71
72 #define OMAP_RTC_KICK0_REG              0x6c
73 #define OMAP_RTC_KICK1_REG              0x70
74
75 #define OMAP_RTC_IRQWAKEEN              0x7c
76
77 #define OMAP_RTC_ALARM2_SECONDS_REG     0x80
78 #define OMAP_RTC_ALARM2_MINUTES_REG     0x84
79 #define OMAP_RTC_ALARM2_HOURS_REG       0x88
80 #define OMAP_RTC_ALARM2_DAYS_REG        0x8c
81 #define OMAP_RTC_ALARM2_MONTHS_REG      0x90
82 #define OMAP_RTC_ALARM2_YEARS_REG       0x94
83
84 #define OMAP_RTC_PMIC_REG               0x98
85
86 /* OMAP_RTC_CTRL_REG bit fields: */
87 #define OMAP_RTC_CTRL_SPLIT             BIT(7)
88 #define OMAP_RTC_CTRL_DISABLE           BIT(6)
89 #define OMAP_RTC_CTRL_SET_32_COUNTER    BIT(5)
90 #define OMAP_RTC_CTRL_TEST              BIT(4)
91 #define OMAP_RTC_CTRL_MODE_12_24        BIT(3)
92 #define OMAP_RTC_CTRL_AUTO_COMP         BIT(2)
93 #define OMAP_RTC_CTRL_ROUND_30S         BIT(1)
94 #define OMAP_RTC_CTRL_STOP              BIT(0)
95
96 /* OMAP_RTC_STATUS_REG bit fields: */
97 #define OMAP_RTC_STATUS_POWER_UP        BIT(7)
98 #define OMAP_RTC_STATUS_ALARM2          BIT(7)
99 #define OMAP_RTC_STATUS_ALARM           BIT(6)
100 #define OMAP_RTC_STATUS_1D_EVENT        BIT(5)
101 #define OMAP_RTC_STATUS_1H_EVENT        BIT(4)
102 #define OMAP_RTC_STATUS_1M_EVENT        BIT(3)
103 #define OMAP_RTC_STATUS_1S_EVENT        BIT(2)
104 #define OMAP_RTC_STATUS_RUN             BIT(1)
105 #define OMAP_RTC_STATUS_BUSY            BIT(0)
106
107 /* OMAP_RTC_INTERRUPTS_REG bit fields: */
108 #define OMAP_RTC_INTERRUPTS_IT_ALARM2   BIT(4)
109 #define OMAP_RTC_INTERRUPTS_IT_ALARM    BIT(3)
110 #define OMAP_RTC_INTERRUPTS_IT_TIMER    BIT(2)
111
112 /* OMAP_RTC_OSC_REG bit fields: */
113 #define OMAP_RTC_OSC_32KCLK_EN          BIT(6)
114 #define OMAP_RTC_OSC_SEL_32KCLK_SRC     BIT(3)
115 #define OMAP_RTC_OSC_OSC32K_GZ_DISABLE  BIT(4)
116
117 /* OMAP_RTC_IRQWAKEEN bit fields: */
118 #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1)
119
120 /* OMAP_RTC_PMIC bit fields: */
121 #define OMAP_RTC_PMIC_POWER_EN_EN       BIT(16)
122 #define OMAP_RTC_PMIC_EXT_WKUP_EN(x)    BIT(x)
123 #define OMAP_RTC_PMIC_EXT_WKUP_POL(x)   BIT(4 + x)
124
125 /* OMAP_RTC_KICKER values */
126 #define KICK0_VALUE                     0x83e70b13
127 #define KICK1_VALUE                     0x95a4f1e0
128
129 struct omap_rtc;
130
131 struct omap_rtc_device_type {
132         bool has_32kclk_en;
133         bool has_irqwakeen;
134         bool has_pmic_mode;
135         bool has_power_up_reset;
136         void (*lock)(struct omap_rtc *rtc);
137         void (*unlock)(struct omap_rtc *rtc);
138 };
139
140 struct omap_rtc {
141         struct rtc_device *rtc;
142         void __iomem *base;
143         struct clk *clk;
144         int irq_alarm;
145         int irq_timer;
146         u8 interrupts_reg;
147         bool is_pmic_controller;
148         bool has_ext_clk;
149         bool is_suspending;
150         const struct omap_rtc_device_type *type;
151         struct pinctrl_dev *pctldev;
152 };
153
154 static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg)
155 {
156         return readb(rtc->base + reg);
157 }
158
159 static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg)
160 {
161         return readl(rtc->base + reg);
162 }
163
164 static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val)
165 {
166         writeb(val, rtc->base + reg);
167 }
168
169 static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val)
170 {
171         writel(val, rtc->base + reg);
172 }
173
174 static void am3352_rtc_unlock(struct omap_rtc *rtc)
175 {
176         rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE);
177         rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE);
178 }
179
180 static void am3352_rtc_lock(struct omap_rtc *rtc)
181 {
182         rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0);
183         rtc_writel(rtc, OMAP_RTC_KICK1_REG, 0);
184 }
185
186 static void default_rtc_unlock(struct omap_rtc *rtc)
187 {
188 }
189
190 static void default_rtc_lock(struct omap_rtc *rtc)
191 {
192 }
193
194 /*
195  * We rely on the rtc framework to handle locking (rtc->ops_lock),
196  * so the only other requirement is that register accesses which
197  * require BUSY to be clear are made with IRQs locally disabled
198  */
199 static void rtc_wait_not_busy(struct omap_rtc *rtc)
200 {
201         int count;
202         u8 status;
203
204         /* BUSY may stay active for 1/32768 second (~30 usec) */
205         for (count = 0; count < 50; count++) {
206                 status = rtc_read(rtc, OMAP_RTC_STATUS_REG);
207                 if (!(status & OMAP_RTC_STATUS_BUSY))
208                         break;
209                 udelay(1);
210         }
211         /* now we have ~15 usec to read/write various registers */
212 }
213
214 static irqreturn_t rtc_irq(int irq, void *dev_id)
215 {
216         struct omap_rtc *rtc = dev_id;
217         unsigned long events = 0;
218         u8 irq_data;
219
220         irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG);
221
222         /* alarm irq? */
223         if (irq_data & OMAP_RTC_STATUS_ALARM) {
224                 rtc->type->unlock(rtc);
225                 rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM);
226                 rtc->type->lock(rtc);
227                 events |= RTC_IRQF | RTC_AF;
228         }
229
230         /* 1/sec periodic/update irq? */
231         if (irq_data & OMAP_RTC_STATUS_1S_EVENT)
232                 events |= RTC_IRQF | RTC_UF;
233
234         rtc_update_irq(rtc->rtc, 1, events);
235
236         return IRQ_HANDLED;
237 }
238
239 static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
240 {
241         struct omap_rtc *rtc = dev_get_drvdata(dev);
242         u8 reg, irqwake_reg = 0;
243
244         local_irq_disable();
245         rtc_wait_not_busy(rtc);
246         reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
247         if (rtc->type->has_irqwakeen)
248                 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
249
250         if (enabled) {
251                 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
252                 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
253         } else {
254                 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
255                 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
256         }
257         rtc_wait_not_busy(rtc);
258         rtc->type->unlock(rtc);
259         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
260         if (rtc->type->has_irqwakeen)
261                 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
262         rtc->type->lock(rtc);
263         local_irq_enable();
264
265         return 0;
266 }
267
268 /* this hardware doesn't support "don't care" alarm fields */
269 static void tm2bcd(struct rtc_time *tm)
270 {
271         tm->tm_sec = bin2bcd(tm->tm_sec);
272         tm->tm_min = bin2bcd(tm->tm_min);
273         tm->tm_hour = bin2bcd(tm->tm_hour);
274         tm->tm_mday = bin2bcd(tm->tm_mday);
275
276         tm->tm_mon = bin2bcd(tm->tm_mon + 1);
277         tm->tm_year = bin2bcd(tm->tm_year - 100);
278 }
279
280 static void bcd2tm(struct rtc_time *tm)
281 {
282         tm->tm_sec = bcd2bin(tm->tm_sec);
283         tm->tm_min = bcd2bin(tm->tm_min);
284         tm->tm_hour = bcd2bin(tm->tm_hour);
285         tm->tm_mday = bcd2bin(tm->tm_mday);
286         tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
287         /* epoch == 1900 */
288         tm->tm_year = bcd2bin(tm->tm_year) + 100;
289 }
290
291 static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm)
292 {
293         tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG);
294         tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG);
295         tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG);
296         tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG);
297         tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG);
298         tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG);
299 }
300
301 static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm)
302 {
303         struct omap_rtc *rtc = dev_get_drvdata(dev);
304
305         /* we don't report wday/yday/isdst ... */
306         local_irq_disable();
307         rtc_wait_not_busy(rtc);
308         omap_rtc_read_time_raw(rtc, tm);
309         local_irq_enable();
310
311         bcd2tm(tm);
312
313         return 0;
314 }
315
316 static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm)
317 {
318         struct omap_rtc *rtc = dev_get_drvdata(dev);
319
320         tm2bcd(tm);
321
322         local_irq_disable();
323         rtc_wait_not_busy(rtc);
324
325         rtc->type->unlock(rtc);
326         rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year);
327         rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon);
328         rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday);
329         rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour);
330         rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min);
331         rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec);
332         rtc->type->lock(rtc);
333
334         local_irq_enable();
335
336         return 0;
337 }
338
339 static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
340 {
341         struct omap_rtc *rtc = dev_get_drvdata(dev);
342         u8 interrupts;
343
344         local_irq_disable();
345         rtc_wait_not_busy(rtc);
346
347         alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG);
348         alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG);
349         alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG);
350         alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG);
351         alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG);
352         alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG);
353
354         local_irq_enable();
355
356         bcd2tm(&alm->time);
357
358         interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
359         alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM);
360
361         return 0;
362 }
363
364 static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
365 {
366         struct omap_rtc *rtc = dev_get_drvdata(dev);
367         u8 reg, irqwake_reg = 0;
368
369         tm2bcd(&alm->time);
370
371         local_irq_disable();
372         rtc_wait_not_busy(rtc);
373
374         rtc->type->unlock(rtc);
375         rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year);
376         rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon);
377         rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday);
378         rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour);
379         rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min);
380         rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec);
381
382         reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
383         if (rtc->type->has_irqwakeen)
384                 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
385
386         if (alm->enabled) {
387                 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
388                 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
389         } else {
390                 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
391                 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
392         }
393         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
394         if (rtc->type->has_irqwakeen)
395                 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
396         rtc->type->lock(rtc);
397
398         local_irq_enable();
399
400         return 0;
401 }
402
403 static struct omap_rtc *omap_rtc_power_off_rtc;
404
405 /**
406  * omap_rtc_power_off_program: Set the pmic power off sequence. The RTC
407  * generates pmic_pwr_enable control, which can be used to control an external
408  * PMIC.
409  */
410 int omap_rtc_power_off_program(struct device *dev)
411 {
412         struct omap_rtc *rtc = omap_rtc_power_off_rtc;
413         struct rtc_time tm;
414         unsigned long now;
415         int seconds;
416         u32 val;
417
418         rtc->type->unlock(rtc);
419         /* enable pmic_power_en control */
420         val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
421         rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN);
422
423 again:
424         /* Clear any existing ALARM2 event */
425         rtc_writel(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM2);
426
427         /* set alarm one second from now */
428         omap_rtc_read_time_raw(rtc, &tm);
429         seconds = tm.tm_sec;
430         bcd2tm(&tm);
431         now = rtc_tm_to_time64(&tm);
432         rtc_time64_to_tm(now + 1, &tm);
433
434         tm2bcd(&tm);
435
436         rtc_wait_not_busy(rtc);
437
438         rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec);
439         rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min);
440         rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour);
441         rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday);
442         rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon);
443         rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year);
444
445         /*
446          * enable ALARM2 interrupt
447          *
448          * NOTE: this fails on AM3352 if rtc_write (writeb) is used
449          */
450         val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
451         rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG,
452                         val | OMAP_RTC_INTERRUPTS_IT_ALARM2);
453
454         /* Retry in case roll over happened before alarm was armed. */
455         if (rtc_read(rtc, OMAP_RTC_SECONDS_REG) != seconds) {
456                 val = rtc_read(rtc, OMAP_RTC_STATUS_REG);
457                 if (!(val & OMAP_RTC_STATUS_ALARM2))
458                         goto again;
459         }
460
461         rtc->type->lock(rtc);
462
463         return 0;
464 }
465 EXPORT_SYMBOL(omap_rtc_power_off_program);
466
467 /*
468  * omap_rtc_poweroff: RTC-controlled power off
469  *
470  * The RTC can be used to control an external PMIC via the pmic_power_en pin,
471  * which can be configured to transition to OFF on ALARM2 events.
472  *
473  * Notes:
474  * The one-second alarm offset is the shortest offset possible as the alarm
475  * registers must be set before the next timer update and the offset
476  * calculation is too heavy for everything to be done within a single access
477  * period (~15 us).
478  *
479  * Called with local interrupts disabled.
480  */
481 static void omap_rtc_power_off(void)
482 {
483         struct rtc_device *rtc = omap_rtc_power_off_rtc->rtc;
484         u32 val;
485
486         omap_rtc_power_off_program(rtc->dev.parent);
487
488         /* Set PMIC power enable and EXT_WAKEUP in case PB power on is used */
489         omap_rtc_power_off_rtc->type->unlock(omap_rtc_power_off_rtc);
490         val = rtc_readl(omap_rtc_power_off_rtc, OMAP_RTC_PMIC_REG);
491         val |= OMAP_RTC_PMIC_POWER_EN_EN | OMAP_RTC_PMIC_EXT_WKUP_POL(0) |
492                         OMAP_RTC_PMIC_EXT_WKUP_EN(0);
493         rtc_writel(omap_rtc_power_off_rtc, OMAP_RTC_PMIC_REG, val);
494         omap_rtc_power_off_rtc->type->lock(omap_rtc_power_off_rtc);
495
496         /*
497          * Wait for alarm to trigger (within one second) and external PMIC to
498          * power off the system. Add a 500 ms margin for external latencies
499          * (e.g. debounce circuits).
500          */
501         mdelay(1500);
502 }
503
504 static const struct rtc_class_ops omap_rtc_ops = {
505         .read_time      = omap_rtc_read_time,
506         .set_time       = omap_rtc_set_time,
507         .read_alarm     = omap_rtc_read_alarm,
508         .set_alarm      = omap_rtc_set_alarm,
509         .alarm_irq_enable = omap_rtc_alarm_irq_enable,
510 };
511
512 static const struct omap_rtc_device_type omap_rtc_default_type = {
513         .has_power_up_reset = true,
514         .lock           = default_rtc_lock,
515         .unlock         = default_rtc_unlock,
516 };
517
518 static const struct omap_rtc_device_type omap_rtc_am3352_type = {
519         .has_32kclk_en  = true,
520         .has_irqwakeen  = true,
521         .has_pmic_mode  = true,
522         .lock           = am3352_rtc_lock,
523         .unlock         = am3352_rtc_unlock,
524 };
525
526 static const struct omap_rtc_device_type omap_rtc_da830_type = {
527         .lock           = am3352_rtc_lock,
528         .unlock         = am3352_rtc_unlock,
529 };
530
531 static const struct platform_device_id omap_rtc_id_table[] = {
532         {
533                 .name   = "omap_rtc",
534                 .driver_data = (kernel_ulong_t)&omap_rtc_default_type,
535         }, {
536                 .name   = "am3352-rtc",
537                 .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type,
538         }, {
539                 .name   = "da830-rtc",
540                 .driver_data = (kernel_ulong_t)&omap_rtc_da830_type,
541         }, {
542                 /* sentinel */
543         }
544 };
545 MODULE_DEVICE_TABLE(platform, omap_rtc_id_table);
546
547 static const struct of_device_id omap_rtc_of_match[] = {
548         {
549                 .compatible     = "ti,am3352-rtc",
550                 .data           = &omap_rtc_am3352_type,
551         }, {
552                 .compatible     = "ti,da830-rtc",
553                 .data           = &omap_rtc_da830_type,
554         }, {
555                 /* sentinel */
556         }
557 };
558 MODULE_DEVICE_TABLE(of, omap_rtc_of_match);
559
560 static const struct pinctrl_pin_desc rtc_pins_desc[] = {
561         PINCTRL_PIN(0, "ext_wakeup0"),
562         PINCTRL_PIN(1, "ext_wakeup1"),
563         PINCTRL_PIN(2, "ext_wakeup2"),
564         PINCTRL_PIN(3, "ext_wakeup3"),
565 };
566
567 static int rtc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
568 {
569         return 0;
570 }
571
572 static const char *rtc_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
573                                         unsigned int group)
574 {
575         return NULL;
576 }
577
578 static const struct pinctrl_ops rtc_pinctrl_ops = {
579         .get_groups_count = rtc_pinctrl_get_groups_count,
580         .get_group_name = rtc_pinctrl_get_group_name,
581         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
582         .dt_free_map = pinconf_generic_dt_free_map,
583 };
584
585 #define PIN_CONFIG_ACTIVE_HIGH          (PIN_CONFIG_END + 1)
586
587 static const struct pinconf_generic_params rtc_params[] = {
588         {"ti,active-high", PIN_CONFIG_ACTIVE_HIGH, 0},
589 };
590
591 #ifdef CONFIG_DEBUG_FS
592 static const struct pin_config_item rtc_conf_items[ARRAY_SIZE(rtc_params)] = {
593         PCONFDUMP(PIN_CONFIG_ACTIVE_HIGH, "input active high", NULL, false),
594 };
595 #endif
596
597 static int rtc_pinconf_get(struct pinctrl_dev *pctldev,
598                         unsigned int pin, unsigned long *config)
599 {
600         struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
601         unsigned int param = pinconf_to_config_param(*config);
602         u32 val;
603         u16 arg = 0;
604
605         val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
606
607         switch (param) {
608         case PIN_CONFIG_INPUT_ENABLE:
609                 if (!(val & OMAP_RTC_PMIC_EXT_WKUP_EN(pin)))
610                         return -EINVAL;
611                 break;
612         case PIN_CONFIG_ACTIVE_HIGH:
613                 if (val & OMAP_RTC_PMIC_EXT_WKUP_POL(pin))
614                         return -EINVAL;
615                 break;
616         default:
617                 return -ENOTSUPP;
618         }
619
620         *config = pinconf_to_config_packed(param, arg);
621
622         return 0;
623 }
624
625 static int rtc_pinconf_set(struct pinctrl_dev *pctldev,
626                         unsigned int pin, unsigned long *configs,
627                         unsigned int num_configs)
628 {
629         struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
630         u32 val;
631         unsigned int param;
632         u32 param_val;
633         int i;
634
635         val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
636
637         /* active low by default */
638         val |= OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
639
640         for (i = 0; i < num_configs; i++) {
641                 param = pinconf_to_config_param(configs[i]);
642                 param_val = pinconf_to_config_argument(configs[i]);
643
644                 switch (param) {
645                 case PIN_CONFIG_INPUT_ENABLE:
646                         if (param_val)
647                                 val |= OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
648                         else
649                                 val &= ~OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
650                         break;
651                 case PIN_CONFIG_ACTIVE_HIGH:
652                         val &= ~OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
653                         break;
654                 default:
655                         dev_err(&rtc->rtc->dev, "Property %u not supported\n",
656                                 param);
657                         return -ENOTSUPP;
658                 }
659         }
660
661         rtc->type->unlock(rtc);
662         rtc_writel(rtc, OMAP_RTC_PMIC_REG, val);
663         rtc->type->lock(rtc);
664
665         return 0;
666 }
667
668 static const struct pinconf_ops rtc_pinconf_ops = {
669         .is_generic = true,
670         .pin_config_get = rtc_pinconf_get,
671         .pin_config_set = rtc_pinconf_set,
672 };
673
674 static struct pinctrl_desc rtc_pinctrl_desc = {
675         .pins = rtc_pins_desc,
676         .npins = ARRAY_SIZE(rtc_pins_desc),
677         .pctlops = &rtc_pinctrl_ops,
678         .confops = &rtc_pinconf_ops,
679         .custom_params = rtc_params,
680         .num_custom_params = ARRAY_SIZE(rtc_params),
681 #ifdef CONFIG_DEBUG_FS
682         .custom_conf_items = rtc_conf_items,
683 #endif
684         .owner = THIS_MODULE,
685 };
686
687 static int omap_rtc_scratch_read(void *priv, unsigned int offset, void *_val,
688                                  size_t bytes)
689 {
690         struct omap_rtc *rtc = priv;
691         u32 *val = _val;
692         int i;
693
694         for (i = 0; i < bytes / 4; i++)
695                 val[i] = rtc_readl(rtc,
696                                    OMAP_RTC_SCRATCH0_REG + offset + (i * 4));
697
698         return 0;
699 }
700
701 static int omap_rtc_scratch_write(void *priv, unsigned int offset, void *_val,
702                                   size_t bytes)
703 {
704         struct omap_rtc *rtc = priv;
705         u32 *val = _val;
706         int i;
707
708         rtc->type->unlock(rtc);
709         for (i = 0; i < bytes / 4; i++)
710                 rtc_writel(rtc,
711                            OMAP_RTC_SCRATCH0_REG + offset + (i * 4), val[i]);
712         rtc->type->lock(rtc);
713
714         return 0;
715 }
716
717 static struct nvmem_config omap_rtc_nvmem_config = {
718         .name = "omap_rtc_scratch",
719         .word_size = 4,
720         .stride = 4,
721         .size = OMAP_RTC_KICK0_REG - OMAP_RTC_SCRATCH0_REG,
722         .reg_read = omap_rtc_scratch_read,
723         .reg_write = omap_rtc_scratch_write,
724 };
725
726 static int omap_rtc_probe(struct platform_device *pdev)
727 {
728         struct omap_rtc *rtc;
729         u8 reg, mask, new_ctrl;
730         const struct platform_device_id *id_entry;
731         const struct of_device_id *of_id;
732         int ret;
733
734         rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
735         if (!rtc)
736                 return -ENOMEM;
737
738         of_id = of_match_device(omap_rtc_of_match, &pdev->dev);
739         if (of_id) {
740                 rtc->type = of_id->data;
741                 rtc->is_pmic_controller = rtc->type->has_pmic_mode &&
742                         of_device_is_system_power_controller(pdev->dev.of_node);
743         } else {
744                 id_entry = platform_get_device_id(pdev);
745                 rtc->type = (void *)id_entry->driver_data;
746         }
747
748         rtc->irq_timer = platform_get_irq(pdev, 0);
749         if (rtc->irq_timer <= 0)
750                 return -ENOENT;
751
752         rtc->irq_alarm = platform_get_irq(pdev, 1);
753         if (rtc->irq_alarm <= 0)
754                 return -ENOENT;
755
756         rtc->clk = devm_clk_get(&pdev->dev, "ext-clk");
757         if (!IS_ERR(rtc->clk))
758                 rtc->has_ext_clk = true;
759         else
760                 rtc->clk = devm_clk_get(&pdev->dev, "int-clk");
761
762         if (!IS_ERR(rtc->clk))
763                 clk_prepare_enable(rtc->clk);
764
765         rtc->base = devm_platform_ioremap_resource(pdev, 0);
766         if (IS_ERR(rtc->base)) {
767                 clk_disable_unprepare(rtc->clk);
768                 return PTR_ERR(rtc->base);
769         }
770
771         platform_set_drvdata(pdev, rtc);
772
773         /* Enable the clock/module so that we can access the registers */
774         pm_runtime_enable(&pdev->dev);
775         pm_runtime_get_sync(&pdev->dev);
776
777         rtc->type->unlock(rtc);
778
779         /*
780          * disable interrupts
781          *
782          * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
783          */
784         rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
785
786         /* enable RTC functional clock */
787         if (rtc->type->has_32kclk_en) {
788                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
789                 rtc_writel(rtc, OMAP_RTC_OSC_REG,
790                                 reg | OMAP_RTC_OSC_32KCLK_EN);
791         }
792
793         /* clear old status */
794         reg = rtc_read(rtc, OMAP_RTC_STATUS_REG);
795
796         mask = OMAP_RTC_STATUS_ALARM;
797
798         if (rtc->type->has_pmic_mode)
799                 mask |= OMAP_RTC_STATUS_ALARM2;
800
801         if (rtc->type->has_power_up_reset) {
802                 mask |= OMAP_RTC_STATUS_POWER_UP;
803                 if (reg & OMAP_RTC_STATUS_POWER_UP)
804                         dev_info(&pdev->dev, "RTC power up reset detected\n");
805         }
806
807         if (reg & mask)
808                 rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask);
809
810         /* On boards with split power, RTC_ON_NOFF won't reset the RTC */
811         reg = rtc_read(rtc, OMAP_RTC_CTRL_REG);
812         if (reg & OMAP_RTC_CTRL_STOP)
813                 dev_info(&pdev->dev, "already running\n");
814
815         /* force to 24 hour mode */
816         new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
817         new_ctrl |= OMAP_RTC_CTRL_STOP;
818
819         /*
820          * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
821          *
822          *  - Device wake-up capability setting should come through chip
823          *    init logic. OMAP1 boards should initialize the "wakeup capable"
824          *    flag in the platform device if the board is wired right for
825          *    being woken up by RTC alarm. For OMAP-L138, this capability
826          *    is built into the SoC by the "Deep Sleep" capability.
827          *
828          *  - Boards wired so RTC_ON_nOFF is used as the reset signal,
829          *    rather than nPWRON_RESET, should forcibly enable split
830          *    power mode.  (Some chip errata report that RTC_CTRL_SPLIT
831          *    is write-only, and always reads as zero...)
832          */
833
834         if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
835                 dev_info(&pdev->dev, "split power mode\n");
836
837         if (reg != new_ctrl)
838                 rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl);
839
840         /*
841          * If we have the external clock then switch to it so we can keep
842          * ticking across suspend.
843          */
844         if (rtc->has_ext_clk) {
845                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
846                 reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE;
847                 reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC;
848                 rtc_writel(rtc, OMAP_RTC_OSC_REG, reg);
849         }
850
851         rtc->type->lock(rtc);
852
853         device_init_wakeup(&pdev->dev, true);
854
855         rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
856         if (IS_ERR(rtc->rtc)) {
857                 ret = PTR_ERR(rtc->rtc);
858                 goto err;
859         }
860
861         rtc->rtc->ops = &omap_rtc_ops;
862         rtc->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
863         rtc->rtc->range_max = RTC_TIMESTAMP_END_2099;
864         omap_rtc_nvmem_config.priv = rtc;
865
866         /* handle periodic and alarm irqs */
867         ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0,
868                         dev_name(&rtc->rtc->dev), rtc);
869         if (ret)
870                 goto err;
871
872         if (rtc->irq_timer != rtc->irq_alarm) {
873                 ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0,
874                                 dev_name(&rtc->rtc->dev), rtc);
875                 if (ret)
876                         goto err;
877         }
878
879         /* Support ext_wakeup pinconf */
880         rtc_pinctrl_desc.name = dev_name(&pdev->dev);
881
882         rtc->pctldev = pinctrl_register(&rtc_pinctrl_desc, &pdev->dev, rtc);
883         if (IS_ERR(rtc->pctldev)) {
884                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
885                 ret = PTR_ERR(rtc->pctldev);
886                 goto err;
887         }
888
889         ret = rtc_register_device(rtc->rtc);
890         if (ret)
891                 goto err_deregister_pinctrl;
892
893         rtc_nvmem_register(rtc->rtc, &omap_rtc_nvmem_config);
894
895         if (rtc->is_pmic_controller) {
896                 if (!pm_power_off) {
897                         omap_rtc_power_off_rtc = rtc;
898                         pm_power_off = omap_rtc_power_off;
899                 }
900         }
901
902         return 0;
903
904 err_deregister_pinctrl:
905         pinctrl_unregister(rtc->pctldev);
906 err:
907         clk_disable_unprepare(rtc->clk);
908         device_init_wakeup(&pdev->dev, false);
909         rtc->type->lock(rtc);
910         pm_runtime_put_sync(&pdev->dev);
911         pm_runtime_disable(&pdev->dev);
912
913         return ret;
914 }
915
916 static int omap_rtc_remove(struct platform_device *pdev)
917 {
918         struct omap_rtc *rtc = platform_get_drvdata(pdev);
919         u8 reg;
920
921         if (pm_power_off == omap_rtc_power_off &&
922                         omap_rtc_power_off_rtc == rtc) {
923                 pm_power_off = NULL;
924                 omap_rtc_power_off_rtc = NULL;
925         }
926
927         device_init_wakeup(&pdev->dev, 0);
928
929         if (!IS_ERR(rtc->clk))
930                 clk_disable_unprepare(rtc->clk);
931
932         rtc->type->unlock(rtc);
933         /* leave rtc running, but disable irqs */
934         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
935
936         if (rtc->has_ext_clk) {
937                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
938                 reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC;
939                 rtc_write(rtc, OMAP_RTC_OSC_REG, reg);
940         }
941
942         rtc->type->lock(rtc);
943
944         /* Disable the clock/module */
945         pm_runtime_put_sync(&pdev->dev);
946         pm_runtime_disable(&pdev->dev);
947
948         /* Remove ext_wakeup pinconf */
949         pinctrl_unregister(rtc->pctldev);
950
951         return 0;
952 }
953
954 static int __maybe_unused omap_rtc_suspend(struct device *dev)
955 {
956         struct omap_rtc *rtc = dev_get_drvdata(dev);
957
958         rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
959
960         rtc->type->unlock(rtc);
961         /*
962          * FIXME: the RTC alarm is not currently acting as a wakeup event
963          * source on some platforms, and in fact this enable() call is just
964          * saving a flag that's never used...
965          */
966         if (device_may_wakeup(dev))
967                 enable_irq_wake(rtc->irq_alarm);
968         else
969                 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
970         rtc->type->lock(rtc);
971
972         rtc->is_suspending = true;
973
974         return 0;
975 }
976
977 static int __maybe_unused omap_rtc_resume(struct device *dev)
978 {
979         struct omap_rtc *rtc = dev_get_drvdata(dev);
980
981         rtc->type->unlock(rtc);
982         if (device_may_wakeup(dev))
983                 disable_irq_wake(rtc->irq_alarm);
984         else
985                 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg);
986         rtc->type->lock(rtc);
987
988         rtc->is_suspending = false;
989
990         return 0;
991 }
992
993 static int __maybe_unused omap_rtc_runtime_suspend(struct device *dev)
994 {
995         struct omap_rtc *rtc = dev_get_drvdata(dev);
996
997         if (rtc->is_suspending && !rtc->has_ext_clk)
998                 return -EBUSY;
999
1000         return 0;
1001 }
1002
1003 static const struct dev_pm_ops omap_rtc_pm_ops = {
1004         SET_SYSTEM_SLEEP_PM_OPS(omap_rtc_suspend, omap_rtc_resume)
1005         SET_RUNTIME_PM_OPS(omap_rtc_runtime_suspend, NULL, NULL)
1006 };
1007
1008 static void omap_rtc_shutdown(struct platform_device *pdev)
1009 {
1010         struct omap_rtc *rtc = platform_get_drvdata(pdev);
1011         u8 mask;
1012
1013         /*
1014          * Keep the ALARM interrupt enabled to allow the system to power up on
1015          * alarm events.
1016          */
1017         rtc->type->unlock(rtc);
1018         mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
1019         mask &= OMAP_RTC_INTERRUPTS_IT_ALARM;
1020         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask);
1021         rtc->type->lock(rtc);
1022 }
1023
1024 static struct platform_driver omap_rtc_driver = {
1025         .probe          = omap_rtc_probe,
1026         .remove         = omap_rtc_remove,
1027         .shutdown       = omap_rtc_shutdown,
1028         .driver         = {
1029                 .name   = "omap_rtc",
1030                 .pm     = &omap_rtc_pm_ops,
1031                 .of_match_table = omap_rtc_of_match,
1032         },
1033         .id_table       = omap_rtc_id_table,
1034 };
1035
1036 module_platform_driver(omap_rtc_driver);
1037
1038 MODULE_ALIAS("platform:omap_rtc");
1039 MODULE_AUTHOR("George G. Davis (and others)");
1040 MODULE_LICENSE("GPL");