drivers/rtc/rtc-lpc32xx.c

   1 /*
   2  * Copyright (C) 2010 NXP Semiconductors
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  *  You should have received a copy of the GNU General Public License along
  10  *  with this program; if not, write to the Free Software Foundation, Inc.,
  11  *  675 Mass Ave, Cambridge, MA 02139, USA.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/rtc.h>
  20 #include <linux/slab.h>
  21 #include <linux/io.h>
  22 #include <linux/of.h>
  23
  24 /*
  25  * Clock and Power control register offsets
  26  */
  27 #define LPC32XX_RTC_UCOUNT              0x00
  28 #define LPC32XX_RTC_DCOUNT              0x04
  29 #define LPC32XX_RTC_MATCH0              0x08
  30 #define LPC32XX_RTC_MATCH1              0x0C
  31 #define LPC32XX_RTC_CTRL                0x10
  32 #define LPC32XX_RTC_INTSTAT             0x14
  33 #define LPC32XX_RTC_KEY                 0x18
  34 #define LPC32XX_RTC_SRAM                0x80
  35
  36 #define LPC32XX_RTC_CTRL_MATCH0         (1 << 0)
  37 #define LPC32XX_RTC_CTRL_MATCH1         (1 << 1)
  38 #define LPC32XX_RTC_CTRL_ONSW_MATCH0    (1 << 2)
  39 #define LPC32XX_RTC_CTRL_ONSW_MATCH1    (1 << 3)
  40 #define LPC32XX_RTC_CTRL_SW_RESET       (1 << 4)
  41 #define LPC32XX_RTC_CTRL_CNTR_DIS       (1 << 6)
  42 #define LPC32XX_RTC_CTRL_ONSW_FORCE_HI  (1 << 7)
  43
  44 #define LPC32XX_RTC_INTSTAT_MATCH0      (1 << 0)
  45 #define LPC32XX_RTC_INTSTAT_MATCH1      (1 << 1)
  46 #define LPC32XX_RTC_INTSTAT_ONSW        (1 << 2)
  47
  48 #define LPC32XX_RTC_KEY_ONSW_LOADVAL    0xB5C13F27
  49
  50 #define rtc_readl(dev, reg) \
  51         __raw_readl((dev)->rtc_base + (reg))
  52 #define rtc_writel(dev, reg, val) \
  53         __raw_writel((val), (dev)->rtc_base + (reg))
  54
  55 struct lpc32xx_rtc {
  56         void __iomem *rtc_base;
  57         int irq;
  58         unsigned char alarm_enabled;
  59         struct rtc_device *rtc;
  60         spinlock_t lock;
  61 };
  62
  63 static int lpc32xx_rtc_read_time(struct device *dev, struct rtc_time *time)
  64 {
  65         unsigned long elapsed_sec;
  66         struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
  67
  68         elapsed_sec = rtc_readl(rtc, LPC32XX_RTC_UCOUNT);
  69         rtc_time_to_tm(elapsed_sec, time);
  70
  71         return 0;
  72 }
  73
  74 static int lpc32xx_rtc_set_mmss(struct device *dev, unsigned long secs)
  75 {
  76         struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
  77         u32 tmp;
  78
  79         spin_lock_irq(&rtc->lock);
  80
  81         /* RTC must be disabled during count update */
  82         tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
  83         rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp | LPC32XX_RTC_CTRL_CNTR_DIS);
  84         rtc_writel(rtc, LPC32XX_RTC_UCOUNT, secs);
  85         rtc_writel(rtc, LPC32XX_RTC_DCOUNT, 0xFFFFFFFF - secs);
  86         rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp &= ~LPC32XX_RTC_CTRL_CNTR_DIS);
  87
  88         spin_unlock_irq(&rtc->lock);
  89
  90         return 0;
  91 }
  92
  93 static int lpc32xx_rtc_read_alarm(struct device *dev,
  94         struct rtc_wkalrm *wkalrm)
  95 {
  96         struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
  97
  98         rtc_time_to_tm(rtc_readl(rtc, LPC32XX_RTC_MATCH0), &wkalrm->time);
  99         wkalrm->enabled = rtc->alarm_enabled;
 100         wkalrm->pending = !!(rtc_readl(rtc, LPC32XX_RTC_INTSTAT) &
 101                 LPC32XX_RTC_INTSTAT_MATCH0);
 102
 103         return rtc_valid_tm(&wkalrm->time);
 104 }
 105
 106 static int lpc32xx_rtc_set_alarm(struct device *dev,
 107         struct rtc_wkalrm *wkalrm)
 108 {
 109         struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
 110         unsigned long alarmsecs;
 111         u32 tmp;
 112         int ret;
 113
 114         ret = rtc_tm_to_time(&wkalrm->time, &alarmsecs);
 115         if (ret < 0) {
 116                 dev_warn(dev, "Failed to convert time: %d\n", ret);
 117                 return ret;
 118         }
 119
 120         spin_lock_irq(&rtc->lock);
 121
 122         /* Disable alarm during update */
 123         tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
 124         rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp & ~LPC32XX_RTC_CTRL_MATCH0);
 125
 126         rtc_writel(rtc, LPC32XX_RTC_MATCH0, alarmsecs);
 127
 128         rtc->alarm_enabled = wkalrm->enabled;
 129         if (wkalrm->enabled) {
 130                 rtc_writel(rtc, LPC32XX_RTC_INTSTAT,
 131                            LPC32XX_RTC_INTSTAT_MATCH0);
 132                 rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp |
 133                            LPC32XX_RTC_CTRL_MATCH0);
 134         }
 135
 136         spin_unlock_irq(&rtc->lock);
 137
 138         return 0;
 139 }
 140
 141 static int lpc32xx_rtc_alarm_irq_enable(struct device *dev,
 142         unsigned int enabled)
 143 {
 144         struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
 145         u32 tmp;
 146
 147         spin_lock_irq(&rtc->lock);
 148         tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
 149
 150         if (enabled) {
 151                 rtc->alarm_enabled = 1;
 152                 tmp |= LPC32XX_RTC_CTRL_MATCH0;
 153         } else {
 154                 rtc->alarm_enabled = 0;
 155                 tmp &= ~LPC32XX_RTC_CTRL_MATCH0;
 156         }
 157
 158         rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp);
 159         spin_unlock_irq(&rtc->lock);
 160
 161         return 0;
 162 }
 163
 164 static irqreturn_t lpc32xx_rtc_alarm_interrupt(int irq, void *dev)
 165 {
 166         struct lpc32xx_rtc *rtc = dev;
 167
 168         spin_lock(&rtc->lock);
 169
 170         /* Disable alarm interrupt */
 171         rtc_writel(rtc, LPC32XX_RTC_CTRL,
 172                 rtc_readl(rtc, LPC32XX_RTC_CTRL) &
 173                           ~LPC32XX_RTC_CTRL_MATCH0);
 174         rtc->alarm_enabled = 0;
 175
 176         /*
 177          * Write a large value to the match value so the RTC won't
 178          * keep firing the match status
 179          */
 180         rtc_writel(rtc, LPC32XX_RTC_MATCH0, 0xFFFFFFFF);
 181         rtc_writel(rtc, LPC32XX_RTC_INTSTAT, LPC32XX_RTC_INTSTAT_MATCH0);
 182
 183         spin_unlock(&rtc->lock);
 184
 185         rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_AF);
 186
 187         return IRQ_HANDLED;
 188 }
 189
 190 static const struct rtc_class_ops lpc32xx_rtc_ops = {
 191         .read_time              = lpc32xx_rtc_read_time,
 192         .set_mmss               = lpc32xx_rtc_set_mmss,
 193         .read_alarm             = lpc32xx_rtc_read_alarm,
 194         .set_alarm              = lpc32xx_rtc_set_alarm,
 195         .alarm_irq_enable       = lpc32xx_rtc_alarm_irq_enable,
 196 };
 197
 198 static int lpc32xx_rtc_probe(struct platform_device *pdev)
 199 {
 200         struct resource *res;
 201         struct lpc32xx_rtc *rtc;
 202         int rtcirq, err;
 203         u32 tmp;
 204
 205         rtcirq = platform_get_irq(pdev, 0);
 206         if (rtcirq < 0) {
 207                 dev_warn(&pdev->dev, "Can't get interrupt resource\n");
 208                 rtcirq = -1;
 209         }
 210
 211         rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
 212         if (unlikely(!rtc))
 213                 return -ENOMEM;
 214
 215         rtc->irq = rtcirq;
 216
 217         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 218         rtc->rtc_base = devm_ioremap_resource(&pdev->dev, res);
 219         if (IS_ERR(rtc->rtc_base))
 220                 return PTR_ERR(rtc->rtc_base);
 221
 222         spin_lock_init(&rtc->lock);
 223
 224         /*
 225          * The RTC is on a separate power domain and can keep it's state
 226          * across a chip power cycle. If the RTC has never been previously
 227          * setup, then set it up now for the first time.
 228          */
 229         tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
 230         if (rtc_readl(rtc, LPC32XX_RTC_KEY) != LPC32XX_RTC_KEY_ONSW_LOADVAL) {
 231                 tmp &= ~(LPC32XX_RTC_CTRL_SW_RESET |
 232                         LPC32XX_RTC_CTRL_CNTR_DIS |
 233                         LPC32XX_RTC_CTRL_MATCH0 |
 234                         LPC32XX_RTC_CTRL_MATCH1 |
 235                         LPC32XX_RTC_CTRL_ONSW_MATCH0 |
 236                         LPC32XX_RTC_CTRL_ONSW_MATCH1 |
 237                         LPC32XX_RTC_CTRL_ONSW_FORCE_HI);
 238                 rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp);
 239
 240                 /* Clear latched interrupt states */
 241                 rtc_writel(rtc, LPC32XX_RTC_MATCH0, 0xFFFFFFFF);
 242                 rtc_writel(rtc, LPC32XX_RTC_INTSTAT,
 243                            LPC32XX_RTC_INTSTAT_MATCH0 |
 244                            LPC32XX_RTC_INTSTAT_MATCH1 |
 245                            LPC32XX_RTC_INTSTAT_ONSW);
 246
 247                 /* Write key value to RTC so it won't reload on reset */
 248                 rtc_writel(rtc, LPC32XX_RTC_KEY,
 249                            LPC32XX_RTC_KEY_ONSW_LOADVAL);
 250         } else {
 251                 rtc_writel(rtc, LPC32XX_RTC_CTRL,
 252                            tmp & ~LPC32XX_RTC_CTRL_MATCH0);
 253         }
 254
 255         platform_set_drvdata(pdev, rtc);
 256
 257         rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
 258         if (IS_ERR(rtc->rtc))
 259                 return PTR_ERR(rtc->rtc);
 260
 261         rtc->rtc->ops = &lpc32xx_rtc_ops;
 262         rtc->rtc->range_max = U32_MAX;
 263
 264         err = rtc_register_device(rtc->rtc);
 265         if (err)
 266                 return err;
 267
 268         /*
 269          * IRQ is enabled after device registration in case alarm IRQ
 270          * is pending upon suspend exit.
 271          */
 272         if (rtc->irq >= 0) {
 273                 if (devm_request_irq(&pdev->dev, rtc->irq,
 274                                      lpc32xx_rtc_alarm_interrupt,
 275                                      0, pdev->name, rtc) < 0) {
 276                         dev_warn(&pdev->dev, "Can't request interrupt.\n");
 277                         rtc->irq = -1;
 278                 } else {
 279                         device_init_wakeup(&pdev->dev, 1);
 280                 }
 281         }
 282
 283         return 0;
 284 }
 285
 286 static int lpc32xx_rtc_remove(struct platform_device *pdev)
 287 {
 288         struct lpc32xx_rtc *rtc = platform_get_drvdata(pdev);
 289
 290         if (rtc->irq >= 0)
 291                 device_init_wakeup(&pdev->dev, 0);
 292
 293         return 0;
 294 }
 295
 296 #ifdef CONFIG_PM
 297 static int lpc32xx_rtc_suspend(struct device *dev)
 298 {
 299         struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
 300
 301         if (rtc->irq >= 0) {
 302                 if (device_may_wakeup(dev))
 303                         enable_irq_wake(rtc->irq);
 304                 else
 305                         disable_irq_wake(rtc->irq);
 306         }
 307
 308         return 0;
 309 }
 310
 311 static int lpc32xx_rtc_resume(struct device *dev)
 312 {
 313         struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
 314
 315         if (rtc->irq >= 0 && device_may_wakeup(dev))
 316                 disable_irq_wake(rtc->irq);
 317
 318         return 0;
 319 }
 320
 321 /* Unconditionally disable the alarm */
 322 static int lpc32xx_rtc_freeze(struct device *dev)
 323 {
 324         struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
 325
 326         spin_lock_irq(&rtc->lock);
 327
 328         rtc_writel(rtc, LPC32XX_RTC_CTRL,
 329                 rtc_readl(rtc, LPC32XX_RTC_CTRL) &
 330                           ~LPC32XX_RTC_CTRL_MATCH0);
 331
 332         spin_unlock_irq(&rtc->lock);
 333
 334         return 0;
 335 }
 336
 337 static int lpc32xx_rtc_thaw(struct device *dev)
 338 {
 339         struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
 340
 341         if (rtc->alarm_enabled) {
 342                 spin_lock_irq(&rtc->lock);
 343
 344                 rtc_writel(rtc, LPC32XX_RTC_CTRL,
 345                            rtc_readl(rtc, LPC32XX_RTC_CTRL) |
 346                            LPC32XX_RTC_CTRL_MATCH0);
 347
 348                 spin_unlock_irq(&rtc->lock);
 349         }
 350
 351         return 0;
 352 }
 353
 354 static const struct dev_pm_ops lpc32xx_rtc_pm_ops = {
 355         .suspend = lpc32xx_rtc_suspend,
 356         .resume = lpc32xx_rtc_resume,
 357         .freeze = lpc32xx_rtc_freeze,
 358         .thaw = lpc32xx_rtc_thaw,
 359         .restore = lpc32xx_rtc_resume
 360 };
 361
 362 #define LPC32XX_RTC_PM_OPS (&lpc32xx_rtc_pm_ops)
 363 #else
 364 #define LPC32XX_RTC_PM_OPS NULL
 365 #endif
 366
 367 #ifdef CONFIG_OF
 368 static const struct of_device_id lpc32xx_rtc_match[] = {
 369         { .compatible = "nxp,lpc3220-rtc" },
 370         { }
 371 };
 372 MODULE_DEVICE_TABLE(of, lpc32xx_rtc_match);
 373 #endif
 374
 375 static struct platform_driver lpc32xx_rtc_driver = {
 376         .probe          = lpc32xx_rtc_probe,
 377         .remove         = lpc32xx_rtc_remove,
 378         .driver = {
 379                 .name   = "rtc-lpc32xx",
 380                 .pm     = LPC32XX_RTC_PM_OPS,
 381                 .of_match_table = of_match_ptr(lpc32xx_rtc_match),
 382         },
 383 };
 384
 385 module_platform_driver(lpc32xx_rtc_driver);
 386
 387 MODULE_AUTHOR("Kevin Wells <wellsk40@gmail.com");
 388 MODULE_DESCRIPTION("RTC driver for the LPC32xx SoC");
 389 MODULE_LICENSE("GPL");
 390 MODULE_ALIAS("platform:rtc-lpc32xx");