drivers/rtc/rtc-jz4740.c

   1 /*
   2  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
   3  *  Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
   4  *       JZ4740 SoC RTC driver
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under  the terms of  the GNU General Public License as published by the
   8  *  Free Software Foundation;  either version 2 of the License, or (at your
   9  *  option) any later version.
  10  *
  11  *  You should have received a copy of the GNU General Public License along
  12  *  with this program; if not, write to the Free Software Foundation, Inc.,
  13  *  675 Mass Ave, Cambridge, MA 02139, USA.
  14  *
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/io.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/of_device.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_wakeirq.h>
  24 #include <linux/reboot.h>
  25 #include <linux/rtc.h>
  26 #include <linux/slab.h>
  27 #include <linux/spinlock.h>
  28
  29 #define JZ_REG_RTC_CTRL         0x00
  30 #define JZ_REG_RTC_SEC          0x04
  31 #define JZ_REG_RTC_SEC_ALARM    0x08
  32 #define JZ_REG_RTC_REGULATOR    0x0C
  33 #define JZ_REG_RTC_HIBERNATE    0x20
  34 #define JZ_REG_RTC_WAKEUP_FILTER        0x24
  35 #define JZ_REG_RTC_RESET_COUNTER        0x28
  36 #define JZ_REG_RTC_SCRATCHPAD   0x34
  37
  38 /* The following are present on the jz4780 */
  39 #define JZ_REG_RTC_WENR 0x3C
  40 #define JZ_RTC_WENR_WEN BIT(31)
  41
  42 #define JZ_RTC_CTRL_WRDY        BIT(7)
  43 #define JZ_RTC_CTRL_1HZ         BIT(6)
  44 #define JZ_RTC_CTRL_1HZ_IRQ     BIT(5)
  45 #define JZ_RTC_CTRL_AF          BIT(4)
  46 #define JZ_RTC_CTRL_AF_IRQ      BIT(3)
  47 #define JZ_RTC_CTRL_AE          BIT(2)
  48 #define JZ_RTC_CTRL_ENABLE      BIT(0)
  49
  50 /* Magic value to enable writes on jz4780 */
  51 #define JZ_RTC_WENR_MAGIC       0xA55A
  52
  53 #define JZ_RTC_WAKEUP_FILTER_MASK       0x0000FFE0
  54 #define JZ_RTC_RESET_COUNTER_MASK       0x00000FE0
  55
  56 enum jz4740_rtc_type {
  57         ID_JZ4740,
  58         ID_JZ4780,
  59 };
  60
  61 struct jz4740_rtc {
  62         void __iomem *base;
  63         enum jz4740_rtc_type type;
  64
  65         struct rtc_device *rtc;
  66         struct clk *clk;
  67
  68         int irq;
  69
  70         spinlock_t lock;
  71
  72         unsigned int min_wakeup_pin_assert_time;
  73         unsigned int reset_pin_assert_time;
  74 };
  75
  76 static struct device *dev_for_power_off;
  77
  78 static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
  79 {
  80         return readl(rtc->base + reg);
  81 }
  82
  83 static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
  84 {
  85         uint32_t ctrl;
  86         int timeout = 10000;
  87
  88         do {
  89                 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
  90         } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
  91
  92         return timeout ? 0 : -EIO;
  93 }
  94
  95 static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc)
  96 {
  97         uint32_t ctrl;
  98         int ret, timeout = 10000;
  99
 100         ret = jz4740_rtc_wait_write_ready(rtc);
 101         if (ret != 0)
 102                 return ret;
 103
 104         writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);
 105
 106         do {
 107                 ctrl = readl(rtc->base + JZ_REG_RTC_WENR);
 108         } while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout);
 109
 110         return timeout ? 0 : -EIO;
 111 }
 112
 113 static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
 114         uint32_t val)
 115 {
 116         int ret = 0;
 117
 118         if (rtc->type >= ID_JZ4780)
 119                 ret = jz4780_rtc_enable_write(rtc);
 120         if (ret == 0)
 121                 ret = jz4740_rtc_wait_write_ready(rtc);
 122         if (ret == 0)
 123                 writel(val, rtc->base + reg);
 124
 125         return ret;
 126 }
 127
 128 static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
 129         bool set)
 130 {
 131         int ret;
 132         unsigned long flags;
 133         uint32_t ctrl;
 134
 135         spin_lock_irqsave(&rtc->lock, flags);
 136
 137         ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 138
 139         /* Don't clear interrupt flags by accident */
 140         ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
 141
 142         if (set)
 143                 ctrl |= mask;
 144         else
 145                 ctrl &= ~mask;
 146
 147         ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
 148
 149         spin_unlock_irqrestore(&rtc->lock, flags);
 150
 151         return ret;
 152 }
 153
 154 static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
 155 {
 156         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 157         uint32_t secs, secs2;
 158         int timeout = 5;
 159
 160         if (jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD) != 0x12345678)
 161                 return -EINVAL;
 162
 163         /* If the seconds register is read while it is updated, it can contain a
 164          * bogus value. This can be avoided by making sure that two consecutive
 165          * reads have the same value.
 166          */
 167         secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 168         secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 169
 170         while (secs != secs2 && --timeout) {
 171                 secs = secs2;
 172                 secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 173         }
 174
 175         if (timeout == 0)
 176                 return -EIO;
 177
 178         rtc_time64_to_tm(secs, time);
 179
 180         return 0;
 181 }
 182
 183 static int jz4740_rtc_set_time(struct device *dev, struct rtc_time *time)
 184 {
 185         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 186         int ret;
 187
 188         ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, rtc_tm_to_time64(time));
 189         if (ret)
 190                 return ret;
 191
 192         return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
 193 }
 194
 195 static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 196 {
 197         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 198         uint32_t secs;
 199         uint32_t ctrl;
 200
 201         secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
 202
 203         ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 204
 205         alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
 206         alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
 207
 208         rtc_time64_to_tm(secs, &alrm->time);
 209
 210         return 0;
 211 }
 212
 213 static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 214 {
 215         int ret;
 216         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 217         uint32_t secs = lower_32_bits(rtc_tm_to_time64(&alrm->time));
 218
 219         ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
 220         if (!ret)
 221                 ret = jz4740_rtc_ctrl_set_bits(rtc,
 222                         JZ_RTC_CTRL_AE | JZ_RTC_CTRL_AF_IRQ, alrm->enabled);
 223
 224         return ret;
 225 }
 226
 227 static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
 228 {
 229         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 230         return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
 231 }
 232
 233 static const struct rtc_class_ops jz4740_rtc_ops = {
 234         .read_time      = jz4740_rtc_read_time,
 235         .set_time       = jz4740_rtc_set_time,
 236         .read_alarm     = jz4740_rtc_read_alarm,
 237         .set_alarm      = jz4740_rtc_set_alarm,
 238         .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
 239 };
 240
 241 static irqreturn_t jz4740_rtc_irq(int irq, void *data)
 242 {
 243         struct jz4740_rtc *rtc = data;
 244         uint32_t ctrl;
 245         unsigned long events = 0;
 246
 247         ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 248
 249         if (ctrl & JZ_RTC_CTRL_1HZ)
 250                 events |= (RTC_UF | RTC_IRQF);
 251
 252         if (ctrl & JZ_RTC_CTRL_AF)
 253                 events |= (RTC_AF | RTC_IRQF);
 254
 255         rtc_update_irq(rtc->rtc, 1, events);
 256
 257         jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);
 258
 259         return IRQ_HANDLED;
 260 }
 261
 262 static void jz4740_rtc_poweroff(struct device *dev)
 263 {
 264         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 265         jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
 266 }
 267
 268 static void jz4740_rtc_power_off(void)
 269 {
 270         struct jz4740_rtc *rtc = dev_get_drvdata(dev_for_power_off);
 271         unsigned long rtc_rate;
 272         unsigned long wakeup_filter_ticks;
 273         unsigned long reset_counter_ticks;
 274
 275         clk_prepare_enable(rtc->clk);
 276
 277         rtc_rate = clk_get_rate(rtc->clk);
 278
 279         /*
 280          * Set minimum wakeup pin assertion time: 100 ms.
 281          * Range is 0 to 2 sec if RTC is clocked at 32 kHz.
 282          */
 283         wakeup_filter_ticks =
 284                 (rtc->min_wakeup_pin_assert_time * rtc_rate) / 1000;
 285         if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
 286                 wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
 287         else
 288                 wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
 289         jz4740_rtc_reg_write(rtc,
 290                              JZ_REG_RTC_WAKEUP_FILTER, wakeup_filter_ticks);
 291
 292         /*
 293          * Set reset pin low-level assertion time after wakeup: 60 ms.
 294          * Range is 0 to 125 ms if RTC is clocked at 32 kHz.
 295          */
 296         reset_counter_ticks = (rtc->reset_pin_assert_time * rtc_rate) / 1000;
 297         if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK)
 298                 reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK;
 299         else
 300                 reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK;
 301         jz4740_rtc_reg_write(rtc,
 302                              JZ_REG_RTC_RESET_COUNTER, reset_counter_ticks);
 303
 304         jz4740_rtc_poweroff(dev_for_power_off);
 305         kernel_halt();
 306 }
 307
 308 static const struct of_device_id jz4740_rtc_of_match[] = {
 309         { .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
 310         { .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
 311         {},
 312 };
 313 MODULE_DEVICE_TABLE(of, jz4740_rtc_of_match);
 314
 315 static int jz4740_rtc_probe(struct platform_device *pdev)
 316 {
 317         int ret;
 318         struct jz4740_rtc *rtc;
 319         struct resource *mem;
 320         const struct platform_device_id *id = platform_get_device_id(pdev);
 321         const struct of_device_id *of_id = of_match_device(
 322                         jz4740_rtc_of_match, &pdev->dev);
 323         struct device_node *np = pdev->dev.of_node;
 324
 325         rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
 326         if (!rtc)
 327                 return -ENOMEM;
 328
 329         if (of_id)
 330                 rtc->type = (enum jz4740_rtc_type)of_id->data;
 331         else
 332                 rtc->type = id->driver_data;
 333
 334         rtc->irq = platform_get_irq(pdev, 0);
 335         if (rtc->irq < 0) {
 336                 dev_err(&pdev->dev, "Failed to get platform irq\n");
 337                 return -ENOENT;
 338         }
 339
 340         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 341         rtc->base = devm_ioremap_resource(&pdev->dev, mem);
 342         if (IS_ERR(rtc->base))
 343                 return PTR_ERR(rtc->base);
 344
 345         rtc->clk = devm_clk_get(&pdev->dev, "rtc");
 346         if (IS_ERR(rtc->clk)) {
 347                 dev_err(&pdev->dev, "Failed to get RTC clock\n");
 348                 return PTR_ERR(rtc->clk);
 349         }
 350
 351         spin_lock_init(&rtc->lock);
 352
 353         platform_set_drvdata(pdev, rtc);
 354
 355         device_init_wakeup(&pdev->dev, 1);
 356
 357         ret = dev_pm_set_wake_irq(&pdev->dev, rtc->irq);
 358         if (ret) {
 359                 dev_err(&pdev->dev, "Failed to set wake irq: %d\n", ret);
 360                 return ret;
 361         }
 362
 363         rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
 364         if (IS_ERR(rtc->rtc)) {
 365                 ret = PTR_ERR(rtc->rtc);
 366                 dev_err(&pdev->dev, "Failed to allocate rtc device: %d\n", ret);
 367                 return ret;
 368         }
 369
 370         rtc->rtc->ops = &jz4740_rtc_ops;
 371         rtc->rtc->range_max = U32_MAX;
 372
 373         ret = rtc_register_device(rtc->rtc);
 374         if (ret) {
 375                 dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
 376                 return ret;
 377         }
 378
 379         ret = devm_request_irq(&pdev->dev, rtc->irq, jz4740_rtc_irq, 0,
 380                                 pdev->name, rtc);
 381         if (ret) {
 382                 dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
 383                 return ret;
 384         }
 385
 386         if (np && of_device_is_system_power_controller(np)) {
 387                 if (!pm_power_off) {
 388                         /* Default: 60ms */
 389                         rtc->reset_pin_assert_time = 60;
 390                         of_property_read_u32(np, "reset-pin-assert-time-ms",
 391                                              &rtc->reset_pin_assert_time);
 392
 393                         /* Default: 100ms */
 394                         rtc->min_wakeup_pin_assert_time = 100;
 395                         of_property_read_u32(np,
 396                                              "min-wakeup-pin-assert-time-ms",
 397                                              &rtc->min_wakeup_pin_assert_time);
 398
 399                         dev_for_power_off = &pdev->dev;
 400                         pm_power_off = jz4740_rtc_power_off;
 401                 } else {
 402                         dev_warn(&pdev->dev,
 403                                  "Poweroff handler already present!\n");
 404                 }
 405         }
 406
 407         return 0;
 408 }
 409
 410 static const struct platform_device_id jz4740_rtc_ids[] = {
 411         { "jz4740-rtc", ID_JZ4740 },
 412         { "jz4780-rtc", ID_JZ4780 },
 413         {}
 414 };
 415 MODULE_DEVICE_TABLE(platform, jz4740_rtc_ids);
 416
 417 static struct platform_driver jz4740_rtc_driver = {
 418         .probe   = jz4740_rtc_probe,
 419         .driver  = {
 420                 .name  = "jz4740-rtc",
 421                 .of_match_table = of_match_ptr(jz4740_rtc_of_match),
 422         },
 423         .id_table = jz4740_rtc_ids,
 424 };
 425
 426 module_platform_driver(jz4740_rtc_driver);
 427
 428 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 429 MODULE_LICENSE("GPL");
 430 MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
 431 MODULE_ALIAS("platform:jz4740-rtc");